# Virtual Space Vector Pulse Width Modulation for AsymmetricT-Type Neutral Point Clamped 3-Level Inverter

Authors: Nam Xuan Doan; Nho Van Nguyen
Journal: Mathematical Problems in Engineering
 (2021)

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## Abstract

This paper proposes a novel 3-phase asymmetric 3-levelT-type NPC inverter and studies its PWM performance using a virtual space vector pulse width modulation control strategy. Firstly, the mathematical model and characteristics of this economical topology are described. Then, a virtual space vector approach is proposed to build a space vector diagram for designing SVPWM control. Similar to the conventional 3-level NPC inverter, the asymmetric inverter can also work with the neutral point voltage self-balancing in a fundamental period, which enables employment of this topology in various applications. Finally, simulation and experiment results under different load conditions have shown good output performance of the asymmetric 3-level topology. Similar tests are also performed on both conventional 2-level and 3-level inverters for comparison. For an almost similar number of different voltage vectors in the space vector diagram, the asymmetric 3-level topology can compete with conventional 3-level inverters for low-cost applications. The obvious benefit of the asymmetric 3-level inverter is a smaller number of switches devices while it can achieve output performance similar to that of the conventional 3-level. The comparative investigation also shows that the total loss given by SVPWM for the asymmetric 3-level configuration is lower than that of the traditional 3-level inverter.


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## Body

## 1. Introduction

Three-level converters have been widely used in industrial applications, which includes high-power motor drivers [1], grid connection for renewable energy systems [2, 9], and electric vehicles [3]. In particular, in high-power and medium-voltage applications, it has outstanding advantages compared with 2-level converters, such as better total harmonic distortion (THD), lower switching losses, and reduced voltage stress dv/dt across the power devices [4–6]. These most common topologies are neutral point clamped (NPC), flying capacitor (FC), and cascaded H-bridge (CHB) types. In fact, NPC converters are being widely used. Among them, the T-type NPC was shown to be more efficient than the traditional NPC up to the medium switching frequency range [7–13]. This topology does not use clamping diodes, and the number of power switches is the same as the NPC converters.For overall good performances in relation to loss distribution, high efficiency compared with conventional 3L-NPC,T-type NPC legs have been commercialized by many manufacturers such as Semikron, Infineon, Mitsubishi, and Fuji [14, 15]. Many modified T-NPC structures have been introduced to satisfy different purposes. For example, an advanced T-NPC (AT-NPC) structure using a reverse blocking IGBT (RB-IGBT) instead of two conventional IGBTs at the T-leg connected to the neutral point has been studied [16–18]. This structure reduces the conduction voltage drop and related device loss when the neutral point is connected to outputs. Another topology named combined AT-NPC and quasi-Z source impedance converter presents an attractive and economic solution for renewable energy applications with low DC input voltage [19]. Recently, numerous research studies on utilizing wide band gap devices for T-type converters also draw much intention from researchers [20, 21]. One of the major trends in modern power converters is to design higher multilevel converters for high-power and high-voltage applications. Because there are no topologies from NPC, FLC and cascaded inverters can meet various demands in practice and many hybrid multilevel topologies were designed and shown as good solutions for industry. For this aim, several five-level hybrid T-type NPC inverters were presented in the recent literature [22–25].Although 3-level NPC inverters have many advantages compared with 2-level inverters, as mentioned above, they have some disadvantages, such as an increased system volume, higher cost, and reduced reliability due to more switches. Many recent studies focus on developing reduced switched topologies [26–32] to improve system reliability, reducing size and cost. In [26–29], the diode NPC 3-level 2-leg topology was proposed in which the required number of switches is reduced from 12 IGBTs and 6 diodes to 8 IGBTs and 4 diodes. A similar structure for the T-type has been proposed to eliminate the diodes [32]. These topologies only need two legs for a three-phase 3-level inverter, so the number of components is reduced by one-third, as shown in Figure 1(a). However, a drawback is that the linear output voltage is limited to half, as shown in Figure 1(b).Figure 1
Structure of the two legsT-type 3-level inverter: (a) the topology of the two legs T-type 3-level inverter; (b) space vector diagram of the two legs T-type 3-level inverter.
(a)(b)This paper proposes a so-called asymmetric 3-levelT-type NPC inverter by adding a half-bridge leg to the 2-leg 3-level NPC inverter. This new configuration, as shown in Figure 2, enables twice the output voltage range compared with Figure 1. In order to evaluate and compare the PWM performance of the novel topology with conventional 2-level and 3-level inverters, virtual space vectors and the related virtual space vector pulse width modulation (VSVPWM) control will be proposed and designed. Simulations and experiments are performed to demonstrate the effectiveness and feasibility of the asymmetric T-type NPC 3-level inverter.Figure 2
Structure of the asymmetric inverter.


## 2. Circuit Analysis and Mathematical Model

The asymmetric inverter topology is illustrated in Figure2. The phase leg B is a half-bridge; phases A and C are 3-level T-type legs. The DC-bus voltage is supplied via two DC-link capacitors c1,c2 in series. Three-phase load R-L is connected to the output terminals of the converter.Under the condition of balanced DC-link capacitor voltages, the voltage from the output terminal to the negative of the DC-bus can be expressed as follows:(1)vXN=SXVdc2,where X∈A,B,C and SX is the switching state and defined in terms of the IGBT states per phase legs. For 3-level leg phases A and C, SX can be 0, 1, and 2. For 2-level leg phase B, SX can be 0, 2. The switching states of the three phases A, B, and C are described in Table 1.Table 1
Switching states and output voltages of the asymmetric inverter.
For phaseX with X∈A,CFor phaseBSwitching stateDevice stateOutput voltageSwitching stateDevice stateOutput voltageSXSX1SX2SX3SX4vXNSBSB1SB2vBN21100Vdc210Vdc101101/2Vdc————0001100010The Clarke formula transforms the voltage vector in theabc to αβcoordinate system as follows:(2)V⟶k=23vAN+ej2π/3vBN+ej4π/3vCN,where V⟶k is the output voltage vector of the inverter in the αβ coordinate system and k is denoted as the vector index.The converter generates 18 voltage vectors, including 2 redundant zero voltage vectors (ZV), 6 small voltage vectors (SV), 4 medium-voltage vectors (MV), and 6 large voltage vectors (LV) illustrated in Figure3. Compared with 7 and 19 difference vectors used in 2-level and 3-level NPC inverters, respectively, the number of difference vectors in the asymmetric NPC is 17, nearly identical to the NPC. So, it is expected that the performance of the asymmetric PWM control will be as good as the 3-level NPC inverter.Figure 3
Space vector diagram of asymmetricT-type 3-level NPC inverter.Form (1), the line voltage between two terminal legs is rewritten and deduced as follows:(3)vAB=vAN−vBN=12VdcSA−SB,vBC=vBN−vCN=12VdcSB−SC,vCA=vCN−vAN=12VdcSC−SA.With the switching stateSX as defined in Table 1, applying the above analysis for the 2-level and 3-level conventional converters, the specific characteristics of each type are compared with the asymmetric configuration reported in Table 2. The asymmetric converter generates line voltages at 5 voltage levels ±Vdc, ±1/2Vdc, and 0, similar to traditional 3-level converters.Table 2
Comparing typical properties of inverters.
Characteristic2-levelAsymmetric 3-level3-levelStructure+ Symmetric + using 6 IGBTs+ Asymmetric + using 10 IGBTs+ Symmetric + using 12 IGBTsSwitching states81827Different voltage vectors71719Line-voltage levels±Vdc;0±Vdc;±1/2Vdc;0±Vdc;±1/2Vdc;0


## 3. Virtual SVPWM for Asymmetric Inverter

The reference voltage vectorV⟶ref can be synthesized in relation with the switching states SX on the phase legs, with X∈A,B,C, as follows:(4)V⟶ref=SA+SBej2π/3+SCej4π/3Vdc3.We defineV1max as the maximum amplitude of the reference vector in the linear modulation range, corresponding to the radius of the largest circle inscribed in the hexagon. The modulation index is defined as follows:(5)ma=V1maxVdc/3.It can be seen that the maximum amplitude ofV1max=Vdc/3, and asymmetric 3-level achieves the same maximum voltage as traditional symmetric configurations.The space vector diagram of the asymmetric inverter in Figure3 lacks two medium-voltage vectors, V⟶210 and V⟶012, in sectors I and IV, respectively. To apply the SVPWM technique of the traditional 3-level into asymmetric topology, two virtual vectors are proposed and added to the space vector diagram as illustrated in Figure 4, defined as follows:(6)V⟶210vir=12V⟶200+12V⟶220,V⟶012vir=12V⟶002+12V⟶022.Figure 4
Virtual space vector diagram.


### 3.1. Identify Region of Sectors

As in Figure4, each sector is divided into 4 regions numbered 1 to 4. The SVPWM technique for V⟶ref will be solved for sector I, and these results will be properly deduced for other sectors.The reference voltage vector synthesized by the three nearest voltage vectors, which are determined through the region where the reference vector is located, is as follows [33]:(7)d1=masinπ3−θI,d2=masinθI.The region identification is related tod1 and d2 as follows:Ifd1+d2≤0.5, then region 1Ifd1>0.5, then region 3Id2>0.5, then region 4Else region 2The remaining sectors will be converted to sector I. Therefore, the reference vector will be calibrated so that the modified angleθI falls between 0 and π/3, that is,(8)θI=θk−k−1π3,where k = 2, …, 6 for sectors II, …, VI, respectively.


### 3.2. Duty Cycle Calculation

The duty cycle for the voltage vector at the vertices of the triangle where the reference vector is placed essentially represents the dwell time of the selected switching states during the sampling intervalTs. For example, the reference vector in region 3 of sector I, as shown in Figure 5, is synthesized by voltage vectors V⟶100, V⟶210vir, and V⟶200 over a sampling period, defined by the following.(9)daV⟶100+dbV⟶210vir+dcV⟶200=V⟶ref,da+db+dc=1,where da, db, and dc are the duty ratios for the vectors V⟶100, V⟶210vir, and V⟶200, respectively.Figure 5
V⟶ref is located in region 3 of sector I.Substituting the values of the voltage vectors into (9) and separating the real and imaginary parts give(10)13Vdc12Vdc23Vdc0123Vdc0111dadbdc=VrcosθIVrsinθI1.Solving (10), the results are as follows:(11)dadbdc=2−2d1+d22d22d1−1,where d1 and d2 are defined as in (7).Calculating similarly for the remaining regions, the relationship between theV⟶ref location and duty factors is summarized in Table 3.Table 3
Duty ratio calculation in conventional 3-level NPC.
V⟶ref locationDuty ratiodadbdc12d11–2(d1 + d2)2d221−2d22(d1 + d2) – 11−2d132–2(d1 + d2)2d22d1−142d2−12d12–2(d1 + d2)In regions 2, 3, and 4 of sectors I and IV, the reference voltage vector is synthesized with the participation of the virtual vector. For example,V⟶ref in region 3 of sector I is synthesized by 3 voltage vectors V⟶100, V⟶200, and V⟶210vir with duty coefficients da, dc, and db, respectively, in which V⟶210vir is performed by V⟶200 and V⟶220, as defined in (6), with duty db/2 for each. The duty factors for available vectors V⟶100, V⟶220, and V⟶200 are adjusted to da, db/2, and db/2+dc, rewritten as 2−2d1+d2, d2, and 2d1+d2−1, respectively. All the adjusted duty coefficients of the voltage vectors of sectors I and IV are detailed in Table 4.Table 4
Adjusted duty ratio for voltage vectors in sectors I and IV.
RegionVoltage vectorAdjusted duty ratioSector ISector IV2V⟶100V⟶1221−2d2V⟶200V⟶022d1+d2−0.5V⟶220V⟶002d1+d2−0.5V⟶221V⟶0011−2d13V⟶100V⟶1222–2(d1 + d2)V⟶200V⟶0222d1+d2−1V⟶220V⟶002d24V⟶200V⟶022d1V⟶220V⟶002d1+2d2−1V⟶221V⟶0012–2(d1 + d2)


### 3.3. Switching Sequence

After calculating the duty for the selected voltage vectors to synthesize into the reference vector, the next step is to arrange the switching sequence. In this section, the switching sequence forV⟶ref is designed to minimize the switching frequency according to required criteria is as follows. ➀ The transition between switching states involves only two switches in the same phase leg. It is satisfied if there is no switching from state 0 to state 2 or vice versa in phase leg A and C. ➁ When the reference vector V⟶ref moves from one sector (or region) to the next, the transition requires no or a minimum number of switching. ➂ The switching sequence is arranged in a half-wave symmetrical pattern to eliminate even-order harmonics on the output line voltages.For example,V⟶ref is located in region 2 of sector I. A typical seven-segment switching sequence and output line-voltage waveforms are presented in Figure 6(a). It can be seen that requirement ➀ is satisfied. The starting and ending point is state 100, so the switching sequence in the remaining regions of sector I must also start from state 100 or 200 to satisfy requirement ➁. For the requirement ➂ to be also satisfied, then region 2 of sector IV must be arranged in the opposite order of sector I, as shown in Figure 6(b).Figure 6
Switching sequence for region 2: (a) sector I; (b) sector IV.
(a)(b)The typical switching sequence for the asymmetricT-type NPC inverter is shown in Figure 7.Figure 7
Switching sequence for asymmetricT-type NPC inverter.


### 3.4. The Self-Balancing Mechanism

The relation between the DC-link capacitor voltagesVc1,Vc2 and DC-link capacitor currents ic1,ic1 is provided as follows [34–38]:(12)Vc1=Vc1o+1C∫otic1dt,Vc2=Vc2o+1C∫otic2dt,where Vc1o and Vc2o are the initial values of c1 and c2 capacitors and supposing their capacitance C1=C2=C.Kirchhoff’s current law is applied at the neutral point as follows:(13)iNP=ic1−ic2.AssumingVc1o=Vc2o, the difference between Vc1 and Vc2 voltages per fundamental cycle is calculated as follows:(14)ΔVc=Vc1−Vc2=1C∫o2πiNPdt.When a zero or large vector is applied, as shown in Figures8(a)and 8(d), the difference voltage ΔVc is not affected because of iNP=0. In contrast, small and medium vectors can contribute to the variation of ΔVc, as shown in Figures 8(b) and 8(c), in which the polarity and magnitude of ΔVc are determined by the load current generated by the switching state.Figure 8
The effect of switching vectors on dc-link capacitors: (a) ZV; (b) SV; (c) MV; (d) LV.
(a)(b)(c)(d)For the selected switching sequence, as in Figure7, the voltage difference ΔVc generated by the switching states at the low modulation index ma≤0.5 in one fundamental period is presented in Figure 9. For example, when the reference vector moves in region 1 of sector I, the switching states 100, 221, and 222 are applied to synthesize the reference vector. The voltage difference caused by the switching states is calculated as follows:(15)ΔVcI=1C∫0ta/2iAdt+∫ta/2ta/2+tc/2iCdt+∫ta/2+tc/2+tbta/2+tc+tbiCdt+∫ta/2+tc+tbπ/3iAdt=ΔVcI①+ΔVcI②+ΔVcI③+ΔVcI④.Figure 9
The difference voltage generated by the switching states atma≤0.5.Similarly for region 1 of sector IV,(16)ΔVcIV=1C∫ππ+ta/2iAdt+∫π+ta/2π+ta/2+tc/2iCdt+∫π+ta/2+tc/2+tbπ+ta/2+tc+tbiCdt+∫π+ta/2+tc+tb4π/3iAdt=ΔVcIV①+ΔVcIV②+ΔVcIV③+ΔVcIV④.The general equation of the load currents is as follows:(17)iA=IAmsinωt+φA,iB=IBmsinωt−2π3+φB,iC=ICmsinωt+2π3+φC,where IXm is the max amplitude of the phase load current and φX is the load power factor angle; X∈A,B,C.Substitute (17) into (15) and (16), the definite integrals ΔVcI① and ΔVcIV② are calculated as follows:(18)VcI①=IAmωCcosφA−cosωta2+φA,VcIV①=IAmωC−cosφA+cosωta2+φA.Expression (18) and Figure 9 show that when applying the switching state 100, it causes a capacitor imbalance, by the red area marked ➀ in sector I. Meanwhile, the switching state 122 in sector IV makes the capacitor unbalanced by an amount equal to that caused by switching state 100 but a different sign (area marker ➀ in sector IV). Similarly, with the remaining definite integrals, we have(19)In one fundamental cycle, the switching state in the first half causes an imbalance. However, it quickly returns to balance in the next half-cycle by switching states on the opposite side, which have the same neutral current characteristics but a different sign, so(20)ΔVcI+ΔVcIV︸0+ΔVcII+ΔVcV︸0+ΔVcIII+ΔVcVI︸0=0,where ΔVci is the difference voltage caused by the switching states in sector i; i∈I, II, III, IV, V, VI.The self-balancing mechanism for the high modulation indexma>0.5 also occurs similarly, as presented in Figure 10.Figure 10
The difference voltage generated by the switching states atma>0.5.


### 3.5. Harmonic Distortion

The harmonic distortion performance of SVPWM strategies is evaluated by the THD of the load current and voltage output as follows [39]:(21)THDI=1Im∑n=2∞In2,THDV=1Vm∑n=2∞Vn2,where Im and In are the fundamental magnitude and the nth harmonic magnitude of phase current output, respectively. Vm and Vn are the fundamental magnitude and the nth harmonic magnitude of line-voltage output, respectively. In this paper, the THD spectrum of load current and output voltage is calculated to the 1000th harmonic.


## 3.1. Identify Region of Sectors

As in Figure4, each sector is divided into 4 regions numbered 1 to 4. The SVPWM technique for V⟶ref will be solved for sector I, and these results will be properly deduced for other sectors.The reference voltage vector synthesized by the three nearest voltage vectors, which are determined through the region where the reference vector is located, is as follows [33]:(7)d1=masinπ3−θI,d2=masinθI.The region identification is related tod1 and d2 as follows:Ifd1+d2≤0.5, then region 1Ifd1>0.5, then region 3Id2>0.5, then region 4Else region 2The remaining sectors will be converted to sector I. Therefore, the reference vector will be calibrated so that the modified angleθI falls between 0 and π/3, that is,(8)θI=θk−k−1π3,where k = 2, …, 6 for sectors II, …, VI, respectively.


## 3.2. Duty Cycle Calculation

The duty cycle for the voltage vector at the vertices of the triangle where the reference vector is placed essentially represents the dwell time of the selected switching states during the sampling intervalTs. For example, the reference vector in region 3 of sector I, as shown in Figure 5, is synthesized by voltage vectors V⟶100, V⟶210vir, and V⟶200 over a sampling period, defined by the following.(9)daV⟶100+dbV⟶210vir+dcV⟶200=V⟶ref,da+db+dc=1,where da, db, and dc are the duty ratios for the vectors V⟶100, V⟶210vir, and V⟶200, respectively.Figure 5
V⟶ref is located in region 3 of sector I.Substituting the values of the voltage vectors into (9) and separating the real and imaginary parts give(10)13Vdc12Vdc23Vdc0123Vdc0111dadbdc=VrcosθIVrsinθI1.Solving (10), the results are as follows:(11)dadbdc=2−2d1+d22d22d1−1,where d1 and d2 are defined as in (7).Calculating similarly for the remaining regions, the relationship between theV⟶ref location and duty factors is summarized in Table 3.Table 3
Duty ratio calculation in conventional 3-level NPC.
V⟶ref locationDuty ratiodadbdc12d11–2(d1 + d2)2d221−2d22(d1 + d2) – 11−2d132–2(d1 + d2)2d22d1−142d2−12d12–2(d1 + d2)In regions 2, 3, and 4 of sectors I and IV, the reference voltage vector is synthesized with the participation of the virtual vector. For example,V⟶ref in region 3 of sector I is synthesized by 3 voltage vectors V⟶100, V⟶200, and V⟶210vir with duty coefficients da, dc, and db, respectively, in which V⟶210vir is performed by V⟶200 and V⟶220, as defined in (6), with duty db/2 for each. The duty factors for available vectors V⟶100, V⟶220, and V⟶200 are adjusted to da, db/2, and db/2+dc, rewritten as 2−2d1+d2, d2, and 2d1+d2−1, respectively. All the adjusted duty coefficients of the voltage vectors of sectors I and IV are detailed in Table 4.Table 4
Adjusted duty ratio for voltage vectors in sectors I and IV.
RegionVoltage vectorAdjusted duty ratioSector ISector IV2V⟶100V⟶1221−2d2V⟶200V⟶022d1+d2−0.5V⟶220V⟶002d1+d2−0.5V⟶221V⟶0011−2d13V⟶100V⟶1222–2(d1 + d2)V⟶200V⟶0222d1+d2−1V⟶220V⟶002d24V⟶200V⟶022d1V⟶220V⟶002d1+2d2−1V⟶221V⟶0012–2(d1 + d2)


## 3.3. Switching Sequence

After calculating the duty for the selected voltage vectors to synthesize into the reference vector, the next step is to arrange the switching sequence. In this section, the switching sequence forV⟶ref is designed to minimize the switching frequency according to required criteria is as follows. ➀ The transition between switching states involves only two switches in the same phase leg. It is satisfied if there is no switching from state 0 to state 2 or vice versa in phase leg A and C. ➁ When the reference vector V⟶ref moves from one sector (or region) to the next, the transition requires no or a minimum number of switching. ➂ The switching sequence is arranged in a half-wave symmetrical pattern to eliminate even-order harmonics on the output line voltages.For example,V⟶ref is located in region 2 of sector I. A typical seven-segment switching sequence and output line-voltage waveforms are presented in Figure 6(a). It can be seen that requirement ➀ is satisfied. The starting and ending point is state 100, so the switching sequence in the remaining regions of sector I must also start from state 100 or 200 to satisfy requirement ➁. For the requirement ➂ to be also satisfied, then region 2 of sector IV must be arranged in the opposite order of sector I, as shown in Figure 6(b).Figure 6
Switching sequence for region 2: (a) sector I; (b) sector IV.
(a)(b)The typical switching sequence for the asymmetricT-type NPC inverter is shown in Figure 7.Figure 7
Switching sequence for asymmetricT-type NPC inverter.


## 3.4. The Self-Balancing Mechanism

The relation between the DC-link capacitor voltagesVc1,Vc2 and DC-link capacitor currents ic1,ic1 is provided as follows [34–38]:(12)Vc1=Vc1o+1C∫otic1dt,Vc2=Vc2o+1C∫otic2dt,where Vc1o and Vc2o are the initial values of c1 and c2 capacitors and supposing their capacitance C1=C2=C.Kirchhoff’s current law is applied at the neutral point as follows:(13)iNP=ic1−ic2.AssumingVc1o=Vc2o, the difference between Vc1 and Vc2 voltages per fundamental cycle is calculated as follows:(14)ΔVc=Vc1−Vc2=1C∫o2πiNPdt.When a zero or large vector is applied, as shown in Figures8(a)and 8(d), the difference voltage ΔVc is not affected because of iNP=0. In contrast, small and medium vectors can contribute to the variation of ΔVc, as shown in Figures 8(b) and 8(c), in which the polarity and magnitude of ΔVc are determined by the load current generated by the switching state.Figure 8
The effect of switching vectors on dc-link capacitors: (a) ZV; (b) SV; (c) MV; (d) LV.
(a)(b)(c)(d)For the selected switching sequence, as in Figure7, the voltage difference ΔVc generated by the switching states at the low modulation index ma≤0.5 in one fundamental period is presented in Figure 9. For example, when the reference vector moves in region 1 of sector I, the switching states 100, 221, and 222 are applied to synthesize the reference vector. The voltage difference caused by the switching states is calculated as follows:(15)ΔVcI=1C∫0ta/2iAdt+∫ta/2ta/2+tc/2iCdt+∫ta/2+tc/2+tbta/2+tc+tbiCdt+∫ta/2+tc+tbπ/3iAdt=ΔVcI①+ΔVcI②+ΔVcI③+ΔVcI④.Figure 9
The difference voltage generated by the switching states atma≤0.5.Similarly for region 1 of sector IV,(16)ΔVcIV=1C∫ππ+ta/2iAdt+∫π+ta/2π+ta/2+tc/2iCdt+∫π+ta/2+tc/2+tbπ+ta/2+tc+tbiCdt+∫π+ta/2+tc+tb4π/3iAdt=ΔVcIV①+ΔVcIV②+ΔVcIV③+ΔVcIV④.The general equation of the load currents is as follows:(17)iA=IAmsinωt+φA,iB=IBmsinωt−2π3+φB,iC=ICmsinωt+2π3+φC,where IXm is the max amplitude of the phase load current and φX is the load power factor angle; X∈A,B,C.Substitute (17) into (15) and (16), the definite integrals ΔVcI① and ΔVcIV② are calculated as follows:(18)VcI①=IAmωCcosφA−cosωta2+φA,VcIV①=IAmωC−cosφA+cosωta2+φA.Expression (18) and Figure 9 show that when applying the switching state 100, it causes a capacitor imbalance, by the red area marked ➀ in sector I. Meanwhile, the switching state 122 in sector IV makes the capacitor unbalanced by an amount equal to that caused by switching state 100 but a different sign (area marker ➀ in sector IV). Similarly, with the remaining definite integrals, we have(19)In one fundamental cycle, the switching state in the first half causes an imbalance. However, it quickly returns to balance in the next half-cycle by switching states on the opposite side, which have the same neutral current characteristics but a different sign, so(20)ΔVcI+ΔVcIV︸0+ΔVcII+ΔVcV︸0+ΔVcIII+ΔVcVI︸0=0,where ΔVci is the difference voltage caused by the switching states in sector i; i∈I, II, III, IV, V, VI.The self-balancing mechanism for the high modulation indexma>0.5 also occurs similarly, as presented in Figure 10.Figure 10
The difference voltage generated by the switching states atma>0.5.


## 3.5. Harmonic Distortion

The harmonic distortion performance of SVPWM strategies is evaluated by the THD of the load current and voltage output as follows [39]:(21)THDI=1Im∑n=2∞In2,THDV=1Vm∑n=2∞Vn2,where Im and In are the fundamental magnitude and the nth harmonic magnitude of phase current output, respectively. Vm and Vn are the fundamental magnitude and the nth harmonic magnitude of line-voltage output, respectively. In this paper, the THD spectrum of load current and output voltage is calculated to the 1000th harmonic.


## 4. Simulation and Experimental Results

### 4.1. Simulation Results

To validate the asymmetric 3-levelT-type NPC inverter, simulations were performed using MATLAB/Simulink software version 2018a, as shown in Figure 11. The system parameters are shown in Table 5.Figure 11
Simulation model in Matlab/Simulink.Table 5
System parameters for simulation.
DescriptionParameterValueDC voltageVdc600 VLoad resistorR12 ΩLoad inductorL20 mHDC-link capacitorC1, C21200μFSwitching frequencyfsw2.4 kHzFrequencyf50 HzFigure12 shows the steady-state of the VSVPWM method for the asymmetric 3-level inverter with ma = 0.9. The load current and the balance of DC-link capacitor voltages are depicted in Figures 12(c) and 12(d). Let V32 be a line voltage between outputs of 3-level and 2-level legs and V33 be a line voltage between outputs of two 3-level legs. The waveforms of V32 and V33 are illustrated in Figures 12(a) and 12(b) with THDV of about 44.4% and 32.8%, respectively.Figure 12
Steady-state response of VSVPWM for the asymmetric 3-level inverter atma = 0.9: (a) output voltage V32; (b) output voltage V33; (c) load current; (d) capacitor voltages.
(a)(b)(c)(d)In order to evaluate the dynamic response performance, a step change in modulation index from 0.4 to 0.8 is examined in this study. The diagram of the load current is shown in Figure13(c). The voltage of the capacitors is maintained in balance with ΔVc around 20 V and 32 V for the modulation index of 0.4 and 0.8, respectively, as shown in Figure 13(d). For ma = 0.4, the line-voltage quality V32 and V33 are almost the same, with THDV about 76%; for ma = 0.8, THDV of V33 is about 38% while that of V32 is 49.3%, as illustrated in Figures 13(a) and 13(b).Figure 13
The dynamic response of the asymmetric 3-level inverter for step changema from 0.4 to 0.8: (a) output voltage V32; (b) output voltage V33; (c) load current; (d) capacitor voltages.
(a)(b)(c)(d)THDV of the asymmetric 3-level inverter for different modulation indices is described in Table 6. For ma≤0.5, THDV on both V32 and V33 is almost the same. For ma>0.5, when the reference voltage vector appears in regions 2, 3, and 4, THDV of V32 is higher than V33. For example, at ma=0.9, THDV of V32 and V33 is 44.4% and 32.8%, respectively.Table 6
THDV for different modulation indices.
Total harmonic distortion (%)ma0.10.20.30.40.50.60.70.80.91V32230.7145.8104.976.552.450.952.449.344.439.0V33229.2147.3105.876.352.144.541.338.032.826.5The behavior of the system is also examined under a sudden change of the load atma = 0.9, as presented in Figure 14(a). In the initial state, the system operates with the load parameters R = 12 Ω and L = 20 mH; then, another resistor R’ = 12 Ω is connected parallel with R at t = 0.5 s. This results in a load current change from 23 A to 36 A with THDI about 1.32% to 0.98%, respectively, as shown in Figure 14(b). As depicted in Figure 14(c), the capacitor voltages are maintained to be well balanced with ΔVc around 22 V and 37 V. The output voltage quality of the asymmetric T-type NPC inverter is not influenced by the load parameters with THDV maintained about 44% and 32% for V32 and V33, as shown in Figure 14(d).Figure 14
System response at the module indexma=0.9 under variable load parameters: (a) change load parameters; (b) load current; (c) capacitor voltages; (d) output voltages.
(a)(b)(c)(d)To evaluate the influence of the load power factor onΔVc, simulation is examined with a fixed load impedance Z = 13.55 Ω and a variable power factor between 0.4 and 0.95 for the different modulation indexes. The results in Figure 15 show that the neutral point voltage maintains a relatively good balance at different load power factors and modulation indices. The region with ma ≤ 0.4 gives a small capacitor voltage difference in the range ΔVc≤4%, i.e., ΔVcmax is about 24 V, with all load power factors. For 0.4 < ma ≤ 0.8, the capacitor voltage difference gradually increases with the modulation index and load power factor and ∆Vc ranges from 3%–7% and reaches the maximum value of about 43 V at (ma; cos φ) = (0.6; 0.95). In the remaining region with ma > 0.8, ΔVc tends to decrease in the range of 3%–5% when the power factor increases. For example, at ma = 1, ΔVc  = 30 V for power factor 0.55 and ΔVc  = 16 V for power factor 0.95.Figure 15
Plot of voltage difference for various load power factors and modulation indices.A test with unbalanced load parameters depicted in Figure16(a) is also performed in this study. Figures 16(b) and 16(c) show that even though the 3-phase load currents are unbalanced, the capacitor voltages are maintained balanced with ΔVc about 28 V.Figure 16
The responses of VSVPWM for asymmetric 3-level inverter under unbalanced load atma = 0.9: (a) the unbalanced load; (b) load current; (c) capacitor voltages.
(a)(b)(c)To verify the behavior of the self-balancing mechanism of neutral point voltage, the simulation is performed atma=0.9, and capacitor c2 is discharged during t=0.5−0.56s by connected a resistor connected in parallel, as shown in Figure 17(a). The difference of capacitor voltages at t=0.56s is about 300 V. Under the proposed VSVPWM, it rapidly decreases and attains a steady-state value at 24 V after 0.3 s, as shown in Figure 17(b).Figure 17
The self-balancing mechanism of VSVPWM for the asymmetric 3-level inverter after setting a large imbalance: (a) forced imbalance withvc1>vc2; (b) capacitor voltages.
(a)(b)The graph in Figure18 compares voltage THD characteristics of the asymmetric T-type NPC, 3-level, and 2-level inverter. As observed, for ma≤0.5, the THD characteristic of the asymmetric T-type NPC topology is similar to that of the conventional 3-level. For ma>0.5, the THDV characteristic of the voltage V32 is higher than that of 3-level inverter, while the THDV characteristic of the voltage V33 is similar to that of 3-level inverter. THDV of the asymmetric T-type NPC inverter is significantly better than that of the 2-level inverter for all modulation indices.Figure 18
Graph of THDV comparison of asymmetric 3-level, conventional 3-level, and 2-level inverter.Another benefit of the asymmetric inverter can be demonstrated in loss comparison. The total loss is calculated as the sum of conduction loss and switching losses of all IGBTs and diodes, whose device datasheets are given in Table7. The principle of power loss calculation is explained in detail in [40]. The calculation is realized with the use of SimPowerSystems and Simscape in Matlab, with parameters Vdc = 300 V, ma = 0.9, and load R=1.5Ω,L=3mH.Table 7
Power device parameters.
IGBT module 2MBI150U2A-060ItemSymbolRatingUnitCollector-emitter voltageVCES600VGate-emitter voltageVGES±20VCollector currentIC150AICP300Collector power dissipationPC500WTurn-on timeton0.40µsTurn-off timetoff0.48Thermal resistanceIGBTRth(j-c)0.25°C/WFWDRth(j-c)0.46Contact thermal resistanceRth(c-f)0.05The comparison chart of conduction loss, switching loss, and total loss between the asymmetrical 3-level inverter and the conventional 3-level inverter is shown in Figures19–21, respectively. The conduction loss is almost unchanged at various switching frequencies, about 284 W for the conventional 3-level inverter and 277 W for the asymmetric 3-level inverter, as shown in Figure 19.Figure 19
Graph of conduction loss comparison for different switching frequencies.Figure 20
Graph of switching loss comparison for different switching frequencies.Figure 21
Graph of total loss comparison for different switching frequencies.The switching loss of the asymmetric 3-level inverter is shown to be smaller than that of the conventional 3-level inverter, as shown in Figure20. At fsw=15kHz, the switching loss of the asymmetric inverter is 73.1 W compared with the 104.4 W of the conventional 3-level inverter. It gives a reduction of about 30% switching loss. Similar results are also obtained for other switching frequencies.As demonstrated in Figure21, the total loss of the asymmetric inverter is lower than that of a conventional 3-level inverter. For example, at fsw=10kHz, the total losses of the asymmetric 3-level inverter and conventional 3-level inverter are 326.1 W and 353.8 W, respectively. Likewise, at fsw=20kHz, the total loss is 374.4 W for the asymmetric inverter and 424.2 W for the conventional 3-level inverter. This translates to a more than 12% improvement in power loss.


### 4.2. Experimental Results

To verify the effectiveness of the presented topology, the experiments were carried out on an asymmetricT-type NPC, 2-level, and 3-level configuration under both transient and steady-state conditions. A laboratory model is built as shown in Figure 22, including ➀ a digital signal processor TMS320F28379D to perform algorithms built-in Matlab/Simulink environment with Embedded Coder Support Package for TI C2000 Processors; ➁ the inverter made from TOSHIBA’s IGBT GT50J325-type; ➂ IGBT driver circuit which uses QP12W08S-37 type; ➃ DC-link capacitors; ➄ R-L load; and ➅ Tektronix TDS2024C oscilloscope. The experimental parameters are listed in Table 8.Figure 22
Experimental model in the laboratory.Table 8
Experimental parameters.
DescriptionParameterValueDC voltageVdc200 VLoad resistorR14.5 ΩLoad inductorL45 mHDC-link capacitorC1, C21200μFSwitching frequencyfsw2.4 kHzFrequencyf50 HzThe first test is performed with the modulation index stepped from 0.4 to 0.9. The results illustrated in Figure23 show that the DC-link capacitor voltages are maintained balanced at both modulation indices. The output voltage qualities V32 and V33 are similar at modulation index ma=0.4, THDV about 76%. For modulation index ma=0.9, the voltages V32 and V33 are distinguished with THDV about 45.32% and 33.85%.Figure 23
System response under step change in the modulation index.The second experiment is performed to evaluate the system’s response under a step change in load parameters atma=0.9. Initially, load 1 is with parameters R1=35Ω and L1=45mH; then, another resistor R2=25Ω is connected parallel with R1, as shown in Figure 24(a). The results from Figure 24(b) show that the capacitor voltage is kept balanced for both load parameters. The load current changes from 2.7 A to 5.1 A. The quality of the output voltage is unchanged, THDV about 45% and 33% for V32 and V33.Figure 24
System response under step change in load parameters: (a) change load parameters; (b) system response.
(a)(b)The test with an unbalanced load is also performed with the load parameters as in Figure25 at ma=0.9. The results shown in Figure 26 show that the capacitor voltages are kept balanced, and the output line-voltage qualities are similar to the above-balanced load test case, THDV about 45% and 33% for V32 and V33.Figure 25
Unbalanced load parameters used in experiment.Figure 26
System response under unbalanced load conditions.The experiment results of the self-balancing mechanism using VSVPWM strategy for asymmetric 3-level inverter under the unbalanced capacitor voltage condition atma = 0.9 are presented in Figure 27. In the initial state in Figure 27(a), switch K is closed, resulting in capacitor c2 discharging and ΔVc attains about 25 V. Then, K is opened, and ΔVc rapidly decreases and obtains balancing, as shown in Figure 27(b).Figure 27
The self-balancing mechanism of VSVPWM for asymmetric 3-level inverter under unbalanced capacitor condition: (a) forced imbalance withvc1>vc2; (b) capacitor voltages.
(a)(b)Figure28 shows the graph of the THDV comparison of the VSVPWM algorithm for the asymmetric 3-level inverter and the SVPWM technique for conventional 2-level and 3-level inverters. The diagram shows that the experimental results are similar to the simulation results obtained in Figure 18.Figure 28
Experimental results of THDV comparison between asymmetric 3-level, conventional 3-level, and 2-level inverter.


## 4.1. Simulation Results

To validate the asymmetric 3-levelT-type NPC inverter, simulations were performed using MATLAB/Simulink software version 2018a, as shown in Figure 11. The system parameters are shown in Table 5.Figure 11
Simulation model in Matlab/Simulink.Table 5
System parameters for simulation.
DescriptionParameterValueDC voltageVdc600 VLoad resistorR12 ΩLoad inductorL20 mHDC-link capacitorC1, C21200μFSwitching frequencyfsw2.4 kHzFrequencyf50 HzFigure12 shows the steady-state of the VSVPWM method for the asymmetric 3-level inverter with ma = 0.9. The load current and the balance of DC-link capacitor voltages are depicted in Figures 12(c) and 12(d). Let V32 be a line voltage between outputs of 3-level and 2-level legs and V33 be a line voltage between outputs of two 3-level legs. The waveforms of V32 and V33 are illustrated in Figures 12(a) and 12(b) with THDV of about 44.4% and 32.8%, respectively.Figure 12
Steady-state response of VSVPWM for the asymmetric 3-level inverter atma = 0.9: (a) output voltage V32; (b) output voltage V33; (c) load current; (d) capacitor voltages.
(a)(b)(c)(d)In order to evaluate the dynamic response performance, a step change in modulation index from 0.4 to 0.8 is examined in this study. The diagram of the load current is shown in Figure13(c). The voltage of the capacitors is maintained in balance with ΔVc around 20 V and 32 V for the modulation index of 0.4 and 0.8, respectively, as shown in Figure 13(d). For ma = 0.4, the line-voltage quality V32 and V33 are almost the same, with THDV about 76%; for ma = 0.8, THDV of V33 is about 38% while that of V32 is 49.3%, as illustrated in Figures 13(a) and 13(b).Figure 13
The dynamic response of the asymmetric 3-level inverter for step changema from 0.4 to 0.8: (a) output voltage V32; (b) output voltage V33; (c) load current; (d) capacitor voltages.
(a)(b)(c)(d)THDV of the asymmetric 3-level inverter for different modulation indices is described in Table 6. For ma≤0.5, THDV on both V32 and V33 is almost the same. For ma>0.5, when the reference voltage vector appears in regions 2, 3, and 4, THDV of V32 is higher than V33. For example, at ma=0.9, THDV of V32 and V33 is 44.4% and 32.8%, respectively.Table 6
THDV for different modulation indices.
Total harmonic distortion (%)ma0.10.20.30.40.50.60.70.80.91V32230.7145.8104.976.552.450.952.449.344.439.0V33229.2147.3105.876.352.144.541.338.032.826.5The behavior of the system is also examined under a sudden change of the load atma = 0.9, as presented in Figure 14(a). In the initial state, the system operates with the load parameters R = 12 Ω and L = 20 mH; then, another resistor R’ = 12 Ω is connected parallel with R at t = 0.5 s. This results in a load current change from 23 A to 36 A with THDI about 1.32% to 0.98%, respectively, as shown in Figure 14(b). As depicted in Figure 14(c), the capacitor voltages are maintained to be well balanced with ΔVc around 22 V and 37 V. The output voltage quality of the asymmetric T-type NPC inverter is not influenced by the load parameters with THDV maintained about 44% and 32% for V32 and V33, as shown in Figure 14(d).Figure 14
System response at the module indexma=0.9 under variable load parameters: (a) change load parameters; (b) load current; (c) capacitor voltages; (d) output voltages.
(a)(b)(c)(d)To evaluate the influence of the load power factor onΔVc, simulation is examined with a fixed load impedance Z = 13.55 Ω and a variable power factor between 0.4 and 0.95 for the different modulation indexes. The results in Figure 15 show that the neutral point voltage maintains a relatively good balance at different load power factors and modulation indices. The region with ma ≤ 0.4 gives a small capacitor voltage difference in the range ΔVc≤4%, i.e., ΔVcmax is about 24 V, with all load power factors. For 0.4 < ma ≤ 0.8, the capacitor voltage difference gradually increases with the modulation index and load power factor and ∆Vc ranges from 3%–7% and reaches the maximum value of about 43 V at (ma; cos φ) = (0.6; 0.95). In the remaining region with ma > 0.8, ΔVc tends to decrease in the range of 3%–5% when the power factor increases. For example, at ma = 1, ΔVc  = 30 V for power factor 0.55 and ΔVc  = 16 V for power factor 0.95.Figure 15
Plot of voltage difference for various load power factors and modulation indices.A test with unbalanced load parameters depicted in Figure16(a) is also performed in this study. Figures 16(b) and 16(c) show that even though the 3-phase load currents are unbalanced, the capacitor voltages are maintained balanced with ΔVc about 28 V.Figure 16
The responses of VSVPWM for asymmetric 3-level inverter under unbalanced load atma = 0.9: (a) the unbalanced load; (b) load current; (c) capacitor voltages.
(a)(b)(c)To verify the behavior of the self-balancing mechanism of neutral point voltage, the simulation is performed atma=0.9, and capacitor c2 is discharged during t=0.5−0.56s by connected a resistor connected in parallel, as shown in Figure 17(a). The difference of capacitor voltages at t=0.56s is about 300 V. Under the proposed VSVPWM, it rapidly decreases and attains a steady-state value at 24 V after 0.3 s, as shown in Figure 17(b).Figure 17
The self-balancing mechanism of VSVPWM for the asymmetric 3-level inverter after setting a large imbalance: (a) forced imbalance withvc1>vc2; (b) capacitor voltages.
(a)(b)The graph in Figure18 compares voltage THD characteristics of the asymmetric T-type NPC, 3-level, and 2-level inverter. As observed, for ma≤0.5, the THD characteristic of the asymmetric T-type NPC topology is similar to that of the conventional 3-level. For ma>0.5, the THDV characteristic of the voltage V32 is higher than that of 3-level inverter, while the THDV characteristic of the voltage V33 is similar to that of 3-level inverter. THDV of the asymmetric T-type NPC inverter is significantly better than that of the 2-level inverter for all modulation indices.Figure 18
Graph of THDV comparison of asymmetric 3-level, conventional 3-level, and 2-level inverter.Another benefit of the asymmetric inverter can be demonstrated in loss comparison. The total loss is calculated as the sum of conduction loss and switching losses of all IGBTs and diodes, whose device datasheets are given in Table7. The principle of power loss calculation is explained in detail in [40]. The calculation is realized with the use of SimPowerSystems and Simscape in Matlab, with parameters Vdc = 300 V, ma = 0.9, and load R=1.5Ω,L=3mH.Table 7
Power device parameters.
IGBT module 2MBI150U2A-060ItemSymbolRatingUnitCollector-emitter voltageVCES600VGate-emitter voltageVGES±20VCollector currentIC150AICP300Collector power dissipationPC500WTurn-on timeton0.40µsTurn-off timetoff0.48Thermal resistanceIGBTRth(j-c)0.25°C/WFWDRth(j-c)0.46Contact thermal resistanceRth(c-f)0.05The comparison chart of conduction loss, switching loss, and total loss between the asymmetrical 3-level inverter and the conventional 3-level inverter is shown in Figures19–21, respectively. The conduction loss is almost unchanged at various switching frequencies, about 284 W for the conventional 3-level inverter and 277 W for the asymmetric 3-level inverter, as shown in Figure 19.Figure 19
Graph of conduction loss comparison for different switching frequencies.Figure 20
Graph of switching loss comparison for different switching frequencies.Figure 21
Graph of total loss comparison for different switching frequencies.The switching loss of the asymmetric 3-level inverter is shown to be smaller than that of the conventional 3-level inverter, as shown in Figure20. At fsw=15kHz, the switching loss of the asymmetric inverter is 73.1 W compared with the 104.4 W of the conventional 3-level inverter. It gives a reduction of about 30% switching loss. Similar results are also obtained for other switching frequencies.As demonstrated in Figure21, the total loss of the asymmetric inverter is lower than that of a conventional 3-level inverter. For example, at fsw=10kHz, the total losses of the asymmetric 3-level inverter and conventional 3-level inverter are 326.1 W and 353.8 W, respectively. Likewise, at fsw=20kHz, the total loss is 374.4 W for the asymmetric inverter and 424.2 W for the conventional 3-level inverter. This translates to a more than 12% improvement in power loss.


## 4.2. Experimental Results

To verify the effectiveness of the presented topology, the experiments were carried out on an asymmetricT-type NPC, 2-level, and 3-level configuration under both transient and steady-state conditions. A laboratory model is built as shown in Figure 22, including ➀ a digital signal processor TMS320F28379D to perform algorithms built-in Matlab/Simulink environment with Embedded Coder Support Package for TI C2000 Processors; ➁ the inverter made from TOSHIBA’s IGBT GT50J325-type; ➂ IGBT driver circuit which uses QP12W08S-37 type; ➃ DC-link capacitors; ➄ R-L load; and ➅ Tektronix TDS2024C oscilloscope. The experimental parameters are listed in Table 8.Figure 22
Experimental model in the laboratory.Table 8
Experimental parameters.
DescriptionParameterValueDC voltageVdc200 VLoad resistorR14.5 ΩLoad inductorL45 mHDC-link capacitorC1, C21200μFSwitching frequencyfsw2.4 kHzFrequencyf50 HzThe first test is performed with the modulation index stepped from 0.4 to 0.9. The results illustrated in Figure23 show that the DC-link capacitor voltages are maintained balanced at both modulation indices. The output voltage qualities V32 and V33 are similar at modulation index ma=0.4, THDV about 76%. For modulation index ma=0.9, the voltages V32 and V33 are distinguished with THDV about 45.32% and 33.85%.Figure 23
System response under step change in the modulation index.The second experiment is performed to evaluate the system’s response under a step change in load parameters atma=0.9. Initially, load 1 is with parameters R1=35Ω and L1=45mH; then, another resistor R2=25Ω is connected parallel with R1, as shown in Figure 24(a). The results from Figure 24(b) show that the capacitor voltage is kept balanced for both load parameters. The load current changes from 2.7 A to 5.1 A. The quality of the output voltage is unchanged, THDV about 45% and 33% for V32 and V33.Figure 24
System response under step change in load parameters: (a) change load parameters; (b) system response.
(a)(b)The test with an unbalanced load is also performed with the load parameters as in Figure25 at ma=0.9. The results shown in Figure 26 show that the capacitor voltages are kept balanced, and the output line-voltage qualities are similar to the above-balanced load test case, THDV about 45% and 33% for V32 and V33.Figure 25
Unbalanced load parameters used in experiment.Figure 26
System response under unbalanced load conditions.The experiment results of the self-balancing mechanism using VSVPWM strategy for asymmetric 3-level inverter under the unbalanced capacitor voltage condition atma = 0.9 are presented in Figure 27. In the initial state in Figure 27(a), switch K is closed, resulting in capacitor c2 discharging and ΔVc attains about 25 V. Then, K is opened, and ΔVc rapidly decreases and obtains balancing, as shown in Figure 27(b).Figure 27
The self-balancing mechanism of VSVPWM for asymmetric 3-level inverter under unbalanced capacitor condition: (a) forced imbalance withvc1>vc2; (b) capacitor voltages.
(a)(b)Figure28 shows the graph of the THDV comparison of the VSVPWM algorithm for the asymmetric 3-level inverter and the SVPWM technique for conventional 2-level and 3-level inverters. The diagram shows that the experimental results are similar to the simulation results obtained in Figure 18.Figure 28
Experimental results of THDV comparison between asymmetric 3-level, conventional 3-level, and 2-level inverter.


## 5. Conclusions

This paper presents virtual SVPWM control for the asymmetricT-type NPC 3-level inverter topology. A modified space vector diagram is built with the help of the virtual vector. Then, the conventional SVPWM algorithm of the three nearest vectors is implemented. The switching sequence has been designed to reduce the amount of switching. A comparative evaluation between asymmetric T-type, 2-level, and 3-level inverters was performed. Simulation and experiment results show that the output voltage quality of the asymmetric T-type NPC inverter is much improved compared with that of the conventional 2-level inverter and almost similar to that of the conventional 3-level inverter. Besides, the capacitor voltages are also maintained in a good balance. The asymmetric inverter is attractive for applications that require lower cost but own similar output performances of a three-level inverter such as full output voltage range and low harmonic distortion. In another application, the proposed VSVPWM control can be applied for a conventional 3-level T-type NPC in a faulty condition while one T-leg connected to the neutral point is defectively open.



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*Source: 1379040-2021-12-07.xml*