# Diagnosis of Intermittent Faults in IGBTs Using the Latent Nestling Method with Hybrid Coloured Petri Nets

Authors: Leonardo Rodriguez-Urrego; Emilio García; Eduardo Quiles; Antonio Correcher; Francisco Morant; Ricardo Pizá
Journal: Mathematical Problems in Engineering
 (2015)

---

## Abstract

This paper presents a fault diagnosis application of the Latent Nestling Method to IGBTs. The paper extends the Latent Nestling Method based in Coloured Petri Nets (CPNs) to hybrid systems in such a manner that IGBTs performance can be modeled. CPNs allow for an enhanced capability for synthesis and modeling in contrast to the classical phenomena of combinational state explosion when Finite State Machine methods are applied. We present an IGBT model with different fault modes including those of intermittent nature that can be used advantageously as predictive symptoms within a predictive maintenance strategy. Ageing stress tests have been experimentally applied to the IGBTs modules and intermittent faults are diagnosed as precursors of permanent failures. In addition, ageing is validated with morphological analysis (Scanning Electron Microscopy) and semiqualitative analysis (Energy Dispersive Spectrometry).


---

## Body

## 1. Introduction

Nowadays digital electronic applications [1], power electronics [2], and even PCB [3] introduce IF diagnosis techniques for the analysis of faults by corrosion, contamination, overtemperature, overloads, electrochemical migration, and defects in manufacturing. IF diagnosis allows the utilization of preventive maintenance routines instead of corrective maintenance, so system reliability is increased.PSD and particularly IGBT are fundamental in many industrial systems. Some of the most important IGBT applications include lighting controls, power supplies, computer systems, industrial control devices, voltage converters [4], motors, or electric generators [5–7]. Recent studies about IGBT diagnosis focus on optimizing their properties as power inverter [8], as a switch [9], aging [10], thermal fatigue [11], or manufacturing defects [12].IF diagnosis in PSDs can be applied to predict the onset of permanent failures. Moreover it can be used to detect persistent IF episodes that degrade the operation of the system and can be considered as a failure. IF diagnosis applied to PSDs under stress tests predict the wearing-out of the component and can be contrasted with the aging related damage or morphological changes on the physical structure of the component allowing for the validation of the proposed diagnosis model. Then IF diagnosis allows for the estimation of the wear out phase in the hazard rate curve of electronic devices and can be applied in preventive maintenance procedures [13].Low power equipment is subjected to lower levels of energy during operation and gets discontinued before reaching the wearing-out stage. On the other hand, high power electronics equipment (IGBTs) is subjected to higher energy levels and faces wearing-out due to aging. The main objective of the paper is to show the relevance of the LNM to detect IF in IGBTs.Different methods have been proposed to diagnose semiconductor faults [14]. In [15] a study to characterize the IGBT behavior under stress conditions using a SPICE model was introduced. The authors develop an IGBT test circuit and they tested it in two conditions: normal operation and under stress. It is important to note that this diagnosis does not allow predictive maintenance tasks.In [16] it is discussed as a new method for IGBT fault detection based on gate voltage monitoring. This study takes into account only the degradation due to overcurrent or overtemperature. This analysis is very interesting and is taken into account for our prototype test development.Another interesting work [17] shows different methods for the aging analysis, such as thermal cycling (TC), hot carrier injection on electrical stress, and dielectric breakdown of time-dependent stimulus. Two of these techniques are applied in our work as accelerated test methods.The LNM was introduced by García et al. (2008) for the fault diagnosis in complex, large scale systems. LNM relies on CPNs as design platform and a method for nesting faulty marks in every place of the net. The formalization and methodology as well as some examples of the LNM can be seen in [18–21].The LNM was developed to handle complex discrete event systems, but many systems can be better modeled with hybrid models. This paper will extend the LNM to hybrid systems so it could be applied to diagnose them.Numerous studies have been carried out to explain hybrid process fault diagnosis using different methodologies [22–24]. New techniques need to be developed for diagnosis of Ifs, like the residual analysis proposed in our method.Furthermore, some researchers [25] analyzed fault models in hybrid PNs. Other authors propose an approximation of differential places to represent continuous places with negative markings (differential PNs [26]) in each place of latent nesting faults (
P
L
N
f
) in order to avoid unobservable transitions and allow faulty tokens of discrete type to be nested in places of continuous nature. The above provide advantages in solving hybrid systems of increasing complexity and finding failure times of each faulty token in the P
V
f using the stay time.IF diagnosis is carried out based on the work by [27] where the authors present a prognosis method to diagnose IF and predict the lifetime of electromechanical devices.The paper is structured as follows. Section2 introduces LNM for hybrid systems. It also includes a simple example to show its performance. Section 3 shows the IF diagnosis modeling based on LNM applied to IGBTs. Section 4 explains the test bench, the analysis, and experimental results. Finally, Section 5 draws some relevant conclusions.


## 2. Latent Nestling Method in Hybrid Systems

### 2.1. LNM Definition in Hybrid Systems

LNM is a methodology for fault diagnosis of discrete event complex systems (see [18, 20, 21]). Because this paper introduces a hybrid model for the IGBTs (presented in Section 3.2) we present an update of LNM to handle hybrid systems.The diagnoser will be a hybrid model of the system including normal and faulty behavior of each device in the system. In order to avoid the combinational explosion, [19] the model is built using hybrid colored PNs.A hybrid CPN for fault diagnosis (HCPNFD) is defined as(1)
H
C
P
N
F
D
=
P
,
T
,
P
r
e
,
P
o
s
t
,
M
0
,
C
o
,
C
,
P
L
N
f
,
T
F
,
P
V
f
,
S
,
k
k
k
P
,
T
,
P
r
e
,
P
o
s
t
,
M
0
,
C
o
,
C
,
P
L
N
f
,
T
F
,
P
V
f
,
S
,
T
e
m
p
o
,where P is a finite set of places, T is a finite set of transitions and Pre and Post are the input and output arc functions, with an additional argument C
k which is the color of the transition firing T
j. Thus P
r
e
(
P
i
,
T
j
/
C
k
) and P
o
s
t
(
P
i
,
T
j
/
C
k
) correspond in the general case to a linear combination of token colours related to place P
i.These functions can be divided into two subsets, depending on the transition-type behavior, namely, normal transitionT or faulty transition T
F
(2)
T
F
=
T
f
∪
T
r
,where T
f and T
r are the fault and recovery transitions, respectively. M
0 is the initial marking. P
L
N
f is the subset of fault latent nestling places, where P
L
N
f
⊆
P. If M
0 includes a faulty token in P
i
∈
P. This P
i is now called P
L
N
f
i. P
V
f is the subset of fault verification places.The places set and transitions set can be divided into two subsets(3)
P
=
P
D
∪
P
C
,
T
=
T
D
∪
T
C
.P
D is the set of discrete places and P
C is the set of continuous places. T
D is the discrete transitions set and T
C is the continuous transitions set.P
D will represent discrete states of a device such that the device is on and off and is starting and stopping, and so forth.P
C will represent the continuous states of a device so it computes a differential equation model.T
D will represent a discrete state change.T
C will represent step execution of the model contained in a P
C.In addition, the normal behavior marks can have discrete or continuous nature:(4)
N
=
N
D
∪
N
C
.N will represent a normal behavior token of a device and its evolution through the diagnoser will show the device state.C is the colour set assigned to different identifiers. C
=
N
D
∪
N
C
∪
f, where f
=
{
f
1
,
f
2
,
…
,
f
i
} is the subset of coloured tokens representing the fault set.Initial marking for a placeP
L
N
f
i in P
D (called P
L
N
f
i
D) will be (
N
D
,
f
), and the initial marking for a place P
L
N
f
i in P
C (called P
L
N
f
i
C) will be (
N
C
,
f
). P
r
e
T
:
(
P
×
T
)
→
Q
+ or N, P
o
s
t
T
:
(
P
×
T
)
→
Q
+ or N. Q
+ stands for the rational numbers (positives or zero). Then, for P
L
N
f
C,(5)
P
r
e
T
F
:
∑
i
=
n
k
P
L
N
f
i
C
×
T
f
⟶
f
∪
P
V
f
×
T
r
⟶
f
.LetP
r
e
T
F be the input arc function corresponding to subset T
F. Consider (6)
P
o
s
t
T
F
:
P
V
f
×
T
f
⟶
f
∪
∑
i
=
n
k
P
L
N
f
i
C
×
T
r
⟶
f
.LetP
o
s
t
T
F be the output arc function corresponding to subset T
F. In P
r
e
T
F and P
o
s
t
T
F case, the number of arc functions corresponding to T
F subset of each P
L
N
f
C depends on the continuous places mutually influenced, such that n is the initial continuous place influenced and k is the last continuous place influenced.ThisP
L
N
f
i
C represents a continuously variable behavior and also allows the nesting of discrete type faults.C
O
f: P
∪
T
→
{
D
,
C
} is a composite function that is defined for every place of the net.S
=
(
S
1
,
S
2
,
…
,
S
n
): it is the hybrid states set in the analyzed system. This set is composed of the operating states OS, fault signatures S
f, and recovery signatures S
r.T
e
m
p
o: it is a delay function that associates a rational number to each timed transition, where if for a function f
(
T
j
)
=
D, t
e
m
p
o
(
T
j
)
=
{
1
,
d
i
} is a delay associated with the transition T
j, expressed in time units, if for a function f
(
T
j
)
=
C, t
e
m
p
o
(
T
j
)
=
{
V
(
T
j
)
,
d
i
}
=
{
V
j
,
h
}, such that V
j represents the maximum firing speed associated with the transition T
j and h is the firing frequency that represents the sampling time. The method for delay fixing (
d
i
) or fixing the frequency firing (
h
) depends on the system behaviour.Definition 1.
A normal discrete transition in a HCPNFD is enabled at a markingM if each place P
i
∈
P
D in T
0
j
D meets the condition:(7)
M
P
i
≥
P
r
e
P
i
,
T
j
D
.Definition 2.
A normal continuous transition in a HCPNFD is enabled at a markingM if each place P
i in T
0
j
C meets the condition:(8)
M
P
i
≥
P
r
e
P
i
,
T
j
C
,
i
f
P
i
∈
P
D
,
M
P
i
∈
Q
+
,
i
f
P
i
∈
P
C
,where T
0
j
D is the set of the input places of discrete T
j and T
0
j
C is the set of the input places of continuous T
j. Likewise, it is necessary to meet the condition ∀
t
∈
T
C and ∀
p
∈
P
D, P
r
e
T
(
p
,
t
)
=
P
o
s
t
T
(
p
,
t
). P
i
,
T
j
/
C
k.


### 2.2. Initial Model and Fault Selection

The initial model is similar to that presented in the LNM. However, it includes continuous places where we could model the continuous behavior of the system variables. This step applies the techniques of modeling hybrid PNs [25].According to [19], the sensors map is defined as sm: M
0
→
S
R, where SR is the sensor readings, such that for M
k marking the expression is given by S
R
(
M
k
)
=
s
r
1
(
M
k
), s
r
2
(
M
k
)
,
…
,
s
r
n
(
M
k
). In the discrete case S
R
O
V
(
M
k
) is the set of sensor read output values for each discrete marking, such that(9)
S
R
O
V
M
k
=
S
R
O
V
e
v
M
k
+
S
R
O
V
u
e
v
M
k
,where S
R
O
V
e
v, S
R
O
V
u
e
v are subsets of expected and unexpected values accordingly.


### 2.3. Latent Nestling Places and Trajectories of Fault Verification and Fault Recovery

Latent nestling places are defined by the LNM. However, in a hybrid system, there is a continuous placeP
i
c which represents an operating state during a certain time t according to the states of the discrete places. Faults are assigned to this continuous place, such that P
L
N
f
i
∈
P
C. This implies that the faults have been generated by the anomalous behavior of the continuous variable, where the faults are nesting in the same continuous place now called P
L
N
f
i
C owing to this hybrid character.The trajectories of the faulty tokens are defined only by the fault and recovery transitions. The normal discrete and continuous transitions are defined by a classical method for modeling Hybrid PNs [25], as well as the firing rules for these transitions. Furthermore, fault and recovery transitions must be added to make restrictions that allow including both the place status as tokens of normal behavior.Definition 3.
A fault or recovery transition in a CPNFD or HCPNFD is enabled at a markingM for discrete places if each place P
L
N
f
k
D or P
V
f in T
F
j
0 meets the condition: for fault transitions T
f
(10)
M
P
L
N
f
k
≥
P
r
e
P
L
N
f
k
,
T
f
j
,for recovery transitions T
r
(11)
M
P
V
f
≥
P
r
e
P
V
f
,
T
r
j
∧
M
P
L
N
f
k
≥
P
r
e
P
L
N
f
k
,
T
r
j
.
LetM
F
′ be the fault marking obtained after firing of transition T
f
j with respect to the fault signature S
f
k. This fault marking is deducted from the marking M
F by the following relation.
For fault trajectory,(12)
M
F
′
P
L
N
f
i
D
=
M
F
P
L
N
f
i
D
+
P
o
s
t
P
V
f
,
T
f
j
S
R
O
V
u
e
v
-
P
r
e
P
L
N
f
i
D
,
T
f
j
S
R
O
V
u
e
v
,
∀
P
L
N
f
i
D
,
M
F
′
P
L
N
f
i
C
=
M
F
P
L
N
f
i
C
+
P
o
s
t
P
V
f
,
T
f
j
S
f
k
-
∑
i
=
n
k
P
r
e
P
L
N
f
i
C
,
T
f
j
S
f
k
,
∀
P
L
N
f
i
C
.
For recovery trajectory,(13)
M
F
′
P
V
f
=
M
F
P
V
f
+
∑
i
,
j
=
1
m
P
o
s
t
P
L
N
f
i
D
,
T
r
j
S
R
O
V
e
v
k
k
k
k
k
k
k
k
l
l
-
P
r
e
P
V
f
,
T
r
j
S
R
O
V
e
v
+
∑
i
=
1
m
∑
j
=
n
k
P
o
s
t
P
L
N
f
i
C
,
T
r
j
S
r
k
k
k
k
k
k
k
k
k
k
l
l
l
l
l
-
P
r
e
P
V
f
,
T
r
j
S
r
k
,
∀
P
V
f
.
m is the last P
L
N
f, n is the initial continuous place influenced, and k is the last continuous place influenced.
In the example case of Figure3 we have for fault verification(14)
M
F
′
P
L
N
f
1
=
M
F
P
L
N
f
1
+
P
o
s
t
P
V
f
,
T
f
1
S
R
O
V
u
e
v
-
P
r
e
P
L
N
f
1
,
T
f
1
S
R
O
V
u
e
v
,
M
F
′
P
L
N
f
1
C
=
M
F
P
L
N
f
1
C
+
P
o
s
t
P
V
f
,
T
f
2
S
f
k
-
P
r
e
P
L
N
f
1
C
,
T
f
2
S
f
k
.
And for fault recovery,(15)
M
F
′
P
V
f
=
M
F
P
V
f
+
P
o
s
t
P
L
N
f
1
,
T
r
1
S
R
O
V
e
v
-
P
r
e
P
V
f
,
T
r
1
S
R
O
V
e
v
+
P
o
s
t
P
L
N
f
1
C
,
T
r
2
S
r
k
-
P
r
e
P
V
f
,
T
r
2
S
r
k
.
To find the residues, it is necessary to obtain the operation dynamic model of the continuous variables. Depending on the complexity, the models could be represented in state variables, as in the hybrid PN analysis [26]. In this case, the approach presented in our example introduces a series of residues of the form r
(
t
)
=
y
(
t
)
-
y
^
(
t
) in every continuous place. The residue is computed in the continuous place, while the residual evaluation is checked in each fault and recovery transition.The definitions on states of hybrid operation, fault signatures, and diagnosability can be seen in [21].


## 2.1. LNM Definition in Hybrid Systems

LNM is a methodology for fault diagnosis of discrete event complex systems (see [18, 20, 21]). Because this paper introduces a hybrid model for the IGBTs (presented in Section 3.2) we present an update of LNM to handle hybrid systems.The diagnoser will be a hybrid model of the system including normal and faulty behavior of each device in the system. In order to avoid the combinational explosion, [19] the model is built using hybrid colored PNs.A hybrid CPN for fault diagnosis (HCPNFD) is defined as(1)
H
C
P
N
F
D
=
P
,
T
,
P
r
e
,
P
o
s
t
,
M
0
,
C
o
,
C
,
P
L
N
f
,
T
F
,
P
V
f
,
S
,
k
k
k
P
,
T
,
P
r
e
,
P
o
s
t
,
M
0
,
C
o
,
C
,
P
L
N
f
,
T
F
,
P
V
f
,
S
,
T
e
m
p
o
,where P is a finite set of places, T is a finite set of transitions and Pre and Post are the input and output arc functions, with an additional argument C
k which is the color of the transition firing T
j. Thus P
r
e
(
P
i
,
T
j
/
C
k
) and P
o
s
t
(
P
i
,
T
j
/
C
k
) correspond in the general case to a linear combination of token colours related to place P
i.These functions can be divided into two subsets, depending on the transition-type behavior, namely, normal transitionT or faulty transition T
F
(2)
T
F
=
T
f
∪
T
r
,where T
f and T
r are the fault and recovery transitions, respectively. M
0 is the initial marking. P
L
N
f is the subset of fault latent nestling places, where P
L
N
f
⊆
P. If M
0 includes a faulty token in P
i
∈
P. This P
i is now called P
L
N
f
i. P
V
f is the subset of fault verification places.The places set and transitions set can be divided into two subsets(3)
P
=
P
D
∪
P
C
,
T
=
T
D
∪
T
C
.P
D is the set of discrete places and P
C is the set of continuous places. T
D is the discrete transitions set and T
C is the continuous transitions set.P
D will represent discrete states of a device such that the device is on and off and is starting and stopping, and so forth.P
C will represent the continuous states of a device so it computes a differential equation model.T
D will represent a discrete state change.T
C will represent step execution of the model contained in a P
C.In addition, the normal behavior marks can have discrete or continuous nature:(4)
N
=
N
D
∪
N
C
.N will represent a normal behavior token of a device and its evolution through the diagnoser will show the device state.C is the colour set assigned to different identifiers. C
=
N
D
∪
N
C
∪
f, where f
=
{
f
1
,
f
2
,
…
,
f
i
} is the subset of coloured tokens representing the fault set.Initial marking for a placeP
L
N
f
i in P
D (called P
L
N
f
i
D) will be (
N
D
,
f
), and the initial marking for a place P
L
N
f
i in P
C (called P
L
N
f
i
C) will be (
N
C
,
f
). P
r
e
T
:
(
P
×
T
)
→
Q
+ or N, P
o
s
t
T
:
(
P
×
T
)
→
Q
+ or N. Q
+ stands for the rational numbers (positives or zero). Then, for P
L
N
f
C,(5)
P
r
e
T
F
:
∑
i
=
n
k
P
L
N
f
i
C
×
T
f
⟶
f
∪
P
V
f
×
T
r
⟶
f
.LetP
r
e
T
F be the input arc function corresponding to subset T
F. Consider (6)
P
o
s
t
T
F
:
P
V
f
×
T
f
⟶
f
∪
∑
i
=
n
k
P
L
N
f
i
C
×
T
r
⟶
f
.LetP
o
s
t
T
F be the output arc function corresponding to subset T
F. In P
r
e
T
F and P
o
s
t
T
F case, the number of arc functions corresponding to T
F subset of each P
L
N
f
C depends on the continuous places mutually influenced, such that n is the initial continuous place influenced and k is the last continuous place influenced.ThisP
L
N
f
i
C represents a continuously variable behavior and also allows the nesting of discrete type faults.C
O
f: P
∪
T
→
{
D
,
C
} is a composite function that is defined for every place of the net.S
=
(
S
1
,
S
2
,
…
,
S
n
): it is the hybrid states set in the analyzed system. This set is composed of the operating states OS, fault signatures S
f, and recovery signatures S
r.T
e
m
p
o: it is a delay function that associates a rational number to each timed transition, where if for a function f
(
T
j
)
=
D, t
e
m
p
o
(
T
j
)
=
{
1
,
d
i
} is a delay associated with the transition T
j, expressed in time units, if for a function f
(
T
j
)
=
C, t
e
m
p
o
(
T
j
)
=
{
V
(
T
j
)
,
d
i
}
=
{
V
j
,
h
}, such that V
j represents the maximum firing speed associated with the transition T
j and h is the firing frequency that represents the sampling time. The method for delay fixing (
d
i
) or fixing the frequency firing (
h
) depends on the system behaviour.Definition 1.
A normal discrete transition in a HCPNFD is enabled at a markingM if each place P
i
∈
P
D in T
0
j
D meets the condition:(7)
M
P
i
≥
P
r
e
P
i
,
T
j
D
.Definition 2.
A normal continuous transition in a HCPNFD is enabled at a markingM if each place P
i in T
0
j
C meets the condition:(8)
M
P
i
≥
P
r
e
P
i
,
T
j
C
,
i
f
P
i
∈
P
D
,
M
P
i
∈
Q
+
,
i
f
P
i
∈
P
C
,where T
0
j
D is the set of the input places of discrete T
j and T
0
j
C is the set of the input places of continuous T
j. Likewise, it is necessary to meet the condition ∀
t
∈
T
C and ∀
p
∈
P
D, P
r
e
T
(
p
,
t
)
=
P
o
s
t
T
(
p
,
t
). P
i
,
T
j
/
C
k.


## 2.2. Initial Model and Fault Selection

The initial model is similar to that presented in the LNM. However, it includes continuous places where we could model the continuous behavior of the system variables. This step applies the techniques of modeling hybrid PNs [25].According to [19], the sensors map is defined as sm: M
0
→
S
R, where SR is the sensor readings, such that for M
k marking the expression is given by S
R
(
M
k
)
=
s
r
1
(
M
k
), s
r
2
(
M
k
)
,
…
,
s
r
n
(
M
k
). In the discrete case S
R
O
V
(
M
k
) is the set of sensor read output values for each discrete marking, such that(9)
S
R
O
V
M
k
=
S
R
O
V
e
v
M
k
+
S
R
O
V
u
e
v
M
k
,where S
R
O
V
e
v, S
R
O
V
u
e
v are subsets of expected and unexpected values accordingly.


## 2.3. Latent Nestling Places and Trajectories of Fault Verification and Fault Recovery

Latent nestling places are defined by the LNM. However, in a hybrid system, there is a continuous placeP
i
c which represents an operating state during a certain time t according to the states of the discrete places. Faults are assigned to this continuous place, such that P
L
N
f
i
∈
P
C. This implies that the faults have been generated by the anomalous behavior of the continuous variable, where the faults are nesting in the same continuous place now called P
L
N
f
i
C owing to this hybrid character.The trajectories of the faulty tokens are defined only by the fault and recovery transitions. The normal discrete and continuous transitions are defined by a classical method for modeling Hybrid PNs [25], as well as the firing rules for these transitions. Furthermore, fault and recovery transitions must be added to make restrictions that allow including both the place status as tokens of normal behavior.Definition 3.
A fault or recovery transition in a CPNFD or HCPNFD is enabled at a markingM for discrete places if each place P
L
N
f
k
D or P
V
f in T
F
j
0 meets the condition: for fault transitions T
f
(10)
M
P
L
N
f
k
≥
P
r
e
P
L
N
f
k
,
T
f
j
,for recovery transitions T
r
(11)
M
P
V
f
≥
P
r
e
P
V
f
,
T
r
j
∧
M
P
L
N
f
k
≥
P
r
e
P
L
N
f
k
,
T
r
j
.
LetM
F
′ be the fault marking obtained after firing of transition T
f
j with respect to the fault signature S
f
k. This fault marking is deducted from the marking M
F by the following relation.
For fault trajectory,(12)
M
F
′
P
L
N
f
i
D
=
M
F
P
L
N
f
i
D
+
P
o
s
t
P
V
f
,
T
f
j
S
R
O
V
u
e
v
-
P
r
e
P
L
N
f
i
D
,
T
f
j
S
R
O
V
u
e
v
,
∀
P
L
N
f
i
D
,
M
F
′
P
L
N
f
i
C
=
M
F
P
L
N
f
i
C
+
P
o
s
t
P
V
f
,
T
f
j
S
f
k
-
∑
i
=
n
k
P
r
e
P
L
N
f
i
C
,
T
f
j
S
f
k
,
∀
P
L
N
f
i
C
.
For recovery trajectory,(13)
M
F
′
P
V
f
=
M
F
P
V
f
+
∑
i
,
j
=
1
m
P
o
s
t
P
L
N
f
i
D
,
T
r
j
S
R
O
V
e
v
k
k
k
k
k
k
k
k
l
l
-
P
r
e
P
V
f
,
T
r
j
S
R
O
V
e
v
+
∑
i
=
1
m
∑
j
=
n
k
P
o
s
t
P
L
N
f
i
C
,
T
r
j
S
r
k
k
k
k
k
k
k
k
k
k
l
l
l
l
l
-
P
r
e
P
V
f
,
T
r
j
S
r
k
,
∀
P
V
f
.
m is the last P
L
N
f, n is the initial continuous place influenced, and k is the last continuous place influenced.
In the example case of Figure3 we have for fault verification(14)
M
F
′
P
L
N
f
1
=
M
F
P
L
N
f
1
+
P
o
s
t
P
V
f
,
T
f
1
S
R
O
V
u
e
v
-
P
r
e
P
L
N
f
1
,
T
f
1
S
R
O
V
u
e
v
,
M
F
′
P
L
N
f
1
C
=
M
F
P
L
N
f
1
C
+
P
o
s
t
P
V
f
,
T
f
2
S
f
k
-
P
r
e
P
L
N
f
1
C
,
T
f
2
S
f
k
.
And for fault recovery,(15)
M
F
′
P
V
f
=
M
F
P
V
f
+
P
o
s
t
P
L
N
f
1
,
T
r
1
S
R
O
V
e
v
-
P
r
e
P
V
f
,
T
r
1
S
R
O
V
e
v
+
P
o
s
t
P
L
N
f
1
C
,
T
r
2
S
r
k
-
P
r
e
P
V
f
,
T
r
2
S
r
k
.
To find the residues, it is necessary to obtain the operation dynamic model of the continuous variables. Depending on the complexity, the models could be represented in state variables, as in the hybrid PN analysis [26]. In this case, the approach presented in our example introduces a series of residues of the form r
(
t
)
=
y
(
t
)
-
y
^
(
t
) in every continuous place. The residue is computed in the continuous place, while the residual evaluation is checked in each fault and recovery transition.The definitions on states of hybrid operation, fault signatures, and diagnosability can be seen in [21].


## 3. IFs Diagnosis Using the LNM Based on HCPNFD

### 3.1. Temporal Modeling of IFs

The main purpose of diagnosing IFs is the generation of tools to perform preventive maintenance of devices in industrial systems. It becomes necessary to apply data obtained online to determine the best time to replace or repair a component. The basic idea is to employ prediction methods based on process fault information. This information is indicative of the deterioration that is suffering the component.From this method we get two measures based on [27]: temporal failure density and pseudo period. Temporal failure density (D
F or density in the rest of the paper) is defined as the average time a particular fault is active within a sliding time window of duration w. D
F computed at time C
T for failure F
j
(
D
F
C
T
,
F
j
) is defined as(16)
D
F
C
T
,
F
j
=
∑
k
=
l
C
N
T
T
i
k
F
j
+
T
A
w
,where CNT is the number of faults inside the window, l stands for the index of the first fault detected inside the window {
l
:
F
T
i
,
l
F
j
>
(
C
T
-
w
), and F
T
l
-
1
F
j
<
(
C
T
-
w
)
} if it exists; otherwise  l
=
C
N
T
+
1 and T
A takes into account the duration of a failure occurred before C
T
-
w which continues active inside the window. Therefore,(17)
T
A
=
I
T
i
,
l
-
1
F
j
+
T
i
,
l
-
1
F
j
-
C
T
-
w
.Equation (17) is valid only if  T
A is positive; otherwise T
A
=
0, as this fact would indicate that the (
l
-
1
)th failure time is completely outside of the window. In a real system, DF tends to increase with time, thus confirming the hypothesis that IFs progressively damage the faulty device. In our case we only apply this measure DF with the LNM.


### 3.2. Initial Hybrid Model

For this case we will focus on a nonlinear model that represents the turn-on and turn-off switching waveforms and will get theV
C
E and V
G
E value that must have the IGBT. Some references that model different aspects of IGBTs and MOSFETs and the turn-on and turn-off waveforms can be seen in [28]. For each state (turn-on, turn-off) there are equations that define its operation.For the turn-on these equations are as follows.The increasing time constant fromV
G
E to V
t
h is limited by(18)
R
G
·
C
G
E
+
C
C
G
.The decreasing time constant fromV
C
E to V
C
E
(
s
a
t
) is limited by(19)
V
G
G
+
-
V
G
E
,
I
0
R
G
·
C
C
G
,where V
G
E
,
I
0 is the V
G
E voltage when it reaches the maximum collector current I
C
m
a
x and V
G
G
+ is the voltage across the gate to the emitter of the transistor during conduction. The increasing time constant from V
G
E to V
G
G
+ is limited by(20)
R
G
·
C
G
E
+
C
r
e
s
.The reverse transfer capacitanceC
r
e
s or C
C
G
,
m
i
l
l
e
r is approximately equal to C
C
G because the emitter is connected to ground. Then we will use C
r
e
s
≅
C
C
G in our final model.Based on the equivalent circuit of the IGBT gate, the gate currentI
G is deduced by(21)
I
G
t
=
C
G
E
·
d
V
G
E
d
t
-
C
C
G
d
V
C
E
-
V
G
E
d
t
.Note thatI
G is directly affected by C
C
G which causes a large change in gate voltage.For the turn-off the equations are as follows.V
G
E falls from injected V
G
G
+ to V
G
E
,
I
0 with a time constant given by (21). At this time, there is no change in the values of V
C
E or I
C.ThenV
C
E increases in this region, and the rate can be controlled with R
G as shown in the equation below:(22)
d
V
C
E
d
t
=
V
G
E
,
I
0
C
r
e
s
·
R
G
.Then the value ofV
C
E is maintained at v
d, while I
C decreases at a rate defined by the following equation. The rate of increase can also be controlled with R
G
(23)
d
I
C
d
t
=
g
f
e
·
V
G
E
,
I
0
C
i
e
s
·
R
G
,where C
i
e
s is the input capacitance measured between the gate and emitter terminals with the collector shorted to the emitter for AC signals, C
i
e
s
=
C
G
E
+
C
C
G. The value of these fixed capacitances can be found in the data sheet of the manufacturer.


#### 3.2.1. Hybrid Model Using Hybrid PNs

The hybrid model is implemented following the scheme of Figure1. Continuous places P
L
N
f
1
C and P
L
N
f
3
C represent the ideal behavior of voltages V
C
E and V
G
E, respectively. The continuous place P
L
N
f
2
C represents the load voltage as a function of the collector current. Transition T
4 represents the activation of the IGBT (turn-on) and transition T
2 shows the switch off the IGBT (turn-off).Figure 1
Model switching behavior of IGBT using HCPNFD based on LNM.Anytime during IGBT switching this model represents voltagesV
G
E and V
C
E. This allows us to detect any small changes in these voltages during the stress tests. Depending on the experimental condition a complete cycle lasts from 20 to 100 ms as shown in the Results section.As there are two continuous places, the model has two different residues that verify the same fault. It is important to nest in every place the same fault but with a different designation. Therefore we nested faultsf
1 as f
1
G if the fault is from the P
L
N
f
1
C and f
1
C if the fault comes from the P
L
N
f
3
C, likewise for fault f
2.We consider two types of IGBT faults. The first fault is the device in opencircuit. When there is a difference betweenV
C
E and V
G
E, such that V
G
E remains in a positive value, it is considered that the system is in a fault mode because the IGBT does not respond to the control signal for some reason. This fault mode can be caused by two conditions: command level design or an internal failure of the component (intermittent fault). This fault is called f
1. When there is a difference between signals V
C
E and V
G
E, such that V
G
E remains in a negative value, it is considered that the system is in a fault mode because the IGBT does not respond to the control signal for some reason. This fault mode can be caused by the same two previously defined conditions. This fault is called f
2.The residues were analyzed using a nonlinear model based on HCPNFD.Observing the model in Figure2, the residues may be obtained using the sensor readings with the values of continuous places. In this model g
f
e is the forward transconductance.Figure 2
Switching waveforms of IGBTs.Figure 3
Model to IFs diagnosis usingM
A
L
f.Therefore, if the fault comes from the placeP
L
N
f
1
C the faulty mark nested is f
1 as f
1
G and if the fault comes from the place P
L
N
f
3
C the faulty mark nested is f
1
C, similarly to the faulty mark f
2. The proposed HCPNFD model has been verified by a reasonably good agreement with measurements. Figure 2 shows the resulting waveforms of the turn-on and turn-off. In this case the turn-on starts with V
C
E high, V
G
E zero or negative and constant gate charging current producing a linear increase of the gate voltage. With falling collector-emitter voltage V
C
E the gate bias current is utilized for changing the charge of C
C
G (C
C
G
×
d
V
C
E
/
d
t) and the gate voltage remains constant. When the collector-emitter voltage has come down C
C
G becomes larger as much that also at reduced slope of V
C
E still all the bias supplied gate current is used up. Only when finally the current needed for charging becomes smaller than the bias supplied current the gate voltage rises again. The turn-off starts with V
C
E low, V
G
E positive or greater than the threshold voltage V
t
h. The gate voltage first decreases nearly linearly. With still low collector-emitter voltage V
C
E and with only moderate increase there is the strongest change (decrease) of C
C
G. Decrease of a capacitance at constant charge increases the voltage. As there is a bias source which is drawing current out of the gate, the gate-emitter voltage remains constant. Subsequently V
C
E increases and most of the gate discharge current is used up for C
C
G
d
V
C
E
/
d
t. The gate voltage further remains constant. The charge over process is finished when V
C
E roughly reaches the operating voltage. Now a further decrease of the gate voltage is possible again.In this case, a residue signal is obtained that would be expressed as(24)
r
x
,
y
=
V
¯
x
-
V
¯
x
′
,where V is the real reading and V
′ is the estimated reading. x is the IGBT analyzed, and y is the obtained residue number for this IGBT. In the case of the four IGBTs of our test, we obtain the following two residues for each IGBT:(25)
I
G
B
T
1
r
1,1
=
V
¯
G
E
1
-
V
¯
G
E
1
′
,
r
1,2
=
V
¯
C
E
1
-
V
¯
C
E
1
′
.Also, the implemented IF diagnosis needs the computing of DF with (17) and (18). So, some parameters must be computed:(i)
a counter CNT in theP
V
f place for each type of fault;
(ii)
a timert
f associated with each faulty mark. This timer is reset each time the fault is recovered;
(iii)
a timert
d associated with the P
V
f place.These parameters allow obtaining for each fault the temporal density and analyze the prediction of change for each IGBT. Therefore for each faultP—timed place P
V
f is T
e
m
p
o
(
P
V
f
)
=
t
d
=
w, where w is the duration of the sliding window.The counters for each fault are given byC
N
T
f
1
C = number of times the fault type f
1
C was isolated in P
V
f place in a window of duration w;
C
N
T
f
1
G = number of times the fault type f
1
G was isolated in P
V
f place in a window of duration w;
C
N
T
f
2
C = number of times the fault type f
2
C was isolated in P
V
f place in a window of duration w;
C
N
T
f
2
G = number of times the fault type f
2
G was isolated in P
V
f place in a window of duration w;
t
f
1
C = residence time of the fault f
1
C in P
V
f place;
t
f
1
G = residence time of the fault f
1
G in P
V
f place;
t
f
2
C = residence time of the fault f
2
C in P
V
f place;
t
f
2
G = residence time of the fault f
2
G in P
V
f place.An example of IFs can be seen in Figure3 with a window of w
=
18 units. There are two iterations of failure and recovery of type f
i
n. From left to right you can see the iteration number, the fired transition, the fault counter for that specific fault, time on the window, the timer of the fault, and finally the vector that stores timer information every time that a fault occurs.Based on the analysis of continuous places of Section2.3 and in Figure 2, we observe that P
1
C and P
3
C places are of isolated type; thereforeO
S
f
=
(
o
s
1
,
o
s
3
), where o
s
1
=
(
S
f
1
(
k
)
,
S
f
3
(
k
)
), respectively, to P
1, P
3 which are the discrete places that influence the behavior of continuous place P
1
C. Consider the following.o
s
3
=
(
S
f
7
(
k
)
,
S
f
9
(
k
)
), respectively, to P
7, P
9 which are the discrete places that influence the behavior of continuous place P
3
C. According to ∀
s
i
∈
S  ∃
∣
S
f
i
∈
o
s
∣
s
i
=
S
f
i for continuous isolated places, we obtain S
1
=
o
s
1, S
3
=
o
s
3 and each state S
i is equal to each fault signature S
f
i; therefore,(26)
S
f
1
k
=
f
1
G
,
S
1
i
f
r
1,1
,
f
2
G
,
S
1
i
f
r
1,1
,
S
f
3
k
=
f
1
G
,
S
3
i
f
r
1,1
,
f
2
G
,
S
3
i
f
r
1,1
,
S
f
7
k
=
f
1
C
,
S
7
i
f
r
1,2
,
f
2
C
,
S
7
i
f
r
1,2
,
S
f
9
k
=
f
1
C
,
S
9
i
f
r
1,2
,
f
2
C
,
S
9
i
f
r
1,2
.Applying (13) to fault trajectory, o
s
1:(27)
M
F
′
P
L
N
f
1
C
=
M
F
P
L
N
f
1
C
+
P
o
s
t
P
V
f
,
T
f
1
S
f
1
-
P
r
e
P
L
N
f
1
C
,
T
f
1
S
f
1
+
P
o
s
t
P
V
f
,
T
f
1
S
f
3
-
P
r
e
P
L
N
f
1
C
,
T
f
1
S
f
3
.o
s
2:(28)
M
F
′
P
L
N
f
3
C
=
M
F
P
L
N
f
3
C
+
P
o
s
t
P
V
f
,
T
f
2
S
f
7
-
P
r
e
P
L
N
f
1
C
,
T
f
2
S
f
7
+
P
o
s
t
P
V
f
,
T
f
2
S
f
9
-
P
r
e
P
L
N
f
1
C
,
T
f
2
S
f
9
.Applying (16) to fault recovery,(29)
M
F
′
P
V
f
=
M
F
P
V
f
+
P
o
s
t
P
L
N
f
1
C
,
T
r
1
S
r
1
-
P
r
e
P
V
f
,
T
r
1
S
r
1
+
P
o
s
t
P
L
N
f
1
C
,
T
r
1
S
r
3
+
P
r
e
P
V
f
,
T
r
1
S
r
3
+
P
o
s
t
P
L
N
f
2
C
,
T
r
2
S
r
7
-
P
r
e
P
V
f
,
T
r
2
S
r
7
+
P
o
s
t
P
L
N
f
2
C
,
T
r
2
S
r
9
-
P
r
e
P
V
f
,
T
r
2
S
r
9
.


## 3.1. Temporal Modeling of IFs

The main purpose of diagnosing IFs is the generation of tools to perform preventive maintenance of devices in industrial systems. It becomes necessary to apply data obtained online to determine the best time to replace or repair a component. The basic idea is to employ prediction methods based on process fault information. This information is indicative of the deterioration that is suffering the component.From this method we get two measures based on [27]: temporal failure density and pseudo period. Temporal failure density (D
F or density in the rest of the paper) is defined as the average time a particular fault is active within a sliding time window of duration w. D
F computed at time C
T for failure F
j
(
D
F
C
T
,
F
j
) is defined as(16)
D
F
C
T
,
F
j
=
∑
k
=
l
C
N
T
T
i
k
F
j
+
T
A
w
,where CNT is the number of faults inside the window, l stands for the index of the first fault detected inside the window {
l
:
F
T
i
,
l
F
j
>
(
C
T
-
w
), and F
T
l
-
1
F
j
<
(
C
T
-
w
)
} if it exists; otherwise  l
=
C
N
T
+
1 and T
A takes into account the duration of a failure occurred before C
T
-
w which continues active inside the window. Therefore,(17)
T
A
=
I
T
i
,
l
-
1
F
j
+
T
i
,
l
-
1
F
j
-
C
T
-
w
.Equation (17) is valid only if  T
A is positive; otherwise T
A
=
0, as this fact would indicate that the (
l
-
1
)th failure time is completely outside of the window. In a real system, DF tends to increase with time, thus confirming the hypothesis that IFs progressively damage the faulty device. In our case we only apply this measure DF with the LNM.


## 3.2. Initial Hybrid Model

For this case we will focus on a nonlinear model that represents the turn-on and turn-off switching waveforms and will get theV
C
E and V
G
E value that must have the IGBT. Some references that model different aspects of IGBTs and MOSFETs and the turn-on and turn-off waveforms can be seen in [28]. For each state (turn-on, turn-off) there are equations that define its operation.For the turn-on these equations are as follows.The increasing time constant fromV
G
E to V
t
h is limited by(18)
R
G
·
C
G
E
+
C
C
G
.The decreasing time constant fromV
C
E to V
C
E
(
s
a
t
) is limited by(19)
V
G
G
+
-
V
G
E
,
I
0
R
G
·
C
C
G
,where V
G
E
,
I
0 is the V
G
E voltage when it reaches the maximum collector current I
C
m
a
x and V
G
G
+ is the voltage across the gate to the emitter of the transistor during conduction. The increasing time constant from V
G
E to V
G
G
+ is limited by(20)
R
G
·
C
G
E
+
C
r
e
s
.The reverse transfer capacitanceC
r
e
s or C
C
G
,
m
i
l
l
e
r is approximately equal to C
C
G because the emitter is connected to ground. Then we will use C
r
e
s
≅
C
C
G in our final model.Based on the equivalent circuit of the IGBT gate, the gate currentI
G is deduced by(21)
I
G
t
=
C
G
E
·
d
V
G
E
d
t
-
C
C
G
d
V
C
E
-
V
G
E
d
t
.Note thatI
G is directly affected by C
C
G which causes a large change in gate voltage.For the turn-off the equations are as follows.V
G
E falls from injected V
G
G
+ to V
G
E
,
I
0 with a time constant given by (21). At this time, there is no change in the values of V
C
E or I
C.ThenV
C
E increases in this region, and the rate can be controlled with R
G as shown in the equation below:(22)
d
V
C
E
d
t
=
V
G
E
,
I
0
C
r
e
s
·
R
G
.Then the value ofV
C
E is maintained at v
d, while I
C decreases at a rate defined by the following equation. The rate of increase can also be controlled with R
G
(23)
d
I
C
d
t
=
g
f
e
·
V
G
E
,
I
0
C
i
e
s
·
R
G
,where C
i
e
s is the input capacitance measured between the gate and emitter terminals with the collector shorted to the emitter for AC signals, C
i
e
s
=
C
G
E
+
C
C
G. The value of these fixed capacitances can be found in the data sheet of the manufacturer.


### 3.2.1. Hybrid Model Using Hybrid PNs

The hybrid model is implemented following the scheme of Figure1. Continuous places P
L
N
f
1
C and P
L
N
f
3
C represent the ideal behavior of voltages V
C
E and V
G
E, respectively. The continuous place P
L
N
f
2
C represents the load voltage as a function of the collector current. Transition T
4 represents the activation of the IGBT (turn-on) and transition T
2 shows the switch off the IGBT (turn-off).Figure 1
Model switching behavior of IGBT using HCPNFD based on LNM.Anytime during IGBT switching this model represents voltagesV
G
E and V
C
E. This allows us to detect any small changes in these voltages during the stress tests. Depending on the experimental condition a complete cycle lasts from 20 to 100 ms as shown in the Results section.As there are two continuous places, the model has two different residues that verify the same fault. It is important to nest in every place the same fault but with a different designation. Therefore we nested faultsf
1 as f
1
G if the fault is from the P
L
N
f
1
C and f
1
C if the fault comes from the P
L
N
f
3
C, likewise for fault f
2.We consider two types of IGBT faults. The first fault is the device in opencircuit. When there is a difference betweenV
C
E and V
G
E, such that V
G
E remains in a positive value, it is considered that the system is in a fault mode because the IGBT does not respond to the control signal for some reason. This fault mode can be caused by two conditions: command level design or an internal failure of the component (intermittent fault). This fault is called f
1. When there is a difference between signals V
C
E and V
G
E, such that V
G
E remains in a negative value, it is considered that the system is in a fault mode because the IGBT does not respond to the control signal for some reason. This fault mode can be caused by the same two previously defined conditions. This fault is called f
2.The residues were analyzed using a nonlinear model based on HCPNFD.Observing the model in Figure2, the residues may be obtained using the sensor readings with the values of continuous places. In this model g
f
e is the forward transconductance.Figure 2
Switching waveforms of IGBTs.Figure 3
Model to IFs diagnosis usingM
A
L
f.Therefore, if the fault comes from the placeP
L
N
f
1
C the faulty mark nested is f
1 as f
1
G and if the fault comes from the place P
L
N
f
3
C the faulty mark nested is f
1
C, similarly to the faulty mark f
2. The proposed HCPNFD model has been verified by a reasonably good agreement with measurements. Figure 2 shows the resulting waveforms of the turn-on and turn-off. In this case the turn-on starts with V
C
E high, V
G
E zero or negative and constant gate charging current producing a linear increase of the gate voltage. With falling collector-emitter voltage V
C
E the gate bias current is utilized for changing the charge of C
C
G (C
C
G
×
d
V
C
E
/
d
t) and the gate voltage remains constant. When the collector-emitter voltage has come down C
C
G becomes larger as much that also at reduced slope of V
C
E still all the bias supplied gate current is used up. Only when finally the current needed for charging becomes smaller than the bias supplied current the gate voltage rises again. The turn-off starts with V
C
E low, V
G
E positive or greater than the threshold voltage V
t
h. The gate voltage first decreases nearly linearly. With still low collector-emitter voltage V
C
E and with only moderate increase there is the strongest change (decrease) of C
C
G. Decrease of a capacitance at constant charge increases the voltage. As there is a bias source which is drawing current out of the gate, the gate-emitter voltage remains constant. Subsequently V
C
E increases and most of the gate discharge current is used up for C
C
G
d
V
C
E
/
d
t. The gate voltage further remains constant. The charge over process is finished when V
C
E roughly reaches the operating voltage. Now a further decrease of the gate voltage is possible again.In this case, a residue signal is obtained that would be expressed as(24)
r
x
,
y
=
V
¯
x
-
V
¯
x
′
,where V is the real reading and V
′ is the estimated reading. x is the IGBT analyzed, and y is the obtained residue number for this IGBT. In the case of the four IGBTs of our test, we obtain the following two residues for each IGBT:(25)
I
G
B
T
1
r
1,1
=
V
¯
G
E
1
-
V
¯
G
E
1
′
,
r
1,2
=
V
¯
C
E
1
-
V
¯
C
E
1
′
.Also, the implemented IF diagnosis needs the computing of DF with (17) and (18). So, some parameters must be computed:(i)
a counter CNT in theP
V
f place for each type of fault;
(ii)
a timert
f associated with each faulty mark. This timer is reset each time the fault is recovered;
(iii)
a timert
d associated with the P
V
f place.These parameters allow obtaining for each fault the temporal density and analyze the prediction of change for each IGBT. Therefore for each faultP—timed place P
V
f is T
e
m
p
o
(
P
V
f
)
=
t
d
=
w, where w is the duration of the sliding window.The counters for each fault are given byC
N
T
f
1
C = number of times the fault type f
1
C was isolated in P
V
f place in a window of duration w;
C
N
T
f
1
G = number of times the fault type f
1
G was isolated in P
V
f place in a window of duration w;
C
N
T
f
2
C = number of times the fault type f
2
C was isolated in P
V
f place in a window of duration w;
C
N
T
f
2
G = number of times the fault type f
2
G was isolated in P
V
f place in a window of duration w;
t
f
1
C = residence time of the fault f
1
C in P
V
f place;
t
f
1
G = residence time of the fault f
1
G in P
V
f place;
t
f
2
C = residence time of the fault f
2
C in P
V
f place;
t
f
2
G = residence time of the fault f
2
G in P
V
f place.An example of IFs can be seen in Figure3 with a window of w
=
18 units. There are two iterations of failure and recovery of type f
i
n. From left to right you can see the iteration number, the fired transition, the fault counter for that specific fault, time on the window, the timer of the fault, and finally the vector that stores timer information every time that a fault occurs.Based on the analysis of continuous places of Section2.3 and in Figure 2, we observe that P
1
C and P
3
C places are of isolated type; thereforeO
S
f
=
(
o
s
1
,
o
s
3
), where o
s
1
=
(
S
f
1
(
k
)
,
S
f
3
(
k
)
), respectively, to P
1, P
3 which are the discrete places that influence the behavior of continuous place P
1
C. Consider the following.o
s
3
=
(
S
f
7
(
k
)
,
S
f
9
(
k
)
), respectively, to P
7, P
9 which are the discrete places that influence the behavior of continuous place P
3
C. According to ∀
s
i
∈
S  ∃
∣
S
f
i
∈
o
s
∣
s
i
=
S
f
i for continuous isolated places, we obtain S
1
=
o
s
1, S
3
=
o
s
3 and each state S
i is equal to each fault signature S
f
i; therefore,(26)
S
f
1
k
=
f
1
G
,
S
1
i
f
r
1,1
,
f
2
G
,
S
1
i
f
r
1,1
,
S
f
3
k
=
f
1
G
,
S
3
i
f
r
1,1
,
f
2
G
,
S
3
i
f
r
1,1
,
S
f
7
k
=
f
1
C
,
S
7
i
f
r
1,2
,
f
2
C
,
S
7
i
f
r
1,2
,
S
f
9
k
=
f
1
C
,
S
9
i
f
r
1,2
,
f
2
C
,
S
9
i
f
r
1,2
.Applying (13) to fault trajectory, o
s
1:(27)
M
F
′
P
L
N
f
1
C
=
M
F
P
L
N
f
1
C
+
P
o
s
t
P
V
f
,
T
f
1
S
f
1
-
P
r
e
P
L
N
f
1
C
,
T
f
1
S
f
1
+
P
o
s
t
P
V
f
,
T
f
1
S
f
3
-
P
r
e
P
L
N
f
1
C
,
T
f
1
S
f
3
.o
s
2:(28)
M
F
′
P
L
N
f
3
C
=
M
F
P
L
N
f
3
C
+
P
o
s
t
P
V
f
,
T
f
2
S
f
7
-
P
r
e
P
L
N
f
1
C
,
T
f
2
S
f
7
+
P
o
s
t
P
V
f
,
T
f
2
S
f
9
-
P
r
e
P
L
N
f
1
C
,
T
f
2
S
f
9
.Applying (16) to fault recovery,(29)
M
F
′
P
V
f
=
M
F
P
V
f
+
P
o
s
t
P
L
N
f
1
C
,
T
r
1
S
r
1
-
P
r
e
P
V
f
,
T
r
1
S
r
1
+
P
o
s
t
P
L
N
f
1
C
,
T
r
1
S
r
3
+
P
r
e
P
V
f
,
T
r
1
S
r
3
+
P
o
s
t
P
L
N
f
2
C
,
T
r
2
S
r
7
-
P
r
e
P
V
f
,
T
r
2
S
r
7
+
P
o
s
t
P
L
N
f
2
C
,
T
r
2
S
r
9
-
P
r
e
P
V
f
,
T
r
2
S
r
9
.


## 3.2.1. Hybrid Model Using Hybrid PNs

The hybrid model is implemented following the scheme of Figure1. Continuous places P
L
N
f
1
C and P
L
N
f
3
C represent the ideal behavior of voltages V
C
E and V
G
E, respectively. The continuous place P
L
N
f
2
C represents the load voltage as a function of the collector current. Transition T
4 represents the activation of the IGBT (turn-on) and transition T
2 shows the switch off the IGBT (turn-off).Figure 1
Model switching behavior of IGBT using HCPNFD based on LNM.Anytime during IGBT switching this model represents voltagesV
G
E and V
C
E. This allows us to detect any small changes in these voltages during the stress tests. Depending on the experimental condition a complete cycle lasts from 20 to 100 ms as shown in the Results section.As there are two continuous places, the model has two different residues that verify the same fault. It is important to nest in every place the same fault but with a different designation. Therefore we nested faultsf
1 as f
1
G if the fault is from the P
L
N
f
1
C and f
1
C if the fault comes from the P
L
N
f
3
C, likewise for fault f
2.We consider two types of IGBT faults. The first fault is the device in opencircuit. When there is a difference betweenV
C
E and V
G
E, such that V
G
E remains in a positive value, it is considered that the system is in a fault mode because the IGBT does not respond to the control signal for some reason. This fault mode can be caused by two conditions: command level design or an internal failure of the component (intermittent fault). This fault is called f
1. When there is a difference between signals V
C
E and V
G
E, such that V
G
E remains in a negative value, it is considered that the system is in a fault mode because the IGBT does not respond to the control signal for some reason. This fault mode can be caused by the same two previously defined conditions. This fault is called f
2.The residues were analyzed using a nonlinear model based on HCPNFD.Observing the model in Figure2, the residues may be obtained using the sensor readings with the values of continuous places. In this model g
f
e is the forward transconductance.Figure 2
Switching waveforms of IGBTs.Figure 3
Model to IFs diagnosis usingM
A
L
f.Therefore, if the fault comes from the placeP
L
N
f
1
C the faulty mark nested is f
1 as f
1
G and if the fault comes from the place P
L
N
f
3
C the faulty mark nested is f
1
C, similarly to the faulty mark f
2. The proposed HCPNFD model has been verified by a reasonably good agreement with measurements. Figure 2 shows the resulting waveforms of the turn-on and turn-off. In this case the turn-on starts with V
C
E high, V
G
E zero or negative and constant gate charging current producing a linear increase of the gate voltage. With falling collector-emitter voltage V
C
E the gate bias current is utilized for changing the charge of C
C
G (C
C
G
×
d
V
C
E
/
d
t) and the gate voltage remains constant. When the collector-emitter voltage has come down C
C
G becomes larger as much that also at reduced slope of V
C
E still all the bias supplied gate current is used up. Only when finally the current needed for charging becomes smaller than the bias supplied current the gate voltage rises again. The turn-off starts with V
C
E low, V
G
E positive or greater than the threshold voltage V
t
h. The gate voltage first decreases nearly linearly. With still low collector-emitter voltage V
C
E and with only moderate increase there is the strongest change (decrease) of C
C
G. Decrease of a capacitance at constant charge increases the voltage. As there is a bias source which is drawing current out of the gate, the gate-emitter voltage remains constant. Subsequently V
C
E increases and most of the gate discharge current is used up for C
C
G
d
V
C
E
/
d
t. The gate voltage further remains constant. The charge over process is finished when V
C
E roughly reaches the operating voltage. Now a further decrease of the gate voltage is possible again.In this case, a residue signal is obtained that would be expressed as(24)
r
x
,
y
=
V
¯
x
-
V
¯
x
′
,where V is the real reading and V
′ is the estimated reading. x is the IGBT analyzed, and y is the obtained residue number for this IGBT. In the case of the four IGBTs of our test, we obtain the following two residues for each IGBT:(25)
I
G
B
T
1
r
1,1
=
V
¯
G
E
1
-
V
¯
G
E
1
′
,
r
1,2
=
V
¯
C
E
1
-
V
¯
C
E
1
′
.Also, the implemented IF diagnosis needs the computing of DF with (17) and (18). So, some parameters must be computed:(i)
a counter CNT in theP
V
f place for each type of fault;
(ii)
a timert
f associated with each faulty mark. This timer is reset each time the fault is recovered;
(iii)
a timert
d associated with the P
V
f place.These parameters allow obtaining for each fault the temporal density and analyze the prediction of change for each IGBT. Therefore for each faultP—timed place P
V
f is T
e
m
p
o
(
P
V
f
)
=
t
d
=
w, where w is the duration of the sliding window.The counters for each fault are given byC
N
T
f
1
C = number of times the fault type f
1
C was isolated in P
V
f place in a window of duration w;
C
N
T
f
1
G = number of times the fault type f
1
G was isolated in P
V
f place in a window of duration w;
C
N
T
f
2
C = number of times the fault type f
2
C was isolated in P
V
f place in a window of duration w;
C
N
T
f
2
G = number of times the fault type f
2
G was isolated in P
V
f place in a window of duration w;
t
f
1
C = residence time of the fault f
1
C in P
V
f place;
t
f
1
G = residence time of the fault f
1
G in P
V
f place;
t
f
2
C = residence time of the fault f
2
C in P
V
f place;
t
f
2
G = residence time of the fault f
2
G in P
V
f place.An example of IFs can be seen in Figure3 with a window of w
=
18 units. There are two iterations of failure and recovery of type f
i
n. From left to right you can see the iteration number, the fired transition, the fault counter for that specific fault, time on the window, the timer of the fault, and finally the vector that stores timer information every time that a fault occurs.Based on the analysis of continuous places of Section2.3 and in Figure 2, we observe that P
1
C and P
3
C places are of isolated type; thereforeO
S
f
=
(
o
s
1
,
o
s
3
), where o
s
1
=
(
S
f
1
(
k
)
,
S
f
3
(
k
)
), respectively, to P
1, P
3 which are the discrete places that influence the behavior of continuous place P
1
C. Consider the following.o
s
3
=
(
S
f
7
(
k
)
,
S
f
9
(
k
)
), respectively, to P
7, P
9 which are the discrete places that influence the behavior of continuous place P
3
C. According to ∀
s
i
∈
S  ∃
∣
S
f
i
∈
o
s
∣
s
i
=
S
f
i for continuous isolated places, we obtain S
1
=
o
s
1, S
3
=
o
s
3 and each state S
i is equal to each fault signature S
f
i; therefore,(26)
S
f
1
k
=
f
1
G
,
S
1
i
f
r
1,1
,
f
2
G
,
S
1
i
f
r
1,1
,
S
f
3
k
=
f
1
G
,
S
3
i
f
r
1,1
,
f
2
G
,
S
3
i
f
r
1,1
,
S
f
7
k
=
f
1
C
,
S
7
i
f
r
1,2
,
f
2
C
,
S
7
i
f
r
1,2
,
S
f
9
k
=
f
1
C
,
S
9
i
f
r
1,2
,
f
2
C
,
S
9
i
f
r
1,2
.Applying (13) to fault trajectory, o
s
1:(27)
M
F
′
P
L
N
f
1
C
=
M
F
P
L
N
f
1
C
+
P
o
s
t
P
V
f
,
T
f
1
S
f
1
-
P
r
e
P
L
N
f
1
C
,
T
f
1
S
f
1
+
P
o
s
t
P
V
f
,
T
f
1
S
f
3
-
P
r
e
P
L
N
f
1
C
,
T
f
1
S
f
3
.o
s
2:(28)
M
F
′
P
L
N
f
3
C
=
M
F
P
L
N
f
3
C
+
P
o
s
t
P
V
f
,
T
f
2
S
f
7
-
P
r
e
P
L
N
f
1
C
,
T
f
2
S
f
7
+
P
o
s
t
P
V
f
,
T
f
2
S
f
9
-
P
r
e
P
L
N
f
1
C
,
T
f
2
S
f
9
.Applying (16) to fault recovery,(29)
M
F
′
P
V
f
=
M
F
P
V
f
+
P
o
s
t
P
L
N
f
1
C
,
T
r
1
S
r
1
-
P
r
e
P
V
f
,
T
r
1
S
r
1
+
P
o
s
t
P
L
N
f
1
C
,
T
r
1
S
r
3
+
P
r
e
P
V
f
,
T
r
1
S
r
3
+
P
o
s
t
P
L
N
f
2
C
,
T
r
2
S
r
7
-
P
r
e
P
V
f
,
T
r
2
S
r
7
+
P
o
s
t
P
L
N
f
2
C
,
T
r
2
S
r
9
-
P
r
e
P
V
f
,
T
r
2
S
r
9
.


## 4. Analysis and Experimental Test Results

### 4.1. Hardware Implementation

The test bench is based on two test circuits. The first circuit is a direct operational model of activation with a resistive load. The second circuit has a driver that protects and regulates the current in the base of the IGBT to avoid losses and high currents that lead to high temperatures and can cause damage to the IGBT. Likewise, this one has a resistive load. The main components of the test bench are the IGBTs with commercial reference IRG4BC30KDPBF, the reference driver HCPL-316J for each IGBT, four driver modules, one for each IGBT, four thin film PT100 2 mm × 10 mm, four variable resistive loads of 10 Ω  25 W for each IGBT, and a ceramic heater 10 cm × 10 cm with a range of 5°C to 540°C. Figure4 shows a complete scheme of the assembly created for the test bench.Figure 4
Scheme of the test bench.The basic driver circuit was based on the circuit presented in [15] that allows stress aging tests using thermal cycling (TC) and hot carrier injection (HCI).The TC is strongly associated with failure by degradation and removal of welding. The HCI is another form of accelerated aging. This aging mechanism can be performed by applying high voltages at the gate of the IGBT or can also be produced by magnetic fields.This circuit uses aV
C
C
=
10 V, R
C
=
10
Ω
↑, R
G
=
100 Ω, I
C
E
=
5 A. The second circuit works as inverter in industrial installations for motor control or power generating systems. This driver circuit allows precision in the control signal at the IGBT gate. For aging tests using the technique of thermal cycling, it is necessary to limit the current out of the driver; therefore,(30)
R
G
m
i
n
=
V
C
C
2
-
V
O
H
I
O
U
T
/
650
μ
A
-
V
O
L
+
V
E
E
I
O
L
/
p
e
a
k
.The maximum current driver isI
O
L
/
p
e
a
k
=
2.5 A, the maximum switching voltage is V
C
C
2
=
15 V, and V
O
H
=
1.2 V according to the manufacturer’s data sheet. Using the low voltage output maximum V
O
L
M
A
X
=
0.5 V (manufacturer’s data sheet), it has a R
G
(
m
i
n
)
=
5.3 Ω. R
G modifies the voltage slope V
G in the t
o
n and t
o
f
f. If R
G is of greater value the transition in t
o
n and t
o
f
f is slower. Therefore we have to employ small values for R
G. The maximum switching frequency is determined by(31)
f
m
a
x
=
1
t
o
n
+
t
o
f
f
,where(32)
t
o
n
=
t
d
+
t
r
,
t
o
f
f
=
t
s
+
t
f
.Likewise, total dissipated power is given by(33)
P
T
=
P
I
+
P
O
,where P
I is the maximum input power dissipated, limited by P
I
<
150 mW. P
O is the maximum output power dissipated, limited by P
O
<
600 mW.Consider(34)
P
I
=
V
C
C
1
·
I
C
C
1
,
P
O
=
I
C
C
2
·
V
C
C
2
-
V
E
E
+
E
S
W
·
f
S
W
,where I
C
C
2, V
C
C
2, and V
E
E, are given by the manufacturer of the driver selected as our circuit. f
S
W is the maximum switching frequency of the driver and E
S
W is the power dissipated in a resistive load switching defined by(35)
E
S
W
=
V
C
C
2
·
I
C
m
a
x
6
·
t
f
.Knowing thatI
C
m
a
x
=
V
C
C
2
/
R
C
m
i
n, take a R
C
m
i
n
=
5 Ω for some aging tests as electrical overstress (EO) and TC methods; then I
C
m
a
x
=
3 A. With these data we obtain E
S
W
=
0.75 μJ. Finally solving (34) and comparing with the maximum input and output values of power dissipated, P
I
=
5 V · 16.5 μA = 82.5 mW  < 150 mW, P
O
=
5.5 mA · (
15
-
0
)
+
0.75 μJ · 5 kHz = 86.25 mW < 600 mW.Figure5 shows the driver circuit for each IGBT.Figure 5
IGBT driver circuit for aging and IFs analysis.In this case the maximum power dissipation is not exceeded according to the more demanding tests performed in our test bench.Figure6 shows the task execution blocks, interconnected to the data acquisition card and the test bench. Figure 7 shows the graphical user interface for fault diagnosis in the IGBTs test bench. Each red number designs information or task panel:(1)
start/finish test;
(2)
test mode, switching frequency, and gate voltage;
(3)
input voltage signal;
(4)
measured gate voltage;
(5)
collector current (by shunt effect);
(6)
switching counter;
(7)
temperature display;
(8)
temperature zoom in;
(9)
collector current standard deviation;
(10)
type 1 and 2 faults switching counter.Figure 6
Software platform for diagnosis.Figure 7
Diagnosis software environment for IGBTs in labview.Figure8 shows in blue IGBT 22 failure in short circuit with a load short circuit fault current of 1.4 A.Figure 8
Short circuit fault current in IGBT 22.


### 4.2. Results

In the IGBT fault-free, the first thing we get is the performance curveI
C
E versus V
C
E for several new IGBTs. Curve I
-
V is commonly presented to show the performance of IGBts (IGBT-IRG4BC30KDPBF).Figure9 shows in graph (a) the behavior of the current versus the collector voltage for a 7 V fixed value of the gate voltage. It can be seen in IGBTs 15 to 19 that the inclination angle of the curve β
>
45
° remains almost constant regardless of the initial resistive load (graphical detail (b)). Aging of IBGTs modifies I
C
E-V
C
E curves as it can be seen in Figure 10(b).Figure 9
Condition monitoring without driver, for TC technique and load for five new driver-controlled IGBTs.
(a)
(b)Figure 10
Condition monitoring without driver, for TC technique and loadR
C
=
5
Ω.
(a)
(b)In addition, it is presented as a morphological analysis and chemical analysis of some selected samples to determine the compounds of the IGBTs.In this case the tests were performed at 4 IGBTs per sample. Each IGBT is carried out the algorithm for detection of IFs. In total 64 IGBTs are analyzed for different types of stress. Most tests were performed by TC and by load. We selected a test to give the best results in this case with the following characteristics: IGBT surface temperature of250
°
C, switching frequency of 500 Hz, gate voltage of  7 V,   and load voltage of 10 V. Finally a condition monitoring by loading with R
=
5
Ω.Figure11 shows the open circuit fault f
1 better than the other test due to the intensity of the test. The graph (b) shows the initial faults and from hour 16 the intermittent faults due to wearing-out of the IGBT. At approximately 23.5 hours occurs the abrupt fault. The graph (a) shows the intensity of the switching and that the last fault f
1 was detected in switching 198000.Figure 11
f
1 fault type, IGBT open circuit. (a) Number of switching where faults occur. (b) Faults occurring every half hour.
(a)
(b)Detail (a) of graph (a) in Figure12 shows small short circuit IF. From f
2 fault number 20 onwards the IGBT only fails in short circuit leading to a short circuit permanent failure. Graph (b) in Figure 12 shows the initial short circuit faults and the f
2 wearing-out faults during the last 30 minutes.Figure 12
f
2 fault type, IGBT open circuit. (a) Number of switching where faults occur. (b) Faults occurring every half hour.
(a)
(b)Figure9 shows the performance curve I
C
E versus V
C
E in order to see the aging curve. The curves represent the beginning of the normal curve, but the curve at hour 22 shows the wear on the IGBT. The detail (c) of the graph (b) shows that the state of the IGBT tends to open circuit as seen in the IFs shown in Figure 11. The end of the IGBTs life by short circuit at the 43rd hour of operation can be seen in the detail (d) of the graph (a).Completing this IFs analysis we proceeded with the SEM/EDS analysis to the samples. This analysis corroborates the morphological and physical changes appreciated in the IGBTs structure. SEM analysis in Figure13 shows an almost union separation and a grain size quite appreciable. Although this qualitative information is not very valuable, the semiquantitative information of EDS clearly shows that the compounds of silicon, copper, and tin are increased in the union. This increase is directly related to the test type, intensity, and hours of operation. While stress by TC and by load increases, the amount of these compounds increases too. These tests were conducted at 700 μm.Figure 13
Images of SEM/EDS at the junction of the IGBT.SEM/EDS analysis is also applied to the gate union in the IGBTs. In this case it was applied 600μm testing. Figure 14 shows that deformations are very remarkable. Analyzing the results we observed in EDS that silicon and oxygen increase with the aggressiveness of the tests and copper and tin decreased in the same proportion.Figure 14
Images of SEM/EDS at the junction of the IGBT gate.


## 4.1. Hardware Implementation

The test bench is based on two test circuits. The first circuit is a direct operational model of activation with a resistive load. The second circuit has a driver that protects and regulates the current in the base of the IGBT to avoid losses and high currents that lead to high temperatures and can cause damage to the IGBT. Likewise, this one has a resistive load. The main components of the test bench are the IGBTs with commercial reference IRG4BC30KDPBF, the reference driver HCPL-316J for each IGBT, four driver modules, one for each IGBT, four thin film PT100 2 mm × 10 mm, four variable resistive loads of 10 Ω  25 W for each IGBT, and a ceramic heater 10 cm × 10 cm with a range of 5°C to 540°C. Figure4 shows a complete scheme of the assembly created for the test bench.Figure 4
Scheme of the test bench.The basic driver circuit was based on the circuit presented in [15] that allows stress aging tests using thermal cycling (TC) and hot carrier injection (HCI).The TC is strongly associated with failure by degradation and removal of welding. The HCI is another form of accelerated aging. This aging mechanism can be performed by applying high voltages at the gate of the IGBT or can also be produced by magnetic fields.This circuit uses aV
C
C
=
10 V, R
C
=
10
Ω
↑, R
G
=
100 Ω, I
C
E
=
5 A. The second circuit works as inverter in industrial installations for motor control or power generating systems. This driver circuit allows precision in the control signal at the IGBT gate. For aging tests using the technique of thermal cycling, it is necessary to limit the current out of the driver; therefore,(30)
R
G
m
i
n
=
V
C
C
2
-
V
O
H
I
O
U
T
/
650
μ
A
-
V
O
L
+
V
E
E
I
O
L
/
p
e
a
k
.The maximum current driver isI
O
L
/
p
e
a
k
=
2.5 A, the maximum switching voltage is V
C
C
2
=
15 V, and V
O
H
=
1.2 V according to the manufacturer’s data sheet. Using the low voltage output maximum V
O
L
M
A
X
=
0.5 V (manufacturer’s data sheet), it has a R
G
(
m
i
n
)
=
5.3 Ω. R
G modifies the voltage slope V
G in the t
o
n and t
o
f
f. If R
G is of greater value the transition in t
o
n and t
o
f
f is slower. Therefore we have to employ small values for R
G. The maximum switching frequency is determined by(31)
f
m
a
x
=
1
t
o
n
+
t
o
f
f
,where(32)
t
o
n
=
t
d
+
t
r
,
t
o
f
f
=
t
s
+
t
f
.Likewise, total dissipated power is given by(33)
P
T
=
P
I
+
P
O
,where P
I is the maximum input power dissipated, limited by P
I
<
150 mW. P
O is the maximum output power dissipated, limited by P
O
<
600 mW.Consider(34)
P
I
=
V
C
C
1
·
I
C
C
1
,
P
O
=
I
C
C
2
·
V
C
C
2
-
V
E
E
+
E
S
W
·
f
S
W
,where I
C
C
2, V
C
C
2, and V
E
E, are given by the manufacturer of the driver selected as our circuit. f
S
W is the maximum switching frequency of the driver and E
S
W is the power dissipated in a resistive load switching defined by(35)
E
S
W
=
V
C
C
2
·
I
C
m
a
x
6
·
t
f
.Knowing thatI
C
m
a
x
=
V
C
C
2
/
R
C
m
i
n, take a R
C
m
i
n
=
5 Ω for some aging tests as electrical overstress (EO) and TC methods; then I
C
m
a
x
=
3 A. With these data we obtain E
S
W
=
0.75 μJ. Finally solving (34) and comparing with the maximum input and output values of power dissipated, P
I
=
5 V · 16.5 μA = 82.5 mW  < 150 mW, P
O
=
5.5 mA · (
15
-
0
)
+
0.75 μJ · 5 kHz = 86.25 mW < 600 mW.Figure5 shows the driver circuit for each IGBT.Figure 5
IGBT driver circuit for aging and IFs analysis.In this case the maximum power dissipation is not exceeded according to the more demanding tests performed in our test bench.Figure6 shows the task execution blocks, interconnected to the data acquisition card and the test bench. Figure 7 shows the graphical user interface for fault diagnosis in the IGBTs test bench. Each red number designs information or task panel:(1)
start/finish test;
(2)
test mode, switching frequency, and gate voltage;
(3)
input voltage signal;
(4)
measured gate voltage;
(5)
collector current (by shunt effect);
(6)
switching counter;
(7)
temperature display;
(8)
temperature zoom in;
(9)
collector current standard deviation;
(10)
type 1 and 2 faults switching counter.Figure 6
Software platform for diagnosis.Figure 7
Diagnosis software environment for IGBTs in labview.Figure8 shows in blue IGBT 22 failure in short circuit with a load short circuit fault current of 1.4 A.Figure 8
Short circuit fault current in IGBT 22.


## 4.2. Results

In the IGBT fault-free, the first thing we get is the performance curveI
C
E versus V
C
E for several new IGBTs. Curve I
-
V is commonly presented to show the performance of IGBts (IGBT-IRG4BC30KDPBF).Figure9 shows in graph (a) the behavior of the current versus the collector voltage for a 7 V fixed value of the gate voltage. It can be seen in IGBTs 15 to 19 that the inclination angle of the curve β
>
45
° remains almost constant regardless of the initial resistive load (graphical detail (b)). Aging of IBGTs modifies I
C
E-V
C
E curves as it can be seen in Figure 10(b).Figure 9
Condition monitoring without driver, for TC technique and load for five new driver-controlled IGBTs.
(a)
(b)Figure 10
Condition monitoring without driver, for TC technique and loadR
C
=
5
Ω.
(a)
(b)In addition, it is presented as a morphological analysis and chemical analysis of some selected samples to determine the compounds of the IGBTs.In this case the tests were performed at 4 IGBTs per sample. Each IGBT is carried out the algorithm for detection of IFs. In total 64 IGBTs are analyzed for different types of stress. Most tests were performed by TC and by load. We selected a test to give the best results in this case with the following characteristics: IGBT surface temperature of250
°
C, switching frequency of 500 Hz, gate voltage of  7 V,   and load voltage of 10 V. Finally a condition monitoring by loading with R
=
5
Ω.Figure11 shows the open circuit fault f
1 better than the other test due to the intensity of the test. The graph (b) shows the initial faults and from hour 16 the intermittent faults due to wearing-out of the IGBT. At approximately 23.5 hours occurs the abrupt fault. The graph (a) shows the intensity of the switching and that the last fault f
1 was detected in switching 198000.Figure 11
f
1 fault type, IGBT open circuit. (a) Number of switching where faults occur. (b) Faults occurring every half hour.
(a)
(b)Detail (a) of graph (a) in Figure12 shows small short circuit IF. From f
2 fault number 20 onwards the IGBT only fails in short circuit leading to a short circuit permanent failure. Graph (b) in Figure 12 shows the initial short circuit faults and the f
2 wearing-out faults during the last 30 minutes.Figure 12
f
2 fault type, IGBT open circuit. (a) Number of switching where faults occur. (b) Faults occurring every half hour.
(a)
(b)Figure9 shows the performance curve I
C
E versus V
C
E in order to see the aging curve. The curves represent the beginning of the normal curve, but the curve at hour 22 shows the wear on the IGBT. The detail (c) of the graph (b) shows that the state of the IGBT tends to open circuit as seen in the IFs shown in Figure 11. The end of the IGBTs life by short circuit at the 43rd hour of operation can be seen in the detail (d) of the graph (a).Completing this IFs analysis we proceeded with the SEM/EDS analysis to the samples. This analysis corroborates the morphological and physical changes appreciated in the IGBTs structure. SEM analysis in Figure13 shows an almost union separation and a grain size quite appreciable. Although this qualitative information is not very valuable, the semiquantitative information of EDS clearly shows that the compounds of silicon, copper, and tin are increased in the union. This increase is directly related to the test type, intensity, and hours of operation. While stress by TC and by load increases, the amount of these compounds increases too. These tests were conducted at 700 μm.Figure 13
Images of SEM/EDS at the junction of the IGBT.SEM/EDS analysis is also applied to the gate union in the IGBTs. In this case it was applied 600μm testing. Figure 14 shows that deformations are very remarkable. Analyzing the results we observed in EDS that silicon and oxygen increase with the aggressiveness of the tests and copper and tin decreased in the same proportion.Figure 14
Images of SEM/EDS at the junction of the IGBT gate.


## 5. Conclusions

Typical electronic devices such as IGBTs have a type B failure characteristic with an infant mortality followed by a constant or slowly increasing failure probability; therefore, they have no an identifiable wearing-out age. So an age limit is not applicable normally. The major contribution of our work is the inclusion of intermittent faults in the developed fault diagnosis model. Intermittent faults can be used as precursor symptoms of identifiable wearing-out age permanent failures in order to apply preventive or predictive maintenance in the electric and electronic devices. This paper shows the validity of this kind of intermittent fault diagnosis for IGBTs.We have used models based in the Latent Nestling Method and HCPN. The dynamics of HCPN allow for the representation of transitions between transitory faults and fault-free states including quantitative measures.Some conclusions can be drawn from the stress tests. The IGBTs condition and fault mode depend on the experimental procedure and stress level applied in the tests. Condition 1 of 10 Omh/230°C/500 Hz had hardly any effect in the aging process of the components leading to no fault. Condition 2 of 5 Omh/250°C/500 Hz produced open circuit intermittent faults leading to short circuit permanent failures. Our aging hypothesis has been confirmed by morphological and chemical analysis (SEM/EDS) carried out on the failed IGBTs.



---

*Source: 130790-2015-09-16.xml*