# Sliding Mode Controller-Based BFCL for Fault Ride-Through Performance Enhancement of DFIG-Based Wind Turbines

Authors: Mehdi Firouzi; Mojtaba Nasiri; Saleh Mobayen; G. B. Gharehpetian
Journal: Complexity
 (2020)

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## Abstract

The fault ride-through (FRT) capability and fault current issues are the main challenges in doubly fed induction generator- (DFIG-) based wind turbines (WTs). Application of the bridge-type fault current limiter (BFCL) was recognized as a promising solution to cope with these challenges. This paper proposes a nonlinear sliding mode controller (SMC) for the BFCL to enhance the FRT performance of the DFIG-based WT. This controller has robust performance in unpredicted voltage sag level and nonlinear features. Theoretical discussions, power circuit, and nonlinear control consideration of the SMC-based BFCL are conducted, and then, its performance is verified through time-domain simulations in the PSCAD/EMTDC environment. To reduce the chattering phenomenon and decrease the reaching time, it used the exponential reaching law (ERL) for designed SMC. Also, the SMC-based BFCL performance is compared with the conventional and PI controller-based BFCL for both symmetrical and asymmetrical short-circuit faults. Simulation results reveal that the SMC-based BFCL provides better performance compared with the conventional and PI controller-based BFCL to enhance the FRT.


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## Body

## 1. Introduction

Due to the increment of energy demand and depletion of fossil fuels, the demand for electric power generations from renewable energy resources (RESs) is gradually growing [1, 2]. The electric power generation from wind energy is growing so quickly, which can be mostly credited to DFIG-based wind turbines (WTs) due to some advantages such as using partial converter ratings (25–30%) of the nominal-rated wind generator, decoupled active and reactive power control, variable speed operation, low cost, and weight [3]. However, under grid fault conditions, the stator current increases due to the direct connection of the DFIG stator windings to the grid. It results in the transient rotor overcurrent and DC-link overvoltage due to magnetically coupling of the stator and rotor circuit. This may lead to damage in the rotor-side converter (RSC) of the DFIG and disconnecting from the grid [4, 5]. This contrasts with the fault ride-through (FRT) requirement. This requirement states that the WTs must stay connected when the connecting point voltage remains above limit line 1, as shown Figure 1. Also, in the above limit line 2, all WTs should be able to experience a fault without disconnection [6].Figure 1
LVRT curve of the E.ON grid code.In the literature, several approaches including software [7–12] and hardware [13–32] methods have been proposed and documented. The software approaches such as robust control [7], virtual damping flux-based control [8], inductance-emulating control [9], scaled current tracking control [10], and sliding mode control [11, 12] are based on the modification of the RSC control system, which has low cost. They can satisfy the FRT requirements under low voltage sag but cannot guarantee the FRT under severe voltage sag and limit fault current. Therefore, it is necessary to apply hardware approaches to meet the FRT requirements under severe voltage sag [13, 14].In the literature, several hardware schemes such as application of the static synchronous compensator (STATCOM) [15], dynamic voltage restorer (DVR) [16, 17], unified interphase power controller (UIPC) [18], series dynamic resistor (SDR) [19, 20], energy storage system (ESS) [21], and fault current limiters (FCLs) [22–33] have been reported and documented. Since the most common cause of voltage drop is short-circuit fault in the downstream of the grid, many researchers are currently studying fault current mitigation techniques to reduce the voltage sag and enhance the WT FRT performance [22–24]. From this perspective, the applications of FCLs are getting more attention to meet the FRT requirements under voltage sag conditions [22–33]. Regarding this background, some studies focus on superconducting-type FCLs (SFCLs) [24–27] and bridge-type FCLs (BFCLs) [28–33]. In [24, 25], the application of the resistive-type SFCL has been suggested for FRT performance enhancement of the DFIG-based WT. In [24], scholars proposed the resistive-type SFCL in the DFIG rotor circuit to mitigate the RSC transient overcurrent and the DC-link overvoltage to meet the FRT. In [26, 27], the active-type SFCL and a flux coupling-type SFCL are proposed to enhance the DFIG FRT performance under grid fault condition. The research results confirm that SFCLs offer a promising solution to meet the FRT requirements of the DFIGs. However, they require high construction cost.In [28], the BFCL with a discharging resistor in the DC side is used to enhance the FRT performance for the first time. In [29, 30], scholars have changed the BFCL configuration by inserting the discharging resistor in the AC side of the BFCL as the limiting impedance to enhance the FRT performance of the DFIG. From this view, BFCLs with different limiting impedances from the ones used in [28] have been proposed. In [31], a parallel resonance circuit is used as the limiting impedance instead of the discharging resistor to enhance the FRT performance of the DFIG. Kartijkolaie et al. and Firouzi and Gharehpetian [32, 33] proposed a capacitor as the limiting impedance to provide the reactive power for supporting the DFIG terminal voltage under fault condition.In all of them, the BFCL inserts the limiting impedance in the fault path to reduce the voltage sag at the coupling point voltage for FRT enhancement under fault conditions. However, the power system has dynamic nonlinear characteristics, especially under fault conditions. Furthermore, the connection of DFIG-based WTs by the nonlinear power electronic converters makes it more nonlinear [17]. Therefore, the integration of a nonlinear controller to the BFCL instead of the conventional linear controllers can enhance the FRT performance of the DFIG under fault conditions. Considering this matter, this paper presents a sliding mode controller- (SMC-) based BFCL to enhance the FRT performance of the DFIG. To achieve this, a nonlinear SMC is designed and implemented to the BFCL to enhance the FRT response of the DFIG under grid fault condition. The efficiency of the SMC-based BFCL is verified by time-domain simulations in the PSCAD/EMTDC software environment. Also, the FRT performance of the SMC-based BFCL is compared with the conventional and PI controller-based BFCL under both symmetrical and asymmetrical short-circuit faults.


## 2. DFIG-Based Wind Turbine Model

Figure2(a) shows the schematic diagram of the DFIG-based wind turbine. The wind turbine, drive train, generator model, and its controller are the main parts of the DFIG-based WT and are modelled as follows.


### 2.1. Aerodynamic Modeling of the Wind Turbine

There are two wind turbine models in the master library of PSCAD/EMTDC software. In this study, the mode 2 wind turbine model is used. In this model, the captured mechanical power (Pm) from the conversed wind power is expressed by the following equation [34]:(1)Pm=0.5πρR2Cpλ,βVw,where ρ, R, and Vw represent the air density, radius of blades, and wind speed, respectively. Cp is the power coefficient and is expressed by(2)Cpλ,β=0.22116λc−0.4β−5e−12.5λc,(3)λc=11/λ+0.08β−0.035/β3−1,where λand β are the tip speed ratio and pitch angle, respectively. Also, the drive train model used in this study is based on the commonly two-mass model [35] as demonstrated in Figure 2(b), which is described by the following:(4)ωg˙ωt˙δtg˙=Dtg2Hg−Dtg2HgKtg2HgDtg2Ht−Dtg2Ht−Ktg2Ht−110ωgωtδtg+−12Hg00012Ht0000TgTt0,where Tt and Tg are the mechanical turbine and electromagnetic generator torque, respectively, Ht and Hg are the equivalent turbine-blade and the generator inertia, respectively, ωt and ωg are the turbine and the generator angular speed, respectively, and Ktg, Dtg, and δtg are the shaft stiffness, the damping constant, and the angular displacement between two ends of the shaft, respectively [34, 35].Figure 2
(a) Schematic diagram of the DFIG-based wind turbine, (b) two-mass drive train system, and (c) equivalent power circuit of the DFIG and its controller.
(a)(b)(c)


### 2.2. DFIG Model and Control System

As demonstrated in Figure2(a), the DFIG consists of the wounded rotor induction generator (WRIG), the rotor-side converter (RSC), DC link, and grid-side converter (GSC). Considering the equivalent circuit of the DFIG as depicted in Figure 2(c) and using the dq synchronous reference frame, the d-q components of the voltage and flux equations of the DFIG are expressed as follows [7]:(5)Vdqs=Rsidqs+dλdqsdt−ωsλdqs,(6)Vdqr=Rriqrdqr+dλdqrdt−ωs−ωrλdqr,(7)λdqs=Lsidqs+Lmidqs,(8)λdqr=Lsidqr+Lmidqr,where Ls = LsLm/(Ls + Lm) and Lr = LrLm/(Lr + Lm). idqs and idqr are the d-q components of the stator and rotor currents. ωs and ωr are the supply and rotor angular frequencies, respectively. Also, the GSC and DC link dynamic equations are expressed as follows:(9)Vdqs=Vdqg+Rgidqg+Lgdλdqgdt+ωsLgidqg,(10)Vdcidc=Pg−Pr−Ploss.In this case,Pg and Qg are(11)Pg=32Vqgiqg+Vdgidg,(12)Pr=32Vqriqr+Vdridr.In addition, the active and reactive output power of the DFIG is defined as follows:(13)PS=32Vqsiqs+Vdsids=−32LmLSVqsiqr,(14)QS=32Vqsids−Vdsiqs=32LmLSVqsims−idr.Figure2(c) demonstrates the control system of the DFIG under steady-state condition. The main objective of the RSC is controlling the output active power (Ps) and reactive power (Qs) by regulating q- and d-axis components of the rotor currents (i.e., iqr and idr), respectively. To achieve this capability, the GSC regulates the DC link and coupling point voltage in the reference values by controlling the q- and d-axis components of the stator currents (i.e., iqs and ids), respectively.


## 2.1. Aerodynamic Modeling of the Wind Turbine

There are two wind turbine models in the master library of PSCAD/EMTDC software. In this study, the mode 2 wind turbine model is used. In this model, the captured mechanical power (Pm) from the conversed wind power is expressed by the following equation [34]:(1)Pm=0.5πρR2Cpλ,βVw,where ρ, R, and Vw represent the air density, radius of blades, and wind speed, respectively. Cp is the power coefficient and is expressed by(2)Cpλ,β=0.22116λc−0.4β−5e−12.5λc,(3)λc=11/λ+0.08β−0.035/β3−1,where λand β are the tip speed ratio and pitch angle, respectively. Also, the drive train model used in this study is based on the commonly two-mass model [35] as demonstrated in Figure 2(b), which is described by the following:(4)ωg˙ωt˙δtg˙=Dtg2Hg−Dtg2HgKtg2HgDtg2Ht−Dtg2Ht−Ktg2Ht−110ωgωtδtg+−12Hg00012Ht0000TgTt0,where Tt and Tg are the mechanical turbine and electromagnetic generator torque, respectively, Ht and Hg are the equivalent turbine-blade and the generator inertia, respectively, ωt and ωg are the turbine and the generator angular speed, respectively, and Ktg, Dtg, and δtg are the shaft stiffness, the damping constant, and the angular displacement between two ends of the shaft, respectively [34, 35].Figure 2
(a) Schematic diagram of the DFIG-based wind turbine, (b) two-mass drive train system, and (c) equivalent power circuit of the DFIG and its controller.
(a)(b)(c)


## 2.2. DFIG Model and Control System

As demonstrated in Figure2(a), the DFIG consists of the wounded rotor induction generator (WRIG), the rotor-side converter (RSC), DC link, and grid-side converter (GSC). Considering the equivalent circuit of the DFIG as depicted in Figure 2(c) and using the dq synchronous reference frame, the d-q components of the voltage and flux equations of the DFIG are expressed as follows [7]:(5)Vdqs=Rsidqs+dλdqsdt−ωsλdqs,(6)Vdqr=Rriqrdqr+dλdqrdt−ωs−ωrλdqr,(7)λdqs=Lsidqs+Lmidqs,(8)λdqr=Lsidqr+Lmidqr,where Ls = LsLm/(Ls + Lm) and Lr = LrLm/(Lr + Lm). idqs and idqr are the d-q components of the stator and rotor currents. ωs and ωr are the supply and rotor angular frequencies, respectively. Also, the GSC and DC link dynamic equations are expressed as follows:(9)Vdqs=Vdqg+Rgidqg+Lgdλdqgdt+ωsLgidqg,(10)Vdcidc=Pg−Pr−Ploss.In this case,Pg and Qg are(11)Pg=32Vqgiqg+Vdgidg,(12)Pr=32Vqriqr+Vdridr.In addition, the active and reactive output power of the DFIG is defined as follows:(13)PS=32Vqsiqs+Vdsids=−32LmLSVqsiqr,(14)QS=32Vqsids−Vdsiqs=32LmLSVqsims−idr.Figure2(c) demonstrates the control system of the DFIG under steady-state condition. The main objective of the RSC is controlling the output active power (Ps) and reactive power (Qs) by regulating q- and d-axis components of the rotor currents (i.e., iqr and idr), respectively. To achieve this capability, the GSC regulates the DC link and coupling point voltage in the reference values by controlling the q- and d-axis components of the stator currents (i.e., iqs and ids), respectively.


## 3. SMC-Based BFCL

In [28], the application of the BFCL is proposed to enhance the FRT performance of the wind turbine for the first time. In this structure, the limiting resistor is configured in the DC side of the BFCL. It can control the DC reactor current to regulate the PCC voltage. In this paper, a SMC is implemented to the BFCL to regulate the terminal voltage at the determined value for different voltage sag levels by controlling the DC reactor current. The power circuit, principle operation, and designing of SMC for the BFCL are described as follows.


### 3.1. BFCL Power Circuit

The power circuit of the BFCL is illustrated in Figure3. It includes the following elements:(1)
A three-phase bridge rectifier including diodesD1–D6(2)
An IGBT switch, which is represented byT to switch the limiting resistor(3)
A DC reactorLD to limit the rate of increasing of fault current and di/dt(4)
A limiting resistor (R)(5)
Three single-phase series coupling transformers (Ta, Tb, and Tc)Figure 3
(a) Power circuit of the BFCL, (b) BFCL performance under fault condition, and (c) equivalent circuit of the BFCL under normal and fault operation modes.
(a)(b)(c)


### 3.2. Principle Operation of the BFCL

Based on the situation of the IGBT switch, two paths, low impedance path (LIP) and high impedance path (HIP), are provided to carry the normal and fault operation mode currents. Figure3(b) demonstrates the line and DC reactor currents under normal and fault operation modes. The LIP consists of LD-rD-T path to carry the normal operation mode current, and the HIP consists of LD-rD-R path to carry the fault operation mode current. Under the normal operation mode (t < t0), the control system of the BFCL closes T. The line current (iL) converts to DC current (id) and flows through the LIP. Figure 3(c) demonstrates the DC reactor current path in this mode. In this condition, the BFCL generates some power losses and voltage drop due to the BFCL switches and DC reactor resistance, which are negligible. When a fault occurs, the line current and subsequently the DC reactor current start to increase. Figure 3(c) demonstrates the DC reactor current path in this mode (t0 < t < t1). When the DC reactor current reaches to i1, the control system of the BFCL opens T to insert the limiting resistor in the fault path. In this condition (t > t1), id flows through the HIP. Therefore, id and subsequently iL are limited under fault condition [36–39].


### 3.3. PI and Conventional Controller-Based BFCL

In the conventional control approach of the BFCL, the PCC voltage is used as a control signal. Figure4(a) demonstrates the conventional control system of the BFCL. Under the steady-state operation of the system VPCC > VTH, T is turned on, and the LIP carries the line current. When VPCC < VTH, T is turned off to force the fault current towards the HIP and limits the fault current.Figure 4
Different control systems of the BFCL: (a) the conventional voltage control, (b) PI control, and (c) SMC control.
(a)(b)(c)Figure4(b) demonstrates the PI control system of the BFCL. In this approach, the PI controller is used to regulate the terminal voltage at the reference value.


### 3.4. Design and Implementation of the SMC to the BFCL

In recent years, nonlinear controllers due to their good performances in parametric uncertainties and unmodeled dynamics are extended. One of the main powerful controllers is SMC which has a robust performance for unmodeled and noisy systems [40–43]. Consider the single input-single output system by the following state equation:(15)x˙=fx+bxu,where x and u are the state variable and system input, respectively. f(x) and b(x) are bounded nonlinear functions of state variables. Let x˜=x−xd be the trajectory error in state x. The time-varying sliding surface for the system is chosen as(16)sx;t=ddt+Λn−1x˜,where Λ is a strictly positive constant and n is the order of the system. By satisfying the following term, the trajectories of the system are remained in the sliding surface:(17)12ddts2≤−μs,where µ is strictly positive. The above equation can be rewritten as follows:(18)ss˙≤0.According to (17), the reaching time will be as follows:(19)treach≤st=0η,where treach is the reaching time. To satisfying (17), generally, s˙ is considered as follows:(20)s˙=−Ksigns,where K is the positive constant. In [42], to decrease the reaching time and the chattering phenomenon in the input controller, the variable gain was used which was known as the exponential reaching law (ERL). Hence, according to Firouzi et al. [43], (16) can be rewritten as(21)s˙=−KDssigns,where(22)Ds=α+1−αe−βs,where 0 < α < 1, 0 < β. Hence, the reaching time will reduce to the following term:(23)treach≤1Kαst=0+1−αβ1−e−βst=0.In order to design the BFCL controller, the average model of the system is used. By using Kirchhoff’s voltage law (KVL) in the DC side of the BFCL circuit, it can be written for each phase the following equation:(24)Vd=RDid+LDi˙d,where id is the reactor DC current, Vd is the DC side voltage. It should be note that the value of RD can be varied by the value of the modulation index (Mi). Hence, Mi can be defined as follows:(25)Mi=RDR.By inserting (25) in (24), (24) can be rewritten as follows:(26)id=1LDVd−MiRid.The sliding surface of the DC-link current of the BFCL is defined as(27)s=idref−id.By taking the time derivative of (27), it becomes(28)s˙=i˙dref−i˙d.To eliminate the tracking error, the sliding surface and time derivative of it must be zero. Hence, it can be written as(29)Mi=Vdi˙drefLDRid−KDssigns.Stability proof: to prove the stability of the controller, (14) should be satisfied. Hence, by using (27)–(29), (14) will be satisfied as follows:(30)−KDssignss≤0.It shows that the designed controller is stable. To provide theT gate signal, the modulation index (Mi) obtained from (29) is compared with the triangular signal. The triangular frequency is set to be 1 kHz as shown in Figure 4(c).


### 3.5. DC Reactor Design

The main purpose of using the DC reactor in the BFCL circuit is limiting the rate of increase of fault current before fault detection time. The cost and inductance of the DC reactor are decisive factors. High value of the DC reactor inductance results in high power losses and cost, which are not acceptable. However, the inductance value of the DC reactor should be sufficient to achieve this purpose. Considering Figure3(c), which presents the equivalent circuit during t0 < t < t1 time, the DC reactor current is approximately given by the following equation:(31)VD=ri+Ldidt,where r = rD and L = LD. Considering (t1-t0) as the necessary time for increasing fault current from i0 to i1 and solving (31), the inductance value of the DC reactor is obtained by the following equation:(32)LD=rDt1−t0lnVD−ri0VD−ri1.VD is the mean value of the source voltage on the DC side of the bridge circuit and is approximately as follows:(33)VD=33AVmπ,where Vm is the magnitude of the source voltage. Furthermore, by determining t1 and i1, the DC reactor inductance is designed.


### 3.6. Limiting Resistance Design

When a fault occurs, the BFCL inserts the limiting resistor (RD) in the fault path to dissipate the excess output active power of the DFIG (PG) during the fault. To make sure the least disturbance reaches to the DFIG during the fault, RD should be sufficient to dissipate the active power transferred by the faulted line. Therefore, the active power dissipated by the BFCL (PD) should be equal with PG during the fault. PD is determined as follows:(34)PD=Vpcc2RD=PG.Using (34), the minimum value of RD can be derived as follows:(35)RD=Vpcc2PG.


## 3.1. BFCL Power Circuit

The power circuit of the BFCL is illustrated in Figure3. It includes the following elements:(1)
A three-phase bridge rectifier including diodesD1–D6(2)
An IGBT switch, which is represented byT to switch the limiting resistor(3)
A DC reactorLD to limit the rate of increasing of fault current and di/dt(4)
A limiting resistor (R)(5)
Three single-phase series coupling transformers (Ta, Tb, and Tc)Figure 3
(a) Power circuit of the BFCL, (b) BFCL performance under fault condition, and (c) equivalent circuit of the BFCL under normal and fault operation modes.
(a)(b)(c)


## 3.2. Principle Operation of the BFCL

Based on the situation of the IGBT switch, two paths, low impedance path (LIP) and high impedance path (HIP), are provided to carry the normal and fault operation mode currents. Figure3(b) demonstrates the line and DC reactor currents under normal and fault operation modes. The LIP consists of LD-rD-T path to carry the normal operation mode current, and the HIP consists of LD-rD-R path to carry the fault operation mode current. Under the normal operation mode (t < t0), the control system of the BFCL closes T. The line current (iL) converts to DC current (id) and flows through the LIP. Figure 3(c) demonstrates the DC reactor current path in this mode. In this condition, the BFCL generates some power losses and voltage drop due to the BFCL switches and DC reactor resistance, which are negligible. When a fault occurs, the line current and subsequently the DC reactor current start to increase. Figure 3(c) demonstrates the DC reactor current path in this mode (t0 < t < t1). When the DC reactor current reaches to i1, the control system of the BFCL opens T to insert the limiting resistor in the fault path. In this condition (t > t1), id flows through the HIP. Therefore, id and subsequently iL are limited under fault condition [36–39].


## 3.3. PI and Conventional Controller-Based BFCL

In the conventional control approach of the BFCL, the PCC voltage is used as a control signal. Figure4(a) demonstrates the conventional control system of the BFCL. Under the steady-state operation of the system VPCC > VTH, T is turned on, and the LIP carries the line current. When VPCC < VTH, T is turned off to force the fault current towards the HIP and limits the fault current.Figure 4
Different control systems of the BFCL: (a) the conventional voltage control, (b) PI control, and (c) SMC control.
(a)(b)(c)Figure4(b) demonstrates the PI control system of the BFCL. In this approach, the PI controller is used to regulate the terminal voltage at the reference value.


## 3.4. Design and Implementation of the SMC to the BFCL

In recent years, nonlinear controllers due to their good performances in parametric uncertainties and unmodeled dynamics are extended. One of the main powerful controllers is SMC which has a robust performance for unmodeled and noisy systems [40–43]. Consider the single input-single output system by the following state equation:(15)x˙=fx+bxu,where x and u are the state variable and system input, respectively. f(x) and b(x) are bounded nonlinear functions of state variables. Let x˜=x−xd be the trajectory error in state x. The time-varying sliding surface for the system is chosen as(16)sx;t=ddt+Λn−1x˜,where Λ is a strictly positive constant and n is the order of the system. By satisfying the following term, the trajectories of the system are remained in the sliding surface:(17)12ddts2≤−μs,where µ is strictly positive. The above equation can be rewritten as follows:(18)ss˙≤0.According to (17), the reaching time will be as follows:(19)treach≤st=0η,where treach is the reaching time. To satisfying (17), generally, s˙ is considered as follows:(20)s˙=−Ksigns,where K is the positive constant. In [42], to decrease the reaching time and the chattering phenomenon in the input controller, the variable gain was used which was known as the exponential reaching law (ERL). Hence, according to Firouzi et al. [43], (16) can be rewritten as(21)s˙=−KDssigns,where(22)Ds=α+1−αe−βs,where 0 < α < 1, 0 < β. Hence, the reaching time will reduce to the following term:(23)treach≤1Kαst=0+1−αβ1−e−βst=0.In order to design the BFCL controller, the average model of the system is used. By using Kirchhoff’s voltage law (KVL) in the DC side of the BFCL circuit, it can be written for each phase the following equation:(24)Vd=RDid+LDi˙d,where id is the reactor DC current, Vd is the DC side voltage. It should be note that the value of RD can be varied by the value of the modulation index (Mi). Hence, Mi can be defined as follows:(25)Mi=RDR.By inserting (25) in (24), (24) can be rewritten as follows:(26)id=1LDVd−MiRid.The sliding surface of the DC-link current of the BFCL is defined as(27)s=idref−id.By taking the time derivative of (27), it becomes(28)s˙=i˙dref−i˙d.To eliminate the tracking error, the sliding surface and time derivative of it must be zero. Hence, it can be written as(29)Mi=Vdi˙drefLDRid−KDssigns.Stability proof: to prove the stability of the controller, (14) should be satisfied. Hence, by using (27)–(29), (14) will be satisfied as follows:(30)−KDssignss≤0.It shows that the designed controller is stable. To provide theT gate signal, the modulation index (Mi) obtained from (29) is compared with the triangular signal. The triangular frequency is set to be 1 kHz as shown in Figure 4(c).


## 3.5. DC Reactor Design

The main purpose of using the DC reactor in the BFCL circuit is limiting the rate of increase of fault current before fault detection time. The cost and inductance of the DC reactor are decisive factors. High value of the DC reactor inductance results in high power losses and cost, which are not acceptable. However, the inductance value of the DC reactor should be sufficient to achieve this purpose. Considering Figure3(c), which presents the equivalent circuit during t0 < t < t1 time, the DC reactor current is approximately given by the following equation:(31)VD=ri+Ldidt,where r = rD and L = LD. Considering (t1-t0) as the necessary time for increasing fault current from i0 to i1 and solving (31), the inductance value of the DC reactor is obtained by the following equation:(32)LD=rDt1−t0lnVD−ri0VD−ri1.VD is the mean value of the source voltage on the DC side of the bridge circuit and is approximately as follows:(33)VD=33AVmπ,where Vm is the magnitude of the source voltage. Furthermore, by determining t1 and i1, the DC reactor inductance is designed.


## 3.6. Limiting Resistance Design

When a fault occurs, the BFCL inserts the limiting resistor (RD) in the fault path to dissipate the excess output active power of the DFIG (PG) during the fault. To make sure the least disturbance reaches to the DFIG during the fault, RD should be sufficient to dissipate the active power transferred by the faulted line. Therefore, the active power dissipated by the BFCL (PD) should be equal with PG during the fault. PD is determined as follows:(34)PD=Vpcc2RD=PG.Using (34), the minimum value of RD can be derived as follows:(35)RD=Vpcc2PG.


## 4. Simulation and Discussion

To verify the proposed SMC-based BFCL performance, the system shown in Figure5 is used. It includes a 2 MW DFIG-based wind turbine, which is connected to the main grid through a step-up 0.7 kV/13.8 kV transformer. Both symmetrical three-line-to-ground (3LG) and asymmetrical single-line-to-ground (SLG) short-circuit faults were applied at the PCC bus to evaluate the capability of the proposed SMC-based BFCL. The simulated system and DFIG parameters are illustrated in Table 1. Both short-circuit faults occur at t = 10s and continue for 150 ms. VT represents the terminal voltage in Figure 5. Simulations were performed for the following cases:Case A: using the conventional-controller BFCLCase B: using the PI-controller BFCLCase C: using the sliding mode controller BFCLFigure 5
Study system.Table 1
Simulated system parameters.
ParametersValueGridGrid voltage13.8 kVGrid frequency50 HzX/R ratio5Induction generatorRated active power2 MWRated voltage690 VRated frequency50 HzInertia constant1 sStator resistance0.0057 ΩStator leakage reactance0.078 ΩRotor resistance0.0159 ΩRotor leakage reactance0.1022 ΩMutual reactance2.434 ΩBFCLDC reactor inductance0.01 HLimiting resistanceR 100 Ω


### 4.1. Symmetrical 3LG Fault Condition

Figure6 demonstrates the performance of the BFCL for three cases under 3LG fault condition. In this condition, the PCC voltage drops to zero, approximately. As demonstrated in Figure 6(a), the BFCL performances in three cases have the same trend in response to severe voltage sag. However, the SMC-controlled BFCL has the lowest voltage sag and oscillation in the fault period. Figure 6(b) demonstrates the DFIG active power for three cases. In cases A and B, the active power drops to 0.8 pu in the fault period, approximately. Also, it is increased to 1.5 pu after fault clearance in case A. However, it has the lowest fluctuation in case C by using the SMC-controlled BFCL. Figure 6(c) demonstrates the DFIG speed under this condition. It demonstrates the least rotor speed deviation for case C. Figure 6(d) demonstrates the DC link voltage of the DFIG under this condition. It can be seen from this figure that the DC link voltage remains constant during and after fault by using the SMC-controlled BFCL.Figure 6
WT response under the 3LG fault: (a) DFIG terminal voltage, (b) DFIG active power, (c) DFIG rotor speed, and (d) DC link voltage.
(a)(b)(c)(d)Figure7 demonstrates the DFIG stator current under this condition. It can be seen from this figure that the fault current is limited in 0.4 pu. In cases B and C, the fault current is 0.5 pu, and they have the same trend. However, the SMC-controlled BFCL has superior performance in both ends of the fault period.Figure 7
DFIG fault current under the 3LG fault: (a) Case A, (b) Case B, and (c) Case C.
(a)(b)(c)


### 4.2. Asymmetrical SLG Fault Condition

Figure8 demonstrates the performance of the BFCL for three cases under 1LG fault condition. As demonstrated in Figure 8(a), the PCC voltage drops to 0.75 pu for this condition. In case A, the terminal voltage of the DFIG is increased to 1.4 pu in the end of the fault period. In case B, the PI control of the BFCL cannot control the terminal voltage at the reference value; however, it remains in acceptable voltage level. In case C, by using the SMC-based BFCL, the terminal voltage is controlled at the reference level by controlling the DC reactor current. Figure 8(b) demonstrates the active power of the DFIG in three cases. As demonstrated in this figure, the active power fluctuation is lowest in the case of using the SMC-based BFCL, which leads to the least rotor speed deviation, as demonstrated in Figure 8(c). Figure 8(d) demonstrates the DC link voltage of the DFIG. It can be seen that the DC link voltage increases to 1.1 pu for scenario A. However, in scenarios B and C, the DC link voltage remains constant.Figure 8
WT response under the 1LG fault: (a) DFIG terminal voltage, (b) DFIG active power, (c) DFIG rotor speed, and (d) DC link voltage.
(a)(b)(c)(d)Figure9 demonstrates the DFIG stator current for three cases under this condition. In case A, the fault current is lower than the per-fault current due to full insertion of the limiting impedance in the fault path. In cases B and C, the fault current is limited in 0.5 pu; however, the SMC-based BFCL has superior performance under fault condition.Figure 9
DFIG fault current under the 1LG fault: (a) Case A, (b) Case B, and (c) Case C.
(a)(b)(c)


## 4.1. Symmetrical 3LG Fault Condition

Figure6 demonstrates the performance of the BFCL for three cases under 3LG fault condition. In this condition, the PCC voltage drops to zero, approximately. As demonstrated in Figure 6(a), the BFCL performances in three cases have the same trend in response to severe voltage sag. However, the SMC-controlled BFCL has the lowest voltage sag and oscillation in the fault period. Figure 6(b) demonstrates the DFIG active power for three cases. In cases A and B, the active power drops to 0.8 pu in the fault period, approximately. Also, it is increased to 1.5 pu after fault clearance in case A. However, it has the lowest fluctuation in case C by using the SMC-controlled BFCL. Figure 6(c) demonstrates the DFIG speed under this condition. It demonstrates the least rotor speed deviation for case C. Figure 6(d) demonstrates the DC link voltage of the DFIG under this condition. It can be seen from this figure that the DC link voltage remains constant during and after fault by using the SMC-controlled BFCL.Figure 6
WT response under the 3LG fault: (a) DFIG terminal voltage, (b) DFIG active power, (c) DFIG rotor speed, and (d) DC link voltage.
(a)(b)(c)(d)Figure7 demonstrates the DFIG stator current under this condition. It can be seen from this figure that the fault current is limited in 0.4 pu. In cases B and C, the fault current is 0.5 pu, and they have the same trend. However, the SMC-controlled BFCL has superior performance in both ends of the fault period.Figure 7
DFIG fault current under the 3LG fault: (a) Case A, (b) Case B, and (c) Case C.
(a)(b)(c)


## 4.2. Asymmetrical SLG Fault Condition

Figure8 demonstrates the performance of the BFCL for three cases under 1LG fault condition. As demonstrated in Figure 8(a), the PCC voltage drops to 0.75 pu for this condition. In case A, the terminal voltage of the DFIG is increased to 1.4 pu in the end of the fault period. In case B, the PI control of the BFCL cannot control the terminal voltage at the reference value; however, it remains in acceptable voltage level. In case C, by using the SMC-based BFCL, the terminal voltage is controlled at the reference level by controlling the DC reactor current. Figure 8(b) demonstrates the active power of the DFIG in three cases. As demonstrated in this figure, the active power fluctuation is lowest in the case of using the SMC-based BFCL, which leads to the least rotor speed deviation, as demonstrated in Figure 8(c). Figure 8(d) demonstrates the DC link voltage of the DFIG. It can be seen that the DC link voltage increases to 1.1 pu for scenario A. However, in scenarios B and C, the DC link voltage remains constant.Figure 8
WT response under the 1LG fault: (a) DFIG terminal voltage, (b) DFIG active power, (c) DFIG rotor speed, and (d) DC link voltage.
(a)(b)(c)(d)Figure9 demonstrates the DFIG stator current for three cases under this condition. In case A, the fault current is lower than the per-fault current due to full insertion of the limiting impedance in the fault path. In cases B and C, the fault current is limited in 0.5 pu; however, the SMC-based BFCL has superior performance under fault condition.Figure 9
DFIG fault current under the 1LG fault: (a) Case A, (b) Case B, and (c) Case C.
(a)(b)(c)


## 5. Conclusions

In this paper, a sliding mode controller has been designed to control the BFCL for enhancing the FRT capability of the DFIG-based wind turbine under severe and low voltage sag levels. The DC reactor current of the BFCL has been considered as a state variable in the SMC to control the DFIG terminal voltage. Also, to show the efficiency of the proposed SMC-based BFCL, its performance has been compared with the PI- and conventional controller-based BFCL. Based on the PSCAD/EMTDC simulation results, the following points are obtained:(i)
By using the SMC-based BFCL, the DFIG terminal voltage is effectively controlled at the reference value at different voltage sag levels. This subject leads to the lowest DFIG speed and active power deviations under voltage sag conditions.(ii)
The SMC-based BFCL limits the transient fault current in both ends of the fault period.(iii)
The SMC has a robust and efficient performance under uncertainty conditions in comparison with the PI and conventional voltage control.



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*Source: 1259539-2020-05-15.xml*