# Two Integrator Loop Filters: Generation Using NAM Expansion and Review

Authors: Ahmed M. Soliman
Journal: Journal of Electrical and Computer Engineering
 (2010)

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## Abstract

Systematic synthesis method to generate a family of two integrator loop filters based on nodal admittance matrix (NAM) expansion is given. Eight equivalent circuits are obtained; six of them are new. Each of the generated circuits uses two grounded capacitors and employs two current conveyors (CCII) or two inverting current conveyors (ICCII) or a combination of both. The NAM expansion is also used to generate eight equivalent grounded passive elements two integrator loop filters using differential voltage current conveyor (DVCC); six of them are new. Changing the input port of excitation, two new families of eight unity gain lowpass filter circuits each using two CCII or ICCII or combination of both or two DVCC are obtained.


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## Body

## 1. Introduction

Recently, a symbolic framework for systematic synthesis of linear active circuits based on nodal admittance matrix (NAM) expansion was presented in [1, 2]. The matrix expansion process begins by introducing blank rows and columns, representing new internal nodes, in the admittance matrix. Then, nullators and norators are used to move the resulting admittance matrix elements to their final locations, properly describing either floating or grounded passive elements. Thus, the final NAM is obtained including finite elements representing passive circuit components.In this framework, nullators and norators [3] that ideally describe active elements in the circuit are used. The nullator and norator are pathological elements that possess ideal characteristics and are specified according to the constraints they impose on their terminal voltages and currents. For the nullator V=I=0, while the norator imposes no constraints on its voltage and current. A nullator-norator pair constitutes a universal active two-port network element called the nullor [3], and hence, nullator and norator are also called nullor elements.Additional pathological elements called mirror elements were introduced in [4, 5] to describe the voltage and current reversing actions. The voltage mirror (VM) is a lossless two-port network element used to represent an ideal voltage reversing action and is described by(1a)V1=-V2,(1b)I1=I2=0.The current mirror (CM) is a two-port network element used to represent an ideal current reversing action and is described by(2a)V1andV2arearbitrary,(2b)I1=I2andtheyarealsoarbitrary.Very recently the systematic synthesis method based on admittance matrix expansion using nullor elements [1, 2] has been extended to accommodate mirror elements [6–8]. This results in a generalized framework encompassing all pathological elements for ideal description of active elements. Accordingly, more alternative realizations are possible and a wide range of active devices can be used in the synthesis.In this paper, the conventional systematic synthesis framework using NAM expansion to synthesize two integrator loop filters using CCII [9] or ICCII [5] or combination of both is given. Eight of such two integrator loop filters are generated, six of them are new. An alternative family of eight two integrator loop filters using two DVCCs with very high input impedance and using grounded passive elements is generated; six of them are new. Additional family of eight lowpass circuits using CCII and ICCII is generated by changing input excitation port.


## 2. NAM Equation of Two Integrator Loop Filters

Figure1 represents the block diagram representation of the two integrator loop filters with two possible sign polarities of the two integrators.Figure 1
Block diagram of the two integrator loop filters.Realizations of type-A two integrator loop filters.
(a)
Circuit A-1(b)
Circuit A-2(c)
Circuit A-3(d)
Circuit A-4The denominatorD(s) of the transfer function in both cases is given by
(3)D(s)=s2+sG1C1+G2G3C1C2.The block diagram shown in Figure1 with the upper sign polarities of the two integrators represents a modified simplified form of the Tow Thomas (TT) circuit with the input resistor taken equal to the feedback resistor from V2to the inverting input of the first operational amplifier (Op Amp) [10–13]. In the modified TT circuit the inverting lossless integrator and the inverter stage are being exchanged in positions [14, 15].It is desirable to generate CCII and ICCII grounded capacitor two integrator loop filters havingD(s) given by (3).Consider the block diagram of Figure1 with the upper signs of the two integrators, and setting VIN=0, the state matrix equation is
(4)[sC1V1sC2V2]=[-G1G3-G20][V1V2].From the above equation and taking the two capacitors to be external elements to the circuit, the admittance matrix defined with ports 1 and 2 as its two ports is obtained as(5)Ii=-sCiVi(i=1,2).From (4) and (5) the admittance matrix Y is given by
(6)Y=[G1-G3G20].The two integrator loop filters represented by the aboveY matrix are referred to as type-A circuits.


## 3. Generation of Type-A Conveyor Circuits

Expanding the above matrix by adding a blank third row and third column, and adding a CM between nodes 1 and 3 in order to move-G3 from the 1, 2 position to 3, 2 position, it follows that
(7)Y=[G100G2000G30]}.Adding a nullator between nodes 2 and 3 in order to moveG3 to the diagonal position 3, 3, it follows that(8)Next a fourth blank row and column are added andG2 is moved to the diagonal position 4, 4 by adding a nullator between nodes 1 and 4 and a norator between nodes 2 and 4 as follows:(9)
The above NAM equation is represented in Figure 2(a) after adding the two capacitors C1 and C2 at nodes 1 and 2, respectively.The circuit is realizable by a CCII+ and a CCII- and the input voltage source is applied to node 5 after disconnecting it from ground.The NAM can also be expanded as follows:(10)Figure2(b) realizes the above equation after adding the two capacitors C1 and C2 at nodes 1 and 2, respectively. The circuit is realizable by a CCII+ and an ICCII+.The NAM can also be expanded as follows:(11)Figure2(c) realizes the above equation after adding the two capacitors C1 and C2 at nodes 1 and 2, respectively. The circuit is realizable by a CCII- and an ICCII-.The NAM can also be expanded as follows:(12)Figure2(d) realizes the above equation after adding the two capacitors C1 and C2 at nodes 1 and 2, respectively. The circuit is realizable by an ICCII- and an ICCII+.The circuits can be realized by the generalized current conveyor circuit shown in Figure3 with the input voltage applied to node N1.Figure 3
The generalized two conveyor two integrator loop filters.Table1 includes the types of the two conveyors used and the polarity of the bandpass and lowpass responses realized in each case. Circuit A-1 has been reported before in [14] and the other three circuits are new.Table 1
Types of conveyors used in the generalized filter of Figure3.
Circuit numberConveyor1Conveyor2BP PolarityLP PolarityFloating PolarityRef.A-1CCII+CCII--+No[14]A-2CCII+ICCII+-+NoNewA-3ICCII-CCII-+-YesNewA-4ICCII-ICCII++-NoNewB-1CCII-CCII+++No[14]B-2CCII-ICCII-++YesNewB-3ICCII+CCII+--NoNewB-4ICCII+ICCII---NoNew


## 4. Generation of Type-B Conveyor Circuits

The block diagram shown in Figure1 with the lower sign polarities of the two integrators represents a simplified form of TT circuit. The simplified TT circuit is obtained by taking the input resistor equal to the feedback resistor from V2 to the inverting input of the first Op Amp.Consider the block diagram of Figure1 with the lower signs of the two integrators, and setting VIN=0, the state matrix equation is given by(13)[sC1V1sC2V2]=[-G1-G3G20][V1V2].From the above equation and taking the two capacitors to be external elements to the circuit, the admittance matrix defined with ports 1 and 2 as its two ports is obtained as(14)Y=[G1G3-G20].The aboveY matrix can be expanded as in the previous section and will result in four new two integrator loop filters classified as type-B circuits. Adding third blank row and column and connecting a nullator between nodes 2 and 3 and a norator between nodes 1 and 3 to move G3  to the diagonal position 3, 3, it follows that(15)Next adding a fourth blank row and column and connecting a nullator between nodes 1, 4 and a CM between nodes 2 and 4 to move the-G2 to the diagonal position 4, 4 with positive sign, it follows that(16)Figure4(a) represents the realization of the above equation after adding the two capacitors at nodes 1 and 2. The circuit includes two nullators, a norator and a CM which are realizable by a CCII- and a CCII+ as given in Table 1.Realizations of type-B two integrator loop filters.
(a)
Circuit B-1(b)
Circuit B-2(c)
Circuit B-3(d)
Circuit B-4Three more new circuits are generated and are shown in Figures4(b), 4(c), and 4(d) and the types of conveyors used are given in Table 1.The transfer functions for each of the eight circuits are given by(17)V1VIN=±sG3/C1s2+sG1/C1+G2G3/C1C2,(18)V2VIN=±G2G3/C1C2s2+sG1/C1+G2G3/C1C2.The bandpass and lowpass polarities for each circuit are shown in Table1. From the above equations, therefore(19)ωο=G2G3C1C2,Q=1G1C1G2G3C2,(20)BPGain(ωο)=G3G1.The magnitude of the DC gain of the lowpass filter is unity.


## 5. Two Integrator Loop Filters Using DVCC

### 5.1. Generation Using Brackets

The NAM expansion introduced in Sections3 and 4 can also be used to generate high input impedance two-stage two integrator loop filter circuits using the DVCC as the basic building block. The single output differential difference current conveyor (DDCC) has been introduced in [16]. The same circuit defined as the DVCC with a balanced output has also been independently introduced in [17].The DVCC with a singleZ+ output is a four-port building block defined by [16, 17]
(21)[VXIY1IY2IZ+]=[01-10000000001000][IXVY1VY2VZ+].It is seen that the DVCC+ includes CCII+ and ICCII+ as special cases. The DVCC with a single Z- output is defined by [17]
(22)[VXIY1IY2IZ-]=[01-1000000000-1000][IXVY1VY2VZ-].It is seen that the DVCC- includes CCII- and ICCII- as special cases.The type-A DVCC-based two integrator loop filter circuits are generated from Figure2 by following the pathological elements between nodes 2 and 3 to determine the Y input of DVCC-1 and then insert input source at the other Y input of DVCC-1. If the pathological element between nodes 2 and 3 is a nullator, then the feedback to DVCC-1 will be to Y1 and input source is applied to Y2 which will represent the additional node in this case. If the pathological element between nodes 2 and 3 is a VM, then the feedback to DVCC-1 will be to Y2 and input source is applied to Y1.The DVCC-2 uses oneY input which is identified from the pathological element between nodes 1 and 4, if it is a nullator, then Y1 will be input node of DVCC-2 and Y2 will be grounded; on the other-hand if it is a VM, then Y2 will be input node of DVCC-2 and Y1 will be grounded.The Z polarities will be determined from the pathological elements between nodes 1, 3 and between nodes 2 and 4 as in the case of CCII and ICCII.For example, in the A-1 circuit a CM is connected between nodes 1 and 3 which implies thatZ+ polarity for the DVCC-1, and a norator is connected between nodes 2 and 4 which implies that Z-polarity for DVCC-2.Figure5 represents the four type-A two DVCC-based two integrator loop filter circuits, and the bandpass and lowpass polarities are given in Table 2. It should be noted that the second stage in each of the four circuits is used as a CCII- or as ICCII+.Table 2
Types of the DVCC used in the two integrator loop filters.
Circuit numberDVCC1DVCC2BP PolarityLP PolarityFloating PolarityRef.A-1DVCC+DVCC--+NoNewA-2DVCC+DVCC+-+NoNewA-3DVCC-DVCC--+YesNewA-4DVCC-DVCC+-+No[13]B-1DVCC-DVCC+++NoNewB-2DVCC-DVCC-++YesNewB-3DVCC+DVCC+++No[16]B-4DVCC+DVCC-++NoNew(a)
Circuit A-1 using two DVCC(b)
Circuit A-2 using two DVCC(c)
Circuit A-3 using two DVCC(d)
Circuit A-4 using two DVCCFigure6 represents the four type-B two DVCC-based two integrator loop filter circuits, and the bandpass and lowpass polarities are given in Table 2.(a)
Circuit B-1 using two DVCC(b)
Circuit B-2 using two DVC(c)
Circuit B-3 using two DVCC(d)
Circuit B-4 using two DVCCIt should be noted that the second stage in each of the four circuits is used as a CCII+ or as ICCII-.The transfer functions for each of the eight DVCC-based two integrator loop filter circuits are the same as given by (17) to (20).It should be noted that the block diagram representing the circuits of Figure5 is the same as that of Figure 1 with upper integrator signs but with a negative sign of the summer input connected to VIN. Similarly the block diagram representing the circuits of Figure 6 is the same as that of Figure 1 with the lower integrator signs but with a negative sign of the summer input connected to VIN.


### 5.2. Generation Using Brackets and Infinity Parameters

The NAM expansion can also be carried out using both the brackets method and the infinity parameters.The infinity parameter representation of the DVCC+ is given by [18](23)XY1Y2XZ+[∞i∞i-∞i-∞i∞i∞i].The infinity parameter representation of the DVCC- is given by [18](24)XY1Y2XZ-[∞i-∞i-∞i∞i∞i-∞i].The brackets are used to realize the second stage of the circuit, and the infinity parameters are used next to realize the first stage.As an example consider the generation of the circuit of Figure5(a). Starting from (6), add two blank rows and columns and then connect a nullator between nodes 1 and 4 and a norator between nodes 2 and 4 to move G2 to the diagonal position 4, 4 as follows:(25)The nullator and norator added to moveG2 are realizable by a CCII- which is realized by the DVCC- with port X connected to G2 and with port Y2connected to ground. Next G1 is connected to port 1 and the capacitors C1 to node 1 and C2 are connected to nodes 1 and 2, respectively.To realize a high-input impedance circuit there must be a row with a zero current; adding a fifth blank row and column results in the following expanded NAM:(26)The infinity parameters movesG3  in a two-step move to the diagonal 3, 3 position as follows:(27)The infinity parameters realizes the first stage DVCC+ with its Y2 as the high-input impedance node 5, Y1 as node 2 and X as node 3 connected to G3   to ground as shown in Figure 5(a).As a second example consider the generation of the circuit of Figure5(c).The NAM can also be expanded as follows:(28)The above equation is realized as shown in Figure5(c) with the first stage as a DVCC- with its Y1 as the high-input impedance node 5 and connected to input, Y2 as node 2, and X as node 3 connected to G3   to ground; the second stage is the same as in Figure 5(a).The type-B DVCC-based two integrator loop filter circuits can also be generated following the same rules mentioned above.


## 5.1. Generation Using Brackets

The NAM expansion introduced in Sections3 and 4 can also be used to generate high input impedance two-stage two integrator loop filter circuits using the DVCC as the basic building block. The single output differential difference current conveyor (DDCC) has been introduced in [16]. The same circuit defined as the DVCC with a balanced output has also been independently introduced in [17].The DVCC with a singleZ+ output is a four-port building block defined by [16, 17]
(21)[VXIY1IY2IZ+]=[01-10000000001000][IXVY1VY2VZ+].It is seen that the DVCC+ includes CCII+ and ICCII+ as special cases. The DVCC with a single Z- output is defined by [17]
(22)[VXIY1IY2IZ-]=[01-1000000000-1000][IXVY1VY2VZ-].It is seen that the DVCC- includes CCII- and ICCII- as special cases.The type-A DVCC-based two integrator loop filter circuits are generated from Figure2 by following the pathological elements between nodes 2 and 3 to determine the Y input of DVCC-1 and then insert input source at the other Y input of DVCC-1. If the pathological element between nodes 2 and 3 is a nullator, then the feedback to DVCC-1 will be to Y1 and input source is applied to Y2 which will represent the additional node in this case. If the pathological element between nodes 2 and 3 is a VM, then the feedback to DVCC-1 will be to Y2 and input source is applied to Y1.The DVCC-2 uses oneY input which is identified from the pathological element between nodes 1 and 4, if it is a nullator, then Y1 will be input node of DVCC-2 and Y2 will be grounded; on the other-hand if it is a VM, then Y2 will be input node of DVCC-2 and Y1 will be grounded.The Z polarities will be determined from the pathological elements between nodes 1, 3 and between nodes 2 and 4 as in the case of CCII and ICCII.For example, in the A-1 circuit a CM is connected between nodes 1 and 3 which implies thatZ+ polarity for the DVCC-1, and a norator is connected between nodes 2 and 4 which implies that Z-polarity for DVCC-2.Figure5 represents the four type-A two DVCC-based two integrator loop filter circuits, and the bandpass and lowpass polarities are given in Table 2. It should be noted that the second stage in each of the four circuits is used as a CCII- or as ICCII+.Table 2
Types of the DVCC used in the two integrator loop filters.
Circuit numberDVCC1DVCC2BP PolarityLP PolarityFloating PolarityRef.A-1DVCC+DVCC--+NoNewA-2DVCC+DVCC+-+NoNewA-3DVCC-DVCC--+YesNewA-4DVCC-DVCC+-+No[13]B-1DVCC-DVCC+++NoNewB-2DVCC-DVCC-++YesNewB-3DVCC+DVCC+++No[16]B-4DVCC+DVCC-++NoNew(a)
Circuit A-1 using two DVCC(b)
Circuit A-2 using two DVCC(c)
Circuit A-3 using two DVCC(d)
Circuit A-4 using two DVCCFigure6 represents the four type-B two DVCC-based two integrator loop filter circuits, and the bandpass and lowpass polarities are given in Table 2.(a)
Circuit B-1 using two DVCC(b)
Circuit B-2 using two DVC(c)
Circuit B-3 using two DVCC(d)
Circuit B-4 using two DVCCIt should be noted that the second stage in each of the four circuits is used as a CCII+ or as ICCII-.The transfer functions for each of the eight DVCC-based two integrator loop filter circuits are the same as given by (17) to (20).It should be noted that the block diagram representing the circuits of Figure5 is the same as that of Figure 1 with upper integrator signs but with a negative sign of the summer input connected to VIN. Similarly the block diagram representing the circuits of Figure 6 is the same as that of Figure 1 with the lower integrator signs but with a negative sign of the summer input connected to VIN.


## 5.2. Generation Using Brackets and Infinity Parameters

The NAM expansion can also be carried out using both the brackets method and the infinity parameters.The infinity parameter representation of the DVCC+ is given by [18](23)XY1Y2XZ+[∞i∞i-∞i-∞i∞i∞i].The infinity parameter representation of the DVCC- is given by [18](24)XY1Y2XZ-[∞i-∞i-∞i∞i∞i-∞i].The brackets are used to realize the second stage of the circuit, and the infinity parameters are used next to realize the first stage.As an example consider the generation of the circuit of Figure5(a). Starting from (6), add two blank rows and columns and then connect a nullator between nodes 1 and 4 and a norator between nodes 2 and 4 to move G2 to the diagonal position 4, 4 as follows:(25)The nullator and norator added to moveG2 are realizable by a CCII- which is realized by the DVCC- with port X connected to G2 and with port Y2connected to ground. Next G1 is connected to port 1 and the capacitors C1 to node 1 and C2 are connected to nodes 1 and 2, respectively.To realize a high-input impedance circuit there must be a row with a zero current; adding a fifth blank row and column results in the following expanded NAM:(26)The infinity parameters movesG3  in a two-step move to the diagonal 3, 3 position as follows:(27)The infinity parameters realizes the first stage DVCC+ with its Y2 as the high-input impedance node 5, Y1 as node 2 and X as node 3 connected to G3   to ground as shown in Figure 5(a).As a second example consider the generation of the circuit of Figure5(c).The NAM can also be expanded as follows:(28)The above equation is realized as shown in Figure5(c) with the first stage as a DVCC- with its Y1 as the high-input impedance node 5 and connected to input, Y2 as node 2, and X as node 3 connected to G3   to ground; the second stage is the same as in Figure 5(a).The type-B DVCC-based two integrator loop filter circuits can also be generated following the same rules mentioned above.


## 6. Generation of New Lowpass Filters

A new family of lowpass filters can be generated from the generalized circuit of Figure3 by injecting the input voltage at node N2 and grounding node N1. The generalized lowpass filter circuit is shown in Figure 7(a) with the same transfer function as given by (18). The magnitude of the DC gain is unity and the polarity is given in Table 3. Eight new alternative realizations that belong to Figure 7(a) according to the conveyors used are given in Table 3. The generalized block diagram of this family of lowpass filters is obtained from Figure 1 by interchanging the two integrator positions [12, 19]. It is worth noting that the circuit numbers three and six have a floating property.Table 3
Types of conveyors used in the lowpass filter of Figure7(a).
CircuitConveyor1Conveyor2LPFloating PolarityNumberPolarity1CCII+CCII-+No2CCII+ICCII+-No3ICCII-CCII-+Yes4ICCII-ICCII+-No5CCII-CCII++No6CCII-ICCII--Yes7ICCII+CCII++No8ICCII+ICCII--No(a)
A generalized two conveyors lowpass filter(b)
Lowpass filter obtained from circuit A-1 in Figure5(a)Similarly eight new DVCC-based lowpass filter circuits can be generated from Figures5 and 6 by changing the input port of excitation. Figure 7(b) represents the new noninverting lowpass filter circuit generated from Figure 5(a). similarly the other seven lowpass filter circuits can be obtained.


## 7. Conclusions

The NAM expansion method using nullor elements and pathological mirrors is used to generate eight grounded capacitor conveyor-based two integrator loop filter circuits. Additional eight grounded passive elements DVCC-based two integrator loop filter circuits are given; six of them are new. The CCII circuits A-1 and B-1 have been reported before in [14]. It is worth noting that circuits A-3 and B-2 have a floating property as shown in Table 1.Additional eight grounded passive elements DVCC-based circuits are given; six of them are new. It is worth noting that circuits A-3 and B-2 have a floating property as shown in Table2.It is worth noting that all the reported circuits whether employing CCII  and ICCII combinations or using two DVCC can be compensated by subtracting the values of the parasitic resistancesRX1 and RX2 from the design values of R3  and R2,respectively. Similarly the parasitic capacitances can be compensated by subtracting the values of CZ1  and CZ2  from the design values of C1 and C2, respectively.A similar circuit to B-1 using two CCII with different port excitations was given in [20]. Other realizations of two integrator loop filter circuits using ICCII were given in [21]. The importance of the VM-CM pathological elements [22] in the generation of the six new two integrator loop filter circuits using CCII or ICCII or combination of both or two DVCC is demonstrated in this review paper.



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