Newsgroup: it.comp.hardware
Titolo: MMX2

Ho letto da qualche arte nel web (o tramite PonitCast) che Intel sta
mettendo a punto le specifiche MMX2 che sareanno implementate nei
futuri processori, ho dato solo un' occhiata di sfuggita e non ricordo
dove. Qualcuno ne sa qualcosa?
<<Vieniquas>> Trust No 1

Giorgio
Certo, fanno un passettino in avanti e noi giu' soldi come polli.........
Ciao Ricy.

posto l' articolo completo reperito su techweb relativo alle MMX2.
Dateci un' occhiata.
SANTA CLARA, Calif. -- In a pair of stealth multimedia maneuvers,
Intel is enhancing its MMX technology. The company is readying a host
of new MMX instructions that will appear in CPUs next year and has
already included a set of little-known performance-boosting registers
in the Pentium II, EE Times has learned.
For engineers and programmers, the improvements aim MMX more squarely
at the sweet spot of mainstream multimedia applications such as 3-D
graphics, video processing, and theater-quality audio. Equally
important, they could remove programmers' lingering concerns about
context switching -- the time lost when a software routine switches
between MMX and floating-point instructions. That issue has dogged the
technology since its debut last year.
Separately, Intel has disclosed what's apparently the first
MMX-related bug. Although the glitch is not believed to be
significant, it could pose new challenges as developers continue to
grapple with the complexities of MMX design.
The revelations come as Intel ups its bets on MMX by halting the
manufacture of all non-MMX Pentium processors. An even bigger vote of
confidence in the technology -- in the form of a series of new
multimedia instructions dubbed MMX2 -- is reportedly on the way in
Katmai, a Pentium II successor that's slated to appear in the second
half of next year.
"My expectation is that MMX2 will include multiple-issue
floating-point instructions, generating two or even four
single-precision results in one cycle," said Michael Slater, principal
analyst at MicroDesign Resources, in Sebastopol, Calif. "This will
really accelerate the geometry side of 3-D graphics."
Rendering, the other key requirement in 3-D processing, is already
adeptly handled by many existing 3-D accelerators and by the 57
existing MMX instructions, which speed multimedia applications by
letting programmers process many chunks of data in parallel. For
example, MMX can handle four 16-bit data elements, or eight 8-bit data
elements, with just one instruction.
The MMX extensions would reportedly comprise between 10 and 20
additional instructions, which would let the host processor handle 3-D
geometry calculations. Intel is also believed to be mulling the
inclusion of instructions tailored for video compression. The approach
could borrow a page from Sun Microsystems, which includes
pixel-distance instructions in the Visual Instruction Set extensions
to its Sparc microprocessor family.
Intel declined to comment on any future plans for MMX. But it did
reveal that a major MMX-related improvement was included in the
Pentium II CPU, which debuted in May. The boost comes from a dedicated
set of on-chip MMX registers; in earlier MMX processors, the MMX
instructions had to share registers used by the chip's floating-point
code.
"It allows us to make the chip run faster," said John Khazam, the
manager of Intel's 3-D graphics group. "It's strictly an
implementation issue for us. The way we designed this stuff, the
programmer just does not have to pay attention to it."
Indeed, programmers can't explicitly access the new registers. And
Pentium II software must continue to "alias" the MMX registers atop
the floating-point registers. That is, the software must still save
the state of all the floating-point registers as it switches back and
forth between MMX and floating-point code.
The aliasing process is significant because it's the limiting factor
behind context switching -- the time lost in saving system-state
information when a multimedia software routine toggles between MMX and
floating-point code. When the first MMX-enhanced Pentium CPUs were
released, some programmers expressed concerns about laggard context
switching. Reliable estimates put the delay at 28 to 53 clock cycles.
The dedicated MMX registers in the Pentium II promise to make such
concerns a thing of the past by cutting context-switching times to the
bone. Estimates indicate that times peak at around 20 clock cycles in
certain situations and are often less than 10 cycles.
"Context switching isn't really an issue" anymore, analyst Slater
said.
Beyond their implications for performance, the reduced
context-switching times mean developers may be able to use MMX in a
broader variety of applications. That's because they can run even
small snippets of MMX code without having to pay a switchover penalty.
"I would consider paying a five-cycle overhead if I were putting 20
MMX instructions in a row," Intel's Khazam said. "But I wouldn't want
to pay a 20-cycle overhead for 20 MMX instructions."
The newfound MMX flexibility is expected to win the technology inroads
into new application areas. According to Sam Wilkie, the Intel
marketing manager responsible for MMX, Intel is partnering with dozens
of OEMs in a bid to create MMX software that supports the MPEG and
AC-3 decoding requirements of digital video disks. Intel is also
working to seed applications in videoconferencing and theater-quality
audio. Wilkie identified printer drivers and software modems as two
emerging areas ripe for MMX exploitation.
Indeed, the speed savings gained by the use of separate MMX registers
is so great that the registers will surely appear in future
incarnations of the Pentium architecture as well as in Merced, the
64-bit CPU that's expected by the end of the decade.
On the downside, aliasing will likely be maintained in future CPUs so
they will be backwardly compatible with existing operating systems.
"If you're designing from scratch, you can do things differently,"
Khazam said. "But with the Pentium processor and the Pentium II, we
needed to make sure everything that was written before would continue
to run on those machines. However we happen to implement the registers
in hardware, it doesn't change the fact that the OS will treat the
floating-point state and the MMX state interchangeably."
Such compatibility is a prime directive for Intel's designers as they
work on Merced. It's also why programmers probably won't be able to
get at the new registers -- at least in the initial versions of the
64-bit chips.
<<Vieniquas>> Trust No 1

<<Vieniquas>> Trust No 1
Ammetto la mia ignoranza, ma in sostanza cosa c'era scritto????
Ciao, MaX

 
Intel , perso il dominio sull'MMX , lancera' MMX2 ( la vendetta),
evolvera' cosi' le CPU CISC in CCISC ( o CquadroISC) ;-)),
e per mostrare che saranno performanti raddoppiera' la cache L1;
forse servira' uno Slot3 oppure bastera' lo SlotOne/bis .
E' un film gia' visto o sbaglio ?
fil...@iol.it

 <<Vieniquas>> Trust No 1
 basterebbe non comprare tutta la immondizie che produce la Intel. Non è
che sia contro alla casa americana, ma purtroppo ultimamente sta proprio
esagerando. Io credo che sia il modo sbagliato di competere sul mercato, e
presto se ne accorgeranno...non è possibile sfornare un processore ogni 3
mesi senza proporre qualcosa di veramente innovativo! Io credo che la
gente continuera' a farsi fregare i soldi per un po' , ma poi la Intel
pagherà le conseguenze della politica commerciale della "sola" !!!


fil...@iol.it
Gira gira ci sbatteranno il muso come la Commodore.....
Ciao Ricy.