Newsgroup: it.comp.hardware.overclock
Titolo: sblocco moltiplicatore PII

Mi hanno detto che il PII si sblocca coprendo opportunamente alcuni pin,
qualcuno lo ha fatto?
mi sono un pò documentato alla Intel.
Può servire?
Table 5-7. Pentium ® II Processor Family Power-On Configuration Register
Bus Frequency to Core Frequency Ratio Bit Field
pin D#:  25   24  23  22     Ratio of Core Frequency to Bus Frequency
             0     0     1     0    4
             0     0     1     1    2
             0     1     0     1    7/2
             0     1     1     0    9/2
             0     1     0     0    2
Pin name D#22= Pin number B58
Pin name D#25= Pin number B56
Pin name D#24= Pin number A57
Pin name D#23=Pin number  A59
7.5. SYSTEM BUS CLOCK AND PROCESSOR CLOCKING
The BCLK input directly controls the operating speed of the Pentium II
processor system bus
interface. All Pentium II processor system bus timing parameters are
specified with respect to
the rising edge of the BCLK input. The Pentium II processor core frequency
must be
configured during Reset by using the A20M#, IGNNE#, LINT[1]/NMI and
LINT[0]/INTR
pins. (See Table 7-1.) The value on these pins during Reset determines the
multiplier that the
PLL will use for the internal core clock.
   Table 7-1. Core Frequency to System Bus Multiplier Configuration (1)
Ratio of System Bus to
Processor Core Frequency  LINT[1]  LINT[0]  A20M#  IGNNE#
 1/2 (2)             L    L      L     L
 1/4                  L     L       H      L
 2/7                  L    H      L     H
 2/9                  L     H       H      L
 1/2 (2)              H    H       H      H
NOTES:
1. L and H designate electrical levels.
2. This combination exists for safe power-on only. The processor should not
be used in this state.
Table 7-2. Voltage Identification Definition (1, 2, 3)
Processor Pins
VID4  VID3  VID2  VID1  VID0     VccCORE
0 1  1 1  1     Reserved
0  1 1 1 0     Reserved
0 1 1 0 1     Reserved
0 1 1 0 0     Reserved
0 1 0 1 1     Reserved
0 1 0 1 0     Reserved
0  1  0  0  1     Reserved
0  1  0  0  0     Reserved
0  0  1  1  1     Reserved
0  0  1  1  0     Reserved
0  0  1  0  1     1.80 (4)
0  0  1  0  0     1.85 (4)
0  0  0  1  1     1.90 (4)
0  0  0  1  0     1.95 (4)
0  0  0  0  1     2.00 (4)
0  0  0  0  0     2.05 (4)
1  1  1  1  1     No Core
1  1  1  1  0     2.1 (4)
1  1  1  0  1     2.2 (4)
1  1  1  0  0     2.3 (4)
1  1  0  1  1     2.4 (4)
1  1  0  1  0     2.5 (4)
1  1  0  0  1     2.6 (4)
1  1  0  0  0     2.7 (4)
1  0  1  1  1     2.8 (4)
1  0  1  1  0     2.9
1  0  1  0  1     3.0
1  0  1  0  0     3.1
1  0  0  1  1     3.2
1  0  0  1  0     3.3
1  0  0  0  1     3.4
1  0  0  0  0     3.5
NOTES:
1. 0 = Processor pin connected to VSS.
2. 1 = Open on processor; may be pulled up to TTL VIH on motherboard. See
the Pentium ®II Processor
Power Distribution Guidelines (Order Number 243332).
3. VRM output should be disabled for VccCORE values less than 1.80V.
4. To ensure the system is ready for Pentium ® II processor variations, the
values in BOLD in Table 7-2
must be supported.

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qualcuno lo ha fatto?
Per l'ennesiva volta. SOLO i P2-350 e 400 prodotti prima di agosto '98
si sbloccano coprendo il B21, gli altri, nanche se piangi in greco antico.
st.