Newsgroup: it.discussioni.ingegneria
Titolo: Intel's strained silicon process

Mi chiedevo se quelli che lavorano all'ST ne sanno qualcosa in piu' di 
questo processo usato dall'Intel (ma anche da altri come IBM)
Cercando di spiegare in un precedente post che produrri asiatici sono 
assolutamente all'avanguardia (Intel a parte) mi sono imbattuto in 
questa particolarita' del processo Intel.
Non essendo stati molto generosi sui dettagli del processo (ovviamente) 
volevo sapere se qualcuno ne sapeva qualcosa di piu'.
http://www.intel.com/labs/features/si12031.htm#2
Strained Silicon Yields Transistor Performance Gains
---------------------------------------------------- 
Intel is ramping up the industry's first high-volume manufacturing of 
strained silicon on its new 90 nanometer (nm) production process. This 
process — needed to fabricate Intel's next-generation desktop and mobile 
processors — improves transistor performance by 10-25 percent while 
increasing manufacturing costs by only two percent. 
Integrating Strained Silicon
----------------------------
 Strained silicon increases transistor drive current which improves 
switching speed by making current flow more smoothly. The process Intel 
uses for strained silicon has negligible impact on manufacturing costs. 
The first Intel® processors built with this technology are a 125-million 
transistor desktop processor, code-named Prescott, and a 144-million 
transistor mobile processor, code-named Dothan. 
This new 90nm process combines higher-performance, lower-power 
transistors, strained silicon, high-speed copper interconnects, and a 
new low-k dielectric material. Intel disclosed in August 2002 its use 
strained silicon to improve the performance of its transistors produced 
by its 90nm process. This is the first time all of these technologies 
will be integrated into a single manufacturing process. Intel plans to 
have three 300 millimeter (mm) wafer fabs using the 90nm process by 
2004. 
 
How Strained Silicon Works
--------------------------
CMOS (complementary metal oxide semiconductor) is Intel's process 
technology for making all logic chips, such as microprocessors and 
chipsets. CMOS consists of two types of transistors, N and P. These 
transistor types operate differently. 
In NMOS devices (N for negative) the signal carriers, or electrons, have 
a negative charge. Current is on when a NMOS transistor gate is at high 
voltage, and off when its gate is at low voltage. 
In PMOS (P for positive) devices, the signal carriers are "holes," or an 
absence of electrons. The current in a PMOS transistor flows opposite to 
that of an NMOS transistor. It is off when its gate voltage is high and 
on when its gate voltage is low. 
Strained silicon is a process to raise drive current in both types of 
CMOS transistors. Using a very thin layer of single-crystal silicon with 
built in stress, or strain, improves drive current, making the devices 
run faster. At the molecular level, this silicon resembles a lattice. 
 
Benefits of Strained Silicon
----------------------------
 Stressing, stretching, or straining, this lattice lets electrons flow 
with less resistance. Lower resistance means that transistors switch 
states faster and that makes chips compute quicker. The Intel process 
stresses the crystal lattice differently for NMOS and PMOS devices. This 
results in drive current improvements of about 10 percent for NMOS and 
25 percent for PMOS in silicon manufactured with Intel's 90nm process. 
Drive current measures the amount of current flowing from source to 
drain in the transistor. Higher drive current causes a transistor to 
switch between its on-off states faster, ultimately creating a higher 
frequency. This gives a substantial gain over the existing 0.13 micron 
processes while only increasing the manufacturing cost by two percent. 
Strained Silicon Process
------------------------
The basic production challenges to date with strained silicon have been 
its performance benefits for NMOS devices, but lack of benefits for PMOS 
devices. High defect rates have also proved difficult. Intel has solved 
both problems. The 90nm process addresses the NMOS-PMOS issue by using 
different processes for each to derive significant drive current 
performance improvements without adverse effects on defect density. 
Intel's implementation of strained silicon devices improves drive 
current about a 25 percent in PMOS and about 10 percent in NMOS in 
silicon manufactured with it 90nm process. This gives a substantial gain 
over existing 0.13 micron processes while only increasing the 
manufacturing cost by two percent. 
D1C Fab Plays Key Role
----------------------
The 90nm process integrates seven layers of high-speed copper 
interconnects and a low-k interlayer dielectric. Intel uses a 
combination of 248nm and 193nm wavelength lithography equipment for this 
process. The company also reused about 75 percent of the process tools 
used on its current 300mm version of its 0.13 micron process, lowering 
implementation costs and ensuring a mature tool set for the 
manufacturing ramp. Intel's D1C fab in Hillsboro, Oregon is ramping the 
90nm process, but the company will also transfer the new technology to 
other 300mm manufacturing fabs during 2004. 
------------------------------------------------------------------------
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http://www.newscientist.com/news/news.jsp?id=ns99994493
 
Secret of 'strained silicon' chips revealed 
 
 
10:15 20 December 03 
 
Exclusive from New Scientist Print Edition. Subscribe and get 4 free 
issues. 
 
Intel has taken the wraps off a secret technique it is using to increase 
the speed of its Pentium and Centrino chips. The technique boosts the 
rate at which transistors switch, without having to make them smaller. 
The announcement, at the International Electron Devices Meeting in 
Washington DC last week, gives a glimpse into the intensely secretive 
way chip firms attempt to gain an edge over their competitors in a 
market worth over $100 billion a year. 
Chip speed ultimately depends on the rate at which transistors can 
switch on and off. This in turn depends on the speed at which current 
can flow through them, and the distance the charge has to travel. 
 
 Faster chips 
The current speed is determined by the material through which it flows - 
and since chipmakers are more or less stuck with silicon, they have 
concentrated on increasing switching speed by making transistors 
smaller.
But the industry is finding it increasingly difficult to reduce size 
further. Intel's new technique increases the speed of current flow by 
deforming the crystal structure of silicon. The company announced that 
it would be selling chips that employed "strained silicon" in 2002. "But 
we did not explain how we did it," says Mark Bohr, a senior research 
fellow at Intel in Santa Clara, California.
Orbital orientation 
The speed of current flow depends on the crystal structure of silicon. 
Inside the silicon lattice, the electrons around each atom form patterns 
of energy states called orbitals. These states merge to form a 
continuous band that allows electrons and positively charged "holes" to 
move through the lattice. 
The orientation of the orbitals is important. Each atom has six lobe-
shaped orbitals: two in the direction of electron flow and four that are 
perpendicular to it (see graphic). 
In ordinary silicon, all six orbitals have the same energy so there is 
no preferred direction of flow. But stretching the lattice decreases the 
energy of the two orbitals in that direction, letting electrons flow 
more easily along the aligned orbitals. Similarly, squeezing the lattice 
lets positive charges to flow more easily. 
Turning this to practical advantage is difficult, though. Transistors 
contain regions of silicon that are doped with a material such as 
phosphorus to create an excess of electrons in the conduction band - "n-
doped" silicon - and regions that are doped with boron, which adds 
positively-charged holes to form "p-doped" silicon. 
Intel's trick is to stretch the n-doped areas while compressing the p-
doped ones. 
Carved trenches 
 
 
 
Subscribe to New Scientist for more news and features  
 
Related Stories 
 
 
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25 November 2003  
 
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30 September 2003  
 
 
For more related stories 
search the print edition Archive  
 
 
 
Weblinks 
 
 
Intel  
 
International Electron Devices Meeting  
 
Microsystems Technology Laboratories, MIT  
 
IBM  
 
 
 
 
Bohr says the company compresses p-doped regions by carving trenches 
along their opposite ends and filling them with silicon germanium, which 
has a larger lattice size than silicon alone and so compresses the 
regions nearby. This improves hole conduction by 25 per cent. 
To stretch the silicon lattice, Intel deposits a film of silicon nitride 
over the whole transistor at high temperature. Because silicon nitride 
contracts less than silicon as it cools, it locks the silicon lattice 
beneath it in place with a wider spacing than it would normally adopt. 
This improves electron conduction by 10 per cent. 
Intel says the approach gives it a significant speed advantage over its 
competitors and is using the technique in its latest generation of 
chips, whose individual features are as small as 90 nanometres. Intel 
claims its technique boosts chip performance by up to 20 per cent 
compared with ordinary chips of the same size.
"Intel's performance is pretty impressive," says Judy Hoyt, a physicist 
at the Massachusetts Institute of Technology, who pioneered the 
strained-silicon idea in 1992. She adds that other strained-silicon 
techniques are likely to emerge soon. IBM says it is now planning to 
introduce strained silicon in its 90-nanometre chips. 
 
 
Celeste Biever
 
-- 
What the eyes see and the ears hear, the mind believes.

Per capirci, mi domandavo se avevo capito correttamente: prima scavano 
dei solchi attorno al transistor PMOS, poi li riempiono di SiGe per 
comprime le regioni P, e alla fine del processo mettano il nitruro di 
silicio sopra il tutto ad alta temperatura per "tirare" le zone N.
Volevo sapere se qualcuno sapeva in che esatto momento del processo 
fanno una cosa e poi l'altra.

 dei solchi attorno al transistor PMOS
non mi pare. La compressione o lo stiramento dovrebbero
avvenire in fase di deposito/crescita del silicio su un substrato
a differente passo reticolare. In questo modo il cristallo si adatta
al passo reticolrare del substrato.
Comunque (_molto_ schematici):
http://www.ece.pdx.edu/~jeske/classes/ECE_415_515/graduate-projects/win2003/Strained-SOI.pdf
http://www.intel.com/research/downloads/Strained-Si-foils-IEDM-1203.pdf
un po' piu' esplicativo (ma non troppo):
http://ej.iop.org/links/q08/UcDSJYT+i3gXg8qt6bwIxQ/sst4_5_l02.pdf
se ti piacciono la fisica dei semiconduttori e le martellate sui coglioni
(sono abbastanza difficili e richiedono una ottima base di fisica dello
stato solido):
http://www.ntu.edu.sg/eee/eee6/LectureNotes/Pub/WCM2004b.pdf
http://www.naruto-u.ac.jp/~matsudak/mypub_pdf/JCE_1(3)_425.pdf
-- 
maitre Aliboron


 
http://www.naruto-u.ac.jp/~matsudak/mypub_pdf/JCE_1(3)_425.pdf
 
Grazie dei link. 


> 
http://www.intel.com/research/downloads/Strained-Si-foils-IEDM-1203.pdf
Dai un'occhiata a pag 5. Intel fa proprio come ha scritto "new 
scientist" per i PMOS. Scavano un solco agli estremi del transistor e 
depositano SiGe che poi una volta raffreddato il componente comprime il 
canale del PMOS.


 canale del PMOS.
si', effettivamente fanno cosi'.
Io avevo in mente l'approccio tradizionale (pag 3 a sinistra)
-- 
maitre Aliboron