Point Set Morphological Filtering and Semantic Spatial Configuration Modeling: application to microscopic image and bio-structure analysis High-level spatial relation and configuration modeling issues are gaining momentum in the image analysis and pattern recognition fields. In particular, it is deemed important whenever one needs to mine high-content images or large scale image databases in a more expressive way than a purely statistically one. Continuing our previous efforts to incorporate structural analysis by developing specific efficient morphological tools performing on mesh representations like Delaunay triangulations, we propose to formalize spatial relation modeling techniques dedicated to unorganized point sets. We provide an original mesh lattice framework which is more convenient for structural representations of large image data by the means of interest point sets and their morphological analysis. The set of designed numerical operators is based on a specific dilation operator that makes it possible to handle concepts like "between" or "left of" over sparse representations of image data such as graphs. While basically proposing a new theoretical framework to reason about images, for the sake of illustration and discussion, we apply these new tools to high-level queries over large histopathological images which are, by nature, high-content and large size image data to be explored for clinical visual assessment. Shape in computer vision usually refers to either an explicit segmented region over a radiometric image or an implicit feature vector as in Fig. 1 . It is less commonly handled as a visual geometrical point set. Yet it has been long the traditional way to define synthetic object models in computer graphics. Recently, representations of virtual models as point sets have started to overtake the mainstream polygonal mesh or spline surface modeling due to both hardware considerations and a few theoretical advances [1] . On the other side of visual computing issues, traditional image analysis is facing all the more challenging issues as the size, resolution and pace of acquisition of images is exponentially growing, in particular in the satellite and medical fields generating huge amount of visual database to be processed. In that perspective, sparse handling of these data as opposed to redundant radiometric traditional coding schemes must be studied. Concise representations of images by the means of structural elements like edges, point sets or graphs of regions are picking up in the computer vision community [2, 3, 5, 6] and in particular in medical imaging applications [18, 34] . Geometrical representations like point sets for shape or pattern analysis are a means to smooth the way to the efficient handling of large radiometric images: First, geometric features are more stable than radiometric ones and second, as a global representation, they encompass more structural information than local radiometric patches do.. We are ultimately interested in extending usual image analysis tools to geometric representations such as perceptual graphs [4] . Beyond current mainstream works about statistical pattern recognition in the field of image analysis, roughly boiling down to a specific feature extraction step feeding supervised classification algorithms like support vector machines, the research works about structural representations of the image signal is gaining momentum even [2, 3] for the recognition of natural categories like horses. [5] proposed to use contour fragments as descriptors instead of radiometric patches and build a kind of structural codebook composed of the outer object contour fragments associated to their position with regard to the center of the object while [6] extended it to bring a major improvement to the representation by a coding (invariant to scale, translation and rotation) of the geometric properties of each group of k adjacent segments (kAS). One key point here is the definition of spatial arrangements of structural elements, and that proved to be useful even for natural images. The end-users can leverage spatial relation and configuration modeling to enhance the interactive mining process over high-content images or large scale image databases in a more expressive way than a purely statistically one [7] . In addition, this structural modeling is likely to be more resilient to radiometric variations inducing learning biases as well as more expressive for end-user interaction issues and, accordingly, to foster the capabilities of now well-studied and efficient statistical models using radiometric patches for instance [8] .. In this paper, however, we are not directly dealing with object categorization but rather with spatial arrangement characterization by morphological considerations. In this perspective, we are considering the issue of high-level spatial relation representations. A few works have dealt with this issue concerning a kind of spatial reasoning in images from a structural point of view: that is how to model spatial relations like "between" or "around" in a sound and generic framework. [9] , [10] and [11] provide good overviews or interesting ways for representing spatial relations in particular in the imprecise and uncertain universe of image analysis.. While most of the algorithmic solutions to this visual reasoning purpose operate either over usual dense radiometric images or within logical, abstract frameworks like first order logic, we propose here an original, theoretically sound and generic framework to work over sparse representations of visual scenes, such as graphs, in an operational way. This paper continues and in a sense completes our previous efforts for developing morphological tools for the analysis of point sets [12] and extends the seminal ideas about spatial relations modeling over sparse representations presented in [13] . In particular, this paper gives (a) a unified version of the mesh morphological operators (b) develops the set of spatial relationships modeling capabilities and (c) extends it to algorithmic fuzzy versions within a real bioimaging application whereby the point set nuclei architecture plays a major role. Even though generic, we chose to closely relate this contribution to a specific application (that we are currently developing in the field of high-content histopathological image exploration and analysis) both for illustration and proofof-concept purposes. In the following Section 2, we expose the medical context of spatial reasoning from an image analysis point of view with a few but inspiring related existing works specially highlighting the underlying nuclei architecture. Section 3 reviews the theoretical operators we designed for point set analysis and in particular the mathematical lattice framework. Then Section 4 presents the innovative contribution to the modeling of high-level linguistic spatial relation modeling over sparse representations of images as point sets. Last, Section 5 illustrates the handling of these spatial relationships within the medical application of interest while Section 6 draws significant theoretical and applicative perspectives of research in particular in the bio-imaging field. To sum up, based on original mathematical morphological filters dedicated to unorganized point sets, we developed new generic operators to perform structural analysis of images via an architectural representation as mesh of interest points for instance. In particular, a new way for handling spatial relation queries has been proposed and illustrations over histopathological images proved the usefulness of this new framework to interactively explore huge images. Beyond the applicative aspect, these operators have been proved to be theoretically sound from the mathematical lattice framework side. Accordingly, these tools open new ways to anchor high-level semantic and spatial relation concepts in the field of image analysis. In perspective, a thorough analysis of topological aspects about the extension to a lattice of simplicial complexes including the edges and the vertices in the morphological process as attempted in [37, 38] should raise interesting new theoretical issues for mathematical modeling and powerful computerized representations for topological study and understanding of biological processes.

O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B I I O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B I O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B I O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B I I O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O


Kinematic and Elastostatic Design Optimisation of the 3-DOF Gantry-Tau Parallel Kinematic Manipulator One of the main advantages of the Gantry-Tau machine is a large accessible workspace/footprint ratio compared to many other parallel machines. The Gantry-Tau improves this ration further by allowing a change of assembly mode without internal link collisions or collisions between the links and end-effector. The reconfigurable Gantry-Tau kinematic design obtained by multi-objective optimisation according to this paper gives the following features: 3-D workspace/footprint ratio is more than 3.19, lowest Cartesian stiffness in the workspace is 5N/µm and no link collisions detected. The optimisation parameters are the support frame lengths, the actuator positions and the robot's arm lengths. The results comparison between the evolutionary complex search algorithm and gradient-based method used for the Gantry-Tau design in the past is also presented in this paper. The detailed statics model analysis of the Gantry-Tau based on a functionally dependency is presented in this paper for the first time. Both the statics model and complex search algorithm may be applied for other 3-DOF Hexapods without major changes. The existing lab prototype of the Gantry-Tau was assembled and completed at the University of Agder, Norway. A generalised parallel kinematic manipulator (PKM) is a closed-loop kinematic chain mechanism where the end-effector is linked to the base by several independent kinematic chains, (Merlet, 2000) . It may consist of redundant mechanisms with more actuators than the number of controlled degrees of freedom of the endeffector. The study of PKMs has been an active research field in robotics and mechanical design for a long time and different parallel mechanism with specified number and type of DOF have been proposed. In the late 1980s a new field of applications and research was developed by (Clavel, 1988) , who put the focus on lower mobility parallel mechanism. The Delta robot presented by Clavel was a base for a large range of machines dedicated to high-speed applications but because of small workspace in relation to footprint and limited number of degrees of freedom the robot can not be used as a general purpose manipulator. Pierrot proposed a 6-DOF fully-parallel robot HEXA. The HEXA robot, (Pierrot et al., 1992) and (Uchiyama et al., 1990) , is an extension of the Delta mechanism having 6 DOFs but because the workspace/footprint ratio and tilting angles are small this robot has also a limited capability compared to serial manipulators.. The Tau family of parallel kinematic manipulators was invented by ABB Robotics, see (Brogårdh, 2000) . The Gantry-Tau PKM makes use of the non-symmetric Tau structure that is based on clustering the links mounted on the actuated arms in the configuration 3-2-1. The different possibilities of Tau structures are presented in (Brogårdh and Gu, 2002) . The link structure 3-2-1 is shown in Fig. 1 , where the six links support only axial forces. Tool forces (represented by F h ) in the figure, generate forces and torques on the manipulated platform (in the figure a shaft), which are fully supported by axial forces in the six links. The link structure 3-2-1 gives the best opportunities to adapt the PKM to the specific application requirements. The high stiffness is obtained by the redundant replacement of the linear actuator M 1 and position of the link L 1 ; the distance between links can be increased without reducing the workspace, it makes a possibility of reducing the link forces, especially with respect to the vertical forces on the TCP. The intended applications of the Gantry-Tau are high speed machining operations requiring a workspace equal to or larger than a typical serial-type robot's, but with higher stiffness. However, the robot can also be designed for very fast material handling and assembly or for high precision processes such as laser cutting, water jet cutting and measurement. One of the main contributions of this paper is the combination of the evolutionary multi-objective methodology based on the complex search algorithm with geometric descriptions of the Gantry-Tau to optimise the parallel kinematic structure. The design optimisation scheme includes the kinematic and elaststatic properties of the PKM. Dimensional synthesis is a part of the design and to obtain the targeted performance at lowest cost, physical design (material selection, bearing design, actuator design etc.) must also be made. The physical design as a part of the Gantry-Tau design optimisation is one of the future research directions. Multi-objective evolutionary algorithms require a relatively large number of iterations to produce reasonably good approximations of the optimal set of the designs. This has motivated the hybridisation of evolutionary algorithms (global search engines) with local search engines of different types to reduce a computational time effort. An optimisation routine for the platform design according to the required applications would also be a challenging future research topic. In addition, we want to acknowledge the support from the University of Agder, Norway for providing the resources needed to optimise the Gantry-Tau presented in this paper. The majority of the work presented in this paper was conducted during the first half of 2008, when I. Tyapin visited the University of Agder. The final optimisation design parameters of the 3-DOF Gantry-Tau were found using the complex search algorithm and gradient-based function f mincon in integrated Matlab optimisation toolbox. The optimisation results obtained in this paper are summarised in Table 4 and compared with original design parameters, worse and average designs. The initial population size is 50 randomised designs. The number of evaluations of the objective function was not fixed and optimisation stopped when the difference between the best and worst designs was less than 10 −3 . Fig. 30 shows the convergence trend of the main objective function F as a summary of 3 sub-objectives (f qual , f stif and f g ) in 2000 iterations. f stif = 1 f g = 0. The results would have been difficult to obtain by a manual design, as the the support frame dimension is different from Q 1 = 2Q 2 ≈ Q 3 , Q 4 = 0 which have been typical manual design choices of the Gantry-Tau in the past. According to Table 4 the the objective function was improved by 36.9 %, sub-objectives f qual and f stif by −48 %, and 59.1 % respectively. The gradient-based search algorithm can not provide an appropriate results and reach the global optimum in Figure 31 : The convergence trend of the sub-objective function f stif 500 iterations.. irregular feasible region. The optimised design was obtained in less than 5 hours on a Pentium Centrino 2 (CPU 2.2 MHz) computer. Furthermore, the approach proposed in this paper is very simple and easy to be implement for other PKMs.

O O O B I O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B O O O O O O O O O O O O O O O O O O O O O B O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B I O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B I O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O


Concurrent Event Handling through Multithreading AbstractÐExceptions have traditionally been used to handle infrequently occurring and unpredictable events during normal program execution. Current trends in microprocessor and operating systems design continue to increase the cost of event handling. Because of the deep pipelines and wide out-of-order superscalar architectures of contemporary microprocessors, an event may need to nullify a large number of in-flight instructions. Large register files require existing software systems to save and restore a substantial amount of process state before executing an exception handler. At the same time, processors are executing in environments that supply higher event frequencies and demand higher performance. We have developed an alternative architecture, Concurrent Event Handling, that incorporates multithreading into event handling architectures. Instead of handling the event in the faulting thread's architectural and pipeline registers, the fault handler is forked into its own thread slot and executes concurrently with the faulting thread. Microbenchmark programs show a factor of 3 speedup for concurrent event handling over a traditional architecture on code that takes frequent exceptions. We also demonstrate substantial speedups on two event-based applications. Concurrent Event Handling is implemented in the MIT Multi-ALU Processor (MAP) chip. M ODERN microprocessors use exception or event hardware to handle infrequently occurring and unpredictable events. Events may be classified as internal, caused by the program executing on the processor, or external, caused by actions outside of the processor. Internal events may include arithmetic faults, memory protection violations, page faults requiring software to modify the TLB or fetch a new page of data from disk, or even user initiated system calls that trap into the operating system. Traditional examples of external events include watchdog timer interrupts and I/O interrupts caused by the disk drive or a keyboard controller. Regardless of event type, the purpose of the event detection hardware is to prevent a program from being penalized in the absence of events. Without hardware for exception detection, programs would be required to continually check for exceptional conditions. Two trends in modern computer systems conspire against traditional exception architectures [28] . First, the cost of exception handling is increasing relative to the performance of microprocessors. The increasing width and depth of out-of-order superscalar pipelines accentuate the cost of event handling since the pipeline must be drained in response to an exception or event. In a 6-wide 10-deep pipeline, this results in as many as 60 wasted issue slots. Exception handling is further slowed by software that must frequently modify the pipeline state, vector to trap handlers, and manipulate the machine visible registers [4] , [24] . The second trend is the increase in novel uses of event handling that are no longer ªexceptional.º These include support for garbage collection [5] , software managed distributed virtual memory [21] , and profiling [32] . Furthermore, for processors in embedded environments, performance can be limited by the ability to respond to a variety of external events, such as sensor inputs or packets in a network router.. The advent of hardware support for multithreading in microprocessors can alleviate both the latency and hardware complexity of event handling. When the hardware detects an event in a traditional single-threaded processor, an expensive sequence of actions must take place even before any of the event handling code is executed. The pipeline must be halted and drained, the stalled thread's registers and protection domain must be saved to memory, and the event handler's state and protection domain must be restored. Once the event handler has completed, this process must be reversed. Instead, with the appropriate mechanisms, a multithreaded processor can avoid most of this overhead by forking the event handler into a separate hardware context. Multithreading also provides the opportunity to execute applications and event handlers simultaneously, further reducing the overhead of events.. This paper introduces a general framework and nomenclature for Concurrent Event Handling and presents the resulting architecture, as well as an example implementation in the MIT Multi-ALU processor (MAP) chip. The MAP chip provides hardware support for concurrent execution of both internal and external events. It incorporates three onchip processors, each of which includes six thread slots for interleaving multiple threads of execution. In each processor, three thread slots are available for user level programs, while additional slots are reserved for exception and event handling, including TLB misses, synchronization failures, cache faults, and asynchronously arriving messages from other MAP chips in a multiprocessor system.. Using multithreading for event handling has two advantages. First, it reduces the overhead to invoke and return from an exception since the faulting thread is not removed from the pipeline. Second, event handling can proceed in parallel with the application, enabling faster event execution for both internal and external events. Hardware support for concurrent event handling allows the traditional requirements for sequentially precise interrupts in microprocessors to be relaxed, improving performance without sacrificing correctness.. In our experiments, we show that concurrent event handling outperforms event architectures that swap or stall the faulting thread. If a hardware thread slot is available for event handling, the latency of a null event drops from 100 cycles to 14 cycles. The null event handler's occupancy in a thread slot also drops to less than 10 cycles, reducing the contention between multiple threads for the execution resources. Applications that exhibit a high event rate show substantial performance improvements when using concurrent event handling. Eliminating swapping improves application performance by 19 percent, while running event handlers in parallel with application code provides an additional improvement of 26-43 percent.. The rest of this paper is structured as follows: Section 2 describes modern exception handing in further detail, highlighting the sources of overhead. The necessary architectural support for a concurrent event system and the implementation of concurrent event mechanisms in the MAP are detailed in Section 3. Section 4 explores the benefits of concurrent event handling through both microbenchmarks and two applications. Section 5 examines related work in multithreading and optimizations for fast event handling. Finally, we summarize the architecture and results in Section 6. The experimental results in this section show the benefits of concurrent event handling in microbenchmarks and in applications that have high event frequencies. The first component of concurrent event handling is the elimination of the high software overhead associated with stopping the application and replacing it with the event handler. In the software shared memory example, this improved the application's performance by 19 percent. With a rate of one sample every 500 cycles in the Dynamic Profiler, performance also improves by 19 percent. Executing events concurrently with application is also critical, with shared memory improving an additional 30 percent and the profiler improving 4 percent. Future computer systems that intend to support event rates on par with those shown in the experiments (30-500 cycles between events) will need to rely on concurrent event mechanisms to reduce event overhead. In this paper, we introduce concurrent event handling, an architecture that increases event performance through multithreading. When an event occurs, the handler is forked into the dedicated thread slot and can execute simultaneously with other programs that are already running. Concurrent event handling has three advantages over traditional event handling. First, dedicating a thread slot in a multithreaded processor to an event handler eliminates the need to stop the faulting thread. The faulting thread state remains in the pipeline registers and none of the nonfaulting instructions need to be nullified. Second, replicating register files for multiple threads eliminates the software overhead that normally is required to remove and restart a faulting thread. Finally, greater thread level parallelism can be achieved by running the event handler concurrently with the faulting threads and other event handlers. As microprocessors are able to issue more instructions per cycle, the number of wasted issue slots (due to a lack of sufficient instruction level parallelism) is increasing. Interleaving execution of event handlers and an application will help improve program throughput and reduce overall execution time.. Many modern microprocessors implement sequentially precise interrupts to enforce a strict order of instructions in a faulting thread when it is halted and replaced by the event handler [27] . However, in multithreaded processors, this conservative approach can unnecessarily hinder performance. Instead, concurrent event handling with precise events maintains consistency while improving performance, as the original thread continues to execute until it reaches a true dependency on the result from the faulted instruction. While the faulting thread proceeds, all necessary information required to resolve the fault is captured and provided to the event handler.. Using a combination of microbenchmarks and applications with high event rates, we demonstrate the advantages of concurrent event handling over more traditional event architectures. Without the software overhead of replacing the faulting thread with the event thread, the latency of a null internal event drops from 100 cycles to 14 cycles. Our sample applications, software shared memory and dynamic profiling, have events that occur on average every 30-500 cycles. In this environment, the reduction in event overhead improves application performance by 19 percent.. The additional advantage of running event handlers in parallel with application code provides a total execution time reduction of 26-43 percent.. Concurrent event handling has been incorporated into the MIT Multi-ALU Processor, a 5 million transistor custom VLSI chip [14] . The MAP chip implements multithreading by replicating pipeline resources across the on-chip processor clusters to improve latency tolerance, function unit utilization, and overall performance. Incorporating concurrent event handling requires only a small amount of additional real estate for the message and event queues, less than 6 percent of the total chip area. While the MAP chip issues instructions in-order, concurrent event handling and the precise event model are applicable as well in out-oforder processors and can simplify the hardware required to maintain consistent state during synchronous and asynchronous events.. Stephen W. Keckler received the BS degree in electrical engineering from Stanford University in 1990, and both the MS and PhD degrees in computer science from the Massachusetts Institute of Technology in 1992 and 1998, respectively. From 1989 to 1990, he worked at Intel designing circuits for the 386SL microprocessor. He is currently an assistant professor of computer science at the University of Texas at Austin. His research interests include computer architecture, parallel and embedded processors, VLSI design, and the relationship between VLSI technology and computer architectures. He is a member of Phi Beta Kappa, Tau Beta Pi, Sigma Xi, the IEEE, and the ACM.. Andrew Chang received the SB degree in 1988 and the SM degree in 1998, both in electrical engineering, from the Massachusetts Institute of Technology. As an engineering group leader at Loral Fairchild Imaging Sensors from 1989 to 1990 and the principal electrical engineer at AOI Systems from 1990 to 1992, he designed CCD imaging systems for automated optical inspection. He is currently a PhD student in the Concurrent VLSI Architecture Group at Stanford University. His research interests include CAD, computer architecture, and VLSI circuit design. He is a student member of both the IEEE and the ACM. Sandeep Chatterjee received the BS degree in electrical engineering and computer science from the University of California at Berkeley in 1995 and the MS degree in electrical engineering and computer science from the Massachusetts Institute of Technology in 1997. He is currently a doctoral candidate at MIT's Laboratory for Computer Science. His research interests include computer architecture, low-power design, and intelligent systems. He is a member of Eta Kappa Nu, Tau Beta Pi, the IEEE, and the ACM.. William J. Dally received the BS degree in electrical engineering from Virginia Polytechnic Institute, the MS degree in electrical engineering from Stanford University, and the PhD degree in computer science from the California Institute of Technology. Dr. Dally and his group have developed system architecture, network architecture, signaling, routing, and synchronization technology that can be found in most large parallel computers today. While at Bell Telephone Laboratories, he contributed to the design of the BELLMAC32 microprocessor and designed the MARS hardware accelerator. He was a research assistant and then a research fellow at Caltech, where he designed the MOSSIM Simulation Engine and the Torus Routing Chip which pioneered wormhole routing and virtual-channel flow control. While a professor of electrical engineering and computer science at the Massachusetts Institute of Technology, he and his group built the JMachine and the M-Machine, experimental parallel computer systems that pioneered the separation of mechanisms from programming models and demonstrated very low overhead mechanisms for synchronization and communication. He has worked with Cray Research and Intel to incorporate many of these innovations in commercial parallel computers and with Avici Systems to incorporate this technology into Internet routers. Dr. Dally is currently a professor of electrical engineering and computer science at Stanford University, where he leads projects on high-speed signaling, multiprocessor architecture, and graphics architecture. He has published more than 80 papers in these areas and is an author of the textbook, Digital Systems Engineering. In addition to the block [1] and round-robin multithreading [2] , [26] , two other multithreaded architectures are of note. Like the MAP, Interleaving schedules multiple threads over a single processor without requiring a thread switch on every cycle [18] . Since pipeline registers are not replicated, events that require a thread to stall, such as a cache miss, must squash instructions that have already been issued into the pipeline. Simultaneous Multithreading extends an outof-order superscalar architecture to execute instructions from multiple threads at the same time [30] . SMT uses a traditional exception model and does not execute interrupts at the same time as user threads. However, the extensions described in this paper can be incorporated into a dynamically scheduled multithreaded architecture in a straightforward manner.. Other architectures and machines have provided hardware support for asynchronous event handling, typically in the framework of a message-passing multiprocessor. The JMachine's Message Driven Processor (MDP) implements one hardware context for background tasks and two contexts for message handling [8] . When a message arrives, the task running in the background context suspends (stalls) and the incoming message invokes a thread to handle the contents of the message. The *T architecture [25] and the FLASH multiprocessor [17] use coprocessors to process incoming messages and to communicate with the master computation processors.. Thekkath and Levy observed that many exceptions need to be handled in user code and that standard event architectures impose a large overhead jumping into and out of the kernel [28] . Consequently, they proposed a hardware mechanism for vectoring events directly to user level code without entering the kernel. In the absence of hardware support, they also examined methods which limit the kernel overhead by detecting a user level event and vectoring directly to it. As a result, they were able to reduce the latency of a null user-handled event from 1,225 to 125 cycles on a 25 MHz R3000 workstation running Ultrix. An even more lightweight form of user-level events is Informing Memory Operations [12] . This event architecture can trigger a fast user specified and user handled trap on a cache miss. The executing program determines which memory operations are enabled for traps. When a cache miss occurs, the trap is handled in the faulting program's register set. The hardware trap handling can be folded into existing branch or event hardware in an out-of-order superscalar microprocessor. While this eliminates full context switching (values in registers can be saved by the trap handler as necessary), it may still incur the hardware execution overhead required by precise interrupts.

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O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O 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Resource virtualization in real-time CORBA middleware Middleware for parallel and distributed systems is designed to virtualize computation and communication resources so that a more abstract and consistent view of those resources is presented to the applications that use them. Providing such a consistent virtualization in distributed real-time and embedded systems becomes increasingly challenging due to application constraints such as timeliness and resource constraints such as CPU speed, power, memory, and bandwidth limitations, which also must be considered.This paper describes several examples of real-time CORBA middleware and examines how different constraints impact the way in which resources are virtualized in each case. Particular attention is paid to which details are hidden from users of the middleware, which details are exposed in the middleware's programming model, and how the hidden and exposed details interact to shape middleware design and implementation choices. Middleware for parallel and distributed systems is designed to shield application developers from many details of the underlying computing environment, and to expose only the particular details that are relevant to a particular programming model. For example, the Object Management Group (OMG)'s Common Object Request Broker Architecture (CORBA) [41] provides object reference and interface semantics so that method invocations between objects written in different programming languages or executing on different endsystems are performed transparently through a set of object request brokers (ORBs).. Such language and location transparency greatly eases the task of developing distributed applications, since the mechanisms for managing the complexities of concurrent computation and asynchronous communication are relegated to the ORBs, and sets of * Supported in part by NSF CAREER award CCF-0448562.. objects can be programmed independently using the languages that are most suited to the application and/or developers' preferences. However, the virtualization of the underlying computing environment is not absolute, so that (even for functional properties such as the correct invocation of remote methods) some details unavoidably must be considered by application developers. For example, in CORBA the NO MEMORY and COMM FAILURE exceptions indicate failure of a method invocation due to memory exhaustion or communication failure, respectively, which may have occurred on a remote endsystem over which the calling program has no control.. Application developers may also choose which features of the middleware's programming model they use, to trade transparency for performance or other benefits. For example, CORBA offers two-way method invocation semantics which mimics a local method invocation in which the caller blocks until the called method returns. To improve performance of distributed applications, CORBA also offers asynchronous method invocation (AMI) [37] in which the calling method can continue to execute concurrently with the called method's execution. The two-way method invocation interface is more transparent as it only requires the caller to obtain a reference to the object and invoke the method, whereas with AMI the caller may also need to poll for the result from the called method, or register an asynchronous callback handler with the ORB.. Providing a consistent virtualization of the underlying computing environment becomes increasingly challenging for distributed real-time and embedded systems, in which application constraints on properties such as timing, or explicit limitations on system resources such as memory, are as important to the correct operation of an application as its functional properties. This has resulted in further expansion of the set of programming model abstractions exposed by the middleware. For example, the OMG's Real-time CORBA Specification [40] extends the CORBA programming model to include prioritization of method invocations and configuration of processing and communication control features, which are crucial to supporting statically scheduled priority based real-time systems.. Although the evolution of standards has helped to address the tension between hiding details application developers do not need to address, while exposing those they do, the number and variety of different design dimensions faced by developers of complex distributed real-time and embedded systems makes it difficult for any one specification to strike a suitable balance for all applications. This has led in turn to new system development approaches in which middleware programming models and the underlying policies and mechanisms they represent are configured using abstract (and often formal) models.. This paper examines the problem of striking a balance between hiding and exposing crucial details in middleware programming models, from the perspective of several previous real-time middleware projects. Section 2 describes the challenges that distributed real-time and embedded systems pose for the design and implementation of real-time CORBA middleware. Section 3 describes solution approaches that have been used to address the challenges presented in Section 2. Section 4 examines the relationships between hidden and exposed abstractions in each of the solution approaches described in Section 3. Section 5 surveys related work, and Section 6 offers concluding remarks. This paper has examined how different middleware frameworks have been designed to support particular sub-domains of the distributed object computing application domain to which the CORBA standard pertains. Common middleware abstractions such as references, objects, components, method invocations, ports, and assembly and deployment descriptors are used to virtualize lower level services provided by the operating system, such as threads, sockets, and event demultiplexors -the operating system services in turn virtualize hardware resources such as network devices, disks, memory, and CPUs. The benefits of this virtualization include increased portability across different operating system interfaces and mechanisms, reduced programming complexity as lower-level details are abstracted away, and removal of inappropriate dependencies among application components and between application components and underlying operating system services.. Adapting middleware solutions to particular sub-domains, and particularly to the intersections among sub-domains (e.g., real-time and small footprint), requires careful specialization that in some cases must sacrifice compliance with standards that govern broader domains, in order to achieve compliance with particular requirements of the relevant sub-domain(s). In such cases, construction of middleware solutions from foundational building blocks offers an important (and often complementary) alternative to decomposing larger-scale frameworks that were designed for the more general domain within which the sub-domain is nested.. Multi-level modeling approaches appear promising to allow analysis and verification of customized systems involving both coarsergrain configuration choices and finer-grain specializations, particularly when applied to middleware frameworks that support significant configurability of all relevant system properties, at both coarse and fine granularity. However, applying multi-level modeling approaches effectively to a broad range of distributed real-time and embedded systems will require significant further research on composition of system properties (particularly across sub-domains and/or architectural layers), and on efficient and flexible mechanisms for run-time enforcement of the composed properties. As Section 3 illustrates, a variety of solution approaches are needed to address all of the challenges given in Section 2. Furthermore, in addition to the particular set of interfaces and configuration options that it exposes, each middleware solution approach has its own internal semantic structure that must be taken into account. Design, verification, implementation, and validation of middleware based systems must represent and leverage this structure for successful re-use of designs, models, implementations, and verification and validation evidence. In this section we first discuss how each of the solution approaches presented in Section 3 virtualizes resources using the abstractions provided to it by lower layers of the system architecture. We then examine open problems that must be addressed to allow different virtualization techniques to be combined effectively and correctly, to increase the fidelity with which the programming model presented to system developers can express and control the issues specific to any particular application.. Resource virtualization: For the distributed object computing domain, TAO hides many low-level system software concerns such as connection establishment, concurrency, and message demultiplexing and dispatching, and exposes higher level abstractions such as location and language transparent object references and method interfaces. For the real-time sub-domain, TAO exposes more of its low-level internal semantics, such as the ability to configure thread pool sizes and priority lanes [42] , according to the RealTime CORBA specifications [40] .. For the distributed object computing domain, CIAO further virtualizes system resources by hiding details of the services provided by TAO. For example, CIAO provides different kinds of ports, (i.e., facets, receptacles, event sources, and event sinks), which encapsulate the client-side and server-side roles of both method invocation and event passing styles of communication between objects. For the real-time sub-domain, CIAO also opens up internal details to reveal not only the Real-Time CORBA features exposed by TAO [53] , but also details of the particular application's constraints and characteristics and of the hardware resources on which the application is deployed [52] .. Because nORB [50] supports multiple sub-domains (i.e., realtime and small footprint), its approach to resource virtualization necessarily includes restricting the set of interfaces and supporting features that it exposes to include only those that are explicitly required and excluding other features whose inclusion would interfere with constraints on properties from any of the sub-domains involved. However, because different combinations of sub-domains may produce different patterns of feature interference, supporting such fine-grain specialization through selecting specific sets of features and interfaces a priori is naturally problematic.. Model-based approaches allow selective configuration of features and interfaces so that such interference can be avoided, while still presenting system developers with common and reasonably simple interfaces and configuration mechanisms. Techniques at several architectural levels, such as domain-specific modeling languages [2] ) at the level of the TAO ORB, and timed models at the level of the ACE building blocks upon which TAO depends [50] allows concerns to be separated appropriately, but then analyzed and enforced across architectural layers.. Open problems: Although nORB cannot claim to be a fully compliant CORBA ORB, it supports the most essential features, and more importantly supports the features required by the sub-domain it targets. However, this raises an important question -how to support a related sub-domain with similar constraints to the one supported by nORB, but which requires one or more additional data or message types? How those types could be added to nORB for use cases that need it, but then eliminated for use cases that cannot tolerate it (or simply do not need it) is an important problem. Aspectoriented middleware configuration techniques have been shown to be helpful [23] , but further experience applying these and other generative programming techniques is needed.. In addition to the need for new tools and techniques for generative transformation (and/or synthesis) of customized middleware implementations and interfaces, additional research is needed both into how different combinations of properties (particularly from different sub-domains) can be combined correctly, in ways that can be enforced. Further work is also needed into techniques by which the correctness of different combinations can be proven or otherwise checked, automatically. Important open problems appear at the level of the properties themselves (for example, how domainspecific information can be exploited to support efficient and provable deadlock avoidance [44] ), and at the level of tools such as model checkers (for example, how domain-specific state-space optimizations [47] can be re-used across use-cases in the domain). Customizable Middleware: MicroQoSCORBA [1] reduces middleware footprint by generating customized instantiations of middleware for embedded systems. Zen [28] is a highly customizable real-time Java [4] CORBA object request broker. Ubiquitous CORBA projects such as the CORBA specialization of the minimal Universally Interoperable Core (UIC) [35] use meta-programming to support a significant degree of middleware customization.

O O O O B O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B O O O O O O O O O O O O O O O O O O O O O O O O O O O B O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B O O O O B O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B I O O O O O O O O O O O O O O O O O O O O B O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B O O O O B O O O O B O O O O O O O O O O O O O O O O O O O


An Effective Multilevel Tabu Search Approach for Balanced Graph Partitioning Graph partitioning is one of the fundamental NP-complete problems which is widely applied in many domains, such as VLSI design, image segmentation, data mining etc. Given a graph G = (V, E), the balanced k-partitioning problem consists in partitioning the vertex set V into k disjoint subsets of about the same size, such that the number of cutting edges is minimized. In this paper, we present a multilevel algorithm for balanced partition, which integrates a powerful refinement procedure based on tabu search with periodic perturbations. Experimental evaluations on a wide collection of benchmark graphs show that the proposed approach not only competes very favorably with the two well-known partitioning packages METIS and CHACO, but also improves more than two thirds of the best balanced partitions ever reported in the literature.Keywords: Balanced partitioning; multilevel approach; iterated tabu search.Given an undirected graph G = (V, E), where V and E denote sets of vertices and edges respectively, the balanced k-partitioning problem consists in partitioning the vertex set V into k (k ≥ 2) disjoint subsets of approximately equal size, such that the number of cutting edges (i.e. edges whose endpoints belong to different subsets) is minimized. The particular partitioning case when k In this section, we turn our attention to the analysis of two important features of the MITS algorithm and try to answer the following questions: Is the perturbation mechanism (see Section 4.2) relevant for the MITS? Is the newly proposed Double move, which is used to define the neighborhood relation N 2 (see Section 4.1.2), a value-added one?. To answer these questions, we report in Table 7 the average results over 10 executions with MITS, when its two components (perturbation mechanism and neighborhood N 2 ) are included and excluded. We conduct these experiments with k set to 4, 8, 16 and 32, on a set of 10 representative instances from the Graph Partitioning archive. For each k, colon "+(P M&N 2 )" provides the average results when both the perturbation mechanism and the neighborhood N 2 are used within MITS. Colons "−P M" and "−N 2 " report respectively the average results when the perturbation mechanism or the neighborhood N 2 is disabled. Finally, the last colon "−(P M&N 2 )" gives the average results when both features are excluded from the MITS algorithm. The last row with heading Total shows the number of times each version of MITS produced the best average result over the 10 graphs.. From Table 7 , we see that the performance of our MITS algorithm decreases when the perturbation mechanism or neighborhood N 2 , or both are disabled. This confirms our previous observation that some diversification is needed to complement the aggressive tabu search strategy, which only considers border (critical) vertices. Indeed, although examining only border vertices for move consideration decreases the number of candidate moves at each iteration, this does not allow the search to escape from deep local optima. Therefore, this experiment confirms this intuitive explanation.. We can also see from Table 7 that in most cases, MITS produces significantly better partitions when the two neighborhoods N 1 and N 2 are jointly explored (see Section 4.1.2). This can be explained by the fact that neighborhood N 2 does not strictly impose the balance constraint as neighborhood N 1 does. With N 2 , there are more vertices which are considered to be moved to the target subset, introducing thus a greater degree of freedom during the search process. This complements the strict selection criterion of neighborhood N 1 .. From Table 7 we can see that in several cases the simplest version of MITS, i.e. when both features are excluded, gives the best average results. However, as can be expected, the initial MITS still outperforms the simplest version in about 80% of cases. This implies that both of these elements are important for the efficiency of the proposed MITS algorithm. Table 7 The average results over 10 executions of MITS when the perturbation mechanism and the neighborhood relation N 2 are included and excluded.

O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B I B I O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O


Approximate moment matrix decomposition in wavelet Galerkin BEM We present an improvement to the wavelet Galerkin BEM in [J. Tausch, A variable order wavelet method for the sparse representation of layer potentials in the nonstandard form. J. Numer. Math. 12(3): 2004]. In the non-standard form representation of integral operators the number of wavelets in every level determines the efficiency of the underlying Galerkin scheme. In order to increase this number, the partial singular value decomposition (PSVD) of the moment matrix is employed. Since the resulting wavelets do not exactly satisfy the conventional vanishing moment condition, i.e., a certain number of polynomial moments of the wavelets are zero, we introduce the concept of "quasi-vanishing moment". For integral equations of the second kind we prove that the asymptotic convergence of the full Galerkin scheme can be retained by controlling the cut-off for singular values in the PSVD appropriately. Numerical results show that our improvement can largely decrease the time and memory usage while preserving the optimal convergence rate of the method. Many mathematical models concerning problems in applied science and engineering are based on boundary integral operators. In this paper we consider the following settings.

O O O O O O B I O O O O O O O B I O O O O O O O O O O O O O O O O O O O O O O O O O O B I O O O O O O O B O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B O O O O O O O O O O O O O O O O O O B O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O


Parametric estimation of affine deformations of planar shapes We consider the estimation of affine transformations aligning a known 2D shape and its distorted observation. The classical way to solve this registration problem is to find correspondences between the shapes and then compute the transformation parameters from these landmarks. Here we propose a novel approach where the exact transformation is obtained as the solution of a polynomial system of equations. The method has been tested on synthetic as well as on real images and its robustness in the presence of segmentation errors and additive geometric noise has also been demonstrated. We have successfully applied the method for the registration of hip prosthesis X-ray images. The advantage of the proposed solution is that it is fast, easy to implement, has linear time complexity, works without established correspondences and provides an exact solution regardless of the magnitude of transformation. Registration is a crucial step in almost all image processing tasks where images of different views or sensors of an object need to be compared or combined. Typical application areas include visual inspection, target tracking in video sequences, super resolution, or medical image analysis. In a general setting, one is looking for a transformation which aligns two images such that one image (called the observation) becomes similar to the second one (called the template). Due to the large number of possible transformations, there is a huge variability of the object signature. In fact, each observation is an element of the orbit of the transformations applied to the template. Hence the problem is inherently ill-defined unless this variability is taken into account. A good survey of registration methods can be found in [1] [2] [3] [4] [5] . Basically registration algorithms fall into two main categories: Feature-based and Area-based methods.. Feature-based methods [6, 7] aim at establishing point correspondences between two images. For that purpose, they extract some easily detectable features (e.g. intersection of lines, corners, etc.) from the images and then use these points to compute the closest transformation based on a similarity metric. Therefore, to make this approach feasible, the correspondence problem must be solved first. Unfortunately, the solution of this problem is far from trivial and usually relies on the assumption that the deformation is close to identity and that features provide a strong contextual evidence for matching landmark points. Other approaches based on "continuous landmarks", such as curves representing the boundaries of objects, usually yield to a complex, non-convex optimization problem requiring computationally expensive algorithms to solve. Searching for the best transformation usually requires an iterative algorithm like the Iterative Closest Point (ICP) algorithm [8] . The main drawback of these methods is that an optimization procedure has high computational cost. In addition, the reliable solution of the correspondence problem assumes that the transformation is close to identity. The main advantage of these methods is that as long as a sufficient number of point matches are available, one can usually find an optimal aligning transformation implying that these algorithms are less sensitive to occlusions.. Area-based methods [9] [10] [11] [12] [13] treat the problem without attempting to detect salient objects. These methods are sometimes called correlation-like methods because they use a rectangular window to gain some preliminary information about the distortion. They search the position in the observation where the matching of the two windows is the best and then look for sufficient alignment between the windows in the template and in the observation. When the distortion is small, often Fourier descriptors [14] or mutual information [15] is used. The drawback of this family of methods is also the high computational cost and the restricted range of distortions.. In many situations, the variability of image features is so complex that the only feasible way to register such images is to reduce them to a binary representation and solve the registration problem in that context [16] . X-ray images are good examples as they usually exhibit highly nonlinear radiometric distor-tions [17, 18] making registration hard to solve. Therefore binary registration (i.e. shape matching) is an important problem for many complex image analysis tasks.. Several techniques have been proposed to address the affine registration problem. By thresholding the magnitude of Fourier Transform of the images Zhang et al. [19] construct affine invariant features, which are insensitive to noise, in order to establish point correspondence. Several Fourier domain based methods [20, 21] represent images in a coordinate system in which the affine transformation is reduced to an anisotropic scaling factor, which can be computed using cross correlation methods. Govindu and Shekar [22] develop a framework that uses the statistical distribution of geometric properties of image contours to estimate the relevant transformation parameters. Main advantages of these methods is that they do not need point correspondences across views and images may also differ by the overall level of illumination. A novel one-element voxel attribute, the distance-intensity (DI) is defined in [23] . This feature encodes spatial information at a global level, and the distance of the voxel to its closest object boundary, together with the original intensity information. Then the registration is obtained by exploiting mutual information as a similarity measure on the DI feature space. For matching 2D feature points, [24] reduces the general affine case to the orthogonal case by using the means and covariance matrices of the point sets, then the rotation is computed as the roots of a low-degree complex coefficients polynomial. Another direct approach [25] extends the given pattern to a set of affine covariant versions, each carrying slightly different information, and then extract features for registration from each of them separately. The transformation is parameterized at different scales, using a decomposition of the deformation vector field over a sequence of nested (multiresolution) subspaces in [26] . An energy function describing the interactions between the images is then minimized under a set of constraints, ensuring that the transformation maintains the topology in the deformed image. Manay et al. [27] explore an optimization framework for computing shape distance and shape matching from integral invariants, which are employed for robustness to high-frequency noise. Shape warping by the computation of an optimal reparameterization allows this method to account for large localized changes such as occlusions and configuration changes. In [28] a method for identifying silhouettes from a given set of Radon projections is presented. The authors study how the Radon transform changes when a given 2D function is subjected to rotation, scaling, translation, and reflection. Using these properties, the parameters of the aligning transformation are expressed in terms of the Radon transform. In [9] a computationally simple solution is proposed to the affine registration of gray level images avoiding both the correspondence problem as well as the need for optimization. The original problem was reformulated as an equivalent linear parameter estimation one having a unique and exact solution. However, the method relies on the availability of rich radiometric information which is clearly not available in the binary case.. In this paper, as an extension of our previous work [29] , we propose a novel method which provides an accurate and computationally simple solution to the affine registration of planar shapes. The main difficulty with binary images is that they do not contain radiometric information, only the foreground pixel coordinates are available for the registration algorithm. We will show how the binary registration problem can be formulated as the solution of a system of polynomial equations obtained by integrating a set of polynomial functions over the shape domains. The proposed method provides a direct solution without established correspondences or optimization. Moreover, the robustness of the resulting algorithm in the presence of an i.i.d. Gaussian noise on the point coordinates as well as segmentation errors are also demonstrated. On the other hand, being an area-based method, it is sensitive to occlusions. Comparative tests on partially occluded shapes reveal, however, that other area-based state of the art methods cannot cope with occlusion either. Finally, we demonstrate the performance on real images and apply the method to align pairs of hip prosthesis X-ray images.. This paper organizes as follows. In Section 2, we present our approach and the proposed algorithmic solution. Then in Section 3, we will analyze the robustness of the proposed method in the presence of an additive Gaussian noise on the pixel coordinates. Finally, experimental results and comparative tests are presented in Section 4. In summary, the error caused by an i.i.d. additive Gaussian noise on the point coordinates of the observation is as follows: An experimental analysis of the noisy case is presented in Section 4.2. Our findings suggest that the proposed algorithm can cope with noisy observations up to as high as σ 1 = σ 2 = 10 noise levels. In this paper, we have presented a novel approach for planar shape alignment. The fundamental difference compared to classical image registration algorithms is that our model works without any landmark, feature detection or optimization by adopting a novel idea where the transformation is obtained as a solution of a set of polynomial equations. It uses all the information available in the input images, but there is no need for established correspondences. Our algorithm is simple to implement and runs quite fast almost independently of the image size. Experimental results show that the proposed method provides good alignment on both real and synthetic images. Furthermore, it is robust in the case of noisy observations. Comparative tests show the efficiency and accuracy of our model compared to state of the art methods.. A Proof of Proposition 1 . It is obvious from the above equation that the system of equation has a degree of up to deg(p k ). Furthermore, by making use of the basic properties of the Lebesgue integral, we get Registration results on real images. For each image pair, the first two rows contain the template and observation with overlayed contours of the segmented silhouettes, while the third row shows the difference between the registered shapes and in the last row the evaluated error measure δ is given. Note that this value is related to the overlapping area hence it depends also on segmentation errors as segmented regions will never match perfectly. δ = 3.69% δ = 7.62% δ = 5.94% δ = 4.13% δ = 1.45% Fig. 6 . Registration of hip prosthesis X-ray images. Each image pair has been taken over a period of time about the same patient. The overlayed contour in the second row shows the aligned contour of the corresponding image in the first row. For each pair, we have also evaluated the δ measure.

O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B I O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B I O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B I O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B I O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O


High Throughput Disk Scheduling with Fair Bandwidth Distribution Abstract-Mainstream applications-such as file copy/transfer, Web, DBMS, or video streaming-typically issue synchronous disk requests. As shown in this paper, this fact may cause work-conserving schedulers to fail both to enforce guarantees and provide a high disk throughput. A high throughput can be, however, recovered by just idling the disk for a short time interval after the completion of each request. In contrast, guarantees may still be violated by existing time-stamp-based schedulers because of the rules they use to tag requests. Budget Fair Queuing (BFQ), the new disk scheduler presented in this paper, is an example of how disk idling, combined with proper back-shifting of request time stamps, may allow a time-stamp-based disk scheduler to preserve both guarantees and a high throughput. Under BFQ, each application is always guaranteed-over any time interval and independently of whether it issues synchronous requests-a bounded lag with respect to its reserved fraction of the total number of bytes transferred by the disk device. We show the single-disk performance of our implementation of BFQ in the Linux kernel through experiments with real and emulated mainstream applications. In this paper, we dealt with the problem of providing service guarantees while simultaneously achieving a high disk throughput in the presence of synchronous requests. This type of requests may cause work-conserving scheduler to fail to provide a high throughput, and time-stamp-based schedulers to fail to enforce guarantees. In this respect, we proposed BFQ, a new disk scheduler that combines disk idling and time stamp back-shifting to achieve a high throughput and preserve guarantees also in the presence of synchronous requests. Existing algorithms for providing a predictable disk service can be broadly divided into three groups: 1) Realtime disk schedulers [20] , 2) Proportional share or bandwidth reservation time-stamp-based disk schedulers (also known as fair-queuing schedulers), and 3) Proportional share roundrobin disk schedulers. In addition, examples of frameworks for providing QoS guarantees are Cello [21] , APEX [22] , PRISM [23] , and Argon [24] . It is worth mentioning also real-time operating systems such as the Dresden RealTime Operating System (DROPS) [5] and RT-Mach [6] , and Real-Time Database Systems (RTDBS), which are architectures for performing database operations with real-time constraints [25] .. There is no relation between any of the scheduling problems highlighted in this paper, namely loss of throughput and/or guarantees due to deceptive idleness and/or delayed arrivals, and any characteristic of the above-mentioned frameworks for QoS provisioning and RTDBSes (apart from which underlying scheduling algorithm(s) they rely on). Accordingly, after the following note about disk internal queuing, in the next sections, we focus only on each of the above-listed classes of scheduling algorithms.. Disk internal queuing can be used only if disk idling is disabled, which ultimately causes loss of guarantees with any scheduler/framework for applications issuing synchronous requests. Consider, e.g., a proportional share scheduler, and suppose that the ith application has an arbitrarily high weight. After each request R j i of the application is completed, the disk starts serving its next internally queued request, or immediately asks for a new request, without waiting for R jþ1 i to arrive. Hence, another application is served, independently of whether R jþ1 i would then happen to be the next request to serve. In the end, the guarantees assigned to the application may be easily violated. The experiments were aimed at measuring the aggregate throughput, long-term bandwidth distribution, and (shortterm) per-request completion time guaranteed by the six schedulers with the following applications/workloads: simultaneous sequential reads, Web server (emulated), DBMS (emulated), and mixed video-streaming/file reads. All these applications only issue synchronous requests on a Linux system. In addition, as discussed at the end of Section 5.3, the same results in terms of aggregate throughput would be achieved with all these applications, apart from DBMS, in case they would issue asynchronous requests. Hence, only in the DBMS case, we also showed the different performances of the schedulers with an asynchronous workload. Due to the space limitations, only a synthesis of the results is reported here. The complete results and all the programs used to generate them can be found in [16] .. We ran the experiments on a PC equipped with a 1 GHz AMD Athlon processor, 768 MB RAM, and a 30 GB IBM-DTLA-307030 ATA IDE hard drive (roughly 36 MB/sec peak bandwidth in the outer zones, $ 35 percent lower throughput in the inner zones), accessed in UDMA mode. Using this low-performance disk device helped us guarantee that the disk was the only bottleneck. Sectors were 512 bytes long (ext2 file-system). The disk was partitioned into 30 consecutive slices of equal size, the first slice covering the outer part of the disk and the last one covering the inner part. All the programs were run from an auxiliary disk. For each type of experiment and set of values of the parameters, the same experiment was repeated 20 times (the buffer cache was flushed before each experiment). The minimum, maximum, and mean value, together with its associated 95 percent confidence interval, were computed for each output quantity. In what follows any mean value v is reported in the form v AE s, where s is the semiwidth of the 95 percent confidence interval for v.

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A Fast Model for Evaluating the Detection of Selfish Nodes Using a Collaborative Approach in MANETs Abstract Mobile ad-hoc networks (MANETs) rely on network cooperation schemes to work properly. Nevertheless, if nodes have a selfish behaviour and are unwilling to cooperate, the overall network performance could be seriously affected. The use of watchdogs is a well-known mechanism to detect selfish nodes.In this paper we propose a collaborative watchdog approach, which is based on the fast diffusion of selfish nodes awareness. Then, we introduce an analytical model to evaluate the time of detection and the overhead (number of messages) of our collaborative watchdog approach for detecting one selfish node. This model is extended for the case of several selfish nodes, including a mean-max approximation for a feasible computation when the number of selfish nodes is high. The results show that a collaborative watchdog is a very efficient approach since the detection time of selfish nodes is reduced, and the overall overhead is very low.

O O O O O O O O B I O O O O O B O O O O B O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B I O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B I O O O O O O O O O O O O B I O O O O O O O O O O O O O O O O O O O B I O O O O O O O O O