Long memory and nonlinearities in realized volatility: A Markov switching approach Goal of this paper is to analyze and forecast realized volatility through nonlinear and highly persistent dynamics. In particular, we propose a model that simultaneously captures long memory and nonlinearities in which level and persistence shift through a Markov switching dynamics. We consider an efficient Markov chain Monte Carlo (MCMC) algorithm to estimate parameters, latent process and predictive densities. The insample results show that both long memory and nonlinearities are significant and improve the description of the data. The out-sample results at several forecast horizons, show that introducing these nonlinearities produces superior forecasts over those obtained from nested models. It is well known that accurately measuring and forecasting financial volatility plays a central role in many pricing and risk management problems. With high frequency intra-daily data sets becoming widely available, more accurate estimates of volatility can be obtained. Realized volatility (RV), i.e. the sum of intra-day squared returns, reduces the noise in the volatility estimate considerably compared to other volatility measures such as squared or absolute daily returns. Thus, volatility becomes in some sense observable and can be modeled directly rather than being treated as a latent process both in a GARCH or in a stochastic volatility setup.. Many empirical regularities on RV have been well documented in the recent literature and a detailed review has been provided in McAleer and Medeiros (2008b) for instance. One of the most relevant is that RV dynamics exhibits long memory or high persistence, as evidenced, amongst others, in Andersen et al. (2003) , Corsi (2009) and Koopman et al. (2005) . For this reason linear fractionally integrated models (ARFIMA) are generally used to capture this feature.. A flexible strategy to model serial dependencies for RV has been proposed in Barndorff-Nielsen and Shephard (2002) through a superposition of ARMA (1,1) processes. However, Granger and Ding (1996) found out that persistence in volatility tends to be non constant over time and in particular Longin (1997) provided evidence of an usually higher level of persistence when volatility is low, thus suggesting presence of nonlinearities.. On the other hand, it is well known that long memory can be overestimated when regime shifts or structural breaks are not taken into account. In fact these are confounding factors and distinguishing between them can be rather troublesome (Diebold and Inoue, 2001 ). However, recent statistical tests aiming at disentangle the effects of long memory and level shifts has been proposed in Baillie and Kapetanios (2007) and in Ohanissian et al. (2008) . In particular, Baillie and Kapetanios (2007) found presence of nonlinearity together with long memory in realized volatilities for currencies, whereas Ohanissian et al. (2008) , in their empirical application, provide evidence that realized volatility of exchange rates such as DM/$ and Yen/$ is properly described by a true long memory process. This latter result seems to be in contrast with Perron and Qu (2009) , who claim that short memory models with level shifts are appropriate to describe volatility. Similarly, Carvalho and Lopes (2007) model volatility with a short memory switching regime dynamics, Chen et al. (2008) propose a range-based threshold heteroskedastic model, whereas He and Maheu (2009) propose a GARCH model subject to an unknown number of structural breaks.. It seems to be still an open question whether to decide if long memory is spurious or not. It thus appears of obvious interest to joint modeling both features into a single time series model. In this way it is also possible to check whether the benefits of combining long memory and nonlinearities represent an improvement in forecasting accuracy.. Recently, some time series models have been suggested to combine long memory and nonlinearities to describe conditional variances. Probably, the first contributions in this direction are, respectively, Martens et al. (2004) and Hillebrand and Medeiros (2008) where they build from an ARFIMA model by allowing for smooth level shifts, day of the week effects and leverage. A different strategy has been proposed in McAleer and Medeiros (2008a) by introducing a multiple regime smooth transition extension of the Heterogeneous Autoregressive (HAR) model of Corsi (2009) .. In this paper we consider a different strategy to model abrupt changes in the conditional mean and time varying long range dependency. We base our analysis on a Markov switching model in line with the seminal work of Hamilton (1989) in which level shifts are modeled through a binary non observable Markov process and in which the parameters, including the degree of persistence, are state dependent. Persistence is introduced through a standard ARFIMA model. Furthermore, we also think it is important to include exogenous regressors in the model's specification. Following Bandi and Perron (2006) we consider the implied volatility as a predictor, since it is proven to be an unbiased long run forecast of future RV, once controlling for a fractionally cointegration relation.. We focus on Bayesian estimation techniques and goodness-of-fit indicators to assess the in-sample performance of our model. We also put particular attention to the forecasting ability of the proposed models.. We base our empirical analysis on the 5 minutes intra-daily series of Standard & Poor's 500 (S&P500) stock index over the period January 2000 to 28 February 2005. Our results evidence that implied volatility is important to predict RV and also that, in the short run, long memory together with nonlinearities improve the forecasting performance. In the long run the ARFIMA effect seems to be dominant with respect to the switching regime mechanism.. The remainder of the paper is organized as follows. Our data set is described in Section 2, whereas the Markov switching models considered are defined in Section 3. Our inferential solution is outlined in Section 4. The forecasting methodology is explained in Section 5 and empirical results based on simulated and real data are illustrated respectively in Section 6 and in Section 7.

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On the complexity of computing with zero-dimensional triangular sets We study the complexity of some fundamental operations for triangular sets in dimension zero. Using Las-Vegas algorithms, we prove that one can perform such operations as change of order, equiprojectable decomposition, or quasi-inverse computation with a cost that is essentially that of modular composition. Over an abstract field, this leads to a subquadratic cost (with respect to the degree of the underlying algebraic set). Over a finite field, in a boolean RAM model, we obtain a quasi-linear running time using Kedlaya and Umans' algorithm for modular composition.Conversely, we also show how to reduce the problem of modular composition to change of order for triangular sets, so that all these problems are essentially equivalent.Our algorithms are implemented in Maple; we present some experimental results. Triangular sets (in dimension zero, in this paper) are families of polynomials with a simple triangular structure, which turns out to be well adapted to solve many problems for systems of polynomial equations. As a result, there is now a vast literature dedicated to algorithms with triangular sets, their generalization to regular chains, and applications: without being exhaustive, we refer the reader to [24, 3, 32, 23, 37, 38] .. However, from the algorithmic point of view, many questions remain. Despite a growing amount of work [31, 28, 8] , the complexity of many basic operations with triangular sets (such as set-theoretic operations on their zero-sets, change of variable order, or arithmetic operations modulo a triangular set) remains imperfectly understood.. The aim of this paper is to answer some of these questions, by describing fast algorithms for several operations with triangular sets, extending our previous results from [34] . In particular, we will focus on the relationship between these problems and some classical operations on univariate and bivariate polynomials, called modular composition and power projection. To describe these issues with more details, we need a few definitions.

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A novel low-power embedded object recognition system working at multi-frames per second One very important challenge in the field of multimedia is the implementation of fast and detailed Object Detection and Recognition systems. In particular, in the current state-of-the-art mobile multimedia systems, it is highly desirable to detect and locate certain objects within a video frame in real time. Although a significant number of Object Detection and Recognition schemes have been developed and implemented, triggering very accurate results, the vast majority of them cannot be applied in state-of-the-art mobile multimedia devices; this is mainly due to the fact that they are highly complex schemes that require a significant amount of processing power, while they are also time consuming and very power hungry. In this article, we present a novel FPGA-based embedded implementation of a very efficient object recognition algorithm called Receptive Field Cooccurrence Histograms Algorithm (RFCH). Our main focus was to increase its performance so as to be able to handle the object recognition task of today's highly sophisticated embedded multimedia systems while keeping its energy consumption at very low levels. Our low-power embedded reconfigurable system is at least 15 times faster than the software implementation on a low-voltage high-end CPU, while consuming at least 60 times less energy. Our novel system is also 88 times more energy efficient than the recently introduced low-power multi-core Intel devices which are optimized for embedded systems. This is, to the best of our knowledge, the first system presented that can execute the complete complex object recognition task at a multi frame per second rate while consuming minimal amounts of energy, making it an ideal candidate for future embedded multimedia systems. Multimedia is a technology which has been enjoying considerable attention for many years. Multimedia involves the use of multiple forms of media such as audio, images and video in an integrated manner. A computer user interacts in a daily basis with a huge amount of multimedia data mostly through the internet. Multimedia usually carries useful but raw and unsorted information. It is an emerging need for the user to be able to search in a content base through multimedia content such as images and video. For this reason object recognition gives today multimedia applications new potentials that enable the previously poorly sorted media data to be classified and unified with the rest of today information.. In the Content-based image retrieval applications we try to find all images in a larger set of images which have a specific content. The content can be specified for example in terms of similarity relative a target image (e.g., find all images similar to image X or find all images showing the specific object depicted in image X).. Google recently introduced image search based on content as well as the Google's Goggles android application which enables the user to search real world objects by taking a picture. In a desktop environment already Apple's iPhoto and Google's Picasa featuring face detection and recognition technology in order to classify user's photos according to the persons depicted in the photo.. By extending the above object recognition approaches we are also now able to search objects or persons in large video streams; this is called Content based Video Retrieval and it is a very important application for numerous future multimedia systems. This problem can also be defined as a generalized Video Mining problem where we are trying to discover patterns and objects, in an unsupervised way, within video streams. In such video streams the amount of data that has to be analyzed can be tremendous; this is the case for example for YouTube or for all the TV broadcast networks. In general, the classification of thousands of video hours is impossible to be done in a supervised way and even in an unsupervised way the processing time is a crucial factor. Moreover, such a classification is also needed in state-of-the-art mobile multimedia systems which can display and store several Gigabytes of high-quality video; in such systems low energy consumption is also crucial.. Moving to the game industry we recently met alternative input systems based around a webcam-style peripheral such as the Microsoft Kinect [XBOX] .. 1 Kinect enables users, by recognizing their gestures (i.e., performing certain object recognition tasks), to control and interact with the Xbox 360 game console without the need to touch a game controller. Such gesture recognition systems are also being introduced in different embedded multimedia systems including interactive shop windows, portable game consoles and smart TVs.. The critical factors in all those discrete yet interrelated applications are the accuracy of the system and well as its response time. Moreover, since in many cases those object recognition systems are utilized in mobile environments the energy consumption is also a critical issue. The object recognition problem itself is a complex and computational intensive task for today microprocessors no matter if they are power-hungry desktop CPUs or low-power embedded ones. This complexity further increases since totally or slightly different objects can appear anywhere in the image (in different light conditions) and the system should also report where those objects are (i.e., localize them). As a result, even when executed on high-end mobile CPUs, such applications cannot be performed at multi-frame per second rates, whereas when optimized for speed they typically give only target specific responses (i.e., a car found in coordinates x,y) .. This article presents a complete generalized object detection system implemented on a reconfigurable device that can execute a very efficient such algorithm at a rate of more than one frame per second while consuming about 60 times less energy than a low-power CPU executing the exact same algorithm.. We clearly demonstrate that such a complex task can, probably for the first time, be addressed by a single chip solution running on minimal power; this is achieved by exploiting the heterogeneity of custom hardware and a low power embedded CPU. We present such a single chip prototype in this article while our ideal target single-chip platform is the already announced by Xilinx 2 Zynq-7000 single chip device featuring a dual-core ARM CPU and FPGA reconfigurable logic in the same silicon.. Moreover, due to the programmability features of the FPGAs, the system can support the requested object recognition tasks only when needed; based on the multimedia applications' requirements, at any given time, this same FPGA can also perform other similar tasks that are executed efficiently on reconfigurable devices such as 3D image reconstruction [Hadjitheophanous et al. 2010] or face detection [Gao and Lu 2008] also met in various embedded multimedia applications. This article describes a complete low-power embedded object recognition system that can support multi frames per second speeds and can efficiently be utilized in multimedia systems performing complex object recognition (such as fixed and mobile game consoles or tomorrow's smartphones). The system implements one of the most efficient Object Recognition Algorithms, the Receptive Fields Cooccurrence Histograms (RFCH) one. This system is highly flexible, since it is not fixed to a specific image size, but instead it is designed to support image sizes up to High Definition (HD), allowing it to be utilized in numerous distinct multimedia applications. Additionally, the number of features and the number of clusters that are supported are not fixed either, and they can be altered by just changing the software part of the system which offers even greater flexibility. Moreover, the programmability feature of the FPGA allows our system to be efficiently instantiated in numerous distinct multimedia applications; for example in a high-accuracy multi-object mode it can utilize our algorithm whereas the reconfigurable sub-system can be rapidly re-programmed to execute a simple face detection algorithm when such a demand is triggered by the end-application. The presented system, when implemented on a relatively low-cost Virtex-6 FPGA connected to an ARM, can be up to 27 times faster than the conventional software approach whereas it consumes about two orders of magnitude less energy than either a low-power CPU executing the exact same algorithm or the recently introduced low-power multi-cores that are optimized for embedded applications.

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A performance and energy comparison of convolution on GPUs, FPGAs, and multicore processors Recent architectural trends have focused on increased parallelism via multicore processors and increased heterogeneity via accelerator devices (e.g., graphics-processing units, field-programmable gate arrays). Although these architectures have significant performance and energy potential, application designers face many device-specific challenges when choosing an appropriate accelerator or when customizing an algorithm for an accelerator. To help address this problem, in this article we thoroughly evaluate convolution, one of the most common operations in digital-signal processing, on multicores, graphics-processing units, and field-programmable gate arrays. Whereas many previous application studies evaluate a specific usage of an application, this article assists designers with design space exploration for numerous use cases by analyzing effects of different input sizes, different algorithms, and different devices, while also determining Pareto-optimal trade-offs between performance and energy. Over the past decade, microprocessors have often been unable to meet the rapidly increasing performance and power requirements of many applications. As a result, designers are increasingly using accelerator devices such as multicores, FieldProgrammable Gate Arrays (FPGAs), and Graphics Processing Units (GPUs), which have been widely shown to have significant performance advantages for various domains [Che et al. 2008; Owens et al. 2008; Kestur et al. 2010; Guo et al. 2004] .. For designers using accelerator devices, one significant design challenge is choosing the appropriate device for a given application. Existing device characterization studies show that using the correct device is critical because metrics for different devices vary widely for different applications [Che et al. 2008; Underwood et al. 2004] . A significant amount of previous work has addressed this problem via application studies for different devices [Kestur et al. 2010; Baker et al. 2007; Underwood et al. 2004; Gac This work is supported by the National Science Foundation grant CNS-0914474. Authors' addresses: J. Fowers (corresponding author), G. Brown, J. Wernsing, G. Stitt, Electrical and Computer Engineering Department, University of Florida, 32611; email: jfowers@ufl.edu. Permission to make digital or hard copies of part or all of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies show this notice on the first page or initial screen of a display along with the full citation. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, to republish, to post on servers, to redistribute to lists, or to use any component of this work in other works requires prior specific permission and/or a fee. Permissions may be requested from et al. 2008] . However, one common limitation of such studies is a focus on a particular usage scenario, such as a particular type of input, input size, or environment (e.g., high-performance computing or embedded systems). Although such analysis provides useful information, the results can cause designers to use inappropriate devices or algorithms for different usage cases.. One important observation for many application studies is that there is often no optimal device and algorithm for an application. Instead, the design space generally consists of a set of Pareto-optimal trade-offs between performance, power, energy, cost, etc. This problem is further complicated by the fact that many of these trade-offs are dependent on the particular use case (e.g., different input sizes and constraints). Given the multitude of accelerator devices, potential algorithms, and usage scenarios, instead of just considering speedup for a particular device, application studies should ideally determine Pareto-optimal devices and algorithms for common usage scenarios. Such analysis enables application designers to rapidly perform design space exploration to choose the best device and algorithm to meet the constraints for their intended usage of an application.. In this article, we perform such an analysis of 1D convolution for various systems consisting of multicores, FPGAs, and GPUs. Although convolution is generally a kernel used as part of larger applications, the presented analysis is critical due to the common usage of convolution in digital-signal processing on all types of accelerator devices in both high-performance computing and embedded systems. In addition to considering multiple systems, the analysis considers both time-domain and frequency-domain algorithms combined with novel optimization strategies, while also determining Pareto-optimal devices for numerous input sizes. This research enables a designer with a predetermined kernel, signal, performance, and energy use case to easily select the device and algorithm which best suits their application. Additionally, the presented Pareto-optimal analysis provides a basis for a more general comparison of CPUs, GPUs, and FPGAs in digital-signal processing. This article presented a detailed exploration of floating-point 1D convolution implementations, which included analysis of different devices, input sizes, optimizations, and algorithms. As expected, frequency-domain implementations generally outperformed time-domain implementations, except for when either the signal or kernel size was small. The frequency-domain multicore implementation was fastest when signal and kernel sizes were small and accelerator devices could not amortize high bus-transfer costs. For large signal sizes and kernel sizes below 12050, the standalone (i.e., not PCIe) frequency-domain FPGA implementation was the fastest implementation, although the GPU achieved comparable performance. For large kernel and signal sizes, GPU frequency-domain performance was up to 15.7x faster than a CPU baseline. For energy efficiency, the best implementations for each input size were similar to the performance results, with the FPGA frequency-domain implementation trailing the GPU by a small margin for many inputs. Interestingly, the standalone FPGA achieved the best energy consumption for almost all input sizes. Such results motivate emerging architectures that integrate GPUs and CPUs on a single chip, which could improve energy and data transfer. CPU-GPU processors will be evaluated in future work along with larger FPGAs and integer operations. This section includes a more detailed analysis and explanation of all performance comparisons, in addition to a discussion of limitations and future work.. 5.5.1. Performance Analysis. After analyzing all results, we determined that the performance of a convolution implementation for a given input size can be explained by: The chart in Figure 10 shows how these four factors vary in importance with input parameters (lower numbers have a higher impact). Setup cost is most relevant for small input sizes and is amortized by computation as either input parameter increases. Kernel cost increases in importance for time-domain and overlap-save implementations as kernel size increases. Parallelism increases in importance as the signal size increases, giving an advantage to massively parallel systems that can process much of a signal simultaneously through either a pipeline or a multitude of threads. Clock speed is of greatest importance for medium kernel and signal sizes when the other factors are not at peak importance.. The success of the multicore implementations where both signal and kernel size are small can be explained by the minimal setup cost due to a lack of off-chip bus transfers. The 8-threaded implementation was slower than the single-threaded implementation for very small input sizes because of the setup cost of thread synchronization, and was faster in all other cases because of the increased available parallelism. Performance for both frequency-domain CPU implementations was highest when kernel sizes were small due to the overlap-save optimization.. The FPGA implementations had the highest startup costs due to the slow PCIe x8 bus, and the lowest clock speed at 175 MHz, but the highest parallelism. Therefore, the frequency-domain implementation saw its best performance for small to medium kernel sizes and medium to large signal sizes and the time-domain implementation was best for small kernel sizes and medium to large signal sizes.. The standalone FPGA execution of the frequency-domain implementation had far higher performance for all inputs, but especially so for small signal sizes because the setup cost represented a large percentage of performance in that region.. The GPU implementations saw high performance in all cases except when both inputs were small, due to the GPU's startup cost from the PCIe x16 bus. High performance in the remaining regions is due to the combination of relatively medium clock speed and parallelism.. The time-domain GPU implementation had its best performance when either input parameter was small due to the high cost of large kernel sizes on the time-domain algorithm. The frequency-domain implementation on the GPU performed best at medium to large signal sizes and all kernel sizes because of the strength of the GPU at executing FFTs. Performance was slightly higher for the small kernel sizes due to the computation savings of the overlap-save optimization.. The overlap-save optimization provided significant performance improvements for the frequency-domain implementations, particularly the CPU and GPU implementations that were able to select FFT sizes over 32,768. The optimization was most effective for small kernels and large signals. For example, a single-FFT approach with a 64M signal and 50-element kernel requires an 128M FFT, or 3.6 billion operations. In contrast, the optimization on the CPU selects an FFT size of 16K, which would only require 1.9 billion operations, for a speedup of 1.9x. The optimization becomes less effective as kernel size increases. For example, for a kernel size of 19550, the optimized approach would select a 256k FFT for a savings of only 1.4x at 2.6 billion operations.. 5.5.2. Limitations and Future Work. Although this study evaluates numerous usage scenarios of convolution, it is not feasible to evaluate all scenarios in a single paper. The presented results are still useful to designers by simply eliminating devices that exceed constraints that we did not evaluate.. One issue that we did not consider was device cost. The largest FPGAs cost around $10,000 [Altera 2011a ], which is significantly higher than most GPUs and multicores, which are typically under $1,000. Specialized GPUs can cost more than $2,000 [NVIDIA 2011c ]. It is difficult to come to generalized conclusions regarding performance per dollar as FPGA device costs vary significantly based on the size.. Another issue that we did not consider was application design complexity and design time. Although it is difficult to determine the exact design time of each implementation, we estimate that the CPU and GPU examples were created and optimized in approximately two weeks per implementation. The FPGA implementations required several months due to the need for custom register-transfer-level VHDL code, in addition to learning the FPGA board's interface. Although a designer familiar with an FPGA board could create such implementations significantly faster, in our experience the productivity for the FPGA was significantly lower than the other devices, which is supported by numerous previous studies [Che et al. 2008; Li et al. 2011; Merchant et al. 2008; Nelson et al. 2008 ].. An additional limitation was that the evaluated Stratix III E260 FPGA used an older 65nm process compared to a 55nm GPU and45 nm CPU. Although ideally we would have analyzed identical technology nodes, it is difficult to select devices that use the same technology node due to different devices having different process schedules. For example, a GPU using the same process as a microprocessor would be commercially available years after the microprocessor, at which point designers would likely be using newer microprocessors. Therefore, we focused on the fastest devices available at the same time, which represents practical equivalency. The selected devices represent the state-of-the-art for 2009.. We also did not evaluate integrated, single-chip CPUs and GPUs because at the time of this study, such architectures were not common and were targeted only towards low-power embedded systems [NVIDIA 2011b] . Performance improvements for standalone FPGAs compared to PCIe FPGAs were significant and in many cases superior to all other devices, which could indicate that similar improvements are possible for integrated GPUs. Similarly, we did not consider ASICs, although a performance bound for the same circuits could be roughly estimated using faster clock frequencies.. Furthermore, we only considered floating-point operations. FPGA studies have shown order of magnitude improvements for integer operations . Therefore, for cases where floating-point precision is not required, FPGAs may have significantly better results, which we will investigate as future work. Numerous application case studies have been done for FPGAs [Bae et al. 2011; Guo et al. 2004; Le et al. 2011] and GPUs [Huang et al. 2009; Owens et al. 2009; Xiao et al. 2009 ]. To our knowledge, there has not been a thorough analysis of convolution across accelerator devices, although Koehler et al. [2012] performed a partial execution time analysis of time-domain convolution on both GPUs and FPGAs. This article extends that previous work by considering multiple algorithms, optimizations, and input sizes, while also evaluating energy.. Recent studies have also compared applications across CPUs, GPUs, and FPGAs. In Che et al. [2008] , the authors evaluated Gaussian Elimination, Data Encryption Standard, and Needleman-Wunsch, and showed that FPGAs had the best performance for all input sizes, but with higher development costs. A matched filter algorithm was evaluated on a Cell processor, FPGA, and GPU in Baker et al. [2007] , which concluded that the Cell provided the best performance and energy efficiency, but the GPU provided the best performance per dollar. Araya-Polo et al. [2011] implemented reverse time migration on a CPU, FPGA, GPU, and Cell and found that the accelerators all outperformed the CPU at the expense of significantly greater development effort. A comparison of BLAS algorithms was conducted in Kestur et al. [2010] , which showed that FPGAs achieved comparable performance to other devices, but improved energy efficiency by 2.7x to 293x. Gac et al. [2008] presented a comparison of devices for highspeed 3D tomography where GPUs achieved the best performance. Li et al. [2011] compared device performance for Fourier-domain optical coherence tomography, for which FPGAs had significant performance advantages. Williams et al. [2010] performed a device characterization analysis of numerous devices, showing that FPGAs were superior in terms of computational density for bit-level operations, in addition to 16-bit and 32-bit integer operations. GPUs provided better computational density for single-precision and double-precision floating-point operations, but FPGAs had better computational density per watt. Overall, these previous works show that GPUs and FPGAs often have significant speedup over CPUs, but that the best device depends heavily on the application and use case.. In addition to evaluating device performance for different applications, numerous studies have identified Pareto-optimal implementations via design space exploration including accelerator selection [Fowers et al. 2012] , hardware/software partitioning [Eles et al. 1997] , tuning configurable resources in a system-on-a-chip [Givargis et al. 2002] , among others. This article complements previous work by performing a detailed analysis of convolution for different devices, different algorithms, different input sizes, and for usage scenarios including both high-performance computing and embedded systems. The experiments section is organized as follows. We first define the hardware used in the experiments and the tests conducted (Section 5.1). We then evaluate each implementation individually and present the performance as speedup over a common baseline, highlighting particular areas of strength for each (Section 5.2). Next, we compare the execution times (Section 5.3) and energy consumptions (Section 5.4) of all implementations. Lastly, we discuss the results and determine Pareto-optimal tradeoffs for a variety of use cases (Section 5.5). All multicore and GPU implementations were tested using a Red Hat Enterprise 5 Linux 64-bit server with 12GB of RAM, a 2.67 GHz Intel Xeon 4-core W3520 with 8 processing threads via Hyper-Threading, and a GeForce 295 PCIe x16. FPGA implementations were tested on Node 5 of the Novo-G reconfigurable supercomputer [George et al. 2011 ], which uses a GiDEL ProcStar III accelerator board with Stratix III E260 and a PCIe x8 interface connected to a 2.27 GHz quad-core Xeon E5520 CPU and 6GB of RAM. All results include data transfer times between devices. Section 4 provides addition information for each setup. Although the slower Novo-G processor potentially makes the FPGA results pessimistic, the CPU was responsible for less than 1% of execution time.. In addition to the PCIe FPGA experiments, we also evaluated the same FPGA frequency-domain implementation for standalone FPGAs where the data source was directly connected to the device, which is common in embedded systems. The performance for a standalone FPGA system was approximated by subtracting the bus-transfer times from the total execution times. We confirmed that such an approximation had a worstcase 10% error via VHDL simulations, although most input sizes had smaller error. Although ideally we would have also evaluated single-chip CPU/GPU processors, at the time of writing, GPUs capable of performing convolution without an external CPU do not come close to the performance for the GeForce GTX 295. Conversely, the Stratix III E260 used in these experiments is used commercially for performing standalone convolutions. Future work will extend the evaluation for emerging devices, such as single-chip CPU/GPUs [Brookwood 2010 ].. All implementations were tested using signal sizes between 128 and 64M and kernel sizes between 50 and 32550. The signal cap was established due to memory constraints for the FPGA board (2GB) and the kernel cap was established due to the FFT size limit in the FPGA. For clarity of discussion we will refer to small signal sizes as the range 128-16K, medium as 16K -512K, and large as 512K -64M; small, medium, and large kernel sizes correspond to ranges of 50-10K, 10K-20K, and 20K-32550, respectively. Such kernel sizes are representative of common convolution usage. For example, FIR filters commonly use small kernels with 32-128 elements. Audio applications may use kernels corresponding to a second-long impulse response, which at 44.1 kHz represents a kernel size of 44100. Based on our analysis of applications, smaller kernels tend to be more common, but different applications use kernels across this entire range.. The baseline for all speedup comparison was the single-threaded, frequency-domain CPU implementation, which we believe represents the most common implementation that achieves useful performance across all signal and kernel sizes. Although we compare this baseline to different algorithms and devices, such a comparison is fair because Pareto-optimal trade-offs are affected by both device and algorithm. Therefore, to allow application designers to select the most appropriate Pareto-optimal design for their intended usage scenario, we evaluate all combinations of devices and algorithms.

O B O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B O O O O O O O O O O O O O O O O O O O O O O O O B O O O O O O O O O O O O O O O O B O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B O O O O O O O O O O O O O O O O O O O O O O O O O O O O B O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O 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O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B O O O O O O O O O O O O O O O O O O O B O O O O O O O O B O O O O O O O O O O O O O O O O O O O O O B O O O O O O O O O O O O O O O O O O O O O O O B O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B O O O O O O O O O O O O O O O O O O O O O O B O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O 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Design and power optimization of CMOS RF blocks operating in the moderate inversion region In this work the design of radiofrequency CMOS circuit blocks in the 910MHz ISM band, while biasing the MOS transistor in the moderate inversion region, is analyzed. An amplifier design tool is presented. This tool shows that it exists an optimum in the power consumption for a given gain. Different technologies are compared, using the proposed tool, regarding its performance in terms of gain and power consumption in the design space I D -g m /I D . The frequency limit of the applied transistor model is discussed and comparisons with simulations using BSIM3v3 are presented. Implementation of a power amplifier and a VCO at 910 MHz in 0.35µm CMOS technology and experimental results are also shown. Nowadays, the development of low-cost, low-power radiofrequency (RF) devices grows up rapidly, specifically in personal communication equipments and networks of sensors. This kind of communications is implemented using new standards, which are characterized by short range links (usually below 100m) and reduced power consumption (since the devices are powered from batteries).. It is known that optimum power consumption of analog circuits can be reached in the moderate inversion region [1] , where is obtained a good trade-off between a high g m /I D and a not too large transistor size and hence reduced parasitic capacitances values. Traditionally the operation at this optimum was restricted to low frequency applications, since the transconductance values required for operation at RF implied currents that, in order to operate in moderate inversion, lead to enormous transistor sizes. This big transistor would imply high parasitic capacitances that would jeopardize the advantage of an increased g m /I D ratio in moderate inversion. However, what is "low" frequency and "high" frequency is technology dependent. Particularly, in current, deep sub micron technologies, the reduction of parasitic capacitances and the increase of the current drive by the increase of the gate oxide capacitance per unit area, make that RF frequencies are, in fact, "low" frequency. This idea, that this work exploits, has been also advanced in works such as [2] . In [3] , this idea is applied in the design of RF low noise amplifiers. However, as far as we know, there is no published work, where a tool for analyzing the trade-offs and possible optimum solution has been presented.. In this work this improvement is applied to design power amplifiers and voltage controlled oscillators (VCO). It will be presented a software tool which can be used either to design amplifiers, obtaining an optimum design and showing the trade off between amplifier's gain and power consumption, or to evaluate the performance of a particular technology at a desired frequency. With this tool it has been checked the good performance of a 0.35µm technology at 910MHz and it has been designed a VCO and a power amplifier of 40V/V gain and 5.5mA current consumption. In this work it has been presented a flexible tool to help in the design of low power RF blocks. It has also been shown the existence of an optimum inversion level which gives the minimum power consumption for a given gain, or equivalently, the maximum gain for a given consumption. This optimum inversion level appears in different types of amplifiers and in varied technologies. Finally it has been shown the feasibility of working, with 0.35µm technologies at 910MHz, in moderate inversion, which gives a better compromise between speed and consumption. Using the described methodology, the amplifier shown in Fig.7 has been designed.. The final design parameters are:

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Distributed multilevel optimization for complex structures Abstract Optimization problems concerning complex structures with many design variables may entail an unacceptable computational cost. This problem can be reduced considerably with a multilevel approach: A structure consisting of several components is optimized as a whole (global) as well as on the component level. In this paper, an optimization method is discussed with applications in the assessment of the impact of new design considerations in the development of a structure. A strategy based on fully stressed design is applied for optimization problems in linear statics. A global model is used to calculate the interactions (e.g., loads) for each of the components. These components are then optimized using the prescribed interactions, followed by a new global calculation to update the interactions. Mixed discrete and continuous design variables as well as different design configurations are possible. An application of this strategy is presented in the form of the full optimization of a vertical tail plane center box of a generic large passenger aircraft. In linear dynamics, the parametrization of the component interactions is problematic due to the frequency dependence. Hence, a modified method is presented in which the speed During the development of many technical products, an automated scheme to evaluate the possible advantages and disadvantages of new design considerations is highly desired. This wish has lead to the development of a flexible optimization scheme.. A fully stressed design (FSD)-based strategy allows the optimization of up to hundreds of design variables and very complex separable structures (Haftka and Gürdal 1992; Berke 1992; Sobieszczanski and Loendorf 1972) . This is achieved by separating the structure optimization problem into a large number of subproblems known as component optimization problems. The scheme consists of a structure evaluation, where the interactions between the components (e.g., component loads) are calculated and component optimizations where the components are optimized separately while taking into account the interactions. The iterative process of structure evaluation and component optimization is continued until convergence.. Please note that the term FSD refers to the historical background of the method. In the application, both buckling and strength constraints are present. Hence, the component is not necessarily fully stressed, but optimized up to a point where constraints prevent further improvement. The FSD scheme is inherently suited for parallel computing, and it is efficient in cases where a change in one component has a small influence on the optimum of the other components. An important disadvantage of this scheme is the fact that it will not result in an optimal solution unless certain strict conditions are met. For information on convergence and optimality in the current test cases, the reader is referred to Sections 3.4 and 4.4.. In the component optimization strategy, the objective and constraint functions are approximated based on finite element (FE) results using neural networks (NNs). The optimum in this approximate optimization problem is identified with a genetic algorithm (GA).. This paper is built up as follows. In Section 2, the component optimization strategy is described, and in Section 3, an application concerning an aircraft vertical tail plane (VTP) is discussed. In Section 4, component mode synthesis (CMS) is introduced into the optimization strategy to make it suitable for problems in linear dynamics. A benchmark problem derived from the placement of sensors and actuators in active structural acoustic control (ASAC) is used as an example. Finally, conclusions are given in Section 5. A multilevel optimization strategy has been developed for the design optimization of complex structures. Based on the current research, the following conclusions can be drawn.. -The current strategy allows overnight optimization of the VTP center box of a commercial aircraft. -Promising results have been obtained for a small benchmark problem in linear dynamics. -The objective functions and constraints must be chosen with some care because the multilevel strategy can converge to strongly suboptimal solutions unless certain strict conditions are met. -A comparison between the NN-based approximate model and other response surface methodologies as well as different selection algorithms requires further study. The optimization strategy has provided good results in a short amount of time. However, it is stressed that there are no guarantees that the global-local strategy will provide optimal or even useful results for general structures and other load cases. On the other hand, the technique leads to an exact optimum for statically determinate trusses subject to only stress and minimum gage constraints if the areas of a cross-section are the design variables. For such trusses, the FSD optimality criterion can be stated as follows:. For the optimum design, each member of the structure that is not at its minimum gage is fully stressed under at least one of the design load conditions (Haftka and Gürdal 1992) .. This statement has been adapted to serve as an intuitive optimality criterion for the VTP problem, which can be stated as follows:. In the test problem, the components are optimized according to one global objective function, and all constraints are bounds. For this specific case, a theoretical study indicates that a converged result is at least a local minimum in the global scale, but convergence cannot be proven for practical cases (Wind 2005) . No guarantees of optimality can be given if the constraints of one component depend on design variables of the other components. The proposed strategy has been implemented and applied to the VTP problem. Twenty MS Windows machines with a clock speed of 2.6 GHz have been used. Convergence has been achieved after 3 structure iterations using a fixed number of 35 component iterations.. With an average FE solving time of approximately 1 min per panel, the optimizations completed in 8-9 h. This runtime is merely an indication because runtimes depend strongly on the mesh sizes as well as the number and speed of the machines available. Nevertheless, it is concluded that overnight optimization of a complete structure is possible provided that enough computers are available. The resulting design configurations of the spar optimization are given in Fig. 6 . In the results of the rear spar, it can be seen clearly that large and heavily loaded panels have more stiffeners than small and mildly loaded panels. Although the effects are less dramatic, similar trends can be observed for the front spar.. The optimizations are performed on a single MS Windows machine with a clock speed of 1.67 GHz. Using a fixed number of 25 component iterations, the runtime has been in the order of magnitude of a few hours. The design variables used for FE are selected with a simple rule. In the first iteration, the GA result is used for FE analysis. If the error between the NN and FE result is larger, then a certain preset value then the NN is retrained and the GA is used again to estimate the optimum in the next iteration. If the difference is smaller, then a random design is supplied to the next FE analysis. Several more advanced algorithms have been tested on a benchmark problem, but this algorithm demonstrated the best behavior in preventing the stagnation of the optimization process. The result of an optimization with a broadband excitation in a frequency range of 50-320 Hz is given in Fig. 10a where the reference result and the optimization result of the global-local strategy are indicated by white and black boxes, respectively. The reference result has been obtained by applying the component optimization strategy on the global level. It can be seen that the resulting locations are different. As the structure is approximately symmetrical, the objective function has two minima with a very small difference in cost. The global-local strategy has outperformed the reference, but the margin is negligible, even for the purpose of testing the strategy. In Fig. 10a , the radiated sound power achieved in the optimization of component 1 is given as a function of the structure iteration number. It has remained constant from the second iteration onward, but the design variables switched more or less randomly between the final result and its mirror image until structure iteration 12. After this iteration, no significant changes are observed. A second optimization is performed with a harmonic excitation of 50 Hz. Again, a reference result is superimposed on the global-local optimization result, but results are almost indistinguishable in this case. The convergence of global-local iteration is more gradual in this case, and the optimal result is obtained at approximately structure iteration 15. It is important to note that the units considered for sound power in Fig. 10 are different.. Several other optimization runs have been performed. In the harmonic case, the optimization can exhibit limit cycling behavior or converge to the optimal result depending on the initial design. In cases where the excitation is broadband, the convergence behavior is more robust: Each optimization has converged to a point that is at least a local minimum from the global point of view. The general component optimization strategy has been presented in Sections 1 and 2.3, but a number of problem-dependent matters are discussed in this section.. On the global level, all components are assembled in a large FE model with a very coarse mesh. Although this model does not predict the local buckling load and stress accurately, the boundary forces on all components are predicted well. These forces are derived and used in the component optimization.. The objective function in the component optimization is panel weight. This function is not approximated by the NN but calculated analytically for each solution generated in the GA. Furthermore, when a feasible design has been found, a new design cannot be an improvement on the component level unless it is lighter. Hence, the requirement that each new design must be lighter than the best feasible solution found for that component is implemented as an explicit constraint in the GA. This selection rule combined with a rule that enforces the evaluation of different design configurations prevents stagnation of the optimization process. Finally, separate NNs are used for skin, spar, and rib panels because they have different load-cases and design configurations. This means that each NN can be identified uniquely by a design configuration number and a panel type.

O B I O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B I O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B I I O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B I O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O


Smooth relevance vector machine: a smoothness prior extension of the RVM Abstract Enforcing sparsity constraints has been shown to be an effective and efficient way to obtain state-of-the-art results in regression and classification tasks. Unlike the support vector machine (SVM) the relevance vector machine (RVM) explicitly encodes the criterion of model sparsity as a prior over the model weights. However the lack of an explicit prior structure over the weight variances means that the degree of sparsity is to a large extent controlled by the choice of kernel (and kernel parameters). This can lead to severe overfitting or oversmoothing-possibly even both at the same time (e.g. for the multiscale Doppler data). We detail an efficient scheme to control sparsity in Bayesian regression by incorporating a flexible noise-dependent smoothness prior into the RVM. We present an empirical evaluation of the effects of choice of prior structure on a selection of popular data sets and elucidate the link between Bayesian wavelet shrinkage and RVM regression. Our model encompasses the original RVM as a special case, but our empirical results show that we can surpass RVM performance in terms of goodness of fit and achieved sparsity as well as computational performance in many cases. The code is freely available. In nonlinear regression a function of interest y is approximated by a linear combination of the input vector, x, projected onto a (typically fixed) set of nonlinear basis func- (1). Thus, provided with a set of N training input vectors {x n } N n=1 and corresponding targets t n , the task is to find the M + 1 weights w m that will yield the most faithful approximation to y. For simplicity the following exposition will assume that the data is mean centered, so that we can omit the bias w 0 and work with M weights. Choosing φ(x) ≡ x regains linear regression. Frequently the basis functions are derived from kernels centered at each of the observations φ m (x) = K(x m , x) in which case the regression is known as kernel regression, however, the basis functions may be quite general functions, including for example wavelets, and may form an over-complete dictionary.. Writing the true signal, y, as an N -vector and w m , the weights, as an M-vector, (1) is conveniently written as y = w, with the basis functions arranged as the columns of the N × M design matrix . Employing the standard assumption of zero-mean Gaussian noise in the target observations, we have:. Demanding a sparse representation in the space spanned by a suitable set of such basis functions provides a general strategy to adjust the bias/variance trade-off in regression and classification problems, as is evinced by the state-of-the-art results achieved by support vector machines (SVMs) in a variety of domains (e.g. Schölkopf and Smola 2002 ). An important additional benefit of sparsity is that it also often translates into significant computational savings. Whilst we have concentrated on the fRVM framework (Faul and Tipping 2002) , since our implementation is based on it, it is worth mentioning that the fRVM is by no means the only attempt to provide a scheme that is computationally more efficient than the original, "slow" RVM (Tipping 2000) and might be adapted to incorporate a smoothness prior; we draw attention to the Subspace EM (SSEM) algorithm (Quiñonero-Candela 2004) and a version based on a Bayesian interpretation of backfitting (D'Souza et al. 2004) .. Before examining more closely the issue of different choices for p(α), we mention other work pertinent to RVM learning. Wipf and Rao (2004) provide a principled justification for approximating the hyperparameter posterior p(α, σ 2 |t) with the point estimates α MAP and σ MAP . Quiñonero-Candela (2004) offers an augmentation to the RVM at the prediction stage to ameliorate the problem of artificially low predictive variances for test-points that are far off the "centres" of the "relevance vectors" (i.e. the final set of basis functions for well-localized kernels such as gauss)-an issue that may be regarded as an undesirable sideeffect of sparsity. Figueiredo (2003) provides an illuminating perspective on sparse Bayesian learning and presents an Expectation Maximization algorithm for learning the coefficients w directly, treating the α as hidden data.

O B I I O B I O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B I I O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B I O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B I O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B I O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O


Authoring transformations by direct manipulation for adaptable multimedia presentations In this paper, we present a method for authoring generic and adaptable multimedia presentations. This method relies on document transformations. For the currently available tools, designing the XML content and the transformation sheets is a tedious and error prone experience. We propose a framework based on an incremental transformation process. Incremental transformation processors represent a b etter alternative to help in the design of both the content and the transformation sheets. We believe that such authoring tools are a first step toward fully interactive transformation-based authoring environments. In this paper, we focus on the authoring of transformation sheets by direct manipulation. In particular, we study the authoring of transformations for the XSLT language defined at the World Wide Web Consortium. The advent of the XML standard at the World Wide Web Consortium has triggered the definition of an incredible amount of vocabulary groups in different areas of content representations. Although these vocabulary groups are defined separately and designed for a variety of purposes such as content structure descriptions, layout languages, vector graphics or mathematical formulas rendering, they can also be inter-mixed in a single and same document. These vocabulary groups share the same encoding language at the syntactic level thanks to XML and are combined using another XML companion standard called XML Namespaces [11] . However, in most cases the content is encoded using third party DTD's while the resulting documents are encoded using rendering vocabularies such as XSL [3] . The result is an increasing diversity of document classes and vocabularies and a lack of authoring tools to cope with this diversity.. Two categories of existing authoring tools for editing XML content have been identified. Authoring tools that belong to the first category deal with rendering vocabularies. These tools are designed specifically for one or many rendering vocabularies. For example, Adobe illustrator allows the authoring of SVG documents, Grins [12] is designed for authoring SMIL documents, Amaya [ 18] allows the authoring of MathML 1 , SVG 2 and XHTML 3 . In the second category, authoring tools are generic and deal with any kind of XML documents. Therefore, the only way to edit XML documents is through a lower-level text representation or at most through an enhanced representation such as a graphical tree. More recently, some authoring tools [14] give the author the ability to edit and attach style to XML elements. This association simplifies the authoring of a document by making the XML content more accessible to the user through the graphical interface. However, style sheets remain of a very limited help when considering more complex presentations, in particular those obtained by transformation. Moreover, authoring style sheets is relatively easy unlike transformation languages which are more complex to edit in a convenient way.. Another feature that must be addressed when presenting XML documents is the adaptation of document content to the current presentation context. This operation must take into account user capabilities, user preferences, physical location, network and system resources, etc. A lot of current content adaptation architectures are based on transformation process [ 6] [16] . However, as we said previously, transformation sheets are hard to design. The challenge is then to provide authoring tools to help the author to design adaptable documents by authoring transformation sheets.. In [17] we have presented a framework that allows the editing of XML documents through one or more of its rendered presentations. In order to produce and to edit complex and adapted presentations, in particular multimedia presentations, this framework is based on an incremental transformation process. In [17] we used this framework for editing source documents of transformations. The next step is to extend this framework for editing transformation sheets.. The goal of this paper is to present a method that allows authoring of transformations by direct manipulation. In particular, this paper focuses on the XSLT transformation language. XSLT [21] is a general-purpose transformation language that is used in many applications: data conversion, database queries, presentation generation, etc. The latter is probably the most popular application directly visible to the end user. In this paper, we focus on this kind of applications. We consider the reader familiar with the XSLT language. The vocabulary used in this paper that is related to XSLT is defined in the section 3.4.. The remainder of the paper is organized as follows: in the second section, we describe existing tools that allow the authoring of transformations and the authoring of queries. In the third section, we present the context of work presented in this paper. In particular, we describe the framework based on an incremental transformation processor. In the fourth section, we give an overview for authoring transformation sheets by direct manipulation. This overview is described through an editing use case study. In the fifth section, we describe the transformation rules that are generated for a subset of editing operations. In the last, section we give some conclusions and draw some perspectives. We have classified the related work in two categories. The first category represents authoring tools designed specifically for XSLT. The second category gathers work about the authoring of presentation models (such as style sheets) and the connection with a database. The latter covers the XPath [20] aspect of the XSLT language.

O O O O O O O B O O O O O O O O O O O O O B O O O O O O O O O O O O O O B O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B I O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B O O O O O O O O O O O O B O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B O O O O O B O O O B O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B I O O O O O O O O O B I O O B O O O O B I O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B I O O O O O O O O B O O O O O O O B O O O O O O O O O O O O O O O O O O O O O O B I O O O O O O O O O O O O B O O O O O O O O O O O O B O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B I O O O O O O O O O O O O O O O O O O O O O O O O B O O O O O O O O O O O O O O O O O O O O O O B O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B O O B O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B O O O O O O O O O O O B O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B I O O O B O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B O


Simulated time for host-based testing with TTCN-3 Prior to testing embedded software in a target environment, it is usually tested in a host environment used for developing the software. When a system is tested in a host environment, its real-time behaviour is affected by the use of simulators, emulation and monitoring. In this paper, the authors provide a semantics for host-based testing with simulated time and propose a simulated-time solution for distributed testing with TTCN-3, which is a standardized language for specifying and executing test suites. The paper also presents the application of testing with simulated time to two real-life systems. Software testing is of key importance for the quality of embedded systems. Although no testing regime can find all errors, testing helps to detect bugs and increases confidence in the trustworthiness of a system. Prior to testing in a target environment, embedded software is usually tested in a host environment used for its development. When being tested, embedded software is executed to check whether it meets certain quality requirements and to detect failures. The requirements are expressed in the form of test cases that are executed by a test system. The test system sends stimuli to the system under test (SUT) and checks whether the response of the SUT matches one of the responses expected by the test case. Note that both the SUT and the test system can be distributed. If a failure is detected, the cause of the failure should be found by debugging and corrected. Wrong timing of stimuli from the test system to the SUT may lead to failures even in a correct system. Therefore, a test system should be an adequate representation of a real environment of the SUT with respect to time behaviour.. Testing is an incremental process where components and (sub-)systems are integrated and tested. Many software and hardware components and services are not available for testing until the end of the development process. When testing a component or a sub-system, a host environment makes use of simulation and emulation techniques to execute it. Monitoring and instrumentation are used to observe the external behaviour of the embedded software. Ideally, the effect of simulation, emulation and monitoring on the real-time behaviour should be negligible, not influencing the test results. However, solutions satisfying this requirement are often expensive and product specific. In case the effects of simulation, emulation and monitoring significantly change the real-time behaviour, real-time testing might miss to find errors or might report non-existing errors.. A simple naive solution would be to test with scaled time. Scaled time is calculated as the initial time plus the product of a time factor and the difference between the current physical time and the initial moment. The larger the factor, the faster the tests can be executed. Choosing the optimal time factor is, however, not trivial. The effects of a host environment are difficult to calculate, particularly for distributed systems. Moreover, they may vary through the execution. Thus, using scaled time does not always solve the problem.. In this paper, the authors propose a time semantics for testing with simulated time. In simulated time, the system clock is modelled by a discrete logical clock and time progression is modelled by a tick action. Simulated time is suitable for testing and verifying a class of systems where delays are significantly larger than the duration of normal events in the system. When used for testing, simulated time ensures that an SUT and a test system agree on time and advance time together. For testing distributed systems, simulated time facilitates debugging by synchronizing time progression at all nodes and providing the ability to stop or suspend time progression. Simulated time thus improves the controllability of testing and debugging. In general, simulated time can be seen as scaled time with a dynamic time factor that is determined automatically. Since the factor is dynamic, the approach is efficient in the case of varying computation times.. The authors have chosen the Testing and Test Control Notation version 3 (TTCN-3) to implement the proposed solution for testing with simulated time. TTCN-3 is a language for specifying test suites. It has a syntax and operational semantics standardized by the European Telecommunications Standards Institute (ETSI) [2] [3] [4] . TTCN-3 was originally developed for real-time testing of telecommunication systems. A TTCN-3 test executable has predefined standard interfaces [4] [5] [6] . Standardized interfaces of TTCN-3 allow the definition of test suites on a level independent of a particular implementation or platform, which significantly increases the reuse of TTCN-3 test suites. TTCN-3 interfaces provide support for distributed testing, which makes TTCN-3 particularly beneficial for testing embedded systems. TTCN-3 has already been successfully applied to the testing of embedded systems not only in telecommunication but also in automotive and railway domains [7, 8] TTCN-3 with different time semantics [3] . Implementing simulated time using existing TTCN-3 interfaces is, however, not straightforward. In this paper, the authors provide a framework for host-based simulated-time testing with TTCN-3. They define the semantics of simulated time for host-based testing with TTCN-3 and discuss which time constraints can be adequately tested in a host environment with simulated time. Furthermore, the authors provide a solution for implementing simulated time for a distributed TTCN-3 test system and argue its correctness. The solution allows the execution of TTCN-3 test suites in real and in simulated time without having to change them.. The rest of the paper is organized as follows. In Section 2, some aspects of host-based testing of timed systems are discussed. In Section 3, the authors define a semantics for host-based testing with simulated time and discuss the adequacy of test results for host-based testing with real and with simulated time. In Section 4, two applications of host-based testing with simulated time are illustrated: one from the railway domain and the other from the telecom domain. Section 5 provides a brief survey on the general structure of a distributed TTCN-3 test system and formalizes requirements to a distributed TTCN-3 test system with simulated time. Section 6 contains requirements to the entities of a TTCN-3 test system which enable implementing simulated time. Section 7 presents a solution for simulated time host-based testing with TTCN-3. Section 8 concludes the paper and provides a discussion of related work.

B I O O B O B O O B O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B O B I O O O O O O O B O B O O O O O O O O O O O O O O O O O O B O B I O O O O O B O O O O O O O O O O O O B O O O O O B O O O O O O O O O O O O O O O B O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B O O O O O O O O O O O O O O O O O O O O O O O B O O O O O O O O B O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B I O O O O O O O O O O O O O O O O O O O O O O O O O O O B O B I O B I O O O O O O O O O O O O O O O O O O O B I O O O B O O O O O O O O O O O O O O O O O O O O O O O B B I O O O O O O O O O O O O O O O O B B I B I O O O O O O O O O O O O O O O O O O O B I O O O O O B O O O O B I O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B O O O O O O B O O O O O O B O B I B O O O O O O O O O O O O O O O O O O O O O O O O O O B O O O O O B O O O O B O O O O O O O O O O O O O B O O O O O O O O O O O O O O O O O O O O O O B O O B O O O O O B O O B O O O B O O B O O O O O O O B O O O O O O O O O O O O O O O O B O O O O O O O B I O O B O O O O O O O O O O O O O O O O B O B O O O O O B I O O B O B O O O O O O O O O O O O O O B I O O O O O O O O B I O O O B O O O O O O O O O O O O B O O O O O O B I O O O O O O O O O O O O O O O O O O O O O B O O O O O O O O O O O O O O O B O B I O O O O O O O O O B O O O O B I O O O O O O O B O B I O O O O O O O O O O O O B O O O O O O O O O O O O O O B O O O O O O O O B O O O B I O O O O O O O O O B O O O O O B I O O O O O O B I O B O B O O O O O O O O O O O O


On synthesis of easily testable (k, K) circuits Abstract-A (k; K) circuit is one which can be decomposed into nonintersecting blocks of gates where each block has no more than K external inputs, such that the graph formed by letting each block be a node and inserting edges between blocks if they share a signal line, is a partial k-tree. (k; K) circuits are special in that they have been shown to be testable in time polynomial in the number of gates in the circuit, and are useful if the constants k and K are small. We demonstrate a procedure to synthesise (k; K) circuits from a special class of Boolean expressions. THE problem of determining a test for a stuck-at fault in an arbitrary combinational circuit is known to be NP-complete [4] . Given this negative result, researchers have tried to come up with restricted classes of circuits for which the problem is known to be solvable in polynomial-time. One example of a class of circuits for which the stuck-at fault testing problem is solvable in polynomialtime is the class of (k; K) circuits introduced by [3] . They showed that for this class of circuits, the testing problem can be solved in Oð2 kK g 2 Þ where k; K are constants and g is the number of gates in the circuit. Membership in this class of circuits is based on certain structural properties of circuits. Since the identification of this class of circuits, research has focused on determining if an arbitrary circuit can be classified as a (k; K) circuit for small values of k and K. Unfortunately, this problem has also been shown to be NP-complete by [9] , thus appearing to severely limit the usefulness of the (k; K) class of circuits in real-life.. In this paper, we investigate a synthesis procedure for (k; K) circuits. More specifically, we determine how to take an arbitrary logic function obeying certain restrictions and produce an easily testable circuit belonging to the (k; K) class. The logic expressions implemented by our class of circuits are of the type F 1 < op > F 2 < op > F 3 < op > :::F n , where each F i represents arbitrary combinational logic on no more than K distinct primary inputs and op stands for another specific logic function. Our synthesis algorithm first checks if an intuitively defined term graph of the given logic expression is a special type of graph called a partial k-tree. If this is the case, then, it finds an embedding of the term graph into a full k-tree. Then, we work with this k-tree to establish an appropriate order of combining terms and come up with a (2k À 1; K þ 1) implementation of the logic expression. In this paper we examined the question of synthesising (k; K) circuits. These circuits are known to be easily testable provided k and K are small. We require the input expressions to be of the form F 1 < op > F 2 < op > . . . F n , where op refers to some operator that is the same throughout the expression and the F i s are Boolean functions on no more than K distinct inputs.

O B O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B I O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B I B O O O O O O O O O O O O O O O O O O O O O O O O O B O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B O O O O O O O O O O O O O O O O O O O O O O O B O O O O O O O O O O O O O O O O O B O O O O O B O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O


Bin packing with fixed number of bins revisited Abstract. As Bin Packing is NP-hard already for k = 2 bins, it is unlikely to be solvable in polynomial time even if the number of bins is a fixed constant. However, if the sizes of the items are polynomially bounded integers, then the problem can be solved in time n O(k) for an input of length n by dynamic programming. We show, by proving the W[1]-hardness of Unary Bin Packing (where the sizes are given in unary encoding), that this running time cannot be improved to f (k) · n O (1) for any function f (k) (under standard complexity assumptions). On the other hand, we provide an algorithm for Bin Packing that obtains in time 2 O(k log 2 k) +O(n) a solution with additive error at most 1, i.e., either finds a packing into k + 1 bins or decides that k bins do not suffice. The aim of this paper is to clarify the exact complexity of Bin Packing for a small fixed number of bins. An instance of Bin Packing consists of a set of rational item sizes, and the task is to partition the items into a minimum number of bins with capacity 1. Equivalently, we can define the problem such that the sizes are integers and the input contains an integer B, the capacity of the bins.. Complexity investigations usually distinguish two versions of Bin Packing. In the general version, the item sizes are arbitrary integers encoded in binary, thus they can be exponentially large in the size n of the input. In the unary version of the problem, the sizes are bounded by a polynomial of the input size; formally, this version requires that the sizes are given in unary encoding.. In the general (not unary) case, a reduction from Partition shows that Bin Packing is NP-hard [7] . Thus it is hard to decide whether a given set of items can be packed into exactly two bins. Apart from NP-hardness, this has a number of other known implications. First of all, unless P = NP, it is impossible to achieve a better polynomial-time approximation ratio than 3/2, matching the best known algorithm [16] .. In contrast, however, there are much better approximation results when the optimum number of bins is larger [4, 12] . De la Vega and Lueker [4] found an asymptotic polynomial-time approximation scheme (APTAS) for Bin Packing with ratio (1 + )OP T (I) + 1 and running time O(n) + f (1/ ) (if the items are sorted). To bound the function f , one has to consider the integer linear program (ILP) used implicitly in [4] . This ILP has 2 O(1/ log(1/ )) variables and length 2 O(1/ log(1/ )) log n. Using the algorithm by Lenstra [13] or Kannan [11] , this ILP can be solved within time 2

B I O O O O O O O O B I O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B I O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B I O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B I O O O O O O O O O O B I O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B I O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B I O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B I O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O