An Efficient Scan Tree Design for Compact Test Pattern Set Abstract-Various designs of scan paths based on tree-like structures have recently been suggested for reducing test application time or test data volume in today's high density VLSI circuits. However, these techniques strongly rely on the existence of a large number of compatible sets of flip-flops under the given test set, and therefore, are unsuitable for highly compact test sets generated by efficient ATPG tools. In this paper, to circumvent this problem, a new two-pass hybrid method is proposed to design an efficient scan tree architecture. Given a compact test set, compatibility relationships among the flip-flops are first explored, and a graph-based heuristic algorithm is employed to construct a scan tree with minimal incompatibility. Next, the same combinational ATPG tool is rerun to generate a new test set satisfying the logical constraints on the secondary inputs imposed by the structure of the scan tree. To cover the remaining hard-to-detect faults, if any, a few test vectors are chosen from the original test set for application in the serial mode. Experimental results on various benchmark circuits demonstrate that the proposed algorithm outperforms the earlier methods in reducing the total test application time significantly without any degradation of fault coverage. The controllability and observability of a digital circuit can be increased by various well known designfor-testability (DfT) techniques. Among them, the most popular one is the widely used serial full scan methodology, which transforms a sequential circuit to its combinational parts in test mode. Although the full-scan method reduces the cost of test generation and provides high fault coverage, the inherent serial nature of the scan path increases the test application time and energy consumption in test mode significantly. The number of clock cycles needed to scan in/out the test data is equal to the product of the number of test patterns and the length of the scan chain. Hence, the test application time (also the test data volume) can be reduced either by reducing the number of test patterns, or by reducing the scan chain length, as used in tree-based scanpath architectures. A fewer number of test patterns may however, reduce the fault coverage. On the other hand, a compact test set with high fault coverage has relatively smaller number of don't cares in the test patterns, which increases the incompatibity relationships among the flip-flops. This in turn, causes the design of scan-tree inefficient, i.e., results in a larger depth of the tree. Thus, the above two key factors *The charges of two extra pages will be paid if the paper is selected.. being conflicting in nature, make the scan tree design problem hard to solve.. There are many existing methods that are used to tackle the problem of reducing the test application time. One approach is to configure the scan elements into multiple scan chains [1] , [2] . But this increases the number of scan-in and scan-out pins needed during test. Hybrid test generation techniques are introduced in [3] , [4] . But, these techniques are computationally expensive and are not suitable for large sequential circuits. A scan-based BIST is introduced in [5] , where a scan chain is partitioned into multiple segments by inserting XOR gates between two adjacent scan segments. Test responses of each scan segment can be observed through an XOR tree. However, this technique do not address the problem of testing embedded cores used in SoC design [6] . The Illinois Scan Architecture (ILS) was recently proposed to circumvent this problem [7] , [8] , [9] . The ILS is shown to be useful both for the standalone chip and when used in embedded cores. It does not require any additional test pin other than the ones used in full scan.. In the ILS scan, several branches of the scan paths emanate from the scan-in pin of the circuit, which may cause overloading. An alternative approach, called scan tree has been proposed [10] , [11] , [12] , [13] to reduce the test application time or test data volume. In such a scan architecture, the structure resembles a tree, where one cell drives other scan cells as in a tree. Like ILS, a scan tree does not require any additional test pin other than the ones used in full scan. The same test data bit must arrive in the scan cells, which have an equidistant common ancestor cell. Thus, in a scan tree architecture, all the bits in each of the test vectors that are to be loaded in the scan cells (flip-flops) lying at the same depth of the tree, must be compatible (i.e., non-conflicting) among themselves. If the above condition is satisfied, the corresponding scan cells are also called compatible. The effectiveness of the scan tree depends on the correlation among the test data of the different scan cells. The test application time in the case of a scan tree depends on the number of test patterns and the depth (length of the longest path in the tree) of the scan tree. The latter strongly depends on the compatibility of the flip-flops under the given test set. An increase the compatibility among the flipflops is likely to result in a decrease in the scan tree depth. Most of the previous works for generating the scan tree use a non-compact test patterns (containing many don't cares), in order to obtain a large number of compatible relationships. In [10] , the don't care values of the test patterns are changed appropriately to generate the scan tree. In these cases, the number of test patterns considered is usually large (compared to those generated by an optimized ATPG tool achieving the same fault coverage). Hence, these methods fail to yield a scan tree of substantial depth for a highly optimal compact test set, and cannot exploit the advantage of using such a test set of small volume.. In this paper, a new graph-based two-pass algorithm is proposed to design the scan tree architecture. The present algorithm is particularly applicable for a compact test set, where the compatibility among the flip-flops is usually low. First, the compatibility relationships among the flip-flops are explored for a given test set, and a scan tree architecture is designed with minimal incompatibility. Next, the same ATPG tool is run again to generate a new test set satisfying the logical constraints on the secondary inputs imposed by the scan tree designed above. These vectors will be applied in the tree mode. To cover the remaining hard-to-detect faults, if any, a few test vectors are chosen from the original test set for application in the serial mode. Experiments on various benchmarks reveal very encouraging results.. The rest of the paper is organized as follows. In Section II prior works on scan tree designs are reviewed. In Section III the proposed algorithm is explained and in Section IV, a technique to cover hardto-detect faults is described. Section V presents some experimental results on benchmark circuits. Section VI concludes the paper.

O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B I O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O


An Effective GML Documents Compressor As GML is becoming the de facto standard for geographic data storage, transmission and exchange, more and more geographic data exists in GML format. In applications, GML documents are usually very large in size because they contain a large number of verbose markup tags and a large amount of spatial coordinate data. In order to speedup data transmission and reduce network cost, it is essential to develop effective and efficient GML compression tools. Although GML is a special case of XML, current XML compressors are not effective if directly applied to GML, because these compressors have been designed for general XML data. In this paper, we propose GPress, a compressor for effectively compressing GML documents. To the best of our knowledge, GPress is the first compressor specifically for GML documents compression. GPress exploits the unique characteristics of GML documents to achieve good performance. Extensive experiments over real-world GML documents show that GPress evidently outperforms XMill (one of the best existing XML compressors) in compression ratio, while its compression efficiency is comparable to the existing XML compressors. As GML is becoming the de facto standard for geographic data storage, transmission and exchange, more and more geographic data exists in GML format. In applications, GML documents are usually very large in size because they contain a large number of verbose markup tags and a large amount of spatial coordinate data. In order to speedup data transmission and reduce network cost, it is essential to develop effective and efficient GML compression tools. Although GML is a special case of XML, current XML compressors are not effective if directly applied to GML, because these compressors have been designed for general XML data. In this paper, we propose GPress, a compressor for effectively compressing GML documents. To the best of our knowledge, GPress is the first compressor specifically for GML documents compression. GPress exploits the unique characteristics of GML documents to achieve good performance. Extensive experiments over real-world GML documents show that GPress evidently outperforms XMill (one of the best existing XML compressors) in compression ratio, while its compression efficiency is comparable to the existing XML compressors. key words: Web-based GIS, geospatial data, GML, compression, algorithm, performance evaluation To cope with the problems of interoperability and heterogeneous integration among GISs and their applications, the Open Geospatial Consortium (OGC) published the Geography Markup Language (simply GML) specification [1] , which offers a vendor-neutral framework for the definition of geo-spatial application schemas and objects. Nowadays, GML is becoming the de facto standard format for geospatial data exchange and transmission, more and more geographic information exists in GML format.. GML has many advantages [2] , but similar to the use of XML, GML's flexibility and extensibility also come at a cost: naive use of GML can easily make GML documents be extremely verbose due to the unlimitedly adopting of hierarchical markup and structural information, long elements and attribute names, verbose hyperlinks and namespaces, and sharply storage-volume expanding caused by spatial data (coordinates) transformation from compact binary format to text string. Such redundancy consequently incurs substan-tial storage and transmission cost, affects both query processing and data exchange. Therefore, it is particularly important to explore effective compression techniques that can considerably reduce storage and transmission cost of GML data. However, current research on GML mainly deals with the issues of storage [3], [4], query processing [5], [6] , and information integration [7], [8] . Little work has done for GML compression.. Considering that GML is a special case of XML, a straightforward way of GML compression is to apply the existing XML compressors directly to GML documents. In recent years, a number of XML compressors have been developed, including XMill [9] , XMLPPM [10], XGrind [11], XPRESS [12], XQzip [13], etc. However, these compressors have been designed for general-purpose XML documents (mainly text-rich documents). Quite different from text-rich XML documents, GML documents are data-rich, they contain not only a lot of verbose structural information, but also a large volume of spatial information, i.e, spatial coordinates. We can not expect optimal performance by simply applying general-purpose XML compressors. It is necessary to propose GML specific compressors by exploiting the unique characteristics of GML documents to achieve better compression performance.. In this paper, we explore compression technique for GML documents, and propose a GML specific compressor. We call this compressor GPress, which is the abbreviation of An approach specifically for GML documents compression is proposed, which exploits the features of GML documents to achieve better compression performance than the existing XML compressors.. The proposed approach is implemented and a GML specific compressor (i.e. GPress) is built. . It is based on a regrouping strategy that groups XML text strings with respect to their meaning and exploits similarities between those text strings for compression.. The compression principles of XMill are: compressing structure and data separately, data values are grouped with regard to meaning, and compressed by corresponding semantic compressors. XMill typically achieves about twice the compression rate of conventional text compressors like gzip without sacrificing speed. However, XMill still has some disadvantages [16] , such as unqueriable compressed output and human intervention required for specifying containers, etc.. XMLPPM was proposed by J. Cheney [10], it uses a technique called Multiplexed Hierarchical Modeling (MHM) that is based on SAX encoding and Prediction by Partial Match (PPM) encoding.. In XMLPPM, an input XML document is modelled as a stream of SAX events. The tokens in the SAX event stream are then processed by a set of four PPM coding models corresponding to different syntactic contexts. Although XMLPPM can achieve good compression ratio (sometimes even better than XMill), its efficiency is un-satisfactory.. XGrind was introduced by P.M. Tolani and J.R. Haritsa [11] . It does compression by two main techniques: metadata compression and enum-type attribute value compression, and retains the structure of the original XML document at the same time. Experimental results indicate that its compression ratio improves as the number of enumerated attributes increases. It has lower compression ratio than XMill, but it is a queriable XML compressor that supports querying the compressed document, especially suitable for resource limited computing devices like palmtops.. XPRESS was proposed by J.-K. Min et al [12] . It supports direct and efficient evaluations of queries on compressed data, and adopts a novel encoding method called reverse arithmetic encoding, which is an efficient path encoding method that yields fewer overheads of partial decompression and quicker path evaluation. XPRESS achieves significant improvement on query performance for compressed XML data and reasonable compression ratio.. XQzip was brought forth by J. Cheng and W. Ng [13] . It supports querying compressed XML data by imposing an indexing structure called Structure Index Tree (SIT) that can be used to remove the duplicate structures . XQzip compresses XML data into a sequence of blocks which can be decompressed individually to achieve a good performance . In addition, XQzip supports a wide scope of XPath queries such as multiple, deeply nested predicates and aggregation .. XQueC was presented as a demo by A. Anon et al at VLDB in 2003 [14] . XQueC compresses each data item individually that may result in compression ratio degradation . One important feature of XQueC is that it supports efficient evaluation of XQuery by using a variety of structure information, such as dataguides, structure tree and other indexes. However, the auxiliary structures and the pointers to the data items compressed individually may cause huge space overhead.. XComp was developed by W. Li [15] . With similar compression principles to XMill, XComp takes advantage of the self describing feature of XML to separate structure from data based on the semantics. XComp also employs a parse-compress architecture that allows parsing and compressing to be done in parallel when the document can not fit in one memory window.. All these XML compressors mentioned above are designed mainly for general XML documents compression. Certainly they can be applied to GML documents compression, but we can not expect that the performance will be satisfactory. were proposed for paper maps and other line-drawings containing curves. These methods approximate curves by a sequence of straight lines, which include vertical, horizontal, diagonal etc. Line-simplification and chain-codes often eliminate original points and add new points as a sideeffect. A typical chain-coding-based algorithm FHM (Fibonacci, Huffman, and Markov) was designed for signature compression [19] , [22] . The dictionary approach used in the FHM [20] algorithm can be used for compressing digital vector maps. Dictionary-based algorithms build a dictionary to match dictionary entries to line segments. When a dataset is decompressed, the dictionary is searched to find the data associated with the dictionary indices. Recently, Shenkhar et al proposed the clustering-based compression method for vector map [21] , [23] . This method adapts a dictionary to a given dataset, which can achieve better approximations of the original map data, so lead to lower error.. In this section, we will first indicate the differences between GML documents and XML documents, then introuce the compression principles of GPress, the architecture of GPress and the technical details of float data compression employed in GPress. Finally, we will give a rough analysis on the reason why GPress works well with GML documents.

O O B O O O B O O O O O O O O O O O O O O O O O O O O B O O O B O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B B O O B O O O O O O O O O O O O O O O O B O O O O O O O O O O O O O O O O O O O O O B O O O O O O O O O O O O O O B O B O O O O O O B O O O O O O O O O B O O O O O O O O O O O O O O O B O O O B O O O O O O O O O B O O O O O O O O O O O O O O O O O O O O B O O O B O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B B O O B O O O O O O O O O O O O O O O O B O O O O O O O O O O O O O O O O O O O O O B O O O O O O O O O O O O O O B O B O O O O O O B O O O O O O O O O B O O O O O O O O O O O O O O O B O O O B O O O O O O O O O O B I B I B B B B I O O O O O O O O O O O O O O O O O O O O O O O O O O B O O O O O O O O O O O O O O O O O O B O O O O O O O O B I O O O O O O O O O O B O B O O O O O O O O O O O O O O O O O O O O O O O O B O O O B O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B O O O O O O O O O O B O O O O O B O O O O O O O O O O O O O O O O O O O O O O O O O B B O O B O O O O O O O O O O B B O O O O O O O O O B O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B O O O O O O O O B O O O O B O O O O O O B O O B O O O O B O O O O O O O O O O O O O O O O B O B O O O O O O O B O O O O B O O O O O O O O O O O O O B O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B O B O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B O O O O O O O O O O O O O O O O O O O O O O O B O O O O O B O O O O B O O O O O O O O O O O O O O O O O O B O O O O O O O O O O O O B O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B O O O O O O B O B O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B O O O O O O O O O B O O O O O O O O O O O O B O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B O O O O O O O B O O O O O O O O O O O O O O B O O O O O O O O O O O O O O O O O O B O


Power-Aware Node Deployment in Wireless Sensor Networks Wireless sensor networks (WSNs) have attracted intense interest due to their extensible capability. In this paper, we attempt to answer a fundamental but practical question: "how should we deploy these nodes?" In most current designs, sensor nodes are randomly or uniformly distributed because of their simplicity. However, the node deployment has a great impact on the performance of WSNs. Instead of maintaining the coverage for some snapshots of a WSN, it is essential that we can provide a continuous coverage in the whole lifecycle of the WSN. We will exhibit the weakness of the uniform distribution by disclosing the fatal sink routing-hole problem. To address this problem, we propose a non-uniform, power-aware distribution scheme. Our analysis and simulation results show that the power-aware deployment scheme can significantly improve the long-term network connectivity and service quality. 226 Y. Liu et al.feasible. However, this part of the work is beyond the scope of this paper. Interested readers may refer to [5] for more details.Concerning the unique features, WSNs are inherently different from existing systems and networks. Unlike traditional mobile ad-hoc networks (MANETs), in WSNs one or a set of nodes (called sink) are designated as gateways between the networked system and users. These sinks account for the critical role of the network as their loss directly leads to the failure of the entire WSNs. Furthermore, not only the sink but the direct neighbors of the sink are also essential for network functionality. An example is shown in Fig. 1 . The shaded area represents the region containing the direct neighbors of the sink. They are required to establish and maintain the connectivity between the sink and distant data nodes. When this set of nodes fails, no data can be delivered to the sink due to the lack of forwarders and thus the whole system fails. Often the sinks are more powerful with permanent power sources. Their failure may not be frequent. However, their nearby neighbor nodes are common sensor nodes with limited resources. These nodes are vulnerable to failure (e.g., running out of energy). An interesting observation is that for most data gathering applications the forwarding workload of sensors increases inversely with their distances to the sink. A node closer to the sink usually has a higher relay workload than those of farther nodes. Accordingly, direct neighbors of the sink have the greatest transmitting workload. They are likely to deplete their energy at the very beginning. When they fail, no matter how many remaining nodes are still active, none of them can communicate with the sink. From the sink and user's perspective, the whole system fails if the sink is isolated from the rest of the sensor nodes. Such a scenario is referred to as the "sink routing-hole" phenomenon. Note that multiple sinks [6] or mobile sinks cannot eradicate the problem as many sink routing-holes will be generated accordingly. Data funneling and aggregation [7] techniques may alleviate the problem to some extent, but cannot eliminate the problem either.The main objective of our work is to provide a long-term continuous connectivity. We attempt to address the problem by designing a power-aware deployment scheme. Major attention is paid to the connectivity of the network as it is a prerequisite for other purposes such as sensing coverage. Note that without a valid data path, an active node has the same role as a dead one. The sensing area covered by unconnected nodes is still inaccessible. However, traditional approaches [8-10] do not take the differential loss of energy in different sub-areas into consideration. They have not noticed the impact of the sink routinghole phenomenon yet. Consequently, they may work well for some snapshots of the network (e.g., in the initial stage), but may not guarantee the quality of service in the whole system lifecycle. To the best of our knowledge, we are the first ones to point out the requirement of long-term continuous connectivity. We systematically study the node deployment issue in WSNs. A preliminary result was published in [11] . The full version of our investigations for the problem is presented here. Recent advances in electronics and wireless communications gave rise to sensor applications ranging from environmental monitoring and pollution detection to feature extractions [1, 2] . Battery-powered sensor nodes are integrated with sensing, local processing, and communication capabilities [3] . They are characterized as tiny devices with constrained resources. Due to large-scale deployment, recharge or reuse of sensor nodes is costly and implausible. Therefore, the power issue arises as the key of the design objective. In particular, the transceiver, including the transmitter and receiver, contributes to the greatest energy consumption [4] .. Among many challenging issues, in this paper we discuss a fundamental and practical problem, how we should deploy these sensor nodes, or what node-deployment function is an optimal for sensors. In most current designs, random and uniform distributions are the popular schemes due to their simplicity. However, as we will show later, node deployment related issues have a great impact on the system functionality and lifetime. The traditional random and uniform distributions are not suitable because of the sink routing-hole phenomenon. Instead, we propose a non-uniform, power-aware node deployment scheme which is the main focus in this work.. One may be concerned as to whether a desired node deployment function is practical to be carried out. In fact, the advances in robotics and automations have made it possible to realize an autonomous sensor deployment by unmanned aerial vehicles [5] . It enables the deployment of individual nodes and thus makes a well-designed distribution function In this paper, we attempted to answer a practical question as to how we should deploy sensors to an application field. By investigating the sink routing-hole phenomenon, we pointed out the main weakness of the random and uniform deployment. Accordingly, we proposed a non-uniform, power-aware deployment scheme based on a general sensor application model. The power-aware deployment is optimized to maintain a continuous connectivity-coverage instead of that for some particular snapshots of the network. Theoretical analysis and simulation results have shown that power-aware deployment can dramatically increase the network lifetime and improve the network service quality.. In our future work, we have mainly two directions. One is to extend our work to more complicated and specific models. Currently, our power-aware deployment scheme is derived from a simple and generic model, where the target territory is a circle centered at a single sink. We shall investigate optimal deployment schemes for other models, including the fields having irregular shapes, the sink being positioned on different places, and the scenarios with multiple sinks. The other is to extend our power-aware deployment from maintaining the connectivity coverage to provide a long-term continuous sensing coverage, which is more concerned by end users. The node deployment problem in WSNs has been discussed in previous work. In [12] , Bogdanov considered the deployment of sinks in a scenario of multiple sinks. The authors of [13, 14] proposed to relocate mobile sensors to some appropriate locations in response to the node failure and loss of sensing area. All these proposals are developed for other purposes without considerations of the impact of the sink routing-hole problem.. Other related work can be classified as:. 1. extending the sensor and network lifetime; or 2. maintaining network topology and sensing coverage of sensors.. Network lifetime has been extensively studied in the literature of MANET [15, 16] . They focus on managing data flow aiming at some optimization purposes. Mainly they are designed for MANET with different optimization goals (e.g., QoS) and are not appropriate for WSNs. For WSNs, most of the existing power-conservation schemes, such as [17] [18] [19] , try to identify those redundant nodes. By switching off their transceivers, these approaches attempt to conserve the energy of idle nodes. For example, in PEAS [9] , a node probes a specific range to determine whether it should sleep. An adaptive sleep strategy is applied to dynamically adjust the sleeping time. PEAS can maintain the network topology to a predefined density. Sleeping strategies and algorithms are indeed complementary to the work of this paper. Given an optimal deployment function of sensors, we still need sleeping strategies to save the power of idle sensors. More recently, the authors of [20] investigated schemes to prolong the network lifetime by introducing mobile relay nodes. They also noticed the sink routing-hole phenomena and the solution is to provide a mobile relay node to replace the dead node. The mobile relay node is assumed to have unbounded energy to help forward packets. Their conclusion is that the mobile nodes only need to cruise nearby the sink because they have a similar observation with us that the neighbors of the sink are the most likely to deplete their energy. However, when the mobile relay nodes replace the neighbors of the sink, the 2-hop neighbors of the sink become the bottleneck of the system lifetime. Therefore, the problem is not solved.. Existing sensing coverage algorithms can be categorized as location-dependent [8, 10, 21] or location-free approaches [9, 22, 23] . In particular, the authors of [23] studied the deployment of mobile sensors to improve the network connectivity. However, they do not consider the impact of differential loss of energy either. They may be valid in the initial stage of the network lifecycle, but will lose their functionality very soon because of the sink routing-hole problem.. Although a large amount of effort has been made to extend the network lifetime and thus the service quality, less work has focused on the node deployment related problems. In other words, the impact of inappropriate deployment functions, the optimal distribution, and the relationship between node deployment and the network service quality have not yet been investigated.

O B I O B I I B I I O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B I O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B I O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B I O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B I O O O O O O O O O O O O O O O O O O B I O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B I O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B I O O O O O O O O O O O O O O O O O O B I O O O O O O O O O O


NoC synthesis flow for customized domain specific multiprocessor systems-on-chip Abstract-The growing complexity of customizable single-chip multiprocessors is requiring communication resources that can only be provided by a highly-scalable communication infrastructure. This trend is exemplified by the growing number of Network-on-Chip (NoC) architectures that have been proposed recently for System-on-Chip (SoC) integration. Developing NoC-based systems tailored to a particular application domain is crucial for achieving high-performance, energy-efficient customized solutions. The effectiveness of this approach largely depends on the availability of an ad hoc design methodology that, starting from a high-level application specification, derives an optimized NoC configuration with respect to different design objectives and instantiates the selected application specific on-chip micronetwork. Automatic execution of these design steps is highly desirable to increase SoC design productivity. This paper illustrates a complete synthesis flow, called NetChip, for customized NoC architectures, that partitions the development work into major steps (topology mapping, selection, and generation) and provides proper tools for their automatic execution (SUNMAP, ÂpipesCompiler). The entire flow leverages the flexibility of a fully reusable and scalable network components library called Âpipes, consisting of highly-parameterizable network building blocks (network interface, switches, switch-to-switch links) that are design-time tunable and composable to achieve arbitrary topologies and customized domain-specific NoC architectures. Several experimental case studies are presented in the paper, showing the powerful design space exploration capabilities of the proposed methodology and tools. I N contrast to past projections, today the introduction of new technology solutions is increasingly application driven. As an example, let us consider ambient intelligence, which is regarded as the new paradigm for consumer electronics. Systems designed for ambient intelligence will be based on high-speed digital signal processing, with computational loads ranging from 10 MOPS for lightweight audio processing, 3 GOPS for video processing, 20 GOPS for multilingual conversation interfaces, and up to 1 TOPS for synthetic video generation [4] . This computational challenge will have to be addressed at manageable power levels and affordable costs, and a single processor will not suffice, thus driving the development of increasingly more complex Multi-Processor Systems-on-Chip (MPSoCs).. SoCs represent high-complexity, high-value semiconductor products that incorporate building blocks from multiple sources (either in-house made or externally supplied), such as general-purpose fully programmable processors, coprocessors, DSPs, dedicated hardware accelerators, memory blocks, I/O blocks, etc. Even though commercial products currently exhibit only a few integrated cores (e.g., NEC's new TCP/IP offload engine is powered by 10 Tensilica Xtensa Processor Cores [42] ), in the next few years technology will support the integration of thousands of cores, making a large computational power available. Full exploitation of the increased level of SoC integration requires new paradigms and significant improvements of design productivity, as current system architectures and design styles do not scale up to such dimensions and complexities. A relevant example regards the system architecture, whose paradigm is progressively shifting from computation-centric to communication-centric. In fact, MPSoC performance will be increasingly determined by the ability of the communication infrastructure to efficiently accommodate the communication needs of the integrated computation resources. Traditional state-of-the-art shared busses cannot meet the scalability requirements of complex MPSoCs due to the serialization of bus access requests, and turn out to be also energy-inefficient due to the broadcast communication paradigm.. A scalable communication architecture that supports the trend of SoC integration consists of an on-chip packetswitched micronetwork of interconnects, generally known as Network-on-Chip (NoC) [2] , [21] , [34] . The scalable and modular nature of NoCs and their support for efficient onchip communication potentially leads to NoC-based multiprocessor systems characterized by high structural complexity and functional diversity. It is observed in [14] that NoCbased systems are economically feasible if they can be used in several product variants, and if the design can be reused in different application areas. On the other hand, successful products must provide good performance characteristics, thus requiring dedicated solutions that are tailored to specific needs. As a consequence, the challenge lies in the capability to design hardware-optimized, customizable computation platforms for each application domain [9] .. Hardware optimization can be achieved by facilitating the integration of domain-specific computation resources in a plug-and-play design style. Standard interface sockets such as Virtual Component Interface (VCI) [43] and Open Core Protocol (OCP) [44] have been developed for this purpose and support the use of a common NoC as the basis for system integration. A relevant task of these interfaces is to make the NoC adaptive to the different features of the integrated cores (e.g., data and address bus width).. NoC architectures are pushing the evolution of traditional IC design methodologies in order to more effectively deal with functional diversity and complexity. At the application level, the key design challenge is to expose task-level parallelism and to formally capture concurrent communication in models of computation [14] . Then, high-level concurrent tasks have to be mapped to the underlying communication and computation resources. At this level, an abstract model of the hardware architecture is usually exposed to the mapping tool, so that area and power estimates can be given in the early design stage, and different objective functions (e.g., minimization of communication energy) can be considered to evaluate the feasibility of alternative mappings. For NoC-based MPSoCs, a critical step in communication mapping is the network topology selection for its significant impact on overall system performance, which is increasingly communication-dominated.. Although a lot of research efforts are being devoted to improving individual design activities, there are very few complete NoC design methodologies and CAD tools. Setting up a fully automated synthesis framework for NoCs is a nontrivial task, particularly for the case of application specific MPSoCs, where a set of heterogeneous computing and storage resources have to be interconnected to each other by means of a custom-tailored communication network. This translates into the need to provide design time instantiation of different network schemes and topologies, tailored to the specific application domain.. A library-based approach to NoC design could be an effective solution [12] , [24] , wherein predesigned soft macros are composed at instantiation time to build arbitrary topologies. However, the full exploitation of a customizable network topology requires an ad hoc design methodology spanning different levels of abstractions (from application specification to physical implementation) and deriving the most efficient NoC configuration for a given application domain.. The design methodology has to partition the design problem into manageable tasks and to define the tools and practices for those tasks. In this paper, we propose a NoC synthesis flow, called NetChip, for designing domainspecific NoCs and automating most of the complex and time-intensive design steps. Significantly, NetChip provides design support also for regular network topologies and, therefore, lends itself to the implementation of both homogeneous and heterogeneous system interconnects.. NetChip assumes that the application has already been mapped onto cores by using preexisting tools (such as [15] ) and the resulting cores together with their communication requirements represent the inputs to our NoC synthesis flow. The tool-assisted design and generation of a customized NoC-based communication architecture is the ultimate goal of NetChip, and is achieved by means of three major design activities: topology mapping, topology selection, and topology generation. NetChip leverages two tools: SUNMAP, which performs the network topology mapping and selection functions, and ÂpipesCompiler, which performs the topology generation function.. SUNMAP produces a mapping of cores onto various NoC topologies that are defined in a topology library. The mappings are optimized for the chosen design objective (such as minimizing area, power or hop delay) and satisfy the design constraints (such as area or bandwidth constraints). SUNMAP uses floorplanning information early in the mapping process to determine the area-power estimates of a mapping and to produce feasible mappings (satisfying the design constraints). The tool supports various routing functions (dimension ordered, minimum-path, traffic splitting across minimum-paths, traffic splitting across all paths) and chooses the mapping onto the best topology from the library of available ones.. A design file describing the chosen topology is input to the ÂpipesCompiler, which automatically generates the SystemC description of the network components (switches, links, and network interfaces) and their interconnection with the cores. A custom hand-mapped topology specification can also be accepted by the NoC synthesizer, and the network components with the selected configuration can be generated accordingly. The resulting SystemC code for the whole design can be simulated at the cycle-accurate and signal accurate level. The ÂpipesCompiler uses the Âpipes library, which consists of highly parameterizable network building blocks that can be tuned and composed at design time to generate the chosen topology. Thus, NetChip automates NoC mapping, selection, and generation functions of a design, thereby bridging an important design gap in building NoCs.. The rest of the paper is organized as follows: In the next section, we present the previous works in this area. In Section 3, we present the design methodology of NetChip. In Sections 4 and 5, we present the SUNMAP tool and the area-power models used in the tool. In Section 6, we present the architecture of networks components defined in the Âpipes library. We present the ÂpipesCompiler in Section 7. The NetChip design flow is used to model several video and network applications. The communication pattern in these applications differ, thereby requiring various topologies for different applications. These are presented in Sections 8.1 and 8.2. The rich design space exploration capabilities of NetChip is shown in Section 8.3. The design flow can also be used to model custom handmapped topologies and is explained in Section 8.4. In Section 8.5, we model a DSP Filter application and generate the SystemC files of the chosen topology. The resulting design is simulated at the cycle-accurate level and the simulations are checked for functional and timing correctness, validating the output of our tools. While the communication needs of a high-speed general purpose on-chip multiprocessor can be accommodated on a homogeneous fabric, heterogeneous structures are required for application-specific computing systems, wherein a set of heterogeneous computing and storage resources have to be interconnected by means of custom-tailored NoCs. In this case, an ad hoc NoC synthesis flow must include selection of the most suitable topology for a certain application domain, mapping of cores onto that topology and generation of the resulting network instance. This paper presents a NoC synthesis framework, called NetChip, wherein these issues are addressed and automated by means of proper tools, thus bridging an important design gap in building NoCs. A library of highly parameterized, design time composable network building blocks (Âpipes) is at the core of the proposed design methodology. The entire design flow has been tested with several experimental case studies, showing the rich design space exploration capabilities of this framework. He is a student member of the IEEE.. Rutuparna Tamhankar received the BE degree in electronics engineering from the University of Pune, India, in 1999 and the MS degree in electrical engineering from West Virginia University in 2001. He is currently pursuing an Engineer's degree at Stanford University and is also working at Sun Microsystems Inc., Sunnyvale, California. At Sun Microsystems Inc., he is working on timing methodology for high performance microprocessor designs. His current research includes low latency and efficient link design for network on chips. He is a student member of the IEEE.. Stergios Stergiou received the BS degree from the University of Athens, Greece, and the MS degree in computer science from the University of Patras, Greece. He is currently pursuing the PhD degree in electrical engineering at Stanford University, Stanford, California. His research interests comprise all aspects of computer-aided design of digital circuits, with particular emphasis on networks on chip. He is a student member of the IEEE.. Luca Benini is an associate professor in the Department of Electrical Engineering and Computer Science (DEIS) at the Universty of Bologna. He received the PhD degree in electrical engineering from Stanford University in 1997. He also holds visiting researcher positions at Stanford University and the Hewlett-Packard Laboratories, Palo Alto, California. Dr. Benini's research interests are in all aspects of computer-aided design of digital circuits, with special emphasis on low-power applications, and in the design of portable systems. On these topics, he has published more than 200 papers in international journals and conferences and three books. He has been program chair and vice-chair of Design Automation and Test in Europe Conference. He is a member of the technical program committee and organizing committee of several technical conferences, including the Design Automation Conference, International Symposium on Low Power Design, and the Symposiom on Hardware-Software Codesign. He is a member of the IEEE. The most advanced state-of-the-art SoC communication architectures represent evolutionary solutions with respect to shared busses. Sonics MicroNetwork [36] is a TDMA-based bus which can easily adapt to the data-word width, burst attributes, interrupt schemes, and other critical parameters of the integrated cores, while providing very high bandwidth utilization. STBUS interconnect is a high performance communication infrastructure that allows to instantiate shared busses as well as more advanced topologies such as partial or full crossbars. Although evolutionary from a topology viewpoint, these solutions can rely on advanced and highly automated design methodologies for the implementation of generic communication subsystems, allowing designers to rapidly assemble, synthesize, and verify their SoCs using the MicroNetwork or the STBUS interconnect as integration platforms.. However, the early works in [2] , [34] pointed out the need for more scalable architectures for on-chip communication and, therefore, to progressively replace shared busses with on-chip networks. Many NoC architectures have therefore been proposed in the open literature so far, but in most cases, the design methodologies and tools are still in the early stage.. One of the earliest contributions in this area is the Maia heterogeneous signal processing architecture, proposed by Zhang et al., based on a hierarchical mesh network [10] . Unfortunately, Maia's interconnect is fully instance-specific. Furthermore, routing is static at configuration time and communication is based on circuit switching, as opposed to packet switching. In this direction, Dally and Lacy sketch the architecture of a VLSI multicomputer using 2009 technology [35] . A chip with 64 processor-memory tiles is envisioned. Communication is based on packet switching. This seminal work draws upon past experiences in designing parallel computers and reconfigurable architectures (FPGAs and their evolutions) [30] , [31] , [32] .. Most proposed NoC platforms are packet switched and exhibit regular structure. An example is a mesh interconnection, which can rely on a simple layout and the switch independence on the network size. The NOSTRUM network described in [5] takes this approach: The platform includes both a mesh topology and the relative design methodology, wherein a concrete architecture is derived from a general NoC template, then application mapping follows.. The Scalable Programmable Integrated Network (SPIN) described in [3] is another regular, fat-tree-based network architecture. It adopts cut-through switching to minimize message latency and storage requirements in the design of network switches. The Linkoeping SoCBUS [39] is a twodimensional mesh network which uses a packet connected circuit (PCC) to set up routes through the network: A packet is switched through the network locking the circuit as it goes. This notion of virtual circuit leads to deterministic communication behavior but restricts routing flexibility for the rest of the communication traffic.. In [8] , the use of octagon communication topology for network processors is presented. Instead, the implementation of a star-connected on-chip network supporting plesiochronous communication among system components is described in [13] .. The Aethereal NoC design framework presented in [7] aims at providing a complete infrastructure for developing heterogeneous NoC with end-to-end quality of service guarantees. The network supports guaranteed throughput (GT) for real-time applications and best effort (BE) traffic for timing unconstrained applications. Support for heterogeneous architectures requires highly configurable network building blocks, customizable at instantiation time for a specific application domain. For instance, the Proteo NoC [12] consists of a small library of predefined, parameterized components that allow the implementation of a large range of different topologies, protocols and configurations. Âpipes interconnect [24] and its synthesizer ÂpipesCompiler [25] push this approach to the limit, by instantiating an application specific NoC from a library of composable soft macros (network interface, link, and switch). The components are highly parameterizable and provide reliable and latency insensitive operation. They represent the core of the NoC synthesis flow illustrated in this paper.. In [11] , a hierarchical approach for designing on-chip networks was presented to help designers compare different design options. Design methodologies for building irregular networks have been proposed in [18] , [20] . Pinto et al. [18] presents a heuristic for the constraint-driven communication synthesis of on-chip communication networks, while [20] describes a design methodology for finding minimal topologies that support low contention or contention-free communication for known communication patterns. In [19] , memory optimization in single chip network fabrics is explored.. The problem of mapping cores onto NoC architectures is addressed in [22] , [23] , [26] , [27] . In [22] , a branch-andbound algorithm is used to map cores onto a mesh-based architecture with the objective of minimizing energy and satisfying the bandwidth constraints of the NoC. A simple dimension-ordered routing is assumed in the work. In [23] , the authors extend the above work for other deadlock free minimal path routing algorithms. In [26] , fast algorithms for mesh NoC architectures under different routing functions (minimum path, split-traffic) and delay/bandwidth constraints are presented.. The design methodology and tools presented in this paper aim at providing MPSoC designers with a framework for the rapid selection and synthesis of application-specific NoC architectures. While still allowing the comparison and generation of regular network topologies, our NoC design framework supports the synthesis of customized irregular topologies, and bridges a gap in a largely unexplored research area.

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Spacetime Texture Representation and Recognition Based on a Spatiotemporal Orientation Analysis Abstract-This paper is concerned with the representation and recognition of the observed dynamics (i.e., excluding purely spatial appearance cues) of spacetime texture based on a spatiotemporal orientation analysis. The term "spacetime texture" is taken to refer to patterns in visual spacetime, ðx; y; tÞ, that primarily are characterized by the aggregate dynamic properties of elements or local measurements accumulated over a region of spatiotemporal support, rather than in terms of the dynamics of individual constituents. Examples include image sequences of natural processes that exhibit stochastic dynamics (e.g., fire, water, and windblown vegetation) as well as images of simpler dynamics when analyzed in terms of aggregate region properties (e.g., uniform motion of elements in imagery, such as pedestrians and vehicular traffic). Spacetime texture representation and recognition is important as it provides an early means of capturing the structure of an ensuing image stream in a meaningful fashion. Toward such ends, a novel approach to spacetime texture representation and an associated recognition method are described based on distributions (histograms) of spacetime orientation structure. Empirical evaluation on both standard and original image data sets shows the promise of the approach, including significant improvement over alternative state-of-the-art approaches in recognizing the same pattern from different viewpoints. M ANY commonly encountered visual patterns are best characterized in terms of the aggregate dynamics of a set of constituent elements, rather than in terms of the dynamics of the individuals. Several examples of such patterns are shown in Fig. 1 . In the computer vision literature, these patterns have appeared collectively under various names, including turbulent flow/motion [1] , temporal textures [2] , time-varying textures [3] , dynamic textures [4] , and textured motion [5] . Typically, these terms have been used with reference to image sequences of natural processes that exhibit stochastic dynamics (e.g., fire, turbulent water, and windblown vegetation). In the present work, the broader class that includes stochastic as well as simpler phenomena (e.g., orderly pedestrian crowds, vehicular traffic, and even scenes containing purely translating surfaces) when viewed on a regional basis is considered in a unified fashion. The term "spacetime texture" is used herein in reference to this broad set to avoid confusion with previous terms that focused on various subsets and thus grouped dynamic patterns (e.g., smooth and stochastic patterns) in an artificially disjoint manner.. The ability to discern dynamic patterns based on visual processing is of significance to a number of applications. In the context of surveillance, the ability to recognize dynamic patterns can serve to isolate activities of interest (e.g., biological movement and fire) from distracting background clutter (e.g., windblown vegetation and changes in scene illumination). Further, pattern dynamics can serve as complementary cues to spatial appearance-based ones to support the indexing and retrieval of video. Also, in the context of guiding the decisions of intelligent agents, the ability to discern certain critical dynamic patterns may serve to trigger corresponding reactive behaviors (e.g., flight and pursuit).. The goal of the present paper is the introduction of a unified approach to representing and recognizing a diverse set of dynamic patterns with robustness to viewpoint and with ability to encompass recognition in terms of semantic categories (e.g., recognition of fluttering vegetation without being tied to a specific view of a specific bush). Toward that end, an approach is developed that is based primarily on observed dynamics (i.e., excluding purely spatial appearance cues). For such purposes, local spatiotemporal orientation is of fundamental descriptive power as it captures the first-order correlation structure of the data irrespective of its origin (i.e., irrespective of the underlying visual phenomena), even while distinguishing a wide range of dynamic patterns of interest (e.g., flicker, single motion, multiple motions, and scintillation). Correspondingly, each dynamic pattern is associated with a distribution (histogram) of measurements that indicates the relative presence of a particular set of 3D orientations in visual spacetime, ðx; y; tÞ, as captured by a bank of spatiotemporal filters and recognition is performed by matching such distributions. In computing these distributions, the local measurements are aggregated over the region of concern, consistent with considerations of homogeneity often invoked in visual texture analysis [6] . Owing to this aggregation, the spatiotemporal layout of pattern structure is ignored. Various representations have been proposed for characterizing spacetime textures for the purpose of recognition [7] . One strand of research explores physics-based approaches, e.g., [8] . These methods derive models for specific dynamic patterns (e.g., water) based on a first-principles analysis of the generating process. With the model recovered from input imagery, the underlying model parameters can be used to drive inference. Beyond computational issues, the main disadvantage of this type of approach is that the derived models are highly focused on specific patterns, and thus lack generalization to other classes.. Motivated by successes in spatial texture research, approaches have been proposed that uniformly treat a diverse set of dynamic patterns based on aggregate statistics of local descriptors. A seminal example of this approach was based on extracting first and second-order statistics of motion flow field-based features, assumed to be captured by estimated normal flow [2] . This work was followed up by numerous proposed variations of normal flow, e.g., [9] , and optical flow-based features, e.g., [10] . There are two main drawbacks related to this strand of research. First, normal flow is correlated with spacetime texture spatial appearance [11] . Thus, in contrast to the goal of the present work, recognition is highly tuned to a particular spatial appearance. Second, optical flow and its normal flow component are predicated on assumptions like brightness constancy and local smoothness, which are generally difficult to justify for stochastic dynamics. Rather than capturing dynamic information alone, others have proposed aggregate measurements of local thresholded values to capture the joint photometric-dynamic pattern structure [12] .. A recent research trend is the use of statistical generative models to jointly capture the spatial appearance and dynamics of a pattern. Recognition is realized by comparing the similarity between the estimated model parameters. Several variants of this approach have appeared, including: autoregressive (AR) models [13] , [14] , [15] , [5] and multiresolution schemes [1] , [3] . By far the most popular of these approaches for recognition is the joint photometric-dynamic, AR-based Linear Dynamic System (LDS) model, proposed in [14] , which has formed the basis for several recognition schemes [4] , [16] , [17] , [18] . Although impressive recognition rates have been reported ($ 90%), most previous efforts have limited experimentation to cases where the pattern samples are taken from the exact same viewpoint. As a result, much of the performance is highly tied to the spatial appearance captured by these models rather than the underlying dynamics [16] , [17] . To address issues with variability in viewpoint, the joint photometric-dynamic LDS model has also been formulated within the bag-of-features framework [18] . Most closely related to the present paper are the LDS variants that have eschewed the appearance component of the model altogether and have instead restricted attention to the dynamic component for recognition [16] , [17] , as captured by the hidden state space. Significantly, a comparative study of many of the proposed LDS approaches, both joint photometric-dynamic and dynamic-only, showed that when applied to image sequences with nonoverlapping views of the same scene ("shiftinvariant" recognition), all yield significantly lower recognition rates ($ 20%), whether using joint spatial-dynamic or only the dynamic portion of the LDS model [17] .. In the current work, spatiotemporal oriented energy filters serve in defining the representation of observed dynamics. Previous research has used similar operators for image sequence analysis toward various ends, including optical flow estimation [19] , [20] , [21] , activity recognition [22] , [23] , [24] , [25] , low-level pattern categorization [26] , tracking [27] , spacetime stereo [28] , and grouping [29] , [30] . Further, distributions of purely spatially oriented measurements have played a prominent role in the analysis of static visual texture [6] , [31] and form the basis of state-of-the-art recognition methods [32] , [33] , [34] . Moreover, psychophysical evidence suggests that spacetime orientation plays a role in human discrimination of temporally stochastic visual patterns [35] , [36] . Psychophysical investigations also have shed light on spatiotemporal perceptual metamers, where physically distinct dynamic patterns are not distinguished by humans [37] . Nevertheless, it appears that the present work is the first to use spatiotemporal orientation as the computational basis for the representation and recognition of spacetime texture. A preliminary version of this research appeared previously [38] .

B I O O O O O O B I O O O O O O O O O O O O O O O O O O O O O B I O O O B I O O O B I O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B I O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B I O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B I O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B I O O O O O O O O O O O O O O O O O O B I O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B I O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B I O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B I O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B I O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B I O O O O O O O O O O B I O O O O O O O O O O


A linear quadrilateral shell element with fast stiffness computation A linear quadrilateral shell element with fast stiffness computation Computational shell analysis is based on stress resultant theories e.g. [1, 2] or on the socalled degenerated approach [3] . New developments in this field are discussed in e.g. [4, 5] . In the following only the main computational aspects are considered. Although the hypothesis underlying the degenerated approach and classical shell theory are essentially the same, the reduction to resultant form is typically carried out numerically in the former, and analytically in the latter, [6] . Many of the computational shell models consider transverse shear deformations within a Reissner-Mindlin theory [7] , [8] to by-pass the difficulties caused by C 1 -requirements of the Kirchhoff-Love theory, see e.g. [9, 10, 11] . Generally, shell behaviour is extremely sensitive to initial geometry and imperfections, thus a successful correlation between theory and analysis is achieved only after including specific details of these quantities. Low order elements like quadrilaterals based on standard displacement interpolation are usually characterized by locking phenomena. In shells two types of locking occur: transverse shear locking in which bending modes are excluded and nearly all energy is stored in transverse shear terms, and; membrane locking in which all bending energy is restrained and energy is stored in membrane terms. Elements which exhibit a locking tendency lead to unacceptable stiff results when reasonable finite element meshes are employed.. In attempting to avoid locking, reduced integration methods have often been advocated, see e.g. [12] . Use of reduced (or selective reduced) integration is often accompanied by spurious zero energy modes. Hence, authors have developed stabilization techniques to regain the correct rank of the element stiffness matrix, e.g. [13, 14, 9] . In some cases, however, results computed using these formulations turned out to be sensitive to the ad hoc hourglass control parameters. Furthermore these elements do not fulfill the bending patch test.. An effective method to avoid transverse shear locking is based on assumed shear strain fields first proposed in [15] , and subsequently extended and reformulated in [16, 17, 18, 19] .. Mixed variational principles provide the basis for the discussed finite element techniques. Assuming linear elasticity a Hellinger-Reissner functional has been used in e.g. [20, 21] . Ref. [20] describe a quadrilateral element with assumed stresses for membrane, bending and shear parts whereas in Ref [21] explicit stabilization matrices for a nine node element have been derived. For general nonlinear material behaviour a three field variational functional with independent displacements, stresses and strains is more appropriate. Within the socalled enhanced strain formulations the independent stresses are eliminated from the set of equations using orthogonality conditions and a two field formulation remains, [22] . For shells this method has been applied enhancing the Green-Lagrangean membrane strains e.g. in [23] .. The drawbacks in [13, 14, 9] have been overcome in [24] . The theory is based on a Hu-Washizu three-field variational principle with independent displacements, stresses and strains. The stabilization matrix is derived from the orthogonality between the constant part of the strain field and the non-constant part using 5 degrees of freedom at each node. In this context we also refer to [25] where an updated Lagrangian approach is used. Further developments for different boundary value problems are considered in [26] , where stabilization matrices on basis of the enhanced strain method have been derived.. An important issue within the context of developing a finite shell model is the number and type of rotational parameters on the element. Mostly general shell theories exclude explicit dependence of a rotational field about the normal to the shell surface which leads to a five parameter model (three displacements and two local rotations). Use of 5 degree-of-freedom frame requires construction of special coordinate systems for the rotational parameters. Considering the so-called drilling degree-of-freedom leads to a finite element discretization with six nodal parameters. This has some advantages since both displacement and rotation parameters are associated with a global coordinate frame. On the other hand a larger set of algebraic equations has to be solved. In this context we mention the four-node shell element according to [27] with three global displacements and three global rotations at each node. The element employs a membrane interpolation field with drilling degrees-of-freedom. The bending stiffness is based on the discrete Kirchhoff theory. For arbitrary shaped elements a transformation of the stiffness matrix, which considers the warping effects, leads to good results also for a non-flat geometry. The element [27] has been widely used in the literature for comparisons, e.g. in [10] and in the present paper.. The essential features and new contributions of the present formulation are summarized as follows:. (i) Assuming linear elasticity the variational formulation of the shear-elastic shell is based on the Hellinger-Reissner principle. We specify the shape functions for the independent stress resultants, where the interpolation of the membrane forces and of the bending moments corresponds to the approach in [10] . Here, the new contribution is the analytical integration of the matrices, which leads to a one-point integrated part and an explicit stabilization matrix. This requires the replacement of the variable base vectors and director vectors by those of the element center, which corresponds to a projection on a flat surface, see also [27] . For warped elements the above mentioned transformation according to [27] is implemented.. (ii) The interpolation of the shear forces along with assumed shear strains and the explicit matrix representation of the stabilization matrix is a further new contribution.. (iii) The element possesses with six zero eigenvalues the correct rank. No control parameters have to be chosen to prevent locking or to avoid hour-glassing. The in-plane and bending patch tests are fulfilled. Especially the convergence behaviour of the stress resultants is superior to comparable four-node shell elements. The main advantage is the fast stiffness computation. In our implementation the present formulation requires only about 60% of the computing time to setup the global stiffness matrix compared with the element [27] .. (iv) The element formulation allows the analysis of shells with intersections. At all nodes which are not positioned on intersections the drilling degree of freedom is fixed. Thus, the nodal degrees of freedom are: three global displacements components, three global rotations at nodes on intersections and two local rotations at other nodes. The main aspect of the present work is to derive a four-node shell element with explicit representation of the stiffness matrix. The formulation with 5 or 6 nodal degrees of freedom is applicable for shell problems with intersections. The element possesses a correct rank, is free of locking, and can be used for the structural analysis of thin and thick shells. The computed results obtained for various shell problems with positive and negative Gaussian curvature are very satisfactory. Especially the convergence behaviour of the stress resultants is superior to comparable elements. The essential advantage is the fast stiffness computation due to the analytically derived stiffness matrix.

O O B I I O O O O O O B I I O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O