Estimating gas concentration using a microcantilever-based electronic nose This paper investigates the determination of the concentration of a chemical vapor as a function of several nonspecific microcantilever array sensors. The nerve agent dimethyl methyl phosphonate (DMMP) in parts-per-billion concentrations in binary and ternary mixtures is able to be resolved when present in a mixture containing parts-per-million concentrations of water and ethanol. The goal is to not only detect the presence of DMMP, but additionally to map the nonspecific output of the sensor array onto a concentration scale. We investigate both linear and nonlinear approaches -the linear approach uses a separate least-squares model for each component, and a nonlinear approach which estimates the component concentrations in parallel. Application of both models to experimental data indicate that both models are able to produce bounded estimates of concentration, but that the outlier performance favors the linear model. The linear model is better suited to portable handheld analyzer, where processing and memory resources are constrained. The biological nose -and in particular, the canine nose -is a highly sensitive detector which is unrivalled its overall performance. Mass spectrometry is able to detect very small vapor concentrations, but such equipment is awkward, bulky and usually requires special operator skill and/or calibration. Emerging applications such as the war on terror, land mine detection, food product analysis and medical applications demand a smaller device which is able to quickly detect minute concentrations of chemical vapor.. Our electronic nose approach, using microcantilever sensor array and an artificial neural network for estimation of the concentrations, was initially reported in [5] . This paper further investigates the algorithmic aspects of the training and estimation phases, since the goal is to produce a reliable hand-held device which, necessarily, is constrained in processing and memory resources. In recent work, we have used selective cantilevers (sorbents on the cantilever surfaces) that make the cantilevers selective to explosive vapor molecules. Our detection of explosive vapors has been enhanced by cantilever selectivity, followed by pattern recognition techniques described here. To the best of our knowledge, this is the first successful application of such techniques to estimate three-component mixtures of such vapors.. The experimental setup is only briefly described here; more extensive details on the experimental procedures may be found in [5] and [6] . We have investigated linear and a multilayer perceptron estimators for the mapping of nonspecific electronic sensors into vapor mixture concentrations. For the present application, detection of the presence of a particular vapor was insufficient; concentration estimates were also required. Microcantilever sensors are utilized; these have the advantage of small size and fast response, but are not specific to individual vapor responses like other chemical sensors. It has been demonstrated that it is possible to estimate the concentration of each vapor in a ternary mixture with surprising accuracy. Although it would be assumed that the sensor responses are nonlinear, it has been demonstrated that a linear model produces good estimates.. The linear approach requires a separate weight parameter vector for each component, and the training phase comprises a one-pass calculation. The nonlinear approach utilizes one set of interconnecting weights to simultaneously estimate all three gas concentrations. However, it also requires a steepest-descent iterative weight parameter re-estimation, and determination of the terminating criteria can be problematic.. Further work requires the investigation of a dual linear-nonlinear hybrid approach, wherein the linear component is first removed, followed by a nonlinear estimator. Also, the investigation of the usefulness of the transient response profile of each sensor is promising, however initial linear filtering is required because of the sensitive nature of the sensors themselves. We have studied two vapor systems: one included the nerve gas stimulant dimethylmethyl phosphonate (DMMP) at parts-per-billion (ppb) concentrations and water and ethanol at parts-per-million (ppm) concentrations (DWE mixtures); the other system included acetone, water and ethanol all of which were at ppm concentrations (AWE mixtures). In both systems, individual, binary and ternary mixtures were detected. Several observations are in order. Firstly, the linear model produces surprisingly good predictions, though this was not unexpected given the preliminary analysis of the covariance matrix of the experimental data. That is, some degree of linear dependence is present, and may be removed by principal component analysis. The linear model appears to function differently for the two vapor mixtures compared, and this is a cause for concern if the approach were to be generalized to other mixture types.. The neural network model is seen to give broadly similar performance for smaller network configurations, and improves with the larger (20-node) model parameterization. Care must be taken in this context, since too large a number of hidden nodes can lead to the well-known problem of network "over-training" -that is, where the output of each hidden node effectively "remembers" a particular training pattern, and does not generalize to unseen patterns.. Considering the above results for linear and nonlinear models, for various neural network parameterizations, it is suggested that a linear pre-processing stage may also be beneficial, in order to decorrelate the input sensor data, and leave only a nonlinear residual for analysis. It is not clear how this would be effected, however, and may require a larger number of sensors for exploration.. It is also noted that the above results utilize only the steady-state sensor output value, rather than the full transient response of each sensor. Whilst this reduces the computational complexity (further discussed below), it may be the case that the transient response profile (as shown at the beginning of the paper) includes important information, which would obviously be overlooked if only the steady-state sensor output is analyzed. Although some preliminary investigations into utilizing the entire time-response profile have been conducted, the amount of data available by sampling each sensor at a suitable rate presents computational problems. In particular, pre-processing stage would be required to smooth the transient response, before input to a neural network. Simply feeding the raw time-response samples as input to a very large (approximately 60 time samples per response) network produces results which are not meaningful, because the network effectively tries to model the sensor noise. Inspection of the time response profiles also indicates that smoothing and perhaps time-alignment of each sensor output would be required.

O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B I O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O


A quality-aware optimizer for information extraction A large amount of structured information is buried in unstructured text. Information extraction systems can extract structured relations from the documents and enable sophisticated, SQL-like queries over unstructured text. Information extraction systems are not perfect and their output has imperfect precision and recall (i.e., contains spurious tuples and misses good tuples). Typically, an extraction system has a set of parameters that can be used as "knobs" to tune the system to be either precision-or recall-oriented. Furthermore, the choice of documents processed by the extraction system also affects the quality of the extracted relation. So far, estimating the output quality of an information extraction task has been an ad hoc procedure, based mainly on heuristics. In this article, we show how to use Receiver Operating Characteristic (ROC) curves to estimate the extraction quality in a statistically robust way and show how to use ROC analysis to select the extraction parameters in a principled manner. Furthermore, we present analytic models that reveal how different document retrieval strategies affect the quality of the extracted relation. Finally, we present our maximum likelihood approach for estimating, on the fly, the parameters required by our analytic models to predict the runtime and the output quality of each execution plan. Our experimental evaluation demonstrates that our optimization approach predicts accurately the output quality and selects the fastest execution plan that satisfies the output quality restrictions. Unstructured text in large collections of text documents such as newspaper articles, Web pages, or email often embeds structured information that can be used for answering structured, relational queries. To extract the structured information from text documents, we can use an information extraction system, such as Snowball , Proteus [Grishman et al. 2002] , MinorThird [Cohen 2004 ], or KnowItAll , which takes as input a text document and produces tuples of the target relation. Often, the extraction process relies on extraction patterns that can be used to extract instances of tuples.. Example 1. An example of an information extraction task is the construction of a table of company headquarters Headquarters(Company, Location) from a newspaper archive. An information extraction system processes documents in the archive (such as the archive of The New York Times; see Figure 1 ) and may extract the tuple Army Research Laboratory, Adelphi from the news articles in the archive. The tuple Army Research Laboratory, Adelphi was extracted based on the pattern " ORGANIZATION in LOCATION ", after identifying the organizations and locations in the given text using a named-entity tagger.. Extracting structured information from unstructured text is inherently a noisy process, and the returned results do not have perfect precision and recall (i.e., they are neither perfect nor complete). The erroneous tuples may be extracted because of various problems, such as erroneous named-entity recognition or imprecise extraction patterns. Additionally, the extraction system may not extract all the valid tuples from the document, for example, because the words in the document do not match any of the extraction patterns. To examine the quality of an extracted relation, we can measure the number of good and bad tuples in the output to study the two types of errors committed during the extraction: the false negatives, namely the number of tuples missing from the extracted relation, and the false positives, namely the number of incorrect tuples that appear in the output.. Example 1 (continued). For the HeadQuarters relation, in Figure 1 , the extraction pattern " ORGANIZATION in LOCATION " also generates the bad tuple Exxon, New York . Figure 1 also shows a missing good tuple Carnegie Group, Inc., Pittsburgh in the document, which was not identified because the extraction system does not include a suitable pattern.. To control the quality of the extracted relations, extraction systems often expose multiple tunable "knobs" that affect the proportion of good and bad tuples observed in the output. As an example of a simplistic knob, consider a decision threshold τ that defines the number of rules employed by the extraction system for the task of extracting the Headquarters relation. A small number of (precise) rules will generate a mostly correct tuples but may also miss many tuples that appear in the documents but do not match any of the (small number of) active rules. By adding more rules, the system can capture more tuples (i.e., decrease the false negatives) but at the same time this also results in an increase in the incorrect tuples in the output (i.e., increase in the false positives). Other examples of knobs may be decision thresholds on the minimum confidence or minimum pattern support required before generating a tuple from the text. In a more extreme setting, we may even have multiple extraction systems for the same relation, each demonstrating different precision-recall trade-offs.. A natural question that arises in a tunable extraction scenario is: How we can choose which extraction system to use and the appropriate parameter settings for an extraction task, in a principled manner? Unfortunately, this important task is currently performed empirically, or by following simple heuristics. In this article, we approach the problem by analyzing a set of information extraction systems using Receiver Operating Characteristic (ROC) curves. As we will see, this allows us to characterize IE systems in a statistically robust manner, and allows the natural modeling of parameters that have a nonmonotonic impact on the false positives and false negatives in the output. We show how ROC analysis allows us to keep only the set of Pareto-optimal configurations that cannot be fully dominated by other configurations. Furthermore, we demonstrate how we take into consideration other parameters, such as execution time and monetary cost, by generalizing the basic ROC paradigm.. Beyond the choice of the extraction system and its settings, the quality characteristics of the extracted relation are also affected by the choice of documents processed by the extraction system. Processing documents that are not relevant to an extraction task may introduce many incorrect tuples, without adding any correct ones in the output. For instance, processing documents from the Food section of a newspaper for the Headquarters relation not only delays the overall extraction task, but also adds false tuples in the relation, such as Crostini,

O O O O B I O O O O O O O O O O O B I O O O O O O O O O O O O O O O O B I O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B I O O O O O O O O O O O O O O O O O O O O O O B I O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B I O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B I O O O O O O O O O O O O O O O O O B I O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B I O O O O O B I O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O


Optimal constant-time approximation algorithms and (unconditional) inapproximability results for every bounded-degree CSP Raghavendra (STOC 2008) gave an elegant and surprising result: if Khot's Unique Games Conjecture (STOC 2002) is true, then for every constraint satisfaction problem (CSP), the best approximation ratio is attained by a certain simple semidefinite programming and a rounding scheme for it.In this paper, we show that similar results hold for constanttime approximation algorithms in the bounded-degree model. Specifically, we present the following: (i) For every CSP, we construct an oracle that serves an access, in constant time, to a nearly optimal solution to a basic LP relaxation of the CSP. (ii) Using the oracle, we give a constant-time rounding scheme that achieves an approximation ratio coincident with the integrality gap of the basic LP. (iii) Finally, we give a generic conversion from integrality gaps of basic LPs to hardness results. All of those results are unconditional. Therefore, for every bounded-degree CSP, we give the best constant-time approximation algorithm among all.A CSP instance is called -far from satisfiability if we must remove at least an -fraction of constraints to make it satisfiable. A CSP is called testable if there is a constanttime algorithm that distinguishes satisfiable instances from -far instances with probability at least 2/3. Using the results above, we also derive, under a technical assumption, an equivalent condition under which a CSP is testable in the bounded-degree model. In a constraint satisfaction problem (CSP), the objective is to find an assignment to a set of variables that satisfies the maximum number of a given set of constraints on them. Formally, a CSP Λ is specified by a set of predicates over alphabets [q] = {1, . . . , q}. Every instance of Λ consists of a set of variables V , and a set of constraints P on them. Each constraint consists of a predicate from Λ applied to a subset of variables. The objective is to find an assignment β ∈ [q] V to the variables that satisfies the maximum number of constraints. A lot of fundamental optimization problems, such as Max Cut and Max k-Sat, are examples of CSPs.. Approximation algorithms for CSPs have been intensively studied. Goemans and Williamson [10] first exploited semidefinite programmings (SDP) to Max Cut and Max 2SAT achieving the approximation ratio ≈ 0.878. After this breakthrough, plethora of approximation algorithms using SDPs have been developed [4, 16] . For inapproximability side, tight hardness results have been successfully obtained for some important optimization problems such as Max 3SAT [15] . However, the approximability of many interesting CSPs such as Max Cut and Max 2SAT remains open. Towards tightening this gap, Khot [17] introduced the Unique Games Conjecture (UGC). Assuming the UGC, tight hardness have been shown for Max Cut [18] , Max 2SAT [5] , and Max k-CSP [6, 27] . Finally, Raghavendra [25] succeeded to unify and generalize those approximation and inapproximability results for every CSP. Specifically, Raghavendra showed that, assuming the UGC, for every CSP, a certain SDP combined with a certain rounding scheme attains the best approximation ratio among all polynomial-time approximation algorithms. The ingenious technique in the proof is giving a generic conversion from integrality gaps of SDPs to hardness results via the UGC.. In this paper, we are concerned with constant-time approximation algorithms CSPs. That is, algorithms are supposed to run in time independent of sizes of instances. We use the bounded-degree model, which was originally introduced for graphs [12] . In this model, the number of alphabets, the maximum arity (the number of inputs to a predicate), the maximum degree (the number of constraints where a variable appears), and the maximum weight of constraints are bounded by constants. Let I be a Λ-CSP instance. Since a constant-time algorithm cannot read the whole I, we assume the existence of an oracle OI with which we can get information of I. By specifying a variable v and an index i, OI returns a constraint P where P is the i-th constraint where v appears. The efficiency of an algorithm is measured by the number of accesses to OI, which is called query complexity.. In this paper, we show an analogous result to Raghavendra's result: for every CSP, a certain linear programming (LP) combined with a certain rounding scheme attains the best approximation ratio among all constant-time approximation algorithms. Furthermore, our results are unconditional. To give the statements precisely, we need to define several notions. For a Λ-CSP instance I with the variable set V and the constraint set P, there is a natural generic LP relaxation which we call BasicLP (see Section 2) . Let lp(I) denote the objective value of an optimal solution to Basi-cLP for I, opt(I) denote the value of an optimal solution of I, and val(I, β) denote the value obtained by an assignment β ∈ [q] V . We define wI as the sum of weights of constraints in I. Then The first result of this paper gives a tight approximation algorithm for every CSP.. Theorem 1.1. In the bounded-degree model, for every CSP Λ and > 0, there exists an algorithm that, given a Λ-CSP instance I with n variables and lp(I) = c ∈ (0, 1], with probability at least 2/3, outputs a value x such that SΛ(c − )wI − n ≤ x ≤ opt(I). Also, for some fixed assignment β such that SΛ(c − )wI − n ≤ val(I, β) ≤ opt(I), given a variable v in I, it computes βv in constant time.. The algorithm computes βv by rounding an LP solution to BasicLP for I. Note that, for an instance I with lp(I) = c, SΛ(c)wI is the best value we can hope for from the definition of SΛ(c). Thus, in this sense, we will give a optimal rounding scheme for BasicLP.. We mention that the additive error n cannot be removed. To see this, suppose an instance I consisting of n variables and only one constraint. Then, we have to see this constraint to approximate opt(I) if we do not allow the additive error. However, it obviously takes Ω(n) to find the constraint in the bounded-degree model.. For hardness side, we show the following.. In the bounded-degree model, for every CSP Λ, c ∈ [0, 1] and > 0, there exists a δ > 0 such that any algorithm that, given an instance I with n variables and opt(I) = c ∈ [0, 1], with probability at least 2/3, outputs a value x such that (SΛ(c) + )wI − δn ≤ x ≤ opt(I) requires Ω( √ n) queries.. Note that, using the algorithm in Theorem 1.1, given an instance I, we can distinguish the case opt(I) ≥ cwI from the case opt(I) ≤ SΛ(c − )wI − n (Technically, we need that SΛ(c) is non-decreasing, but this is obvious from the definition). On the contrary, Theorem 1.2 asserts that we cannot distinguish the case opt(I) ≥ cwI from the case opt(I) ≤ (SΛ(c) + )wI − δn. Thus, the algorithm given in Theorem 1.1 is not just the best among constant-time approximation algorithm using BasicLP, but the best among all constant-time approximation algorithms. A value x is called an (α, β)-approximation to a value x * if it satisfies αx * − β ≤ x ≤ x * . An algorithm is called an (α, β)-approximation algorithm for a CSP Λ if, given a Λ-CSP instance I, it computes an (α, β)-approximation to opt(I) with probability at least 2/3 [23, 24] . The following is an immediate corollary achieved by Theorems 1.1 and 1.2. Corollary 1.3. In the bounded-degree model, for every CSP Λ and > 0, there exists a constant-time (αΛ − , n)approximation algorithm for the CSP Λ. On the other hand, for every CSP Λ and > 0, there exists a δ > 0 such that any (αΛ + , δn)-approximation algorithm for the CSP Λ requires Ω( √ n) queries.. Theorem 1.2 has much implication to property testing. A Λ-CSP instance I is called satisfiable if there is an assignment to variables that satisfies all the constraints. Also, I is called -far from satisfiability if we must remove at least twn constraints to make it satisfiable, where t, w, n is the maximum degree, the maximum weight, and the number of variables, respectively. An algorithm is called a testing algorithm for (the satisfiability of) a CSP Λ if, given a Λ-CSP instance, it accepts with probability at least 2/3 if the instance is satisfiable, and rejects with probability at least 2/3 if the instance is -far from satisfiability. Unlike the hardness result given in [25] , Theorem 1.2 holds also for c = 1, i.e., satisfiable instances. Using this observation, we have the following theorem. Theorem 1.4. In the bounded-degree model, the following holds for a CSP Λ. If SΛ(1) < 1, then any testing algorithm for the CSP Λ requires Ω( √ n) queries. If SΛ(1) = 1 and SΛ(c) is continuous at c = 1, then there exists a constant-time testing algorithm for the CSP Λ.. We mention that Theorem 1.4 gives an "if and only if" condition of the testability of CSPs when their integrality gap curves are continuous at the point one while we are not aware of any CSP for which the curve is not continuous at that point.. We give two direct applications of Theorem 1.4. An instance of 2-SAT is a CNF formula where each constraint consists of at most two literals. It is known that S Max 2-SAT (1) = 1/2, and it follows that we need Ω( √ n) queries to test 2-SAT. On the contrary, 2-SAT is known to be testable with O( √ n) queries [11] . This fact implies that the lower bound in Theorem 1.2 is almost tight. An instance of Horn Sat is a CNF formula where each constraint has at most one positive literal. From [31] , it is easy to derive that S Max Horn SAT (1) = 1 and S Max Horn SAT (c) is continuous at c = 1. Thus, Horn SAT is testable in constant time.

O B I O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B I O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B I O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B I O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B I O O O O O O O O B I O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B I O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O


Speculative dynamic vectorization Abstract Vector processors [2, 6, 10, 16] are very effective to exploit SIMD parallelism, which is present in numerical and multimedia applications.. Vector instructions' efficiency comes from streamed memory accesses and streamed arithmetic operations. Traditionally, the burden to exploit this type of parallelism has been put on the compiler and/or the programmer [1, 24] .. The average programmer can deal with codes whose vectorization is relatively straightforward, The compiler has a partial knowledge of the program (i.e. it has a limited knowledge of the values of the variables). Because of that, it generates code that is safe for any possible scenario according to its knowledge, and thus, it may loose significant opportunities to exploit SIMD parallelism. On top of that, we have the problem of legacy codes that have been compiled for former versions of the ISA with no SIMD extensions and therefore are not able to exploit new SIMD extensions incorporated in newer ISA versions.. In this paper we present a mechanism for dynamically generating SIMD instructions (also referred to as vector instructions). These SIMD instructions speculatively fetch and precompute data using the vector units of the processor. This vectorization scheme works even for codes in which a typical vectorizing compiler would fail to find SIMD parallelism. The vectorization process begins when the processor identifies a load operation that is likely to have a constant stride (based on its past history). Any instruction whose operands have been vectorized is also vectorized. In this way, the 'vectorizable' attribute is propagated down the dependence graph. The scalar unit has to verify the correctness of the vectorization. For this purpose, the corresponding scalar instructions are converted into 'check' operations that basically validate that the operands used by the vector instructions are correct. This is very similar in concept to other checker proposed in the past for other purposes such as fault tolerance [3, 13] . In case of a vectorization misspeculation, the current instances of the vector instructions are executed in scalar mode.. The proposed mechanism also allows the processor to exploit control-flow independence. When a branch is mispredicted, the scalar pipeline is flushed but the vector operations are not squashed. The new scalar instructions corresponding to the correct path will check whether the operations performed by the vector instructions are still correct and if this is the case, their results will be committed. Otherwise, a vectorization misspeculation will be fired, which will discard the vector results.. With the dynamic vectorization mechanism the number of memory requests decreases by 15% for Speclnt and 20% for SpecFP, and the number of executed arithmetic instructions is 25% lower for Speclnt in a 4-way superscalar processor with one wide bus. This reduction in memory requests and executed instructions results in significant speedups. For instance, a 4-way superscalar processor with dynamic vectorization and one wide data cache bus is 19% faster than a 4-way superscalar processor with 4 scalar buses and no dynamic vectorization.. The rest of the paper is organized as follows. Section 2 motivates this work by presenting some statistics about strided memory accesses. Section 3 presents the hardware implementation of the dynamic vectorization mechanism. Performance statistics are discussed in section 4. Section 5 outlines the related work. We conclude in section 6. Speculative dynamic vectorization begins when a strided load is detected. When this happens, a vectorized instance of the instruction is created and it is executed in a vector functional unit storing the results in a vector register. Next instances of the same static instruction are not executed but they just validate if the corresponding speculatively loaded element is valid. This basically consists in checking that the predicted address is correct and the loaded element has not been invalidated by a succeeding store. Every new instance of the scalar load instruction validates one element of the corresponding destination vector register.. Arithmetic instructions are vectorized when any of the source operands is a vector register. Succeeding dynamic instances of this instruction just check that the corresponding source operands are still valid vector elements (details on how the state of each element is kept is later explained).. When a validation fails, the current and following instances of the corresponding instruction are executed in scalar mode, until the vectorizing engine detects again a new veetorizable pattern. With this dynamic vectorization mechanism, as shown in Figure 3 , with unbounded resources, 47% of the Speclnt95 instructions and 51% of the SpecFP95 instructions can be vectorized. In this paper we have proposed a speculative dynamic vectorization scheme as an extension to superscalar processors. This scheme allows the processor to prefetch data into vector registers and to speculatively manipulate these data through vector arithmetic instructions. The main benefits of this microarchitecture are a) the use of SIMD parallelism, even in irregular codes; b) the exploitation of control-flow independence; and c) the increase in the effectiveness of wide memory buses.. We have shown that these benefits resuIt in significant speedups for a broad range of microarchitectural configurations. For instance, a 4-way superscalar processor with one wide port and speculative dynamic vectorization is 3% faster than an 8-way superscalar processor with 4 scalar ports. Speculative dynamic vectorization increases the IPC of a 4-way superscalar processor with one wide bus by 21,2% for Speclnt and 8,1% for SpecFP.. (FEDER funds) under contract TIC2001-0995-C02-01 and by a research grant from Intel Corporation. We also acknowledge the European Center for Parallelism o f Barcelona (CEPBA) for supplying the computing resources for our experiments. Strided memory loads [7, 8] are the instructions that fire the proposed speculative dynamic vectorization mechanism. To identify a strided load, at least three dynamic instances of the static load are needed. The first dynamic instance sets the first memory address that is accessed. The second dynamic instance computes the initial stride, subtracting the memory address of the first dynamic instance from the current address. The third dynamic instance checks if the stride is repeated computing the current stride and comparing it with the first computed stride. Figure i shows the stride distribution for Speclnt95 and SpecFP95 (for this figure, the stride is computed dividing the difference of memory addresses by the size of the accessed data). Details of the evaluation framework can be found in section 4. I.. As shown in Figure 1 , the most frequent stride for Speclnt95 and SpecFP95 is 0. This means that dynamic instances of the same static load access the same memory address. For Speclnt this stride is due, mainly, to the accesses of local variables and memory addresses referenced through pointers. For SpecFP the stride 0 is mainly due to spill code.. Usually, for SpecFP, the most frequent stride is stride 1 because these applications execute the same operations over every element of some array structures. However, due to the code optimizations [4, 9] included by the scalar compiler, such as loop unrolling, some stride 1 accesses become stride 2, 4 or 8. The bottom line of this statistics is that strided accesses are quite common both in integer and FP applications.. The results in Figure 1 also suggest that a wide bus to the L1 data cache can be very effective at reducing the number of memory requests. For instance, if the cache line size is 4 elements, multiple accesses with stride lower than 4 can be served with a single request if the bus width is equal to the line size. These types of strides represent 97,9% and 81,3% of the total strided loads for Speclnt95 and SpecFP95 respectively. Vajapeyam [21] presents a dynamic vectorization mechanism based on trace processors. The mechanism executes in parallel some iterations of a loop. This mechanism tries to enlarge the instruction window capturing in vector form the body of the loops. The whole loop body is vectorized provided that all iterations of the loop follow the same control flow. The mechanism proposed in this paper is more flexible/general in the sense that it can vectorize just parts of the loop body and may allow different control flows in some parts of the loop.. The CONDEL architecture [20] proposed by Uht captures a single copy of complex loops in a static instruction window. It uses state bits per iteration to determine the control paths taken by different loop iterations and to correctly enforce dependences.. The use of wide buses has been previously considered to improve the efficiency of the memory system for different microarchitectures [ 12, 22, 23] .. Rotenberg et al. present a mechanism to exploit control flow independence in superscalar [14] and trace [15] processors. Their approach is based on identifying control independent points dynamically, and a hardware organization of the instruction window that allows the processor to insert the instructions after a branch misprediction between instructions previously dispatched, i.e., after the mispredicted branch and before the control independent point.. Lopez et al. [11] propose and evaluate aggressive wide VL1W architectures oriented to numerical applications. The main idea is to take advantage on the existence of stride one in numerical and multimedia loops. The compiler detects load instructions to consecutive addresses and combines them into a single wide load instruction that can be efficiently executed in VLIW architectures with wide buses. The same concept is applied to groups of instructions that make computations. In some cases, these wide architectures achieve similar performance, compared to architectures where the buses and fimctional units are replicated, but at reduced cost.

B I I O O O O O O O O O O O B O O O O O O O O O O B I O O O O O O O O O O O O O O B O O O O O O O O O O O O O O O O O O O O O O O O B O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B O O O O O O O O O O B O O O O O O O O O O O O O B I O O O O O O O B O O O O O O B O B O O O O O O O O O O O O O O O O O O B O O O O B O O O O O O O O O O O O O O O O O O B O O O O O O O O O O O O O O O O O O O O O O O O O O O B O O B O O O O O O O O O O O O O O O O O O O O O B I O O O O O O O O O O O O O O O O O O O O O O O O O O B O O B O O O O O O B I O O O O O O O O O O O B O B O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B I O O O O O O O O B O O O O O O O B O O O O O O O O O O O O B B O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B I O O O O O B O O O O O O O O O O O O O O B I O B B O O O B I O O O O O O O B I O O O O O O B B O O O O B O O O O O O O O O O O O O O O O O O O O O O O O O B B O O O O O O O O O O O O O O O O O O O B I I O O O O O O O O O O O O O O O B O O O O O O O O O O O O O O O O O O O O O O O O B O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B O O O O O O O O O O O O O O O O O O O O O O O O B O O O B O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B O O O O O O O O O O O O O O O O O B B O O O O O O O O O O O O O O O O O O O O O O O O O O B O O O O B I I O O O O O O O O O O O B O O B O O O O O O O O B O O O O O O O O O B O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B I O O O O O B I I O O O O O O B I O O O O B I I O O O O O O B I O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B I I O O O O O O O O O B O O O O O O O O O B O O O O O O O O O O O B O O O O O O O O O O O O B O O O O O O O B O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B I O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B B O O O O O O O O O B O O O O O O O O O O O B O O O O O O O O O O O O O O O O O O O O O O O O O O B O O O O O O B O O O O O O O O O O O O O O O O O O O O B O O O O O O O O O B O O O O O O O O O O O O O O B O O O O O O O O O O B O O O O O O O O O O O O O O B I O O O O O O O O O O O O O O O O O O O O O O O O O O O B B O O O O O O O O O O O O O O O B O O O O O O O O O B O O O O B O O O O O O O O O O O O O O O O O O O O B O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B O O O O O O O O O B I O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O


Grid Vertex-Unfolding Orthogonal Polyhedra An edge-unfolding of a polyhedron is produced by cutting along edges and flattening the faces to a net, a connected planar piece with no overlaps. A grid unfolding allows additional cuts along grid edges induced by coordinate planes passing through every vertex. A vertexunfolding permits faces in the net to be connected at single vertices, not necessarily along edges. We show that any orthogonal polyhedra of genus zero has a grid vertex-unfolding. (There are orthogonal polyhedra that cannot be vertex-unfolded, so some type of "gridding" of the faces is necessary.) For any orthogonal polyhedron P with n vertices, we describe an algorithm that vertex-unfolds P in O(n 2 ) time. Enroute to explaining this algorithm, we present a simpler vertex-unfolding algorithm that requires a 3×1×1 refinement of the vertex grid. Two unfolding problems have remained unsolved for many years [DO05a, DO07] : (1) Can every convex polyhedron be edge-unfolded? (2) Can every polyhedron be unfolded? An unfolding of a 3D object is an isometric mapping of its surface to a single, connected planar piece, the "net" for the object, that avoids overlap. An edge-unfolding achieves the unfolding by cutting edges of a polyhedron, whereas a general unfolding places no restriction on the cuts. A net representation of a polyhedron finds use in a variety of applications [O'R00] -from flattening monkey brains [SSW89] to manufacturing from sheet metal [Wan97] to low-distortion texture mapping [THCM04] .. It is known that some nonconvex polyhedra cannot be unfolded without overlap with cuts along edges. However, no example is known of a nonconvex polyhedron that cannot be unfolded with unrestricted cuts. Advances on these difficult problems have been made by specializing the class of polyhedra, or easing the stringency of the unfolding criteria. On one hand, it was established in [BDD + 98] that certain subclasses of orthogonal polyhedra -those whose faces meet at right angles and whose edges are parallel to coordinate axes -that are multiples of 90 • -have an unfolding. In particular, the class of orthostacks, stacks of extruded orthogonal polygons, was proven to have an unfolding (but not an edge-unfolding). On the other hand, loosening the criteria of what constitutes a net to permit connection through points/vertices, the so-called vertex-unfoldings, led to an algorithm to vertex-unfold any triangulated manifold [DEE + 03] (and indeed, any simplicial manifold in higher dimensions). A vertex unfolding maps the surface to a single, connected piece K in the plane, but K may have "cut vertices" whose removal disconnects K.. A second loosening of the criteria is the notion of grid unfoldings, which are especially natural for orthogonal polyhedra. A grid unfolding adds edges to the surface by intersecting the polyhedron with planes parallel to Cartesian coordinate planes through every vertex. The two approaches were recently married in [DIL05] , which established that any orthostack may be grid vertex-unfolded. For orthogonal polyhedra, a grid unfolding is a natural median between edge-unfoldings and unrestricted unfoldings.. Our main result is that any orthogonal polyhedron, without shape restriction except that its surface be homeomorphic to a sphere, has a grid vertex-unfolding. We present an algorithm that grid vertex-unfolds any orthogonal polyhedron with n vertices in O(n 2 ) time. We also present, along the way, a simpler algorithm for 3×1×1 refinement unfolding, a weakening of grid unfolding that we define below. We believe that the techniques in our algorithms may help show that all orthogonal polyhedra can be grid edge-unfolded. The two algorithms we present share a common central structure, with the second achieving a stronger result; both are vertex-unfoldings that use orthogonal cuts only. We note that it is the restriction to orthogonal cuts that makes the vertex-unfolding problem difficult: if arbitrary cuts are allowed, then a general vertex-unfolding can be obtained by simply triangulating each face and applying the algorithm from [DEE + 03].. The (3×1×1)-algorithm unfolds any genus-0 orthogonal polyhedron that has been refined in one direction 3-fold. The bands themselves are never split (unlike in [BDD + 98] ). The algorithm is simple. The (1×1×1)-algorithm also unfolds any genus-0 orthogonal polyhedron, but this time achieving a grid vertex-unfolding, i.e., without refinement. This algorithm is more delicate, with several cases not present in the (3×1×1)-algorithm that need careful detailing. Clearly this latter algorithm is stronger, and we vary the detail of presentation to favor it. The overall structure of the two algorithms is the same:. 1. A band "unfolding tree" T u is constructed by shooting rays vertically from the top of bands.. The root of T u is a frontmost band (of smallest y-coordinate), with ties broken arbitrarily.. 2. A forward and return connecting path of vertical front/back gridfaces is identified, each of which connects a parent band to a child band in T u .. 3. Each band is unfolded horizontally as a unit, but interrupted when a connecting path to a child is encountered. The parent band unfolding is suspended at that point, and the child band is unfolded recursively. The final unfolding lays out all bands horizontally, with the front and back gridfaces hanging below and above the bands. Non-overlap is guaranteed by this strict two-direction structure. Although our result is a broadening of that in [DIL05] from orthostacks to all orthogonal polyhedra, we found it necessary to employ techniques different from those used in that work. The main reason is that, in an orthostack, the adjacency structure of bands yields a path, which allows the unfolding to proceed from one band to the next along this path, never needing to return. In an orthogonal polyhedron, the adjacency structure of bands is generally not linear. Thus in our algorithm, unfolding band-by-band leads to a tree traversal (e.g., Fig. 1b) , which requires traversing each arc in both directions. It is this aspect which we consider our main novelty, and which leads us to hope for an extension to edge-unfoldings as well.

O B B I O O O O O O O O O O O O O O O O O O O O O O O O O O B I O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B I O O O O O O B O O B I O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B I O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B I O B I O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B I O B I O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B I O O O O O O O O O O O O O O O O O B I O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B O O O O O O O O O O B O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B I O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O


Efficient Deadline-Based QoS Algorithms for High-Performance Networks Abstract-Quality of service (QoS) is becoming an attractive feature for high-performance networks and parallel machines because, in those environments, there are different traffic types, each one having its own requirements. In that sense, deadline-based algorithms can provide powerful QoS provision. However, the cost associated with keeping ordered lists of packets makes these algorithms impractical for high-performance networks. In this paper, we explore how to efficiently adapt the Earliest Deadline First family of algorithms to high-speed network environments. The results show excellent performance using just two virtual channels, FIFO queues, and a cost feasible with today's technology.Index Terms-Quality of service, high-speed interconnection networks. M ODERN supercomputers and parallel machines put a lot of pressure on the interconnection network. Nowadays, low-latency and contention-free interconnection networks are demanded for the execution of parallel applications. Moreover, high bandwidth is also required to access storage devices. In addition to these, there is also a need for administration traffic used to configure and manage the machine. Finally, some low-priority traffic-like backup copies are needed. Therefore, there is a great variety of application requirements in such environments.. The usual solution to cope with this variety of communication necessities is to overprovision the network. The designers provide more resources than needed to ensure meeting traffic requirements [1] . Besides, to provide the different classes of traffic with their requirements, it is common to settle on a network for each traffic class (TC). For instance, the recently built supercomputer MareNostrum [2] implements a Myrinet network for parallel applications, a Gigabit Ethernet for storage access, and a regular Ethernet for management purposes. Although Ethernet interfaces are quite cheap nowadays, keeping three times the wires is complex, costly, and power consuming.. A subtler approach could be taken in the design of the interconnection for such machines. A single network with some quality-of-service (QoS) support could be used to provide each kind of traffic with its specific requirements. In fact, some of the latest high-performance interconnection proposals incorporate some support for QoS. In the next section, we will introduce the InfiniBand and PCI AS interconnection standards, which include some QoS mechanisms.. The two main types of QoS support are per-traffic-class and per-flow support. The first approach requires the classification of the traffic in TCs and the assignment of one virtual channel (VC) per TC. The network switches offer a traffic differentiation based on these TCs by applying different scheduling algorithms at the VC level. On the other hand, per-flow QoS support requires a flow identifier to be associated with each packet and per-flow information to be kept at each switch of the network. This second approach is much more powerful, but it is also so complex that it has never been implemented in a high-performance environment, with perhaps the exception of ATM [3] .. In this paper, we discuss how to obtain most of the benefits of the per-flow QoS approach within the restrictions of high-performance switches. More specifically, we will propose a novel strategy to emulate the Earliest Deadline First (EDF) family of algorithms by using just a pair of FIFO queues.. The remainder of this paper is structured as follows: In Section 2, the related work is presented. In Section 3, we present our strategy to offer QoS support. Details on the experimental platform are in Section 4 and the performance evaluation is presented in Section 5. Finally, Section 6 summarizes the results of this study. In this paper, we have explored how to efficiently adapt the EDF family of algorithms to high-speed network environments. As far as we know, no similar attempt has been made since some adaptations of ATM due to the cost of using ordered buffers. On the other hand, our proposal is an architecture which, using FIFO buffers, offers almost the same performance, even for the most delay-sensitive traffic.. We have also compared our proposals with typical VCbased QoS, such as can be found in recent standards such as InfiniBand or PCI AS. We have seen that, for similar cost in terms of the silicon area, our proposals offer a much better performance. Achieving similar performance in a traditional multi-VC architecture would require a larger number of VCs, which would significantly increase the cost of the switches and would limit the applicability to high-speed interconnects. In this section, we will review the state of the art in QoS support in wired interconnects with a special attention to the characteristics of per-flow QoS algorithms.

O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B I I O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O


Design, development and assessment of control schemes for IDMS in a standardized RTCP-based solution Simulation results prove the satisfactory responsiveness of our IDMS solution in a small scale scenario, as well as its consistent behavior, when using each one of the deployed architectural schemes. In this work, we have presented the design and development of an adaptive, accurate and standard compliant RTP/RTCP-based IDMS solution. Moreover, because of the suitability of different control schemes for specific use cases, our IDMS solution has been extended and adapted to adopt both centralized (SMS and M/S Scheme) and distributed schemes (DCS). This enhances the flexibility of our IDMS solution to be efficiently deployed in a wide range of scenarios. Simulation tests have shown the consistent behavior of the control schemes and the satisfactory responsiveness of our RTCP-based IDMS solution in a small scale setup. In particular, simulation results confirm prove the ability of our IDMS solutions to achieve an overall sync status (in independent groups of disjoint clients) while minimizing the occurrence of long-term playout discontinuities or disruptions (such as skips & pauses), and hardly increasing the network and computational load.. Likewise, the results confirm the differences between IDMS control schemes, mainly in terms of coherence and interactivity.. Despite that simulation tests cannot definitively validate the performance of our IDMS solution, they show the satisfactory responsiveness of the designed algorithms and techniques, as well as the consistent behavior of the deployed control schemes for IDMS, according to our qualitative study in [3] .. We believe in the relevancy of IDMS in current and future media delivery deployments.. Accordingly, we have in mind several lines for future work. First, we will assess the impact of the application of the proposed IDMS techniques by implementing them in a real media framework (e.g., GStreamer [36] ). This will enable us to perform real-world assessments in present-day network environments, analyzing the effects on the QoE of different levels of out-of-sync situations and how they are handled/avoided by using our IDMS solution. Second, we plan to design further RTCP extensions to enable the triggering of dynamic IDMS adjustments based on the instantaneous importance of the media content being delivered, as done in other works for interstream sync purposes (e.g. [2] ). Third, we plan to further investigate on AMP for IDMS. On one hand, we will examine the effectiveness of our AMP technique when using modern H.264 SVC (Scalable Video Coding) codecs with increased rate variability [37] , and the implications on various aspects, such as delay, buffer settings, computational load or sync accuracy. On the other hand, we plan to design advanced adjustment techniques (e.g., non-linear, content-aware) with the objective of minimizing abrupt changes in the media playout rate. Finally, we need to extend our studies with a thorough analysis of the behavior of our IDMS solution in large-scale scenarios, with lots of Sync Clients joining and leaving the session. This will determine the relevancy, stability and scalability of our IDMS solution, and if further mechanisms need to be designed and adopted to enhance its performance in such situations. Due to the increasing relevancy of IDMS, several works have addressed this topic. In [5] , authors presented a survey of IDMS solutions, whilst in [3] we presented a compilation of IDMS use cases.. Besides, the recent work in [6] provides a historical review of multimedia sync techniques (including IDMS).. Two main categories of IDMS solutions can be distinguished (see [5, 6] ): axis-based, which aim to continuously align the presentation of media streams along either a virtual or a wall-clock timeline axis; and control-based (a.k.a. event-based), which handle the sync of media streams over a discrete set of reference control points or events.. In general, existing IDMS solutions were designed for specific applications, such as audio/video streaming (e.g., [1] , [2] , [9] , [14] ), conferencing (e.g., [15] [16] [17] [18] ), gaming (e.g., [19] [20] [21] [22] ), collaborative virtual environments (e.g., [23] , [24] ) or synchronous e-learning (e.g., [15] , [17] ).. Likewise, these solutions involve different types of media streams, such as audio, video, haptic media (e.g., [16] , [17] ), and user-generated events (e.g., [4] , [20] , [21] ). It is important to note that most of them are ad-hoc solutions, rely on the definition of new (application-specific) proprietary protocols, and make inter-operability between implementations and domains very difficult.. In addition, as such solutions were devised for specific networked environments and for meeting specific requirements, they differ on the adopted architectural approach to exchange the required information about IDMS. In this context, three main IDMS control schemes have been identified (see Fig. 1 ): two centralized (Master/Slave, or M/S, Scheme and Sync Maestro Scheme or SMS) and one distributed (Distributed Control Scheme or DCS). Readers are referred to [3] to find an exhaustive description, classification (summarized in Table 1 ) and a qualitative comparison among these IDMS schemes. Even though it was concluded in that work that SMS is, in general, the best-ranked scheme for IDMS, the appropriateness of DCS and M/S schemes for specific use cases was also identified. On one hand, M/S Scheme outperforms SMS in terms of scalability, traffic overhead, interactivity and causality. On the other hand, DCS can provide better performance than SMS in terms of robustness, scalability, interactivity, flexibility and fairness. [4] , [9] , [14] [15], [23] , [16] , [17] , [5] , [10] [20], [21] , [22] , [17] , [4] In general, the specification of an IDMS solution is highly dependent on the context and environment for which it is going to be deployed. For instance, some applications can be smallscale, while others can be deployed over large-scale settings. Some others require the achievement of stringent sync levels, while lower sync accuracy may be acceptable in other solutions.

O O O O O B I O O O O O O O B O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B I O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B O O O O O O O O B I O O O O O O O O O O O O O O O O B O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B I O O O O O O O O O B O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B I O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B I O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O


A Framework for the Evaluation of Session Reconstruction Heuristics in Web-Usage Analysis W eb-usage mining has become the subject of intensive research, as its potential for personalized services, adaptive Web sites and customer profiling is recognized. However, the reliability of Web-usage mining results depends heavily on the proper preparation of the input datasets. In particular, errors in the reconstruction of sessions and incomplete tracing of users' activities in a site can easily result in invalid patterns and wrong conclusions. In this study, we evaluate the performance of heuristics employed to reconstruct sessions from the server log data. Such heuristics are called to partition activities first by user and then by visit of the user in the site, where user identification mechanisms, such as cookies, may or may not be available. We propose a set of performance measures that are sensitive to two types of reconstruction errors and appropriate for different applications in knowledge discovery (KDD) applications.We have tested our framework on the Web server data of a frame-based Web site. The first experiment concerned a specific KDD application and has shown the sensitivity of the heuristics to particularities of the site's structure and traffic. The second experiment is not bound to a specific application but rather compares the performance of the heuristics for different measures and thus for different application types. Our results show that there is no single best heuristic, but our measures help the analyst in the selection of the heuristic best suited for the application at hand. The discovery of Web-usage patterns is an essential prerequisite for the personalization of Web services, the tuning of Web services, the presentation of promotional contents, the launching of e-marketing campaigns, and in short, for all applications in which user interests, preferences, requirements, and behavioral conventions must be assessed and served.. Web-usage analysis is a subdomain of knowledge discovery. It employs data mining techniques to extract patterns from data. These data are Web activity logs, often enriched with external information such as customer transactions from a pay-bill department, customer records from a customer care division or demographics from an external third party. The reliability of data mining results depends on the quality of these data, which may be noisy, erroneous or incomplete.. Web server logs are the primary source of data in which the activities of Web users are captured. However, due to constraints of the HTTP specification, these records are incomplete, in the sense that the requests they contain cannot be uniquely assigned to the individual that has performed them. This ambiguity has led to several "proactive" and "reactive" strategies. Proactive strategies aim at an unambiguous association of each request with an individual before or during the individual's interaction with the Web site. Reactive strategies attempt to associate requests to individuals after the interaction with the Web site, based on the existing, incomplete records.. Proactive strategies include user authentication, the activation of cookies that are installed at the user's work area and can thus attach a unique identifier to her requests, as well as the replacement of a site's static pages with dynamically generated pages that are uniquely associated with the browser that invokes them. The following characteristics are pertinent to proactive strategies:. • They raise privacy considerations among site users, and may thus have a negative impact on the contact efficiency of the Web site.. • They presume that Web site owners understand the importance of good quality data for their business, can quantify and compare the negative and the positive potential impact of proactive strategies in their business domain, and are willing to perform the investment needed to implement these strategies.. Reactive strategies exploit background knowledge on user navigational behavior to assess whether requests registered by the Web server can belong to the same individual, and whether these requests were performed during the same or subsequent visits of the individual to the site. It is generally believed that their results are of lower accuracy than those of the proactive strategies. It is also believed that proactive strategies are error-proof, except for some statistically negligible number of cases. However, the validity of such beliefs, which is in essence the accuracy of proactive and reactive strategies, has not been quantified to date.. The absence of well-founded accuracy results is problematic from a business perspective: Should a business venue in a privacy-sensitive market segment (as are many customer segments in Europe) opt for a proactive strategy, or would a good reactive strategy incur only a minor quality loss? Are all proactive strategies equally reliable? If yes, why are some sites operating multiple proactive strategies, some of which require non-minor investments? If not, what is the best strategy or the best combination? And what is the accuracy loss when opting for the second-best one?. In this study, we introduce a framework for answering such questions. Our framework is designed for the comparison of proactive and reactive strategies that (re)construct the activities of individual users from the stream of requests accessing a site and assign them into sessions, i.e., into separate visits to the site. Our framework incorporates a set of measures for the comparison of session reconstruction results, a test environment where alternative strategies have been implemented, and an experimental setting for our comparisons.. In the next section, we discuss related research. In Section 3, we give a detailed description of proactive and reactive strategies for session reconstruction, and we elaborate on the particularities in their behavior. In Section 4, we measure the impact of reactive strategies on the reconstruction of basic session features, and we give an example of how reconstruction errors can affect mining results. Section 5 extends this by introducing a set of measures for the performance of the heuristics. In Section 6, we describe our first experimental results with the proposed set of measures, interpret the performance differences among the investigated reactive strategies, and use these results to identify appropriate application areas for each strategy. Section 7 concludes our study. Studies related to our work come from two areas: data preparation and evaluation methodologies for data mining.. Data Preparation. In the process of knowledge discovery from data, the data preparation phase precedes data analysis. As pointed out by Pyle (1999) ,

O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B I O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B I O O O O O O B I O O O O O O O O O B I O O O O O O O O O O O


A scalable front-end architecture for fast instruction delivery In the pursuit of instruction-level parallelism, significant At a high-level, a modern high-performance processor is composed of two processing engines: the front-end processor and the execution core. The front-end processor is responsible for fetching and preparing (e.g., decoding, renaming, etc.) instructions for execution. The execution core orchestrates the execution of instructions and the retirement of their register and memory results to non-speculative storage. Typically, these processing engines are connected by a buffering stage of some form, e.g., instruction fetch queues or reservation stations -the front-end acts as a producer, filling the connecting buffers with instructions for consumption by the execution core.. This producer/consumer relationship between the frontend and execution core creates a fundamental bottleneck in computing, i.e., execution performance is strictly limited by fetch performance. The trend towards exploiting more ILP in execution cores works to place further demands on the rate of instruction delivery from the front-end. Without complementary increases in front-end delivery performance, more exploitation of ILP will only decrease functional unit utilization with little or no increase in overall performance.. Unfortunately, scaling the performance of the front-end is no easy task. Three primary detractors work to make this a very challenging endeavor. First, instruction cache misses stall instruction delivery until instructions are returned from the next level of the instruction memory hierarchy. Second, the misprediction of the address or direction of a branch forces a pipeline flush, resulting in wasted fetch bandwidth between the time the branch was mispredicted and the time the misprediction was detected. Third, in modern front-end designs, resolving the target of a taken branch requires an access to the branch predictor and branch target buffer (BTB). As a result, the rate at which these devices can be cycled times the average basic block size places an upper limit on instruction delivery rates.. To further compound the challenge of front-end design, a process technology trend is materializing that will make it more difficult to design fast front-ends, i.e., front-ends with low cycle times. Looking ahead a few process technology generations (e.g., 0.18m and 0.10m) 1 it becomes apparent that the performance (latency) of wires is not scaling as well as the performance of transistors [2, 3] . Wire performance may not scale at all and may even deteriorate in a few process generations. The problem is worse for large memories, like those typically found in front-end designs, because they are composed of significantly more interconnect. Large front-end designs may see little improvement and possibly even a reduction in the rate at which the processor can deliver instructions to the execution core.. As a result of this trend, architects must start concerning themselves less with the amount of logic in the critical path of a design and instead focus on the amount of wire in the critical path. Designs with less wire will naturally scale better because their latency is more a function of transistor latency which scales with process feature size. A scalable design is one that can perform well in the face of process technology trends -ideally we would like to see performance increases commencerate with the feature size scaling factor. We predict, given the interconnect scaling bottleneck, a scalable design will be one with minimal wire lengths on the critical path of the design.. In this paper, we present a new scalable front-end design. Our design decouples the branch predictors and branch target buffers from the I-cache, to allow maximum performance for each. We call this new design a Fetch Target Buffer (FTB). The FTB organization was chosen to (1) maximize the number of instructions fetched for each prediction, and (2) perform a useful prediction every cycle. Each FTB entry represents a large variable length sequential fetch block up until the next taken branch. In an effort to provide fast cycle times, while allowing sufficient capacity to maintain history and targets for a large number of branches, the FTB uses a multi-level memory hierarchy. The top-level (L1) FTB is able to store its targets and predictor history into a larger second-level (L2) FTB. Through cycle-based simulation and circuit-level timing analysis, we show that this multi-level design performs better than traditional single-level designs, and is scalable to future process generations.. The remainder of this paper is organized as follows. In Section 2 we detail the interconnect scaling bottleneck and its impact on front-end design. In Section 3 we present a new scalable front-end architecture, and in Section 4 we detail the organization and operation of the fetch target buffer. In Section 5 we describe the methodology used to gather our results. In Section 6 we evaluate the scalability of the new designs, comparing the performance of single and two-level FTB designs with traditional BTB-based designs, both in the cycle and time domains. Section 7 presents related work. Finally, Section 8 provides a summary and concludes with future directions. A scalable front-end architecture was presented and evaluated. The design features the fetch target buffer (FTB), a multi-level fetch block-oriented target predictor. Simulationbased evaluations indicate the design is more capable than traditional BTB designs and single-level FTB designs. Circuit-level analyses show that the design also features a higher instruction delivery rate, measured in instructions per nano-second (IPS). For a 0.10m technology, a two-level FTB design with a 64-entry first level and a 1k-entry second level provides a 25% improvement in IPS over the best performing single-level designs. When the performance of the various designs is examined across multiple process generations, the multi-level FTB designs exhibit the best performance and scalability of all the designs investigated.. We feel our approach is quite promising since it focuses on simplicity and raw speed. Unlike techniques that work to increase the number of instruction delivered per cycle, we were able to gain marked increases in performance while being able to sidestep the very difficult problems of multiple branch and target prediction.. We are currently extending this research in several directions. First, we are examining other FTB designs that may provide increased fetch block sizes. Second, we are evaluating using the FTQ to provide streaming of data from secondlevel cache to the first level. If the FTQ is full, because of I-cache misses or a backed up pipeline, the FTQ entries can be used to stream in cache blocks from the L2 cache into a stream buffer, eliminating L1 I-cache misses. Third, we are extending the multi-level FTB design to provide multiple branch prediction, which will produce multiple FTQ entries per cycle. Finally, we are comparing the performance of the FTB to other promising high-fetch bandwidth architectures like the trace cache. A complete evaluation of some of the above ideas along with a more detailed description of the Cacti timing models used in this paper can be found in [22] . First we present a comparison of the BBTB design and the single-level FTB design. Next, we compare our single level FTB to a two level FTB, presenting results in Instructions Per nanoSecond (IPS). We then investigate how the performance of the FTB tolerates changes in factors such as the number of bits allocated to the fetch distance and variance in the size of the FTQ. For all of the FTB results we used a fetch distance of size 16 instructions (4 bits for the partial fall-through address), which we found to be sufficient as described in Section 6.3. Finally, the scalability of the FTB across different feature sizes is considered. Figure 3 shows IPC results comparing the BBTB design our single-level FTB configurations. Both architectures were simulated with a coupled front-end (no FTQ) to provide a fair comparison with non-pipelined caches. Overall, the FTB designs provide slightly better fetch bandwidth than the BBTB designs, since the FTB does not need to store every encountered basic block (branch) -only those that have been taken in the past. Figure 3 shows that a small 64 entry FTB can hold the majority of branches executed by compress, ijpeg, and m88ksim whereas the rest of the programs benefit from having a large FTB. For all programs, little performance gain is seen when increasing the predictor size beyond 4K entries. The results show that the FTB design consistently outperformed or performed as well as a comparably sized BBTB design. The remainder of the results compare the performance of the two-level FTB with the single level FTB. Table 3 : FTB Performance. Average fetch block size provided by the FTB, along with the percent of fetch block predictions that were correct when hitting in the first (L1) or second (L2) level FTB, and the percent of correct predictions that occurred when missing in the FTB. a 1K entry second-level FTB (64-1K). The average fetch block size is the dynamic size obtained for predictions on the non-speculative path. The correct prediction rates show the percent of time the FTB provided a correct prediction from each FTB level, and the percent of time predicting a fixed fall-through fetch distance was correct for an FTB hierarchy miss. For a miss, a fall-through fetch block of size 16 instructions is predicted. Once an FTB entry has been brought into the first level from the second level, it is counted as a L1 correct prediction for all subsequent predictions -until it is again swapped out of the first level. The average fetch block size of the single level FTB configuration is higher due to increased FTB misses. On FTB misses, the large fixed fetch distance (16 instructions) is predicted which makes the average fetch block size larger, but also increases the chance of including a taken branch. The two-level FTB structure provides a total of 83.3% correct fetch block predictions on average, with an average fetch size of 6.6 instructions. The simulators used in this study are derived from the SimpleScalar/Alpha 3.0 tool set [5] , a suite of functional and timing simulation tools for the Alpha AXP ISA. The timing simulator executes only user-level instructions, performing a detailed timing simulation of an aggressive 8-way dynamically scheduled microprocessor with two levels of instruction and data cache memory. Simulation is execution-driven, including execution down any speculative path until the detection of a fault, TLB miss, or branch mis-prediction.. To perform our evaluation, we collected results for six of the SPEC95 C benchmarks plus 2 C++ programs. Groff is a text formatting program, and deltablue is a constraint solving system. The programs were compiled on a DEC Alpha AXP-21164 processor using the DEC C and C++ compilers under OSF/1 V4.0 operating system using full compiler optimization (-O4 -ifo). we used in gathering results for each program, the number of instructions executed in the program to completion (in millions), and the percent of executed branches in each program. Also shown is the number of instructions that were executed (fast forwarded) before actual simulation. Results are then reported for simulating each program for up to 100 million instructions.

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