Periodic scheduling of marked graphs using balanced binary words Abstract: This report presents an algorithm to statically schedule live and strongly connected Marked Graphs (MG). The proposed algorithm computes the best execution where the execution rate is maximal and place sizes are minimal. The proposed algorithm provides transition schedules represented as binary words. These words are chosen to be balanced. The contributions of this paper is the proposed algorithm itself along with the characterization of the best execution of any MG.Key-words: Marked Graph, Scheduling, Balanced binary word Ordonnancement périodique de graphes marqués en utilisant les mots binaires balancésCe rapport presente un algorithme pour ordonnancer statiquement un graphe marqué fortement connexe et vivant. L'algorithme proposé calcule la meilleur exécution pour laquelle le rendement effectif est maximal et la taille des places est minimale. L'agorithme proposé fournit les ordonnancements de chacun des noeuds de calcul sous la forme de mots binaires. Ces mots sont choisis balancés. Les contributions du rapport sont à la fois l'algorithm proposé lui-même et la caractérisation de la meilleure exécution d'un graphe marqué.Mots-clés : graphe marqué, ordonnancement, mot binaire balancé Periodic scheduling of marked graphs using balanced binary words 3 In the System-on-Chip design domain, the trend is component based design. A new design is assembled from IP components which are interconnected through a network of point-to-point communication channels. In this area, the problem of long wire communication latency has emerged as a limitation [20] . A channel is not able to forward a datum in a single step but requires many.. To solve this problem, a component based design has to be provided with its scheduling to take care of the latency issues. Luca Carloni et al. have proposed the theory of Latency Insensitive Design (LID) [14] as a dynamic scheduling solution but LID is greedy in buffering element. From our initial tentative to improve the LID [12] , we have established that a component based design along with its latency issues can be modeled using Marked/Event graph (MG) [17] . Consequently, from the challenge of scheduling a System-on-Chip design, we arrive to the more general and abstract challenge of scheduling an MG with respect to communication and computation latencies.. To enter this challenge, we have developed the proposed algorithm which provide a statically computed execution to any live and strongly connected MG. The proposed algorithm can eventually be applied to any system (software, hardware, production chain) which can be abstracted as an MG with fixed communication and computation latencies.. It is clear from historical results [6, 13, 22 ] that a live MG always admits an execution irrespectively of the communication or computation latencies. The proposed algorithm consists in computing the best ASAP execution where execution rate is maximal and place sizes are minimal. These properties match with the requirements encountered in the domain of Systemon-Chip design [14] . Lastly, the proposed algorithm is extended to simply connected MGs. However, the validity of the computed execution relies on the on-demand availability of tokens on global inputs.. Except the proposed algorithm itself, the main contribution of the paper is the characterization of this best ASAP execution. From the initial marking, an guided execution shall lead to different markings. From each of these markings, the ASAP execution will be different and token accumulation in the places may vary. For example, in a given ASAP execution, a transition may fire all its tokens in sequence and then stall for the rest of the period, while in another ASAP execution, the same transition is fired every two instants. The first example promotes tokens accumulation. Within this set of ASAP executions, the one with the smallest tokens accumulation is called the balanced ASAP execution. This execution always exists and can be analytically computed for any MG. In a balanced ASAP execution, the binary words that represent the activities of the transitions through time (1 for activity, 0 for inactivity) are all balanced.. Related works Marked graphs is a well studied domain for more than forty years and many works are closely related to ours. [18] state the notions but also some results used in this paper. [13] and [6] are the bases of our scheduling theory.. Historically, some works related to the notion of balancedness can be found in a publication of Jean Bernoulli in the 18 th century [7] . Then they appeared as Christoffel words in the 19 th century [15] . More recently Christoffel words appear again in [19] , and as Sturm words in [8, 3] , or as mechanical words in [5] . [9] records the history of balanced binary words. In [1, 2] , balanced binary words are used to balance load of Erlang network. In [4] , the authors try to minimize the data lose in a graph with fixed storage capacities by optimally routing data trough communication channels using balanced binary words.. Outline Section 2 runs the proposed algorithm on an example.Section 3 presents the MG definition followed by all the required results about static analysis of MG. Balanced binary words are presented and studied in Section 4. The proposed algorithm is presented in Section 5, followed by the proofs of correctness and then Section 6 discusses our results.

O B O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B I B B I I O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B O O O O O O O O O O O O O O O O O O O O O O O O B O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B O O O O O O O O O O O O O B O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O


Low-latency adaptive mode transitions and hierarchical power management in asymmetric clustered cores Recently, engineering solutions that include asymmetric multicores have been fabricated for low form-factor computing devices, indicating a potential direction for future evolution of processors. In this article we propose an asymmetric clustered core architecture, exhibiting low-latency switching between modes relative to asymmetric multicores, and having similarities with the same asymmetric multicore architecture in the context of a wider dynamic range of the processor power-performance characteristic. Asymmetric clustered cores incur additional microarchitectural complexity and area cost inside a core but exhibit better chip-level integration characteristics compared to asymmetric multicores. Focusing on power efficiency of asymmetric clustered cores, we describe: (1) a hierarchical power management partitioning between the operating system and on-die firmware for coarse-grain switch policies, and (2) core-internal tracking hardware for fine-grain switching. The mode switch policies of the core's tracking hardware are dependent on higher-level directives and hints from the operating system, on-die firmware, and compiler or profiling software. We further explore the potential power management benefits of asymmetric clustered cores relative to asymmetric multicores, demonstrating that the ability of asymmetric clustered cores to use tight training periods for adaptive behavior, with low overhead switching between modes, results in a more efficient utilization of power management directives. Physical properties of fabricated transistors dictate changes in computer architecture. Silicon scaling rules applied in the past [Dennard et al. 1974 ] cannot be sustained for low operating voltages, due to circuit sensitivity to manufacturing variations and operating point changes [Gonzalez et al. 1997] . As a result, various engineering solutions are required to accommodate the increase in transistor density within a highly constrained power budget [Borkar 1999 ]. These solutions need to take into account the different usage models of a general-purpose processor, optimizing for latency and (2) We discuss core-level and chip-level functional and layout integration considerations for ACC and asymmetric multicore architectures, presenting area comparisons between the two options based on a specific chip-level integration scheme. (3) We describe a hierarchical power management control-partitioning scheme: (a) the operating system and a central power management control unit on the global level, and (b) an ACC on the local level. The latter performs fine-grain power mode transitions according to given directives and hints. (4) We propose a fine-grain, adaptive switch heuristic for single-thread workload which is based on training periods and real-time information. (5) We provide a single-thread power-performance analysis of the ACC for the proposed switch heuristic scheme. (6) We demonstrate the relative power management efficiency of ACCs and asymmetric multicores. The rest of the article is comprised of the following sections. Section 2 discusses the ACC microarchitecture. Section 3 describes the methodology used in this article to study the scalar performance characteristics of the ACC. Section 4 describes mode switch considerations and mode switch heuristics. Section 5 presents the ACC evaluation results. Section 6 presents a comparison between ACC and asymmetric multocre. Section 7 discusses related work. Section 8 summarizes the work and discusses future research. ACC is an alternative for asymmetric multicores, providing a wide dynamic range of power-performance characteristics and enabling efficient multithreading scalability. The ACC provides an opportunity for efficient core-level optimization at the expense of core complexity and loss of flexibility in setting a distinct pipeline ratio. Under an assumption of no operating system involvement, for a ratio of two between simple and complex pipelines and for a specific core configuration provided in this work, a comparable asymmetric multicore incurs a 14% increase in total chip area, accompanied by additional chip-level power dissipation of 5%. The asymmetric multicore gains in area efficiency when peak power is managed by an operating system that is aware of the distinct core type and power-performance characteristics.. The ACC architecture is characterized by an ability to perform low-latency mode switches, locally within the core, according to directives and hints received from software and firmware. The benefit of having a highly coupled ACC relative to a partially decoupled ACC or a fully decoupled asymmetric core was demonstrated by the ability of the highly coupled ACC to utilize better power directives from software and on-die firmware. The higher utilization of power directives was manifested by achieving lower energy values for different directives such as energy delay 2 or minimal energy with a constraint of allowed performance loss. For the directive of energy-delay 2 optimization, a highly coupled core exhibited lower energy consumption of 5-11% at an about 3-6% additional cost of performance degradation. For the directive of minimal energy consumption at a constraint of allowed performance loss, the highly coupled ACC was able to utilize the directive for energy saving beyond the given performance loss limit, while the decoupled ACC achieved an energy saving level that was lower than the given performance loss limit, due to the high overhead of changing modes. The RAPL algorithm described in this work can utilize additional energy credits returned by a highly coupled ACC for efficient thermal capping and power budgeting in a multithreaded environment.. As a future research topic, the multithreading scalability characteristics of ACCs relative to asymmetric multicores should be explored. One of the most challenging tasks when operating in a multithreaded environment is the runtime allocation of threads among distinct core types. Our expectation in this context is that the ability of the RAPL algorithm to allocate energy credits across application phases and among multiple threads, and the ability of the ACC to make local mode switch decisions based on directives derived from the RAPL energy budget will provide more efficient scaling relative to asymmetric multicores. The ability to reconfigure a CPU at runtime and form different computation entities according to dynamic workload demand was suggested in several works. Clustered core architecture was presented in Farkas et al. [1997] as a method for reducing the clock cycle time as a result of better partitioning of internal hardware blocks. A method for predicting runtime variations in thread parallelism and switching between in-order and out-of-order operation modes for the purpose of saving power was presented in Ghiasi and Grunwald [2000] . Kumar et al. [2004] investigated possible sharing of floating point units, crossbar ports, instruction and data caches between adjacent cores of a chip multiprocessor. The potential morphing of heterogeneous cores with floating point and integer units that exhibit different performance characteristics was described in Das et al. [2010] . Another form of core morphing was presented in Ipek et al. [2007] suggesting to group independent cores into a larger CPU as needed at runtime by applications. MorphCore [Khubaib et al. 2012] begins with a conventional out-of-order core, which may be used for high-performance applications, but may be also morphed into an in-order SMT configuration for the purpose of high throughput. Another recent work, Composite Cores [Lukefahr et al. 2012 ], suggests an architecture in which big and little microengines share a substantial proportion of the architectural state, thus reducing switching time. Although this proposal shares some similarity with our work at the conceptual level, the two approaches are very different in terms of the design details.. The benefits of heterogeneous computing were investigated in several papers. For example, Kumar et al. [2003] and Kumar [2005] show power, performance, and area implications when tuning the selection of four types of Alpha cores to a workload ILP (Instruction-Level Parallelism). A theoretical analytical model describing the potential performance benefit for a given power envelope of ACCMP (Asymmetric Cluster Core MultiProcessor) as opposed to SCMP (Symmetric Cluster Core MultiProcessor) was given in Morad et al. [2006] . The analytic model was based on an empirical observation that core performance is roughly proportional to the square root of its area. The proposed ACCMP architecture was based on distinct cores of different sizes grouped in clusters.. A scheme that combines a narrow out-of-order core with a wide in-order core and performs binary translation for efficient utilization of the wide in-order core was described in Wu et al. [2011] . Another work that combined hardware and software mechanisms to efficiently accelerate critical-section-intensive workloads on an asymmetric multicore architecture was described in Suleman et al. [2009] with a reported acceleration of 23% relative to a nonimproved asymmetric multicore architecture and 34% performance improvement relative to a symmetric CMP architecture.. While asymmetric architectures present new opportunities for saving power and chip area, utilizing such chips involves scheduling challenges at the operating system level [Li et al. 2007] . Li et al. [2010] propose algorithms for sharing heterogeneous cores among applications. These algorithms were implemented in the Linux 2.6.24 kernel and their performance evaluated by running the OS on a heterogeneous multicore processor. The paper reports performance improvements for a set of applications. Saez et al. [2010] propose a comprehensive scheduler for asymmetric multicore processors. The scheduler was implemented in the OpenSolaris operating system. The evaluation reported in the paper shows that the proposed scheduler utilizes asymmetric cores in an efficient way for a range of applications.

O O O O O O B O O O B I O O O O O B I O O O O O O O O O O O O O O O O O O O O O O O O O O B O O O O O O O B I O O O O O O O O B O O O O O O O O O O O O O O B I O O O O O O O O O O O O O O O O O O B I O O B O O O B I O O O O O B O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B O O O O B I O O B I O O O O O O B I O O O O O O O O O O O O O O O O O O O O O B O O O O O O O O O O O B O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B O O O O O O O O O O B O O O O O O O O O O O O O O O O O O O B O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B O O O O O B I O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B I O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B O O O O O O O O O O O O B O O O O O O O O O O O O O O O O O O O B O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B O O O O O O O O O O B O O O O O O O O O O O O O B I O O O O O O O O O B O O O O O O O O O O O O O O O O O O O O O O O O O B O O O O O O O O O O O O O B O O O O O O O O O O O O O O O O O B O O O O O O O O O O O O O O O O O B O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B O O O O O O O O O O O O O O O O O O B I O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B I O O O O O O O O O O O O O O O O O O O O O O O O O B O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B O O O O O O O O O O O O B I O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B O O O O O O O O O O O O O O O O O O O O O B B O O O O O O O O O O O O O O O O O O O O O O O O O O B O O O O B O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B O O O O O O O O O O O O O B O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B O O O O O O O O O O O O O O O O O O O B O O B O O O O O O B O O O O O O O O B O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B O O O O O O O O O O O O O B O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O


Application-aware management of parallel simulation collections This paper presents a system deployed on parallel clusters to manage a collection of parallel simulations that make up a computational study. It explores how such a system can extend traditional parallel job scheduling and resource allocation techniques to incorporate knowledge specific to the study.Using a UINTAH-based helium gas simulation code (ARCHES) and the SimX system for multi-experiment computational studies, this paper demonstrates that, by using application-specific knowledge in resource allocation and scheduling decisions, one can reduce the run time of a computational study from over 20 hours to under 4.5 hours on a 32-processor cluster, and from almost 11 hours to just over 3.5 hours on a 64-processor cluster. Computer simulation has become an integral part of the scientific method, often delivering deeper insights into complex physical processes than possible using only the traditional dyad of theory and experiment. Often, such insights manifest themselves in the scientific exploration process in the form of computational studies built out of multiple computational experiments corresponding to individual runs of simulation software. Examples of such studies range from exploration of design spaces in engineering to molecular simulations for drug design.Traditionally, much research effort has been put into discovering ways to speed up the performance of a single simulation under high levels of parallelism. However, relatively less effort has been directed toward improving the performance of entire computational studies. As gains in computation power is increasingly being delivPermission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. To copy otherwise, to republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. ered on ever-higher levels of parallelism, the ability to exploit parallelism inherent in computational studies becomes more important.One example that demonstrates this rift is in Design Space Exploration (DSE). DSE is a type of computational study used in various disciplines such as automotive design, mechanical engineering, electrical engineering, chemical engineering and medicine (15; 21; 9; 5; 14). An example of multi-experiment studies, DSE relies on multiple executions of a simulation code using different input parameters to discover a region of interest. Each execution would simulate, for example, the dynamics of a car crash under variously-shaped body frames, or the accuracy of a chemical simulation software under different values of model parameters. Out of all these simulations, a subset is then identified as the 'best' and singled out as the belonging to the region of interest.Since the simulations in a DSE are completely independent of each other, DSE can be a trivially parallel problem. However, as shown in (1) and (23), if the runtime system understands the characteristics of the underlying DSE, the system can use the results of earlier simulations to guide the exploration in later simulations, significantly reducing the overall size of the search space. Additionally, (22) shows that, if the runtime system can store the results and internal states of some early simulations, they can be reused by later simulations, thus reducing the runtime of later simulations and the overall run time of the DSE.Hence, not all simulations are created equal: some simulations may be more important because their results and internal states have more reuse potential, or because their results are beneficial to trimming the design space in later exploration. Thus, if the system can devote more computational resources to these higher-priority simulations, it could improve the runtime of the DSE.(23) and (22) have shown how application-specific knowledge can be used to improve the performance of computational studies made up of multiple execution of serial simulation codes. This paper expands on that work by looking at how application-specific knowledge can be used to schedule and allocate resources for computational studies made up of multiple execution of parallel simulations codes. In particular, we examine how to expand on the work in traditional parallel job scheduling, described in Section 6, to incorporate application-specific knowledge. This knowledge helps the system decide which simulations to run, and in what order, as well as to decide which processing elements to devote to execute each simulation.Section 2 describes the formulation of the multi-experiment computational study problem, and presents the helium model validation study (5), which serves as a running example throughout the paper. Section 3 introduces the SimX system, a runtime system designed to conduct multi-experiment studies. Section 4 describes how application-level knowledge can influence system decisions 35 This paper described system support for and the benefits from exploiting application-specific knowledge of a multi-experiment study involving dozens of executions of a parallel simulation code. We have demonstrated that, by taking into account information such as reuse classes, scaling behavior, and study objectives in its sampling strategies, batching policies, and preemption policies, the SimX system can reduce the overall run time of the helium model validation study by more than four times.. While this paper has demonstrated a number of improvements, additional opportunities remain. For example, the current SimX system does not have knowledge of expected run times -only that runs with reuse are expected to take less time. An implementation of SimX that takes advantage of the simulation software's performance model (provided by the user or inferred from SISOL) can construct more sophisticated execution plans to further reduce the run time of the study. Also, SimX currently treats all worker processes as equal, but by being topologically-aware, SimX can co-locate nearby processors in the same worker processor groups, thereby further improving the performance of parallel simulations. Time (mins) Figure 7 . Helium validation study scheduling graph, Configuration E SimX builds on a body of related work, some of which are mentioned here.. The issue of resource allocation in a multi-processor environment is not new. (7) surveys conventional parallel scheduling techniques such as dynamic re-partitioning to minimize the turn-around time of individual tasks. (18) and (17) advocate "fairness" in distributing processing elements: the proportion of processing elements out of the whole cluster assigned to a task is decided by comparing its expected run time to that of the other tasks on the task queue. (19) reduces the parallel overhead of individual tasks by ensuring they are run on co-located processors. However, as is apparent, these systems differ from SimX in that SimX aims to minimize the overall run time of the entire study, while these systems focus on the turn-around time of individual tasks.. Theoretical results of the Multi-Processor Scheduling problem (MPS) are surveyed in (8) . In MPS, a system tries to allocate processing elements to a group of inter-dependent tasks while minimizing the total makespan of the entire group of tasks. However, the MPS model does not capture application-specific information such as result reuse and scaling overhead.. Grid-based parameter sweep infrastructures provide scheduling support for running the same application with a change in parameter values across distributed resources. Example systems include Nimrod (2), Nimrod/O (1), Condor (20) , Globus (11), Virtual Instruments (6), and NetSolve (3). Like SimX, they aim to minimize the makespan of an entire computational study, but they primarily focus on fault tolerance, resource management, and load balancing issues on grid computing infrastructures, rather than the use of application-level knowledge in resource allocation and scheduling. Computer simulation has become an integral part of the scientific method, often delivering deeper insights into complex physical processes than possible using only the traditional dyad of theory and experiment. Often, such insights manifest themselves in the scientific exploration process in the form of computational studies built out of multiple computational experiments corresponding to individual runs of simulation software. Examples of such studies range from exploration of design spaces in engineering to molecular simulations for drug design.. Traditionally, much research effort has been put into discovering ways to speed up the performance of a single simulation under high levels of parallelism. However, relatively less effort has been directed toward improving the performance of entire computational studies. As gains in computation power is increasingly being delivPermission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. To copy otherwise, to republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. ered on ever-higher levels of parallelism, the ability to exploit parallelism inherent in computational studies becomes more important.. One example that demonstrates this rift is in Design Space Exploration (DSE). DSE is a type of computational study used in various disciplines such as automotive design, mechanical engineering, electrical engineering, chemical engineering and medicine (15; 21; 9; 5; 14) . An example of multi-experiment studies, DSE relies on multiple executions of a simulation code using different input parameters to discover a region of interest. Each execution would simulate, for example, the dynamics of a car crash under variously-shaped body frames, or the accuracy of a chemical simulation software under different values of model parameters. Out of all these simulations, a subset is then identified as the 'best' and singled out as the belonging to the region of interest.. Since the simulations in a DSE are completely independent of each other, DSE can be a trivially parallel problem. However, as shown in (1) and (23) , if the runtime system understands the characteristics of the underlying DSE, the system can use the results of earlier simulations to guide the exploration in later simulations, significantly reducing the overall size of the search space. Additionally, (22) shows that, if the runtime system can store the results and internal states of some early simulations, they can be reused by later simulations, thus reducing the runtime of later simulations and the overall run time of the DSE.. Hence, not all simulations are created equal: some simulations may be more important because their results and internal states have more reuse potential, or because their results are beneficial to trimming the design space in later exploration. Thus, if the system can devote more computational resources to these higher-priority simulations, it could improve the runtime of the DSE.. (23) and (22) have shown how application-specific knowledge can be used to improve the performance of computational studies made up of multiple execution of serial simulation codes. This paper expands on that work by looking at how application-specific knowledge can be used to schedule and allocate resources for computational studies made up of multiple execution of parallel simulations codes. In particular, we examine how to expand on the work in traditional parallel job scheduling, described in Section 6, to incorporate application-specific knowledge. This knowledge helps the system decide which simulations to run, and in what order, as well as to decide which processing elements to devote to execute each simulation.. Section 2 describes the formulation of the multi-experiment computational study problem, and presents the helium model validation study (5) , which serves as a running example throughout the paper. Section 3 introduces the SimX system, a runtime system designed to conduct multi-experiment studies. Section 4 describes how application-level knowledge can influence system decisions made by SimX. In Section 5, we evaluate the effectiveness of various types of application-level knowledge in the helium model validation study. Section 6 provides an overview of previous work, and we conclude in Section 7.

O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O


Refactoring Java programs for flexible locking Recent versions of the Java standard library offer flexible locking constructs that go beyond the language's built-in monitor locks in terms of features, and that can be fine-tuned to suit specific application scenarios. Under certain conditions, the use of these constructs can improve performance significantly, by reducing lock contention. However, the code transformations needed to convert between locking constructs are non-trivial, and great care must be taken to update lock usage throughout the program consistently. We present Relocker, an automated tool that assists programmers with refactoring synchronized blocks into ReentrantLocks and ReadWriteLocks, to make exploring the performance tradeoffs among these constructs easier. In experiments on a collection of real-world Java applications, Relocker was able to refactor over 80% of built-in monitors into ReentrantLocks. Additionally, in most cases the tool could automatically infer the same ReadWriteLock usage that programmers had previously introduced manually. As multi-core processors are becoming pervasive, programs are becoming more concurrent to take advantage of the available parallelism. However, increasing concurrency in a program is often non-trivial, due to various potential scalability bottlenecks. One common bottleneck is lock contention, where scalability is limited by many threads waiting to acquire some common lock in order to safely access shared memory.. Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. To copy otherwise, to republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Various solutions exist for addressing lock contention, each with benefits and drawbacks. Approaches that avoid locks altogether include lock-free data structures (see, e.g., [17] ) and transactional memory (TM) [11] . However, writing correct lock-free data structures requires more expertise than can be expected from most programmers, and the semantics of TM may not be suitable in some cases (e.g, if I/O needs to be performed). Making locking more fine-grained can also increase concurrency, but potentially risks introducing subtle race conditions. In the context of Java, the standard java.util.concurrent library (in the sequel abbreviated as j.u.c) provides a number of data structures and locking constructs that could also be helpful, with their own tradeoffs. With all these options, there is a strong need for tool support to help programmers experiment with different solutions to see what works best in a particular situation.. In this paper, we focus on refactoring support for the advanced locking constructs available in j.u.c [21] . The ReentrantLock type enables many features unsupported by Java's built-in locks, such as non-block-structured lock operations, checking if a lock is held (tryLock()), interrupting lock acquisition, and specifying fairness behavior under contention. Additionally, the ReadWriteLock type enables distinguished reader and writer locks, where multiple threads holding the reader lock may execute concurrently. The goal of our research is to provide refactoring tools that support the transition from built-in locks to these advanced lock types.. Many difficulties arise when manually transforming a program to use the locking constructs of j.u.c, motivating better tool support. First, these constructs lack the concise and intuitive syntax of the synchronized blocks associated with Java's built-in monitor locks. Instead, locks are modeled as objects, and lock operations as method calls, and the burden is on the programmer to ensure that acquisition and release of locks are properly matched. Second, the relative performance of different lock types strongly depends on the number of threads and their workload, and on the architecture and JVM being used. As we shall show in Section 2, these performance tradeoffs are often unclear, and may change as programs and JVMs evolve. Therefore, programmers may need to switch back and forth between different lock types to determine the best lock for the job. Third, the transformation from one locking construct to another can require tricky non-local reasoning about program behavior. All code blocks using the same lock must be transformed together to ensure behavior preservation, and discovering all such blocks can be nontrivial. In some cases, the migration to advanced locks is impossible when the program extends a framework that relies on a specific form of synchronization. Introducing read-write locks requires careful reasoning about where a read lock is safe to introduce, as incorrect use of a read lock can lead to subtle race conditions.. In this paper, we present Relocker, an automated refactoring tool Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. To copy otherwise, to republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. that can replace built-in monitor locks with ReentrantLocks and The Java class libraries now provide flexible locking constructs that can improve performance by reducing lock contention. However, experimenting with these locks has been difficult as it requires non-trivial code transformations. We have presented algorithms for determining how programs can be refactored to use. ReentrantLocks and ReadWriteLocks instead of built-in monitor locks, and implemented these algorithms in an automated refactoring tool called Relocker. In an evaluation on a collection of Java programs, Relocker was able to convert over 80% of the monitor locks in these programs into ReentrantLocks. Moreover, Relocker was able to infer read-locks in most cases where programmers had previously introduced them manually.. Future work includes the design of refactorings for shrinking the regions of code protected by locks, possibly by taking advantage of the ability of ReentrantLocks to protect non-block-structured regions. In the same spirit, a future tool could help developers safely downgrade write locks to read locks (a feature supported by ReadWriteLock) to further decrease lock contention. Most previous work on refactoring has concentrated only on sequential programs without considering the implications of concurrency. Early refactoring research studied the mechanics of expressing behavior-preserving transformations for sequential programs using pre-and post-conditions [20, 23] and program dependence graphs [9, 10] . Later work considered various features of sequential programs such as class hierarchies [12, 28, 29] , generics [5, 6, 14, 31] , design patterns [13] , and access modifiers [27] . Other research has focused on refactoring support to adapt programs to evolving libraries [3] , combining refactorings with other programs transformations [22] , empirical studies [18, 19] , and domain-specific languages for specifying refactorings [30] .. Schäfer et al. [26] proposed to formulate refactorings in terms of their effect on static semantic dependencies, such as name binding or def-use dependencies. The present authors then showed how this approach can be extended to a concurrent setting by using dependencies to statically capture concurrent behavior [25] .. Recently, there has been a lot of interest in refactoring programs to enhance their concurrent behavior. The CONCURRENCER tool of Dig et al. [2] refactors code to make use of ConcurrentHashMaps and AtomicIntegers, also provided by the j.u.c library. Use of such types is another technique for improving scalability by reducing lock contention. Dig et al.'s RELOOPER tool [4] refactors loops to execute in parallel via the proposed ParallelArray class. Recently, the same group have also proposed a technique and a tool for making classes immutable, thereby ensuring their thread safety [15] .. Balaban et al. [1] considered the issue of migration from legacy classes (e.g., Vector) to functionally equivalent classes that replace them (e.g., ArrayList). While this work was primarily concerned with handling incompatibilities in the APIs, some support was provided to ensure that synchronization behavior was preserved, by inserting synchronization wrappers where needed. The REEN-TRANCER tool transforms sequential programs to be reentrant, enabling safe parallel execution [33] . Finally, several researchers have tackled the problem of implementing refactorings for X10, a Javabased language with sophisticated concurrency support, and have reported promising first results [7, 16] .

B O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B I O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B O O O O O O O O O O O O O B O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O


Handling Defeasibilities in Action Domains Representing defeasibility is an important issue in common sense reasoning. In reasoning about action and change, this issue becomes more difficult because domain and action related defeasible information may conflict with general inertia rules. Furthermore, different types of defeasible information may also interfere with each other during the reasoning. In this paper, we develop a prioritized logic programming approach to handle defeasibilities in reasoning about action. In particular, we propose three action languages AT 0 , AT 1 and AT 2 which handle three types of defeasibilities in action domains named defeasible constraints, defeasible observations and actions with defeasible and abnormal effects respectively. Each language with a higher superscript can be viewed as an extension of the language with a lower superscript. These action languages inherit the simple syntax of A language but their semantics is developed in terms of transition systems where transition functions are defined based on prioritized logic programs. By illustrating various examples, we show that our approach eventually provides a powerful mechanism to handle various defeasibilities in temporal prediction and postdiction. We also investigate semantic properties of these three action languages and characterize classes of action domains that present more desirable solutions in reasoning about action within the underlying action languages. Representing defeasibility is an important issue in common sense reasoning. In reasoning about action, this issue becomes more difficult because domain and action related defeasible information may conflict with general inertia rules -that are necessary to specify things that persist with respect to actions and usually defeasible as well. Furthermore, different types of defeasible information may also interfere with each other during the reasoning. Therefore, most previous action theories usually ignored such defeasible information in problem domains. However, recent work on causality reveals that in many situations defeasibility plays an important role in temporal prediction and postdiction and ignoring this issue may cause difficulties in deriving correct solutions in reasoning about action.. Let us consider the Switch-Power domain that was first addressed in (Zhang, 1999) , where two domain constraints were taken into account:. if the switch is on, then the light is usually on;. if there is no power, then the light is not on.. Intuitively, the first constraint is defeasible from our common sense. For instance , even if the switch is on, the light might not be on if there is no power, or there is a problem in the circuit, and so on. But if this constraint is not expressed as a defeasible rule, we may have a difficulty in our reasoning. Suppose we simply represent the above two constraints as logical implications Switch ⊃ On and ¬Power ⊃ ¬On respectively. If the initial state is {On, Power , Switch} and the robot is asked to perform an action Cut -Power with effect ¬Power (e.g. a fire alarm leads the robot to perform this action). Clearly, Cut -Power will cause a direct effect ¬Power , and then from constraint Switch ⊃ On and ¬Power ⊃ ¬On, an indirect effect ¬Switch is derived. Obviously, this effect is not quite reasonable from our intuition as cutting off the power should be irrelevant to the switch's position. People may argue that the above problem is due to the duality of logical implication (i.e. A ⊃ B ≡ ¬B ⊃ ¬A). Now suppose we adopt McCain and Turn's causal theory (McCain & Turner, 1995) where constraints (1) and (2) are represented as inference rules Switch ⇒ On and ¬Power ⇒ ¬On respectively 1 . Then under the same initial state as above, it turns out that action Cut -Power becomes unexecutable because the effect ¬Power together with rule ¬Power ⇒ ¬On contradicts fact On which is derivable from fact Switch and rule Switch ⇒ On. This is not a desirable solution either.. The above example just illustrates one type of defeasibility -defeasible constraints, which causes difficulties in reasoning about action. In fact, there are other types of defeasible information, such as defeasible observations and actions with defeasible and abnormal effects, that also significantly influence temporal prediction and postdiction. Although the problem of defeasibilities has been investigated by some researchers recently, e.g. (Baral & Lobo, 1997; Geffner, 1997; Jab lonowski et al., 1996; Zhang, 1999) , none of the previous proposals is completely satisfactory in terms of representing and handling different types of defeasibilities in temporal reasoning (we will discuss this issue in section 7).. In this paper, we address three basic types of defeasible information related to temporal prediction and postdiction where incomplete information is allowable: defeasible constraints, defeasible observations and actions with defeasible and abnormal effects. Our goal is to handle these three types of defeasibilities in reasoning about action under a unified framework of logic programming.. The issue of representing action in logic programming languages is not new. It was explored by some researchers previously, e.g. (Eshghi & Kowalski, 1989) . However, probably Gelfond and Lifschitz's work (Gelfond & Lifschitz, 1993) was the first time to make a major progress in this direction. By introducing a simple action language A, Gelfond and Lifschitz's action formulation was able to deal with both temporal prediction and postdiction, while properties of actions were characterized by translating action language A into the language of extended logic programs (Gelfond & Lifschitz, 1991) . In other words, in Gelfond and Lifschitz's formulation, extended logic program was used as an implementation of the high level action language A.. It has been recognized that logic programming can not only be used as the implementation of a high level action language, but also can be used as a basis for providing a formal semantics of the high level language, e.g. (Baral & Lobo, 1997) . In this paper, we further demonstrate that prioritized logic programming has a great flexibility to serve as a semantic basis to develop high level action languages that handle various information conflicts in reasoning about action. The paper is organized as follows. Section 2 briefly reviews the concept of prioritized logic programs. Section 3 proposes a simple action language AT 0 which can represent actions in domains with defeasible constraints. The syntax of AT 0 is similar to that of A style action languages. A transition system is proposed to provide a formal semantics of AT 0 , where a corresponding prioritized logic program is employed as a basis for defining such a transition system. Section 4 then extends action language AT 0 to AT 1 so that it can represent defeasible observations and shows how it handles the problem of temporal postdiction under the occurrence of defeasible observations. Section 5 further generalizes AT 1 to action language AT 2 to represent actions with defeasible and abnormal effects. Section 6 then investigates various properties of action languages AT 0 , AT 1 and AT 2 and characterize specific classes of action domains that may present desirable solutions in reasoning about action. Section 7 discusses related work, and finally section 8 concludes the paper with some remarks. The syntax of AT 1 is the same as AT 0 's except that AT 1 also has an observation proposition of the form:. where L, L 1 , · · · , L n are fluent expressions, and A 1 , · · · , A l are actions. Intuitively, (20) says after actions (20) represents a kind of defeasible information. In the case that no action occurs in (20), (20) can be written as the following form:. Under the language AT 1 , we define a domain description D to be a finite set of observation propositions, causal propositions and action effect propositions. AT 1 will still have the value proposition (4) and its special case the initial proposition (5), but are only used as query statements in AT 1 .. We will use a similar way as described in section 3.2 to develop a formal semantics of AT 1 based on a transition system that is defined on the basis of the translation from a AT 1 domain description into a PLP. We have developed a unified action formulation to handle three types of defeasibilities in reasoning about action. Our formulation consists of three action languages named AT 0 , AT 1 and AT 2 respectively. We have showed that our action formulation is applicable to both temporal prediction and postdiction with incomplete information while defeasible constraints, defeasible observations and actions with defeasible and abnormal effects are admitted. As discussed in the previous section, although the issue of defeasibility in reasoning about action has been addressed by some researchers recently, our work presented here is the first effort to handle various defeasible information in temporal reasoning by using a prioritized logic programming approach. It enhances the viewpoint that the logic programming languages can be employed as efficient low level formal languages for reasoning about action.. Besides the author's work (Zhang & Foo, 1997a) , different prioritized logic programming formalisms have been proposed recently, e.g. (Brewka, 1996; Brewka & Eiter, 1999; Grosof, 1997) . The reason why we choose our PLPs to develop our action formulation is as follows. First we think that the answer set semantics for PLPs provides an intuitive and natural interpretation for conflict resolution in logic programs, and hence it is easy to use not only in reasoning about action, but also in other aspects of modeling system dynamics (Zhang & Foo, 1997b; Zhang & Foo, 1998) . Second, a propositional prioritized logic programming system (PLPS) has been implemented recently by the author and his students (Y et al., 2001) . We believe that our PLPS can finally provide a practical programming language prototype for representing actions with the capability of the defeasibility handling within the framework we proposed in this paper.. The computational issue of prioritized logic programs has been addressed in the author's another work (Zhang, 2001) . Briefly, the author has proved that for a propositional prioritized logic program, deciding whether it has an answer set is NP-complete, and deciding whether a given ground literal is entailed from this prioritized logic program is Π P 2 -complete. It is also easy to observe that since a rule containing variables in a PLP is viewed as a set of ground instances of this rule by replacing variables with all possible constants occurring in the PLP, under the case that a PLP does not have function symbols, the number of defeated rules eliminated from this PLP as described in Definition 2 is always finite. Hence, we can always compute a finite reduct of such PLP 17 . In the case that there are function symbols occurring in a PLP, the situation is different. Basically, the set of ground instances of a rule, that includes variables and function symbols, may be infinite and therefore it might be possible that there are infinite number of defeated rules which should be eliminated from the original PLP. Under this situation, a reduct containing infinite rules may be produced according to Definition 2. From a practical viewpoint, we are only able to deal with finite reducts. To overcome this problem, we can set a proper restriction on the variable substitution. For instance, in the modified Switch-Power domain discussed in Example 4 (see section 3.2.2), if all we are interested is to know what are the effect after actions Cut-Power and Turn-On are executed, then in the computation of the answer set of P AT 0 (Switch-Power ′ ), we only need to consider situations S 0 , Result (Turn-On, S 0 ), Result (Cut -Power , S 0 ), and Result (Turn-On, Result (Cut -Power , S 0 )). This implies that the ground form of PLP P AT 0 (Switch-Power ′ ) only has finite rules and hence it always has a finite reduct.. Finally, we should mention that currently our action formulation cannot represent nondeterministic actions and disjunctive domain information. That is, we only consider deterministic problem domains in this paper. This is due to the limit of prioritized logic programs inherited from extended logic programs. But we would argue that our prioritized logic programs are extendedable to represent disjunctive information by using a similar method described in (Gelfond & Lifschitz, 1991) for extended logic programs, and our action formulation can then be extended to represent nondeterministic actions.

O O O O O O B O O O O O B I I O B I I O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B I O O O O O B I I O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B I I O O O O O O B O O O O O B I I O B I I O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B O O O O O O O O O O O O O O O O O O O O O B I I O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B O O O O O O B I I O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B I O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B I I O O O O O B I O O O O O O B I O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B I O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B I O O O O O O O O O O O O O O O O O O O O O O B I I O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B I I O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B I I O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B O B I I O O O O O O O O O O O O O O O O O O O O O B I O O O O B I O O O O O O O B I O O O O O O O O O O O B I I O O O O O O O O O O O B I O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B I I O O O O O O O O O O O O O O O O O O O O O O B I O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O


A Hybrid End-to-End QoS Path Computation Algorithm for PCE-Based Multi-Domain Networks Abstract Inter-domain quality of service (QoS) routing is a challenging problem for today's Internet. This problem requires the computation of paths that cross multiple domains and meet different QoS constraints. In addition, the used computation methods must meet the constraints of confidentiality and autonomy imposed by the domains of different operators. Path computation element (PCE)-based architecture offers a promising solution for inter-domain QoS routing. It ensures the computation of end-to-end QoS paths while preserving the confidentiality and the autonomy of the domains. In this paper, we propose a novel hybrid end-to-end QoS path computation algorithm, named HID-MCP, for PCE-based networks. HID-MCP is a hybrid algorithm that combines the advantages of precomputation and on-demand computation to obtain end-to-end QoS paths. Moreover, it integrates a crankback mechanism for improving path computation results in a single domain or in multiple domains based on the PCE architecture. Detailed analyses are provided to assess the performance of our algorithm in terms of success rate and computational complexity. The simulation results show that our algorithm has an acceptance rate of the requests very close to the optimal solution; precisely, the difference is lower than 1 % in a realistic network. Moreover, HID-MCP has a low computational complexity. Besides, our solution relies on the PCE architecture to overcome the limitations related to inter-domain routing such as domain autonomy and confidentiality.A. Frikha (&) Á S. Lahoud Á B. Cousin In this paper, we studied the inter-domain QoS routing problem. We proposed a novel inter-domain QoS routing algorithm based on a hybrid computation scheme, named HID-MCP. Our algorithm relies on the PCE architecture. This architecture allows end-to-end path computation subject to multiple QoS constraints, while preserving the confidentiality and the autonomy of the domains. We introduced two different mechanisms for improving the success rate of the HID-MCP algorithm. The first mechanism performs local improvement using an intra-domain crankback, while the second one executes a global improvement using an inter-domain crankback.. The simulation results showed that HID-MCP, with both of the aforementioned approaches, has a success rate very close to the optimal solution while having a low computational complexity. We also compared the average computational time of the path combination and the on-demand computation. This comparison study showed us the advantage of using pre-computation in reducing the computational time of our proposed algorithm.. As future prospects of this work, the stability of the pre-computed paths should be analyzed when they deal with dynamic changes of link state. This allows inferring the validity of the pre-computed paths after an eventual change of the network conditions. Another interesting extension for this work takes into account operators that do not participate in our scheme. In fact, when End-to-End services have to be set over several networks managed by different providers, an agreement has to be established between these providers. Thus we made the assumption that all providers of the alliance have accepted to participate in the proposed inter-domain QoS routing algorithm. In other cases, if one operator does not accept to participate in the computation scheme, we include this as a constraint in the domain sequence selection, in order to avoid this operator's domain.

O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B I I O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B I O O O O O O O O O B I O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B I I O O O O O B I I O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B I O O O O O O O O O B O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B I I O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O


Probabilistic rebound Turing machines This paper introduces a probabilistic rebound Turing machine (PRTM), and investigates the fundamental property of the machine. We ÿrst prove a sublogarithmic lower space bound on the space complexity of this model with bounded errors for recognizing speciÿc languages. This lower bound strengthens a previous lower bound for conventional probabilistic Turing machines with bounded errors. We then show, by using our lower space bound and an idea in the proof of it, that (i) $[PRTM (o(logn))] is incomparable with the class of context-free languages, (ii) there is a language accepted by a two-way deterministic one counter automaton, but not in $[PRTM(o(logn))], and (iii) there is a language accepted by a deterministic one-marker rebound automaton, but not in $[PRTM(o(logn))], where $[PRTM(o(logn))] denotes the class of languages recognized by o(logn) space-bounded PRTMs with error probability less than 1 2 . Furthermore, we show that there is an inÿnite space hierarchy for $[PRTM(o(logn))]. We ÿnally show that $[PRTM(o(logn))] is not closed under concatenation, Kleene+, and length-preserving homomorphism. This paper answers two open problems in a previous paper. : S 0 3 0 4 -3 9 7 5 ( 0 1 ) 0 0 0 9 8 -6 The rebound automaton (RA) introduced by Sugata et al. [17] has the same structure as a two-dimensional ÿnite automaton [1, 8, 14] , but an input to it is a square tape whose top row is a word to be recognized, and whose other symbols are all blank. It was demonstrated in [17] that many nonregular languages (e.g., the languages {a n b n c n | n¿1} and {ww | w ∈ {0; 1} * }) are accepted by RAs. In papers [9, 11, 12, 15] , investigations of RAs have been continued. Furthermore, in [20] , alternating rebound Turing machines were introduced, and their fundamental properties were investigated. It should be noted that Petersen [11] (resp., [12] ) gave a language accepted by a twoway (resp., one-way) deterministic one-counter automaton, but not accepted by any nondeterministic RA, and Petersen [12] gave a separation of the classes of languages accepted by deterministic and nondeterministic RAs, solving the long standing open problems.. Recently, in [19] , we introduced a probabilistic rebound automaton (PRA), and showed that (1) the class of languages recognized by PRAs with error probability less than 1 2 , $[PRA], is incomparable with the class of context-free languages, (2) there is a language accepted by a two-way nondeterministic one counter automaton, but not in $[PRA], (3) there is a language accepted by a deterministic one-marker RA, but not in $[PRA], and (4) $[PRA] is not closed under concatenation and Kleene +. It is quite natural to introduce a probabilistic rebound Turing machine (PRTM) which is a PRA equipped with one semi-inÿnite read-write storage tape. In this paper, we investigate recognizing powers, space hierarchy, and closure property of o(log n) spacebounded PRTMs with error probability less than 1 2 . Section 2 of the paper presents some deÿnitions and notations necessary for this paper.. Dwork and Stockmeyer [2] proved an impossibility result for probabilistic ÿnite automata with bounded errors. By using an idea similar to the proof of this result, Freivalds and Karpinski [4] proved, for the ÿrst time, a sublogarithmic lower space bound for probabilistic Turing machines with bounded errors. In Section 3, by extending their proof techniques to our model, we ÿrst prove a sublogarithmic lower space bound on the space complexity of our model with bounded errors for recognizing speciÿc languages. We believe that our sublogarithmic space lower bound is the strongest for probabilistic machines (with bounded errors) so far, because our o(log n) space-bounded models are more powerful than conventional o(log n) space-bounded probabilistic Turing machines, which is shown below.. Freivalds and Karpinski [4] showed, by using their lower space bound theorem, that there is a context-free language not accepted by any o(log n) space-bounded probabilistic Turing machine with bounded error. Pal, i.e., the set of all the palindromes, is such a language. Dwork and Stockmeyer [2] also showed that there is another context-free language 'Center = {u1v | u; v ∈ {0; 1} * and the lengths of u and v are the same}' not accepted by any o(log n) space-bounded probabilistic Turing machine with bounded error. It is easy to see that the languages Pal and Center are recognized by deterministic RAs, and thus by PRAs with bounded errors. Thus, L(n) space-bounded PRTMs with bounded errors are more powerful than L(n) space-bounded probabilistic Turing machines with bounded errors for any L(n) = o(log n).. In Section 4, by using our lower space bound theorem and an idea in the proof of it, we investigate relationships between $[PRTM(o(log n))], which is the class of languages recognized by o(log n) space-bounded PRTMs with error probability less than 1 2 , and other classes of languages. We ÿrst show that $[PRTM(o(log n))] is incomparable with the class of context-free languages. We next show that there is a language accepted by a two-way deterministic one counter automaton [6] , but not in $[PRTM(o(log n))]. This result solves an open problem in [19] . Further, we show that there is a language accepted by a deterministic one-marker RA, but not in $[PRTM(o (log n))].. Section 5 investigates a space hierarchy for $[PRTM(o(log n))], and shows that if L(n) is space constructible by a deterministic rebound Turing machine (DRTM) [20] , log log n 6 L(n) = o(log n), and L (n) = o(L(n)), then there is a language accepted by L(n) space-bounded DRTM, but not recognized by any L (n) space-bounded PRTM with error probability less than 1 2 . Section 6 investigates closure properties of $[PRTM(o(log n))]. We ÿrst show that $[PRTM(o(log n))] is not closed under concatenation and Kleene +. We next show that $[PRTM(o(log n))] is not closed under length-preserving homomorphism. This result solves an open problem in [19] . We again note that Petersen [11] showed that the class of languages accepted by nondeterministic RAs is not closed under length-preserving homomorphism.. Section 7 presents several open problems. We conclude this paper by giving the following open problems.. (1) Does $[PRTM(L(n))] properly contain the class of languages accepted by L(n) space-bounded deterministic (or nondeterministic) rebound Turing machines [20] for any L(n)? (2) Is there a language in $[PRTM(o(log n))] which cannot be accepted by any nondeterministic (or deterministic) two-way one counter automaton? (3) Is there an inÿnite space hierarchy for PRTMs with error probability ¡ 1 2 whose space are below log log n?

O O O O O O O O B I I I O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B I O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B I O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B I O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B I O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B I I I O O O O O O O O O O O O O O O O O O O B I O B I O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B I O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B I O O O O O O O O O O O O O O O


Minimum-link paths among obstacles in the plane Given a set of nonintersecting polygonal obstacles in the plane, the link distance between two points s and t is the minimum number of edges required to form a polygonal path connecting s to t that avoids all obstacles. We present an algorithm that computes the link distance (and a corresponding minimum-link path) between two points in time O(Ea(n)log 2 n) (and space O(E)), where n is the total number of edges of the obstacles, E is the size of the visibility graph, and a(n) denotes the extremely slowly growing inverse of Ackermann's function.The study of link distance problems is partially motivated by a robot motion-planning problem. Consider a point-size robot that wants to move in a collision-free way from a source position s to some target position t in the plane. Suppose the robot can

O O O O O O O O O O O O O O O O O O O B O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B O O O O B O O O O O O O O O O O O O O B O O O O O O O O O O O O O O O B O O B B O O O O O O O O O O O O O O B O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O


A unifying reference framework for multi-target user interfaces This paper describes a framework that serves as a reference for classifying user interfaces supporting multiple targets, or multiple contexts of use in the field of context-aware computing. In this framework, a context of use is decomposed in three facets: the end users of the interactive system, the hardware and software computing platform with which the user have to carry out their interactive tasks and the physical environment where they are working. Therefore, a context-sensitive user interface is a user interface that exhibits some capability to be aware of the context (context awareness) and to react to changes of this context. This paper attempts to provide a unified understanding of context-sensitive user interfaces rather than a prescription of various ways or methods of tackling different steps of development. Rather, the framework structures the development life cycle into four levels of abstraction: task and concepts, abstract user interface, concrete user interface and final user interface. These levels are structured with a relationship of reification going from an abstract level to a concrete one and a relationship of abstraction going from a concrete level to an abstract one. Most methods and tools can be more clearly understood and compared relative to each other against the levels of this framework. In addition, the framework expresses when, where and how a change of context is considered and supported in the context-sensitive user interface thanks to a relationship of translation. In the field of multi-target user interfaces is also introduced, defined, and exemplified the notion of plastic user interfaces. These user interfaces support some adaptation to changes of the context of use while preserving a predefined set of usability properties. Recent years have seen the introduction of many types of computers, devices and Web appliances. In order to perform their tasks, people now have available a wide variety of computational devices ranging over an important spectrum: mobile phones, UMTS phones, smart and intelligent phones, Personal Digital Assistants (PDAs), pocket PC, handheld PC, Internet enabled televisions (WebTV), Internet ScreenPhones, Tiqit computers, interactive kiosks, tablet PCs, laptop or notebooks, desktops, and electronic whiteboards powered by high end desktop machines (Fig. 1) . While this increasing proliferation of fixed and mobile devices fits with the need for ubiquitous access to information processing, this diversity offers new challenges to the HCI software community (Eisenstein et al., 2001 ). These include:. -Constructing and maintaining versions of single applications across multiple devices.. -Checking consistency between versions for guaranteeing a seamless interaction across multiple devices. -Building into these versions the ability to dynamically respond to changes in the environment such as network connectivity, user's location, ambient sound or lighting conditions.. To address these new requirements, the notions of multi-targeting and plasticity are introduced. Both deal with adaptation to context of use to cover this new diversity without exploding the cost of development and maintenance. We first define the notion of context of use and then precise the way multi-targeting and plasticity follow to satisfy these new requirements. A Unifying Reference Framework has been presented that attempts to characterize the models, the methods, and the process involved for developing user interfaces for multiple contexts of use, or so-called multi-target user interfaces. Here, a context of use is decomposed into three facets: the user, the computing platform including specific devices and the complete environment in which the user is carrying out interactive tasks with the platforms specified. Any variation of these facets can be considered as a change of the context of use that should or could be reflected in some way in the user interface.. The Unifying Reference Framework consists in an attempt to provide a better understanding and a common representation of scheme of the models, the methods and the process for multi-target user interfaces. First, it clarifies what are the models used (e.g., task, concept, presentation, dialog, user, platform, environment, interactors), when (e.g. at design-time vs. run-time), how (i.e. at the four levels of concern: task & concepts, abstract UI, concrete UI and final UI) and according to which process. Secondly, forward engineering can be expressed from the highest level of the framework (i.e. Task & concepts) to the lowest level (i.e. the Final UI), while Reverse engineering takes the inverse path. Bidirectional engineering or reengineering , that is a combination of both forward and reverse engineering, can be expressed equally. Thirdly, three types of relationships between the levels have been defined: reification for forward engineering, abstraction for reverse engineering and translation for migration from one context of use to another one. Fourthly, different entry points allow the process to be initiated at any point of the framework and not only at the top (like in a full top-down approach) or at the bottom (like in a full bottom-up approach). Fifthly, a special attention has been paid to support the expressivity of run-time mechanisms.. We hope that this Unifying Reference Framework will be used not only to characterise existing work in the domain of context-aware computing and to easily communicate this characterisation, but also to identify new opportunities for uncovered or underexplored paths in the framework. The combination of all the entry points, the models involved, the relationships used makes it very rich to express many configurations possible.

O O O O O B I I O O O O O O O O O O O O O O O O O O O O O O O O O O B I O O O O B I I O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B I I O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B I I O O O O O O O O O O O O O O O O O O O O O O B I I O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B I I O O O O O O O O O O O O O O O O O O O B I I O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B I I O O B I I O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B I I O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B I I O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B I I O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B I O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O


A note on worst-case performance of heuristics for maintenance scheduling problems We study a machine scheduling model in which job scheduling and machine maintenance activities have to be considered simultaneously. We develop the worst-case bounds for some heuristic algorithms, including a sharper worst-case bound of the SPT schedule than the results in the literature, and another bound of the EDD schedule. In this note, we will study the worst-case bound analysis of two heuristic algorithms for maintenance scheduling problems. The situation is as follows. We have a set of jobs to be processed on a single machine. The machine has to be interrupted for maintenance from time to time. The problem is to determine the schedule of jobs and the maintenance activities for the machine simultaneously.. When the objective is to minimize total completion time of jobs, the problem has been studied by Qi et al. [14] where they prove that the problem is NP-hard in the strong sense, and propose several heuristic algorithms including the SPT schedule. Meanwhile, the same scheduling model is independently studied by Akturk et al. [1, 2] with a different motivation from tool management where they interpret the maintenance activities as the tool changes. Recently, Akturk et al. [3] show that the SPT schedule has a worst-case bound of 2. In this paper, we will present some new results that further improve the bound.. The problem belongs to the field of machine scheduling with non-availability constraints (see [9, 13] for reviews). In general, there are two types of models: (1) the non-available machine periods are given and (2) the non-available machine periods are decision variables. Some recent results on the worst-case bound analysis of SPT and WSPT schedules for the former case can be found in Kacem and Chu [11] and Sadfi et al. [12] . Our model falls into the latter case. Some related results for similar models can be found in Cassady and Kutanoglu [4] , Chen [5] , Graves and Lee [7] , and Lee and Lin [10] . In the rest of this paper, we first formally define the problem in Section 2, then study the problem with two different objective functions in Sections 3 and 4, respectively. Our focus is the worst-case analysis for some simple heuristic algorithms.

O O O O O O O O B B O O O O O B O O O O B O O B O O O O O O O O O O O O O O O O O O B I O O B I O O O O O O O O O O O B I O O O O O O O B I O O O O O O B B O O O O O O O O O O O O O O O O O O O O O O O O O O B O O O O O O O O O O O O O O O B O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B I O O O B O O O O O O O O O O O O O O O O O O O O O B O O O O O O O O O O O O O B I O O B I O O O O O O O O O O O O O O O O O O O O O O O O B O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B I O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O