Design for responsibility: safeguarding moral perception via a partnership architecture Abstract Advanced warfare technologies (AWT) create unprecedented capabilities to control the delivery of military force up to the point, some argue, that we are loosing humanity. But dependence on them generates difficult moral challenges impacting the decision-making process, which are only beginning to be addressed. In order to arrive at an informed opinion about the impact of AWT on decision-making, we need to know more about what AWTs are and how they operate. We provide a short overview of the different types of AWTs and discuss the key principles that underlie Humanitarian Law. We also discuss the impact of physical distance and increased levels of autonomy on AWT and discuss the challenges posed to moral perception. Before such systems can be deployed, we need to rest assured that their usage enhances, rather than undermines, human decision-making capacities. There are important choices to be made, and sound design is 'design for responsibility'. As a solution, we therefore propose the partnership architecture that embeds concurrent views of the world and working agreements, ensuring that operators use appropriate information in the decision-making process. Today's use of drones is no longer limited to surveillance and reconnaissance tasks only. Drones are also deployed for the uncontroversial practise of targeted killings. Typically, a drone is launched in the vicinity of an area of interest but controlled from a remote control cabinet, often thousands of miles away. In addition, military organizations consider equipping drones with high levels of autonomy in order to reduce the degree and amount of interactions between them and their operators, thereby lowering the cost of ownership.. One issue within the academic and public discourse over military actions that has not yet received sufficient attention concerns the impact of advanced warfare technologies, like drones and other robots, on the human decision-making process. There is a growing concern that ethical values are violated as a result of high levels of autonomy and remote control. Scholars from different disciplines expressed concerns regarding implication on the human decision-making process due to the distance from the battlefield and increased levels of autonomy, potentially leading to the abdication of responsibility. The impact on the decision-making process also raises concerns with regard to the principles of distinction, proportionality and necessity, all critical elements of International Humanitarian Law.. Some scholars provide arguments in favour of such advanced technologies in warfare (Altman and Wellman 2009; Strawser 2013) . Firstly, for reasons of proportionality, they argue, the use is desirable if other means are equal. Using unmanned aerial vehicles to carry out, say, targeted killings leads to less damage and destruction than a large-scale military operation with boots on the ground. Secondly, states are under increasing pressure to minimize casualties amongst their own service personnel, especially during operations that are not directly classifiable as selfdefence (Shaw 2005) . Indeed, one of the morally and politically attractive features of advanced warfare technologies is their ability to protect the lives of service personnel (Strawser 2010) .. Needless to say, there have been critical voices. Ignatieff seems sceptical about the prospects of 'virtual war', while Robert Sparrow argues that (some types of) advanced warfare technologies must not be deployed because they undermine a commitment to moral and legal responsibility in the armed forces (Sparrow 2007) . On top of the responsibility gap, Noel Sharkey is worried about so-called killer robots as misuse might arise…'by extending the range of legally questionable, targeted killings by security and intelligence forces' (Sharkey 2010, p. 369) . Furthermore, Royakkers discusses emergence of the cubicle warrior that gets morally disengaged (Royakkers and van Est 2010). These critical voices are typically used as reasons not to deploy these advanced warfare technologies.. However, we stress the importance of this highly relevant debate, and we appreciate the arguments provided by the critics and proponents. But instead of rejecting advanced warfare technologies, we use those arguments to design better systems. This requires an informed opinion about the impact of advanced warfare technologies on the human decision-making process. Following value sensitive design rationales, it is important to (re)design advanced warfare technologies for ethical values like responsibilities, proportionality, necessity and discrimination. This will lead up to advanced warfare technologies that behave more like a team player or partner. Research in this area is in its infancy, but is likely to become more prominent. We begin by giving an overview of the different types of advanced warfare technologies and discuss some of the challenges they pose to moral perception The issue of moral perception, in fact, is crucial for a commitment to responsibility within the armed forces. We continue by making design recommendations. There are important choices to be made, and sound design is always 'design for responsibility'-or so we shall argue. We started by noting that some commentators have argued in favour of the deployment of advanced warfare technologies during combat. Indeed, there are some benefits associated with such advanced technologies. But the downsides posed by these systems must not be neglected either. Before advanced warfare technologies can be deployed, we need to rest assured that their usage is safe and that they enhance, rather than undermine, human decisionmaking capacities and a commitment to responsibility. This is important in any type of armed conflict. During military missions, the operational requirements upon advanced warfare technologies and those who operate them are high. Operators and their superiors need reliable information about the complex environment they operate in, especially when they are not directly present.. Following value sensitive design rationales, it is important to (re)design advance warfare technologies for a commitment to responsibility and for that, it is important to discuss ethical values like proportionality, necessity and discrimination. We therefore propose the partnership architecture that embeds concurrent views of the world and we discuss working agreements. Both ensure that operators use appropriate information in the decision-making process. There are important choices to be made, and sound design is 'design for responsibility'. The partnership approach is a promising way forward, especially in the light of a commitment to responsibility and when compared to proposals for fully operationally autonomous machines.

O O B O B I O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B I O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B O O O O O O O O O O O O O O O O O B I O O O O O O O O O O O O O B O O O O O O O O O O B O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B O O O O O O O O O O O B O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B I O O O B I O O O O O O O O B O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B I O O O O O O O O O O O O O O O O O O O O O O O O B O O O O O O O O O O O O O O O O B O O O O O O O O O O


Energy-Efficient Pre-Execution Techniques in Two-Step Physical Register Deallocation Instruction pre-execution is an effective way to prefetch data. We previously proposed an instruction pre-execution scheme, which we call two-step physical register deallocation (TSD). The TSD realizes pre-execution by exploiting the difference between the amount of instruction-level parallelism available with an unlimited number of physical registers and that available with an actual number of physical registers. Although previous TSD study has successfully improved performance, it still has an inefficient energy consumption. This is because attempts are made for instructions to be pre-executed as much as possible, independently of whether or not they can significantly contribute to load latency reduction, allowing for maximal performance improvement. This paper presents a scheme that improves the energy efficiency of the TSD by preexecuting only those instructions that have great benefit. Our evaluation results using the SPECfp2000 benchmark show that our scheme reduces the dynamic pre-executed instruction count by 76%, compared with the original scheme. This reduction saves 7% energy consumption of the execution core with 2% overhead. Performance degrades by 2%, compared with that of the original scheme, but is still 15% higher than that of the normal processor without the TSD. The load latency in cycles increases as LSI technology advances because the rate of improvement of memory access time is much slower than that of the processor's clock frequency. This gap between processor and memory is often called a memory wall. A general method of reducing latency due to a memory wall is to fill the gap with several cache hierarchy levels, and to satisfy load requests at as high a level as possible. However, this method is both very costly and often insufficient.. Data prefetching is an alternative or additional method of solving this problem. Many hardware schemes have been proposed for prefetching of data with both a regular pattern (e.g., [1] ) and an irregular pattern (e.g., [2] ). Instruction pre-execution (e.g., [3] ) is effective for prefetching data with an irregular pattern. Pre-execution of loads that miss the cache moves data from a lower level to an upper level of the memory hierarchy, before the main execution that builds the Manuscript received June 8, 2009 . † The authors are with the Department of Computational Science and Engineering, Nagoya University, Nagoya-shi, 464-8601 Japan.. † † The author is with the Department of Electrical Engineering and Computer Science, Nagoya University, Nagoya-shi, 464-8601 Japan.. * Presently, with Denso Corp. a) E-mail: ando@nuee.nagoya-u.ac.jp DOI: 10.1587/transinf.E92.D.2186. architectural state.. We previously proposed an instruction pre-execution scheme, which we call two-step physical register deallocation (TSD) [4] , [5] . A feature of this scheme that is different to other pre-execution based schemes is that the TSD realizes prefetching within a single thread context with a modest amount of simple hardware. The TSD removes the pipeline stall in the rename stage that is due to a shortage of physical registers, by deallocating a physical register temporarily and allocating it to an instruction. Such instructions are inserted into the instruction window. While waiting for the temporarily allocated physical register to be actually available, these instructions are executed (pre-execution) if their source operands are available, although the result is not written to the physical register. Instead, the result of a preexecuted instruction is passed to its dependent instructions by the bypass logic or a small buffer called the forwarding buffer [6] , and thus pre-execution can be performed continuously. If the pre-executed load incurs a cache miss, the requested data is moved from memory to a cache, thus realizing data prefetching. Later, when the temporarily allocated physical register has actually been available, the instruction is notified, and is executed again (main execution). At this time, the result is written to the physical register, as in a normal processor. In the main execution, a load will hit the cache, which would have been a miss without the prefetch in the earlier pre-execution.. Although TSD can reduce load latency, the previous study did not take into account energy consumption. The TSD attempted to pre-execute as many instructions as possible for maximal performance improvement. The instruction that can, however, potentially contribute to reducing load latency are those that are directly or indirectly related to a load causing a cache miss. Since pre-execution consumes extra energy of the execution core (the instruction window, function units, D-caches, etc.), to improve energy efficiency, only instructions that contribute greatly to performance improvement should be selectively pre-executed.. In this paper, we propose a scheme that achieves selective pre-execution for TSD [7] - [9] . Our scheme comprises the following two steps:. 1. The scheme finds a delinquent load [10] , and then searches for instructions on which the load depends, either directly or indirectly. 2. It optimizes the length of the instruction sequence obtained to achieve high energy efficiency. In this paper, we proposed a scheme to improve the energy efficiency of the TSD previously proposed. Our scheme selectively pre-executes only those instructions that contribute significantly to performance improvement. The evaluation results using the SPECfp2000 benchmark programs show a significant reduction in the number of pre-executed instructions, leading to a reduction in energy consumption, with only a modest performance degradation, compared to the original TSD. A number of prefetch studies based on pre-execution have been carried out [3] , [10] - [15] . Most of these schemes extract the instructions necessary for prefetching statically as a thread, and then spawn this thread at a certain point in the program execution to a different context of the processor. An energy-aware thread selection scheme proposed by Petric et al. [16] estimates performance benefit and energy consumption analytically, and then selects threads with good performance/energy tradeoff. The disadvantage of these schemes, including Petric's scheme, is that they require a multithreaded environment such as simultaneous multithreading [17] or chip multiprocessors. Even in such an environment, a disadvantage arises in that the context is consumed; it may be more profitable to allocate other threads to the context for a better throughput. Furthermore, static thread extraction and thread selection requires recompilation.. Among the multithreaded pre-execution schemes, a scheme in which pre-execution instructions are extracted dynamically is, to our knowledge, only the scheme proposed by Collins et al [18] . Like our scheme, this scheme also focuses on delinquent loads for energy efficiency, but unlike our scheme, it greedily extracts pre-execution instructions for high performance and thus does not optimize the length of the pre-execution instruction sequence for energy saving.. The only pre-execution scheme, to our knowledge, that does not need a multithreaded environment is runahead execution [19] , which attempts to exploit memory-level parallelism (MLP) when an L2 cache miss occurs. Mutlu et al. proposed several schemes to improve energy efficiency, for example, by suppressing ineffective runahead execution based on past history [20] . Yet, they neither focus on delinquent loads nor optimize the length of the runahead (i.e., pre-executed) instruction sequence, unlike in our scheme.

O O O O O O O O B I O O O O O O O O O O O B I O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B I O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B I O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O


Fully Scalable Fault-Tolerant Simulations for BSP and CGM Abstract Most of theoretical research on parallel computation has focused on shared-memory models such as PRAM [15] or specific interconnection network models such as the hypercube [23] . In these models the ratio of memory to processors is fairly small (typically Ç´½µ). Recently, bridging models such as BSP [30, 31] , CGM [7] , and LogP [6, 18] have been proposed, where the ratio of memory to processors is non-constant. In particular, the BSP model attracted considerable attention and many algorithms for important problems have been designed on this model [12, 13, 14, 8] .. In BSP and CGM there are Ô processors and a memory of Ò words (usually, Ò is also the input size) is distributed evenly across the processors.. The BSP and CGM models, as is usually the case, refers to ideal machines where all processors are fully operational. But the increasing complexity of multiprocessor computers makes the machines prone to hardware failures. This necessitates the design of algorithms that are resilient to hardware faults. A most natural solution is to design a general simulation mechanism of an ideal machine on its faulty counterpart.. In this paper we develop general techniques that can efficiently simulate ideal BSP (CGM) computations on BSP (CGM) machines where some processors may be faulty. The faults are deterministic (i.e., worst-case distributions of faults are considered) and static (i.e., they do not change in the course of computation). We assume that a constant fraction of processors are faulty and that a processor that tries to communicate with a faulty processor is notified, at the end of the communication round, that the communication was unsuccessful. The fault-tolerant simulation for PRAM with faulty processors was first studied by Kanellakis and Shvartsman [17] (for the deterministic distribution of faults) and Kedem, Palem and Spirakis [20] (for probabilistic faults). They considered fail-stop dynamic faults, i.e., faults may happen at any time during the computation and cause processors to stop till the end of computation. For the same model of faults Kedem et al. [19] designed fault-tolerant simulations that have constant expected slowdown under some assumptions on the faults probability. Diks and Pelc [9] developed efficient simulation algorithms for EREW PRAM under the probabilistic processor-fault model. Kanellakis, Michailidis and Shvartsman [16] developed an optimal simulation for EREW PRAM when all processor faults are static. Buss et al. [2] developed deterministic PRAM simulations under the model of restartable failures.. For PRAM with faulty memory, Chlebus, Gambin and Indyk [3] designed randomized simulations for both dynamic and static faults, assuming a constant fraction of deterministic memory faults. For static faults, they gave a simulation algorithm of Ò-processor CRCW PRAM on Ò ÐÓ Ò-processor CRCW PRAM with Ç´ÐÓ Òµ step overhead, which is preceded by an Ç´ÐÓ ¿ ¾ Òµ-time preprocessing. They also gave an algorithm for performing the simulation in real time, but in this case the number of processors of the faulty machine grows to Ç´Ò ÐÓ Òµ. Chlebus, Gasieniec and Pelc [5] presented a deterministic simulation of Ò-processor EREW PRAM on Ò-processor EREW PRAM prone to processor and memory failures, with step overhead Ç´ÐÓ Òµ and preprocessing time Ç´ÐÓ ¾ Òµ. Using randomization, Gasieniec and Indyk [10] reduced the number of processors to Ò ÐÓ Ò and the preprocessing time to Ç´ÐÓ Òµ without changing the step overhead, hence making the simulation work-optimal. They also proved the existence of a deterministic algorithm with the same step overhead and preprocessing time. Recently, Chlebus, Gambin and Indyk [4] To our best knowledge, there are no previous works on the fault-tolerance of CGM.

O O O O O B O B O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B O O O B O O O O O O O O O O O O O O O O O O O O O B O O O O O O O O O O O O O O O O O O O O O O B O B O O O O O O O O O O O O O O O O O O O O O O O O B O B O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B B O O B B O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B O B


Multidimensional Scaling For Group Memory Visualization We describe an attempt to overcome information overload through information visualization -in a particular domain, group memory. A brief review of information visualization is followed by a brief description of our methodology. We Ž . discuss our system, which uses multidimensional scaling MDS to visualize relationships between documents, and which Ž . we tested on 60 subjects, mostly students. We found three important and statistically significant differences between task performance on an MDS-generated display and on a randomly generated display. With some qualifications, we conclude that MDS speeds up and improves the quality of manual classification of documents and that the MDS display agrees with subject perceptions of which documents are similar and should be displayed together. q Information overload frustrates productive Internet use more and more every day. Searching and browsing waste time and yield unsatisfying results. Users feel that desired documents are tantalizingly near, yet buried beneath an avalanche of irrelevant, time-wasting reading matter. The Internet is like a library where new books arrive at a staggering pace, are shelved randomly, and where uncoordinated masses of tireless librarians stand ready, if given a slip of paper with a word scribbled on it, to race through the crowded aisles, retrieving 0 or 10,000 books containing the scribbled word, but nothing in between. It is a mess.. How can we make sense of the massive information overload that worsens every day? We can exploit our own vision system. Half of the human w x brain's neurons are associated with vision 13 , suggesting not merely a ready audience for information visualization, but highly capable partners. Recent advances in computer graphics technology have begun to exploit the cognitive opportunity enough to identify visualization as a field of research. In the 9 years since the first paper naming it as a field, a flood of research has taken the visualization label. In this brief, productive period, numerous developments have transpired that could be applied to business, but few applications explicitly meant for business have appeared in the visualization literature.. ( )The overall goal of our research is to reduce the problem of information overload, specifically in browsing and searching document collections, through information visualization. Although the broad domain of our work encompasses the Internet, we have chosen to narrow our focus, to start with, by working with the group memory generated by elec-Ž . w x tronic meeting systems EMS 15 . Each meeting Ž mediated by an EMS, like GroupSystems groupware developed at the University of Arizona MIS Depart-. ment, and marketed by Ventana , generates a log that can be used by future team members and others with a stake in the team's work. These logs are underutilized in practice. Our immediate goal is to produce and experiment with a series of mapsrsnapshots of meetings. Fig. 1 shows just such a map. A stake holder could flip through this set of mapsrsnapshots to find relevant meetings and only inspect interesting meetings. Further, only the interesting portions of the relevant meetings need to be viewed, since clicking on a region of the map brings up only the text of the meeting related to that region. Previous experiments at the University of Arizona have shown that a neural network technique, based Ž . on Kohonen's Self-Organizing Feature Map SOM , offers a viable alternative to traditional information w x retrieval methods for effective browsing 4 . The Ž SOM system constructs a map different from the . map in Fig. 1 of terms or documents automatically, showing relationships that would not be apparent in keyword search or browsing through indexed lists. Major limitations remain to be overcome with this technique, opening the way for other techniques to replace or be synthesized with the SOM. This paper describes an alternative technique from Ž . statistics, multidimensional scaling MDS . MDS cannot directly replace SOM, since it only determines distance between objects. Two important Ž . properties of the SOM are that it applies 1 bound-Ž . aries to regions containing objects, as well as 2 text labels for the bounded region. Our goal in the present research is to demonstrate the validity of MDS as a tool to locate objects relative to each other to improve user execution of a classification task. Success here would give us a foundation on which to use MDS as a visualization tool.. The remainder of the paper includes the following sections. In Section 2, we give a brief review of the visualization literature, focusing on a definition of visualization, and the history and taxonomy of the visualization literature. In Section 3, we describe the systems development methodology, which specifies an interplay between the development of a computer-based system and three research activities Ž . experimentation, observation, and theory building that system development contributes to. In Sections 3.2, 3.3 and 3.4, we describe our MDS system. In Section 3.5, we propose hypotheses to be tested with the working prototype of our MDS system. In Section 4, we give results of the test. In Section 5, we give conclusions based on the test results and present qualifications and future directions. Ø Cluster sizes generated by the m group are significantly smaller than those generated by the r group, confirming H . Sixty subjects, mostly students of MIS and ECE at the University of Arizona, were tested using the experimental interface shown in Fig. 9 . The subjects were presented with a screen full of clumps of dots. A menu allowed them to color dots according to categories, as well as to type a name in each of the selected categories.. Subjects could see the content of a single document by selecting the associated dot or by dragging a Ž . group of dots, as shown in Fig. 9 . Selected dot s could then be assigned a color, and the label for that color modified. Fig. 3 shows an almost completed experiment, in which all documents have been colored and all colors labeled with a category name.. Forty-five documents were used. Samples of two categories may be seen in Figs. 3 and 9. All the documents were generated in a meeting about the question captioned in Fig. 1 . ( )The subjects were divided into two groups, with Ž 30 subjects randomly assigned to each group. Because some of the subjects did not understand the instructions and gave nonresponsive results, some additional subjects were introduced to bring the total . of usable subjects to 60. Ž . One group of subjects the m group was presented with a display generated by MDS. The other Ž . group r group was presented with a randomly Ž . generated display. A third group the p group was created by projecting the points from the randomly generated space into the MDS space. A typical comparison between the m group and r group is shown in Figs. 10 and 11 , where we see plainly that the clusters specified by the m group are drastically smaller than those specified by the r group.. We selected the perimeters of the convex hulls of the clusters, in other words, the least enclosing convex polygons of the clusters, as measures of cluster size, and wrote a program to calculate the average convex hull perimeters for each group based on Ref.

B I O B I B O O O O O O O O O O B O O O O B I O O O O O B O O O O O O O O O O O O O O O O O B I O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B O O O O O O O O O O O O O O O O O O O O B O O O O O O O O O O O O O O O O O O O O O O O O O B O O O O O O O O O O O O O O O O O O O O O O O O O O O B O O O O O O O O O O O O O O O O O O O O O O O O O B O O O O O O O O O O O O O O O O O O O O O O O O B I O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B I O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B O O O O O O O O O O O O O O O O O O O O B O O O O O O B O O O O O O O B O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O


Learning Graphical Model Parameters with Approximate Marginal Inference Abstract-Likelihood based-learning of graphical models faces challenges of computational-complexity and robustness to model misspecification. This paper studies methods that fit parameters directly to maximize a measure of the accuracy of predicted marginals, taking into account both model and inference approximations at training time. Experiments on imaging problems suggest marginalization-based learning performs better than likelihood-based approximations on difficult problems where the model being fit is approximate in nature. G RAPHICAL models are a standard tool in image processing, computer vision, and many other fields. Exact inference and inference are often intractable, due to the high treewidth of the graph.. Much previous work involves approximations of the likelihood. (Section 4). In this paper, we suggest that parameter learning can instead be done using "marginalization-based" loss functions. These directly quantify the quality of the predictions of a given marginal inference algorithm. This has two major advantages. First, approximation errors in the inference algorithm are taken into account while learning. Second, this is robust to model mis-specification.. The contributions of this paper are, first, the general framework of marginalization-based fitting as implicit differentiation. Second, we show that the parameter gradient can be computed by "perturbation"-that is, by re-running the approximate algorithm twice with the parameters perturbed slightly based on the current loss. Third, we introduce the strategy of "truncated fitting". Inference algorithms are based on optimization, where one iterates updates until some convergence threshold is reached. In truncated fitting, algorithms are derived to fit the marginals produced after a fixed number of updates, with no assumption of convergence. We show that this leads to significant speedups. We also derive a variant of this that can apply to likelihood based learning. Finally, experimental results confirm that marginalization based learning gives better results on difficult problems where inference approximations and model mis-specification are most significant. Training parameters of graphical models in a high treewidth setting involves several challenges. In this paper, we focus on three: model mis-specification, the necessity of approximate inference, and computational complexity.. The main technical contribution of this paper is several methods for training based on the marginals predicted by a given approximate inference algorithm. These methods take into account model mis-specification and inference approximations. To combat computational complexity, we introduce "truncated" learning, where the inference algorithm only needs to be run for a fixed number of iterations. Truncation can also be applied, somewhat heuristically, to the surrogate likelihood.. Among previous methods, we experimentally find the surrogate likelihood to outperform the pseudolikelihood or piecewise learning. By more closely reflecting the test criterion of Hamming loss, marginal-based loss functions perform still better, particularly on harder problems (Though the surrogate likelihood generally displays smaller train/test gaps.) Additionally marginalbased loss functions are more amenable to truncation, as the surrogate likelihood diverges with too few iterations. These experiments consider three different datasets with varying complexity. In all cases, we try to keep the features used relatively simple. This means some sacrifice in performance, relative to using sophisticated features tuned more carefully to the different problem domains. However, given that our goal here is to gauge the relative performance of the different algorithms, we use simple features for the sake of experimental transparency.. We compare marginal-based learning methods to the surrogate likelihood/EM, the pseudolikelihood and piecewise likelihood. These comparisons were chosen because, first, they are the most popular in the literature (Sec. 4). Second, the surrogate likelihood also requires marginal inference, meaning an "apples to apples" comparison using the same inference method. Third, these methods can all cope with hidden variables, which appear in our third dataset.. In each experiment, an "independent" model, trained using univariate features only with logistic loss was used to initialize others. The smoothed classification loss, because of more severe issues with local minima, was initialized using surrogate likelihood/EM.

O O O O O O O B O O O B I O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B O B O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B O O O O O O O O O O O B O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B O O O O O O O O O O B I O O O O O O O O O O O O O O O O O O O O O B O O O O O O O O O O O O O O O O O O O O O O O O B O O O O O O O O O B O O O O O O O O O O O B O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B O O O O O O O O O B O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O


Understanding software artifact provenance In a well designed software system, units of related functionality are organized into modules and classes, which are in turn arranged into inheritance trees, package hierarchies, components, libraries, frameworks, and services. The trade-offs between simplicity versus flexibility and power are carefully considered, and interfaces are designed that expose the key functional properties of a component while hiding much of the complexity of the implementation details. However, over time the design integrity of a well-engineered system tends to decay as new features are added, as new quality attributes are emphasized, and as old architectural knowledge is lost when experienced development personnel shift to new jobs. Consequently, as developers and as users we often find ourselves looking at a piece of functionality or other design artifact and wondering, "Why is this here?" That is, we would like to examine the provenance of an artifact to understand its history and why it is where it is within the current design of the system.In this brief paper, we sketch some of the dimensions of the broad problem of extracting and reasoning about the provenance of software development artifacts. As a motivating example, we also describe some recent related work that uses hashing to quickly and accurately identify version information of embedded Java libraries.Keywords: Software artifact provenance, software analytics, code cloning Paul, it is easy to be impressed by your body of work at a distance. There are so many important and well-cited papers over many years, and the tools and techniques you and your group have contributed have had concrete and demonstrable impact on the research community. But when I spent my sabbatical at CWI, I learned an awful lot from you about running a research group, and getting the best out of talented people. You make it seem so easy and effortless, although I know it is neither. Your management style is low key and encouraging, yet the yield is so high. Perhaps most importantly, I have seen how the young researchers you supervise -many of whom go on to careers in industry -come away with justifiable pride in their efforts, an understanding of exactly how their work fits into the grand scheme of things, and a strong belief in the value of research itself. Surely this is the right way to build an ongoing, vibrant, and collegial community of scientists, engineers, and practitioners. In art and antiques, the term "provenance" is used to denote a set of evidence as to the origin and history of an artifact. Sometimes, the evidence is direct and clear, consisting of chains of accepted documentation. For example, the origin and history of the Italian renaissance painting Diana and Actaeon is well documented historically [16] : it was painted by Titian in the late 1550s for the Spanish ambassador; it subsequently passed through a series of French, Belgian, and British owners until it was purchased in 2009 by a consortium of UK public trusts. Sometimes, however, the evidence is much less certain, and guesses must be made according to imperfect knowledge. For example, the painting La Bella Principessa is believed to have been executed by Leonardo da Vinci [19] ; this belief is based on a combination of incomplete historical documentation plus "best guess" analysis of the materials, presumed tools and processes, and artistic styles. The W3C model for web document provenance (diagram taken from [3] ); its entity-agent-activity metaphor also works well for other problem domains, including software development.. More recently, the term provenance has been used in new ways. In software security, for example, the provenance of an executable component determines how trusted it is and what its permissions are [8] . Data provenance in the sciences is important for reproducibility of experiments; scientists must be able to tell which parts of which data set were generated at what time, by whom, using what tools, and which settings [12] . And the W3C has recently published a specification for web-based documents that authors can use to mark up their web pages with meta-data about the provenance of web resources (Fig.1) .. Increasingly, the term provenance is being used within the context of software development. Developers, managers, QA team members, and other stakeholders often wish to understand how and why a feature, component, chunk of code, test suite, or other development artifact came to be where it is. For example, when a manager finds a section of code that is involved in an unusually large number of problems, he may wish to find out how old the code in question is, which developers have been working on it recently, which change sets it has been involved in, and which features, quality attributes, and bug fixes it implements. When a IP lawyer is concerned about a claim of open source licensing violations within a closed source system, she may wish to be able to track the design history of the code in question [4] . When a software architect is trying to understand the current design of a module within a software system, he may wish to be able to compare the change history against discussions in the developer mailing list archives [5] . Additionally, the burgeoning research areas of Mining Software Repositories [10] and Software Analytics [9] concern developing infrastructure for asking these kinds of questions by analyzing disparate kinds of artifacts, considering how best to model and link the knowledge together, and presenting a practical interface to allow stakeholders to explore the space.. In this brief paper, we attempt to sketch the emerging domain of software development provenance. We discuss some of the typical problems, and what they have in common. We consider a general approach to attacking these problems using the metaphor of Bertillonage, a 19 th century approach to forensic analysis. And finally, we describe an example of such an approach that was used to solve a software artifact provenance problem.

O B I I O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B I I B I B I O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B I O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B I I O


Automated mapping for reconfigurable single-electron transistor arrays Reducing power consumption has become one of the primary challenges in chip design, and therefore significant efforts are being devoted to find holistic solutions on power reduction from the device level up to the system level. Among a plethora of low power devices that are being explored, single-electron transistors (SETs) at room temperature are particularly attractive. Although prior work has proposed a binary decision diagrambased reconfigurable logic architecture using SETs, it lacks an automated synthesis tool for the device. Consequently, in this work, we develop a product-term-based approach that synthesizes a logic circuit by mapping all its product terms into the SET architecture. The experimental results show the effectiveness and efficiency of the proposed approach on a set of MCNC benchmarks. As technology scaling enables packing of billion transistors into a single chip, power consumption becomes one of the primary bottlenecks of continuously meeting Moore's law. At the system level, there has been a paradigm shift from frequency scaling of a monolithic processor to multiple slower computing nodes that communicate through a common network fabric [6] [12]. A tight power budget constraint is one of the primary reasons that causes this paradigm shift. Moreover, leakage power is becoming a dominant source of power consumption and several works have looked into mitigating this power wastage [5] [7] . * This work was supported in part by the National Science Council of Taiwan under grants NSC 99-2918-I-007-007, NSC 99-2628-E-007-096, and NSC 99-2220-E-007-003, and by the National Science Foundation of USA under grants 0829926, 0903432, 0916887, and 0643902. * Soumya Eachempati contributed to this work prior to joining Intel Corporation.. Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. To copy otherwise, to republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. On the device level, as the power-delay product reaches quantum limits, a plethora of new device concepts are being explored to exploit tunneling in semiconductor layers as the operation basis. These novel device structures use significantly low-drive current of the order of a few electrons. Numerous demonstrations of the room temperature operation of Single-Electron Transistors (SETs) have proved that these devices are very attractive as a possible way for extending Moore's law.. Majority of these ultra-low power emerging nanodevices suffer from low transconductance and degraded output resistance, making it essential to co-explore an emerging device design in conjunction with a non-CMOS logic architecture. To this end, a novel binary decision diagram (BDD)-based [1] logic architecture was proposed as a suitable candidate for implementing logic using ultra-low power nanodevices [4] . Then, the BDD of a combinational circuit is mapped onto a hexagonal nanowire network controlled by Schottky wrap gates [3] .. In the hexagonal network, a logic function is achieved by a passive path switching of messenger electrons that arrive at the root node through either the left arm ("0") or right arm ("1") depending on the control gate of the wrap gates. Each row of the hexagonal fabric is controlled by a single variable. Both the normal and the complement of the variable are supplied to a node of the BDD and are used to control the left and right edges as shown in Fig. 1(a) .. A BDD implementation can be mapped onto this fabric and the variables implementing the given function establish a path in this fabric from the root node to either a 1 terminal or a 0 terminal to realize the desired functionality. Fig. 1(b) shows an example of a 2-bit XOR. There is a current detector at the root associated to every output bit that measures the current (if any). Depending on the operating modes, active high or active low, the current flowing is interpreted as a logic one or a zero (In the active high mode, no current is a logic zero and presence of current is a logic one and vice-versa in the active low mode).. However, the realization of the BDD architecture in [4] is fixed and not amenable to functional reconfiguration. This is because the approach selectively etches all paths that do not lead to a 1 terminal and also customizes the edges of a hexagon to either be a conducting nanowire or have a wrapped gate. Consequently, this structure is not very regular and cannot be restructured to implement a different function due to the physical etching process involved in its realization. Furthermore, if any of the nanowire segments or the wrap gates is defective, the whole circuit becomes non-functional. This is a significant limitation considering that nanowires and few electron nanodevices have traditionally suffered from the variability and reliability issues.. To solve the problem, a reconfigurable version of SET using wrap gate tunable tunnel barriers was proposed [2] and the indepth device simulation to study the electrostatic properties was presented [8] . This device can operate in three distinct operation states: a) active b) open and c) short state based on the wrap gate bias voltages. Such programmability leads to immense flexibility in designing a circuit. The device simulation shows that this device can provide an order of magnitude lower energy-delay than CMOS device [8] .. However, the synthesis of a BDD using the device in [2] is manual rather than automated. The reason is that mapping a reduced ordered BDD (ROBDD) into a planar SET array could be very complicated, especially when the BDD has crossing edges, which is typical in minimized BDDs. In this work, we address this mapping problem and propose an automated mapping approach. Instead of mapping a BDD directly, the proposed approach first divides a BDD into a set of product terms that represent the paths leading to the 1 terminal in the BDD. Then, it sequentially maps these product terms. Since the mapping order of the product terms affects the mapping results, we propose four sorting heuristics to reduce area cost. Additionally, the automated mapping approach incorporates the granularity and fabric constraints that are imposed in order to decrease the number of metal wires used for programming the SET array and for supplying the input signals, respectively [2] .. We conduct experiments on a set of MCNC benchmarks [10] . The experimental results show that the proposed approach can complete mapping within 1 second for most of the benchmarks. The main contribution of this work is proposing an automated synthesis tool for the promising energy-efficient SET array architecture.. The rest of this paper is organized as follows: Section 2 uses an example to demonstrate the problem considered in this paper, and introduces some notations. Section 3 presents the proposed mapping approach. Section 4 discusses and addresses two mapping constraints. Finally, the experimental results and conclusion are presented in Sections 5 and 6. In this paper, we propose a product-term-based approach that can efficiently map a Boolean function into a SET array. It solves the problem of automatically mapping a BDD into a SET array that previous works suffer from. The proposed approach simplifies the mapping problem by transforming a BDD into a set of product terms, and then individually mapping these product terms. Additionally, four product term sorting heuristics are proposed to enrich the approach. The granularity and fabric constraints can also be handled by the proposed approach. The experimental results show its effectiveness and efficiency of mapping a set of MCNC benchmarks. Our automated mapping is a key enabler for using the promising BDD technology.

O O O O B I O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B I I O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O


Predictive thread-to-core assignment on a heterogeneous multi-core processor As multi-core processors are becoming common, vendors are starting to explore trade offs between the die size and the number of cores on a die, leading to heterogeneity among cores on a single chip. For efficient utilization of these processors, application threads must be assigned to cores such that the resource needs of a thread closely matches resource availability at the assigned core. Current methods of thread-to-core assignment often require an application's execution trace to determine its runtime properties. These traces are obtained by running the application on some representative input. A problem is that developing these representative input sets is time consuming, and requires expertise that the user of a general-purpose processor may not have. We propose an approach for automatic thread-to-core assignment for heterogeneous multicore processors to address this problem. The key insight behind our approach is simple -if two phases of a program are similar, then the data obtained by dynamic monitoring of one phase can be used to make scheduling decisions about other similar phases. The technical underpinnings of our approach include: a preliminary static analysis-based approach for determining similarity among program sections, and a thread-to-core assignment algorithm that utilizes the statically generated information as well as execution information obtained from monitoring a small fraction of the program to make scheduling decisions. The number of processor cores in a die is expected to continue to multiply in coming years making multi-core CPUs with large number of cores a commodity item [6] . The increasing demand Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. To copy otherwise, to republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. for multi-core processors over single core general purpose processors can be attributed to the fact that no significant performance increase is obtained when the processor clock frequency is scaled [14] . Moreover, the processor is mostly idle since the instruction feed rate cannot match the speed of the high performance core. Multi-core processors solve this problem by placing multiple cores on a single die to boost performance and account for better area utilization.. A multi-core processor is heterogeneous when the cores on a single die differ in their characteristics e.g. cache-size, core-type (in-order or out-of-order), clock frequency, instruction issue width, etc [10] . Heterogeneous multi-core processors are seen as a more viable alternative by many due to better die area utilization, reduced heat dissipation, power consumption and often better performancepower ratio compared to their homogeneous counterparts [7] . They also help cater to a wider class of applications with varying levels of parallelism [9] .. There are two challenges to efficient utilization of heterogeneous multi-core processors. First, the amount of parallelism present in the workload must increase significantly. This can either be done by automatic extraction of thread-level parallelism [13] or by developing novel parallel programming language constructs [5] . Second, thread-to-core assignments techniques must be developed that match the resource needs of a thread closely with the resource availability, while maintaining fairness and optimizing overall throughput. This paper presents a technique to address the second issue.. The basic idea behind our technique is as follows. A program exhibits phase behavior [15] in that it goes through several phases of execution that show approximately similar runtime characteristics compared to other phases of execution. If we can approximately predict similarity among program phases statically, we can use this information to determine assignments of threads-to-core at a low runtime cost. In particular, by monitoring the execution of an initial phase in the program, we can predict the execution characteristic of the later phases of the program that resemble this phase. Statically predicted similarity and dynamically measured execution characteristics of the representive initial phase can then be used for selecting an appropriate thread-to-core assignment for the later phases in the program.. Based on this idea, our technique consists of a static analyser, which can be augmented into a compiler, and a dynamic monitoring and scheduling framework, which can become part of the operating system's scheduler. The purpose of the static analyser is to classify an application into a set of phases, and to group these phases into clusters such that each phase in the cluster is likely to show similar runtime behavior. The purpose of the dynamic monitoring and scheduling framework is to estimate the expected resource needs of a cluster by monitoring the execution of one representative The rest of this paper is organized as follows. Section 2 describes our approach for determining similar phases of execution and mapping phases to processor cores as well as our testing infrastructure in detail. Section 3 presents our planned evaluation framework. Section 4 compares and contrasts our approach with related work. Section 5 describes some potential benefits of our approach and Section 6 discusses future work and concludes. In this paper, we described a technique for thread-to-core assignment for a heterogeneous multi-core processor. Our technique statically determines the approximate phase behavior in a program. This phase behavior and the exhibited execution characteristics of a small set of representative phases is then exploited at runtime to determine likely profitable thread-to-core assignments for later phases of the program. By monitoring the execution of a small representative set, as opposed to simulating the application, our approach is likely to reduce the simulation overhead. With support in the operating system kernels and compilers, our technique can be used automatically without requiring any special input from the user. This may allow programs written by an end-user with no expertise to harness the capabilities of a heterogeneous multi-core processor.. Currently our approach determines similarity at the basic block level. As part of our future work we will group instructions at a more coarse level of granularity. One such approach could be to combine basic blocks into intervals and then form clusters from intervals rather than from basic blocks. This increased granularity will help to reduce the overhead associated with frequent core switching. Increasing this granularity will also give a better picture of the programs execution since the current method considers only certain basic blocks. The approach discussed in this paper is likely to provide two major benefits. Since the thread-core assignment policy plays a crucial role in deciding performance, Becchi et al. claim that dynamic thread assignment policies better make use of the benefits of a heterogeneous CMP [3] . According to this assignment policy, run-time behavior of threads is observed and thread switching is carried out accordingly. Another phase detection and optimization approach which dynamically optimizes the application based on the current execution profile is given by Nagpurkar et al. [12] . Our approach similarly uses dynamic results from the program's execution to change the thread assignment policy.. Kumar et al. introduce an approach for dynamically scheduling threads on heterogeneous multi-core architectures [10] . After a certain amount of execution, a trigger is generated which starts a sampling phase which modifies the current thread assignment. Our approach first groups the program instructions into sections statically. Our approach differs from their method in that we monitor the performance of these sections on the assigned core and then apply the performance results to other sections which are determined to be similar.. Sherwood et al. presented a dynamic profiling-based technique for similar program phase identification that performs application runs to obtain execution traces of applications [15] . This profile information is then used to identify appropriate simulation points within the application. Here, program execution is broken up into fixed length sections and basic block vector profiles are collected for every section. A similarity metric is used to group similar sections based on their basic block vector profiles. Our approach only uses static information therefore it does not require a dynamic profile.. Our procedure for determining similar basic blocks is also related to the approach used by Sherwood et al., where the clustering is done on the basis of similar intervals of execution [15] . In our approach, basic blocks are grouped into categories of similar basic blocks based on their machine instruction types (arithmetic, data transfer, control transfer, etc.), whereas in their approach Basic Block Vectors (BBVs) are grouped into clusters.. Another related work that strongly motivates the usage of heterogeneous multi-core architectures is by Tullsen et al. [8] . This paper shows that heterogeneous multi-core processors offer greater advantages in terms of performance and power when compared with any other class of Chip Multiprocessors (CMPs). The paper stresses the fact that applications achieved performance improvements of up to 40% when power and area constraints were tighter. It also gives us a deep insight into the design issues of a heterogeneous multi-core processor. The paper lays emphasis on tuning cores to a workload set which exhibit certain common execution characteristics rather than running all kinds of workloads. Our approach statically determines which sections of code exhibit similar characteristics in order to tune the thread assignment policy.

O B I O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B I O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B I O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B I O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B I I O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B I I O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B I O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B I O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B I O O O O O O O O O O O B I O O O O B I O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B I I O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O


Identifying potential adverse effects using the web: A new approach to medical hypothesis generation Medical message boards are online resources where users with a particular condition exchange information, some of which they might not otherwise share with medical providers. Many of these boards contain a large number of posts and contain patient opinions and experiences that would be potentially useful to clinicians and researchers. We present an approach that is able to collect a corpus of medical message board posts, deidentify the corpus, and extract information on potential adverse drug effects discussed by users. Using a corpus of posts to breast cancer message boards, we identified drug event pairs using co-occurrence statistics. We then compared the identified drug event pairs with adverse effects listed on the package labels of tamoxifen, anastrozole, exemestane, and letrozole. Of the pairs identified by our system, 75-80% were documented on the drug labels. Some of the undocumented pairs may represent previously unidentified adverse drug effects. Medical message boards are online resources where users with a particular condition exchange information, some of which they might not otherwise share with medical providers. Many of these boards contain many posts and contain patient opinions and experiences that would be potentially useful to clinicians and researchers. We present an approach that is able to collect a corpus of medical message board posts, de-identify the corpus, and extract information on potential adverse drug effects discussed by users. Using a corpus of posts to breast cancer message boards, we identified drug event pairs using co-occurrence statistics. We then compared the identified drug event pairs with adverse effects listed on the package labels of tamoxifen, anastrazole, exemestane, and letrozole. Of the pairs identified by our system, 75-80% were documented on the drug labels. Some pairs may represent previously unidentified adverse drug effects. It is well known that the lay public frequently uses online resources such as message boards to seek and exchange medical information [1] [2] [3] [4] [5] . Users of these resources ask questions and seek advice about topics that they may be hesitant to discuss with their health care providers. One such topic is concern about adverse effects experienced with some medications, especially those prescribed for serious conditions such as cancer, where patient anxiety may be heightened by the characteristics of the disease and the long-term exposure to potentially toxic drugs. Although adverse events should be reported through available channels, such as the Adverse Event Reporting System (AERS) of the U.S. Food and Drug Administration, many patients do not do so, perhaps because of ignorance of these channels, embarrassment, perceptions of poor provider availability, etc. Instead, they often use informal networks such as internet message boards to report and discuss adverse events. The burgeoning of medical message boards provides evidence of the frequency of discussions about health-related matters in society at large, and the boards in turn provide a fertile source of data for identifying and evaluating the advice, concerns, and opinions that are sought and provided by message board users. However, these data remain largely untapped by researchers in medical and healthcare domains.. While there are several studies evaluating discussions in message boards and chat rooms, these have used qualitative research methods. [6] [7] [8] [9] [10] To date, there are no reports in the medical or social sciences literature that apply text mining methods to these discussions to identify and analyze reports of adverse drug events. Reasons for this include the unstructured nature of message board text, the use of nonstandard abbreviations, a wide variety in the use of syntax and spelling, the temporal relationship between posts in a single thread, and references within messages to other threads.. Despite the difficulties associated with using message board text, researchers in many domains, particularly marketing, have successfully applied methods to extract information from this irregular medium. Glance, et al. [11] have developed a comprehensive system that crawls message boards and derives several different metrics about products including how much people discuss them and how much users seem to like those products. Feldman, et al. [12] have also published a system that extracts comparisons between different products and the attributes that they are compared on. Other systems have focused on different forms of web content such as product reviews in order to extract people's sentiment about certain products [13;14] or have relied on the pages produced by Google searches to extract the reputation of a product [15] .. Medical message boards have been examined to a much lesser degree. Malouf, Davidson, and Sherman [16] applied sentiment analysis to epilepsy blogs in order to extract patient preferences for different seizure disorder drugs. Although not focused on online user-generated content, pharmacovigilance researchers have also applied data mining methods in order to extract signals of possible adverse drug events from databases such as the AERS [17] [18] [19] . Electronic health records have also been examined to identify similar signals [20] as well as to generate more general biomedical hypotheses [21] . Though there is a history of data mining in the medical domain, it has yet to exploit the knowledge that can be derived from online user-generated content.. We present here methods that we used to identify such knowledge, specifically selfreported adverse events that may be associated with four hormonal medications that are commonly used in the treatment of breast cancer. We have designed a system to identify signals of potential adverse events that overcomes many of the difficulties associated with medical message boards and is able to extract useful information from them. Our system is able to generate a corpus of medical message board text by downloading the message pages, extracting the relevant fields from the pages, and programmatically removing identifying information from the documents. These de-identified documents are then searched for terms occurring in the controlled vocabulary in order to extract association rules that may signify meaningful relationships between these terms.. We demonstrated the efficacy of this system by extracting the significant drug-event association rules for four hormonal breast cancer treatment drugs from a corpus of breast cancer message board posts and compared this list to a list of all AEs that were documented on each drug label. Although our system's recall over these documented AE lists was relatively low (average of 35.1%), the precision was relatively high (average of 77.0%), suggesting that the terms in the significant association rules returned are not only correlated, but represent a real semantic relationship as well.. In addition, we identified that some of the undocumented AEs considered significant by our system signaled an AE that message board authors claimed to have experienced from the drug. Whether or not the AE was actually caused by the drug is unknown.. However, it may signal a true AE from that drug, and may be worth further investigation.. Even if the AE is not caused by the drug, it is useful to know what symptoms patients believe (correctly or not) are being caused by the drug.. In future work, we plan to extend the system to identify the speech act that was used for each drug-side effect mention and to use this system to identify undocumented adverse effects from dietary supplements. In order to address the unique difficulties posed by medical message boards, our system was structured as illustrated in Figure 1 . In step 1, the system downloaded message post pages from a set of message board sites and removed content unrelated to the posts from these pages. In step 2, the deidentification module removed personal identifiers (e.g., e-mail addresses, phone numbers, and usernames) from these posts. In Step 3 we developed the controlled vocabulary by scraping drug and side effect terms from various databases and websites using automated scripts in the Scrape Terms process. Afterwards, terms that were not indicative of a drug or event/symptom were removed by hand in the Curate process. In step 4, all terms in the controlled vocabulary were identified in our de-identified corpus and any pair of terms that co-occurred at a statistically significant rate was treated as a "finding".

O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B I I O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B I I O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B I O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B I O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B I I O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O


Interactive detection of network anomalies via coordinated multiple views This paper presents a new approach to intrusion detection that supports the identification and analysis of network anomalies using an interactive coordinated multiple views (CMV) mechanism. A CMV visualization consisting of a node-link diagram, scatterplot, and time histogram is described that allows interactive analysis from different perspectives, as some network anomalies can only be identified through joint features in the provided spaces. Spectral analysis methods are integrated to provide visual cues that allow identification of malicious nodes. An adjacency-based method is developed to generate the time histogram, which allows users to select time ranges in which suspicious activity occurs. Data from Sybil attacks in simulated wireless networks is used as the test bed for the system. The results and discussions demonstrate that intrusion detection can be achieved with a few iterations of CMV exploration. Quantitative results are collected on the accuracy of our approach and comparisons are made to single domain exploration and other high-dimensional projection methods. We believe that this approach can be extended to anomaly detection in general networks, particularly to Internet networks and social networks. Accurate and timely detection of network intrusions is a crucial component for many security and privacy applications. Some intrusions are notoriously difficult to detect due to their complexity and number of variations. Attackers can often easily modify their patterns and signatures to hide from existing detection approaches. Therefore, exploring features of network anomalies during attacks can fundamentally improve various intrusion detection methods.. Several single domain exploration methods for analysis of security data have been developed, as described in our related work in Section 5. Approaches such as these can often overcome the limits of algorithmic methods by integrating interactive exploration with visualizations. However, single domain approaches are not capable of exploring network anomalies across different domains. Such capabilities can be vital in identifying complex intrusions, especially attacks that can be identified only by comparing and correlating several different criteria. The system described in this paper combines node-link diagrams (referred to as the graph domain) with a derived spectral domain. The temporal domain, while crucial to the beginning of an analysis session, is discussed to a lesser extent. Each domain provides a different perspective and can manifest features of the data that the others cannot.. Specifically, this paper presents a CMV approach that facilitates the detection of network anomalies based on changes in network attributes when attacks occur. We concentrate on exploring network features in the graph and spectral domains. The visualization of the graph domain is shown via a node-link diagram, in which node clustering and connectivity can be explored. The visualization of the spectral space represents network nodes as points in a scatterplot, in which anomalous node distributions can be detected through the spectral analysis approaches described in Section 2.1. The temporal domain is visualized as a time histogram of node activity, which allows users to identify and select temporal ranges during which attacks are likely to have occurred. This CMV approach facilitates the exploration of network features using all of the temporal, spectral, and graph domains, thereby providing an effective network anomaly detection solution.. The system described in this paper has been designed to facilitate the detection of Sybil attacks in a time-varying setting. Detection is achieved via the linked visualizations which allows iterative exploration of network features. Because attacks cannot be consistently detected without closely selecting the attack time range, a time histogram is provided to guide users in choosing time ranges in which attacks are likely to have occurred. Several interaction techniques are provided that are designed specifically for facilitating the detection of network anomalies, particularly through exploring subgraphs and examining features of interest in both the graph and spectral spaces. An application of the described approach is demonstrated by detecting Sybil attacks in simulated wireless networks. Neighbor relationships are collected among the wireless nodes during a selected time period and the accumulative results are converted into an adjacency matrix. Then spectral and network graph based analysis techniques are applied to the matrix to create several dimensions that are used in the visualizations. Both case studies and quantitative results are presented to evaluate the effectiveness of the described approach. The CMV exploration approach is also compared to single domain exploration and other high-dimensional projection methods.. The main contribution of this paper is a CMV exploration approach that facilitates detection of network anomalies based on feature inspection in spectral, graph, and temporal domains. The described system provides suitable visualizations of the graph, spectral, and temporal spaces and interactive exploration mechanisms necessary for detecting anomalies and identifying malicious nodes. Spectral analysis metrics are incorporated into the intrusion detection procedures and visualization, particularly the spectral nonrandomness measurement. These metrics are shown to be useful in the intrusion detection process.. The remainder of this paper is organized as follows. In Section 2 we introduce the background of spectral analysis and Sybil attacks. Section 3 presents the CMV exploration approach, including the design of the graph, spectral, and temporal spaces as well as CMV interaction mechanisms. Section 4 describes the experimental results including case studies and quantitative data. Comparative results are also presented between the described approach and other high-dimensional projection and single domain detection methods. We review related work on spectral analysis, Sybil attack detection, and interactive visualization techniques in Section 5. Finally, we conclude and discuss future work in Section 6. This paper presents a CMV approach that facilitates the detection of Sybil attacks of varying time durations in simulated wireless networks. The described system allows users to detect suspicious activity through the temporal space and analyze network anomalies via visual features on both graph space and spectral space, thus providing new exploration capabilities by integrating network features from different perspectives. We have designed CMV visualization with essential interactive exploration methods for studying the network features required to detect malicious activity. The given results and discussion indicate that our approach provides a suitable detection mechanism that has potential to be extended to general network security applications or social network analysis.. For future work, we first plan to test the described system with network flow data. We are also interested in utilizing existing spectral analysis approaches to explore other network features that can be affected during attacks. Furthermore, we plan to test our prototype system with other types of attacks in wireless networks with the goal of achieving a generic intrusion detection visualization system for wireless networks. While there are several different mechanisms that can be used to calculate the primary components of a matrix, we choose the spectral approach over other schemes because of its simplicity and consistency in visual representation. For example, the multi-dimensional scaling (MDS) mechanism [25] can reconstruct the relative positions of the nodes based on their neighbor relationships. However, the reconstructed result can rotate freely before the positions of several anchor nodes are determined. To better justify our decision, we compare the spectral analysis results with the results of principal component analysis (PCA) [28] and MDS. In Figure 10 , we can see in all three schemes the attackers are outliers. However in the spectral space, the malicious nodes are always at the upper-right corner in the space, since they have large non-randomness values. Therefore, users may consistently focus their attention on these regions during the interactive detection process and disregard entities below the decision line in the spectral space. In contrast, PCA and MDS produce an inconsistent positioning of clusters, so users must explore all the different clusters to find malicious nodes.. Performance for the described system can be discussed in terms of visualization and spectral scalability. Since the most detailed analyses are performed in the scatterplot and node-link diagrams, these are of particular interest in terms of performance.. The limitation of the node-link approach is that it can only visualize several hundred nodes effectively on a normal sized display. To address this limitation, the proposed system can easily make use of more effective space filling algorithms, or could implement an administrator-defined hierarchical schema based on the network being observed, along with the necessary interactions to handle hierarchical constructs. Scatterplots are also limited in terms of screen space. However, since users will usually filter out nodes classified as normal by the spectral analysis, this is only a problem if the number of outliers is in the thousands when the user has a normal sized display.. Our detection solution and case studies have demonstrated that Sybil attacks cannot be successfully detected with a high degree of certainty by using the graph space or spectral space visualizations alone. However, by facilitating the detection of attack features in the graph, spectral, and temporal domain, users may isolate malicious nodes in a timely and accurate manner. Interactive detection of intrusion attacks is a popular topic in security visualization. For clarity, we only review the most relevant work on spectral approaches for analyzing network properties, Sybil attack detection methods, and interactive networking detection and CMV exploration methods.

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