An ILP formulation and genetic algorithm for the Maximum Degree-Bounded Connected Subgraph problem A general instance of a Degree-Constrained Subgraph problem may be found in an edgeweighted or vertex-weighted graph G whereas the objective is to find an optimal weighted subgraph, subject to certain degree constraints on the vertices of the subgraph. This class of combinatorial problems has been extensively studied due to its numerous applications in network design. If the input graph is bipartite, these problems are equivalent to classical transportation and assignment problems in operational research. This paper is an illustration of a research of the NP-hard Maximum Degree-Bounded Connected Subgraph problem (MDBCS). It is a classical NP-complete problem. Moreover this paper offers a first integer linear programming formulation of the (MDBCS), and a formal proof that it is correct. A genetic algorithm for obtaining the optimal solution of (MDBCS) has also been provided. The proposed solution comprises a genetic algorithm (GA) that uses binary representation, fine-grained tournament selection, one-point crossover, simple mutation with frozen genes and caching technique. In this paper the NP-hard problem, as well as the Maximum Degree-Bounded Connected Subgraph (MDBCS), (listed in [1] ), has been studied whereby an ILP model for solving this (MDBCS) problem is demonstrated.. In complexity theory, NP denotes the set of all (decision) problems solvable by a non-deterministic polynomial time algorithm. P denotes the set of all (decision) problems solvable by a deterministic polynomial time algorithm. NP problems are ''hard'' in the sense they are not currently solvable in deterministic polynomial time. It is an open question whether. Throughout this paper the graph G is supposed to be simple, i.e. to be a finite undirected graph without loops or multiple edges.. To start with some definitions that will need further elaboration are provided.. The graph G is a pair (V , E), where V is a set of vertices and E a set of edges. If G is a directed graph (digraph) then each edge is an ordered pair (u, v) ∈ E where u, v ∈ V . If G is an undirected graph then each edge is a two element set {u, v} ∈ E where u, v ∈ V .. Or, if the graph G is a pair (V , E), where V is a set of vertices, and E is a set of edges between the vertices E ⊆ {(u, v)|u, v ∈ V }, then G is a directed graph. If a graph does not allow self-loops, adjacency is irreflexive, that is E ⊆ {(u, v)|u, v ∈ V ∧ u = v}.. Two vertices of a graph are adjacent if they are joined by an edge. Vertex v is adjacent to u if and only if (u, v) ∈ E. In an undirected graph where the edge is {u, v}, and hence {v, u}, v is adjacent to u and u is adjacent to v. A path between two vertices is a sequence of edges that begins at one vertex and ends at another vertex i.e. v 1 , v 2 , . . . , v n is a path if {v i , v i+1 } ∈ E for i = 1, . . . , n − 1. A simple path passes through a vertex only once. A cycle is a path that begins and ends at the same vertex. A simple cycle is a cycle not passing through other vertices more than once.. A connected graph has a path between each pair of distinct vertices. A cycle in a directed graph is a path of length where at least 1 is such that v 1 = v n . This cycle is simple if the path is simple. For undirected graphs, the edges must be distinct.. An undirected graph is connected if there is a path from every vertex to every other vertex. We can label the edges of a graph with numeric values, the graph is called a weighted graph.. A graph G = (V , E ) is a subgraph of another graph G = (V , E) iff V ⊆ V , and E ⊆ E ∧ ((v 1 , v 2 ) ∈ E → v 1 , v 2 ∈ V ). In general, a subgraph does not need to have all possible edges. If a subgraph has every possible edge, it is an induced subgraph.. An edge-induced subgraph is a subset of the edges of a graph G together with any vertices that are their endpoints. A vertex-induced subgraph (sometimes simply called an ''induced subgraph'') is a subset of vertices of a graph G together with any edges whose endpoints are both in this subset.. A tree is a special kind of undirected graph. That is, a tree is a connected undirected graph without cycles.. In graph theory, a tree is a connected acyclic graph; unless stated otherwise, trees and graphs are undirected. There is no one-to-one correspondence between such trees and trees as data structure. We can take an arbitrary undirected tree, arbitrarily pick one of its vertices as a root, make all its edges directed by making them point away from the root nodeproducing an arborescence -and assign an order to all the nodes. The result corresponds to a tree data structure. Picking a different root or different ordering produces a different one.. All trees are graphs, but not all graphs are trees.. A spanning tree of a connected undirected graph G is a subgraph of G that contains all of G's vertices and sufficiently of its edges to form a tree. There may be several spanning trees for a given graph. If we have a connected undirected graph with cycles, and we remove edges until there are no cycles, then we obtain a spanning tree.. In the mathematical field of graph theory, a spanning tree T of a connected, undirected graph G is a tree composed of all vertices and some (or perhaps all) of the edges of G. Informally, a spanning tree of G is a selection of edges of G that form a tree spanning every vertex. That is, every vertex lies in a tree, but no cycles (or loops) are formed. On the other hand, every bridge of G must belong to T . A spanning tree of a connected graph G can also be defined as a maximal set of edges of G that contains no cycle, or as a minimal set of edges that connect all vertices. In certain fields of graph theory it is often useful to find a minimum spanning tree of a weighted graph. Other optimization problems on spanning trees have also been studied, including the maximum spanning tree, the minimum tree that spans at least k vertices, the minimum spanning tree with at most k edges per vertex (Degree-Constrained Spanning Tree), the spanning tree with the largest number of leaves (closely related to the smallest connected dominating set), the spanning tree with the fewest leaves (closely related to the Hamiltonian path problem), the minimum diameter spanning tree, and the minimum dilation spanning tree.. A spanning subgraph of a graph G = (V , E) is a subgraph with vertex set V . A spanning tree is a spanning subgraph that is a tree. Spanning trees have been found to be structures of paramount importance in both theoretical and practical problems [2] .. A single graph can have many different spanning trees. We can also assign a weight to each edge, which is a number representing how unfavorable it is, and use this to assign a weight to a spanning tree by computing the sum of weights of edges in that spanning tree. As a result spanning trees of a connected graph have been the focus for extensive attention in graph theoretic research.. In graph theory, a connected component of an undirected graph is a subgraph in which any two vertices are connected to each other by paths, and to which no more vertices or edges can be added while preserving its connectivity. That is, it is a maximal connected subgraph. Any notation or definition not explained here can be found in [3] .. Observations about graphs:. A connected undirected graph with n vertices must have at least n − 1 edges. A connected undirected graph with n vertices and exactly n − 1 edges cannot contain a cycle. A connected undirected graph that has n vertices and more than n − 1 edges must contain a cycle.. We consider the undirected graphs G = (V , E), where E is an edge set and V is the vertex set, and let |V | = n and |E| = m. Let G = (V , E) be a connected graph (although the graph does not have to be connected), with a weight function w : E → R + . For simplicity, we simply say that G is a w-weighted graph. For any subset E ⊆ E, we denote by G the subgraph of G induced by E ; and we denote by w(E ) the sum of the weights of the edges in E , that is w(E ) = e∈E w(e).. Observations about genetics algorithms: Genetic algorithms (GA) are a family of algorithms using some genetic principles that are present in nature, in order to solve certain mathematical problems [4] . These natural principles are: inheritance, crossing, mutation, survival of the best custom (or survival of the fittest), migration, etc. These algorithms can be used for solving various classes of problems, because they are fairly general in nature. In this case, they are used in the optimization problem -finding the optimal parameters of a system. The genetic algorithm is applied to the final set of individuals called population. Each individual in the population is represented by a series of characters (genetic code) and corresponds to a solution in the search space. Encoding can be binary or of some other higher cardinality alphabet. Encoding solutions is an important step of genetic algorithm because an inadequate choice of code can lead to bad results regardless of the other structures of the algorithm. Genetic algorithms are therefore robust and adaptive methods in addition to other fields of application that can be used for solving combinatorial optimization problems. The central concept in the description of genetic algorithms is a population of individuals, which is usually between 10 and 200. Each individual represents a possible solution in the search space of the problem (the space of all solutions). Each individual is presented as genetic code of a certain finite alphabet, with the most commonly used binary coding, where the genetic code consists of a series of bits.. Adaptation function (or fitness function) are assigned to each of the individuals and they are evaluating the quality of a given species, as well as individual solutions in the search space. The task of genetic algorithms is to provide a constant improving, from generation to generation, of absolute fitness of the whole population. It is realized by repeated application of genetic operators selection, cross and mutation, thus improving all the solutions of the particular problem. This paper deals with one of the known Degree-Constrained Subgraph problems, the Maximum Degree-Bounded Connected Subgraph problem. The paper also describes the ILP model and the genetic algorithm for solving the MDBCS problem.. Here, a first integer linear programming formulation for this problem, is presented, with formal proof of its correctness. In this paper a GA approach to solving the MDBCS has also been described. The problem is solved by a genetic algorithm which includes a binary representation with frozen genes, a limited number of different individuals with the same objective value and the caching GA technique. Experimental results are very encouraging and show the effectiveness of the GA approach.. This research can be extended in several ways. It would be desirable to investigate the exact methods based on linear relaxation, as Branch-and-Cut, or Brunch-and-Cut-and-Price. Beyond the aesthetic and theoretical appeal of Degree-Constrained Subgraph problems, the reason for such intensive study is rooted in their wide applicability in the areas of interconnection networks and routing algorithms, among others. For instance, given an interconnection network developed by an undirected graph, one may be interested in finding a small subset of nodes whit high degree of connectivity for each node.. The Maximum Degree-Bounded Connected Subgraph (MDBCS) takes as input a weight function w : E → R + and an integer d ≥ 2. Let us assume for a subset E ⊆ E and V ⊆ V such that the subgraph G = (V , E ) is connected, subgraph G has a maximum degree of d, and e⊆E w(e) is maximized. . Let E w denote a set of edges with the value of weight function, between an unordered pairs {u, v} of vertices. Therefore,. The optimal objective value in this example is 21.. The corresponding subgraph G is represented in this way: V = {11, 12} and E w = {({11, 12}, 21)}.. Example 2. Supposing function w : E → R + in the graph G is presented as follows: V = {1, 2, 3, 4, 5, . . . , 14, 15} and. The optimal objective value is 335. The corresponding subgraph G is done with: 3, 4, 6, 7, 10, 11, 12, 14, 15} and. This problem is one the classical NP-hard problems listed in [1] , but there have been no documented results so far, except for d = 2. For d = 2, the unweighted (MDBCS) problem corresponds to the Longest Path Problem. Indeed, given the input graph G (which can be assumed to be connected), let P and G be optimal solutions of the Longest Path and (MDBCS 2 ) in G respectively.. Note that the Minimum Subgraph of Minimum Degree Problem (MSMD) is closely related to (MDBCS) Problem. Indeed, (MSMD) corresponds exactly to the dual (unweighted) node-minimization version of (MDBCS) [5] .. Amidi et al. in [5] , have proven that the (MDBCS) problem is not in the Apx for any d ≥ 2. On the other hand, they offer an approximation algorithm for general unweighted graphs with the ratio min . The first algorithm uses an algorithm introduced in [6] , and based on the color-coding method.. The class Apx consists of all NP-hard optimization problems that can be approximated within a constant factor. The subclass PTAS (Polynomial Time Approximation Scheme) contains the problems that can be approximated in polynomial time within the ratio 1 + for any constant > 0. Assuming P = NP, there is a strict inclusion of PTAS in Apx (for instance, the Vertex Cover is in Apx \ PTAS), hence an Apx-hardness result for a problem implies the non-existence of a PTAS.. Without the connectivity constraint, the (MDBCS) problem is known as to be in P using matching techniques [7] . The following lemma shows that the (MDBCS) problem is NP-complete.

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Associating assertions with business processes and monitoring their execution Business processes that span organizational borders describe the interaction between multiple parties working towards a common objective. They also express business rules that govern the behavior of the process and account for expressing changes reflecting new business objectives and new market situations.In our previous work we developed a service request language and support framework that allow users to formulate their requests against standard business processes. In this paper we extend this approach by presenting a framework capable of automatically associating business rules with relevant processes involved in a user request. This framework plans and monitors the execution of the request against services underlying these processes. Definitions and classifications of business rules (named assertions in the paper) are given together with an assertion language for expressing them. The framework is able to handle the non-determinism typical for service-oriented computing environments and it is based on the interleaving of planning and execution. Web services technologies offer high-level specifications that provide functionality that supports and leverages web services and enables specifications for integrating automated business processes. Currently, there are two largely complementary initiatives for developing business process definition specifications which aim to define and manage business process activities and business interaction protocols comprising collaborating web services. The terms orchestration and choreography have been widely used to describe business interaction protocols comprising collaborating web services. Orchestration (as championed by BPEL) describes how web services can interact with each other at the message level, including the business logic and execution order of the interactions from the perspective and under control of a single endpoint. Orchestration refers to an executable business process that may result in a long-lived, transactional, multistep process model. Choreography (as championed by the Web Services Choreography Description Language) is typically associated with the public (globally visible) message exchanges, rules of interaction and agreements that occur between multiple business process endpoints, rather than a specific business process that is executed by a single party. Choreography is more collaborative in nature than orchestration. It is described from the perspectives of all parties (common view), and defines the complementary observable behavior between participants in business process collaboration. Currently, both orchestration and choreography initiatives are in their infancy and based on WSDL which is strongly emphasizes XML syntax and human-targeted descriptions.. In this paper we propose an approach based on interleaving planning and execution in the context of non-deterministic domains to deal with user expressed requests against standard business processes that result in initiating and executing business processes from diverse organizations. The execution of these business processes in the proposed framework is governed by assertions, which are business rules applied to processes. The framework we propose deals with non-deterministic domains, where it tries to satisfy a user request by taking into account how assertions that appear at different levels, e.g., business process, role, and provider level, are applied during business process execution. The framework focuses in particular on the application of business rules that are associated with choreographies. The ap-plication of choreography assertions usually results in activating only selected business process segments in different organizations. These are the business process segments that satisfy the choreography constraints and consequently can be involved in the result of a user request. In addition, the execution path of business processes is monitored to make certain that environmental conditions, i.e., web service supplied information, conform to the choreography assertions and user request requirements. The proposed framework deals with three kinds of assertions depending on their operational context and complexity: simple assertions, where simple reachability conditions are checked; preservation assertions, where maintenance of some condition needs to be satisfied throughout a path comprising a set of states traversed by the process during execution time; and business entity assertions, where the evolution sequence of a particular variable is monitored for correctness. In this paper we are not concerned with the effect that choreography assertions have on orchestration assertions (assertions that apply in the local context of an organization). We henceforth use the term assertion to mean choreography assertions.. The remainder of the paper is organized as follows. In Section 2, we recall the notion of the service-oriented business process and introduce various kinds of assertions. Section 3 presents an interleaving planning and execution framework for the monitoring of the execution of user requests and assertions against standardized business processes. Section 3.1 presents a formal domain definition. Section 3.2 introduces the service assertion language XSAL. A formulation of an example in terms of the formally defined domain is the offered in Section 3.3; while Section 3.4 provides algorithms for the working of the framework. Section 4 illustrates how the proposed framework processes the assertions on a traveling marketplace example. Related work is overviewed in Section 5. Concluding remarks and future work are discussed in Section 6. In our previous work we developed a service request language and support framework that allow users to formulate their requests against standard business processes [1, 13, 9] . In this paper we extend this approach by presenting a framework capable of automatically associating business rules with relevant processes involved in a user request. More specifically, we have introduced the assertion language XSAL whose main purpose is to express business rules in the form of assertions over business processes. This allows for consistency and conformance to organizational rules and policies when executing a business process. Additionally, it offers run-time control over its execution. We have classified assertions with respect to two process characteristics: its operational context and its ownership. As regards the operational context, we distinguish between simple, preservation and business entity assertions. As regards ownership, we distinguish between business process, role and provider level assertions. We have then introduced a framework for planning user requests that comply with assertions and monitoring their execution to recover from violating conditions. Specialized algorithms for planning, monitoring and executing requests and assertions have been proposed for this framework.. The proposed framework and the XSAL language open several interesting research issues. A particularly interesting open issue regards the performance of the framework, in particular, the way providers are selected from the service registry is crucial for the efficiency and effectiveness of the architecture. The current proposal does not address this issue, in other words, providers are chosen randomly. A better solution would be that of selecting providers based on provider-level assertions (for instance by comparing active assertions), on reputation and history of previous interactions with the provider, or optimizing some specific QoS parameter (e.g., cost of the service, average latency of the service, etc.).. The proposed framework plans for requests and assertions, then monitoring the execution of the plans. If there is one possible execution path that can satisfy the request and comply with its associated assertions, this will be found and executed, if not, a failure will be returned. In case that a request succeeds no information is currently provided regarding the quality of the execution. That is, if more possible execution paths complying with the assertions and the user request exist, then only one is guaranteed to be taken. An open issue concerns the comparison of potential solutions (execution trajectories) against optimality metrics, e.g., the shortest plan, the cheapest, the fastest or any other optimality criteria. In the web services literature there are several approaches dealing with the monitoring of the assertions over serviceenabled business processes. The WS-Policy framework [18] provides a general purpose model for describing a broad range of service requirements, preferences, and capabilities. Typically, it is used when the provider describes the set of conditions the requester should satisfy before invoking the service. RuleML [5] is a powerful technique for expressing business rules over semantically annotated service. On the negative side is the lack of any support for run-time monitoring of the business rules.. With respect to web services and planning techniques a review of web service composition techniques is presented in [17] and it is argued that planning techniques can be of help in tackling the problem of web service composition. Temporally extended goals, i.e., goals expressing not only desired states to achieve but also conditions on how these are to be reached, are on expressive way of defining complex business goals [13, 9, 15] . Various authors have emphasized the importance of planning for web services [8, 10, 11] . In particular, Knoblock et al. [8] use a form of template planning based on hierarchical task networks and constraint satisfaction, in [10] regression planning is used, while in [11] the Golog planner is used to automatically compose semantically described services. Various authors use planners over service description in DAML-S [16, 17] . Feasibility of HTN planning algorithms was shown in [19] . Finite-state machine framework for automatic composition was introduced in [2] . Service orchestration based on object-oriented data models are presented in [4] . In [12] service composition rules are used for governing the business process construction.

O O O O O O B O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B O O O O O O O O O O O B O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O


Optimization of high-performance superscalar architectures for energy efficiency In recent years reducing power has become a critical design goal for high-performance microprocessors. This work attempts to bring the power issue to the earliestphase of high-performance microprocessor development. We propose a methodology for poweroptimization at the micro-architectural level. First, major targets for power reduction are identiJied within superscalar microarchitecture, then an optimization of a superscalar micro-architecture is performed that generates a set of energ?l-eficient configurations forming a convex hull in the power-performance space. The energv-eficient families are then compared to find configurations that dissipate the lowest power given a perjormance target, 01; conversely. deliver the highest performance given a power budget. Application of the developed methodology to a superscalar microarchitecture shows that at the architectural level there is a potential for reducing power up to 50%, given a performance requirement, and for up to 15% performance improvement, given a power budget. Until heat removal from a workstation micro-chip became a major issue, high performance microprocessors remained free of power conservation requirements. As a result, microprocessor architecture tradeoff decisions have traditionally been based on costperformance analysis. Such features as wide out-of-order issue, speculation, register renaming, multiple branch prediction, multilevel caches, memory disambiguation, etc. have become standard, and little work has been done so far to improve the energy efficiency of structures providing these architectural features.. This work attempts to bring the power issue to the earliest phase of high-performance microprocessor development, where there is still a significant potential for power reduction.. Since performance is the main factor that sells in this high-end processor market, solutions compromising performance, such as those used in IOW power embedded microprocessors, are not an option. It is the goal of this paper to explore architectural level solutions to the power problems in high-performance superscalar microprocessors that achieve a power reduction without compromising performance.. The organization of the paper is as follows: Sections 1 analyses the critical design points of a superscalar microarchitecture and discusses energy models. Section 2 applies the energy model to the superscalar architecture and describes the developed optimization procedure along with obtained results. Section 3 suggests an architectural solution to the power growth problem and evaluates the potential of the proposed technique. Section 4 summarizes the paper.. *This work was supported in part by the National Science Foundation under Grant No.MlP-95-03682.. Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. To copy otherwise, to republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. ISLPED '00, Rapallo, Italy.. Copyright 2000 ACM 1-581 13-190-9/00/0007 ... $5.00. A methodology has been proposed for power-optimization at the micro-architecture level. Major targets for power reduction have been identified, then an energy-efficiency optimization of a superscalar micro-architecture has been performed to construct a family of energy-efJicient configurations. Analysis of centralized superscalar architecture has been performed, indicating the inherent energy inefficiency of the traditional approach. Multicluster architecture has been suggested as a possible solution to the problem. Comparison of energy-efficient families of centralized and multicluster micro-architectures shows that at the architectural level there is a potential for reducing power of the traditional design up to 50%, given a performance requirement, and for up to 15% performance improvement, given a power budget.

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Scalable subgraph mapping for acyclic computation accelerators Computer architects are constantly faced with the need to improve performance and increase the efficiency of computation in their designs. To this end, it is increasingly common to see acyclic computation accelerators appear in embedded processor designs. One major problem with adding accelerators to a design is that it is difficult to generate high-quality code utilizing them. Hand-written assembly code is typical, and if compiler support does exist, it is implemented using only greedy algorithms. In this work, we investigate more thorough techniques for compiling to processors with acyclic accelerators. Where as greedy solutions only explore one possible solution, the techniques presented in this paper explore the entire design space, when possible. Intelligent pruning methods are employed to ensure compilation is both tractable and scalable. Overall, our new compilation algorithms produce code that performs on average 10%, and up to 32% better than standard greedy methods. These algorithms also run in less than one second for more than 98% of basic blocks tested. Many portable devices must be capable of performing computationally demanding tasks, such as processing images, signals, video, or packet streams. However, current embedded processors are not capable of meeting the performance requirements within their tight power and cost constraints. Traditionally, applicationspecific integrated circuits (ASICs) are utilized to do the heavy lifting in system-on-chip designs, where critical portions of applications are mapped directly to hardware implementations. These Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. To copy otherwise, to republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. ASICs are nonprogrammable accelerators that can achieve extremely efficient solutions through hardware customization. ASICs often yield orders of magnitude wins over programmable solutions in cost, performance, and energy.. Lack of programmability is the central drawback associated with ASICs. The need to freeze a hardware implementation is a major obstacle, as the software is often a moving target due to changing standards, bug fixes, and the desire to incorporate more features. A middle-ground solution is to employ smaller, but compilable hardware accelerators, referred to as computation accelerators, within the context of a programmable processor. Such ASIPs (application specific instruction processors) utilize computation accelerators that are tightly integrated into a processor pipeline. The computation accelerators are essentially small ASICs that can atomically execute portions of an application's dataflow graph, termed computation subgraphs. The processor is augmented with a set of new instructions or a dynamic mapping mechanism to invoke the computation accelerators. Computation accelerators offer several potential advantages, including reduced latency for subgraph execution, increased execution bandwidth, improved utilization of pipeline resources, and reduced burden on the register file for storing temporary values. And unlike ASIC solutions, computation accelerators do not sacrifice the post-programmability of the system.. Many computation accelerator designs have been proposed by researchers. The most widely used in industry is the multiplyaccumulate, or MAC, unit. Many DSPs have specialized hardware for common computations in signal and image processing, such as dot product, sum of absolute differences, and compare-select. A number of generalized accelerator designs have also been proposed, such as 3-1 ALUs [22, 25] , closed-loop ALUs [27] , or ALU pipelines [5] . Larger accelerators can support bigger subgraphs and thus enhance the performance advantages. Examples that exemplify this approach include FPGA-style accelerators [14, 23, 26, 30] , configurable compute accelerators [8] , and programmable carry function units [31] . An alternative strategy is to synthesize specialized computation accelerators for a particular application [3, 4, 6, 9, 13, 17] . These approaches analyze an application to identify important computation subgraphs to implement in hardware. Hardware synthesis creates highly specialized accelerators to execute the selected subgraphs. Several commercial tool chains utilize this approach, including Tensilica Xtensa, ARC Architect, and ARM OptimoDE.. Compiler support to exploit computation accelerators has been an overlooked challenge, and comprises the focus of this paper. The compiler has two major tasks when targeting a computation accelerator. First, it must identify candidate subgraphs in the target application that are functionally executable on the accelerator. This is essentially a subgraph isomorphism problem. The second task is to select which candidate subgraphs to actually execute on the computation accelerator. Candidates often overlap, thus the compiler must select a subset to maximize performance gain. This task is essentially a graph covering problem.. Most prior solutions employ a greedy compiler approach for both subgraph identification and selection [5, 16] . With this approach, a seed operation is selected and a subgraph compatible with the accelerator is grown by iteratively including connected operations. As with all greedy approaches, this approach can achieve sub-optimal solutions in both identification and selection. Further, disjoint subgraphs cannot be identified. However, for small accelerators, such as 3-1 ALUs, this approach is sufficient due to the simple nature of compatible subgraphs. The greedy approach breaks down for larger accelerators where correspondingly larger subgraphs must be identified. As a result, others have proposed using exact methods for subgraph isomorphism and covering [20, 21, 24] . These methods grow exponentially in subgraph size, region size (the unit of operations analyzed by the compiler), or both. As a result, exact methods can suffer from excessive compilation times for moderate to large applications and hence may not be practically deployable.. In this paper, we propose an approach for compiler subgraph mapping that combines exact methods with a set of intelligent pruning techniques. Pruning ensures the proposed algorithms are scalable in both application and accelerator size to provide practical compilation times. The approach has three distinct phases. First, potential subgraphs are identified using bounded enumeration. Subgraph isomorphism is then used to remove candidates that are not compatible with the computation acceleration. Finally, unate covering is used to select subgraphs that will be executed on the accelerator.. This paper makes the following three contributions:. • It collects and describes state of the art algorithms for accelerator compilation.. • It presents new algorithms for identifying and mapping subgraphs optimally with intelligent pruning mechanisms.. • It evaluates these new algorithms in terms of both performance and compilation time across a variety of accelerator designs, and compares the results to a traditional greedy approach. In this work, we addressed the inefficiencies of traditional compiler algorithms used to identify candidate subgraphs for execution on computation accelerators. Several new algorithms were developed to find better candidates for both small and large accelerators. These algorithms comprised enumerating subgraphs in a dataflow graph, using subgraph isomorphism to prune invalid subgraphs, and using unate covering to select which valid subgraphs to execute on the targeted accelerators. Simulation results demonstrate that our proposed algorithms achieve, on average 10%, and as much as 32% more speedup than traditional greedy solutions.. This work also quantified the effect of register allocation on subgraph identification. On average, performing subgraph mapping prior to register allocation results in 8% more speedup. This result implies that performing dynamic subgraph identification in hardware or a virtual machine would reduce the effectiveness of mapping algorithms. In order to evaluate the proposed mapping algorithm, an experimental framework was built using the Trimaran research compiler and SimpleScalar ARM simulator. Trimaran was retargeted for the ARM instruction set and subgraphs to be accelerated were delineated in the binary. After compilation, the simulator recognized the subgraphs and modeled them as if an accelerator was present. SimpleScalar was configured to represent an ARM-926EJ [2] , a popular embedded core, with accelerators that took one cycle to execute.. Twenty three benchmarks from MediaBench and MiBench were used to evaluate the proposed mapping algorithms. Omitted benchmarks were due to issues in the compiler infrastructure, not limitations of the subgraph mapping algorithm. We tested three different algorithms: greedy enumeration -immediate selection (as described in Section 3.1), full enumeration -unate covering selection, or FEU (described in 3.2), and a hybrid technique full enumeration -greedy selection, or FEG.. Algorithm Comparison: Figure 5 shows the speedups attained when using the three proposed algorithms to target the 4 input / 2 output accelerator shown in Figure 1A . The figure illustrates that the FEU algorithm consistently outperforms greedy on nearly every benchmark. On average, 10% more speedup was achieved by using the FEU algorithm instead of greedy heuristics. Sha showed the largest difference between greedy and FEU, a 32% improvement. The primary reason for this is that full enumeration identified a considerable number of disconnected subgraphs in the critical loop, which the greedy algorithm was not capable of finding. Dijkstra large showed the least improvement when moving from greedy to FEU mapping. The important subgraphs in this benchmark only consist of 2 back-to-back instructions, thus the subgraphs are easy to identify regardless of enumeration algorithm. As would be expected, this shows that computation-bound applications with very large basic blocks benefit more from the FEU algorithm than applications with small basic blocks.. One surprising result illustrated in Figure 5 is that most applications did not benefit from unate covering selection (comparing FEG with FEU). On average, FEU performed only 1% better than FEG. The main reason for this is that the critical computation in most basic blocks was small enough that very few subgraphs were needed in the cover. If more subgraphs are used to cover the DFG (for example, when targeting a smaller accelerator), then greedy selection is more likely to get stuck in a local minima and perform worse. However, when targeting the large accelerator from Figure 1A , greedy selection is sufficient. In two instances, djpeg and rijndael, unate covering selection actually caused slight performance decreases. This is due to second-order effects, such as cache alignment, that are not modeled by the unate covering formulation.. Sensitivity to Targeted Accelerator: Figure 6 shows how much better FEU performs relative to greedy when varying the targeted accelerator. Bars greater than one imply FEU performed better than greedy and bars less than one imply greedy performed better than FEU. The rightmost bar for each benchmark represents the 4 input / 2 output accelerator used throughout this paper. The 3 input / 1 output accelerator consists of two back-to-back FUs, and is modeled after the accelerator used in [16] . The 4 input / 1 output accelerator has computation capabilities between the others, with 7 FUs and maximum dependence height of 3.. There are several interesting trends illustrated by this figure. First note that FEU outperforms greedy much more on the 4/2 configuration than on the 4/1 or the 3/1. This is because accelerators with only one output preclude disconnected subgraphs from being executed. If no disconnected subgraphs are allowed, then greedy can potentially find the same subgraphs as full enumeration. This definitely helps narrow the gap between the two algorithms. In general, larger accelerators with multiple inputs and outputs place more importance on high quality subgraph enumeration.. A second important trend in Figure 6 is that FEU outperforms greedy more in 3/1 than in 4/1. The reason for this is that the small number of FUs in 3/1 (only 2) made the number of subgraphs selected in the final cover relatively high, compared with 4/1 which has 7 FUs. Since more subgraphs are needed, more emphasis is placed on the covering algorithm, and unate covering helped quite a bit. The 4/1 accelerator used relatively few subgraphs, that were all discoverable via greedy enumeration, therefore FEU provided little benefit beyond the greedy algorithm. This shows that more thorough strategies, used in FEU, are more important whenever the search space is very large.. A last trend to note in Figure 6 is that in certain benchmarks, such as md5, greedy actually performed better than FEU. This is due to the partitioning used during full enumeration. Recall that in order to make full enumeration tractable, some very large blocks sometimes have to be partitioned into smaller graphs. Occasionally, this partitioning precludes full enumeration from finding important subgraphs which can be discovered by greedy methods. This problem is pronounced in accelerators with only one output, since full enumeration cannot make up ground on greedy by using disconnected subgraphs. Figure 6 motivates future work to develop faster enumeration algorithms and better partitioners to alleviate the problem in md5.. Effect of Register Allocation: Figure 7 depicts the result of applying the FEU mapping algorithm before and after register allocation. This is an important result because many researchers have proposed subgraph mapping in virtual machines or as a part of binary-to-binary translation. The drawback of subgraph mapping after register allocation is that spill code essentially breaks dataflow edges by placing values in memory. This limits the size of computation subgraphs that can be identified for acceleration. On the other hand, register allocation does introduce some additional computation (e.g., stack adjustments) that could potentially be accelerated, which is not available when mapping before allocation.. On average, we found that performing subgraph mapping prior to allocation produced results with 8% more speedup than postallocation mapping. In some benchmarks, like rawcaudio, the innermost loop was so small that there was no spill code, and so there was no difference in the results. In other benchmarks, such as 3des, the amount of spill code was so large that virtually none of the pre-allocation subgraphs were discoverable post-allocation. Only one benchmark, epic, performed better from post-allocation mapping. Figure 7 clearly shows that performing subgraph mapping pre-allocation in the compiler is much more effective than post compilation techniques, such as binary translation.

O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B O O O O O O O O B O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B I O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B O O O O O O O O O O O O O O O O O O O O O O O O O O O B O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B O O O O O


Evapotranspiration estimation based on the SEBAL model in the Nansi Lake Wetland of China As a major component of the water budget of a wetland, evaporation has proven difficult to measure evapotranspiration accurately. This paper developed a scheme to assess actual evapotranspiration (ETa) across a range of land uses in Nansi Lake Wetland, China, using a remote sensing technique and the Surface Energy Balance Algorithm for Land (SEBAL) model. The estimation of pixel-scaled ETa was conducted via SEBAL using Landsat-7 ETM+ images, DEM and meteorological data. Compared with the recorded pan evaporation, the estimated evapotranspiration calculated by SEBAL agreed well with the results derived from pan observations. Then, the spatial distribution characteristic of daily evapotranspiration was analyzed by referencing the land-use map of 2000. It was found that the open water body and creed swamp were at a high evapotranspiration rate, while the crop land, grassland and rural residential land took the second place, and the overflow land, town constructed land and bare soil were at the lowest evapotranspiration rate, which accorded with the evapotranspiration theory. The research demonstrates the considerable potential of SEBAL model for estimation of spatial ETa with little ground-based weather data over large areas such as wetlands.Crown More and more emphasis is being placed on the preservation of wetlands, due to wetlands providing a unique habitat and the wide variety of plant and animal species; some of them are being threatened or endangered. Many of the world's wetlands are threatened by changes in their water regimes with often adverse consequences for their biota and the provision of ecosystem services of importance to many people [1] . This poses the challenge of not only protecting water supplies dedicated for wetland maintenance, but also of managing those supplies for maximum wetland vitality. So it is widely recognized that wetland vitality is not merely a function of wetness, but also of water quality, timing and depths. Thus, it is valuable to estimate the actual evapotranspiration (ETa) of wetland areas. More accurate determination of ETa could lead to more informed decisions about the conservation, development and management of wetlands.. Evaporation is a major component of the water budget in a wetland, but it has proven difficult to measure accurately. So some researches have developed many methods to estimate evaporation. Meteorological or climatological methods are based on point data, which cannot provide a good estimation of ET in large areas. Although the water balance method can

B O O O O B O O O B I B O O O O O O O O O O O O B O O O O O O B O O O O O O O O O B O O O O O O O O B I B O O O O O O O O O O O O O O B O O O O O O O O O B O O O O O O O O O O O O O O O O B O O B O O O O O O O O O O O O O O O O B O O O O O O O O O O O O O O O O O O O O O O O O B O O O O O O O O O O O O O O O O O O O O O O O O O O O O B O O O O O B O O O O O O O O B O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B O O O O O O O O O B O O O O O O O B O O O O O O O O O O O O O O O O O O O O O O O O B O O B O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O


A hybrid unsupervised approach for document clustering We propose a hybrid, unsupervised document clustering approach that combines a hierarchical clustering algorithm with Expectation Maximization. We developed several heuristics to automatically select a subset of the clusters generated by the first algorithm as the initial points of the second one. Furthermore, our initialization algorithm generates not only an initial model for the iterative refinement algorithm but also an estimate of the model dimension, thus eliminating another important element of human supervision. We have evaluated the proposed system on five real-world document collections. The results show that our approach generates clustering solutions of higher quality than both its individual components.General Terms: Algorithms Keywords: Unsupervised clustering, EM initializationThe work presented in this paper is motivated by research into text mining and classification from large, real-world document collections. As the amount of available data becomes virtually unlimited, manual or supervised mining approaches become prohibitively expensive due to the limited reading and processing speed of the human experts. For this reason, we concentrate our research only on unsupervised methods. From the larger field of text mining and classification, this paper focuses on document clustering. Clustering, loosely defined as the grouping of similar data items, is the keystone of data classification. Following our creed, we focus on unsupervised clustering techniques that do not require labeled data or human feedback.From the vast array of clustering methods, iterative refinement clustering techniques are extremely popular due to their good performance, relative simplicity, and good theoretical foundations. By and large the most popular iterative refinement clustering algorithm is Expectation MaxPermission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. To copy otherwise, to republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. imization (EM) [2] . EM iteratively: (a) assigns membership probabilities for all data items and all clusters, and (b) re-estimates its model parameters based on the new assignments.The EM class of clustering algorithms are not problem free. Like all clustering algorithms, they rely on outside sources to provide the expected number of clusters, k. Having the human domain expert provide this information is not feasible when dealing with large document collections containing new, potentially unknown data. Hence, we focus only on automated, unsupervised methods for the estimation of k. The most popular probabilistic method to determine the dimensions of a given model is the Bayes Information Criterion (BIC) [9] . From all possible model dimensions, BIC chooses the one that maximizes the model log likelihood function. Calinski and Harabasz [1] proposed maximizing the ratio of inter (or between) and intra (or within) cluster distances as a means for estimating k. This last method was empirically shown to be the most efficient [5] . However, unless the data is part of a certain family of distributions, all these methods are not consistent. A second problem that is specific to iterative refinement clustering algorithms is the choice of the initial model parameters. Being part of the hill-climbing family of algorithms, iterative refinement algorithms converge to local maxima, which may be far from the global maximum if the choice of the initial point is poor. De facto solutions in most implementations of iterative refinement clustering algorithms use random or user-chosen starting points [3, 7] . Comparative studies indicate that other, more complex, initialization methods show no improvement over random initialization [4] .The work presented in this paper addresses all previously mentioned issues that plague EM and in general iterative refinement clustering algorithms with the following advantages:1. It is an integrated method that detects both the number of clusters k and the initialization model for each identified category; and 2. It consistently outperforms its constituents individually: the hierarchical algorithm and EM with random initialization.The paper is organized as follows. Section 2 overviews the proposed method for the selection of the initial model for EM. Section 3 introduces several measures that indicate the quality of the initial points. These measures are the key of the initialization algorithm. In Section 4 we evaluate the performance of the initialization algorithm and the perfor-Research Track Poster This paper introduces a hybrid clustering approach that extracts the initial model for an EM algorithm from the dendrogram generated by a hierarchical clustering algorithm. The initial EM model is extracted in a two-step process.. First, a number of candidate models are generated by sorting the dendrogram clusters according to a battery of quality measures and extracting the top-ranked clusters for various collection coverages. Then, the candidate model that locally maximizes a global quality score is chosen as the initial model for the EM algorithm.. The first novelty of the proposed method is that only the "best" clusters produced by the hierarchical algorithm are selected as the initial model of the expectation maximization algorithm. The second novelty is that our initialization algorithm generates not only an initial model but also an estimate of the model dimension, thus eliminating another important element of human supervision.. An instance of our clustering algorithm has been empirically evaluated on five real-world document collections. The results show that our approach is always superior to both EM with random initialization and the hierarchical agglomerative algorithm. A comparison of our technique for estimating the model dimension with the Calinski and Harabasz method indicate that the latter prefers simpler models, while our approach tends to generate more complex models, which increases the number of categories recovered in the clustering solution. Underestimating the model dimension can be a serious drawback for a real-world system because it reduces the number of categories recovered in the clustering solution. Potentially important categories may simply be dispersed among existing clusters instead of getting a cluster of their own, which makes them virtually invisible to the human analyst that browses the generated clustering solution. We believe that Calinski's approach suffers more from this issue because the clustering models used cover all the collection documents, including ambiguous documents that minimize the distance between distinct (but close) categories. On the other hand, our method works only with documents that are part of the "best" clusters, i.e. dense clusters that are well separated from the rest of the collection. We have shown that this approach is beneficial for both the detection of the model dimension (see Section 4.4) and for the selection of an initial model for EM (see Section 4.3).. One question that remains unanswered is: what is the best performance we can expect from such an unsupervised system? To answer this question we inspected the quality of the clustering solutions generated from all the initial model candidates (for all collection coverages γ and for all quality measures). We found that the upper limits for purity ranged from 75% (in LATIMES and REUTERS) to 92% (in SMART), and the upper limits for entropy ranged from 10% (in REUTERS-Top10) to 40% (in LATIMES). These relatively high upper limits on the system performance indicate that the proposed quality measures generate initial clustering models of good quality. Furthermore, the performance of our unsupervised method is, on the average, in the top 14% of all candidate models' purities and top 21% of all entropies, which is a strong indication of the robustness of our approach. Although these results are certainly encouraging they indicate that the proposed method can be extended at least with a better performing selection component.. Lastly, Table 5 lists the quality measures and collection coverages γ selected by the unsupervised system. Table 5 indicates that, if execution time is an important concern, a practical optimization of the proposed method that uses only one quality measure (GW ) would still have acceptable qualitative performance.

O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B I O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B I O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O


Feedback-directed memory disambiguation through store distance analysis Feedback-directed optimization has developed into an increasingly important tool in designing optimizing compilers. Based upon profiling, memory distance analysis has shown much promise in predicting data locality and memory dependences, and has seen use in locality based optimizations and memory disambiguation. In this paper, we apply a form of memory distance, called store distance, to the problem of memory disambiguation in out-of-order issue processors. Store distance is defined as the number of store references between a load and the previous store accessing the same memory location. By generating a representative store distance for each load instruction, we can apply a compiler/micro-architecture cooperative scheme to direct run-time load speculation. Using store distance, the processor can, in most cases, accurately determine on which specific store instruction a load depends according to its store distance annotation. Our experiments show that the proposed store distance method performs much better than the previous distance based memory disambiguation scheme, and yields a performance very close to perfect memory disambiguation. The store distance based scheme also outperforms the store set technique with a relatively small predictor space and achieves performance comparable to that of a 16K-entry store set implementation for both floating point and integer programs. Modern superscalar processors allow instructions to execute out of program order to exploit more instruction level parallelism (ILP). Because load instructions usually appear on the program's critical execution paths, processors must schedule loads as early as possible. However, to ensure the correctness of program execution, a load should not be scheduled ahead of any preceding stores that access the same memory location as the load. Memory disambiguation detects these memory dependences in order to avoid memory order violations while speculating load instructions.. Previous work has employed numerous static-analysis and hardware techniques to disambiguate memory references to improve performance [5, 10, 11, 15, 16, 17] . While many hardware techniques achieve good performance, most require a large on-chip memory to record memory dependences. In contrast, static dependence analysis does not require the large on-chip memory, but can only effectively identify load/store dependences for regular array references in loop nests. In this paper, we explore a compiler/microarchitecture cooperative solution to the memory disambiguation problem for superscalar processors. We give a feedback-directed mechanism based upon memory distance analysis to assist the processor in determining the exact memory dependences at runtime. The proposed scheme does not require a large on-chip memory and is not limited to array-based codes.. Memory distance is defined as a dynamic quantifiable distance in terms of memory references between two accesses to the same memory location. Fang et al. [9] define memory distance to include reuse distance, access distance and value distance. The reuse distance of a memory reference is defined as the number of distinct memory locations accessed between two references to the same memory location. Both whole-program [7, 28] and instructionbased [8, 9, 13] reuse distances have been predicted accurately across all program inputs using a few profiling runs. Reuse distance analysis has shown much promise in locality-based optimizations. Access distance is the number of memory references between a load and its dependent store, while value distance is the access distance with the consideration that a load depends only on the first store in a sequence of stores writing to the same address with the same value. Fang et al. [9] propose a feedback-directed mechanism based upon access distance and value distance to determine whether or not to speculate a load.. In this paper, we apply a form of memory distance, called store distance [26] , to the problem of memory disambiguation in outof-order issue superscalar processors. Store distance is defined as the number of store instructions between a load and the previous store accessing the same memory location. Through profiling the program with one small input, we analyze the instruction-based store distance distribution and generate a representative store distance for each static load instruction. Then, a cost effective microarchitecture mechanism is developed for the processor to determine accurately on which specific store instruction a load depends according to its store distance annotation.. The proposed store distance based mechanism shows very good results across a set of SPEC CPU2000 benchmarks. Our experimental evaluations indicate that the store distance based method performs much better than the previous access distance based memory disambiguation scheme [9] , and yields performance very close to perfect memory disambiguation, which uses exact knowledge of memory dependences for each dynamic load instance. The store distance based scheme also outperforms the store set technique with a relatively small predictor space and achieves performance comparable to that of a 16K-entry store set implementation [5] for both floating point and integer programs. In both cases, store distance requires a negligible amount of chip space (16 bytes in our implementation) compared to the several thousand bytes of chip space used by store set.. We begin the rest of this paper with a review of related work and background in the field of memory distance analysis and memory disambiguation. Next, we describe our analysis techniques and algorithms for measuring and analyzing store distance. Then, we present the micro-architectural considerations of our work and our experimental evaluation of store distance based memory disambiguation. Finally, we present our conclusions and propose future work. In this paper, we have developed a novel compiler and microarchitecture cooperative mechanism for dynamic memory disambiguation in superscalar processors. Based upon store distance analysis, the compiler generates a representative store distance for each load instruction and passes this information through an instruction annotation to the micro-architecture. Guided by the store distance annotation, the processor can accurately identify the specific store instruction on which a load depends and make speculation decisions accordingly.. The store distance based mechanism shows very promising results across a set of SPEC CPU2000 benchmarks. Our experimental evaluations indicate that the store distance based method performs much better than the access distance based memory disambiguation scheme and yields a performance very close to perfect memory disambiguation. The store distance based scheme also outperforms the store set technique with a small predictor space and achieves a performance comparable to a 16K-entry store set implementation for both floating point and integer programs.. We are currently adding path information to our computation of memory distance to help disambiguate store distances on multiple paths. In the future, we plan to incorporate this analysis into our speculation scheme to enhance store distance based memory disambiguation. In this section, we report the results of our experiment on our benchmark suite. First, we report the store distance characteristics of SPEC CPU2000 benchmarks that we used in our experiment. Then, we report raw IPC data using a number of speculation schemes.

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