Transistor Sizing Issues And Tool For Multi-threshold Cmos Technology Multi-threshold CMOS is an increasingly popular circuit approach that enables high performance and low power operation. However, no methodologies have been developed to size the high V, sleep transistor in an intelligent manner that trades off area and performance. In fact, many attempts at sizing the sleep transistor without close consideration of input vector patterns or internal structures can lead to large overestimates or large underestimates in sleep transistor sizing. This paper describes some of the issues involved in sizing transistors for MTCMOS and also introduces a variable breakpoint switch level simulator that can rapidly calculate delay in MTCMOS circuits as functions of design variables such as Vdd, V,, and sleep transistor sizing.Power consumption in conventional CMOS circuits can be attributed to switching power, leakage power, and short circuit power. Switching power is usually the dominant term and is given by the well known formula: Clearly, to reduce this energy dissipated to charge and discharge load capacitances, the circuit designer's optimum choice is to scale the supply voltage down. However, in order to maintain performance, the threshold voltage should also be scaled down as well so that the gate drive, (Vgs -V,), remains large enough, since propagation delay in a CMOS gate can be approximated as:where a is for modeling short channel effects [ I ] [2]. By reducing Vdd, the switching power is reduced quadratically, but a reduction in V, causes an exponential increase in subthreshold leakage current. As one continues to scale down Vdd and V,, the increased leakage power can dominate the dynamic switching power [3].In many event driven applications, like a processor running an X-server, circuits spend most of their time in an idle state where no i "Permission to make digital/hard copy of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for protit or commercial advantage, the copyright notice, the title of the publication and its date appear, and notice is given that copying is by permission of ACM, Inc. To copy otherwise, to republish, to post on servers or to redistribute to lists, requires prior specitic permission and /or a fee " computation is being performed, so large subthreshold leakage becomes unacceptable. Multi-threshold CMOS was developed in order to reduce this leakage current during idle modes by providing a high threshold "gating" transistor in series with the low V, circuit transistors. In active mode, the high V, transistor is turned on, while in sleep mode it is turned off, providing a small subthreshold leakage current 141. For a purely combinational circuit, where state does not need to be preserved, only one type of high V, device is actually required. The NMOS is preferable because it has a lower on resistance and can be sized smaller than a corresponding PMOS sleep transistor. Many other alternatives such as dual gated SOI, substrate biasing, or switched source impedance (closely related to MTC-MOS) have recently been proposed to address the conflicting requirement of high performance during active periods and low leakage during idle times [5] [6] [7] 181. However, MTCMOS has emerged as one of the more practical solutions that can be easily implemented using minor modifications to current designs and technology. The MTCMOS process only requires an extra implant step to produce the high V, devices, and the circuit implementation can be based on existing CMOS designs. Recently, several large chips have been fabricated and tested including a I -V DSP chip for mobile phone applications [9].Correct sleep transistor sizing is a key parameter that affects the performance of MTCMOS circuits. If sized too large, then valuable silicon area would be wasted and switching energy overhead would be increased, but on the otherhand if sized too small, then the circuit would be too slow because of the increased resistance to ground. Although there has been much activity and development of MTCMOS circuits recently, little work has been done on methodologies for sizing the high Vt sleep transistors. One possible approach to estimate the transistor size is to sum the widths of internal low V, transistors, but this can produce unnecessarily large estimates for transistor sizes. Designers may also try to design for peak current spikes [4], but this too gives overly conservative estimates. Ideally, one could simulate circuits for varying sleep transis-409 Multi-threshold CMOS is becoming a very popular circuit technique for low power, high performance applications. Recently there has been a great number of MTCMOS implementations, but as this technology becomes more widestream, it will be important to develop some important sizing methodologies for the high V, sleep transistor. This paper described some of the issues presented in sizing MTCMOS circuits, and then proceeded to develop a simple MTCMOS delay model that was applied to a variable break-414 point switch level simulator that could very quickly simulate large numbers of input vectors. The key for this tool was to provide the circuit designer with initial delay information as a function of input vector, Vdd, V,, and sleep transistor sizing, so that the he/she may recognize input vector patterns that may be especially susceptible in MTCMOS circuits. After the design and simulation space is narrowed sufficiently, the designer could then use a more detailed simulator like SPICE to verify circuit details. Power consumption in conventional CMOS circuits can be attributed to switching power, leakage power, and short circuit power. Switching power is usually the dominant term and is given by the well known formula: 2 Pswitching = aCLVdd fclk where a is the activity factor, C, is the total load capacitance, v d d is the supply voltage, and fclk is the clock frequency.. Clearly, to reduce this energy dissipated to charge and discharge load capacitances, the circuit designer's optimum choice is to scale the supply voltage down. However, in order to maintain performance, the threshold voltage should also be scaled down as well so that the gate drive, (Vgs -V,), remains large enough, since propagation delay in a CMOS gate can be approximated as:. where a is for modeling short channel effects [ I ] [2] . By reducing Vdd, the switching power is reduced quadratically, but a reduction in V, causes an exponential increase in subthreshold leakage current. As one continues to scale down Vdd and V,, the increased leakage power can dominate the dynamic switching power [3] .. In many event driven applications, like a processor running an X-server, circuits spend most of their time in an idle state where no i "Permission to make digital/hard copy of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for protit or commercial advantage, the copyright notice, the title of the publication and its date appear, and notice is given that copying is by permission of ACM, Inc. To copy otherwise, to republish, to post on servers or to redistribute to lists, requires prior specitic permission and /or a fee " DAC 97, Anaheim, California (c) 1997 ACM 0-89791-920-3/97/06 ..$3.50 computation is being performed, so large subthreshold leakage becomes unacceptable. Multi-threshold CMOS was developed in order to reduce this leakage current during idle modes by providing a high threshold "gating" transistor in series with the low V, circuit transistors. In active mode, the high V, transistor is turned on, while in sleep mode it is turned off, providing a small subthreshold leakage current 141. For a purely combinational circuit, where state does not need to be preserved, only one type of high V, device is actually required. The NMOS is preferable because it has a lower on resistance and can be sized smaller than a corresponding PMOS sleep transistor. Many other alternatives such as dual gated SOI, substrate biasing, or switched source impedance (closely related to MTC-MOS) have recently been proposed to address the conflicting requirement of high performance during active periods and low leakage during idle times [5] [6] [7] 181. However, MTCMOS has emerged as one of the more practical solutions that can be easily implemented using minor modifications to current designs and technology. The MTCMOS process only requires an extra implant step to produce the high V, devices, and the circuit implementation can be based on existing CMOS designs. Recently, several large chips have been fabricated and tested including a I -V DSP chip for mobile phone applications [9] .

O O O O B O O O O O O O O O O O O O O O O O B I O O O O O O O O B O O O O O O O O O O O O O O O O O O O O O O O O O O O O B O O O O O O O O O O O O O O O O O O B O O O O O O O O O O O O O O O O O B O O O O O O O O O B O O O B O O O O O O O O O O O O O B O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B O O O O O O O O O O O O O O O O O O O O O O B O O O O O O O O O O O O O O O O O O O O O O O O O B O O O O O O O O O O O O O O O O B O O O O O O O O O O O O O O B I O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B O O O O O O O O O B O O O O O O O O O O O O O O O O O O B O O O O O O O O O O B O O O O O B O O O O O O O O O O O O O O B O O O O O O O O O O O O O B O O O O O O O O O B O O B O B O O O O O O O O O O O O O O O O O O O O O O O O B O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O


Optimal Per-Edge Processing Times in the Semi-Streaming Model We present semi-streaming algorithms for basic graph problems that have optimal per-edge processing times and therefore surpass all previous semi-streaming algorithms for these tasks. The semi-streaming model, which is appropriate when dealing with massive graphs, forbids random access to the input and restricts the memory to O(n · polylog n) bits.Particularly, the formerly best per-edge processing times for finding the connected components and a bipartition are O(α(n)), for determining k-vertex and k-edge connectivity O(k 2 n) and O(n·log n) respectively for any constant k and for computing a minimum spanning forest O(log n). All these time bounds we reduce to O(1).Every presented algorithm determines a solution asymptotically as fast as the best corresponding algorithm up to date in the classical RAM model, which therefore cannot convert the advantage of unlimited memory and random access into superior computing times for these problems. When facing computational tasks on massive graphs the postulate of the classical RAM model, that is, storing the whole input in memory allowing random access to it, is no longer adequate. In fact, information building up the graph may arrive at no specified order and the attempt of completely storing it exceeds common main memories. Regarding this Muthukrishnan [8] 2003 proposed the semi-streaming model as a more restrictive model of computation. According to this the edges of the input graph G appear at arbitrary order and the memory is limited to O(n · polylog n) bits, where n is the number of vertices in G. An important parameter of a semi-streaming algorithm is described by the per-edge processing time T , i.e., the time the algorithm needs to handle each single edge. This time determines at which frequency the edges may arrive. The second parameter of the semi-streaming model denotes the number P of passes the algorithm takes over the input stream. All considered algorithms in this paper use only one pass.. Despite the heavy restrictions in the semi-streaming model there are algorithms known solving basic graph problems. In [4] semi-streaming algorithms are given for computing the connected components and a bipartition of a graph as well as a minimum spanning tree of a weighted graph. There are approaches to determine the k-edge connectivity [5] and the k-vertex connectivity [5] , [13] of a graph for any constant k.. In this paper we present semi-streaming algorithms for computing the connected components and a bipartition of a graph, to calculate the kvertex and k-edge connectivity for any constant k and to find a minimum spanning forest MSF. All these algorithms have constant and therefore optimal per-edge processing times.. Section 2 gives the usual definitions, in Section 3 we discuss our definition of the per-edge processing time which is a slight refinement of previous definitions. We develop our semi-streaming algorithms in Section 4. In Section 5 we debate on how the obtained algorithms compete with the corresponding algorithms in the RAM model. A final conclusion is found in Section 6. We presented semi-streaming algorithms for computing the connected components, a bipartition, the k-vertex and k-edge connectivity for any constant k and an MSF of a given graph. The presented per-edge processing times T surpass former semi-streaming algorithms and are optimal because they are constant. All introduced semi-streaming algorithms are asymptotically as fast as the fastest corresponding algorithms in the RAM model. For connected components, bipartition and MSF we actually achieve the time bounds of the best possible RAM algorithms.. The main idea for our semi-streaming algorithms is quite simple: A sparse memorized subgraph is merged with buffered edges and while computing a sparse subgraph of the merged one the next edges are buffered. We believe this idea to be fruitful for other graph problems as well when tackling them without random access and within the memory constraints of the semistreaming model. In this section we compare the obtained semistreaming algorithms to algorithms determining the same properties in the classical RAM model allowing random access to all the edges of a graph without any memory constraints.. First note that the presented semi-streaming algorithms have optimal per-edge processing times, that is, no semi-streaming algorithm exists allowing asymptotically shorter times: Every single edge must be considered to determine a solution for the problems considered in this paper, so a time of Ω(1) per edge is a lower bound for these problems.. Let us now take a look at the presented semistreaming algorithms testing k-vertex and k-edge connectivity. For k-vertex connectivity with k being a constant the fastest algorithm in the RAM model to date is due to Gabow [7] which runs in O(kn 2 ). Gabow obtains this result even in graphs with multiple edges by preprocessing the input graph with the algorithm of Nagamochi and Ibaraki [9] in time O(m) producing a running time of O(kn 2 + m) on graphs and multigraphs. This asymptotically equals our computing time, which is not surprising since we use Gabow's algorithm as our subroutine. The same situation we find when looking at k-edge connectivity. Our achieved computing time of O(m + k 2 n log(n/k)) is asymptotically as fast as the fastest algorithm in the RAM model due to Gabow [6] which we use as a subroutine. So both our connectivity algorithms have a computing time that is asymptotically the same as the fastest known corresponding algorithms in the RAM model.. It is possible that there are faster but still unknown algorithms in the RAM model for k-vertex and k-edge connectivity which cannot be utilized in the semi-streaming model because they consume to much space. The converse is true for the problems of finding connected components, a bipartition and an MSF of a given graph. The presented semi-streaming algorithms have asymptotically the same computing time as the fastest possible algorithms in the RAM-model. That can easily be seen for connected components and bipartition: We obtain in each case a computing time of O(n + m) which is trivially a lower bound for any algorithm in the RAM model solving these problems. For computing an MSF we get a computing time of O(T * (m, n)), where T * (m, n) is the lower time bound for any RAM algorithm.. For the asymptotic time needed to determine a solution there is no difference for k-edge and kvertex connectivity between the currently fastest algorithms in the RAM model and the presented semi-streaming algorithms. Unless faster connectivity algorithms in the RAM model are developed there is no demand for a random access to the edges and for a memory exceeding O(n · polylog n) bits. For computing the connected components, a bipartition and an MSF such a demand will never emerge since the presented semi-streaming algorithms have optimal computing times. The RAM model cannot capitalize on its mighty potential of unlimited memory and random access to beat the computing times of the weaker semi-streaming model.. We close this section by indicating a tradeoff be-tween memory and time when computing an MSF in the semi-streaming model. If the memory constraint of the semi-streaming algorithm is reduced from O(n · polylog n) to O(n · log 2−ε n) bits, only s = o(n · log n) edges can be memorized. So the optimal MST algorithm we use as a subroutine needs a time of O(T * (s, n)). Provided that T * (s, n) = ω(s) we obtain a per-edge processing time of ω(1) and therefore a computing time of ω(m). Both bounds are significantly larger than the corresponding ones when O(n · polylog n) bits of memory are permitted. However, if it turns out that T * (m, n) = O(m) for any m, it suffices to store Θ(n) edges to obtain both optimal peredge and computing time in the semi-streaming model.

O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B I I O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B I I O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B I I O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O


Hybrid index maintenance for contiguous inverted lists Abstract Index maintenance strategies employed by dynamic text retrieval systems based on inverted files can be divided into two categories: merge-based and in-place update strategies. Within each category, individual update policies can be distinguished based on whether they store their on-disk posting lists in a contiguous or in a discontiguous fashion. Contiguous inverted lists, in general, lead to higher query performance, by minimizing the disk seek overhead at query time, while discontiguous inverted lists lead to higher update performance, requiring less effort during index maintenance operations. In this paper, we focus on retrieval systems with high query load, where the on-disk posting lists have to be stored in a contiguous fashion at all times. We discuss a combination of re-merge and in-place index update, called HYBRID IMMEDIATE MERGE. The method performs strictly better than the re-merge baseline policy used in our experiments, as it leads to the same query performance, but substantially better update performance. The actual time savings achievable depend on the size of the text collection being indexed; a larger collection results in greater savings. In our experiments, variations of HYBRID IMMEDIATE MERGE were able to reduce the total index update overhead by up to 73% compared to the re-merge baseline.This work extends upon the previous publications ''A hybrid approach to index maintenance in dynamic text retrieval systems'' (S. The fundamental data structure of most text search engines is the inverted index, also known as inverted file (Zobel and Moffat 2006 ). An inverted index consists of two principal components: the dictionary and the posting lists (also known as inverted lists). The dictionary provides a lookup interface that can be used to quickly locate the posting list for a given term. A term's posting list is a list of all its occurrences within the text collection for which the index has been created (each such occurrence is called a posting). A search engine processes incoming keyword queries by locating the query terms' posting lists and combining the information found in these lists, perhaps according to Boolean query constraints, or according to probabilistic retrieval methods, such as Okapi BM25 (Robertson et al. 1998 ).. The problem of constructing an inverted index from a given, static text collection has been studied extensively over the last two decades (cf. Moffat 1992; Moffat and Zobel 1994; Moffat and Bell 1995; Heinz and Zobel 2003) and is well understood. The dynamic case, however, where the search engine has to update an existing index, reacting to changes in the underlying text collection, has received some attention lately (cf. Cutting and Pedersen 1990; Tomasic et al. 1994; Shieh and Chung 2005; Lester et al. 2005 Lester et al. , 2006 , but is not yet fully understood.. Many applications, such as digital libraries, Internet news search engines, and file system search engines, have to deal with continually changing text collections and sometimes even have to meet real-time (or near-real-time) performance requirements. A news search engine, for instance, would lose much of its appeal to the users if it only updated its index once per week. To keep the users happy, the engine must react to changes in the text collection by updating its index data structures, and must do so in a timeefficient manner.. Different text collections exhibit different update patterns. A fully dynamic text collection, in general, allows the following three types of update operations:. • INSERT: a new document is added to the collection; • DELETE: an existing document is removed from the collection;. • MODIFY: an existing document is modified (e.g., some text is appended at the end).. A search engine maintaining an inverted index for such a dynamic text collection must update its internal index structures whenever it detects (or receives notification about) a change to the collection. Updating the index may involve adding new postings to the index, removing postings from the index, or a combination of these two kinds of operations.. Within the scope of this paper, we restrict ourselves to the case of incremental text collections, where new documents may be added to the collection, but existing documents are never deleted or modified. Index update strategies that deal with deletions and modifications can easily be combined with the methods proposed in this paper. Possible ways of extending the techniques described here to non-incremental text collections are discussed by Chiueh and Huang (1998) and Büttcher (2007) .. Our work is based on the assumption that the index maintained by the search engine is substantially larger than the available amount of main memory and therefore, at least partially, needs to be stored on disk. Index maintenance strategies for on-disk inverted files are fundamentally different from those for in-memory indices. In both cases, it is generally desirable to store each posting list in a contiguous fashion, increasing spatial locality and cache effectiveness of the query processing routines. However, the impact of non-contiguous posting lists on the search engine's query processing performance is far greater for on-disk indices than if the search engine stores all its data in main memory. With an in-memory index, a discontiguity in a query term's posting list usually results in a CPU cache miss, carrying a penalty of around 100 CPU cycles (comparable to accessing a few dozen in-memory postings in a sequential fashion). With an on-disk index, each discontiguity at query time requires a disk seek-an operation that is roughly as expensive as reading 100,000 contiguously stored postings from disk.. As a consequence of this dichotomy, our results are applicable to desktop search engines and small enterprise search solutions with scarce memory resources, but not necessarily to large-scale search engines (e.g., Web search engines) that are composed of hundreds or thousands of machines and that might be equipped with enough main memory to hold the entire index in memory at all times.. Despite the fundamental difference between hard disks and RAM, however, there is a close connection between incremental update strategies for in-memory and for on-disk inverted files. Virtually every on-disk index update strategy operates by accumulating index data for incoming documents in RAM, building an in-memory inverted index; whenever the size of the in-memory index exceeds a certain, predefined threshold (or, alternatively, after some period of inactivity), the entire in-memory index is transferred to disk and combined with the existing on-disk index data (cf. Cutting and Pedersen 1990; Lester et al. 2005 Lester et al. , 2006 . By following this approach, costly on-disk index updates are amortized over a larger number of postings and a larger number of inverted lists. Furthermore, because the in-memory index is immediately queriable by the search engine, it allows for real-time index updates.. Different index update policies usually only differ in the way in which they combine the in-memory index data with the existing on-disk index structures. The two traditional index update strategies are re-merge update and in-place update. The re-merge policy operates by sequentially reading the existing on-disk index and merging it with the in-memory index, thus creating a new on-disk index that includes the in-memory data and that supersedes the old index. In-place update strategies, in contrast, do not read the entire on-disk index when the indexing process runs out of memory. Instead, whenever a new on-disk inverted list is created, some amount of free space is pre-allocated at the end of the list. When transferring in-memory index data to disk, postings for a given term are appended at the end of the respective list. A term's list is relocated whenever there is insufficient space for such an append operation, with some amount of free space pre-allocated again at the end of the list's new on-disk location.. The necessity to store each on-disk posting list in a contiguous fashion, and to enforce this contiguity at all times, is the main limitation of traditional merge-based and in-place index maintenance algorithms. To overcome this limitation, Büttcher and Clarke (2005) and Lester et al. (2005) investigated indexing time versus query time trade-offs, showing how the search engine's index maintenance overhead can be reduced by allowing a small amount of fragmentation in the on-disk posting lists. At query time, this results in a slightly increased query processing cost, due to the greater number of disk seeks.. In this paper, we are not concerned with such trade-offs. Instead, we focus on the case where all on-disk posting lists have to be stored in contiguous form, so as to maximize query processing performance. We show that a combination (hybrid) of the two competing index update paradigms for contiguous inverted lists (re-merge, in-place) leads to better performance than each policy type alone. We also show that the search engine's index maintenance overhead can be reduced even further by moving away from the idea that the entire in-memory index needs to be transferred from memory to disk when the indexing process runs out of memory. The resulting technique, called partial flushing, allows the search engine to only transfer some posting lists to disk, instead of all of them. As two different on-disk posting lists may have a different update cost, when measured in an amortized fashion (i.e., per incoming posting or incoming byte of compressed postings data), partial flushing leads to better overall performance than treating all lists equally.. In the next section, we give a brief overview of existing work in the area of inverted index maintenance. Section 3 contains a description of our basic hybrid index maintenance strategy, called HYBRID IMMEDIATE MERGE with contiguous posting lists (HIM C ). This is followed by a discussion of partial flushing (Sect. 4). In Sect. 5, we present a theoretical complexity analysis of HYBRID IMMEDIATE MERGE, based on the assumption that terms in the text collection being indexed roughly follow a Zipfian distribution (Zipf 1949) . Section 6 presents the key results we obtained in our experiments with hybrid and non-hybrid index maintenance. It includes an experimental validation of the performance characteristics of hybrid index maintenance, derived theoretically in Sect. 5. We conclude the paper with a discussion of our findings and some directions for future work (Sect. 7). We have presented and analyzed HYBRID IMMEDIATE MERGE with contiguous posting lists (HIM C ), an index maintenance strategy to be used in dynamic text retrieval systems for incremental text collections. The method is a combination of the well-known REMERGE and INPLACE update policies for on-disk inverted files. Posting lists are divided into short lists and long lists. Short lists are updated according to the REMERGE policy, while long lists are updated in place. In contrast to previous approaches to hybrid index maintenance, our method is not based on heuristics, but takes into account the actual performance characteristics of the storage system (random access performance versus sequential read/write performance) when deciding whether a list should be updated in place or not.. Our experiments with two text collections of non-trivial size showed that HIM C can reduce the search engine's index update overhead by up to 56%, compared to REMERGE. A refined version of HIM C , called partial flushing, was able to achieve a reduction of 73%.. A theoretical performance analysis of HIM C , based on the assumption that the terms in the text collection being indexed roughly follow a Zipfian distribution, was able to predict the general performance of the method, and was also able to predict the relative performance of HIM C on different text collections with different term distributions. It did, however, fail to predict HIM C 's exact index maintenance complexity, measured by the number of bytes transferred to disk and the number of in-place list updates performed. We found that the reason for the discrepancy between theoretical performance and measured performance was the disagreement between Zipfian distribution and actual term Inf Retrieval (2008) 11:175-207 205 distribution. For both collections used in our experiments, the Zipfian distribution consistently underestimated the frequency of terms in the range 10 1 B rank B 10 5 (the Zipfian distribution was off by up to a factor 5 for one of the collections).. Unfortunately, this discrepancy is impossible to avoid, as a Zipfian distribution (after a log/log transformation) is always represented by a straight line in the rank/frequency plot. The text collections used in our experiments (and in fact all other collections that we looked at), however, exhibit a curved rank/frequency plot. Term distribution models that better reflect the actual term distribution in a given collection are known (e.g., Lavrenko 2001), but require more complicated parameter estimation procedures than the simple Zipf distribution with its single parameter a. Furthermore, we do not know yet whether those models can be used to arrive at an asymptotical performance prediction of the type derived in Sect. 5.. Despite this slightly unsatisfactory result, it is clear that HIM C constitutes a substantial improvement over the basic REMERGE policy. This was not only confirmed by our experimental performance figures, but also by a regression analysis which we conducted and which showed that HIM C with partial flushing reduces the overall disk complexity of the search engine's index maintenance routines from REMERGE's Hðn 2 Þ to between Hðn 1:6 Þ and Hðn 1:7 Þ; depending on the term distribution in the text collection. Unlike other index update strategies (e.g., geometric partitioning; Lester et al. 2005) , HIM C does not achieve this speedup by sacrificing its query performance. HIM C and REMERGE both store their on-disk posting lists in a contiguous fashion and therefore exhibit the same query performance. Thus, the method does not represent a trade-off, but is indeed superior to the REMERGE baseline.. In our evaluation of HIM C , we strictly limited ourselves to the case of incremental text collections, where new documents are added to the collection, but existing documents are never removed or modified. Of course, this is not a very realistic assumption. Fortunately, it is not very difficult to add support for document deletions to a maintenance policy designed for incremental updates, for example by defining a garbage collection policy that periodically sweeps the entire index whenever the relative number of garbage postings in the index exceeds a certain, predefined threshold (Büttcher 2007, ch. 6 ). In fact, such a garbage collection policy has more flexibility in combination with HIM C than with the non-hybrid REMERGE strategy, as it may be applied to individual lists instead of the entire index, perhaps even in a piggy-backing fashion, during query processing (Chiueh and Huang 1998) . At this point, we do not have any experimental evidence indicating the exact effect of document deletions and of HIM C 's greater garbage collection flexibility. We surmise, however, that HIM C 's performance advantage over REMERGE is slightly lower in the presence of deletions than for the strictly incremental case. We evaluated HYBRID IMMEDIATE MERGE with contiguous posting lists (HIM C ), with and without partial flushing, on two different computer systems and using two different text collections. The results are compared to the non-hybrid IMMEDIATE MERGE baseline policy. Our experiments are limited to the index maintenance performance of the individual methods and do not cover their query processing performance. However, because all methods covered in this paper store their on-disk posting lists in a contiguous manner, we strongly suspect that the difference between the individual methods would have been extremely small and would have been unlikely to provide any additional insight into the problem of updating an inverted index.

O B I O O O O O B I O O O O B I O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B I O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B I O O B I O O O O O O O O O B I O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B I O O O B I O O O O O O O O O O O O O O O O O O O O O O O O O O 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O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B I O O O O O O O O O O O O O O O O O O O O O O O O O O B I O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B I O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B I O O O O O O O O O B I O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B I O O O O O O O O O O O B I O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B I O O O O O O B I O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B I O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B I O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O 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GENERATION OF SHAPE FUNCTIONS FOR STRAIGHT BEAM ELEMENTS Straight beam finite elements with greater than two nodes are used for edge stiffening in plane stress analyses and elsewhere. It is often necessary to match the number of nodes on the edge stiffener to the number on a whole plane stress element side. Beam elements employ shape functions which are recognised to be level one Hermitian polynomials. An alternative to the commonly adopted method for determining these shape functions is given in this note, using a formula widely reported in mathematical texts which has hitherto not been applied to this task in the finite element literature. The procedure derives shape functions for beams entirely from the set of Lagrangian interpolating polynomials. Examples are given for the derivation of functions for a three and four-noded beam elements. Analysis of structures using the finite element method is well-established. Many formulations exist for complex elements but simple elements remain popular since they are usually well-tested and easy to implement into an analysis program. Two-dimensional plane stress analysis, for thin structures subject to in-plane loading, may employ continuum elements, such as the fifteen-node triangle, having a large number of nodes along a side . Where edge stiffening is required, beam elements can be connected to continua edge nodes. There is then a requirement for formulations of beam elements having more than two nodes.. Conventional two-dimensional beam elements have two degrees of freedom at each node: one lateral displacement and one rotation. Unless the structure is loaded entirely laterally, axial stiffness must also be incorporated, by an additional degree of freedom at each node. With this amendment, beam elements are usually referred to as frame elements. The axial effects are uncoupled for straight beams and the determination of suitable shape functions is straightforward [1] .. The author has recently contributed to the development of a complex threedimensional finite element model at the Department of Engineering Science, Oxford University to study the damage accruing to surface structures from adjacent tunnelling [2] . Modelling was also undertaken in two-dimensions (to validate the complex model) where tunnel linings were represented with simple beam elements. The procedure outlined in this note was used in the implementation of these beam elements into an existing in-house finite element code (OXFEM).. In this note we are concerned with the generation of the shape functions which interpolate the lateral displacements along beam elements having more than two nodes. Bernoulli-Euler beam theory is assumed where transverse shear deformation is zero. While most finite element texts describe the simple twonoded beam [1, 4] few explain how more complex elements may be formulated [3] . This work presents an alternative derivation of bending shape functions for simple beam elements, for implementation of many-noded straight beam elements within a finite element analysis code. While the elements described are simple the theory will be of interest to developers of other C 1 continuous elements such as rectangular plates.

O O B I O O O O O O B I O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B I O O O O O O O O O O O O O O O O O O O B I O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B I O B O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B O O O O O B I O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B I O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B I O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O


Toward a higher-level visual representation for content-based image retrieval Having effective methods to access the desired images is essential nowadays with the availability of a huge amount of digital images. The proposed approach is based on an analogy between content-based image retrieval and text retrieval. The aim of the approach is to build a meaningful mid-level representation of images to be used later on for matching between a query image and other images in the desired database. The approach is based firstly on constructing different visual words using local patch extraction and fusion of descriptors. Secondly, we introduce a new method using multilayer pLSA to eliminate the noisiest words generated by the vocabulary building process. Thirdly, a new spatial weighting scheme is introduced that consists of weighting visual words according to the probability of each visual word to belong to each of the n Gaussian. Finally, we construct visual phrases from groups of visual words that are involved in strong association rules. Experimental results show that our approach outperforms the results of traditional image retrieval techniques. Due to the explosive spread of digital devices, the amount of digital content grows rapidly. The increasing need for automatic processing, description, and structuring of large digital archives motivates to have an effective content-based image retrieval (CBIR) [29] . In typical CBIR systems, it is always important to select an appropriate representation for images. Indeed, the quality of the retrieval depends on the quality of the internal representation for the content of the visual documents [2] . Recently, many image retrieval systems have shown that the partbased representation for image retrieval [37] is much superior to traditional global features. Indeed, one single image feature computed over the entire image is not sufficient to represent important local characteristics of different objects within the image.. Nowadays, bag-of-visual-words [17, 28, 32] has drawn much attention. Analogous to document representation in terms of words in text domain, the bag-of-visual-words approach models an image as an unordered bag of visual words, which are formed by vector quantization of local region descriptors. This approach achieves good results in representing variable object appearances caused by changes in pose, scale and translation. Despite the success of the bag-of-visual-words approach in recent studies, the precision of image retrieval is still incomparable to its analogy in text domain, i.e. document retrieval, because of many important drawbacks.. Firstly, most of the local descriptors are based on the intensity or gradient information of images, so neither shape nor color information is used. In the proposed approach, in addition to the SURF descriptor that was proposed by Bay et al. [3] , we introduce a novel descriptor (Edge context) that is based on the distribution of edge points.. Secondly, since the bag-of-visual-words approach represents an image as a collection of local descriptors, ignoring their order within the image, the resulting model provides a rare amount of information about the spatial structure of the image. In this paper, we propose a new spatial weighting scheme that consists of weighting visual words according to the probability of each visual word to belong to one of the n Gaussian in the 5-dimensional color-spatial feature space.. Thirdly, the low discrimination power of visual words leads to low correlations between the image features and their semantics. In our work, we build a higher-level representation, namely visual phrase from groups of adjacent words using association rules extracted with the Apriori algorithm [1] . Having a higher-level representation, from mining the occurrence of groups of low-level features (visual words), enhances the image representation with more discriminative power since structural information is added.. The remainder of the article is structured as follows: Section 2 reviews related works to the proposed approach. In Section 3, we describe the method for constructing visual words from images. In Section 4, we describe the method for mining visual phrases from visual words to obtain the final image representation. In Section 5, we present an image similarity method based on visual words and visual phrases. We report the experimental results in Section 6, and we give a conclusion to this article in Section 7. We successfully drew out an analogy between the techniques in text retrieval and image retrieval by building visual words and phrases. Visual words were constructed by extracting features based on the fusion of descriptors. A new "spatial weighting" technique has been introduced, which enhances the basic 'bag of-visualwords' approach by using spatial relations. Finally, we devised the methods to construct visual phrases based on association rule technique. Our experimental studies showed that a combined use of words and phrases could perform better than using them separately. It also showed good performance compared to similar recent approaches.. In our future work, we will investigate the usage of such model on proposing computer vision solutions like human behavior analysis from video. We will work on further justification based on other datasets such as TRECVID and NUS-WIDE. This section describes the set of experiments we have performed to explore the performance of the proposed methodology. Firstly, we investigate the performance of the proposed approach and the average number of visual words on each class of images after filtering the noisy visual words. Secondly, we evaluate the effect of fusion Edge context descriptor with SURF. Thirdly, we compare the performance of the spatial weighting scheme with the traditional bag-of-visual-words. Fourthly, we evaluate the contribution between visual words and visual phrases. Finally, we compare our approach to Zheng et al. approach [38] .

O O O O O O B I I O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B I I O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B I O O O O O O O O O O O O O O O O B O O O O O O O O O O O O O O B I O O O O O O O B I O O O O O O O O O O O O O O O O O O O B I O O O B I O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B I I O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B I O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B I O O O O O B I O O O O O O O O O O O O O O O O O O O O O O O O O O O O B I O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B I O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B I O O O O O O O O O O O B I O B I O O O O O O O O O O O O O O O O O B I O B I O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B I O O B I O O O O O O O O O O O O O B I O O O O O O O O O O O O O O O O O O O O O O B I O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B I O O O O O O O O O B I O O O O O O O O O O O B O O O O O O O B I O O O O O O O O O O O B I O B I O O O O O O O O O O O O


The convergence of Euler-like method for the simultaneous inclusion of polynomial zeros Abstract-In this paper we give the convergence analysis of the Euler-like iterative method for the simultaneous inclusion of all simple real or complex zeros of a polynomial. The established initial conditions provide the safe convergence of the considered method and the fourth order of convergence. These conditions are computationally verifiable, which is of practical importance. A procedure for the choice of initial inclusion disks is also given. Iterative methods for solving polynomial equations, realized in complex interval arithmetic, produce resulting complex intervals (disks or rectangles) containing the zeros of a given polynomial. In this manner a control of rounding errors and information about upper error bounds of complex approximations to the zeros are provided (see [1] for more details). Moreover, in some practical problems of applied and industrial mathematics, algebraic polynomials with uncertain coefficients can appear. This kind of problems is effectively solved applying interval methods (c.f. [2] , [3] ).. The Euler-like method for the simultaneous inclusion of the zeros of a polynomial was derived and tested on numerical examples in the recent paper [4] , but without details on the convergence rate. The aim of this paper is to present a detailed analysis of the convergence order, initial conditions for the convergence and the choice of initial disks which provide the guaranteed convergence of the Euler-like method. The stated conditions for the safe convergence are computationally verifiable, which is of practical importance.. The development and convergence analysis of the proposed algorithms need the basic properties of the so-called circular complex arithmetic, introduced by Gargantini and Henrici [5] . A circular closed region (disk) Z := {z : |z − c| ≤ r} with center c := mid Z and radius r := rad Z we will denote by the parametric notation Z := {c; r}. If Z k := {c k ; r k } (k = 1, 2), then Z 1 ± Z 2 = {c 1 ± c 2 ; r 1 + r 2 }, Z 1 · Z 2 = {c 1 c 2 ; |c 1 |r 2 + |c 2 |r 1 + r 1 r 2 }, Z −1 = {c; r} −1 = {c; r} |c| 2 − r 2 (|c| > r, i.e. 0 / ∈ Z),. where the bar denotes the complex conjugate. Beside the exact inversion Z −1 of a disk, we also use the so-called centered inversion Z I defined by. 1. The square root of a disk {c; r} in the centered form, where c = |c|e iϕ and |c| > r, is defined as the union of two disks (see [6] ):. For the basic interval operations +, −, ·, : the inclusion property is valid, that is,. Moreover, if f is a rational function and F its complex circular extension, then. Particularly, we have. In this paper we will use the following obvious properties:. More details about circular arithmetic can be found in the book [7, Ch. 5] . Throughout this paper disks in the complex plane will be denoted by capital letters.. As in many papers on this subject, circular interval arithmetic is used in this paper too since it is more comfortable for calculations and manipulations. We note that the rectangular interval arithmetic can be also applied successfully; moreover, then the advantage of this type of interval arithmetic to incorporate rounding errors and reduce the interval result by using the intersection becomes evident.

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High performance annotation-aware JVM for Java cards ABSTRACT Smart cards have become ubiquitous platforms for personalized services [1] . For example, a smart card is used as a phone card, a health insurance card, identity cards, in GSM phones or an electronic wallet [2, 3] . A typical smart card consists of a microprocessor, ROM (Read Only Memory), EEPROM (Electrically Erasable Programmable Read Only Memory) and RAM (Random Access memory). The ROM contains the card operating system and other applications.. Although a smart card has benefits over magnetic-strip cards, it has certain limitations such as non-portability of applications, lack of flexibility to download applications into a smart card. Recently, Java Card has been proposed as a solution to these limitations. Java Card is based on a subset of the Java API plus some special-purpose card commands [4, 5] . The Java Card technology enables portability of applications, and provides a secure platform to store and execute multiple applications, called applets, 1 on a smart card [6] . Applets are small enough so that several of them can fit into a single card with small amount of memory. Further, it facilitates installation of applications after the card has been issued which provides card issuers with the ability to dynamically respond to their customer's changing needs. For example, if a customer decides to change the frequent flyer program associated with the card, the card issuer can make this change, without having to issue a new card. Java provides a security model that lets applets from multiple sources reside safely on the same card. This is important because an applet on a smart card may attempt to access data intended to be private only to some other applet. The Java Card platform can be implemented in either of the following two ways:. a) It can be implemented as an external Java Card tool. The tool loads, verifies and prepares Java classes for on-card execution.. (1) ldub [ PC + 2], TARGET ! Read next bytecode to be executed (2) ldub [PC +1], %o2 ! Read ILOAD index operand (3) sll %o2, 2, %o2 (4) neg %o2 (5) ld [LOCALS + %o2], %l3 ! Read local variable at index %o2 (6) st %l3 ! Save local variable on the stack (7) add TOP, -4, TOP ! Update stack pointer (8) sll TARGET, SDISP, TARGET ! Calculating address of next bytecode (9) jmp ORIGIN + TARGET (10) add PC, 2, PC ! Update PC, delay slot (11) ldub [ PC + 2], TARGET ! Read next bytecode to be executed (12) ldub [PC +1], %o2 ! Read ISTORE index operand (13) sll %o2, 2, %o2 (14) neg %o2 (15) ld [ TOP] , %l3 ! Load value from the stack (16) st %l3, [LOCALS + %o2] ! Store value in local variable at index %o2 (17) add TOP, 4, TOP ! Update stack pointer (18) sll TARGET, SDISP, TARGET ! Calculating address of next bytecode (19) jmp ORIGIN + TARGET (20) add PC, 2, PC ! Updating PC, delay slot Separate Translation: ILOAD followed by ISTORE (1) ldub [ PC + 4] , TARGET ! Read next bytecode to be executed (2) ldub [PC +1], %o2 ! Read ILOAD index operand (3) sll %o2, 2, %o2 (4) neg %o2 (5) ld [LOCALS + %o2], %l3 ! Read local variable at index %o2 (6) ldub [PC + 3] , %o2 ! Read ISTORE index operand (7) sll %o2, 2, %o2 (8) neg %o2 (9) st %l3, [LOCALS + %o2] ! Store value in local variable at index %o2 (10) sll TARGET, SDISP, TARGET ! Calculating address of next bytecode (11) jmp ORIGIN + TARGET (12) add PC, 4, PC ! Updating PC, delay slot (3) sll %o2, 2, %o2 (4) neg %o2 (5) ld [LOCALS + %o2], %l3 ! Read local variable at index %o2 (6) st %l3 ! Save local variable on the stack (7) add TOP, -4, TOP ! Update stack pointer (8) sll TARGET, SDISP, TARGET ! Calculating address of next bytecode (9) jmp ORIGIN + TARGET (10) add PC, 2, PC ! Update PC, delay slot (11) ldub [ PC + 2], TARGET ! Read next bytecode to be executed (12) ldub [PC +1], %o2 ! Read ISTORE index operand (13) sll %o2, 2, %o2 (14) neg %o2 (15) ld [ TOP] , %l3 ! Load value from the stack (16) st %l3, [LOCALS + %o2] ! Store value in local variable at index %o2 (17) add TOP, 4, TOP ! Update stack pointer (18) sll TARGET, SDISP, TARGET ! Calculating address of next bytecode (19) jmp ORIGIN + TARGET (20) add PC, 2, PC ! Updating PC, delay slot sll %o2, 2, %o2 (8) neg %o2 (9) st %l3, [LOCALS + %o2] ! Store value in local variable at index %o2 (10) sll TARGET, SDISP, TARGET ! Calculating address of next bytecode (11) jmp ORIGIN + TARGET (12) add PC, 4, PC ! Updating PC, delay slot Combined Translation: ILOAD followed by ISTORE Figure 1 : Traces of the translations of an ILOAD followed by an ISTORE operation. b) It can be implemented as an on-card Java Card VM based on Java bytecode Interpreter.. With the development of Java Cards, new application languages are being designed and put into use, for example, Java Card 2.x [7, 8] .. The above facilitates code reuse with the potability across different chip architectures. In addition, the object-oriented approach of Java Card 2.x provides flexibility in programming smart cards. The widespread use of networked devices has rendered the program and application data on such cards susceptible to external attacks. Thus it has increased the need for securing the data against such attacks [9, 10] . Securing the digital data mandates personal identification and non-repudiation. For the same, most cards have builtin support for cryptography. The need for higher security levels has led to the use of complex crypto keys (usually DES or RSA private keys). However, use of complex, computation-intensive security algorithms adversely affects the performance of the smart card due to its limited computation resources.. Most of the research in the context of the JVM has concentrated in high-end optimizations such as advanced garbage collection techniques, just-in-time (JIT) compilation, hotspot analysis and adaptive compilation techniques. However, Java programs running on low-end smart cards cannot afford the overhead (such as increase in class file size and additional compilation time) associated with such optimizations. The latter stems from the limited on-card memory which restricts the size of the VM code itself. In addition, support for multiple applications and cryptographic services demands high performance VM execution engine. The above necessitates the optimization of the JVM for Java cards.. In this paper we propose new methods for optimizing the performance of Java interpreters for Java cards with patterns of Java bytecode operations or SuperOperators. 2 For example, consider the two traces shown in Figure 1 which illustrate how combining bytecode operations into patterns can lead to optimized interpreted execution. The upper side of Figure 1 shows the execution trace of an ILOAD operation immediately followed by an ISTORE operation. A total of 20 instructions are executed. The trace in the bottom portion of Figure 1 shows the situation in which at the moment of translating the ILOAD operation it was known that such instruction was followed by an ISTORE operation. In this new trace, the dispatch cost for the ISTORE operation is eliminated (instructions 8, 9, 10 and 11 from the upper trace). Besides, the stack accesses and stack pointer updates in the translation of both operations are completely eliminated (instructions 6, 7 and 15 in the upper trace). The result produced by the ILOAD operation is kept in the machine register l3 and reused by the subsequent ISTORE bytecode, with no need to access the stack (instructions 5 and 9 in the lower trace). The combined translation of the two bytecodes executes 12 instructions, a 40% improvement over the separate translation.. The rest of the paper is organized as follows: In Section 2 we present a brief overview of program interpretation schemes. Next, in Section 3 we discuss our approach for generation of SOs. Static and dynamic customization of the interpreter is discussed in Sections 4 and 5 respectively. The SO annotation format is discussed in Section 6. The experimental framework and results are presented in Section 7. In Section 8 we discuss previous work. Finally, we conclude with directions for future research in Section 9. In this paper we presented an annotation-aware JVM for Java cards that optimizes interpreted execution of Java code using Java bytecode SOs. The most valuable SOs are identified ahead of time via profiling and information about SOs is conveyed to the runtime system via annotations. Annotation attributes in the class files mark the occurrences of valuable SOs, dispensing the expensive task of selecting SOs at runtime, without hindering class file portability. The low run-time overhead coupled with minimal memory requirements makes our annotation-based approach ideal for optimization of JVM for low-end embedded systems.. In order to achieve high performance, the SOs can be formed by OF patterns which cover more than 50% of the total bytecodes executed. Therefore, optimizations that target only the top SOs can substantially improve the interpreted execution performance. An average speedup of 18% is obtained using an interpreter customized with the top SOs formed by OF patterns. Greater speedups can be achieved by statically adding to the interpreter applicationspecific SOs formed by top BBs. Our results show performance improvement of (upto) 131% obtained using SOs formed from optimized BBs. As future work, we would like to extend our annotationbased approach for compression of Java bytecodes for Java cards. The breakthrough in the efficient implementation of virtual machine interpreters is the threaded code technique [23, 24, 25, 26] . The threaded interpreter still pays the cost of an instruction dispatch for each bytecode executed. If simple bytecodes are combined into bytecode sequences, the dispatch overhead is reduced. Optimizing interpreters with bytecode sequences has been tried in previous research. Proebsting's work on SuperOperators [27] introduces SOs as specialized instructions automatically inferred from repeated patterns in the tree-like intermediate representation produced by lcc compiler [28] . His bytecoded interpreter extended with SOs runs 2 to 3 times faster with the tested benchmarks. Ertl, Gregg et al. [29, 30] have combined the advantages of threaded code interpreter with the merging of single instructions into Superinstructions. By inspecting traces of a program execution, patterns of instructions of length 2, 3 and up to 4 are detected. In a later phase, the behavior of the original virtual machine operations and the patterns of instructions are defined using a special syntax in C. An automatic interpreter generator takes in this specification and outputs an interpreter in C that implements the described behaviors. Their work relies on a smart C compiler to remove redundant stack accesses, unnecessary stack pointer updates and bytecode dispatch instructions within patterns. Hundreds of patterns are incorporated to the interpreter code, substantially increasing the size of the interpreter. Up to 2 fold-speedups have been reported for the indirect interpretation of Java bytecodes.. Piumarta et al. propose a technique that eliminates the dispatch overhead within a basic block using selective inlining [31] . The code to be interpreted is first translated to threaded code and basic blocks are identified. A second pass dynamically generates macro opcodes representing the basic blocks and replaces threaded code opcodes with the macro opcodes. The implementation of each macro is a simple concatenation of the C-code implementations of the bytecodes that it replaces. The technique was applied to the Objective Caml bytecode interpreter and resulted in 50% average speedup, reaching twice as fast in some cases. Thibault et al. [32] proposes interpreter Specialization as a more generic solution for optimizing interpreters than Piumarta's. An interpreter specialized for a particular program is essentially a concatenation of the implementations of all the bytecodes in the program. This technique fully eliminates the bytecode dispatch cost resulting in 4-fold speedups.. Sun designed a stack operation folding mechanism for PicoJava I [33] and PicoJava II [34] architectures that converts many cycles of stack oriented instructions into an one-cycle register based instruction, which can be implemented with a few registers. This technique groups or folds contiguous operations that have true data dependency. For example, the bytecode sequence iload 1 iload 2 iadd istore 3 (two stack copy operations, an ALU operation and a local variable store operation) can be transformed into a single add R1, R2, R3 operation. Sun's folding technique is based on pattern matching with a very limited set of patterns. A special decode unit in the PicoJava processor converts the bytecode instructions into microoperations and looks for folding patterns up to 4 consecutive instructions long. If a pattern is identified, the decoder replaces the instructions belonging to the pattern with a simple micro-operation. Other stack operation folding techniques that enhance PicoJava's simple grouping rules have been proposed in literature [35, 36, 20] . Kim [37] has proposed a software approach to stack operation folding in which he creates a Smart Loader, a custom class loader that finds folding patterns at load-time by applying PicoJava-like grouping rules. With this approach, the JVM hardware can be simplified yet benefit from folding.. Static program analysis for identifying repetitive sequences of bytecodes for compression has been studied in [38, 39] . Casey et al. [40] proposed a Java instruction, called superinstruction, to reduce the number of instruction dispatches. However, their approach for selecting bytecode sequences is restricted to per-program basis. Donoghue and Power proposed an approach to (statically) select a generic set of superinstructions to be used across different programs [41] . In [42] , Ertl and Gregg proposed a method to exploit dynamic superinstructions in conjunction with stack caching [25] to minimize the interpreter dispatch overhead; in addition, they propose a shortest path search algorithm to determine an "optimal" sequence of state transitions and VM instructions. In [13] , Ogata et al. proposed a prefetching-based technique to minimize redundant memory accesses and the overhead of indirect branches. Gaganon and Hendren proposed a technique called preparation sequences employed for inlined-threading of Java interpreters in presence of dynamic class loading, lazy class initialization and multithreading [43] . Program interpretation is the process of emulating in software the basic tasks of fetching, decoding and executing instructions of a normal program execution, which are usually done by a microprocessor hardware. Therefore interpretation has inferior performance compared to direct program execution. An interpreter is essentially structured as an infinite loop that reads in a new instruction from an array of instructions pointed by a software program counter, decodes the instruction, transfers control to code parts that handle the instruction just decoded, updates the program counter to point to the next instruction in the stream and eventually returns to the same fetch-decode-execute cycle to translate the next instruction. The implementation of an interpreter loop in a high level language like C is shown in the upper part of Figure 2 , and is referred to as a switch-based or bytecoded interpreter.. There are two main sources of overhead in the interpreted execution of Java bytecode programs. We discuss the overheads by analyzing Figure 3 , which shows part of LaTTe's interpreter engine directly written in SPARC assembly code. LaTTe is an open-source, high performance JVM interpreter implementation [11] . We use LaTTe for our experiments as it is non-proprietary and for ease of reproducibility of results. However, the ideas presented in this paper are applicable and beneficial for optimizing any JVM.. Each Java bytecode implementation is declared as a section of assembly code at position interpret start + opcode * DISP where interpret start label marks the base address of the loop; opcode is the byte representing the bytecode opcode; and DISP is the maximum number of bytes (256) reserved for the native code that implements the bytecode semantics. Notice that in LaTTe's interpreter engine, the most important loop variables, the top of the stack (TOP) and the logical program counter (PC), are kept in SPARC machine registers for improved performance. Figure 3 also details the execution of an ILOAD operation, which requires 6 machine instructions. The tasks of fetching, decoding and jumping to the next bytecode to be executed define the bytecode dispatch cost. The dispatch cost requires 4 more instructions of expensive type (load and branch instructions) to be executed: a ldub to load the next bytecode; a sll to calculate the next bytecode address; a jmp to transfer control to that new address; and an add to update the program counter. In this example, we also notice that the dispatch cost is more than half of the typical size of the native code implementation of the most commonly executed Java bytecode (load from local variables on the average account for 35.5% of SPEC JVM98 total executed bytecodes [12] ). A dispatch optimization technique has been proposed in [13] .. Another source of overhead exists in the execution of the bytecode semantics in which a stack machine is being emulated in software. This forces the copy of operands and results to and from the other Java memory areas (e.g., the heap and the local variables array) to the Java stack. Any technique that reduces the cost of dispatching a new bytecode (like threaded code interpreter), reduces the data transfer to/from the Java stack or reutilizes the translation work of previously executed bytecodes can improve the overall performance of Java programs. In this paper we focus on minimizing the stack machine overhead.. JIT compilers [11, 14, 15] eliminate the above issues altogether at the cost of more space to store the compiled methods and the compilation framework itself and associated runtime cost. A JIT compiler is not a viable solution in domains where space constraints limit the available memory such as smart card.

B I O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B I O O O O O O O O O B I O O O O O O O O O O O O O O O O O O B I O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B I O O O O O O O O O O O O O O O O O O O B I O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B I O O O O O O O O O O O O O O O O O O O O O O O O B I O O O O O O O O O O O O O O O O O O O O O O B I O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B I O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O 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