An L2-miss-driven early register deallocation for SMT processors The register file is one of the most critical datapath components limiting the number of threads that can be supported on a Simultaneous Multithreading (SMT) processor. To allow the use of smaller register files without degrading performance, techniques that maximize the efficiency of using registers through aggressive register allocation/deallocation can be considered. In this paper, we propose a novel technique to early deallocate physical registers allocated to threads that experience L2 cache misses. This is accomplished by speculatively committing the load-independent instructions and deallocating the registers corresponding to the previous mappings of their destinations, without waiting for the cache miss request to be serviced. The early deallocated registers are then made immediately available for allocation to instructions within the same thread as well as within other threads, thus improving the overall processor throughput. On the average across the simulated mixes of multiprogrammed SPEC 2000 workloads, our technique results in 33% improvement in throughput and 25% improvement in terms of harmonic mean of weighted IPCs over the baseline SMT with the state-of-the-art DCRA policy. This is achieved without creating checkpoints, maintaining per-register counters of pending consumers, performing tag re-broadcasts, register re-mappings and/or additional associative searches. Simultaneous Multithreading (SMT) is an important architectural paradigm for increasing the processor throughput in an area-efficient manner by sharing the key datapath resources among the instructions from multiple threads [18, 25] . One such shared resource in an SMT datapath is the physical register file (RF), which needs to be sized very generously to support the full architectural state for each thread as well as to provide a sufficient number of additional registers for renaming, all within a common RAM structure. For example, for an ISA with 32 architectural registers, 128 registers are needed to maintain the precise state for a 4-threaded SMT, in both integer and floating point RFs. When renaming registers are taken into account, the total number of entries within each RF can reach several hundred. The large access delays, high power consumption, and significant design complexity associated with such RFs are major factors limiting the number of simultaneous threads that can be supported by an SMT machine, especially at high frequency implementations. Pipelining the access to large RFs over several cycles requires multiple levels of bypass and also lengthens the branch resolution and the load-hit speculation loops [3] .. An alternative to building large RFs is to use a smaller number of registers in a more efficient fashion. Higher efficiency of register utilization in an SMT processor can be achieved by addressing two related issues: 1) how to distribute the available registers among the threads, and 2) how to manage these registers in order to provide a larger supply for distribution. We generically refer to these two key aspects as register distribution and register management.. Register distribution. This issue is addressed in the recent literature through a series of proposals, such as I-Count [25] , STALL [24] , FLUSH [24] , DCRA [5] , and Hill-Climbing [7] techniques. I-Count gives fetching (and thus register allocation) priority to threads with fewer not-yet-executed instructions. The FLUSH mechanism completely squashes a thread which experienced a long-latency L2 cache miss, releasing all physical registers allocated to this thread and assigning them to other threads while the cache miss is being serviced. The STALL mechanism simply blocks further resource allocations to such threads, without squashing the in-flight instructions. FLUSH generally provides higher performance than STALL [24] , but it also incurs non-trivial overheads, because the squashed instructions have to always be re-fetched, rescheduled, reexecuted and all shared resources have to be reallocated to these instructions again. Consequently, the first allocations, performed prior to the discovery of a cache miss, just waste the resources, even for the load-independent instructions that executed without problems. The DCRA policy takes a different approach and instead allocates more resources to memory-bound threads, attempting to help their performance. The Hill-Climbing mechanism further improves on DCRA by observing the impact of resource distribution decisions at run time and feeding this information back to the front end of the pipeline to guide future allocations. Register management. All of the above approaches still work within the traditional register management framework. Traditional register allocation and deallocation mechanisms, both on superscalar and SMT processors, are very conservative -a physical register allocated to the destination of an instruction is released only when the next instruction (from the same thread) writing to the same destination architectural register commits. Several techniques have been proposed in the literature (all in the domain of superscalar processors) to relax these conditions and achieve higher efficiency of register usage. These techniques can be broadly classified into three groups: late allocation [10, 15] , early deallocation [12, 14, 15, 16] and register sharing [2] . While it is possible to trivially extend at least some of these approaches to an SMT machine, the complexity of the resulting solution (which is already high in superscalars) could further escalate on SMT if modifications to the thread-specific resources are required.. In particular, these techniques often require wakeup tag rebroadcasts, register remappings, additional associative searches within the issue queue and the rename table, deadlock avoidance techniques and/or periodic creation of full register file checkpoints. In this paper, we seek solutions for improving the register management mechanisms, but without incurring the complications of the aforementioned designs. Moreover, the scheme that we propose can be used in conjunction with all of these techniques, as it exploits different opportunities for optimizing register usage.. Our solution is motivated by the observation that the primary reason for having a large number of physical registers in the RF, especially on SMT processors, is the capability to buffer a sizable number of inflight instructions following a load that misses into the L2 cache. Figure 1 compares the performance of a 4-threaded SMT machine with perfect L2 cache to one with a realistic L2 cache of 2MB for various RF sizes. As seen from the graph, the performance saturates at 200 registers in the former case, and at around 300 registers in the latter case (details of our simulation framework are provided in Section 3). Consequently, if the registers assigned to instructions waiting for the resolution of the L2 cache miss were not tied up, a much smaller RF would be sufficient to maintain the same performance. Alternatively, a considerably higher performance would be realized using similarly-sized RFs. As the L2 cache misses are relatively more frequent on SMT (because the caches are shared among multiple threads) and physical registers are relatively scarcer compared to a superscalar, it is important to consider techniques for optimizing the RF usage under the L2 cache misses.. The key statistics that provided an inspiration for this work is that the majority of the instructions in the shadow of the long-latency loads are, in fact, load-independent [19] . These load-independent instructions release their issue queue entries fairly fast, but then pile up in the reorder buffer, waiting for the cache miss to be serviced. Therefore, the only shared resources within the SMT datapath that remain allocated to these instructions are the physical registersthose are not released until the cache miss is serviced and the process of instruction commitment resumes. We note that neither STALL, nor FLUSH is designed to specifically exploit this behavior. While STALL does not release the already allocated resources, FLUSH does so aggressively, but incurs inefficiencies of having to refetch and re-execute all flushed instructions, even those that are independent of the long-latency load.. We propose a mechanism to aggressively release physical registers allocated to threads which experience L2 cache misses by speculatively committing the load-independent instructions and deallocating early the previous mappings of their destination registers. The instructions committed speculatively in this fashion remain in the ROB until the load miss is serviced and the actual commitment occurs. The early released registers can be made available to instructions within the same thread (to support higher Memory-Level Parallelism (MLP) by overlapping multiple cache misses), as well as to instructions from other threads, thus directly exploiting the Thread-Level Parallelism (TLP) and improving the overall throughput. The specific nature of the register assignments to threads is still dictated by the best-performing underlying resource distribution policies, such as DCRA or Hill-Climbing -our mechanism just provides more registers for the distribution. In order to maintain the precise state on interrupts and exceptions, the values of the early released registers are saved directly within the ROB entries of the instructions that triggered corresponding early deallocations -this mechanism avoids the need for full register state checkpointing. In order to correctly execute the loaddependent instructions, neither the previous instances of their destinations, nor the previous instances of their sources are early released.. The early register deallocation mechanism proposed in this paper has the following key characteristics:. • It does not incur tag re-broadcasts, register re-mappings, associative searches, rename table modifications or register file checkpoints, does not require per register consumer counters and requires no additional storage within the datapath. Instead, it relies on a simple off-the-critical-path logic at the back end of the pipeline to identify the early deallocation opportunities and save the values of the early deallocated registers within the existing ROB space for precise state reconstruction.. • While it provides some performance benefits even in a singlethreaded execution environment (5% IPC gains for 64-entry RFs), the real advantages come in SMT processors with multiple threads due to the more frequent L2 cache misses and higher pressure on the register file. For a 4-way SMT machine with 256 integer and 256 floating point registers, the proposed mechanism results in 25% improvements in fairness compared to the baseline processor with DCRA resource distribution policy.. • It is complementary to all existing late register allocation and early register deallocation schemes and can be used in conjunction with those mechanisms, as it exploits distinct and previously unexplored early register deallocation opportunity. However, even by itself it outperforms some previously proposed early deallocation schemes (e.g. physical register inlining) on SMT, although results in slightly lower gains during single-threaded execution.. • It works synergistically with recently proposed resource allocation policies for SMT, such as DCRA [5] and Hill-Climbing [7] . While those policies control the distribution of available resources among threads, our technique effectively provides more resources (physical registers) to be used by these policies. As a result, we achieve additional 25% gains on top of DCRA and 26% gains on top of Hill-Climbing for 256-entry RFs in terms of the fairness metric.. The rest of the paper is organized as follows. Section 2 reviews the related work. Our simulation methodology is presented in Section 3. We motivate the proposed technique and present its details in Section 4. Section 5 presents the results and we conclude in Section 6. Physical register file is one of the most critical and performance limiting resources in SMT processors that constrains the number of simultaneous threads that can be supported. In this paper, we proposed a novel mechanism for early deallocation of physical registers to increase the register file efficiency and provide higher performance for the same number of registers. Our technique specifically exploits two fundamental trends in multithread processor design: a) increasing memory access latencies and, b) relatively higher number of L2 cache misses due to cache sharing effects.. The early register deallocation scheme proposed in this paper has the following key advantages:. • It works synergistically with, and can be applied on top of, existing early register deallocation / late allocation mechanisms as well as existing SMT resource distribution polices such as DCRA [5] and Hill-Climbing [7] .. • Applied to a 4-threaded SMT machine with 256 integer and 256 floating point registers (for the combined 512 registers), it provides additional gains of 33% (25%) on top of DCRA mechanism, 38% (26%) on top of Hill-Climbing technique, and 51% (48%) on top of ICOUNT fetching policy in terms of the throughput IPC (fairness metric).. • It does not incur tag re-broadcasts, register re-mappings, associative searches, rename table modifications or register file checkpoints, does not require per register consumer counters and requires no additional storage within the datapath. Instead, it relies on a simple off-the-critical-path logic at the back end of the pipeline to identify the early deallocation opportunities and save the values of the early deallocated registers for precise state reconstruction. While most of the related work was briefly described in Section 1, this section provides more detailed analysis of some prior efforts in the areas of SMT resource distribution, aggressive register management, and checkpointed processor architectures, all of which provided some inspiration for this work.. SMT Resource Distribution. The use of shared as well as partitioned resources in an SMT processor can be indirectly controlled by instruction fetching mechanisms. Several such mechanisms (I-Count [25] , FLUSH [24] and STALL [24] ) were discussed in Section 1. FLUSH++ [6] combines the benefits of STALL and FLUSH and uses the cache behavior of threads to dynamically switch between these two mechanisms. The Data Gating technique of [8] avoids fetching from threads that experience an L1 data miss. In [5] , a resource distribution policy (called DCRA) exercising a more fine grained dynamic control over the shared SMT resources (such as physical registers) was proposed. DCRA first classifies the threads according to their demands for the resources and, based on this classification, determines how the resources should be distributed among the threads. The Hill-Climbing approach [7] observes the impact of resource distribution decisions on the performance and uses this information to improve future decisions. We apply the proposed mechanism on top of both DCRA and HillClimbing and show that serious additional performance gains can be realized in either case. In fact, our mechanism works synergistically with the best-performing resource distribution techniques: it does not take away their advantages, but instead supplies more physical registers to enable more effective register distribution.. Register File Optimizations. Researchers have exploited the inefficiencies in register usage to reduce the number of registers in three major ways. One set of solutions delays the actual allocation of physical registers until the time that the result is written back, [10] , [15] . These schemes avoid tying up destination physical registers between the time of instruction dispatch and instruction writeback by allocating a physical register only at the time of writeback and using separate tags to satisfy the data dependencies. The major drawback of the late allocation schemes is in the form of non-trivial increases in the datapath complexity due to the need to: (a) support several levels of register mapping tables, (b) perform various associative searches on the rename table and issue queue after the reassignment of mappings and (c) avoid potential deadlocks. The second set of techniques aim at reducing the register file pressure by using the early deallocation of physical registers [12] , [14] , [15] , [16] , [9] , [31] , [32] . While these mechanisms differ in the timing and manner of register deallocation, the additional logic needed to support precise state reconstruction and guarantee correctness of the execution is fairly complex, sometimes requiring additional accesses to the rename table [12] or register state checkpointing support [9, 14] . Furthermore, these schemes need to maintain accurate counters of pending consumers to ensure that deallocation occurs only after all such consumers are issued. The technique of [16] deallocates a register after commitment of its last consumer, [9] deallocates a register right after commitment of the instruction itself, and [12] and [14] attempt to deallocate registers after the result is produced. [32] completely avoids register allocations to instructions producing transient values. None of these mechanisms directly exploit the L2 cache misses to optimize register file. While it is possible to implement some of these techniques on SMT to reduce the number of registers, the complexity of the resulting solution will be at least as high as on a superscalar and in some cases (when modifications to the thread-specific resources are involved) even higher. The solution to register file optimization proposed in this paper takes advantage of a previously unexploited opportunity for early register deallocation. Because of this, our technique works synergistically with the previous schemes for register optimization (including those that deallocate registers early) and can be used in conjunction with those mechanisms to provide additional performance advantages, especially in SMT machines. A detailed performance analysis of such synergies is presented in the results section. The third set of solutions reduces the number of registers through the use of register sharing [2] . To address the RF scalability in a multi-context environment, a technique to virtualize logical register contexts by automatically saving the values of unused registers to memory and restoring them back on demand was proposed in [30] . The scheme of [30] requires modifications to the rename stage of the pipeline and the insertion of additional load and store instructions to implement fills and spills.. Checkpointed Processor Architectures. Although we do not rely on creating checkpoints in this work, we draw some inspiration from several recent proposals which use register file checkpointing and exploit load-independence to accelerate the execution of single-threaded applications [11, 17, 19] . There are some principal differences between our proposal and those prior works and it is important to highlight them. For example, Runahead Execution [17] unblocks the ROB when the missing load reaches the ROB head, creates a full register file checkpoint and then allows the following instructions to pseudo-commit. After the load is serviced, the execution resumes from the checkpoint. The net effect is that some subsequent cache misses are generated earlier, effectively resulting in cache prefetching and improved performance. The technique of [11] introduced load value prediction on top of the runahead execution and augmented the benefits of runahead execution with direct performance advantages on the correct predictions. Unless the value prediction is used and it is correct, all instructions executed in the runahead mode still need to be re-executed when the cache miss is serviced. In addition, the complexities and overheads of maintaining the register state checkpoints, buffering the results of the speculative store instructions, and possibly supporting value prediction/verification logic are considerable, especially in SMT processors.. In contrast, the registers that are early deallocated by our scheme are always used by the instructions from the same thread as well as from other threads for the actual execution. Instructions are never re-executed and no resource wastages occur. Most importantly, all pseudo-committed instructions still remain in the ROB (in contrast to the above mentioned schemes), thus no speculative updates of the memory state by the store instructions ever occur and need to be addressed, avoiding the associated complexities (such as the need to maintain and manage the runahead cache as in [17] and [11] ). While our scheme has a somewhat limited utility on a single-threaded superscalar machine as the ROB is likely to quickly fill up and block forward progress (although we show in the results section that performance gains can be realized even in that case), the presence of explicit TLP within a multithreaded processor allows for the progress of other threads to be sustained and fueled by the early deallocated registers even if the ROB of the thread that experienced the L2 cache miss becomes full.. A recent study [19] showed that most of the instructions fitting into the instruction window following an L2 miss are load-independent. This result was corroborated by our experiments and we exploit these statistics directly. Other proposals [1, 23] completely eliminate the ROB and instead use periodic checkpoints, effectively allowing outof-order commit and more aggressive use of registers. In contrast, our technique builds on top of traditional ROB-based architectures, keeping the datapath changes to the minimum. For estimating the performance impact of the schemes described in this paper, we used M-Sim [20] -a significantly modified version of the Simplescalar 3.0d simulator [4] that supports the SMT processor model. M-Sim implements separate models for the key pipeline structures such as the issue queue (IQ), the reorder buffer (ROB), and the physical register file; it also explicitly models register renaming. In the SMT model, the threads share the IQ, the pool of physical registers, the execution units and the caches, but have separate rename tables, program counters, load/store queues and reorder buffers. Each thread also has its own branch predictor. The details of the studied processor configuration are shown in Table 1 . We simulated the full set of SPEC 2000 integer and floating point benchmarks, using the precompiled Alpha binaries available from the Simplescalar website [4] . We skipped the initialization part of each benchmark using the procedure prescribed by the Simpoints tool [21] and then simulated the execution of the following 100 million instructions. For multithreaded workloads, we stopped the simulations after 100 million instructions from any thread had committed.. Our multithreaded workloads contain a subset of the possible combinations of the simulated benchmarks. In selecting the multithreaded workloads, we first simulated all benchmarks in the single-threaded superscalar environment and used these results to classify them as low, medium, and high ILP, where the low ILP benchmarks are memory bound and the high ILP benchmarks are execution bound. In total, we simulated 12 4-threaded workloads, 12. 3-threaded workloads and 12 2-threaded workloads. All workloads were created by mixing the benchmarks with different ILP levels in various ways. The specific benchmarks that constituted each of our workloads are available in [29] .. We used several metrics for evaluating the performance of the multithreaded workloads throughout this paper. The first metric is the total throughput in terms of the commit IPC rate. However, this metric does not accurately reflect changes that favor a thread with high IPC at the expense of significantly hindering a thread with low IPC [13] . Therefore, we also present the result using another metric -"harmonic mean of weighted IPCs". Although the latter metric is really a performance metric that represents a balance between performance and fairness, in the rest of the paper we refer to this metric as "fairness" to be consistent with some previous work [13] .

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On numerical methods for highly oscillatory problems in circuit simulation We propose in this paper a novel technique for an efficient numerical approximation of systems of highly oscillatory ordinary differential equations. In particular, we consider electronic systems subject to modulated signals. A Filon-type method is proposed for use and compared with traditional trapezoidal rule and Runge-Kutta methods. The Filontype method is combined with the waveform relaxation technique for nonlinear systems. Preliminary numerical examples highlight the efficacy of this approach. Most numerical simulators of electric and electronic circuits, such as SPICE (Nagel 1975) , as well as general-purpose solvers of ordinary differential equations (ODEs), like those in MATLAB, use either multistep or Runge-Kutta methods. This is perfectly adequate for a great majority of ODEs in applications, yet falls woefully short for systems subject to modulated signals or RF oscillators. In this setting, traditional quadrature approaches can necessitate the use of minute step-sizes with the consequent outcome of great inefficiencies and often impractical simulation times.. Modulation is the process whereby information is transmitted at a high frequency to enable antennae of practical dimensions to be employed. In amplitude modulation (AM), the information signal/envelope is in the form of a low frequency sinewave, A m sin ω m t. The resultant amplitude-modulated signal is therefore A c (1 + m sin ω m t) sin ω c t, where m = A m /A c . Another variation of amplitude modulation is the Double-Sided Suppressed Carrier A m sin ω m t sin ω c t. ω c = 2πf c is the carrier frequency in rad/s and A c is its amplitude. In general AM the information signal is in the KHz range, while the carrier signal is in the MHz range.. In digital modulation the information to be transmitted is a sequence of ones and zeros, termed bits. The amplitude, frequency or phase of a carrier signal is varied dependent on the bit value. For example, in Binary Phase Shift Keying (BPSK) the modulated signal is of the form b(t) = cos(ω c t)x(t), where x(t) is +A or −A if a '1' or a '0' bit is to be transmitted, respectively. In digital technologies involving more complex formats, such as EDGE, the information/envelopes have bandwidths in the KHz range, while the carriers are 800MHz and 1800MHz. For evaluation of a bit-error ratio of such an RF transmission, several information envelope time periods are required, but the step size is governed by the underlying carrier frequency which is significantly higher than the envelope frequency.. All this motivates the present contribution, which addresses the issue of simulating ODEs involving very high frequencies and widely varying frequency ranges. In particular, we intend to demonstrate that Filon-type methods, applied in tandem with exponential integrators, result in increased efficiencies for systems involving signal of widely varying frequencies. Similar techniques have been already investigated for different models of highly oscillatory ODEs by Khanamirian (2008) .. Some of the results in this paper have been already addressed from the mathematical standpoint in (Condon, Deaño & Iserles 2008) . This paper presents a preliminary study into an alternative technique for numerical integration suitable for systems subjected to high-frequency signals. Numerical examples confirm the theoretical expectations on the significant potential of Filon-type methods in this setting.. Needless to say, this paper lays no claims to a comprehensive treatment of the subject, whether from mathematical, electronic engineering or software engineering point of view, being merely an introduction to the subject and a feasibility study of preliminary ideas. It expands on the theoretical insight gained from (Condon et al. 2008 ) and we expect it to be followed by further publications, addressing this important subject with greater degree of detail.

O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B I O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B O O O O O O O O O O O O O B I O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B I O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O


Using Hardware Counters to Automatically Improve Memory Performance In this paper, we introduce a profile-driven online page migration scheme and investigate its impact on the performance of multithreaded applications. We use lightweight, inexpensive plug-in hardware counters to profile the memory access behavior of an application, and then migrate pages to memory local to the most frequently accessing processor. Using the Dyninst runtime instrumentation combined with hardware counters, we were able to add page migration capabilities to the system without having to modify the operating system kernel, or to re-compile application programs. This approach reduced the total number of non-local memory accesses of applications by up to 90%. Even on a system with small remote to local memory access latency rations, this resulted in up to 16% improvement in execution time. Large cache-coherent, shared-memory servers are widely used for high performance computing. Sun Fire servers now support more than 100 processors [6] . Similarly, the IBM pSeries 680 [10] scales up to 24 processors, the HP Superdome [9] scales to 64 processors, the Compaq AlphaServer GS-series [7] scales to 32 processors, and the SGI Origin 2000 [12] scales up to more than 100 processors 1 .. In this paper, we introduce a dynamic page migration scheme that profiles applications to determine the preferred location for each memory page using hardware counters. We then use system calls to request that the kernel move memory pages to their preferred locations.. In our dynamic page migration algorithm, both profiling and page migration are conducted during the runtime of the applications. For each memory page in the application, we continuously monitor hardware performance counters and collect information about which processor most frequently accesses the page. At fixed time intervals during the application's execution, 1 All names are trademarks of their owners.. 0-7695-2153-3/04 $20.00 (c) 2004 IEEE pages are migrated to memory that is local to the processor that most frequently accesses those.. Although page migration has been extensively studied, our dynamic page migration approach demonstrates several novel features. First, the goal in this paper is not to introduce a new page placement policy. Instead, our goal is to demonstrate that the combination of inexpensive plug-in hardware counters that sample information about interconnect transactions and a simple page migration policy can be used effectively to improve the performance of real applications. The plugin hardware we used in this research is commercially available from Sun Microsystems.. Second, even on multiprocessor systems with small remote to local memory latency ratios, optimizing page placement still provides substantial benefit to some applications. The remote and local latencies in the Sun Fire 6800 servers we used in our research are approximately 300ns and 225ns respectively (i.e. a remote:local memory latency ratio of 1.33:1). This is quite low for a NUMA system, and previous research on optimizing page placements has tended to focus on systems with much larger remote to local memory latency ratios.. Third, using the information provided by hardware counters that gather information based on physical addresses rather than virtual addresses is accurate enough to guide page migration and eliminates the need for getting virtual address information via hardware counters.. The rest of the paper is organized as follows: Section 2 describes the hardware and software components we used; Section 3 describes the steps of our algorithm for dynamic page migration; Section 4 presents the results of our preliminary experiments; Section 5 presents the results for a series of experiments conducted to evaluate our dynamic page migration approach; Section 6 presents the related work. Finally, Section 7 summarizes our results and presents some conclusions. In this paper, we introduced an automatic profiledriven page migration scheme and investigated the impact of our page migration scheme on the memory performance of multithreaded programs. We used commercially available plug-in hardware monitors to profile the applications. We tested our dynamic page migration approach using the OpenMP C implementation of the NAS Parallel Benchmark suite.. Our dynamic page migration approach always reduced the total number of non-local memory accesses in the applications we analyzed compared to their original executions, by up to 90%. Our page migration approach was also able to improve the execution time of the applications up to 16% compared to their original execution time.. We conducted our experiments on a Sun Fire 6800 server which has only small differences between local and non-local memory access times (225ns vs. 300ns). We believe our page migration approach will be even more effective in improving the performance of the applications running on larger cc-NUMA servers such as the Sun Fire 15K. In these larger cc-NUMA servers, the data transfer times differ significantly among local and non-local memory accesses (225ns vs. 400ns). For our page migration approach to work on these larger cc-NUMA servers, however, separate plug-in hardware counters for each coherency domain would be required.. More importantly, the effectiveness of our page migration approach shows the importance of inexpensive hardware counters in automatic performance tuning of the applications. In this paper, our page migration approach depends on accurate interconnect transaction samples gathered from hardware counters. We believe this type of hardware counters and tools like our page migration approach will be of increasing utility as memory systems become more complex.. We believe the effectiveness of our page migration approach also shows the advantage of putting the page migration policy at the user level while only relying on the operating system kernel to provide the actual migration mechanism.. We also believe that for page migration mechanism to be more beneficial, underlying operating system should provide means to trigger page migration without stopping the application. That is, if the user could simply request migration of a page and the underlying operating system could migrate the page during available idle cycles, most of the migration overhead would be hidden. Noordergraaf and Zak [15] describe a set of embedded hardware instrumentation mechanisms implemented for monitoring the system interconnect on Sun Fire servers. The instrumentation supports sophisticated programmable filtering of event counters. Their implementation results in a very small hardware footprint making it appropriate for inclusion in commodity hardware. In our page migration scheme, we heavily used these instrumentation mechanisms to sample interconnect transactions.. Many prior page migration policies [1, 11] have been in the context of non-cache-coherent NUMA multiprocessor systems. These kernel-level policies were based on page fault mechanisms and studied different page placement and migration policies for NUMA multiprocessors with large remote to local latency ratios. Bolosky et al [1] used memory reference traces to drive simulations of NUMA page placement policies. LaRowe et al [11] modified OS memory management modules to decide whether a page will be migrated. In contrast, our research introduces page migration policies for cache-coherent shared memory multiprocessor systems with small remote to local latency ratios. Moreover, our approach implements the migration policy at the user level and uses access frequencies gathered from the plug-in hardware counters.. Chandra et al [5] investigated the effects of different OS scheduling and page migration policies for cachecoherent shared-memory multiprocessors using the Stanford DASH multiprocessor. Although they mainly focused on OS scheduling policies, they also investigated page migration policies based on TLB misses. Chandra et al. reported that page migration did not improve the response time for the workloads used due to overhead incurred by the operating system. They also performed a trace-driven study to explore the possible benefits of memory page migrations. Compared to their approach, our page migration approach is more effective partially due to elimination of most of the operating system overhead by using a slower migration rate.. Verghese et al. [19] studied operating system support for page migration, and replication in cache-coherent shared-memory multiprocessors. They introduced a decision tree to select the action to be taken on memory pages upon cache misses. The actions taken for a page include replication, migration and freeze, depending on the threshold values used in the decision tree. Using the thresholds that gave the best results, they evaluated the approach using a machine simulator for SGI Origin2000 multiprocessors. The multiprocessor system they used also had a large remote to local memory latency ratio of 4:1. They reported that dynamic page placements did not yield performance gains due to the overhead introduced by the operating system. They also reported that the primary sources of overhead were processor synchronization and TLB flushing. Unlike their approach, our page migration approach eliminates most of the operating system overhead due to using a slower migration rate. Moreover, the Sun Fire servers we used in our research incur a lower overhead due to TLB flushing since TLB misses are serviced by hardware.. Kernel-level dynamic page placement schemes are also extensively studied in the Sun(TM) WildFire systems [4, 8, 14] . The Sun WildFire system is a prototype cache coherent NUMA architecture, built from small number of large standard SMP nodes and has large remote to local latency ratios. Hagersten and Koster [8] evaluated the impact of coherent page replication and hierarchical affinity scheduling on TPC-C execution. They used excess-remote-cache-miss counts to guide page placement. Noordergraaf and vander Pas [14] also evaluated kernel-level page migration and replication using a simple HPC application in a large Sun Wild-Fire system. To identify memory pages for migration, they used excess misses that indicate conflict and capacity misses in a local node's cache. They reported that using a replication-only policy yielded much better performance than policies that included migration.. Recently, Bull and Johnson [4] studied the interactions between data distribution, migration and replication for the OpenMP applications. Although they primarily focused on a data distribution extension for OpenMP, they also studied the impact of page migration and replication. Their study also showed that page replication is more beneficial than migration. This is mainly due to higher overhead in page migration from copying a memory page from its local node to a remote node. In comparison, our page migration approach also has a slower migration rate, which partly explains the reduction in page migration overhead.. Recent work has used dynamic page placements to improve the locality for TPC-C in cc-NUMA servers.. Wilson and Aglietti [20] used Verghese's dynamic page placement algorithm to tune TPC-C execution on Sybase. They used a one-second trace of TPC-C execution and a simulator for a 4-node multiprocessor system to study the performance, bandwidth and locality of TPC-C. They used hand-tuned threshold values for dynamic page placements in their simulations.. Wilson and Aglietti showed that dynamic page placement could be effective if operating system overhead is hidden within the idle CPU cycles. Our dynamic page migration algorithm consists of two different modules. The first module gathers profiling information using the Sun Fire Link counters and bus analyzer 3 . The second module migrates memory pages using the profiling information gathered by the first module. In our page migration approach, we insert instrumentation code into the application to gather profiling information, to migrate the memory pages, to bind application threads to processors and to detect the application termination.. We used Dyninst [2] to insert instrumentation code into the application being analyzed. Dyninst is a li-brary that permits the insertion of code into a running program. The Dyninst library provides a machine independent interface to permit the creation of tools and applications that use runtime code patching.. For our dynamic page migration algorithm, instrumentation code is inserted at the entry of the main function, exit point(s) of thr_create function, and the entry of exithandle function. The instrumentation code that is inserted at main loads a shared library that creates additional helper threads for gathering profiling information and migrating memory pages. The instrumentation code inserted at the exit point(s) of thr_create calls the processor_bind system call to explicitly bind the newly created application threads to available processors in a round robin fashion. The helper threads are bound to dedicated processors and the remaining processors are used to bind the other threads in the application. The instrumentation code inserted at the entry to exithandle detects the application termination and cleans up the hardware counters and software libraries.. Our dynamic page migration algorithm is a two-phase algorithm. It creates two helper threads, one for profiling and another for page migration. The profiling thread samples the interconnect transactions and updates the access frequencies of the memory pages for each system board. The migration thread stops the execution of all other application threads at fixed time intervals and triggers page migration based on the profiling information gathered. In addition, to prevent memory pages ping ponging between memory boards, we freeze memory pages that have been migrated recently for a fixed number of page migration iterations (We currently freeze a page if it migrated during the last 3 consecutive intervals). Thus, the memory pages are migrated at fixed time intervals and a page may be migrated more than once throughout the execution of the application.. Our migration algorithm does not currently use any minimum access frequency threshold for the migration of a page. At every migration interval, regardless of the number of accesses, each page is considered as candidate for migration. Alternatively, we could limit migration to the pages with a minimum number of accesses or cache misses and thus migration overhead would potentially be eliminated for pages with little contribution to the application's memory time.

O B O O O O O B O O B O O O O B O O B O O O O O O B O O B O B O O O B O O O O O B B O O O O O O O O O O O O O O O B O O O B O O O B O O O O O O O O B O O O O O O O O B I O O O O O O O O O O O O O O O O O B O O O O O O O O O O O O O O B B O O O O O O O O O O O O O O O O O O O O B O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B O O O O O O B O B B O O O O O O O O O O B O O O B O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B O O B O O O O O O O O O O B B O O O O O O B O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B O O O O O O O O O O O O O O O O O O O O O O O O O O B O O O O O O O O O O O O O O O O O O O O O B O O O O O O O O O O O O O O O O O O O O B O O B O O B O O O O O O O O O O O O O O O B O O O O O O B O O O O O O O O O O B O O O O O O O O O O O O O O O O O O O O O O O O O O B O O O O O O O O O O O O O O O O O O O O O O O B O O O O O O O B O O O O O O O B O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B O O O O O B O O O O O O O O B O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B O O O O O O O B O O O O O O O O B O O O B O O O O O O O O B O O O O B O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B O O O O O O O O O O O O O O O O O O O O O O O O O B O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B O O O O O O O O O O O O O O O O O O B O O B O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B O O O O O O O O O O O O O O O O O O O O O O B O O O B O O O B O O B O O O O O O O O O O O O B O O O O O O B O O O O O O O O O O O O O O O B O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B I O O O O O O O O O O O O O O O O O O O O B I O O O O O O O O O O O O O O O O O O O O O O O O O O B I O O O O O O O O O O O O O O O O O O O O O O O O O B O O O O O O O O O O O O O O O O O O O O O O O O O O O O B O O O O O O O O B O O O O B O O O O O O O O O O O O O O O O O O O O O O O O O O B O O O O O O O O O O O O O O O O O O O O O O O O O B O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B O O O O O B O O O O O O O O O O O O O O B O O O O O B O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B I O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B I O O O O O O O O O O O O B I O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B O O O O O O O O O O O O B O O O O O O O O B I O O O O O O O O O O B O O O O O O O O O O O O O O O B I O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B O O O O O O O O O O O O O B O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B O O O O O O O O O O O O O O O O O O O O O O B O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B O O B O O O O O O O O O O O O O O O O O O O O O O O O O O B I O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B O O O O O O O O O O O O O O O B O B B O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B O O B O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O


Language and Emotional Knowledge: A Case Study on Ability and Disability in Williams Syndrome Williams Syndrome provides a striking test case for discourses on disability, because the characteristics associated with Williams Syndrome involve a combination of “abilities” and “disabilities”. For example, Williams Syndrome is associated with disabilities in mathematics and spatial cognition. However, Williams Syndrome individuals also tend to “have a unique strength in their expressive language skills”, and are socially outgoing and unselfconscious when meeting new people. Children with Williams are said to be “typically unafraid of strangers and show a greater interest in contact with adults than with their peers.” This apparently keen social knowledge is a counterexample to the discussion of disability among academic philosophers, especially philosophers in the early modern period. Locke infamously used the example of disability to claim that Descartes’ arguments in favor of innate ideas were incorrect. On the contrary, Williams Syndrome may stand as an example of innate social knowledge; something that could benefit current discourse in philosophy, disability theory, and medical ethics.

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Computations modulo regular chains The computation of triangular decompositions involves two fundamental operations: polynomial GCDs modulo regular chains and regularity test modulo saturated ideals. We propose new algorithms for these core operations based on modular methods and fast polynomial arithmetic. We rely on new results connecting polynomial subresultants and GCDs modulo regular chains. We report on extensive experimentation, comparing our code to pre-existing Maple implementations, as well as more optimized Magma functions. In most cases, our new code outperforms the other packages by several orders of magnitude. A triangular decomposition of a set F ⊂ k[x1, . . . , xn] is a list of polynomial systems T1, . . . , Te, called regular chains (or regular systems) and representing the zero set V (F ) of F . Each regular chain Ti may encode several irreducible components of V (F ) provided that those share some properties (same dimension, same free variables, . . . ).. Triangular decomposition methods are based on a univariate and recursive vision of multivariate polynomials. Most of their routines manipulate polynomial remainder sequences (PRS). Moreover, these methods are usually "factorization free", which explains why two different irreducible components may be represented by the same regular chain. An essential routine is then to check whether a hypersurface f = 0 contains one of the irreducible components encoded by a regular chain T . This is achieved by testing whether the polynomial f is a zero-divisor modulo the so-called saturated ideal of T . The univariate vision on regular chains allows to perform this regularity test by means of GCD computations. However, since the saturated ideal of T may not prime, the concept of a GCD used here is not standard.. The first formal definition of this type of GCDs was given by Kalkbrener in [14] . But in fact, GCDs over non-integral domains were already used in several papers [9, 16, 12] since the introduction of the celebrated D5 Principle [7] by Della Dora, Dicrescenzo and Duval. Indeed, this brilliant and simple observation allows one to carry out over direct product of fields computations that are usually conducted over fields. For instance, computing univariate polynomial GCDs by means of the Euclidean Algorithm.. To define a polynomial GCD of two (or more) polynomials modulo a regular chain T , Kalkbrener refers to the irreducible components that T represents. In order to improve the practical efficiency of those GCD computations by means of subresultant techniques, Rioboo and the second author proposed a more abstract definition in [23] . Their GCD algorithm is, however, limited to regular chains with zero-dimensional saturated ideals. While Kalkbrener's definition cover the positive dimensional case, his approach cannot support triangular decomposition methods solving polynomial systems incrementally, that is, by solving one equation after another. This is a serious limitation since incremental solving is a powerful way to develop efficient sub-algorithms, by means of geometrical consideration. The first incremental triangular decomposition method was proposed by Lazard in [15] , without proof nor a GCD definition. Another such method was established by the second author in [22] together with a formal notion of GCD adapted to the needs of incremental solving. This concept, called regular GCD, is reviewed in Section 2 in the context of regular chains. A more abstract definition follows.. Let B be a commutative ring with unity. Let P, Q, G be non-zero univariate polynomials in B [y] . We say that G is a regular GCD of P, Q if the following three conditions hold: (i) the leading coefficient of G is a regular element of B, (ii) G lies in the ideal generated by P and Q in B[y], and (iii) if G has positive degree w.r.t. y, then G pseudo-divides both of P and Q, that is, the pseudo-remainders prem(P, G) and prem(Q, G) are null.. In the context of regular chains, the ring B is the residue class ring of a polynomial ring A := k[x1, . . . , xn] (over a field k) by the saturated ideal sat(T ) of a regular chain T . Even if the leading coefficients of P, Q are regular and sat(T ) is radical, the polynomials P, Q may not necessarily admit a regular GCD (unless sat(T ) is prime). However, by splitting T into several regular chains T1, . . . , Te (in a sense specified in Section 2) one can compute a regular GCD of P, Q over each of the ring A/sat(Ti), as shown in [22] .. In this paper, we propose a new algorithm for this task, together with a theoretical study and implementation report, providing dramatic improvements w.r.t. previous work [14, 22] . Section 3 exhibits sufficient conditions for a subresultant polynomial of P, Q ∈ A[y] (regarded as univariate polynomials in y) to be a regular GCD of P, Q w.r.t. T . Some of these properties could be known, but we could not find a reference for them, in particular when sat(T ) is not radical. These results reduce the computation of regular GCDs to that of subresultant chains, see Section 4 for details.. Since Euclidean-like algorithms tend to densify computations, we consider an evaluation-interpolation scheme based on FFT techniques for computing subresultant chains. In addition, we observe that, while computing triangular decomposition, whenever a regular GCD of P and Q w.r.t. T is needed, the resultant of P and Q w.r.t. y is likely to be computed too. This suggests to organize calculations in a way that the subresultant chain of P and Q is computed only once. Moreover, we wish to follow a successful principle introduced in [20] : compute in k[x 1, . . . , xn] instead of k[x1, . . . , xn]/sat(T ), as much as possible, while controlling expression swell. These three requirements targeting efficiency are satisfied by the implementation techniques of Section 5.1. The use of fast arithmetic for computing regular GCDs was proposed in [6] for regular chains with zerodimensional radical saturated ideals. However this method does not meet our other two requirements and does not apply to arbitrary regular chains. We state complexity results for the algorithms of this paper in Sections 5.1 and 5.2.. Efficient implementation is the main objective of our work. We explain in Section 5.3 how we create opportunities for using modular methods and fast arithmetic in operations modulo regular chains, such as regular GCD computation and regularity test. The experimental results of Section 6 illustrate the high efficiency of our algorithms. We obtain speed-up factors of several orders of magnitude w.r.t. the algorithms of [22] for regular GCD computations and regularity test. Our code compares and often outperforms packages with similar specifications in Maple and Magma. The concept of a regular GCD extends the usual notion of polynomial GCD from polynomial rings over fields to polynomial rings modulo saturated ideals of regular chains. Regular GCDs play a central role in triangular decomposition methods. Traditionally, regular GCDs are computed in a top-down manner, by adapting standard PRS techniques (Euclidean Algorithm, subresultant algorithms, . . . ).. In this paper, we have examined the properties of regular GCDs of two polynomials w.r.t a regular chain. The Algorithm presented in Section 3 is our main theoretical result; it shows that one can proceed in a bottom-up manner. This has three benefits described in Section 5. First, this algorithm is well-suited to employ modular methods and fast polynomial arithmetic. Secondly, we avoid the repetition of (potentially expensive) intermediate computations. Lastly, we avoid, as much as possible, computing modulo regular chains and use polynomial computations over the base field instead, while controlling expression swell. The experimental results reported in Section 6 illustrate the high efficiency of our algorithms.

O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B I I O O O O O O O B O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B I O O O O O O O O O O O O O O O B I O O O O O O O O O O O O O O O O O O O O O O O O B I O O O O O O O O O O O O O O O O O O O O O O O O O B I O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B I O O O O O O O O O O O O O O O O O O O O O O B I O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B I O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B I O O B I O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B I O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B I O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B I O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B I O O O O O O O O O O O O O O O O O O O O O O O O O O B I O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B I O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B I O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B I O O B I O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B I O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B I O O O O O O O O O O O O O O O O O O O O O O B I O O O O O O O O O O O O O O O O O O O O O O O O O O O O B I O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B I O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B I I O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O


Bias-free Hypothesis Evaluation in Multirelational Domains Abstract. In propositional domains using a separate test set via random sampling or cross validation is generally considered to be an unbiased estimator of true error. In multirelational domains previous work has already noted that linkage of objects may cause these procedures to be biased and has proposed corrected sampling procedures. However, as we show in this paper, the existing procedures only address one particular case of bias introduced by linkage. We show that the distinction between training and test set needs to be carefully extended based on a graph of potentially linked objects and on their assumed probabilities of reoccurrence. We demonstrate that the bias due to linkage to known objects varies with the chosen proportion of the training/test split and present an algorithm, generalized subgraph sampling, that is guaranteed to avoid bias in the test set for more generalized cases. Experiments with data from the Internet Movie Database illustrate the performance of our algorithm. In machine learning one typically assumes that the true classification of an object depends only on the object itself and, given the object, is independent of the classification of other objects. In this case, setting aside a sufficiently large and randomly chosen part of the training data as a test set, the observed sample error on the test set is an unbiased estimator of true error. However, in many application settings, those mainstream approaches to model evaluation might be inappropriate. As pointed out by [3] , among others, whenever there is autocorrelation, i.e., whenever the target value of one object depends not only on the object itself, but also on other objects' classifications or information that is shared between objects, the observed error on a randomly chosen test set may not be an unbiased estimator anymore. Subgraph sampling as proposed by [3] eliminates this effect but assumes that information shared in the training set does not reoccur with future instances of the domain. We introduce generalized subgraph sampling which prevents a bias due to an increased or reduced proportion of linked objects in the test set and which includes subgraph sampling as a special case. In an experimental evaluation on data from the Internet Movie Database 3 we show that generalized subgraph sampling is indeed able to achieve the correct proportion of linked objects in the test set as required by the application while at the same time delivering the required training/test set sizes. The paper is organized as follows. Section 2 introduces the bias caused by linked objects in multirelational data. We show the importance of reflecting a realistic proportion of linked objects in the test set and consequently present an adapted sampling algorithm in Section 3. Section 4 experimentally compares two variants of generalized subgraph sampling with random sampling and Section 5 discusses related work. The paper concludes with an example of hierarchical relationships in traffic data and poses further challenges for error estimation using multirelational data. In multirelational domains it is well known that linkage introduced by shared objects and autocorrelation causes a bias in test procedures. We demonstrated that the bias varies with the chosen split proportion of a given sample and showed that the test set should reflect the known neighbor probability as encountered on future instances. We presented a sampling procedure, generalized subgraph sampling, which guarantees to partition a sample such that the test set reflects a given known neighbor probability and thus avoids a bias in the error estimate. We demonstrated the effectiveness of our algorithm by experiments on the movie data set.. Other interesting research topics identified during our work concern the question whether it is possible to estimate the known neighbor probability from the data sample under certain conditions. Further, the exploration of corrected sampling procedures applicable to cross validation seem very valuable to us. This paper is motivated by work on traffic data. Traffic data provides information about the number of vehicles and pedestrians that pass along a street during a fixed time interval. The instance space hereby consists of street segments, which denote the part of a street between two intersections. Each segment can be characterized by numerous attributes, e.g. the street name and type, its spatial coordinates and nearby points of interest. As the traffic frequencies within Fig. 6 . Hierarchical structure of traffic data one street are very similar, instances belonging to the same street are subject to autocorrelation. Likewise the expected number of vehicles traveling on a street in a capital city like Berlin is much higher than in some small village. Thus, a hierarchical structure of linkage is imposed on the domain, which is depicted in Figure 6 . In future research we will therefore investigate the behavior of linkage and autocorrelation in hierarchical and graph structured data and try to deduce corrected sampling procedures for those domains.

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Disjoint paths in symmetric digraphs Given a number of requests , we propose a polynomial-time algorithm for finding disjoint paths in a symmetric directed graph. It is known that the problem of finding The purpose of a telecommunication network is to let its nodes communicate with each other. The network tries to satisfy communication requests, each request being composed of a sender, a receiver and some amount of data that must be transmitted. Satisfying the requests means finding a set of paths for each request on which a connection will be established, within the network's capacity constraints. A network is usually represented by a directed or undirected graph, vertices of the graph representing nodes of the network, and edges representing the links between nodes of the network. Furthermore, each vertex and each edge have a capacity which represents the maximum amount of data that may be processed by it at any given time. Whether or not it is possible to satisfy requests on a network translates into a routing problem on a graph with capacities, a classical graph theory problem [1] . If the requests represent simple data transmissions, and if the data can be freely split into small parts that will be independently routed in the network, then the routing problem is called a multicommodity flow problem. On the other hand, if the requests correspond to unsplittable communication channels with unit capacities, the routing problem is called a disjoint path problem. Disjoint paths are used for instance to make a logical ATM 1 network, and for many other networking applications. In this paper, we will study the disjoint path problem within a specific class of graphs: symmetric digraphs. Our motivation comes from the study of optical telecommunication networks (in particular ATM networks). Optical telecommunication devices are directed which means that they are used to send data to a specific direction, or to receive data from a specific direction. However, optical equipments are constituted of pairs of opposite devices so that the amount of data that can be sent in or received from a given direction is the same. We thus model the network by a symmetric digraph where each edge is matched by an opposite edge. The problem is to satisfy a family of requests R = {(x 1 , y 1 ), (x 2 , y 2 ), . . . , (x , y )}, by finding pairwise disjoint paths from x i to y i . Note that in the general problem, each request from x i to y i is associated with a certain amount of traffic expressed as a multiple of some unitary traffic. Here if we have k units of traffic from x i to y i (G + R) Eulerian (in other words the demand can be split and routed via k different paths), then R contains k times the request (x i , y i ). That is the reason we consider R as a family. Disjoint path problems cover in fact four categories, depending on whether the paths must be vertex-disjoint or edgedisjoint, and depending on whether the graph is directed or not. Vertex-disjoint and edge-disjoint path problems are equivalent in many cases [2, 3] . For instance, edge-disjoint path problems can be polynomially reduced to vertex-disjoint path problems without changing the number of requests using line graphs [4] ; in directed graphs vertex-disjoint path problems can be reduced to edge-disjoint ones by simply splitting each vertex into an input/output pair. 2 For undirected graphs, Karp [5] showed that the disjoint path problem is NP-complete. Lynch [6] showed that the problem is NP-complete even if G is planar; Kramer and van Leeuwen [7] showed that the problem is NP-complete even if G is a grid; Middendorf and Pfeiffer [8] showed that the problem is NP-complete even if (G + R) is planar. 3 Nishizeki, Vygen and Xiao Zhou [9] showed that the problem is NP-complete even if G is series-parallel. On the other hand, for a given number of requests, Robertson and Seymour [3] gave a polynomial-time-decision algorithm in O(|V | 3 ). For directed graphs, Even, Itai and Shamir [10] showed that the disjoint path problem is NP-complete, and Fortune, Hopcroft and Wyllie [11] showed that the problem is NP-complete even if the number of requested paths is two. Table 1 recapitulates some of the principal variants of the disjoint path problem in directed graphs and their complexity. 4 We study the case of symmetric digraphs which is one of the best ways to represent any optical network. The vertexdisjoint path problem is the same problem in symmetric digraphs or in undirected graphs. However, the edge-disjoint problem has not yet been entirely solved; it has already been shown by Chanas [16] that the problem is NP-complete in the general case, and that there is a linear algorithm for finding two disjoint paths.. In this paper, we propose a polynomial-time algorithm for finding a bounded number of edge-disjoint paths in a symmetric multigraph, proving the following theorem: We have proven that the disjoint path problem is polynomial for requests in symmetric digraphs (Theorem 1) by proposing a polynomial-time algorithm and proving its correctness in Theorems 2 and 3. This result was quite surprising since disjoint path problems are notoriously hard in directed graphs (finding only two disjoint paths in a directed graph being NP-hard following a result of Fortune, Hopcroft and Wyllie [11] ). This opens up the possibility of finding exact solutions for a few number of requests in symmetric digraphs. It should be noted, however that even though our algorithm relies on Robertson and Seymour's algorithm which they themselves call ''practically unfeasible'', it is possible to make feasible algorithms tailored to a few number of requests (3, 4, 5, . . . ). Indeed, it turns out that the effective number of minimal symmetric disjoint path problems is much smaller than the bound we propose (only 7 minimal problems with 3 requests need to be investigated). Each of those relatively few and small minimal problems could then be tested with more efficient algorithms [18] [19] [20] .

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Anisotropy Preserving DTI Processing Abstract Statistical analysis of diffusion tensor imaging (DTI) data requires a computational framework that is both numerically tractable (to account for the high dimensional nature of the data) and geometric (to account for the nonlinear nature of diffusion tensors). Building upon earlier studies exploiting a Riemannian framework to address these challenges, the present paper proposes a novel metric and an accompanying computational framework for DTI data processing. The proposed approach grounds the signal processing operations in interpolating curves. Well-chosen interpolating curves are shown to provide a computational framework that is at the same time tractable and information relevant for DTI processing. In addition, and in contrast to earlier methods, it provides an interpolation method which preserves anisotropy, a central information carried by diffusion tensor data. Diffusion-weighted imaging (DWI) allows non-invasive quantification of the self diffusion of water in vivo. In biological tissues, characterized by cell membranes and cytostructures, the movement of water is restricted because of these barriers. In tissues such as white matter, which is highly directional, the resulting movement of water is therefore anisotropic. In this way, high diffusion anisotropy reflects the underlying directional arrangement of white matter fibre bundles. Diffusion measurements [which use the same tools as magnetic resonance imaging (MRI)] can characterize this anisotropy. The most common representation of the directional diffusion is through the use of diffusion tensors, a formalism introduced by Basser et al. (1994) . Since then, other higher level representations have been introduced, such as the Q-ball imaging (Tuch 2004) and the diffusion kurtosis imaging (Jensen and Helpern 2010) . In the context of diffusion tensor imaging (DTI), each voxel of the image contains a diffusion tensor, which is derived from a set of DWI measured in different directions. A diffusion tensor is a symmetric positive definite matrix whose general form is given by. where D x x , D yy , D zz relate the diffusion flows to the concentration gradients in the x, y and z directions. The off-diagonal terms reflect the correlation between diffusion flows and concentration gradients in orthogonal directions. This diffusion tensor can be graphically represented as an ellipsoid. This ellipsoid takes the three eigenvectors of the matrix as principal axes (representing the three principal directions of diffusion). The length of the axes, related to the intensities of diffu-sion along them, is determined by the eigenvalues. Diffusion tensor images can thus be viewed as fields of ellipsoids. Classical image processing methods have been developed for scalar fields. As a result, early processing of DTI data first converted the tensor information into scalar data, for instance focusing on the scalar measure of fractional anisotropy (FA), see e.g. (Alexander and Gee 2000) . However, the tensor nature of DTI data soon motivated a generalization of signal processing methodological frameworks to tensor fields. In particular, methods based on the Riemannian geometry of symmetric positive definite matrices have emerged Fletcher and Joshi 2007; Castaño-Moraga et al. 2006; Gur and Sochen 2007; Batchelor et al. 2005; Lenglet et al. 2006 Lenglet et al. , 2009 because the geometric framework provides a nonlinear generalization of calculus in linear spaces.. The present paper also adopts a geometric framework but puts the emphasis on interpolation curves as the central mathematical object required for signal processing in nonlinear spaces. Interpolating curves need not be geodesics to be practically relevant. Instead, the choice of interpolation curves is problem dependent and a subtle trade-off between practical considerations (such as numerical tractability) and theoretical considerations (such as invariance properties by certain group actions for the robustness of the processing operations). We advocate the use of interpolating curves that interpolate separately the eigenvalues of the tensor and its orientation. This is similar in spirit to several previous works (Weldeselassie et al. 2009; Tschumperlé and Deriche 2001; Ingalhalikar et al. 2010 ) and offers good control on the interpolation of the spectral properties and in particular anisotropy, a key DTI information.. The current work is different from the works grounded in the affine-invariant geometry of the cone Arsigny et al. 2007 ), which suffer from swelling anisotropy effect but are nevertheless widely used in practice mainly because of their computational advantage. In the present paper, we recover the tractability of the LogEuclidean framework by handling rotation in the space of quaternions, taking inspiration of their widespread use in robotics. Our approach is also different from the Procrustes analysis proposed in (Dryden et al. 2009; Zhou 2010; Zhou et al. 2013 ). The geometry proposed in those papers shares the invariance properties of our framework but does not enjoy similar computational and anisotropy preserving properties.. Our 'spectral-quaternion' interpolating curves are easy to compute, and allow for a number of desirable properties, including geometric interpolation of the eigenvalues (and of the volume), linear interpolation of (Hilbert) anisotropy, and shadowing of rotations when the anisotropy is small, that is, when the orientation is uncertain. The paper focuses on the theoretical foundations of the proposed framework, not restricted to DTI processing, but also illustrates the potential of the proposed approach for DTI processing through basic filtering and interpolation operations needed in this application. The paper is organized as follows: Sect. 2 introduces four different interpolating curves for symmetric definitepositive matrices. Section 3 studies the mathematical properties of those curves, namely their computational cost, invariances, and the way they deal with diffusion information. Section 4 explores the computation of weighted means using our framework, which is important in all the processing steps. Section 5 uses the interpolating curves to define metrics and similarity measures. Section 6 illustrates the result of our framework in different applications, while Sect. 7 contains concluding remarks. In this paper, we have introduced a novel geometric framework for the diffusion tensor images processing. This framework is based on interpolating curves that interpolate intensities and orientation separately. The main advantage of this method is to control the spectral interpolation of tensors during the processing. Moreover, it possesses all the important properties of existing metrics, such as the invariances and the preservation of other information as the determinant and the orientation of tensors.. Computational obstacles previously described in (Tschumperlé and Deriche 2001; Chefd'hotel et al. 2004) are circumvented by embedding the set of rotation matrices in the space of quaternions, long used for its numerical efficiency in robotics.. The resulting interpolation method retains the computational tractability and the geometry of the Log-Euclidean framework but addresses a limitation of this framework regarding the degradation of anisotropy.. Although several illustrations of the paper exemplify the potential benefit of preserving anisotropy through averaging and interpolation operation encountered in statistical process, the benefits of the proposed framework for clinical applications remain to be demonstrated. Registration and tractography are two particular areas where the advantages of the proposed method should be evaluated quantitatively.. Future research will extend the proposed framework to more complex models of diffusion, such as HARDI. In particular, Riemannian methods used to process those models suffer the same drawback of degradation of the anisotropy (Cheng et al. 2009; Goh et al. 2011) . It is interesting to note that recent contributions have advocated a decoupling between orientation and other parts of the diffusion model to correct those artifacts (Cetingül et al. 2012; Ncube and Srivastava 2011) .

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Software verification for TinyOS We describe the first software tool for the verification of TinyOS 2, MSP430 applications at compile-time. Given assertions upon the state of the sensor node, the tool boundedly explores all program executions and returns to the programmer an error trace leading to any assertion violation. Besides memory-related errors (out-of-bounds arrays, nullpointer dereferences), we verify application-specific assertions, including low-level assertions upon the state of the registers and peripherals.

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