Timing-Driven Floorplanning with Intermediate Buffer Insertion Maggie Z.-W . Kang Wayne W.-M . Dai Tom Dillinger David LaPotin UCSC-CRL-97-03 February 14 , 1997 Baskin Center for Computer Engineering & Information Sciences University of California , Santa Cruz Santa Cruz , CA 95064 USA abstract As the devices and lines shrink into the deep submicron range , it is more effective to insert the intermediate buffers rather than to widen the wires . Almost all existing timing driven floorplanning and placement algorithms and tools do n't consider the option of buffer insertion , so many good solutions with smaller area and better routability may be unnecessarily excluded . In this paper , we propose a new methodology of floorplanning and placement where buffered trees are used to estimate the wiring delay . Instead of treating the delay as one of the objectives as done by most of the previous works , we formulate the Delay Bounded Minimum Buffered Tree -LRB- DBMB-tree -RRB- as follows : given a net and delay bounds associated with critical terminals , construct a tree with intermediate buffers inserted to minimize the total wiring length while satisfying the given delay bounds . Based on the Elmore delay model , we propose an efficient algorithm to construct DBMB-tree for floorplanning and placement . Experiment results show that using buffer insertion at the floorplanning and placement stage yields significantly better solutions in terms of both chip area and total wire length . Existing multi-objective floorplanning tools use weighted cost summation subject to user-defined constraints to evaluate the solution . It is difficult , if not impossible , to derive a set of weight values from the vaguely defined multiple objectives and the optimization results are very sensitive to the choice of the weight values . Multi-dimension cost vector is introduced to represent the cost value for each objective explicitly -LSB- 10 -RSB- . We define the acceptance function in multiple dimensions based on the votes of invited experts , and order the objectives by their sensitivities . Multiple objectives are introduced gradually during the optimization process . The experiment results demonstrate the efficiency of the approach . 1 Introduction In high speed design , long lines should be treated as distributed RC delay lines and the delay of the lines can be reduced by wire widening or intermediate buffer insertion . Widening the wire makes it a more capacitive line with smaller line resistance . By increasing the sizes of buffers at the source , the wire delay will be reduced . On the other hand , the intermediate buffers decouple a large load that is off the critical path or divide a long wire into short segments each of which has small line resistance , making the delay of the line more linear with the length . As the devices and lines shrink into the deep submicron range , it is more effective , both in terms of power and area , to insert the intermediate buffer rather than to widen the wires . Because floorplanning and placement have a significant impact on achievable signal delay in timing driven layout design , many research centered on timing driven floorplanning and placement . Almost all existing timing driven floorplanning and placement algorithms do n't consider the option of buffer insertion . Only wire lengths or Elmore delay of the lines are used to evaluate the delay . However , it is common practice to insert buffers late at the routing stage . A large industry design may contain as many as tens of thousands intermediate buffers . Therefore it is too conservative to ignore the option of buffer insertion during floorplanning and many good solutions with smaller area and better routability may be unnecessarily excluded . To make the feasible solution space more realistic , in this paper , we propose a new methodology of floorplanning and placement where buffered trees are used to estimate the wiring delay . We formulate the Delay Bounded Minimum Buffered Tree -LRB- DBMB-tree -RRB- as follows : given a net and delay bounds associated with critical terminals , construct a tree with intermediate buffers inserted to minimize the total wiring length while satisfying the given delay bounds . Based on Elmore delay model , we propose an efficient algorithm to construct DBMB-trees for floorplanning and placement . Experiment results show that using buffer insertion at the floorplanning and placement stage yields significantly better solutions in terms of both chip area and total wiring length . The byproduct of this work is the explicit exploration of multiple objectives . Buffer insertion added another competing criteria into the already complicated design space . While a good tradeoff is searched for the competing objectives , such as chip area , total wire lengths , and power consumption , some other constraints have to be met such as delay bound , chip aspect ratio , total number of buffers , and legal buffer locations . Existing multi-objective floorplanning tools use weighted cost summation subject to user-defined constraints to evaluate the solution . It is difficult , if not impossible , to derive a set of weight values from the vaguely defined multiple objectives . The optimization results are very sensitive to the choice of the weight values . Furthermore , the constant weights may not be sufficient to keep the terms of the cost function properly balanced throughout the optimization process . Finally , the reported single solution with minimized aggregated cost value may not represent the best tradeoff among multiple objectives . The inherent weight and constraint specification problems 2 2 . Related Works and Overview of DBMB can be eliminated by explicit design space exploration -LSB- 10 -RSB- . Explicit design space exploration is performed by using a multi-dimensional cost vector and searching for a set of non-redundant solutions representing the best tradeoffs of the cost dimensions . A desirable solution may be chosen from the set and only at that time the trade-offs get made . This methodology fits in the Genetic Algorithm -LRB- GA -RRB- very well since GA maintains a population of solutions -LSB- 10 -RSB- . However , GA has no explicit way to make continuous local search but causes large jumps in the solution space . On the other hand , Simulated Annealing -LRB- SA -RRB- generates a single sequence of solutions and searches for an optimum solution along this search path . We propose a new stochastic optimization method , named genetic simulated annealing -LRB- GSA -RRB- -LSB- 15 -RSB- . GSA successfully combines the local stochastic hill climbing features from simulated annealing and the global crossover operation from genetic algorithm . Multi-dimension cost vector is introduced to represent the cost value for each objective explicitly . SA-based local search generates the single search path and accept each solution along the path by the acceptance function based on its cost and current temperature . The traditional acceptance function is one dimensional and limits the explicit cost value representation in multiple dimensions . We define the multi-dimension acceptance function based on the votes of invited experts . The objectives are ordered by the sensitivity defined for each of them . Multiple objectives are introduced gradually during the optimization process but not simultaneously . The experiment results demonstrate the efficiency of the approach . The remainder of the paper is as follows . Section 2 reviews the related works on interconnect optimization and intermediate buffer insertion , and overviews the underlying idea of our DBMB-tree algorithm . Section 3 describes the DBMB algorithm in detail and presents the experiment results on general floorplanning using DBMB . The Multiple objective optimization is discussed in Section 4 , followed by the conclusion in Section 5 . 2 Related Works and Overview of DBMB 2.1 Related Works Until recently , the minimum steiner tree has been used to construct the routing since it has the smallest total wiring length . However , the source-to-sink path delay in a minimum steiner tree may be too large to satisfy the required delay bound . A number of algorithms have been proposed to make the trade-offs between the total wiring length and the radius -LRB- the longest source-to-sink path length -RRB- of the tree -LSB- 1 , 5 , 7 , 8 , 11 , 17 -RSB- . The \ Bounded-Radius Minimum Routing Tree -LRB- BRMRT -RRB- '' -LSB- 6 -RSB- uses parameter ffl to specify the tradeoff between the minimum radius and the minimum cost . Fig. 2.1 shows three interconnection trees for the same net with different ffl value . For deep submicron design , the path length is no longer accurate for the estimation of the path delay . To directly optimize Elmore delay taking into account different -LRB- b -RRB- -LRB- c -RRB- -LRB- a -RRB- Figure 2.1 : -LRB- a -RRB- the shortest path tree -LRB- SPT -RRB- with ffl = 0 ; -LRB- b -RRB- the minimum cost spanning tree -LRB- MST -RRB- with ffl = 1 ; -LRB- c -RRB- a \ tradeoff '' between the two constructions with < ffl < 1 load capacitances of the sinks , several attempts have been made . With exponential timing complexity , the branch and the bound algorithms -LSB- 4 , 3 -RSB- provide the optimal and near-optimal solutions that minimize the delay from the source to an identified critical sink or a set of critical sinks . For a set of critical sinks , it minimizes the linear combination of sink delays . It is very difficult to choose the proper weights , or the criticality , for the linear combination . While -LSB- 12 -RSB- proposed a modified DreyfusWagner Steiner tree algorithm for minimizing the maximal source-to-sink delay , -LSB- 20 -RSB- proposed an algorithm for maximizing the delay slack , differences between the real delays and the given delay bounds , at sinks . The maximal source-to-sink delay is not necessarily interesting when the corresponding sink is off the critical path . On the other hand , there maybe more than one critical sinks in the same net , which associate with multiple critical paths . In typical deep submicron designs , more than 60 % of the paths in a timing critical design may be critical -LSB- 24 -RSB- . Intermediate buffer insertion creates another degree of freedom for interconnect optimization . Early works on fanout optimization problem focused on the construction of buffered trees in logic synthesis -LSB- 2 , 22 , 23 -RSB- without taking into account the wiring effect . Recently , layout driven fanout optimization have been proposed -LSB- 14 , 25 -RSB- . For a given steiner tree , a polynomial time dynamic programming algorithm was proposed in -LSB- 26 -RSB- for the delay-optimal buffer insertion problem . Based on the dynamic programming algorithm , -LSB- 16 -RSB- integrated wire sizing and power minimization with the tree construction under a more accurate delay model taking signal slew into account . Inspired by the same dynamic programming algorithm , simultaneous steiner tree construction and buffer insertion algorithm was proposed by -LSB- 19 -RSB- , and late the work extended to include wire sizing -LSB- 18 -RSB- . In the formulation of the problem -LSB- 19 , 18 -RSB- , the main objective is to maximize the required arrival time at the root of the tree , which is defined as the minimum among the differences between the arrival time of the sinks and the delay from the root to the sinks . Because timing driven floorplanning and placement are usually iterated with the static timing analysis tools , the critical path information is often available and the timing requirement for critical terminals becomes more and more clear when the 4 3 . Description of DBMB-tree Algorithm iteration progresses . Therefore , it is sufficient to have delay bounded rather than optimizing the delay as in -LSB- 19 , 18 -RSB- . -LSB- 27 -RSB- proposed a Delay Bounded Minimum Steiner tree algorithm -LRB- DBMST -RRB- to construct a low cost Steiner tree with bounded delay constraints . DBMST algorithm consists of two phases : initialization of tree satisfying the given delay bounds and iterative refinement of the topology to reduce the wiring cost while satisfying the delay bounds associated with critical sinks . The Elmore delay at sinks are very sensitive to the topology change and they have to be recomputed every time the topology is changed . DBMST algorithm searches all possible topological update exhaustively at each iteration and it is very time consuming . Our DBMB-tree algorithm makes following two major contributions : ffl Treating the delay bounds provided by static timing analysis tools as constraints rather than formulating the delay into the objectives , as in -LSB- 16 , 26 -RSB- . ffl Efficient buffer insertion and tree refinement algorithm which try to minimize total wire length and the number of buffers . 2.2 Overview of DBMB-tree Algorithm We formulate the Delay Bounded Minimum Buffered tree -LRB- DBMB-tree -RRB- as follows : given a signal net and the delay bounds associated with the critical terminals , construct a tree with intermediate buffers inserted to minimize the total wiring length while satisfying the given delay bounds . Based on Elmore delay model , we develop an efficient algorithm for DBMB spanning tree construction . Contrast to DBMST -LSB- 27 -RSB- which starts with max-delay-slack tree , DBMB-tree algorithm begins with a routing tree which trades off the minimum total wiring length and the minimum source-sink path length based on the criticality defined for critical sinks . For those sinks not meeting the delay bounds , the algorithm first applies buffer insertion to reduce the Elmore delay of the sinks . Then for the sinks whose delay bounds still can not be satisfied with intermediate buffer insertion , the algorithm refines the topology of the tree by the cut-and-link operation to reduce the sourceto-sink path delay . The cut-and-link operation will not increase the Elmore delay from the source to other sinks and minimize the increase in total wire length . If necessary , the buffer insertion operation will be invoked for the second time . The algorithm guarantees to find a feasible , hopefully optimal or near optimal , solution , if one exists . The overall time complexity of the DBMB spanning tree algorithm is O -LRB- n2 -RRB- , where n is the total number of terminals of the net . 3 Description of DBMB-tree Algorithm 3.1 Delay Model Before discussing the DBMB-tree algorithm , we briefly review the Elmore delay model . Elmore delay model is based on the first moment of the impulse response for 3 . Description of DBMB-tree Algorithm 5 a distributed RC representation of the routing tree -LSB- 13 , 21 -RSB- and it is widely used in interconnect optimization -LSB- 13 -RSB- . Given a signal net S = fs0 ; s1 ; ? ? ? ; sng with s0 the source and s1 , ? ? ? , sn sinks , routing tree T rooted at the source s0 , let ewv denote the edge from node v to its parent node w in T . The resistance and capacitance of edge ewv are denoted by rwv and cwv , respectively . Let Tv denote the subtree of T rooted at v , and let ci denote the load capacitance of sink si . We use Cv to denote the tree capacitance of Tv , defined to be the sum of the load capacitances of the sinks and the capacitances of the edges in Tv . The Elmore delay along edge ewv equals to rwv -LRB- cwv2 + Cv -RRB- . Let rd denote the on-resistance of the output driver at the source . Then t0 ; i , the Elmore delay from the source to the sink si , is : t0 ; i = rdC0 + X ewv2path -LRB- s0 ; si -RRB- rwv -LRB- cwv 2 + Cv -RRB- -LRB- 3.1 -RRB- Assume rwv and cwv proportional to the length of ewv , scaled by the unit resistance r0 and unit capacitance c0 , the first term rdC0 in Eq . 3.1 is linear with the total wire length of the tree T , while the second term has quadratic dependence on the path length from s0 to si and also depends on the capacitive load of the sinks in T . 3.2 DBMB-tree Algorithm We formulate the DBMB spanning tree problem as follows : Input : A signal net S = fs0 ; s1 ; ? ? ? ; sng , where s0 is the source and s1 , ? ? ? , sn the sinks . The geometric locations for each terminal of S and delay bound del -LRB- si -RRB- associated with each critical sink si . Output : Spanning tree T rooted at s0 which spans S and has intermediate buffers inserted . Objective : Minimize the total wiring length of T . Constraint : For each critical sink si : t0 ; i < = del -LRB- si -RRB- , where t0 ; i is the Elmore delay from the source to si . In the DBMB-tree algorithm presented here , we only consider non-inverting buffers . The algorithm can be easily extended to handle the inverting buffers . Let tb , rb and cb denote the internal delay , resistance and capacitance of the non-inverting buffer respectively . DBMB-tree construction consists of three phases : 1 . Estimate the achievable optimal delay t ? 0 ; i for each critical sink si 2 S . If 9si 2 S : t ? 0 ; i > del -LRB- si -RRB- , no buffered tree satisfying the delay bounds exists . 2 . Construct an initial spanning tree T using Prim-Dijkstra tradeoff algorithm which obtains the good routing cost and good source-sink path length at critical sinks simultaneously . 3 . Refine T by placing buffers or applying the cut-and-link operations . For each critical sink si , whose Elmore delay does n't meet the specified bound : ffl Insert intermediate buffers if the reduced Elmore delay t00 ; i < = del -LRB- si -RRB- . 6 3 . Description of DBMB-tree Algorithm ffl Otherwise , disconnect si and the subtree Ti from T . Select a sink sj 2 T and connect sj to si . Insert a buffer in edge eji eliminating the effect of topology changes to the Elmore delay from the source to the sinks other than those in Ti . Insert buffers at other edges if necessary . The Elmore delay t0 ; i in the modified tree is guaranteed to be within the given bound del -LRB- si -RRB- while the increase of total wiring length is minimized . Given a tree topology T , assume uniform wiring lines and only one buffer can be placed at each edge ejk . Let dj ; k denote the length of edge ejk . The Elmore delay along edge ejk without buffer insertion is : tj ; k = r0dj ; k -LRB- c0dj ; k 2 + Ck -RRB- -LRB- 3.2 -RRB- When a buffer is placed x away from sj on edge ejk , the edge delay is : tj ; k = r0x -LRB- c0x 2 + cb -RRB- + r0 -LRB- dj ; k ? x -RRB- -LRB- c0 -LRB- dj ; k ? x -RRB- 2 + Ck -RRB- + rb -LRB- c0 -LRB- dj ; k ? x -RRB- + Ck -RRB- + tb -LRB- 3.3 -RRB- where rb << r0dj ; k , cb << c0dj ; k and tb << tj ; k . The optimal x value can be found for the single buffer accordingly -LSB- 9 -RSB- . For the purpose of floorplanning , we assume the buffer is placed immediately after sj in the following . 3.3 Estimation of Achievable Optimal Delay Given the terminal locations determined by the floorplanning or placement , the algorithm first estimates , for each critical sink , the shortest path delay that can be obtained with buffer insertion . Fig . 3.1 shows the buffered shortest path tree TBSP for the given net S = fs0 ; s1 ; ? ? ? ; s10g . Let l ? 0 ; i denote the length of the shortest path from s0 to si . According to Eq . 3.1 , the Elmore delay of si in TBSP , denoted by t ? 0 ; i , gives the smallest delay achievable with buffer insertion : t ? 0 ; i = rdncb + tb + rb -LRB- c0l ? 0 ; i + ci -RRB- + r0l ? 0 ; i -LRB- c0l ? 0 ; i 2 + ci -RRB- -LRB- 3.4 -RRB- We introduce criticality ffi for each sink si to measure how difficult the delay bound can be achieved : ffi = t ? 0 ; i del -LRB- si -RRB- , i.e. the ratio of the achievable smallest delay t ? 0 ; i to specified delay bound of si . If t ? 0 ; i << del -LRB- si -RRB- , then ffi ! 0 . If t ? 0 ; i > del -LRB- si -RRB- , ffi > 1 then the bound is too tight to be achievable for the given floorplan or placement . If 8i 2 -LSB- 1 ; n -RSB- , t ? 0 ; i < = del -LRB- si -RRB- , then the algorithm continues phase 2 and 3 , otherwise the floorplanning or placement is timing infeasible . O -LRB- n -RRB- is sufficient for the calculation of t ? 0 ; i and ffi for all the sinks . 3.4 Construction of Initial Spanning Tree The second term of Elmore delay t0 ; i in Eq . 3.1 has quadratical dependence on the path length from s0 to si . For sinks with higher criticality ffi ? 1 , l0 ; i should be closer to the shortest path length l ? 0 ; i. 3 . Description of DBMB-tree Algorithm 7 s s s s s s 6 3 7 8 4 10 1 s s 9 s 2 s s 5 Figure 3.1 : Shortest path tree with buffer insertion , which connects each sink si with source s0 directly and places a buffer on each source-sink connection . Instead of starting with extreme solutions with minimum total wiring lengths or minimum path lengths , we combine Prim 's MST algorithm with Dijkstra 's SPT algorithm and use criticality to make the tradeoff between both objectives . Initially tree T consists of only s0 and iteratively edge eij and sink sj are added to T , where si 2 T and sj 2 S ? T . si and sj are chosen in such a way to minimize : ffjl0 ; i + di ; j -LRB- 3.5 -RRB- When for each sj 2 S : ffj = 0 , the algorithm is identical to Prim 's MST and constructs T with minimum wiring length as in Fig. 3.2 -LRB- a -RRB- . As ffj increases , T has larger wiring length but smaller path length as in Fig. 3.2 -LRB- b -RRB- . The algorithm is identical to Dijkstra 's SPT when ffj = 1 for each sj 2 S as in Fig. 3.2 -LRB- c -RRB- . We define slack for each sink si as follows : ffii = del -LRB- si -RRB- ? t0 ; i -LRB- 3.6 -RRB- After the initial construction , if 8si 2 S : ffii > = 0 , the algorithm has already found the buffered spanning tree subject to the given constraints . Otherwise , continues phase 3 to reduce the Elmore delay at si with no increase of Elmore delay at other sinks and with minimal increase of the total wiring length . The capacitances for all subtrees can be calculated by traversing the routing tree in depth first order . The delays along all edges and the delay from the source to sinks , which equals the added delay of edges along the source-sink path , can be computed by traversing the routing tree in breadth first order . Therefore , the Elmore delays and slacks of all the sinks can be calculated in O -LRB- n -RRB- time . The timing complexity of this initialization is O -LRB- n2 -RRB- , due to the Prim-Dijstra 's tradeoff algorithm . 3.5 Intermediate Buffer Insertion Given a routing topology T , for a critical sink si whose Elmore delay does n't meet the bound , we define the driving path pdi ; j for each sink sj 2 T : 8 3 . Description of DBMB-tree Algorithm s 5 s 6 s 7 s 10 s 9 s 8 ss 1 s 4 3 s 2 s s 5 s 6 s 7 s 10 s 9 s 8 ss 1 s 4 3 s 2 s s 5 s 6 s 10 s 9 ss 1 s 4 2 s s 3 s 8 s 7 -LRB- a -RRB- -LRB- b -RRB- -LRB- c -RRB- Figure 3.2 : Prim-Dijkstra tradeoff : when 8sj 2 S : ffj = 0 , the algorithm is identical to Prim 's MST and constructs T with minimum wiring length shown in -LRB- a -RRB- . As ffj increases , T has larger wiring length but smaller path length shown in -LRB- b -RRB- , and the algorithm is identical to Dijkstra 's SPT when ffj = 1 for each sj 2 S shown in -LRB- c -RRB- . pdi ; j = fewv j ewv 2 path -LRB- s0 ; si -RRB- ^ ewv 2 path -LRB- s0 ; sj -RRB- ^ no buffer on path -LRB- sv ; sj -RRB- g -LRB- 3.7 -RRB- Let ldi ; j denote the length of pdi ; j . To calculate the driving path length for all other sinks with respect to si , first trace the path path -LRB- s0 ; si -RRB- from si to s0 and mark each edge on this path . Then traverse T from s0 ; for each visited sink sv , ldi ; v can be calculated based on ldi ; w and dw ; v where sw is the parent of sv and dw ; v the length of ewv . The driving path length for sv is given by : ldi ; v = 8 >> > < >> > : ldi ; w + dw ; v if ewv 2 path -LRB- s0 ; si -RRB- and no buffer on ewv dw ; v if ewv 2 path -LRB- s0 ; si -RRB- and one buffer on ewv ldi ; w if ewv = 2 path -LRB- s0 ; si -RRB- and no buffer on ewv if ewv = 2 path -LRB- s0 ; si -RRB- and one buffer on ewv -LRB- 3.8 -RRB- Therefore the driving path length of other sinks with respect to one particular sink si can be computed in linear time . After inserting one buffer at edge ejk in topology T , the reduction of Elmore delay at si is : ? tjk0 ; i = rd?Cjk0 + ldi ; j -LRB- Ck + cjk ? cb -RRB- -LRB- 3.9 -RRB- where ? Cjk0 equals to Ck + cjk ? cb if there is no buffer along the path path -LRB- s0 ; sj -RRB- as illustrated in Fig. 3.3 -LRB- a -RRB- ; it equals to 0 , otherwise as illustrated in Fig. 3.3 -LRB- b -RRB- . For a sink in Tk , the buffer placed on edge ejk introduces a little delay penalty : tb + rb -LRB- Ck + cjk -RRB- , where tb and rb , the internal delay and the resistance of the buffer respectively , are usually very small . Traversing T from s0 , ? Cjk0 , thus ? tjk0 ; i can be calculated in linear time . To reduce the Elmore delay from the source to the critical sink si , whose Elmore delay does n't meet the bound , select an edge ejk with maximal tjk0 ; i and insert one 3 . Description of DBMB-tree Algorithm 9 s 5 s

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O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B I I O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B I O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B O O O O O O O O O O O O O O O O O O O O O O O O O O O B O O O O O O O O O O O O O O O O O O O O O O B I O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B I O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O 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O O O O O O O O O O O O B I I O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O B I O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O

buffer insertion
delay bounded minimum buffered tree
floorplanning
total wiring length

cost vectors
multi-objectives
timing constraints