Counting

Networks

James

Aspnes

Maurice

Herlihy

Nir

Shavit

Digital

Equipment

Corporation

Cambridge

Research

Lab

CRL

August

Almaden

Research

Center

A

large

part

of

this

work

was

performed

while

the

author

was

at

Carnegie-Mellon

University

Laboratory

for

Computer

Science

Author

's

current

address

Computer

Science

Department

School

of

Mathematics

Tel-Aviv

University

Tel-Aviv

Israel

This

work

was

supported

by

ONR

contract

NSF

grant

DARPA

contract

and

by

a

Rothschild

postdoctoral

fellowship

A

large

part

of

this

work

was

performed

while

the

author

was

at

IBM

's

Almaden

Research

Center

Abstract

Many

fundamental

multi-processor

coordination

problems

can

be

expressed

as

counting

problems

processes

must

cooperate

to

assign

successive

values

from

a

given

range

such

as

addresses

in

memory

or

destinations

on

an

interconnection

network

Conventional

solutions

to

these

problems

perform

poorly

because

of

synchronization

bottlenecks

and

high

memory

contention

Motivated

by

observations

on

the

behavior

of

sorting

networks

we

offer

a

new

approach

to

solving

such

problems

by

introducing

counting

networks

a

new

class

of

networks

that

can

be

used

to

count

We

give

two

counting

network

constructions

one

of

depth

log

n

-LRB-

log

n

-RRB-

using

n

log

n

-LRB-

log

n

-RRB-

gates

and

a

second

of

depth

n

using

n

n

gates

These

networks

avoid

the

sequential

bottlenecks

inherent

to

earlier

solutions

and

substantially

lower

the

memory

contention

Finally

to

show

that

counting

networks

are

not

merely

mathematical

creatures

we

provide

experimental

evidence

that

they

outperform

conventional

synchronization

techniques

under

a

variety

of

circumstances

This

report

supersedes

CRL

Tech

Report

A

preliminary

version

of

this

work

appeared

in

the

Proceedings

of

the

ACM

Symposium

on

the

Theory

of

Computing

New

Orleans

May

c

Digital

Equipment

Corporation

James

Aspnes

and

Nir

Shavit

All

rights

reserved

INTRODUCTION

Introduction

Many

fundamental

multi-processor

coordination

problems

can

be

expressed

as

counting

problems

processors

collectively

assign

successive

values

from

a

given

range

such

as

addresses

in

memory

or

destinations

on

an

interconnection

network

In

this

paper

we

offer

a

new

approach

to

solving

such

problems

by

introducing

counting

networks

a

new

class

of

networks

that

can

be

used

to

count

Counting

networks

like

sorting

networks

-LSB-

-RSB-

are

constructed

from

simple

two-input

two-output

computing

elements

called

balancers

connected

to

one

another

by

wires

However

while

an

n

input

sorting

network

sorts

a

collection

of

n

input

values

only

if

they

arrive

together

on

separate

wires

and

propagate

through

the

network

in

lockstep

a

counting

network

can

count

any

number

N

AE

n

of

input

tokens

even

if

they

arrive

at

arbitrary

times

are

distributed

unevenly

among

the

input

wires

and

propagate

through

the

network

asynchronously

Figure

provides

an

example

of

an

execution

of

a

counting

network

A

balancer

is

represented

by

two

dots

and

a

vertical

line

-LRB-

see

Figure

-RRB-

Intuitively

a

balancer

is

just

a

toggle

mechanism

alternately

forwarding

inputs

to

its

top

and

bottom

output

wires

It

thus

balances

the

number

of

tokens

on

its

output

wires

In

the

example

of

Figure

input

tokens

arrive

on

the

network

's

input

wires

one

after

the

other

For

convenience

we

have

numbered

them

by

the

order

of

their

arrival

-LRB-

these

numbers

are

not

used

by

the

network

-RRB-

As

can

be

seen

the

first

input

-LRB-

numbered

-RRB-

enters

on

line

and

leaves

on

line

the

second

leaves

on

line

and

in

general

the

Nth

token

will

leave

on

line

N

mod

-LRB-

The

reader

is

encouraged

to

try

this

for

him/herself

-RRB-

Thus

if

on

the

ith

output

line

the

network

assigns

to

consecutive

outputs

the

numbers

i

i

i

it

is

counting

the

number

of

input

tokens

without

ever

passing

them

all

through

a

shared

computing

element

Counting

networks

achieve

a

high

level

of

throughput

by

decomposing

interactions

among

processes

into

pieces

that

can

be

performed

in

parallel

This

decomposition

has

two

performance

benefits

It

eliminates

serial

bottlenecks

and

reduces

memory

contention

In

practice

the

performance

of

many

can

implement

a

balancer

using

a

read-modify-write

operation

such

as

Compare

Swap

or

a

short

critical

section

INTRODUCTION

shared-memory

algorithms

is

often

limited

by

conflicts

at

certain

widelyshared

memory

locations

often

called

hot

spots

-LSB-

-RSB-

Reducing

hot-spot

conflicts

has

been

the

focus

of

hardware

architecture

design

-LSB-

-RSB-

and

experimental

work

in

software

-LSB-

-RSB-

Counting

networks

are

also

non-blocking

processes

that

undergo

halting

failures

or

delays

while

using

a

counting

network

do

not

prevent

other

processes

from

making

progress

This

property

is

important

because

existing

shared-memory

architectures

are

themselves

inherently

asynchronous

process

step

times

are

subject

to

timing

uncertainties

due

to

variations

in

instruction

complexity

page

faults

cache

misses

and

operating

system

activities

such

as

preemption

or

swapping

Section

defines

counting

networks

In

Sections

and

we

give

two

distinct

counting

network

constructions

each

of

depth

less

than

or

equal

to

n

each

using

less

than

or

equal

to

-LRB-

n

n

-RRB-

balancers

To

illustrate

that

counting

networks

are

useful

we

use

counting

networks

to

construct

high-throughput

shared-memory

implementations

of

concurrent

data

structures

such

as

shared

counters

producer/consumer

buffers

and

barriers

A

shared

counter

is

simply

an

object

that

issues

the

numbers

to

m

in

response

to

m

requests

by

processes

Shared

counters

are

central

to

a

number

of

shared-memory

synchronization

algorithms

-LRB-

e.g.

-LSB-

-RSB-

-RRB-

A

producer/consumer

buffer

is

a

data

structure

in

which

items

inserted

by

a

pool

of

producer

processes

are

removed

by

a

pool

of

consumer

processes

A

barrier

is

a

data

structure

that

ensures

that

no

process

advances

beyond

a

particular

point

in

a

computation

until

all

processes

have

arrived

at

that

point

Compared

to

conventional

techniques

such

as

spin

locks

or

semaphores

our

counting

network

implementations

provide

higher

throughput

less

memory

contention

and

better

tolerance

for

failures

and

delays

The

implementations

can

be

found

in

Section

Our

analysis

of

the

counting

network

construction

is

supported

by

experiment

In

Section

we

compare

the

performance

of

several

implementations

of

shared

counters

producer/consumer

buffers

and

barrier

synchronization

on

a

shared-memory

multiprocessor

When

the

level

of

concurrency

is

sufficiently

high

the

counting

network

implementations

outperform

conventional

implementations

based

on

spin

locks

sometimes

dramatically

Finally

Section

describes

how

to

mathematically

verify

that

a

given

network

counts

In

summary

counting

networks

represent

a

new

class

of

concurrent

algorithms

They

have

a

rich

mathematical

structure

they

provide

effective

NETWORKS

THAT

COUNT

x

x

y

x

x

y

x

x

balancer

input

output

Figure

A

Balancer

solutions

to

important

problems

and

they

perform

well

in

practice

We

believe

that

counting

networks

have

other

potential

uses

for

example

as

interconnection

networks

-LSB-

-RSB-

or

as

load

balancers

-LSB-

-RSB-

and

that

they

deserve

further

attention

Networks

That

Count

Counting

Networks

Counting

networks

belong

to

a

larger

class

of

networks

called

balancing

networks

constructed

from

wires

and

computing

elements

called

balancers

in

a

manner

similar

to

the

way

in

which

comparison

networks

-LSB-

-RSB-

are

constructed

from

wires

and

comparators

We

begin

by

describing

balancing

networks

A

balancer

is

a

computing

element

with

two

input

wires

and

two

output

-LRB-

see

Figure

-RRB-

Tokens

arrive

on

the

balancer

's

input

wires

at

arbitrary

times

and

are

output

on

its

output

wires

Intuitively

one

may

think

of

a

balancer

as

a

toggle

mechanism

that

given

a

stream

of

input

tokens

repeatedly

sends

one

token

to

the

top

output

wire

and

one

to

the

bottom

effectively

balancing

the

number

of

tokens

that

have

been

output

on

its

output

wires

We

denote

by

xi

i

the

number

of

input

tokens

ever

received

on

the

balancer

's

ith

input

wire

and

similarly

by

yi

i

the

number

of

tokens

ever

output

on

its

ith

output

wire

Throughout

the

paper

we

will

abuse

this

notation

and

use

xi

-LRB-

yi

-RRB-

both

as

the

name

of

the

ith

input

-LRB-

output

-RRB-

wire

and

a

count

of

the

number

of

input

tokens

received

on

the

wire

Let

the

state

of

a

balancer

at

a

given

time

be

defined

as

the

collection

of

tokens

on

its

input

and

output

wires

For

the

sake

of

clarity

we

will

assume

Figure

as

well

as

in

the

sequel

we

adopt

the

notation

of

-LSB-

-RSB-

and

and

draw

wires

as

horizontal

lines

with

balancers

stretched

vertically

NETWORKS

THAT

COUNT

that

tokens

are

all

distinct

We

denote

by

the

pair

-LRB-

t

b

-RRB-

the

state

transition

in

which

the

token

t

passes

from

an

input

wire

to

an

output

wire

of

the

balancer

b

We

can

now

formally

state

the

safety

and

liveness

properties

of

a

balancer

In

any

state

-LRB-

i.e.

a

balancer

never

creates

output

tokens

-RRB-

Given

any

finite

number

of

input

tokens

m

to

the

balancer

it

is

guaranteed

that

within

a

finite

amount

of

time

it

will

reach

a

quiescent

state

that

is

one

in

which

the

sets

of

input

and

output

tokens

are

the

same

In

any

quiescent

state

m.

In

any

quiescent

state

dm

and

bm

A

balancing

network

of

width

w

is

a

collection

of

balancers

where

output

wires

are

connected

to

input

wires

having

w

designated

input

wires

xw

-LRB-

which

are

not

connected

to

output

wires

of

balancers

-RRB-

w

designated

output

wires

yw

-LRB-

similarly

unconnected

-RRB-

and

containing

no

cycles

Let

the

state

of

a

network

at

a

given

time

be

defined

as

the

union

of

the

states

of

all

its

component

balancers

The

safety

and

liveness

of

the

network

follow

naturally

from

the

above

network

definition

and

the

properties

of

balancers

namely

that

it

is

always

the

case

that

Pw

i

xi

Pw

i

yi

and

for

any

finite

sequence

of

m

input

tokens

within

finite

time

the

network

reaches

a

quiescent

state

i.e.

one

in

which

Pw

i

yi

m

It

is

important

to

note

that

we

make

no

assumptions

about

the

timing

of

token

transitions

from

balancer

to

balancer

in

the

network

the

network

's

behavior

is

completely

asynchronous

Although

balancer

transitions

can

occur

concurrently

it

is

convenient

to

model

them

using

an

interleaving

semantics

in

the

style

of

Lynch

and

Tuttle

-LSB-

-RSB-

An

execution

of

a

network

is

a

finite

sequence

en

sn

or

infinite

sequence

of

alternating

states

and

balancer

transitions

such

that

for

each

-LRB-

si

ei

si

-RRB-

the

transition

ei

carries

state

si

to

si

A

schedule

is

the

subsequence

of

transitions

occurring

in

an

execution

A

schedule

is

valid

if

it

is

induced

by

some

execution

and

complete

if

it

is

induced

by

an

execution

which

results

in

a

quiescent

state

A

schedule

s

is

sequential

if

for

any

two

transitions

ei

-LRB-

ti

bi

-RRB-

and

ej

-LRB-

tj

bj

-RRB-

where

ti

and

tj

are

the

same

token

then

all

transitions

between

them

also

involve

that

token

NETWORKS

THAT

COUNT

outputs

inputs

Figure

A

sequential

execution

for

a

Bitonic

-LSB-

-RSB-

counting

network

On

a

shared

memory

multiprocessor

a

balancing

network

is

implemented

as

a

shared

data

structure

where

balancers

are

records

and

wires

are

pointers

from

one

record

to

another

Each

of

the

machine

's

asynchronous

processors

runs

a

program

that

repeatedly

traverses

the

data

structure

from

some

input

pointer

-LRB-

either

preassigned

or

chosen

at

random

-RRB-

to

some

output

pointer

each

time

shepherding

a

new

token

through

the

network

-LRB-

see

section

-RRB-

We

define

the

depth

of

a

balancing

network

to

be

the

maximal

depth

of

any

wire

where

the

depth

of

a

wire

is

defined

as

for

a

network

input

wire

and

max

-LRB-

depth

-LRB-

-RRB-

depth

-LRB-

-RRB-

-RRB-

for

the

output

wires

of

a

balancer

having

input

wires

and

We

can

thus

formulate

the

following

straightforward

yet

useful

lemma

Lemma

If

the

transition

of

a

token

from

the

input

to

the

output

by

any

balancer

-LRB-

including

the

time

spent

traversing

the

input

wire

-RRB-

takes

at

most

time

then

any

input

token

will

exit

the

network

within

time

at

most

times

the

network

depth

A

counting

network

of

width

w

is

a

balancing

network

whose

outputs

yw

satisfy

the

following

step

property

In

any

quiescent

state

yi

yj

for

any

i

j.

NETWORKS

THAT

COUNT

To

illustrate

this

property

consider

an

execution

in

which

tokens

traverse

the

network

sequentially

one

completely

after

the

other

Figure

shows

such

an

execution

on

a

Bitonic

-LSB-

-RSB-

counting

network

which

we

will

define

formally

in

Section

As

can

be

seen

the

network

moves

input

tokens

to

output

wires

in

increasing

order

modulo

w.

Balancing

networks

having

this

property

are

called

counting

networks

because

they

can

easily

be

adapted

to

count

the

total

number

of

tokens

that

have

entered

the

network

Counting

is

done

by

adding

a

local

counter

to

each

output

wire

i

so

that

tokens

coming

out

of

that

wire

are

consecutively

assigned

numbers

i

i

w

i

-LRB-

yi

-RRB-

w.

-LRB-

This

application

is

described

in

greater

detail

in

Section

-RRB-

The

step

property

can

be

defined

in

a

number

of

ways

which

we

will

use

interchangeably

The

connection

between

them

is

stated

in

the

following

lemma

Lemma

If

yw

is

a

sequence

of

non-negative

integers

the

following

statements

are

all

equivalent

For

any

i

j

yi

yj

Either

yi

yj

for

all

i

j

or

there

exists

some

c

such

that

for

any

i

c

and

j

c

yi

yj

If

m

Pw

i

yi

yi

lm?i

w

m

It

is

the

third

form

of

the

step

property

that

makes

counting

networks

usable

for

counting

Proof

We

will

prove

that

implies

implies

and

implies

For

any

indexes

a

b

since

a

b

w

it

must

be

that

lm?a

w

m

lm?b

w

m

Thus

implies

Assume

holds

for

the

sequence

yw

If

for

every

i

j

w

yi

yj

then

follows

Otherwise

there

exists

the

largest

a

such

that

there

is

a

b

for

which

a

b

and

ya

yb

From

a

's

being

largest

we

get

that

ya

ya

and

from

we

get

yi

ya

for

any

i

a

and

yi

ya

for

any

a

i

w.

Choosing

c

a

completes

the

proof

Thus

implies

Assume

by

way

of

contradiction

that

does

not

hold

and

does

Without

loss

of

generality

there

thus

exists

the

smallest

a

such

that

m

Pw

i

yi

and

NETWORKS

THAT

COUNT

ya

lm?a

w

m

If

ya

lm?a

w

m

then

since

Pk

i

yi

m

by

simple

arithmetic

there

must

exist

a

b

a

such

that

yb

lm?b

w

m

Since

lm?a

w

m

lm?b

w

m

yb

ya

and

no

c

as

in

exists

a

contradiction

Similarly

if

ya

lm?a

w

m

there

exists

a

b

a

such

that

yb

lm?b

w

m

and

ya

yb

Again

no

c

as

in

exists

a

contradiction

Thus

implies

The

requirement

that

a

quiescent

counting

network

's

outputs

have

the

step

property

might

appear

to

tell

us

little

about

the

behavior

of

a

counting

network

during

an

asynchronous

execution

but

in

fact

it

is

surprisingly

powerful

Even

in

a

state

in

which

many

tokens

are

passing

through

the

network

the

network

must

eventually

settle

into

a

quiescent

state

if

no

new

tokens

enter

the

network

This

constraint

makes

it

possible

to

prove

such

important

properties

as

the

following

Lemma

Suppose

that

in

a

given

execution

a

counting

network

with

output

sequence

yw

is

in

a

state

where

m

tokens

have

entered

the

network

and

tokens

have

left

it

Then

there

exist

non-negative

integers

di

i

w

such

that

Pw

i

di

and

yi

di

lm?i

w

m

Proof

Suppose

not

There

is

some

execution

e

for

which

the

non-negative

integers

di

i

w

do

not

exist

If

we

extend

e

to

a

complete

execution

allowing

no

additional

tokens

to

enter

the

network

then

at

the

end

of

the

network

will

be

in

a

quiescent

state

where

the

step

property

does

not

hold

a

contradiction

In

a

sequential

execution

where

tokens

traverse

the

network

one

at

a

time

the

network

is

quiescent

every

time

a

token

leaves

In

this

case

the

i-th

token

to

enter

will

leave

on

output

i

mod

w

The

lemma

shows

that

in

a

concurrent

asynchronous

execution

of

any

counting

network

any

gap

in

this

sequence

of

mod

w

counts

corresponds

to

tokens

still

traversing

the

network

This

critical

property

holds

in

any

execution

even

if

quiescent

states

never

occur

and

even

though

the

definition

makes

no

explicit

reference

to

non-quiescent

states

NETWORKS

THAT

COUNT

bitonic

-LSB-

-RSB-

bitonic

-LSB-

-RSB-

merger

-LSB-

k

-RSB-

x

x

x

x

x

x

x

y

y

y

y

y

y

y

Figure

Recursive

Structure

of

a

Bitonic

-LSB-

-RSB-

Counting

Network

Counting

vs.

Sorting

A

balancing

network

and

a

comparison

network

are

isomorphic

if

one

can

be

constructed

from

the

other

by

replacing

balancers

by

comparators

or

vice

versa

The

counting

networks

introduced

in

this

paper

are

isomorphic

to

the

Bitonic

sorting

network

of

Batcher

-LSB-

-RSB-

and

to

the

Periodic

Balanced

sorting

network

of

Dowd

Perl

Rudolph

and

Saks

-LSB-

-RSB-

There

is

a

sense

in

which

constructing

counting

networks

is

harder

than

constructing

sorting

networks

Theorem

If

a

balancing

network

counts

then

its

isomorphic

comparison

network

sorts

but

not

vice

versa

Proof

It

is

easy

to

verify

that

balancing

networks

isomorphic

to

the

EvenOdd

or

Insertion

sorting

networks

-LSB-

-RSB-

are

not

counting

networks

For

the

other

direction

we

construct

a

mapping

from

the

comparison

network

transitions

to

the

isomorphic

balancing

network

transitions

By

the

principle

-LSB-

-RSB-

a

comparison

network

which

sorts

all

sequences

of

's

and

's

is

a

sorting

network

Take

any

arbitrary

sequence

of

's

and

's

as

inputs

to

the

comparison

network

and

for

the

balancing

network

place

a

token

on

each

input

wire

and

no

token

on

each

input

wire

We

now

show

that

if

we

run

both

networks

in

lockstep

the

balancing

network

will

simulate

the

comparison

network

that

is

the

correspondence

between

tokens

and

's

holds

NETWORKS

THAT

COUNT

The

proof

is

by

induction

on

the

depth

of

the

network

For

level

the

claim

holds

by

construction

Assuming

it

holds

for

wires

of

a

given

level

k

let

us

prove

it

holds

for

level

k

On

every

gate

where

two

's

meet

in

the

comparison

network

two

tokens

meet

in

the

balancing

network

so

one

leaves

on

each

wire

in

the

comparison

network

on

level

k

and

one

token

leaves

on

each

line

in

the

balancing

network

on

level

k

On

every

gate

where

two

's

meet

in

the

comparison

network

no

tokens

meet

in

the

balancing

network

so

a

leaves

on

each

level

k

wire

in

the

comparison

network

and

no

tokens

leave

in

the

balancing

network

On

every

gate

where

a

and

meet

in

the

comparison

network

the

leaves

on

the

lower

wire

and

the

on

the

upper

wire

on

level

k

while

in

the

balancing

network

the

token

leaves

on

the

lower

wire

and

no

token

leaves

on

the

upper

wire

If

the

balancing

network

is

a

counting

network

i.e.

it

has

the

step

property

on

its

output

level

wires

then

the

comparison

network

must

have

sorted

the

input

sequence

of

's

and

's

Corollary

The

depth

of

any

counting

network

is

at

least

-LRB-

log

n

-RRB-

Though

in

general

a

balancing

network

isomorphic

to

a

sorting

network

is

not

guaranteed

to

count

its

outputs

will

always

have

the

step

property

if

the

input

sequence

satisfies

the

following

smoothness

property

A

sequence

xw

is

smooth

if

for

all

i

j

jxi

xjj

This

observation

is

stated

formally

below

Theorem

If

a

balancing

network

is

isomorphic

to

a

sorting

network

and

its

input

sequence

is

smooth

then

its

output

sequence

in

any

quiescent

state

has

the

step

property

Proof

The

proof

follows

along

the

lines

of

Theorem

We

will

show

the

result

by

constructing

a

mapping

this

time

from

the

transitions

of

the

balancing

network

to

the

transitions

of

the

isomorphic

sorting

network

However

unlike

in

the

proof

of

Theorem

we

will

map

sets

of

transitions

of

the

balancing

network

to

single

transitions

of

the

isomorphic

sorting

network

We

do

this

by

considering

the

number

of

tokens

that

have

passed

along

each

wire

of

a

balancing

network

in

an

execution

ending

in

a

quiescent

state

From

this

perspective

the

transitions

of

a

balancer

gate

can

be

mapped

to

those

of

A

BITONIC

COUNTING

NETWORK

a

mathematical

device

that

receives

integers

and

-LRB-

numbers

of

tokens

-RRB-

and

outputs

integers

m

and

k

Given

that

the

input

sequence

to

the

balancing

network

is

smooth

there

is

a

quantity

x

such

that

each

input

wire

carries

either

x

or

x

tokens

By

simple

induction

on

the

depth

of

the

network

one

can

prove

that

the

inputs

and

outputs

of

any

balancer

in

a

network

with

x

or

x

tokens

on

each

input

wire

will

have

as

outputs

x

or

x

tokens

and

that

for

a

given

balancer

If

both

input

wires

have

x

tokens

then

both

outputs

will

have

x.

If

one

input

has

x

and

the

other

has

x

then

the

output

on

the

top

wire

will

be

x

tokens

and

on

the

bottom

wire

it

will

be

x

tokens

If

both

input

wires

have

x

tokens

then

both

output

wires

will

have

x

tokens

This

behavior

if

one

considers

x

and

x

as

integers

maps

precisely

to

that

of

comparators

of

numeric

values

in

a

comparison

network

Consequently

in

a

quiescent

state

of

a

balancing

network

isomorphic

to

a

sorting

network

if

the

network

as

a

whole

was

given

a

smooth

input

sequence

its

output

sequence

must

map

to

a

sorted

sequence

of

integers

x

and

x

implying

that

it

has

the

step

property

A

Bitonic

Counting

Network

Naturally

counting

networks

are

interesting

only

if

they

can

be

constructed

In

this

section

we

describe

how

to

construct

a

counting

network

whose

width

is

any

power

of

The

layout

of

this

network

is

isomorphic

to

Batcher

's

famous

Bitonic

sorting

network

-LSB-

-RSB-

though

its

behavior

and

correctness

arguments

are

completely

different

We

give

an

inductive

construction

as

this

will

later

aid

us

in

proving

its

correctness

Define

the

width

w

balancing

network

Merger

-LSB-

w

-RSB-

as

follows

It

has

two

sequences

of

inputs

of

length

w

x

and

and

a

single

sequence

of

outputs

y

of

length

w.

Merger

-LSB-

w

-RSB-

will

be

constructed

to

guarantee

that

in

a

quiescent

state

where

the

sequences

x

and

have

the

step

property

y

will

also

have

the

step

property

a

fact

which

will

be

proved

in

the

next

section

A

BITONIC

COUNTING

NETWORK

x

x

x

x

x

x

x

y

y

y

y

y

y

y

Merger

-LSB-

-RSB-

Merger

-LSB-

-RSB-

Merger

-LSB-

-RSB-

x

x

x

x

x

x

y

y

y

y

y

Merger

-LSB-

-RSB-

Figure

A

Merger

-LSB-

-RSB-

balancing

network

We

define

the

network

Merger

-LSB-

w

-RSB-

inductively

-LRB-

see

example

in

Figure

-RRB-

Since

w

is

a

power

of

we

will

repeatedly

use

the

notation

in

place

of

w

When

k

is

equal

to

the

Merger

-LSB-

-RSB-

network

consists

of

a

single

balancer

For

k

we

construct

the

Merger

-LSB-

-RSB-

network

with

input

sequences

x

and

from

two

Merger

-LSB-

k

-RSB-

networks

and

k

balancers

Using

a

Merger

-LSB-

k

-RSB-

network

we

merge

the

even

subsequence

xk

of

x

with

the

odd

subsequence

of

-LRB-

i.e.

the

sequence

xk

is

the

input

to

the

Merger

-LSB-

k

-RSB-

network

-RRB-

while

with

a

second

Merger

-LSB-

k

-RSB-

network

we

merge

the

odd

subsequence

of

x

with

the

even

subsequence

of

Call

the

outputs

of

these

two

Merger

-LSB-

k

-RSB-

networks

z

and

The

final

stage

of

the

network

combines

z

and

by

sending

each

pair

of

wires

zi

and

into

a

balancer

whose

outputs

yield

and

The

Merger

-LSB-

w

-RSB-

network

consists

of

log

w

layers

of

w

balancers

each

Merger

-LSB-

w

-RSB-

guarantees

the

step

property

on

its

outputs

only

when

its

inputs

also

have

the

step

property

but

we

can

ensure

this

property

by

filtering

these

inputs

through

smaller

counting

networks

We

define

Bitonic

-LSB-

w

-RSB-

to

be

the

network

constructed

by

passing

the

outputs

from

two

Bitonic

-LSB-

w

-RSB-

networks

into

a

Merger

-LSB-

w

-RSB-

network

where

the

induction

is

grounded

in

the

Bitonic

-LSB-

-RSB-

network

which

contains

no

balancers

and

simply

passes

its

input

directly

to

its

output

This

construction

gives

us

a

network

consisting

of

log

w

layers

each

consisting

of

w

balancers

A

BITONIC

COUNTING

NETWORK

Proof

of

Correctness

In

this

section

we

show

that

Bitonic

-LSB-

w

-RSB-

is

a

counting

network

Before

examining

the

network

itself

we

present

some

simple

lemmas

about

sequences

having

the

step

property

Lemma

If

a

sequence

has

the

step

property

then

so

do

all

its

subsequences

Lemma

If

xk

has

the

step

property

then

its

even

and

odd

subsequences

satisfy

k

X

i

k

X

i

xi

and

k

X

i

k

X

i

xi

Proof

Either

for

i

k

or

by

Lemma

there

exists

a

unique

j

such

that

and

for

all

i

j

i

k

In

the

first

case

P

Pxi

and

in

the

second

case

dPxi

and

bP

xi

Lemma

Let

xk

and

yk

be

arbitrary

sequences

having

the

step

property

If

Pk

i

xi

Pk

i

yi

then

xi

yi

for

all

i

k.

Proof

Let

m

Pxi

P

yi

By

Lemma

xi

yi

lm?ik

m

Lemma

Let

xk

and

yk

be

arbitrary

sequences

having

the

step

property

If

Pk

i

xi

Pk

i

yi

then

there

exists

a

unique

j

j

k

such

that

xj

yj

and

xi

yi

for

i

j

i

k.

Proof

Let

m

Pxi

P

yi

By

Lemma

xi

lm?ik

m

and

yi

lm

i

k

m

These

two

terms

agree

for

all

i

i

k

except

for

the

unique

i

such

that

i

m

-LRB-

mod

k

-RRB-

We

now

show

that

the

Merger

-LSB-

w

-RSB-

networks

preserves

the

step

property

Lemma

If

Merger

-LSB-

-RSB-

is

quiescent

and

its

inputs

xk

and

both

have

the

step

property

then

its

outputs

have

the

step

property

A

PERIODIC

COUNTING

NETWORK

Proof

We

argue

by

induction

on

log

k

If

Merger

-LSB-

-RSB-

is

just

a

balancer

so

its

outputs

are

guaranteed

to

have

the

step

property

by

the

definition

of

a

balancer

If

let

zk

be

the

outputs

of

the

first

Merger

-LSB-

k

-RSB-

subnetwork

which

merges

the

even

subsequence

of

x

with

the

odd

subsequence

of

and

let

be

the

outputs

of

the

second

Since

x

and

have

the

step

property

by

assumption

so

do

their

even

and

odd

subsequences

-LRB-

Lemma

-RRB-

and

hence

so

do

z

and

-LRB-

induction

hypothesis

-RRB-

Furthermore

P

zi

dPxi

and

P

bPxi

-LRB-

Lemma

-RRB-

A

straightforward

case

analysis

shows

that

P

zi

and

P

can

differ

by

at

most

We

claim

that

yi

yj

for

any

i

j

If

P

zi

P

then

Lemma

implies

that

zi

for

i

k

After

the

final

layer

of

balancers

yi

yj

zbi

zbj

and

the

result

follows

because

z

has

the

step

property

Similarly

if

P

zi

and

P

differ

by

one

Lemma

implies

that

zi

for

i

k

except

for

a

unique

such

that

z

and

differ

by

one

Let

max

-LRB-

z

-RRB-

x

and

min

-LRB-

z

-RRB-

x

for

some

non-negative

integer

x.

From

the

step

property

on

z

and

we

have

for

all

i

zi

x

and

for

all

i

zi

x

Since

z

and

are

joined

by

a

balancer

with

outputs

and

it

follows

that

x

and

x.

Similarly

zi

and

for

i

are

joined

by

the

same

balancer

Thus

for

any

i

x

and

for

any

i

x

The

step

property

follows

by

choosing

c

and

applying

Lemma

The

proof

of

the

following

theorem

is

now

immediate

Theorem

In

any

quiescent

state

the

outputs

of

Bitonic

-LSB-

w

-RSB-

have

the

step

property

A

Periodic

Counting

Network

In

this

section

we

show

that

the

bitonic

network

is

not

the

only

counting

network

with

depth

O

-LRB-

-RRB-

We

introduce

a

new

counting

network

with

the

A

PERIODIC

COUNTING

NETWORK

interesting

property

that

it

is

periodic

consisting

of

a

sequence

of

identical

subnetworks

Each

stage

of

this

periodic

network

is

interesting

in

its

own

right

since

it

can

be

used

to

achieve

barrier

synchronization

with

low

contention

This

counting

network

is

isomorphic

to

the

elegant

balanced

periodic

sorting

network

of

Dowd

Perl

Rudolph

and

Saks

-LSB-

-RSB-

However

its

behavior

and

therefore

also

our

proof

of

correctness

are

fundamentally

different

We

start

by

defining

chains

and

cochains

notions

taken

from

-LSB-

-RSB-

Given

a

sequence

x

fxiji

n

it

is

convenient

to

represent

each

index

-LRB-

subscript

-RRB-

as

a

binary

string

A

level

i

chain

of

x

is

a

subsequence

of

x

whose

indices

have

the

same

i

low-order

bits

For

example

the

subsequence

xE

of

entries

with

even

indices

is

a

level

chain

as

is

the

subsequence

xO

of

entries

with

odd

indices

The

A-cochain

of

x

denoted

xA

is

the

subsequence

whose

indices

have

the

two

low-order

bits

or

For

example

the

A-cochain

of

the

sequence

is

The

B-cochain

xB

is

the

subsequence

whose

low-order

bits

are

and

Define

the

network

Block

-LSB-

k

-RSB-

as

follows

When

k

is

equal

to

the

Block

-LSB-

k

-RSB-

network

consists

of

a

single

balancer

The

Block

-LSB-

-RSB-

network

for

larger

k

is

constructed

recursively

We

start

with

two

Block

-LSB-

k

-RSB-

networks

A

and

B.

Given

an

input

sequence

x

the

input

to

A

is

xA

and

the

input

to

B

is

xB

Let

y

be

the

output

sequence

for

the

two

subnetworks

where

yA

is

the

output

sequence

for

A

and

yB

the

output

sequence

for

B

The

final

stage

of

the

network

combines

each

yAi

and

yBi

in

a

single

balancer

yielding

final

outputs

and

Figure

describes

the

recursive

construction

of

a

Block

-LSB-

-RSB-

network

The

Periodic

-LSB-

-RSB-

network

consists

of

log

k

Block

-LSB-

-RSB-

networks

joined

so

that

the

ith

output

wire

of

one

is

the

ith

wire

of

the

next

Figure

is

a

Periodic

-LSB-

-RSB-

counting

network

This

recursive

construction

is

quite

different

from

the

one

used

by

Dowd

et

al.

We

chose

this

construction

because

it

yields

a

substantially

simpler

and

shorter

proof

of

correctness

Proof

of

Correctness

In

the

proof

we

use

the

technical

lemmas

about

input

and

output

sequences

presented

in

Section

The

following

lemma

will

serve

a

key

role

in

the

the

apparent

similarities

between

the

layouts

of

the

Block

and

Merger

networks

there

is

no

permutation

of

wires

that

yields

one

from

the

other

A

PERIODIC

COUNTING

NETWORK

inductive

proof

of

our

construction

Lemma

For

i

The

level

i

chain

of

x

is

a

level

i

chain

of

one

of

x

's

cochains

The

level

i

chain

of

a

cochain

of

x

is

a

level

i

chain

of

x.

Proof

Follows

immediately

from

the

definitions

of

chains

and

cochains

As

will

be

seen

the

price

of

modularity

is

redundancy

that

is

balancers

in

lower

level

blocks

will

be

applied

to

sub-sequences

that

already

have

the

desired

step

property

We

therefore

present

the

following

lemma

that

amounts

to

saying

that

applying

balancers

evenly

to

such

sequences

does

not

hurt

Lemma

If

x

and

are

sequences

each

having

the

step

property

and

pairs

xi

and

are

routed

through

a

balancer

yielding

outputs

yi

and

then

the

sequences

y

and

each

have

the

step

property

Proof

For

any

i

j

given

that

x

and

have

the

step

property

xi

xj

and

and

therefore

the

difference

between

any

two

wires

is

xi

-LRB-

xj

-RRB-

By

definition

for

any

i

yi

lxi

m

and

jxi

k

and

so

for

any

i

j

it

is

the

case

that

yi

yj

and

implying

the

step

property

To

prove

the

correctness

of

our

construction

for

Periodic

-LSB-

k

-RSB-

we

will

show

that

if

a

block

's

level

i

input

chains

have

the

step

property

then

so

do

its

level

i

output

chains

for

i

in

log

k

This

observation

implies

that

a

sequence

of

log

k

Block

-LSB-

k

-RSB-

networks

will

count

an

arbitrary

number

of

inputs

Lemma

Let

Block

-LSB-

-RSB-

be

quiescent

with

input

sequence

x

and

output

sequence

y

If

xE

and

xO

both

have

the

step

property

so

does

y.

Proof

We

argue

by

induction

on

log

k

The

proof

is

similar

to

that

of

Lemma

For

the

base

case

when

Block

-LSB-

-RSB-

is

just

a

balancer

so

its

outputs

are

guaranteed

to

have

the

step

property

by

the

definition

of

a

balancer

A

PERIODIC

COUNTING

NETWORK

x

x

x

x

x

x

x

y

y

y

y

y

y

y

Block

-LSB-

-RSB-

Block

-LSB-

-RSB-

Block

-LSB-

-RSB-

x

x

x

x

x

x

y

y

y

y

y

Block

-LSB-

-RSB-

Figure

A

Block

-LSB-

-RSB-

balancing

network

For

the

induction

step

assume

the

result

for

Block

-LSB-

k

-RSB-

and

consider

a

Block

-LSB-

-RSB-

Let

x

be

the

input

sequence

to

the

block

z

the

output

sequence

of

the

nested

blocks

A

and

B

and

y

the

block

's

final

output

sequence

The

inputs

to

A

are

the

level

chains

xEE

and

xOO

and

the

inputs

to

B

are

xEO

and

xOE

By

Lemma

each

of

these

is

a

level

chain

of

xA

or

xB

These

sequences

are

the

inputs

to

A

and

B

themselves

of

size

k

so

the

induction

hypothesis

implies

that

the

outputs

zA

and

zB

of

A

and

B

each

has

the

step

property

Lemma

implies

that

PxEE

i

PxEO

i

and

P

xOE

i

PxOO

i

It

follows

that

the

sum

of

A

's

inputs

PxEE

i

PxOO

i

and

the

sum

of

B

's

inputs

PxEO

i

PxOO

i

differ

by

at

most

Since

balancers

do

not

swallow

or

create

tokens

P

zA

and

P

zB

also

differ

by

at

most

If

they

are

equal

then

Lemma

implies

that

zAi

zBi

For

i

j

yi

yj

zAbi

zAbj

and

the

result

follows

because

zA

has

the

step

property

Similarly

if

P

zAi

and

P

zBi

differ

by

one

Lemma

implies

that

zAi

zBi

for

i

k

except

for

a

unique

such

that

zA

and

zB

differ

by

one

Let

max

-LRB-

zA

zB

-RRB-

x

and

min

-LRB-

zA

zB

-RRB-

x

for

some

non-negative

integer

x.

From

the

step

property

on

zA

and

zB

we

have

for

all

i

zAi

zBi

x

and

for

all

i

zAi

zBi

x

Since

zA

and

zB

are

joined

by

a

balancer

with

IMPLEMENTATION

AND

APPLICATIONS

outputs

and

it

follows

that

x

and

x.

Similarly

zAi

and

zBi

for

i

are

joined

by

the

same

balancer

Thus

for

any

i

x

and

for

any

i

x

The

step

property

follows

by

choosing

c

and

applying

Lemma

Theorem

Let

Block

-LSB-

-RSB-

be

quiescent

with

input

sequence

x

and

output

sequence

y

If

all

the

level

i

input

chains

to

a

block

have

the

step

property

then

so

do

all

the

level

i

output

chains

Proof

We

argue

by

induction

on

i.

Lemma

provides

the

base

case

when

i

is

For

the

induction

step

assume

the

result

for

chains

up

to

i

Let

x

be

the

input

sequence

to

the

block

z

the

output

sequence

of

the

nested

blocks

A

and

B

and

y

the

block

's

final

output

sequence

If

i

Lemma

implies

that

every

level

i

chain

of

x

is

entirely

contained

in

one

cochain

or

the

other

Each

level

i

chain

of

x

contained

in

xA

-LRB-

xB

-RRB-

is

a

level

i

chain

of

xA

-LRB-

xB

-RRB-

each

has

the

step

property

and

each

is

an

input

to

A

-LRB-

B

-RRB-

The

induction

hypothesis

applied

to

A

and

B

implies

that

the

level

i

chains

of

zA

and

zB

have

the

step

property

But

Lemma

implies

that

the

level

i

chains

of

zA

and

zB

are

the

level

i

chains

of

z.

By

Lemma

if

the

level

i

chains

of

z

have

the

step

property

so

do

the

level

i

chains

of

y.

By

Theorem

the

proof

of

Theorem

constitutes

a

simple

alternative

proof

that

the

balanced

periodic

comparison

network

of

-LSB-

-RSB-

is

a

sorting

network

Implementation

and

Applications

In

a

MIMD

shared-memory

architecture

a

balancer

can

be

represented

as

a

record

with

two

fields

toggle

is

a

boolean

value

that

alternates

between

and

and

next

is

a

array

of

pointers

to

successor

balancers

A

balancer

is

a

leaf

if

it

has

no

successors

A

process

shepherds

a

token

through

the

network

by

executing

the

procedure

shown

in

Figure

In

our

implementations

we

preassigned

processes

to

input

lines

so

that

they

were

evenly

distributed

Thus

a

given

process

always

started

shepherding

tokens

from

the

same

preassigned

line

It

toggles

the

balancer

's

state

and

visits

the

next

balancer

halting

when

it

reaches

a

leaf

The

network

's

wiring

IMPLEMENTATION

AND

APPLICATIONS

x

x

x

x

x

x

x

y

y

y

y

y

y

y

Periodic

-LSB-

-RSB-

Block

-LSB-

-RSB-

Block

-LSB-

-RSB-

Block

-LSB-

-RSB-

Figure

A

Periodic

-LSB-

-RSB-

counting

network

IMPLEMENTATION

AND

APPLICATIONS

balancer

-LSB-

toggle

boolean

next

array

-LSB-

-RSB-

of

ptr

to

balancer

-RSB-

traverse

-LRB-

b

balancer

-RRB-

loop

until

leaf

-LRB-

b

-RRB-

i

rmw

-LRB-

b.toggle

b.toggle

-RRB-

b

b.next

-LSB-

i

-RSB-

end

loop

end

traverse

Figure

Code

for

Traversing

a

Balancing

Network

information

can

be

cached

by

each

process

and

so

the

transition

time

of

a

balancer

will

be

almost

entirely

a

function

of

the

efficiency

of

the

toggle

implementation

Advancing

the

toggle

state

can

be

accomplished

either

by

a

short

critical

section

guarded

by

a

spin

or

by

a

read-modify-write

operation

-LRB-

rmw

for

short

-RRB-

if

the

hardware

supports

it

Note

that

all

values

are

bounded

We

illustrate

the

utility

of

counting

networks

by

constructing

highly

concurrent

implementations

of

three

common

data

structures

shared

counters

producer/consumer

buffers

and

barriers

In

Section

we

give

some

experimental

evidence

that

counting

network

implementations

have

higher

throughput

than

conventional

implementations

when

contention

is

sufficiently

high

Shared

Counter

A

shared

counter

-LSB-

-RSB-

is

a

data

structure

that

issues

consecutive

integers

in

response

to

increment

requests

More

formally

in

any

quiescent

state

in

which

m

increment

requests

have

been

received

the

values

to

m

have

been

issued

in

response

To

construct

the

counter

start

with

an

arbitrary

width-w

counting

network

Associate

an

integer

cell

ci

with

the

ith

output

wire

Initially

ci

holds

the

value

i

A

process

requests

a

number

by

traversing

the

counting

network

When

it

exits

the

network

on

wire

i

it

atomically

adds

w

to

the

value

of

ci

and

returns

ci

's

previous

value

Lemmas

and

imply

that

spin

lock

is

just

a

shared

boolean

flag

that

is

raised

and

lowered

by

at

most

one

processor

at

a

time

while

the

other

processors

wait

IMPLEMENTATION

AND

APPLICATIONS

Lemma

Let

x

be

the

largest

number

yet

returned

by

any

increment

request

on

the

counter

Let

R

be

the

set

of

numbers

less

than

x

which

have

not

been

issued

to

any

increment

request

Then

The

size

of

R

is

no

greater

than

the

number

of

operations

still

in

progress

If

y

R

then

y

x

wjRj

Each

number

in

R

will

be

returned

by

some

operation

in

time

d

c

where

d

is

the

depth

of

the

network

is

the

maximum

balancer

delay

and

c

is

the

maximum

time

to

update

a

cell

on

an

output

wire

Producer/Consumer

Buffer

A

producer/consumer

buffer

is

a

data

structure

in

which

items

inserted

by

a

pool

of

m

producer

processes

are

removed

by

a

pool

of

m

consumer

processes

The

buffer

algorithm

used

here

is

essentially

that

of

Gottlieb

Lubachevsky

and

Rudolph

-LSB-

-RSB-

The

buffer

is

a

w-element

array

buff

-LSB-

w

-RSB-

There

are

two

w-width

counting

networks

a

producer

network

and

a

consumer

network

A

producer

starts

by

traversing

the

producer

network

leaving

the

network

on

wire

i

It

then

atomically

inspects

buff

-LSB-

i

-RSB-

and

if

it

is

replaces

it

with

the

produced

item

If

that

position

is

full

then

the

producer

waits

for

the

item

to

be

consumed

-LRB-

or

returns

an

exception

-RRB-

Similarly

a

consumer

traverses

the

consumer

network

exits

on

wire

j

and

if

buff

-LSB-

j

-RSB-

holds

an

item

atomically

replaces

it

with

If

there

is

no

item

to

consume

the

consumer

waits

for

an

item

to

be

produced

-LRB-

or

returns

an

exception

-RRB-

Lemmas

and

imply

that

Lemma

Suppose

m

producers

and

consumers

have

entered

a

producer/consumer

buffer

built

out

of

counting

networks

of

depth

d.

Assume

that

the

time

to

update

each

buff

-LSB-

i

-RSB-

once

a

process

has

left

the

counting

network

is

negligible

Then

if

m

every

producer

leaves

the

network

in

time

d

Similarly

if

m

every

consumer

leaves

the

network

in

time

d

Barrier

Synchronization

A

barrier

is

a

data

structure

that

ensures

that

no

process

advances

beyond

a

particular

point

in

a

computation

until

all

processes

have

arrived

at

that

IMPLEMENTATION

AND

APPLICATIONS

point

Barriers

are

often

used

in

highly-concurrent

numerical

computations

to

divide

the

work

into

disjoint

phases

with

the

property

that

no

process

executes

phase

i

while

another

process

concurrently

executes

phase

i

A

simple

way

to

construct

an

n-process

barrier

is

by

exploiting

the

following

key

observation

Lemma

implies

that

as

soon

as

some

process

exits

with

value

n

the

last

phase

must

be

complete

since

the

other

n

processes

must

already

have

entered

the

network

We

present

a

stronger

result

one

does

not

need

a

full

counting

network

to

achieve

barrier

synchronization

A

threshold

network

of

width

w

is

a

balancing

network

with

input

sequence

xi

and

output

sequence

yi

such

that

the

following

holds

In

any

quiescent

state

yw

m

if

and

only

if

mw

Pxi

-LRB-

m

-RRB-

w.

Informally

a

threshold

network

can

detect

each

time

w

tokens

have

passed

through

it

A

counting

network

is

a

threshold

network

but

not

vice-versa

Both

the

Block

-LSB-

w

-RSB-

network

used

in

the

periodic

construction

and

the

Merger

-LSB-

w

-RSB-

network

used

in

the

bitonic

construction

are

threshold

networks

provided

the

input

sequence

satisfies

the

smoothness

property

Recall

that

a

sequence

xw

is

smooth

if

for

all

i

j

jxi

xjj

Every

sequence

with

the

step

property

is

smooth

but

not

vice-versa

The

following

two

lemmas

state

that

smoothness

is

stable

under

partitioning

into

subsequences

or

application

of

additional

balancers

Lemma

Any

subsequence

of

a

smooth

sequence

is

smooth

Lemma

If

the

input

sequence

to

a

balancing

network

is

smooth

so

is

the

output

sequence

Proof

Observe

that

if

the

inputs

to

a

balancer

differ

by

at

most

one

then

so

do

its

outputs

By

a

simple

induction

on

the

depth

of

the

network

the

output

sequence

from

the

balancers

at

any

level

of

a

balancing

network

with

a

smooth

input

sequence

is

a

permutation

of

its

input

sequence

hence

the

network

's

output

sequence

is

smooth

Theorem

If

the

input

sequence

to

Block

-LSB-

w

-RSB-

is

smooth

then

Block

-LSB-

w

-RSB-

is

a

threshold

network

IMPLEMENTATION

AND

APPLICATIONS

Proof

Let

xi

be

the

block

's

input

sequence

zi

the

output

sequence

of

nested

blocks

A

and

B

and

yi

the

block

's

output

sequence

We

first

show

that

if

yw

m

then

mw

Pxi

-LRB-

m

-RRB-

w

We

argue

by

induction

on

w

the

block

's

width

If

w

the

result

is

immediate

Assume

the

result

for

w

k

and

consider

Block

-LSB-

-RSB-

in

a

quiescent

state

where

m

Since

x

is

smooth

by

hypothesis

by

Lemma

so

are

z

and

y

Since

and

are

outputs

of

a

common

balancer

is

either

m

or

m

The

rest

is

a

case

analysis

If

m

then

m.

By

the

induction

hypothesis

and

Lemma

applied

to

A

and

B

mk

PxAi

-LRB-

m

-RRB-

k

and

mk

PxBi

-LRB-

m

-RRB-

k

and

therefore

PxAi

PxBi

-LRB-

m

-RRB-

k

If

m

then

one

of

zAi

and

zBi

is

m

and

the

other

is

m

Without

loss

of

generality

suppose

zAi

m

and

zBi

m.

By

the

induction

hypothesis

-LRB-

m

-RRB-

k

PxAi

-LRB-

m

-RRB-

k

and

mk

PxBi

-LRB-

m

-RRB-

k

Since

x

is

smooth

by

Lemma

xB

is

smooth

and

some

element

of

xB

must

be

equal

m

which

in

turn

implies

that

no

element

of

xA

exceeds

m

This

bound

implies

that

-LRB-

m

-RRB-

k

PxAi

It

follows

that

k

PxAi

PxBi

-LRB-

m

-RRB-

k

yielding

the

desired

result

We

now

show

that

if

mw

Pxi

-LRB-

m

-RRB-

w

then

yw

m

We

again

argue

by

induction

on

w

the

block

's

width

If

w

the

result

is

immediate

Assume

the

result

for

w

k

and

consider

Block

-LSB-

-RSB-

in

a

quiescent

state

where

Pxi

-LRB-

m

-RRB-

k

Since

x

is

smooth

by

Lemma

m

Furthermore

since

x

is

smooth

by

Lemma

either

mk

PxAi

-LRB-

m

-RRB-

k

and

mk

PxBi

-LRB-

m

-RRB-

k

or

vice

versa

which

by

the

induction

hypothesis

implies

that

zAk

zBk

It

follows

that

m

which

completes

our

claim

The

proof

that

the

Merger

-LSB-

w

-RSB-

network

is

also

a

threshold

network

if

its

inputs

are

smooth

is

omitted

because

it

is

almost

identical

to

that

of

Theorem

A

threshold

counter

is

constructed

by

associating

a

local

counter

ci

with

each

output

wire

i

just

as

in

the

counter

construction

We

construct

a

barrier

for

n

processes

where

n

mod

w

using

a

width-w

threshold

counter

The

construction

is

an

adaptation

of

the

sensereversing

barrier

construction

of

-LSB-

-RSB-

as

follows

Just

as

for

the

counter

construction

we

associate

a

local

counter

ci

with

each

output

wire

i.

Let

F

be

a

boolean

flag

initially

false

Let

a

process

's

phase

at

a

given

point

in

the

execution

of

the

barrier

algorithm

be

defined

as

initially

and

incremented

PERFORMANCE

by

every

time

the

process

begins

traversing

the

network

With

each

phase

the

algorithm

will

associate

a

sense

a

boolean

value

reflecting

the

phase

's

parity

true

for

the

first

phase

false

for

the

second

and

so

on

As

illustrated

in

Figure

the

token

for

process

P

after

a

phase

with

sense

s

enters

the

network

on

wire

P

mod

w

If

it

emerges

with

a

value

not

equal

to

n

mod

n

then

it

waits

until

F

agrees

with

s

before

starting

the

next

phase

If

it

emerges

with

value

n

mod

n

it

sets

F

to

s

and

starts

the

next

phase

As

an

aside

we

note

that

a

threshold

counter

implemented

from

a

Block

-LSB-

k

-RSB-

network

can

be

optimized

in

several

additional

ways

For

example

it

is

only

necessary

to

associate

a

local

counter

with

wire

w

and

that

counter

can

be

modulo

n

rather

than

unbounded

Moreover

all

balancers

that

are

not

on

a

path

from

some

input

wire

to

exit

wire

w

can

be

deleted

Theorem

If

P

exits

the

network

with

value

n

after

completing

phase

OE

then

every

other

process

has

completed

phase

OE

and

no

process

has

started

phase

OE

Proof

We

first

observe

that

the

input

to

Block

-LSB-

w

-RSB-

is

smooth

and

therefore

it

is

a

threshold

network

We

argue

by

induction

When

P

receives

value

v

n

at

the

end

of

the

first

phase

exactly

n

tokens

must

have

entered

Block

-LSB-

w

-RSB-

and

all

processes

must

therefore

have

completed

the

first

phase

Since

the

boolean

F

is

still

false

no

process

has

started

the

second

phase

Assume

the

result

for

phase

OE

If

Q

is

the

process

that

received

value

n

at

the

end

of

that

phase

then

exactly

OE

n

tokens

had

entered

the

network

when

Q

performed

the

reset

of

F

If

P

receives

value

v

n

at

the

end

of

phase

OE

then

exactly

-LRB-

OE

-RRB-

n

tokens

have

entered

the

network

implying

that

an

additional

n

tokens

have

entered

and

all

n

processes

have

finished

the

phase

No

process

will

start

the

next

phase

until

F

is

reset

Performance

Overview

In

this

section

we

analyze

counting

network

throughput

for

computations

in

which

tokens

are

eventually

spread

evenly

through

the

network

As

mentioned

before

to

ensure

that

tokens

are

evenly

spread

across

the

input

wires

PERFORMANCE

barrier

-LRB-

-RRB-

v

exit

wire

of

traverse

-LRB-

wire

P

mod

w

-RRB-

if

v

n

-LRB-

mod

w

-RRB-

then

F

s

else

wait

until

F

s

end

if

s

s

end

barrier

Figure

Barrier

Synchronization

Code

each

processor

could

be

assigned

a

fixed

input

wire

Alternatively

processors

could

choose

input

wires

at

random

The

network

saturation

S

at

a

given

time

is

defined

to

be

the

ratio

of

the

number

of

tokens

n

present

in

the

network

-LRB-

i.e.

the

number

of

processors

shepherding

tokens

through

it

-RRB-

to

the

number

of

balancers

If

tokens

are

spread

evenly

through

the

network

then

the

saturation

is

just

the

expected

number

of

tokens

at

each

balancer

For

the

Bitonic

and

Periodic

networks

S

wd

The

network

is

oversaturated

if

S

and

undersaturated

if

S

An

oversaturated

network

represents

a

full

pipeline

hence

its

throughput

is

dominated

by

the

per-balancer

contention

not

by

the

network

depth

If

a

balancer

with

S

tokens

makes

a

transition

in

time

-LRB-

S

-RRB-

then

approximately

w

tokens

emerge

from

the

network

every

-LRB-

S

-RRB-

time

units

yielding

a

throughput

of

w

-LRB-

S

-RRB-

is

an

increasing

function

whose

exact

form

depends

on

the

particular

architecture

but

similar

measures

of

degradation

have

been

observed

in

practice

to

grow

linearly

-LSB-

-RSB-

The

throughput

of

an

oversaturated

network

is

therefore

maximized

by

choosing

w

and

d

to

minimize

S

bringing

it

as

close

as

possible

to

The

throughput

of

an

undersaturated

network

is

dominated

by

the

network

depth

not

by

the

per-balancer

contention

since

the

network

pipeline

is

partially

empty

Every

S

time

units

w

tokens

leave

the

network

yielding

throughput

The

throughput

of

an

undersaturated

network

is

therefore

maximized

by

choosing

w

and

d

to

increase

S

bringing

it

as

close

as

possible

to

This

analysis

is

necessarily

approximate

but

it

is

supported

by

exper

PERFORMANCE

concurrency

-LRB-

num

of

proc

-RRB-

time

-LRB-

sec

-RRB-

Spin-lock

Bitonic

-LSB-

-RSB-

Bitonic

-LSB-

-RSB-

Bitonic

-LSB-

-RSB-

Figure

Bitonic

Shared

Counter

Implementations

PERFORMANCE

imental

evidence

In

the

remainder

of

this

section

we

present

the

results

of

timing

experiments

for

several

data

structures

implemented

using

counting

networks

As

a

control

we

compare

these

figures

to

those

produced

by

more

conventional

implementations

using

spin

locks

These

implementations

were

done

on

an

Encore

Multimax

using

Mul-T

-LSB-

-RSB-

a

parallel

dialect

of

Lisp

The

spin

lock

is

a

simple

test-and-test-and-set

loop

-LSB-

-RSB-

written

in

assembly

language

and

provided

by

the

Mul-T

run-time

system

In

our

implementations

each

balancer

is

protected

by

a

spin

lock

The

Shared

Counter

We

compare

seven

shared

counter

implementations

bitonic

and

periodic

counting

networks

of

widths

and

and

a

conventional

spin

lock

implementation

-LRB-

which

can

be

considered

a

degenerate

counting

network

of

width

-RRB-

For

each

network

we

measured

the

elapsed

time

necessary

for

a

-LRB-

approximately

a

million

-RRB-

tokens

to

traverse

the

network

controlling

the

level

of

concurrency

For

the

bitonic

network

the

network

has

balancers

the

network

has

balancers

and

the

network

has

balancers

In

Figure

the

horizontal

axis

represents

the

number

of

processes

executing

concurrently

When

concurrency

is

each

process

runs

to

completion

before

the

next

one

starts

The

number

of

concurrent

processes

increases

until

all

sixteen

processes

execute

concurrently

The

vertical

axis

represents

the

elapsed

time

-LRB-

in

seconds

-RRB-

until

all

tokens

had

traversed

the

network

With

no

concurrency

the

networks

are

heavily

undersaturated

and

the

spin

lock

's

throughput

is

the

highest

by

far

As

saturation

increases

however

so

does

the

throughput

for

each

of

the

networks

The

network

is

undersaturated

at

concurrency

levels

less

than

As

the

level

of

concurrency

increases

from

to

saturation

approaches

and

the

elapsed

time

decreases

Beyond

saturation

increases

beyond

and

the

elapsed

time

eventually

starts

to

grow

The

other

networks

remain

undersaturated

for

the

range

of

the

experiment

their

elapsed

times

continue

to

decrease

Each

of

the

networks

begins

to

outperform

the

spin

lock

at

concurrency

levels

between

and

When

concurrency

is

maximal

all

three

networks

have

throughputs

at

least

twice

the

spin

lock

's

Notice

that

as

the

level

of

concurrency

increases

the

spin

lock

's

performance

degrades

in

an

approximately

linear

fashion

-LRB-

because

of

increasing

contention

-RRB-

PERFORMANCE

concurrency

-LRB-

num

of

proc

-RRB-

time

-LRB-

sec

-RRB-

Spin-lock

Periodic

-LSB-

-RSB-

Periodic

-LSB-

-RSB-

Periodic

-LSB-

-RSB-

Figure

Periodic

Shared

Counter

Implementations

PERFORMANCE

spin

width

width

width

bitonic

periodic

Figure

Producer/Consumer

Buffer

Implementations

The

performance

of

the

periodic

network

-LRB-

Figure

-RRB-

is

similar

The

network

reaches

saturation

at

processes

its

throughput

then

declines

slightly

as

it

becomes

oversaturated

The

other

networks

remain

undersaturated

and

their

throughputs

continue

to

increase

Each

of

the

counting

networks

outperforms

the

spin

lock

at

sufficiently

high

levels

of

contention

At

processes

the

and

networks

have

almost

twice

the

throughput

of

the

single

spin-lock

implementation

Each

bitonic

network

has

a

slightly

higher

throughput

than

its

periodic

counterpart

Producer/Consumer

Buffers

We

compare

the

performance

of

several

producer/consumer

buffers

implemented

using

the

algorithm

of

Gottlieb

Lubachevsky

and

Rudolph

-LSB-

-RSB-

discussed

in

Section

Each

implementation

has

producer

processes

which

continually

produce

items

and

consumer

processes

which

continually

consume

items

If

a

producer

-LRB-

consumer

-RRB-

process

finds

its

buffer

slot

full

-LRB-

empty

-RRB-

it

spins

until

the

slot

becomes

empty

-LRB-

full

-RRB-

We

consider

buffers

with

bitonic

and

periodic

networks

of

width

and

As

a

final

control

we

tested

a

circular

buffer

protected

by

a

single

spin

lock

a

structure

that

permits

no

concurrency

between

producers

and

consumers

Figure

shows

the

time

in

seconds

needed

to

produce

and

consume

tokens

Not

surprisingly

the

single

spin-lock

implementation

is

much

slower

than

any

of

the

others

The

network

is

heavily

oversaturated

the

bitonic

network

is

slightly

oversaturated

while

the

others

are

undersaturated

VERIFYING

THAT

A

NETWORK

COUNTS

Spin

lock

Barrier

Barrier

Barrier

time

-LRB-

seconds

-RRB-

Figure

Barrier

Implementations

Barrier

Synchronization

Figure

shows

the

time

-LRB-

in

seconds

-RRB-

taken

by

processes

to

perform

barrier

synchronizations

The

remaining

columns

show

Block

-LSB-

k

-RSB-

networks

of

width

and

The

last

column

shows

a

simple

sense-reversing

barrier

in

which

the

Block

network

is

replaced

by

a

single

counter

protected

by

a

spin

lock

The

three

network

barriers

are

equally

fast

and

each

takes

about

two-thirds

the

time

of

the

spin-lock

implementation

Verifying

That

a

Network

Counts

The

law

states

that

a

comparison

network

is

a

sorting

network

if

-LRB-

and

only

if

-RRB-

it

sorts

input

sequences

consisting

entirely

of

zeroes

and

ones

a

property

that

greatly

simplifies

the

task

of

reasoning

about

sorting

networks

In

this

section

we

present

an

analogous

result

a

balancing

network

having

m

balancers

is

a

counting

network

if

-LRB-

and

only

if

-RRB-

it

satisfies

the

step

property

for

all

sequential

executions

in

which

up

to

tokens

have

traversed

the

network

This

result

simplifies

reasoning

about

counting

networks

since

it

is

not

necessary

to

consider

all

concurrent

executions

However

as

we

show

the

number

of

tokens

passed

through

the

network

in

the

longest

of

these

sequential

executions

can

not

be

less

than

exponential

in

the

network

depth

We

begin

by

proving

that

it

suffices

to

consider

only

sequential

executions

Lemma

Let

s

be

a

valid

schedule

of

a

given

balancing

network

Then

there

exists

a

valid

sequential

schedule

such

that

the

number

of

tokens

which

pass

through

each

balancer

in

s

and

is

equal

Proof

Let

s

p

q

where

are

sequences

of

transitions

p

and

q

are

individual

transitions

involving

distinct

tokens

P

and

Q

and

where

is

the

concatenation

operator

If

p

and

q

do

not

occur

at

the

same

balancer

VERIFYING

THAT

A

NETWORK

COUNTS

then

q

p

is

a

valid

schedule

If

p

and

q

do

occur

at

the

same

balancer

then

q

is

a

valid

schedule

where

is

constructed

from

by

swapping

the

identities

of

P

and

Q

In

each

case

we

can

swap

p

and

q

without

changing

the

preceding

sequence

of

transitions

and

without

changing

the

number

of

tokens

that

pass

through

any

balancer

during

the

execution

Now

suppose

that

s

is

a

complete

schedule

We

will

transform

it

into

a

sequential

schedule

by

a

process

similar

to

selection

sorting

Choose

some

total

ordering

of

the

tokens

in

s.

Split

s

into

where

is

the

empty

sequence

and

s

Now

repeatedly

carry

out

the

following

procedure

which

constructs

si

ti

from

si

ti

while

ti

is

nonempty

let

p

be

the

earliest

transition

in

ti

whose

token

is

ordered

as

less

than

or

equal

to

all

tokens

in

ti

Move

p

to

the

beginning

of

ti

by

swapping

it

with

each

earlier

token

in

ti

as

described

above

and

let

si

si

p

and

ti

be

the

suffix

of

the

resulting

schedule

after

p

This

procedure

is

easily

seen

to

maintain

the

following

invariant

After

stage

i

si

ti

is

a

valid

schedule

in

which

each

balancer

passes

the

same

number

of

tokens

as

in

s.

After

stage

i

si

is

sorted

by

token

Thus

when

the

procedure

terminates

we

have

a

valid

sequential

schedule

in

which

each

balancer

passes

the

same

number

of

tokens

as

in

s.

Theorem

A

balancing

network

with

m

balancers

satisfies

the

step

property

in

all

executions

if

-LRB-

and

only

if

-RRB-

it

satisfies

it

in

all

sequential

executions

in

which

at

most

tokens

traverse

the

network

Proof

Since

the

step

property

depends

only

on

the

number

of

tokens

that

pass

through

the

network

's

output

wires

it

follows

from

Lemma

that

a

balancing

network

satisfies

the

step

property

in

all

executions

if

-LRB-

and

only

if

-RRB-

it

satisfies

it

in

all

sequential

executions

We

now

show

that

any

failure

to

satisfy

the

step

property

can

be

detected

in

some

execution

involving

at

most

tokens

Consider

sequential

executions

of

a

balancing

network

with

m

balancers

Any

quiescent

state

is

characterized

by

specifying

for

each

balancer

the

output

wire

to

which

it

will

send

the

next

token

yielding

a

maximum

of

distinct

quiescent

states

In

a

sequential

execution

each

time

a

token

traverses

the

network

it

carries

VERIFYING

THAT

A

NETWORK

COUNTS

the

network

from

one

quiescent

state

to

another

Thus

in

any

execution

after

at

most

traversals

the

network

must

reenter

its

initial

state

Let

H

be

the

shortest

sequential

execution

needed

to

detect

a

violation

of

the

step

property

If

H

involves

more

than

tokens

then

H

can

be

split

into

a

prefix

and

a

suffix

such

that

involves

at

most

tokens

and

leaves

the

network

in

its

initial

state

If

sends

illegal

numbers

of

tokens

through

two

output

wires

then

alone

suffices

to

detect

the

violation

and

otherwise

alone

suffices

How

tight

is

this

bound

We

now

construct

a

balancing

network

that

is

not

a

counting

network

yet

satisfies

the

step

property

for

any

execution

in

which

the

number

of

tokens

is

less

than

exponential

in

the

network

depth

Through

the

remainder

of

this

section

we

will

only

consider

networks

in

quiescent

states

so

that

we

can

ignore

issues

of

timing

and

concentrate

solely

on

the

total

number

of

tokens

that

have

passed

along

each

wire

First

consider

the

following

balancing

network

Stage

-LSB-

-RSB-

Take

two

counting

networks

A

and

B

of

width

w

having

outputs

wires

through

aw

and

through

bw

respectively

Add

a

layer

of

w

balancers

such

that

the

i-th

balancer

has

inputs

ai

and

bw

i

and

outputs

and

i

The

resulting

network

Stage

-LSB-

-RSB-

is

not

a

counting

network

however

it

is

easily

extended

to

one

by

virtue

of

the

following

lemma

Lemma

For

any

input

to

Stage

-LSB-

-RSB-

there

exists

a

permutation

ssa

of

the

output

sequence

and

a

permutation

ssb

of

the

output

sequence

such

that

the

sequence

ssa

-LRB-

-RRB-

ssb

-LRB-

-RRB-

has

the

step

property

Proof

Observe

that

the

total

inputs

to

any

two

balancers

in

the

last

layer

differ

by

at

most

Thus

there

is

always

a

k

such

that

every

balancer

in

the

last

layer

outputs

either

k

or

k

tokens

If

k

is

even

then

k

for

all

i

and

ai

bw

i

k

which

is

either

k

or

k

One

can

obtain

a

sequence

with

the

step

property

by

setting

ssa

to

sort

the

values

in

If

k

is

odd

then

each

is

-LRB-

k

-RRB-

and

each

is

aw

i

bi

-LRB-

k

-RRB-

which

will

be

either

-LRB-

k

-RRB-

or

-LRB-

k

-RRB-

In

this

case

having

ssb

sort

the

values

in

produces

the

desired

result

By

Lemma

it

follows

that

VERIFYING

THAT

A

NETWORK

COUNTS

Corollary

For

any

m

tokens

input

to

Stage

-LSB-

-RSB-

Pw

i

Pw

i

dm

i

and

Pw

i

i

w

dm

i

In

other

words

the

total

number

of

tokens

that

end

up

on

the

and

outputs

wires

is

the

same

as

in

a

proper

counting

network

In

fact

Lemma

guarantees

an

even

stronger

property

the

actual

number

of

tokens

on

each

wire

correspond

to

the

number

of

tokens

that

occur

on

some

wire

in

the

output

sequence

of

a

proper

counting

network

However

there

is

no

guarantee

that

these

numbers

appear

in

the

correct

order

-LRB-

or

even

the

same

order

given

different

inputs

-RRB-

Because

of

Theorem

we

can

extend

the

Stage

-LSB-

-RSB-

network

into

a

-LRB-

not

very

efficient

-RRB-

counting

network

by

passing

the

outputs

and

to

two

separate

balancing

networks

isomorphic

to

sorting

networks

But

we

are

not

interested

in

getting

a

working

counting

network

instead

we

will

use

a

modified

version

of

Stage

-LSB-

-RSB-

to

construct

a

balancing

network

which

counts

all

input

sequences

with

up

to

some

bounded

number

of

tokens

but

fails

on

sequences

with

more

tokens

We

construct

such

a

balancing

network

-LRB-

denoted

Almost

-LSB-

-RSB-

-RRB-

as

follows

Take

a

Stage

-LSB-

-RSB-

network

and

modify

it

by

picking

some

x

other

than

or

w

and

deleting

the

final

balancer

between

ax

and

bw

x.

Denote

this

balancing

network

as

Stagex

-LSB-

-RSB-

Let

Almost

-LSB-

-RSB-

be

the

periodic

network

constructed

from

k

stages

for

some

k

each

a

Stagex

-LSB-

-RSB-

network

with

the

outputs

of

each

stage

connected

to

the

inputs

of

the

next

Let

At

and

Bt

be

the

sums

of

the

number

of

tokens

input

to

each

of

the

two

subnetworks

A

and

B

in

the

t-th

stage

of

Almost

-LSB-

-RSB-

and

are

thus

the

numbers

of

tokens

input

to

A

and

B

respectively

Let

y

be

the

sequence

given

by

yi

d

-LRB-

-RRB-

Thus

yi

counts

the

number

of

tokens

that

would

exit

on

output

wire

i

if

Almost

-LSB-

-RSB-

were

a

counting

network

We

now

define

the

quantities

and

used

in

the

proofs

below

They

measure

the

number

of

tokens

that

would

have

come

out

of

the

respective

parts

of

network

in

the

last

stage

-LRB-

t

-RRB-

if

it

were

a

counting

network

Formally

let

Pw

i

yi

and

i

w

yi

Note

that

At

Bt

for

all

t

and

that

by

Lemma

d

-LRB-

i

-RRB-

we

yi

and

d

-LRB-

i

-RRB-

we

yw

i

for

all

i.

Finally

let

the

imbalance

ffit

At

-LRB-

Bt

-RRB-

this

quantity

represents

how

far

the

network

is

from

balancing

the

tokens

between

the

VERIFYING

THAT

A

NETWORK

COUNTS

A

and

B

subnetworks

in

stage

t

in

other

words

how

many

excess

tokens

must

be

moved

from

the

A

part

of

the

network

to

the

B

part

-LRB-

or

if

the

quantity

is

negative

how

many

tokens

should

be

moved

from

B

to

A

-RRB-

The

following

lemma

follows

from

arguments

almost

identical

to

those

of

Lemma

Lemma

If

the

input

sequence

to

a

balancing

network

has

the

step

property

then

so

does

the

output

sequence

Lemma

In

the

output

sequence

of

stage

t

of

Almost

-LSB-

-RSB-

each

ai

is

equal

to

yi

ei

where

ei

when

ffit

and

ei

when

ffit

and

each

bi

is

equal

to

yw

i

ew

i

where

ei

when

ffit

and

ei

when

ffit

Proof

For

i

w

we

have

ei

ai

yi

d

-LRB-

At

i

-RRB-

we

d

-LRB-

i

-RRB-

we

d

-LRB-

ffit

i

-RRB-

we

d

-LRB-

i

-RRB-

we

which

is

at

least

zero

when

ffi

and

at

most

zero

when

ffi

The

claim

for

ew

i

bi

yw

i

follows

by

a

similar

argument

Corollary

If

ffit

then

the

output

sequences

of

stage

t

of

Almost

-LSB-

-RSB-

have

the

step

property

Proof

If

ffit

then

by

the

preceding

lemma

each

ai

yi

and

bi

yw

i

so

the

output

sequences

of

stage

t

form

the

sequence

y

Since

y

has

the

step

property

it

is

left

unchanged

by

the

final

layer

of

balancers

-LRB-

Lemma

-RRB-

Lemma

ffit

j

d

-LRB-

At?x

-RRB-

we?d

-LRB-

Bt

-LRB-

w

x

-RRB-

-RRB-

we

k

Proof

If

a

balancer

were

placed

between

and

x

after

stage

t

then

the

Stagex

-LSB-

-RSB-

network

would

become

a

Stage

-LSB-

-RSB-

counting

network

and

by

Corollary

exactly

tokens

would

emerge

from

the

A

half

of

the

network

after

stage

t

giving

an

imbalance

would

be

The

above

quantity

ffit

is

simply

the

number

of

tokens

that

this

balancer

would

move

from

the

A

part

of

the

network

to

the

B

part

in

order

to

bring

the

parts

into

balance

and

is

thus

the

actual

imbalance

that

results

from

deleting

the

balancer

VERIFYING

THAT

A

NETWORK

COUNTS

The

following

lemmas

show

that

the

imbalance

tends

toward

zero

as

more

stages

are

added

Lemma

If

ffit

then

ffit

If

ffit

then

ffit

Proof

Suppose

ffit

Then

At

and

Bt

and

so

ffit

d

-LRB-

At

x

-RRB-

we

d

-LRB-

Bt

-LRB-

w

x

-RRB-

-RRB-

we

d

-LRB-

x

-RRB-

we

d

-LRB-

-LRB-

w

x

-RRB-

-RRB-

we

-LRB-

The

last

equality

holds

because

when

the

two

parts

of

the

network

hold

and

tokens

there

is

no

imbalance

-RRB-

Reversing

the

inequalities

gives

the

corresponding

result

for

ffit

Lemma

If

jffitj

then

jffit

j

jffitj

Proof

By

virtue

of

Lemma

we

need

only

show

that

ffi

decreases

when

positive

and

increases

when

negative

Let

aw

bw

be

the

outputs

of

the

A

and

B

subnetworks

of

the

-LRB-

t

-RRB-

th

stage

before

the

last

layer

of

balancers

Because

ffit

this

sequence

does

not

have

the

step

property

however

each

of

the

two

subsequences

aw

and

bw

is

the

output

of

a

counting

network

and

so

has

the

step

property

Thus

the

step

property

of

the

whole

sequence

must

be

violated

by

some

ai

bj

such

that

ai

bj

is

either

less

than

or

greater

than

We

will

consider

two

cases

depending

on

the

sign

of

ffit

Case

ffit

Then

by

Lemma

each

ai

yi

and

each

bj

yw

j

-LRB-

Recall

that

yi

is

the

number

of

tokens

that

would

exit

from

the

i-th

output

of

a

counting

network

with

the

same

input

sequence

-RRB-

So

for

each

ai

and

each

bj

we

have

using

the

step

property

of

the

y

sequence

ai

yi

yw

j

bj

Thus

For

each

ai

and

bw

i

ai

bw

i

so

the

balancer

between

these

outputs

moves

no

tokens

from

the

A

side

to

the

B

side

VERIFYING

THAT

A

NETWORK

COUNTS

Given

some

ai

and

bj

that

violate

the

step

property

it

can

not

be

the

case

that

ai

bj

and

thus

it

must

be

the

case

that

ai

bj

But

then

aw

ai

bj

and

since

aw

and

are

connected

by

a

balancer

that

balancer

moves

at

least

one

token

from

the

B

side

to

the

A

side

Hence

at

least

one

token

moves

from

the

B

side

to

the

A

side

and

ffit

ffit

Case

ffit

Then

each

ai

yi

and

each

bi

yw

i

So

ai

yi

yw

bi

Thus

For

each

ai

and

bw

i

ai

bw

i

so

no

final-stage

balancer

moves

tokens

from

the

B

side

to

the

A

side

Given

some

ai

and

bj

that

violate

the

step

property

it

must

be

the

case

that

ai

bj

But

ai

bj

bw

so

the

balancer

between

and

bw

moves

at

least

one

token

from

the

A

side

to

the

B

side

Hence

at

least

one

token

moves

from

the

A

side

to

the

B

side

and

ffit

ffit

Lemma

ffit

ffit

w

c

where

c

Proof

From

Lemma

we

have

ffit

d

-LRB-

At

x

-RRB-

we

d

-LRB-

Bt

-LRB-

w

x

-RRB-

-RRB-

we

Looking

more

closely

at

the

Bt

term

notice

that

lB

-LRB-

w

x

-RRB-

w

m

lB

x

w

m

If

-LRB-

B

x

-RRB-

w

is

not

an

integer

then

this

is

just

jB

x

w

k

which

is

equal

to

jB

x

w

k

since

subtracting

from

the

numerator

can

not

bring

it

below

the

next

integral

multiple

of

w

Now

if

-LRB-

B

x

-RRB-

w

is

an

integer

then

this

is

jB

x

w

k

which

in

this

case

is

equal

to

jB

x

w

k

since

subtracting

from

the

numerator

does

bring

it

below

an

integral

multiple

of

w

So

in

either

case

we

have

lB

-LRB-

w

x

-RRB-

w

m

jB

x

w

k

and

we

can

rewrite

the

original

expression

as

VERIFYING

THAT

A

NETWORK

COUNTS

ffit

d

-LRB-

At

x

-RRB-

we

b

-LRB-

Bt

x

-RRB-

wc

-LRB-

At

x

-RRB-

w

-LRB-

Bt

x

-RRB-

w

At

Bt

x

w

-LRB-

-RRB-

x

w

where

and

Using

the

fact

that

w

-LRB-

hence

-LRB-

-RRB-

-RRB-

and

that

x

w

-LRB-

hence

x

w

-RRB-

we

can

rewrite

all

of

the

terms

not

containing

ffi

as

a

single

value

c

and

get

ffit

ffit

w

c

where

the

bound

c

is

obtained

by

summing

the

bounds

on

the

individual

terms

Theorem

Let

w

be

a

power

of

greater

than

Then

there

exists

a

balancing

network

that

has

the

step

property

in

all

executions

with

up

to

w

-LRB-

k

-RRB-

tokens

yet

is

not

a

counting

network

Proof

From

Lemma

we

have

jffit

j

jffitj

w

Let

U

-LRB-

t

-RRB-

be

defined

by

the

recurrence

U

-LRB-

-RRB-

U

-LRB-

t

-RRB-

U

-LRB-

t

-RRB-

w

then

U

-LRB-

t

-RRB-

is

a

strict

upper

bound

on

jffitj

for

t

Solving

the

recurrence

using

standard

methods

yields

U

-LRB-

t

-RRB-

-LRB-

-RRB-

w

-LRB-

-RRB-

w

w?t

Now

suppose

the

network

is

given

an

input

involving

at

most

wt

tokens

Then

can

not

possibly

exceed

wt

and

after

t

stages

jffitj

U

-LRB-

t

-RRB-

-LRB-

-RRB-

w

-LRB-

-RRB-

w

w?t

which

is

at

most

if

w

and

t

So

by

Lemma

jffit

j

and

thus

by

Corollary

the

outputs

of

stage

t

have

the

step

property

Thus

a

network

with

k

t

stages

will

count

up

to

w

-LRB-

k

-RRB-

tokens

To

see

that

this

k-stage

network

is

not

a

counting

network

suppose

-LRB-

k

-RRB-

From

Lemma

we

have

jffit

j

jffitj

w

Let

L

-LRB-

t

-RRB-

be

defined

by

L

-LRB-

-RRB-

and

L

-LRB-

t

-RRB-

L

-LRB-

t

-RRB-

w

L

-LRB-

t

-RRB-

is

a

strict

lower

bound

on

jffitj

DISCUSSION

for

t

Solving

the

recurrence

gives

L

-LRB-

t

-RRB-

-LRB-

-RRB-

w

-LRB-

-RRB-

w

w?t

Dropping

the

last

term

and

setting

-LRB-

k

-RRB-

gives

jffik

j

L

-LRB-

k

-RRB-

-LRB-

-RRB-

w

Since

ffik

the

outputs

of

stage

k

-LRB-

and

hence

the

entire

network

-RRB-

can

not

have

the

step

property

Discussion

Counting

networks

deserve

further

study

We

believe

that

they

represent

a

start

toward

a

general

theory

of

low-contention

data

structures

Work

is

needed

to

develop

other

primitives

to

derive

upper

and

lower

bounds

and

new

performance

measures

We

have

made

a

start

in

this

direction

by

deriving

constructions

and

lower

bounds

for

linearizable

counting

networks

-LSB-

-RSB-

networks

which

guarantee

that

the

values

assigned

to

tokens

reflect

the

realtime

order

of

their

traversals

Aharonson

and

Attiya

-LSB-

-RSB-

Felton

LaMarca

and

Ladner

-LSB-

-RSB-

and

Hardavellas

Karakos

and

Mavronicolas

-LSB-

-RSB-

have

investigated

the

structure

of

counting

networks

with

fan-in

greater

than

two

Klugerman

and

Plaxton

-LSB-

-RSB-

have

shown

an

explicit

network

construction

of

depth

O

-LRB-

c

log

n

log

n

-RRB-

for

some

small

constant

c

and

an

existential

proof

of

a

network

of

depth

O

-LRB-

log

n

-RRB-

Work

is

also

needed

in

experimental

directions

comparing

counting

networks

to

other

techniques

for

example

those

based

on

exponential

backoff

-LSB-

-RSB-

and

for

understanding

their

behavior

in

architectures

other

than

the

single-bus

architecture

provided

by

the

Encore

We

have

made

a

start

in

this

direction

by

comparing

the

performance

of

counting

networks

to

that

of

known

methods

using

the

ASIM

simulator

of

the

MIT

Alewife

machine

-LSB-

-RSB-

Preliminary

results

show

that

there

is

a

substantial

gain

in

performance

due

to

parallelism

on

such

distributed

memory

machines

Finally

we

point

out

that

smoothing

networks

balancing

networks

that

smooth

but

do

not

necessarily

count

are

interesting

in

their

own

right

since

they

can

be

used

as

hardware

solutions

to

problems

such

as

load

balancing

-LRB-

cf.

-LSB-

-RSB-

-RRB-

ACKNOWLEDGMENTS

Acknowledgments

Orli

Waarts

made

many

important

remarks

The

serialization

lemma

and

the

observation

that

smoothing

sorting

counting

are

products

of

our

cooperation

with

her

and

with

Eli

Gafni

to

whom

we

are

also

in

debt

Our

thanks

to

Heather

Woll

and

Shanghua

Teng

for

several

helpful

discussions

to

Cynthia

Dwork

for

her

comments

and

to

David

Kranz

and

Randy

Osborne

for

Mul-T

support

and

to

the

helpful

yet

anonymous

referees

Finally

the

first

and

third

authors

wish

to

thank

David

Michael

Herlihy

for

remaining

quiet

during

phone

calls

References

-LSB-

-RSB-

A.

Agarwal

and

M.

Cherian

Adaptive

Backoff

Synchronization

Techniques

Symposium

on

Computer

Architecture

June

-LSB-

-RSB-

A.

Agarwal

et

al.

The

MIT

Alewife

Machine

A

Large-Scale

DistributedMemory

Multiprocessor

In

Proceedings

of

Workshop

on

Scalable

Shared

Memory

Multiprocessors

Kluwer

Academic

Publishers

An

extended

version

of

this

paper

has

been

submitted

for

publication

and

appears

as

MIT/LCS

Memo

-LSB-

-RSB-

E.

Aharonson

and

H.

Attiya

Counting

Network

with

Arbitrary

FanOut

In

Symposium

on

Discrete

Algorithms

pages

-LCB-

ACM

SIAM

January

-LSB-

-RSB-

M.

Ajtai

J.

Komlos

and

E.

Szemeredi

An

O

-LRB-

n

log

n

-RRB-

sorting

network

In

Proceedings

of

the

ACM

Symposium

on

the

Theory

of

Computing

-LSB-

-RSB-

T.E.

Anderson

The

performance

implications

of

spin-waiting

alternatives

for

shared-memory

multiprocessors

Technical

Report

University

of

Washington

Seattle

WA

April

-LSB-

-RSB-

J.

Aspnes

M.P.

Herlihy

and

N.

Shavit

Counting

Networks

and

MultiProcessor

Coordination

In

Proceedings

of

the

Annual

Symposium

on

Theory

of

Computing

May

New

Orleans

Louisiana

REFERENCES

-LSB-

-RSB-

K.E.

Batcher

Sorting

networks

and

their

applications

In

Proceedings

of

AFIPS

Joint

Computer

Conference

-LSB-

-RSB-

T.H.

Cormen

C.E.

Leiserson

and

R.

L.

Rivest

Introduction

to

Algorithms

MIT

Press

Cambridge

MA

-LSB-

-RSB-

M.

Dowd

Y.

Perl

L.

Rudolph

and

M.

Saks

The

Periodic

Balanced

Sorting

Network

Journal

of

the

ACM

-LRB-

-RRB-

-LCB-

October

-LSB-

-RSB-

C.S.

Ellis

and

T.J.

Olson

Algorithms

for

parallel

memory

allocation

Journal

of

Parallel

Programming

-LRB-

-RRB-

-LCB-

August

-LSB-

-RSB-

E.W.

Felton

A.

LaMarca

and

R.

Ladner

Building

Counting

Networks

from

Larger

Balancers

Technical

Report

University

of

Washington

Seattle

WA

April

-LSB-

-RSB-

E.

Freudenthal

and

A.

Gottlieb

Process

Coordination

with

Fetch-andIncrement

In

Proceedings

of

the

International

Conference

on

Architecture

Support

for

Programming

Languages

and

Operating

Systems

April

Santa

Clara

California

-LSB-

-RSB-

D.

Gawlick

Processing

hot

spots

in

high

performance

systems

In

Proceedings

COMPCON

-LSB-

-RSB-

J.

Goodman

M.

Vernon

and

P.

Woest

A

set

of

efficient

synchronization

primitives

for

a

large-scale

shared-memory

multiprocessor

In

International

Conference

on

Architectural

Support

for

Programming

Languages

and

Operating

Systems

April

-LSB-

-RSB-

A.

Gottlieb

R.

Grishman

C.P.

Kruskal

K.P.

McAuliffe

L.

Rudolph

and

M.

Snir

The

NYU

ultracomputer

-LCB-

designing

an

mimd

parallel

computer

IEEE

Transactions

on

Computers

-LRB-

-RRB-

-LCB-

February

-LSB-

-RSB-

A.

Gottlieb

B.D.

Lubachevsky

and

L.

Rudolph

Basic

techniques

for

the

efficient

coordination

of

very

large

numbers

of

cooperating

sequential

processors

ACM

Transactions

on

Programming

Languages

and

Systems

-LRB-

-RRB-

-LCB-

April

REFERENCES

-LSB-

-RSB-

N.

Hardavellas

D.

Karakos

and

M.

Mavronicolas

Notes

on

Sorting

and

Counting

Networks

in

Proceedings

of

WDAG

to

appear

-LSB-

-RSB-

D.

Hensgen

and

R.Finkel

and

U.

Manber

Two

algorithms

for

barrier

synchronization

International

Journal

of

Parallel

Programming

-LRB-

-RRB-

-LSB-

-RSB-

M.P.

Herlihy

B.H.

Lim

and

N.

Shavit

Low

Contention

Load

Balancing

on

Large

Scale

Multiprocessors

In

Annual

ACM

Symposium

on

Parallel

Algorithms

and

Architectures

June

pp.

-LCB-

-LSB-

-RSB-

M.P.

Herlihy

N.

Shavit

and

O.

Waarts

Low-Contention

Linearizable

Counting

In

IEEE

Symposium

on

Foundations

of

Computer

Science

October

pp.

-LCB-

-LSB-

-RSB-

D.

Kranz

R.

Halstead

and

E.

Mohr

Mul-T

A

High-Performance

Parallel

Lisp

ACM

SIGPLAN

Conference

on

Programming

Language

Design

and

Implementation

Portland

OR

June

pp.

-LCB-

-LSB-

-RSB-

C.P.

Kruskal

L.

Rudolph

and

M.

Snir

Efficient

synchronization

on

multiprocessors

with

shared

memory

In

Fifth

ACM

SIGACT-SIGOPS

Symposium

on

Principles

of

Distributed

Computing

August

-LSB-

-RSB-

M.

Klugerman

and

C.G.

Plaxton

Small-depth

Counting

Networks

In

ACM

Symposium

on

the

Theory

of

Computing

-LSB-

-RSB-

N.A.

Lynch

and

M.R.

Tuttle

Hierarchical

Correctness

Proofs

for

Distributed

Algorithms

In

Sixth

ACM

SIGACT-SIGOPS

Symposium

on

Principles

of

Distributed

Computing

August

pp.

-LCB-

Full

version

available

as

MIT

Technical

Report

MIT/LCS/TR

-LCB-

-LSB-

-RSB-

J.M.

Mellor-Crummey

and

M.L.

Scott

Algorithms

for

scalable

synchronization

on

shared-memory

multiprocessors

Technical

Report

Technical

Report

University

of

Rochester

Rochester

NY

April

-LSB-

-RSB-

L.

Rudolph

Decentralized

cache

scheme

for

an

MIMD

parallel

processor

In

Annual

Computing

Architecture

Conference

pp

REFERENCES

-LSB-

-RSB-

J.M.

Mellor-Crummey

and

M.L.

Scott

Synchronization

without

Contention

In

Proceedings

of

the

International

Conference

on

Architecture

Support

for

Programming

Languages

and

Operating

Systems

April

Santa

Clara

California

-LSB-

-RSB-

D.

Peleg

and

E.

Upfal

The

token

distribution

problem

In

IEEE

Symposium

on

Foundations

of

Computer

Science

October

-LSB-

-RSB-

G.H.

Pfister

et

al.

The

IBM

research

parallel

processor

prototype

-LRB-

-RRB-

introduction

and

architecture

In

International

Conference

on

Parallel

Processing

-LSB-

-RSB-

G.H.

Pfister

and

A.

Norton

hot

spot

contention

and

combining

in

multistage

interconnection

networks

IEEE

Transactions

on

Computers

-LRB-

-RRB-

-LCB-

November

-LSB-

-RSB-

H.S.

Stone

Database

applications

of

the

fetch-and-add

instruction

IEEE

Transactions

on

Computers

-LRB-

-RRB-

-LCB-

July

-LSB-

-RSB-

U.

Vishkin

A

parallel-design

distributed-implementation

-LRB-

PDDI

-RRB-

general

purpose

computer

Theoretical

Computer

Science

-LCB-