Behavioral-Level

Synthesis

of

Heterogeneous

BISR

Reconfigurable

Lisa

Guerra

Miodrag

Potkonjak

and

Jan

Rabaey

University

of

California

Berkeley

EECS

Department

Berkeley

CA

University

of

California

Los

Angeles

CS

Department

Los

Angeles

CA

Abstract

Behavioral-level

synthesis

techniques

have

traditionally

focussed

on

design

of

a

fully-hardwired

application-specific

implementation

of

a

given

computation

In

this

paper

new

techniques

are

presented

for

the

synthesis

of

reconfigurable

hardware

The

technique

is

applicable

for

synthesis

of

several

classes

of

designs

including

-RRB-

design

for

fault

tolerance

against

permanent

faults

-RRB-

design

for

improved

manufacturability

and

-RRB-

design

of

Application

Specific

Programmable

Processors

-LRB-

ASPPs

-RRB-

processors

designed

to

perform

any

computation

from

a

specified

set

on

a

single

implementation

platform

This

paper

focuses

on

design

techniques

for

efficient

Built-InSelf-Repair

-LRB-

BISR

-RRB-

and

thus

directly

addresses

the

former

two

applications

Previous

BISR

techniques

have

been

based

on

replacing

a

failed

module

with

a

backup

of

the

same

type

We

present

new

heterogeneous

BISR

methodologies

which

remove

this

constraint

and

enable

replacement

of

a

module

with

a

spare

of

a

different

type

The

approach

is

based

on

the

flexibility

of

behavioral-level

synthesis

to

explore

the

design

space

Two

behavioral

synthesis

techniques

are

developed

the

first

method

is

through

assignment

and

scheduling

and

the

second

utilizes

transformations

Experimental

results

verify

the

effectiveness

of

the

approaches

In

particular

significant

yield

and

productivity

improvements

calculated

using

state-of-the

art

yield

modeling

techniques

show

the

power

of

these

techniques

for

improving

manufacturability

Preliminary

versions

of

this

work

appeared

in

the

Proc

IEEE/ACM

ICCAD

November

and

in

the

Proc

of

the

IEEE

International

Workshop

on

Defect

and

Fault

Tolerance

in

VLSI

Systems

October

Behavioral-Level

Synthesis

of

Heterogeneous

BISR

Reconfigurable

ASICs

Introduction

With

the

rising

cost

of

semiconductor

manufacturing

and

the

increasing

complexity

of

integrated

circuits

improvement

of

manufacturing

yields

is

crucial

for

achieving

economic

utilization

of

semiconductor

manufacturing

facilities

Fault

tolerance

techniques

such

as

the

Built-In-SelfRepair

-LRB-

BISR

-RRB-

sparing

methodology

will

play

an

important

role

in

achieving

yield

improvements

BISR

is

a

hybrid

redundancy

technique

in

which

a

set

of

spare

modules

are

provided

in

addition

to

the

core

operational

modules

-LSB-

-RSB-

If

an

implementation

is

found

to

have

defective

core

modules

these

modules

can

be

replaced

by

functional

spare

ones

before

packaging

BISR

methods

can

be

applied

not

only

for

yield

improvement

but

also

for

improvement

of

design

reliability

Designs

can

be

made

fault

tolerant

to

failures

occurring

during

operation

by

automatic

replacement

of

failed

modules

with

spare

ones

so

that

the

overall

system

can

continue

to

function

correctly

This

is

especially

important

in

military

systems

and

space

exploration

missions

-LSB-

-RSB-

where

it

is

critical

that

there

are

no

system

failures

or

where

manual

replacement

of

failed

modules

is

either

impossible

or

prohibitively

expensive

BISR

techniques

are

regularly

used

in

primary

and

secondary

memories

-LSB-

-RSB-

and

sometimes

in

general

purpose

bit-sliced

execution

units

-LSB-

-RSB-

While

they

have

hitherto

received

little

attention

in

application-specific

integrated

circuit

-LRB-

ASIC

-RRB-

design

the

ever

increasing

level

of

integration

should

soon

make

them

an

important

methodology

for

ASIC

yield

and

productivity

improvements

This

paper

introduces

a

novel

concept

of

Heterogeneous

BISR

for

ASIC

designs

As

opposed

to

traditional

BISR

where

a

failed

module

is

replaced

by

a

spare

of

the

same

type

we

propose

Heterogeneous

BISR

-LRB-

HBISR

-RRB-

which

enables

replacement

of

a

module

with

a

spare

of

a

different

type

HBISR

leverages

on

a

computation?s

flexibility

or

its

ability

to

be

implemented

in

a

number

of

competitive

ways

to

increase

productivity

and

fault

tolerance

In

addition

behaviorallevel

synthesis

techniques

for

exploiting

this

flexibility

in

automated

design

are

presented

One

method

is

through

assignment

and

scheduling

and

the

second

utilizes

transformations

The

paper

is

organized

in

the

following

way

After

a

survey

of

previous

works

and

discussion

of

several

design

preliminaries

simple

yet

real-life

examples

are

used

to

introduce

the

main

ideas

Next

new

behavioral-level

synthesis

algorithms

which

minimize

hardware

overhead

for

HBISR

during

resource

allocation

assignment

scheduling

and

transformations

are

discussed

The

paper

concludes

by

presenting

and

analyzing

experimental

results

on

a

variety

of

real-life

DSP

examples

and

briefly

outlining

extensions

and

directions

for

future

research

Behavioral-Level

Synthesis

of

Heterogeneous

BISR

Reconfigurable

ASICs

Previous

Work

The

main

target

for

BISR

techniques

are

systems

that

are

bit

byte

or

digit

sliced

By

far

the

most

important

use

of

bit-sliced

BISR

is

in

SRAM

and

DRAM

circuits

-LSB-

-RSB-

Almost

all

current

day

memory

designs

use

BISR

techniques

-LSB-

-RSB-

as

they

significantly

increase

memory

production

profitability

Programmable

logic

arrays

are

another

class

of

bit-sliced

devices

for

which

BISR

has

been

well

addressed

-LSB-

-RSB-

It

has

also

been

successfully

applied

for

arithmetic-logic

unit

byte

slices

-LSB-

-RSB-

Other

areas

in

which

BISR

techniques

are

being

used

include

secondary

storage

systems

-LSB-

-RSB-

massive

parallelism

-LSB-

-RSB-

wafer

scale

integration

-LSB-

-RSB-

and

systolic

array

designs

-LSB-

-RSB-

Note

that

BISR

methodology

is

not

limited

to

memory

and

execution

units

Lewis

for

example

proposed

the

use

of

a

backup

fault

tolerant

clock

-LSB-

-RSB-

While

all

previous

BISR

techniques

have

been

based

on

replacing

a

failed

module

with

a

backup

of

the

same

type

we

present

new

heterogeneous

BISR

methodologies

Additionally

we

present

synthesis

techniques

for

their

design

Behavioral-level

synthesis

provides

the

flexibility

of

design

space

exploration

so

that

a

variety

of

design

goals

can

be

addressed

An

overview

and

extensive

bibliography

of

behavioral-level

synthesis

algorithms

can

be

found

in

-LSB-

-RSB-

Most

of

these

works

target

the

optimization

of

area

and

speed

-LRB-

throughput

-RRB-

Recently

other

important

goals

such

as

power

-LSB-

-RSB-

testability

-LSB-

-RSB-

and

reliability

and

fault

tolerance

-LSB-

-RSB-

have

been

addressed

Little

work

has

been

reported

on

behavioral-level

synthesis

techniques

for

reliable

and

fault

tolerant

design

Raghavendra

and

Lursinsap

-LSB-

-RSB-

concentrated

on

designs

with

self

recovery

from

transient

faults

using

micro

roll-back

and

checkpoint

insertion

Karri

and

Orailoglu

presented

scheduling

and

assignment

and

transformation-based

methods

for

minimizing

hardware

overhead

while

achieving

a

certain

level

of

fault

tolerance

in

micro

roll-back

-LSB-

-RSB-

and

fault-secure

fault-tolerant

architectures

-LSB-

-RSB-

While

all

previous

behavioral-level

synthesis

methods

for

enhancing

fault

tolerance

have

addressed

intermittent

and

transient

faults

-LSB-

-RSB-

this

work

concentrates

on

permanent

faults

where

fault

tolerance

is

used

for

reliability

yield

and

productivity

enhancement

Issues

in

HBISR

Reconfigurable

Datapath

Design

Given

a

behavioral

description

of

the

algorithm

an

underlying

hardware

model

and

a

throughput

constraint

the

goal

is

to

synthesize

a

minimum

area

design

that

can

tolerate

a

number

of

faulty

hardware

resources

This

section

describes

our

targeted

application

and

computation

and

Behavioral-Level

Synthesis

of

Heterogeneous

BISR

Reconfigurable

ASICs

hardware

models

as

well

as

several

implementation

issues

in

the

design

of

reconfigurable

datapaths

for

HBISR

design

Computational

and

Hardware

Models

Targeted

applications

include

real-time

DSP

video

multi-media

and

other

numerically

intensive

algorithms

Applications

are

represented

as

hierarchical

data-control

flowgraphs

with

nodes

representing

the

flowgraph

operations

and

edges

the

data

and

control

dependencies

between

them

-LSB-

-RSB-

The

underlying

model

of

computation

is

the

homogeneous

synchronous

data

flow

model

of

-LSB-

-RSB-

The

ASIC

hardware

model

being

considered

is

shown

in

Figure

This

model

the

dedicated

register

model

clusters

all

registers

in

register

files

connected

only

to

the

inputs

of

the

corresponding

execution

units

-LSB-

-RSB-

We

also

assume

that

there

is

no

bus

merging

so

there

exists

a

dedicated

bus

connecting

any

two

units

between

which

there

are

data

transfers

Note

that

the

HBISR

methodology

itself

is

not

limited

to

this

hardware

model

generalizations

are

discussed

in

Section

Fault

Model

Detection

and

Diagnosis

At

the

gate

level

a

single

stuck-at

model

-LSB-

-RSB-

is

assumed

for

faults

and

at

the

register

transfer

level

we

assume

that

a

unit

is

faulty

if

it

has

one

or

more

gate

level

faults

Faults

can

occur

in

either

an

execution

unit

register

file

or

bus

Under

the

targeted

hardware

model

and

these

assumptions

all

faults

can

be

classified

as

execution

unit

faults

A

faulty

register

file

prevents

its

corresponding

execution

unit

from

receiving

data

and

thus

has

the

same

effect

as

a

fault

in

the

execution

unit

Similarly

a

faulty

bus

can

be

treated

as

a

failure

in

the

execution

unit

at

its

receiving

end

Note

again

that

the

HBISR

methodology

itself

is

general

and

can

be

easily

extended

to

other

fault

models

FIG.

Dedicated

Register

File

Hardware

Model

execution

unit

register

Behavioral-Level

Synthesis

of

Heterogeneous

BISR

Reconfigurable

ASICs

A

number

of

testing

approaches

are

available

to

detect

that

a

fault

exists

and

to

diagnose

its

location

If

BISR

is

used

to

improve

manufacturability

any

off-line

testing

and

diagnosis

scheme

can

be

used

-LRB-

i.e.

partial-scan

sequential

automatic

test

pattern

generation

-LRB-

ATPG

-RRB-

-LSB-

-RSB-

full-scan

and

combinational

ATPG

-LSB-

-RSB-

Built-In-Self-Test

-LRB-

BIST

-RRB-

-LSB-

-RSB-

and

insertion-point

based-schemes

-LSB-

-RSB-

-RRB-

Note

that

any

scheme

which

does

not

have

strong

diagnosis

capabilities

-LRB-

e.g.

IDDQ-based

testing

-LSB-

-RSB-

-RRB-

can

not

be

used

If

the

BISR

methodology

supports

in-field

reconfiguration

after

failure

of

particular

hardware

part

-LRB-

s

-RRB-

a

BIST

scheme

is

required

In

this

case

testing

capabilities

are

built-in

-LRB-

resulting

in

test-hardware

overhead

-RRB-

to

the

chip

itself

The

BIST

scheme

can

be

either

on-line

or

off-line

-LSB-

-RSB-

In

the

off-line

BIST

scheme

periodic

interruption

of

the

functional

mode

is

required

Controller

Implementation

Upon

diagnosis

of

a

fault

the

controller

is

reconfigured

Several

alternatives

for

efficient

low

overhead

controller

implementation

include

Programmable

Controller

-LSB-

-RSB-

While

this

type

of

controller

often

brings

a

somewhat

large

implementation

area

and

a

small

degradation

in

performance

it

provides

flexibility

not

only

for

HBISR

but

also

for

relatively

minor

alterations

in

the

chip

functionality

as

is

often

required

in

modern

day

designs

Off-chip

controller

This

controller

can

be

replaced

as

necessary

since

it

is

located

on

a

separate

chip

A

number

of

high

performance

datapath

intensive

chips

have

used

this

option

-LSB-

e.g.

-RSB-

The

same

drawbacks

and

advantage

as

in

the

previous

case

hold

Composed

controller

This

controller

is

located

on-chip

and

is

the

composition

of

all

possible

control

configurations

that

may

be

used

Its

effectiveness

depends

on

how

well

several

different

-LRB-

but

often

similar

-RRB-

controllers

can

be

merged

In

all

cases

we

assume

that

the

controller

itself

is

fault-free

This

assumption

can

be

easily

replaced

by

a

fault-tolerance

mechanism

which

provides

resiliency

of

the

controller

Since

the

controller

usually

occupies

a

very

small

fraction

of

chip

area

in

datapath-intensive

ASIC

designs

-LSB-

-RSB-

simple

replication

is

often

an

adequate

solution

While

interconnect

from

the

controller

to

the

datapath

usually

takes

a

somewhat

larger

percentage

of

the

area

in

absolute

terms

it

still

results

in

a

rather

small

overhead

Note

that

while

datapath

interconnect

usually

transfers

data

of

significant

word

lengths

each

control

interconnect

is

a

single

bit

Behavioral-Level

Synthesis

of

Heterogeneous

BISR

Reconfigurable

ASICs

Assignment

and

Scheduling

for

HBISR

Design

Key

Ideas

and

Motivational

Example

Probably

the

most

straightforward

approach

to

BISR

is

to

provide

a

spare

for

each

hardware

instance

resulting

in

full

duplication

of

the

hardware

With

the

detection

of

a

faulty

unit

reconfiguration

takes

place

to

initiate

use

of

its

spare

This

reconfiguration

is

conceptually

a

switch

that

passes

control

from

the

failed

to

the

backup

unit

Fortunately

the

BISR

overhead

need

not

be

so

high

If

the

number

of

faulty

units

K

is

for

example

the

behavioral-level

synthesis

assignment

step

provides

us

with

the

flexibility

under

which

it

is

clear

that

only

spare

for

each

hardware

class

is

necessary

as

opposed

to

one

spare

per

hardware

instance

The

operations

from

the

failed

unit

will

be

transferred

to

a

spare

of

the

same

type

The

flexibility

gained

through

assignment

clearly

reduces

the

amount

of

hardware

redundancy

needed

Considering

the

additional

flexibility

brought

by

scheduling

however

we

can

often

use

even

fewer

spares

This

is

possible

since

assignment

and

scheduling

enable

the

replacement

of

a

module

by

a

spare

of

a

different

type

When

a

failed

unit

is

detected

instead

of

reassigning

only

those

operations

of

the

failed

unit

we

completely

reassign

and

reschedule

all

operations

of

the

flowgraph

The

specific

goal

addressed

can

now

be

restated

as

follows

find

the

minimum

area

solution

which

meets

the

throughput

constraint

for

which

the

algorithm

can

be

reassigned

and

scheduled

even

when

as

many

as

K

units

are

faulty

The

main

ideas

are

illustrated

with

the

following

example

-LRB-

Figure

Table

-RRB-

where

the

goal

is

a

low-overhead

HBISR

implementation

that

can

tolerate

up

to

one

faulty

unit

The

example

includes

the

imaginary

part

of

a

complex

number

multiplication

with

a

constant

and

with

a

variable

-LRB-

multiplication

with

a

constant

is

such

that

it

can

be

done

using

a

single

shift

-RRB-

Assume

that

each

operation

takes

one

control

cycle

and

the

available

time

is

three

control

cycles

The

min

a

b

c

d

e

f

A

B

C

D

E

F

FIG.

Scheduling

and

assignment

for

HBISR

Imaginary

part

of

complex

multiplication

-LRB-

a

-RRB-

with

constant

multiplications

-LRB-

b

-RRB-

with

variable

multiplications

-LRB-

a

-RRB-

-LRB-

b

-RRB-

Behavioral-Level

Synthesis

of

Heterogeneous

BISR

Reconfigurable

ASICs

imum

hardware

required

for

non-BISR

implementation

consists

of

shifters

multiplier

and

adder

If

scheduling

flexibility

is

not

exploited

the

minimum

BISR

hardware

will

require

an

additional

unit

of

each

type

However

using

both

assignment

and

scheduling

only

shifters

multipliers

and

adders

are

needed

If

the

adder

fails

operations

A

and

B

are

done

on

the

shifters

in

step

D

and

E

on

the

multipliers

also

in

step

one

and

C

and

F

on

the

single

remaining

adder

in

steps

and

Table

shows

the

schedules

for

all

three

cases

of

failed

units

An

important

point

to

note

is

that

no

additional

shifters

are

needed

In

the

event

of

a

shifter

failure

the

scheduling

flexibility

brought

by

the

redundant

multiplier

is

exploited

Allocation

Assignment

and

Scheduling

Algorithm

The

global

strategy

of

the

Hyper

behavioral-level

synthesis

system

-LSB-

-RSB-

is

well

suited

for

use

as

the

starting

point

for

developing

new

algorithms

targeting

HBISR

In

this

system

allocation

first

proposes

a

hardware

solution

then

assignment

and

scheduling

are

performed

to

check

its

feasibility

To

take

into

account

BISR

requirements

it

was

necessary

to

develop

a

new

allocation

scheme

A

generic

assignment

and

scheduling

module

can

easily

be

modified

for

use

within

this

framework

We

have

used

the

Hyper

scheduler

and

assigner

with

small

modifications

Before

explaining

the

details

of

the

new

allocation

algorithm

several

definitions

are

presented

An

allocation

A

is

a

proposed

set

of

hardware

units

for

the

HBISR

realization

of

an

application

algorithm

For

a

given

K

there

are

many

possible

combinations

of

K

units

which

can

fail

Let

i

represent

one

such

failure

event

The

child

allocation

A

-LRB-

i

-RRB-

is

the

effective

allocation

of

hardware

-LRB-

allocation

of

good

units

-RRB-

for

the

failure

event

i.

Note

that

the

number

of

elements

is

equal

to

K

A

feasible

allocation

A

is

thus

one

for

which

successful

reassignment

and

scheduling

can

be

accomplished

for

all

of

its

child

allocations

A

-LRB-

i

-RRB-

The

basic

idea

of

the

allocation

mechanism

is

to

start

at

an

initial

allocation

add

hardware

until

a

feasible

allocation

is

found

then

remove

all

unnecessary

redundant

hardware

Note

that

for

Control

Step

Adder

Failure

Shifter

Failure

Multiplier

Failure

A

B

D

E

A

D

E

A

B

D

C

B

F

E

C

F

C

F

Table

Schedules

for

the

example

of

Fig.

to

be

used

when

an

adder

shifter

or

multiplier

fails

A

i

-LRB-

-RRB-

A

A

A

i

-LRB-

-RRB-

Behavioral-Level

Synthesis

of

Heterogeneous

BISR

Reconfigurable

ASICs

any

proposed

allocation

solution

it

is

necessary

to

assure

that

scheduling

can

succeed

with

any

combination

of

K

failed

units

The

basic

framework

for

the

allocation

algorithm

has

been

set

up

and

implemented

for

K

The

pseudo-code

for

the

global

flow

is

presented

below

The

key

components

of

the

algorithm

are

described

in

the

following

sections

Initial

Allocation

A

sharp

minimum

bound

Mj

on

the

necessary

amount

of

hardware

of

each

class

j

is

used

as

the

initial

allocation

Mj

is

defined

as

where

mj

is

a

minimum

bound

on

the

amount

of

hardware

j

necessary

for

any

non

fault-tolerant

implementation

and

K

is

the

number

of

faults

For

each

hardware

class

j

relaxed

based

scheduling

techniques

-LSB-

-RSB-

are

used

to

derive

an

estimate

of

mj

The

equation

for

Mj

can

be

understood

by

observing

that

any

implementation

requires

at

least

mj

units

and

since

up

to

K

units

of

type

j

can

be

bad

at

least

-LRB-

mj

K

-RRB-

units

are

needed

Expansion

Phase

If

the

initial

allocation

fails

the

allocation

expansion

phase

is

entered

where

new

hardware

units

are

added

-LRB-

AddHardware

routine

-RRB-

one

by

one

until

the

allocation

succeeds

Good

selection

heuristics

have

a

crucial

impact

on

the

speed

of

the

algorithm

and

the

quality

of

the

solution

Firstly

we

want

to

reach

the

solution

as

quickly

as

possible

avoiding

the

addition

of

unnecessary

units

along

the

way

Secondly

we

want

to

avoid

a

greedy

steepest

descent

type

algorithm

which

could

lead

to

many

suboptimal

solutions

Two

modes

of

addition

stress-based

addition

and

last

gasp

addition

have

been

constructed

Stress-based

addition

uses

a

measure

called

the

global

stress

of

a

hardware

resource

class

to

GetInitialAllocation

-LRB-

-RRB-

while

-LRB-

Success

-RRB-

-LCB-

SortInDecreasingOrderOfStress

-LRB-

-RRB-

foreach

j

-LCB-

Success

Assign

and

ScheduleWithFailedUnit

-LRB-

j

-RRB-

if

-LRB-

Success

-RRB-

break

-RCB-

UpdateStress

-LRB-

-RRB-

if

-LRB-

Success

-RRB-

-LCB-

AddHardware

-LRB-

-RRB-

-RCB-

-RCB-

RedundancyRemoval

-LRB-

-RRB-

M

j

m

j

K

Behavioral-Level

Synthesis

of

Heterogeneous

BISR

Reconfigurable

ASICs

decide

which

hardware

type

to

add

next

This

measure

is

described

in

Section

and

is

composed

of

several

heuristic

measures

of

the

difficulty

of

assignment

and

scheduling

of

each

hardware

class

The

larger

the

stress

the

more

likely

it

is

that

type

of

unit

is

the

cause

for

the

failure

of

the

assignment

and

scheduling

For

additional

robustness

we

have

also

added

a

last

gasp

addition

phase

similar

in

concept

but

not

technique

to

the

Last

Gasp

routine

of

Espresso

-LSB-

-RSB-

This

phase

is

entered

if

it

is

found

that

the

stress

measure

has

ceased

to

give

useful

feedback

During

last

gasp

addition

units

are

added

one

by

one

in

random

order

till

a

feasible

allocation

is

reached

In

practice

this

phase

is

rarely

entered

but

assures

a

solution

will

be

found

if

one

exists

Redundancy

Removal

At

the

completion

of

the

expansion

phase

there

is

no

guarantee

that

the

feasible

allocation

is

minimal

It

is

possible

that

a

subset

of

the

allocation

is

also

a

solution

To

assure

that

a

local

minimum

has

been

reached

it

is

necessary

to

assure

that

if

any

units

are

removed

from

the

current

solution

success

can

not

be

achieved

In

general

the

units

with

minimum

stress

are

tried

for

removal

first

It

is

also

imperative

however

to

incorporate

a

remember-and-look-ahead

technique

so

that

time

is

not

wasted

attempting

allocations

that

will

definitely

fail

The

idea

of

the

technique

is

to

remember

all

allocations

and

child

allocations

that

failed

and

to

use

this

information

whenever

considering

an

allocation

A

Before

attempting

A

a

look-ahead

to

its

child

allocations

will

determine

if

there

is

any

overlap

between

the

children

of

A

and

any

known

allocations

that

have

failed

More

formally

let

us

define

F

to

be

the

set

of

failed

child

allocations

Let

G

be

the

set

of

A

and

all

children

of

A

If

then

A

need

not

be

considered

as

a

possible

allocation

Suppose

for

example

that

the

proposed

solution

A

-LCB-

adders

subtracters

multipliers

-RCB-

failed

because

a

reassignment

and

scheduling

could

not

be

found

for

its

child

allocation

A

-LRB-

adder

-RRB-

-LCB-

adders

subtracters

multipliers

-RCB-

A

subtracter

was

added

and

the

new

allocation

A

-LCB-

adders

subtracters

multipliers

-RCB-

was

successful

At

this

point

the

removal

phase

is

entered

At

first

glance

knowing

that

A

-LCB-

adders

subtracters

multipliers

-RCB-

failed

and

that

A

-LCB-

adders

subtracters

multipliers

-RCB-

succeeded

it

is

not

clear

what

will

happen

with

A

-LCB-

adders

subtracters

multipliers

-RCB-

With

remember-and-look-ahead

however

we

can

immediately

dismiss

A

from

consideration

since

F

-LCB-

A

-LRB-

adder

-RRB-

-RCB-

G

-LCB-

A

A

-LRB-

subtracter

-RRB-

A

-LRB-

adder

-RRB-

A

-LRB-

multiplier

-RRB-

-RCB-

gives

since

A

-LRB-

subtracter

-RRB-

A

-LRB-

adder

-RRB-

A

A

G

F

f

G

F

f

Behavioral-Level

Synthesis

of

Heterogeneous

BISR

Reconfigurable

ASICs

Ordering

Mechanism

and

Stress

Functions

For

a

successful

allocation

a

feasible

schedule

for

each

child

allocation

must

be

found

We

thus

order

the

schedules

in

decreasing

order

of

difficulty

so

that

we

can

exit

as

fast

as

possible

in

the

event

that

there

is

an

insufficient

allocation

The

ordering

is

a

function

of

the

global

stress

so

that

schedules

for

the

failure

of

highly

stressed

units

are

tried

first

The

ordering

mechanism

as

well

as

several

other

portions

of

the

allocation

algorithm

rely

heavily

on

the

idea

of

stress

of

a

hardware

unit

In

the

remainder

of

this

section

three

intuitive

and

experimentally

verified

heuristics

for

the

stress

function

are

described

Minimum

bounds

stress

MB

By

experimental

observation

operations

of

type

j

whose

relaxed

scheduling

minimum

hardware

bound

-LRB-

R

-RRB-

is

close

to

its

absolute

minimum

hardware

bound

-LRB-

X

-RRB-

are

difficult

to

schedule

The

absolute

minimum

bound

-LSB-

-RSB-

for

hardware

type

j

is

where

NumNodesj

is

the

number

of

nodes

that

are

executed

on

hardware

of

type

j

durationj

is

the

clock

cycle

duration

of

the

hardware

AvailableTime

is

the

sample

period

in

clock

cycles

and

K

is

the

number

of

allowable

faulty

units

The

minimum

bounds

stress

for

hardware

type

j

is

-LRB-

EQ

-RRB-

The

absolute

minimum

bound

indicates

the

number

of

units

needed

assuming

that

the

flowgraph

structure

has

enough

parallelism

to

achieve

hardware

utilization

The

relaxed

scheduling

bounds

on

the

other

hand

take

the

graph

structure

and

some

data

precedences

into

account

giving

a

more

accurate

bound

Neither

of

the

bounds

take

into

account

constraints

such

as

conflicts

in

writing

to

register

files

and

neither

fully

honors

data

precedences

The

closer

these

two

bounds

are

the

smaller

the

hardware

slack

available

to

satisfy

these

constraints

and

thus

the

better

the

particular

unit

is

as

a

candidate

for

addition

e-critical

network

stress

C

If

a

high

percentage

of

the

nodes

of

a

particular

hardware

type

j

lie

in

the

e-critical

network

this

type

of

operation

is

likely

a

bottleneck

for

scheduling

and

its

hardware

is

thus

a

good

candidate

for

addition

The

e-critical

network

consists

of

all

operations

on

paths

which

have

lengths

within

a

small

e

percentage

of

the

critical

path

length

The

e-critical

network

stress

for

hardware

type

j

is

-LRB-

EQ

-RRB-

X

NumNodes

j

dura

t

i

on

j

-LRB-

-RRB-

Ava

i

l

ableT

i

me

-LRB-

-RRB-

K

MB

j

R

X

R

X

R

C

j

NumNodes

j

eNe

t

NumNodes

j

NumNodes

j

Behavioral-Level

Synthesis

of

Heterogeneous

BISR

Reconfigurable

ASICs

These

first

two

measures

take

into

account

various

elements

of

the

algorithm

specification

Both

deal

with

aspects

of

the

overall

structure

of

the

flowgraph

and

the

minimum

bounds

stress

also

accounts

for

the

user-specified

available

time

Since

they

capture

information

about

the

specification

and

the

initial

starting

allocation

they

are

most

valuable

in

the

beginning

of

the

allocation

addition

phase

We

therefore

heavily

weight

their

effect

to

be

greatest

in

the

beginning

and

to

quickly

diminish

as

hardware

is

added

Scheduling

stress

S

Unlike

the

previous

two

this

measure

changes

dynamically

with

the

allocation

It

is

calculated

during

the

assignment

and

scheduling

The

scheduling

difficulty

SD

-LRB-

k

-RRB-

is

calculated

for

each

operation

k

and

is

inversely

proportional

to

the

slack

time

between

the

As

Late

As

Possible

-LRB-

ALAP

-RRB-

scheduling

time

and

a

relaxed

As

Soon

As

Possible

-LRB-

ASAP

-RRB-

scheduling

time

-LSB-

-RSB-

This

value

is

summed

over

all

nodes

of

type

j

to

give

the

un-normalized

stress

-LRB-

EQ

-RRB-

Since

we

are

interested

in

the

minimum

area

solution

we

normalize

the

stress

value

by

the

hardware

cost

of

the

unit

giving

the

scheduling

stress

for

hardware

type

j

as

a

function

of

the

scheduling

difficulty

and

the

hardware

cost

-LRB-

EQ

-RRB-

where

cj

is

the

hardware

cost

-LRB-

area

-RRB-

of

an

execution

units

of

hardware

type

j.

Finally

we

define

the

global

stress

G

for

hardware

type

j

-LRB-

EQ

-RRB-

where

x

is

the

number

of

additional

units

added

and

b

is

an

empirical

parameter

determined

through

testing

to

be

equal

to

The

global

stress

is

a

functionally

weighted

function

of

the

heu

ristics

and

was

constructed

through

the

use

of

testing

and

statistical

validation

As

mentioned

above

since

MB

and

C

capture

information

about

the

starting

allocation

they

have

a

large

impact

stress

j

SD

k

-LRB-

-RRB-

k

Nodes

j

-LRB-

-RRB-

S

j

f

s

t

ress

j

c

j

-LRB-

-RRB-

s

t

ress

c

j

SD

k

-LRB-

-RRB-

k

Node

s

j

-LRB-

-RRB-

c

j

G

j

f

MB

j

C

j

S

j

-LRB-

-RRB-

S

j

MB

j

C

j

-LRB-

-RRB-

x

b

Behavioral-Level

Synthesis

of

Heterogeneous

BISR

Reconfigurable

ASICs

on

the

global

stress

function

in

the

early

stages

of

the

allocation

addition

phase

The

scheduling

stress

S

quickly

gains

dominance

as

units

are

added

Transformations

for

HBISR

Design

Transformations

are

alterations

in

the

computational

structure

such

that

the

behavior

-LRB-

the

relationship

between

output

and

input

data

-RRB-

is

maintained

Transformations

are

used

extensively

in

several

computer

science

computer

engineering

and

CAD

areas

most

often

in

compilers

-LSB-

-RSB-

and

behavioral-level

synthesis

-LSB-

-RSB-

This

section

shows

how

transformations

using

specifically

tailored

optimization

techniques

can

significantly

reduce

the

area

overhead

for

designs

with

BISR

requirements

Key

Ideas

and

Motivational

Examples

The

basic

idea

behind

using

transformations

in

behavioral-level

synthesis

for

HBISR

is

to

transform

the

computation

according

to

the

needs

imposed

by

the

available

hardware

for

each

possible

scenario

of

failed

units

The

simple

example

in

Figure

will

be

used

to

illustrate

this

idea

In

all

the

examples

in

this

section

assume

that

each

operation

takes

one

control

cycle

and

that

transformations

are

done

in

such

a

way

that

important

numerical

properties

-LRB-

e.g.

numerical

stability

and

overflow

control

-RRB-

are

maintained

in

the

transformed

designs

The

validity

of

the

assumptions

about

the

numerical

properties

of

the

transformed

designs

can

be

verified

using

fixed-point

simulation

tools

-LSB-

e.g.

-RSB-

The

assumed

available

time

for

the

first

example

is

two

control

cycles

The

identity

shown

in

Figure

is

used

to

transform

into

It

is

easy

to

verify

FIG.

Transformations

for

HBISR

using

associativity

and

the

inverse

element

law

the

HBISR

hardware

overhead

is

reduced

a

b

c

d

-LRB-

a

-RRB-

a

bc

d

-LRB-

b

-RRB-

-LRB-

a

b

-RRB-

-LRB-

c

d

-RRB-

-LRB-

a

c

-RRB-

-LRB-

b

d

-RRB-

Behavioral-Level

Synthesis

of

Heterogeneous

BISR

Reconfigurable

ASICs

that

both

algorithms

calculate

the

same

output

for

the

same

set

of

inputs

All

operations

lie

on

the

critical

path

so

it

is

not

possible

to

reduce

BISR

overhead

using

the

techniques

of

Section

In

this

case

however

transformations

can

help

to

reduce

the

overhead

If

we

consider

only

implementation

and

assume

that

any

unit

can

fail

then

adders

and

subtracters

are

needed

since

adders

and

subtracter

were

needed

for

the

non-BISR

implementation

However

if

we

consider

both

implementations

only

of

each

type

of

unit

are

needed

If

the

subtracter

fails

we

can

use

implementation

which

needs

adders

and

subtracter

and

when

the

adder

fails

we

can

use

implementation

which

needs

subtracters

and

adder

In

general

there

exists

a

large

variety

of

transformations

each

of

which

reduces

a

computation

in

different

ways

The

transformations

to

reduce

HBISR

overhead

can

be

grouped

into

two

classes

-LRB-

-RRB-

transformations

to

increase

the

resource

utilization

-LRB-

and

therefore

need

-RRB-

of

the

units

of

the

same

type

as

the

failed

execution

unit

and

-LRB-

-RRB-

transformations

to

reduce

the

number

of

operations

that

use

the

type

of

unit

that

failed

While

the

former

strategy

is

the

same

as

that

used

during

scheduling

the

latter

is

specific

to

transformations

Transformations

in

the

former

group

include

retiming

functional

pipelining

associativity

and

loop

permutation

while

those

in

the

latter

group

include

strength

reduction

-LRB-

substitution

of

multiplication

with

a

constant

by

shifts

and

additions

-RRB-

constant

propagation

dead

code

elimination

and

common

sub-expression

elimination

Some

transformations

can

even

be

used

for

both

strategies

simultaneously

-LRB-

e.g.

inverse

element

law

distributivity

loop

fusion

and

loop

blocking

-RRB-

The

remainder

of

this

section

illustrates

how

four

important

and

powerful

transformations

associativity

the

inverse

element

law

retiming

and

pipelining

can

be

used

for

transformationbased

HBISR

Although

it

is

not

explicitly

stated

it

is

implied

that

transformations

in

the

explanatory

examples

and

in

the

software

application

are

supported

by

the

commutativity

transformation

Figure

shows

the

application

of

associativity

for

HBISR

For

this

example

the

available

time

is

three

and

assignment

and

scheduling

flexibility

does

not

help

to

reduce

overhead

Notice

that

shift

A

on

Figure

and

multiplication

B

on

Figure

are

the

only

operations

which

are

not

on

the

critical

path

It

can

be

determined

that

the

minimum

non-BISR

hardware

configuration

for

Behavioral-Level

Synthesis

of

Heterogeneous

BISR

Reconfigurable

ASICs

the

computation

of

Figure

requires

adders

multipliers

and

shifter

Using

associativity

only

one

additional

adder

and

one

additional

shifter

are

needed

Table

shows

the

feasible

schedules

when

adders

multipliers

and

shifters

are

available

for

various

scenarios

of

unit

failures

When

a

shifter

fails

the

implementation

from

Figure

is

used

when

a

multiplier

or

adder

fail

the

implementation

of

Figure

is

used

-LRB-

actually

either

or

can

be

used

when

an

adder

fails

-RRB-

The

inverse

element

law

transformation

is

used

in

the

example

shown

in

Figure

For

an

available

time

of

two

the

non-BISR

design

can

be

implemented

with

adder

and

subtracter

As

in

the

previous

example

scheduling

and

assignment

can

not

enable

a

low

overhead

HBISR

implementation

-LRB-

of

only

one

additional

execution

unit

-RRB-

However

use

of

the

inverse

element

law

-LRB-

combined

with

the

enabling

transformations

of

distributivity

and

associativity

-RRB-

gives

two

identities

-LRB-

Figure

-RRB-

which

can

be

used

to

transform

into

Control

Step

Shifter

Failure

Multiplier

Failure

Adder

Failure

C

F

B

C

A

F

C

A

F

A

D

G

B

D

G

B

D

G

E

H

E

H

H

Table

Feasible

schedules

for

the

example

of

Fig.

Two

shifters

two

multipliers

and

two

adders

are

sufficient

for

HBISR

implementation

a

b

c

d

-LRB-

a

-RRB-

a

b

-LRB-

b

-RRB-

e

f

g

e

c

d

f

g

C

D

E

F

B

A

G

H

C

D

E

F

A

B

G

H

FIG.

Associativity

for

HBISR

-LRB-

a

-RRB-

before

and

-LRB-

b

-RRB-

after

application

of

associativity

Behavioral-Level

Synthesis

of

Heterogeneous

BISR

Reconfigurable

ASICs

By

using

this

transformation

just

two

subtracters

and

one

adder

are

sufficient

to

enable

the

implementation

of

the

required

functionality

regardless

of

which

unit

is

detected

as

faulty

If

one

of

subtracters

fails

the

structure

of

Figure

is

used

if

the

adder

fails

then

used

Note

that

it

is

sometimes

possible

to

totally

eliminate

the

need

for

a

particular

type

of

unit

The

computation

of

Figure

for

example

could

be

implemented

for

HBISR

using

only

three

subtracters

This

HBISR

scheme

is

not

preferred

however

since

a

subtracter

is

slightly

more

expensive

than

an

adder

Also

notice

that

this

particular

application

of

the

inverse

element

law

can

similarly

be

applied

to

pairs

of

multiplications

and

divisions

In

such

a

case

however

it

would

be

significantly

more

efficient

to

use

the

HBISR

scheme

which

uses

two

dividers

and

one

multiplier

instead

of

the

solution

where

three

dividers

are

used

Using

a

larger

set

of

transformations

-LRB-

to

include

algebraic

and

redundancy

manipulations

-RRB-

brings

more

options

for

the

trading

of

operations

For

example

can

be

implement

in

two

ways

either

as

or

as

In

this

identity

one

multiplication

can

be

traded

for

an

adder

Next

Figure

shows

how

retiming

can

be

used

for

HBISR

The

available

time

in

this

example

is

two

control

cycles

The

rectangles

in

Figures

-LRB-

and

-RRB-

denote

pipeline

delays

-LRB-

states

-RRB-

The

operation

following

the

delay

uses

data

produced

in

the

previous

iteration

by

the

operation

preceding

the

delay

Therefore

operations

which

have

direct

dependencies

only

with

respect

to

the

states

can

be

scheduled

in

the

first

control

step

Notice

once

again

that

all

the

operations

reside

on

the

critical

path

so

there

is

no

flexibility

during

scheduling

b

c

-LRB-

a

-RRB-

a

d

e

f

e

f

-LRB-

b

-RRB-

d

a

b

c

FIG.

Inverse

element

law

for

HBISR

a

-LRB-

b

c

-RRB-

-LRB-

a

b

-RRB-

c

f

-LRB-

d

e

-RRB-

d

-LRB-

e

f

-RRB-

x

x

-LRB-

-RRB-

y

y

-LRB-

-RRB-

x

y

-LRB-

-RRB-

x

y

-LRB-

-RRB-

Behavioral-Level

Synthesis

of

Heterogeneous

BISR

Reconfigurable

ASICs

Although

retiming

can

not

in

this

case

change

the

slacks

-LSB-

-RSB-

on

various

operations

it

can

reshuffle

the

operation

overlaps

This

redistribution

is

done

such

that

operations

competing

for

a

faulty

unit

are

no

longer

bound

to

happen

in

the

same

control

step

Analysis

of

the

various

schedules

shows

that

subtracters

adders

and

shifters

are

sufficient

for

HBISR

implementation

This

results

once

again

in

a

lower

overhead

than

that

achievable

using

only

assignment

and

scheduling

It

is

important

to

recognize

that

the

effectiveness

of

retiming

as

a

behavioral-level

synthesis

optimizing

transformation

is

often

strongly

constrained

by

the

underlying

structure

of

computation

Furthermore

many

widely

used

applications

have

no

algorithmic

delays

in

their

functional

description

and

therefore

retiming

can

not

be

applied

at

all

In

such

instances

pipelining

can

be

used

to

reduce

the

HBISR

overhead

cost

Functional

pipelining

-LSB-

-RSB-

with

n

stages

is

functionally

equivalent

to

the

procedure

of

first

adding

n

algorithmic

delays

on

each

primary

input

or

each

primary

output

then

applying

retiming

-LSB-

-RSB-

We

assume

that

the

number

of

pipeline

stages

is

fixed

and

indicated

by

the

amount

of

additional

latency

which

can

be

introduced

Figure

illustrates

how

pipelining

can

be

used

as

a

HBISR

transformation

It

is

assumed

that

due

to

a

latency

constraint

at

most

one

pipeline

stage

can

be

used

The

available

time

is

two

control

steps

The

non-BISR

implementation

requires

either

shifters

adder

and

multiplier

or

shifter

adders

and

multiplier

Using

the

structures

of

Figure

and

Figure

just

of

each

unit

are

necessary

for

HBISR

implementation

The

corresponding

schedules

are

shown

in

Table

c

d

g

e

f

h

b

b

c

d

g

e

f

h

-LRB-

b

-RRB-

-LRB-

a

-RRB-

FIG.

Retiming

for

HBISR

rearranging

ASAP

and

ALAP

times

-LSB-

-RSB-

so

that

operations

which

require

the

faulty

units

are

more

uniformly

distributed

over

the

available

time

D

D

D

Behavioral-Level

Synthesis

of

Heterogeneous

BISR

Reconfigurable

ASICs

The

algorithm

version

that

was

used

in

each

scenario

is

also

indicated

on

the

table

Pipelining

obviously

does

not

change

the

number

of

operations

and

thus

belongs

to

the

group

of

transformations

which

reduce

HBISR

overhead

by

redistributing

scheduling

freedom

of

the

various

types

of

operations

Control

Step

Adder

Failure

-LRB-

-RRB-

Shifter

Failure

-LRB-

-RRB-

Multiplier

Failure

-LRB-

-RRB-

C

A

D

A

B

C

A

B

D

E

B

E

C

D

E

Table

Schedules

for

the

example

of

Fig.

after

the

application

of

appropriate

pipelining

A

B

C

D

E

A

B

C

D

E

A

B

C

D

E

-LRB-

a

-RRB-

-LRB-

b

-RRB-

-LRB-

c

-RRB-

FIG.

Pipelining

for

HBISR

D

D

D

D

Behavioral-Level

Synthesis

of

Heterogeneous

BISR

Reconfigurable

ASICs

Optimization

Algorithm

The

transformation-based

HBISR

optimization

algorithm

is

given

by

the

following

pseudocode

The

initial

hardware

allocation

is

given

by

the

HBISR

allocation

algorithm

New

resources

are

added

until

a

transformed

and

feasibly

scheduled

version

of

the

computation

is

found

for

each

fault

unit

scenario

In

the

initial

phases

of

the

exploration

process

estimation

routines

based

on

relaxed

scheduling

-LSB-

-RSB-

are

used

in

place

of

scheduling

Only

when

estimates

indicate

that

a

complete

solution

is

potentially

found

is

the

scheduling

run

The

AddHardware

and

SelectMostCriticalResource

routines

add

resources

using

the

stress

functions

of

Section

in

determining

which

hardware

to

add

and

the

order

in

which

to

try

the

fault

scenarios

For

the

core

optimization

two

approaches

are

employed

a

probabilistic

sampling

algorithm

-LSB-

-RSB-

and

a

pipelining-based

algorithm

-LSB-

-RSB-

This

probabilistic

sampling

algorithm

applies

two

types

of

basic

moves

retiming

and

generalized

associativity

where

the

later

is

a

transformation

that

combines

associativity

inverse

element

law

and

commutativity

moves

The

algorithm

has

two

phases

The

first

phase

is

a

global

search

using

probabilistic

sampling

where

the

design

space

is

probabilistically

evaluated

to

detect

the

k

most

promising

starting

points

-LRB-

k

is

a

small

integer

number

which

is

a

function

of

the

number

of

nodes

in

the

computation

-RRB-

Note

that

starting

points

with

varying

numbers

of

operations

of

various

types

-LRB-

e.g.

subtraction

vs.

addition

-RRB-

are

generated

using

generalized

associativity

moves

which

include

the

inverse

element

law

The

second

local

optimization

phase

uses

the

basic

steepest

descent

approach

to

locally

maximize

these

starting

points

After

each

move

the

objective

function

is

evaluated

to

get

an

estimate

of

the

final

area

-LRB-

execution

units

interconnect

and

registers

-RRB-

expected

from

the

system

This

objective

function

is

composed

of

key

parts

all

of

which

are

strongly

correlated

to

the

final

area

the

critical

path

the

while

-LRB-

Done

-RRB-

-LCB-

for

-LRB-

i

-RRB-

-LCB-

resolved

-LRB-

i

-RRB-

NO

-RCB-

for

-LRB-

count

-RRB-

-LCB-

k

SelectMostCriticalResource

-LRB-

-RRB-

OptimizeUsingProbalisticSamplingWithFailedUnit

-LRB-

k

-RRB-

if

-LRB-

estimate

-LRB-

-RRB-

indicates

feasibility

-RRB-

-LCB-

resolved

-LRB-

k

-RRB-

YES

-RCB-

else

-LCB-

OptimizeUsingPipeliningWithFailedUnit

-LRB-

k

-RRB-

if

-LRB-

estimate

-LRB-

-RRB-

indicates

feasibility

-RRB-

-LCB-

resolved

-LRB-

k

-RRB-

YES

-RCB-

else

-LCB-

break

-RCB-

-RCB-

if

-LRB-

there

is

an

unresolved

resource

-RRB-

-LCB-

AddHardware

-LRB-

-RRB-

-RCB-

elseif

-LRB-

scheduling

-LRB-

-RRB-

feasible

-RRB-

-LCB-

AddHardware

-LRB-

-RRB-

-RCB-

else

-LCB-

Done

TRUE

-RCB-

-RCB-

Behavioral-Level

Synthesis

of

Heterogeneous

BISR

Reconfigurable

ASICs

number

of

delays

and

a

measure

of

the

expected

resource

utilization

of

each

hardware

type

-LRB-

the

overlap

component

-RRB-

During

the

local

phase

the

overlap

components

of

the

objective

function

are

normalized

by

the

available

number

of

resources

of

each

hardware

type

When

a

unit

is

in

short

supply

due

to

failure

the

overlap

component

for

the

resource

is

large

and

thus

the

algorithm

will

transform

the

graph

in

such

a

way

that

the

need

for

this

unit

is

alleviated

When

the

probabilistic

sampling

does

not

succeed

in

transforming

the

graph

for

successful

implementation

under

the

given

fault

scenario

a

pipelining-based

optimization

-LSB-

-RSB-

is

used

in

which

varying

number

of

pipeline

states

are

tried

Both

the

probabilistic

sampling

and

pipelining

algorithms

run

in

O

-LRB-

-RRB-

time

Since

the

number

of

required

hardware

resources

is

bounded

by

the

number

of

nodes

in

the

computation

the

worst-case

running

time

is

O

-LRB-

-RRB-

Experimental

studies

indicate

that

the

actual

run-time

is

quadratic

and

was

less

than

minutes

for

all

examples

on

a

Sun

Notice

that

both

classes

of

transformations

for

HBISR

are

utilized

-LRB-

-RRB-

transformations

to

increase

the

chance

for

high

utilization

-LRB-

and

therefore

reduced

need

-RRB-

of

the

units

of

the

same

type

as

the

failed

execution

unit

and

-LRB-

-RRB-

transformations

to

reduce

the

number

of

operations

of

a

failed

type

by

trading

operations

of

that

type

for

other

operations

Experimental

Results

The

HBISR

methodology

techniques

and

proposed

algorithms

were

validated

on

the

set

of

DSP

video

control

and

communication

examples

shown

in

Table

Supporting

tools

from

the

Hyper

behavioral-level

synthesis

system

-LSB-

-RSB-

were

used

for

other

synthesis

tasks

The

table

shows

all

relevant

data

for

the

standard

and

the

HBISR

synthesis

procedures

During

the

selection

of

benchmark

examples

special

attention

was

devoted

to

include

examples

with

a

variety

of

computational

structures

For

example

note

that

although

the

different

forms

of

the

order

low

pass

IIR

Avenhaus

filters

provide

the

same

functionality

they

have

drastically

different

structures

and

sizes

The

average

and

median

HBISR

design

area

overheads

were

and

respectively

Note

also

that

although

the

initial

implementations

of

all

examples

had

on

average

dif

Behavioral-Level

Synthesis

of

Heterogeneous

BISR

Reconfigurable

ASICs

ferent

types

of

hardware

units

an

average

of

only

additional

units

were

needed

for

the

HBISR

designs

a.

Examples

Jaumann

Jaumann

LDI

filter

Winograd

point

FFT

WDF

order

elliptical

wave

digital

filter

IIR

DFa

IIR

DFb

order

bandpass

IIR

direct

form

filter

for

two

different

set

of

timing

constraints

GMa

GMb

order

bandpass

IIR

filter

Gray

Markel

form

for

two

sets

of

timing

constraints

point

Winograd

Cyclic

Convolution

order

low

pass

IIR

filter

for

two

sets

of

timing

constraints

IIR

P

IIR

C

order

IIR

filter

parallel

and

cascade

form

DCT

dimensional

DCT

state

linear

controller

Wavelet

Wavelet

quadrature

mirror

filter

Nonlin

order

nonlinear

filter

and

Sort

and

Sort

fast

sorting

algorithms

for

and

numbers

respectively

Examplea

NonBISR

#Units

HBISR

#Units

Hardware

Classes

NonBISR

Area

-LRB-

-RRB-

HBISR

Area

-LRB-

-RRB-

Percentage

Area

Overhead

Jaumann

WDF

IIR

DFa

IIR

GMa

WConv

IIRa

IIR

GMb

IIR

P

IIR

C

DCT

IIR

IIRb

IIR

DFb

Wavelet

Nonlin

Sort

Sort

Table

Results

for

assignment

and

scheduling-based

HBISR

Behavioral-Level

Synthesis

of

Heterogeneous

BISR

Reconfigurable

ASICs

Table

shows

results

for

several

examples

designed

using

the

transformation-based

methods

of

HBISR

design

The

average

and

median

area

increases

are

only

and

respectively

The

examples

had

an

average

of

different

types

of

execution

units

but

an

average

of

only

additional

hardware

units

were

needed

While

the

HBISR

techniques

increase

the

yield

per

wafer

-LRB-

percentage

of

functional

die

-RRB-

the

area

overhead

reduces

the

number

of

wafer

per

die

Productivity

-LRB-

number

of

functional

dies

per

wafer

-RRB-

takes

both

of

these

effects

into

account

Productivity

improvement

can

thus

be

used

to

measure

the

effectiveness

of

the

HBISR

techniques

For

these

calculations

we

used

Stapper?s

yield

formula

-LSB-

-RSB-

which

calculates

the

probability

that

exactly

m

out

of

n

modules

operate

correctly

for

a

given

value

of

the

variability

parameter

m

and

single

module

yield

a.

Examples

FIR

order

high

pass

FIR

filter

IIR

order

low

pass

IIR

filter

FIR

order

Butterworth

Flat

Low

Pass

FIR

filter

FIR

order

multi-band

FIR

filer

IIR

order

IIR

Avenhaus

direct

form

II

filter

Lin

and

Lin

different

linear

controllers

tap

echo

canceller

and

Adapt

order

adaptive

filter

Examplea

NonBISR

#Units

HBISR

#Units

Hardware

Classes

NonBISR

Area

-LRB-

-RRB-

HBISR

Area

-LRB-

-RRB-

Percentage

Area

Overhead

FIR

IIR

FIR

FIR

IIR

Lin

Lin

Echo

Adapt

Table

Results

for

transformation-based

HBISR

Y

mn

n

m

m

i

m

i

Y

i

m

Y

-LRB-

-RRB-

n

m

m

j

Y

-LRB-

-RRB-

m

j

n

m

Behavioral-Level

Synthesis

of

Heterogeneous

BISR

Reconfigurable

ASICs

A

slight

modification

is

made

to

the

formula

to

take

into

account

units

of

largely

different

areas

This

model

is

based

on

the

combination

of

the

binomial

and

beta

distributions

for

faults

The

high

accuracy

of

this

model

has

been

demonstrated

on

a

variety

of

real-life

production

designs

Although

Stapper?s

procedures

primarily

target

BISR

memory

design

they

have

been

regularly

and

successfully

used

in

both

BISR

for

custom

-LSB-

-RSB-

and

programmable

-LSB-

-RSB-

datapath

analysis

Table

shows

the

yield

and

productivity

data

for

the

examples

designed

using

transformation-based

HBISR

A

initial

yield

is

assumed

for

designs

without

redundant

HBISR

circuitry

This

or

similar

values

were

also

assumed

in

-LSB-

-RSB-

The

relative

productivity

is

the

relative

yield

increase

divided

by

the

relative

area

increase

The

data

are

calculated

for

various

values

of

the

variability

parameter

m

This

parameter

gives

an

indication

of

the

assumed

probability

of

clustered

defects

the

most

common

sources

of

chip

malfunctions

Large

values

of

m

correspond

to

smaller

levels

of

clustering

and

therefore

lower

processing

variability

For

all

examples

including

those

of

Table

whose

yield

and

productivity

data

are

not

shown

here

a

significant

improvement

in

productivity

is

apparent

for

all

values

of

m.

Example

Percentage

Yield

Relative

Productivity

m

m

m

m

m

m

m

m

m

m

FIR

IIR

FIR

FIR

IIR

LIN

LIN

Echo

Adapt

Table

Yield

and

relative

productivity

for

transformation-based

HBISR

designs

for

various

values

of

the

variability

parameter

m

The

initial

yield

is

assumed

to

be

Behavioral-Level

Synthesis

of

Heterogeneous

BISR

Reconfigurable

ASICs

In

general

additional

multiplexers

add

extra

delays

which

can

affect

clock

cycle

time

and

throughput

-LRB-

if

they

are

on

the

critical

path

-RRB-

Another

important

consequence

of

the

low

hardware

overhead

of

HBISR

is

fewer

multiplexers

as

compared

to

alternate

fault-tolerance

techniques

Generalizing

the

HBISR

Methodology

Arbitrary

Hardware

Models

In

this

section

we

describe

how

the

HBISR

methodology

can

be

used

when

an

arbitrary

hardware

model

is

adopted

All

that

is

necessary

actually

is

to

first

propose

the

HBISR

implementation

and

then

check

whether

the

computation

can

be

correctly

implemented

on

all

subsets

of

the

implementation

where

hardware

primitives

-LRB-

execution

units

register

and

interconnects

-RRB-

of

the

model

are

removed

-LRB-

assumed

faulty

and

not

used

-RRB-

one

by

one

Note

that

even

in

relatively

small

designs

the

total

number

of

execution

units

interconnect

and

registers

is

usually

high

Therefore

while

an

arbitrary

model

offers

potential

for

further

hardware

reduction

and

an

attractive

conceptual

generalization

the

number

of

required

schedules

and

assignments

may

combinatorially

explode

Clearly

there

is

a

trade-off

between

potential

overhead

reduction

and

tractability

of

the

synthesis

algorithms

A

more

practical

HBISR

scheme

can

be

achieved

by

grouping

several

hardware

components

together

and

assuming

that

all

of

them

are

either

simultaneously

faulty

or

simultaneously

functional

This

is

actually

a

generalization

of

the

initial

proposed

dedicated

register

file

hardware

model

-LRB-

Figure

-RRB-

where

an

execution

unit

its

register

files

and

corresponding

interconnects

are

considered

as

simultaneously

susceptible

to

a

fault

Varying

Levels

of

Fault

Tolerance

Until

now

we

have

restricted

our

attention

to

the

case

when

the

number

of

failed

modules

K

is

equal

to

one

A

natural

question

to

ask

is

how

well

the

proposed

methodology

is

suited

to

address

higher

levels

of

fault

tolerance

In

general

as

K

is

increased

the

improvement

in

the

productivity

can

give

diminishing

returns

and

can

even

produce

lower

productivity

-LSB-

-RSB-

An

interesting

issue

for

HBISR

design

is

the

actual

selection

of

the

value

of

K

which

gives

the

optimal

effective

yield

as

a

trade-off

between

resilience

to

failure

and

hardware

overhead

Analysis

of

the

number

of

different

schedules

and

assignments

needed

for

high

levels

of

fault

tolerance

indicates

that

direct

application

of

the

methodology

is

most

likely

impractical

assuming

current

manufacturing

technologies

However

conceptually

simple

modifications

pro-

Behavioral-Level

Synthesis

of

Heterogeneous

BISR

Reconfigurable

ASICs

vide

a

convenient

way

to

achieve

our

goal

In

the

first

part

of

this

section

the

trends

in

the

implementation

complexity

of

the

generic

methodology

will

be

analyzed

Then

several

modifications

are

introduced

for

extending

the

behavioral-level

synthesis

techniques

to

efficiently

handle

large

values

of

K.

Suppose

that

we

have

targeted

an

ASIC

design

with

n

different

types

of

operations

and

that

we

want

an

implementation

that

can

tolerate

up

to

K

nonfunctional

units

The

number

of

different

schedules

and

assignments

needed

is

equal

to

the

number

of

combinations

of

K

elements

from

n

-LSB-

-RSB-

It

is

clear

that

the

required

number

of

schedules

and

assignments

grows

quickly

with

K

and

n.

For

example

a

fault

tolerance

to

failed

units

out

of

a

total

of

units

would

require

different

schedules

and

assignments

It

is

immediately

clear

that

for

larger

values

of

K

it

is

even

more

important

to

efficiently

use

the

look

ahead

and

remember

technique

and

to

terminate

unfeasible

allocations

as

early

as

possible

by

trying

them

early

in

the

search

process

Another

important

point

is

that

design

space

exploration

can

be

conducted

efficiently

by

employing

an

iterative

deepening

technique

by

testing

the

proposed

allocations

for

iteratively

increasing

values

of

K.

However

even

if

all

necessary

assignments

and

schedules

are

produced

in

a

reasonable

amount

of

time

important

implementation

details

-LRB-

e.g.

the

exponentially

growing

size

of

the

controller

or

the

number

of

different

programs

which

have

to

be

generated

and

stored

-RRB-

become

the

limiting

factor

In

this

situation

techniques

which

combine

the

scheme

when

only

assignment

flexibility

is

used

with

the

one

when

both

scheduling

and

assignment

flexibility

are

explored

provides

a

good

trade-off

between

complexity

and

efficiency

Several

such

schemes

can

be

envisioned

For

example

after

generating

the

solution

for

K

if

we

add

two

instances

of

each

type

of

execution

unit

with

the

corresponding

register

files

and

interconnect

as

required

for

the

assignment

only-based

BISR

we

have

a

design

which

is

fault

tolerant

against

as

many

as

four

faulty

units

Another

possibility

is

that

we

divide

all

execution

types

in

two

subsets

The

first

subset

of

execution

types

is

treated

using

the

assignment-only

BISR

scheme

while

the

second

subset

is

addressed

using

the

full-fledged

behavioral-level

synthesis

approach

In

this

scenario

it

is

apparently

advantageous

to

select

more

expensive

units

for

the

second

subset

n

K

Behavioral-Level

Synthesis

of

Heterogeneous

BISR

Reconfigurable

ASICs

Application-Specific

Programmable

Processor

-LRB-

ASPP

-RRB-

designs

The

HBISR

approach

as

demonstrated

can

be

used

for

ASIC

yield

improvement

or

lowhardware

overhead

fault-tolerance

against

permanent

faults

The

technique

is

directly

built

on

the

flexibility

provided

by

behavioral-level

synthesis

during

design

space

exploration

The

identification

and

the

techniques

for

exploiting

this

flexibility

however

are

in

themselves

important

Intelligent

strategies

to

use

the

flexibility

of

solutions

can

also

be

used

in

the

reconfigurable

datapath

design

of

Application

Specific

Programmable

Processors

-LRB-

ASPPs

-RRB-

An

ASSP

design

provides

an

efficient

implementation

for

a

set

of

different

applications

This

is

in

contrast

to

traditional

ASIC

designs

which

implement

a

single

application

Minimal

hardware

ASPP

implementation

is

achieved

most

often

by

identifying

a

set

of

implementations

for

individual

applications

which

are

not

necessarily

minimum

hardware

implementations

but

which

are

similar

in

terms

of

the

required

hardware

resources

Consider

for

example

the

design

of

an

ASPP

to

implement

the

two

different

computations

A

and

B.

Let

Ai

and

Bj

represent

particular

implementation

solutions

for

the

computations

A

and

B

where

and

are

the

total

number

of

possible

implementations

of

A

and

B

respectively

As

the

ASPP

implementation

must

be

able

to

implement

both

computations

its

hardware

is

the

union

of

the

hardware

for

any

i

and

j

The

goal

is

not

to

find

the

implementation

but

to

find

the

solution

which

in

many

instances

is

one

for

which

Ai

and

Bj

have

similar

hardware

implementations

The

techniques

introduced

in

this

paper

have

a

high

potential

to

facilitate

the

synthesis

of

ASPP

datapaths

due

to

their

ability

to

produce

a

great

variety

of

competitive

solutions

This

increases

the

likelihood

of

finding

the

solution

pair

-LRB-

Ai

Bj

-RRB-

for

which

both

Ai

and

Bj

have

a

small

implementation

cost

and

require

mainly

identical

resources

Conclusions

Behavioral-level

synthesis

of

datapaths

has

traditionally

concentrated

on

synthesizing

a

specific

implementation

for

a

given

computational

problem

New

techniques

have

been

presented

to

compose

a

reconfigurable

BISR

implementation

with

a

minimum

amount

of

area

overhead

BISR

is

an

efficient

yield

productivity

and

reliability

fault

tolerance

improvement

technique

which

will

continue

to

gain

importance

especially

with

the

increase

in

commercial

significance

of

massive

parallelism

We

have

presented

novel

synthesis

techniques

based

on

assignment

scheduling

and

transformations

which

support

a

new

Heterogeneous

BISR

methodology

for

ASIC

designs

These

methods

are

based

on

the

flexibility

of

the

design

solution

space

and

the

exploration

poten

i

j

A

i

B

j

Min

Ai

-LRB-

-RRB-

M

i

n

B

j

-LRB-

-RRB-

M

i

n

A

i

B

j

-LRB-

-RRB-

Behavioral-Level

Synthesis

of

Heterogeneous

BISR

Reconfigurable

ASICs

tial

of

behavioral-level

synthesis

processes

to

find

designs

where

resources

of

several

different

types

can

be

backed

up

with

the

same

unit

Future

issues

include

evaluating

the

effectiveness

of

alternate

hardware

models

and

varying

levels

of

fault

tolerance

and

investigating

the

role

of

other

system-level

and

behavioral-level

synthesis

tasks

-LRB-

e.g.

algorithm

selection

module

selection

and

partitioning

-RRB-

in

fault-tolerant

design

A

key

future

research

direction

involves

the

extension

of

techniques

to

exploit

algorithm

flexibility

for

new

applications

such

as

ASPP

design

Behavioral-level

synthesis

for

the

design

of

reconfigurable

datapath

structures

is

a

new

field

with

many

venues

of

research

still

remaining

to

be

explored

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behavioral-level synthesis
built-in-self repair
reconfigurable asic
transformational synthesis