@action(Seq(Rule("<STR_LIT>"), Opt(Seq(Loc("<STR_LIT>"), Tok("<STR_LIT>")))))<EOL><INDENT>def dotted_as_name(self, dotted_name, as_name_opt):<DEDENT>

asname_name = asname_loc = as_loc = None<EOL>dotted_name_loc, dotted_name_name = dotted_name<EOL>loc = dotted_name_loc<EOL>if as_name_opt:<EOL><INDENT>as_loc, asname = as_name_opt<EOL>asname_name = asname.value<EOL>asname_loc = asname.loc<EOL>loc = loc.join(asname.loc)<EOL><DEDENT>return ast.alias(name=dotted_name_name, asname=asname_name,<EOL>loc=loc, name_loc=dotted_name_loc, as_loc=as_loc, asname_loc=asname_loc)<EOL>


@action(Seq(*map(Loc, kinds)), loc=kwargs.get("<STR_LIT>", None))<EOL>def rule(parser, *tokens):<EOL><INDENT>return klass(loc=tokens[<NUM_LIT:0>].join(tokens[-<NUM_LIT:1>]))<EOL><DEDENT>return rule<EOL>

A rule that accepts a sequence of tokens of kinds ``kinds`` and returns
an instance of ``klass`` with ``loc`` encompassing the entire sequence
or None if the first token is not of ``kinds[0]``.


@action(Alt(Rule("<STR_LIT>"), Rule("<STR_LIT>"), Rule("<STR_LIT>"),<EOL>Rule("<STR_LIT>"), Rule("<STR_LIT>"), Rule("<STR_LIT>"),<EOL>Rule("<STR_LIT>"), Rule("<STR_LIT>")))<EOL><INDENT>def compound_stmt(self, stmt):<DEDENT>

return [stmt]<EOL>

compound_stmt: if_stmt | while_stmt | for_stmt | try_stmt | with_stmt |
                          funcdef | classdef | decorated


@action(Seq(Loc("<STR_LIT>"), Rule("<STR_LIT>")))<EOL><INDENT>def import_name(self, import_loc, names):<DEDENT>

return ast.Import(names=names,<EOL>keyword_loc=import_loc, loc=import_loc.join(names[-<NUM_LIT:1>].loc))<EOL>


@llrule(loc, lambda parser: [])<EOL>def rule(parser):<EOL><INDENT>return value<EOL><DEDENT>return rule<EOL>

A rule that accepts no tokens (epsilon) and returns ``value``.


@action(Seq(Loc("<STR_LIT:*>"), Rule("<STR_LIT>")))<EOL><INDENT>def star_expr__32(self, star_loc, expr):<DEDENT>

return ast.Starred(value=expr, ctx=None,<EOL>star_loc=star_loc, loc=expr.loc.join(star_loc))<EOL>


@llrule(loc, lambda parser: [])<EOL>def rule(parser):<EOL><INDENT>results = []<EOL>while True:<EOL><INDENT>data = parser._save()<EOL>result = inner_rule(parser)<EOL>if result is unmatched:<EOL><INDENT>parser._restore(data, rule=inner_rule)<EOL>return results<EOL><DEDENT>results.append(result)<EOL><DEDENT><DEDENT>return rule<EOL>

A rule that accepts a sequence of tokens satisfying ``inner_rule`` zero or more times,
and returns the returned values in a :class:`list`.


return ast.Break(loc=stmt_loc, keyword_loc=stmt_loc)<EOL>


@action(Seq(Loc("<STR_LIT>"), Loc("<STR_LIT::>"), Rule("<STR_LIT>"), Alt(try_stmt_1, try_stmt_2)))<EOL><INDENT>def try_stmt(self, try_loc, try_colon_loc, body, stmt):<DEDENT>

stmt.keyword_loc, stmt.try_colon_loc, stmt.body =try_loc, try_colon_loc, body<EOL>stmt.loc = stmt.loc.join(try_loc)<EOL>return stmt<EOL>

try_stmt: ('try' ':' suite
           ((except_clause ':' suite)+
            ['else' ':' suite]
            ['finally' ':' suite] |
            'finally' ':' suite))


@action(Rule("<STR_LIT>"))<EOL><INDENT>def comparison(self, lhs, rhs):<DEDENT>

if len(rhs) > <NUM_LIT:0>:<EOL><INDENT>return ast.Compare(left=lhs, ops=list(map(lambda x: x[<NUM_LIT:0>], rhs)),<EOL>comparators=list(map(lambda x: x[<NUM_LIT:1>], rhs)),<EOL>loc=lhs.loc.join(rhs[-<NUM_LIT:1>][<NUM_LIT:1>].loc))<EOL><DEDENT>else:<EOL><INDENT>return lhs<EOL><DEDENT>

(2.6, 2.7) comparison: expr (comp_op expr)*
(3.0, 3.1) comparison: star_expr (comp_op star_expr)*
(3.2-) comparison: expr (comp_op expr)*


if len(self.queue) == <NUM_LIT:0>:<EOL><INDENT>self._refill(eof_token)<EOL><DEDENT>return self.queue.pop(<NUM_LIT:0>)<EOL>

Returns token at ``offset`` as a :class:`Token` and advances ``offset``
to point past the end of the token, where the token has:

- *range* which is a :class:`pythonparser.source.Range` that includes
  the token but not surrounding whitespace,
- *kind* which is a string containing one of Python keywords or operators,
  ``newline``, ``float``, ``int``, ``complex``, ``strbegin``,
  ``strdata``, ``strend``, ``ident``, ``indent``, ``dedent`` or ``eof``
  (if ``eof_token`` is True).
- *value* which is the flags as lowercase string if *kind* is ``strbegin``,
  the string contents if *kind* is ``strdata``,
  the numeric value if *kind* is ``float``, ``int`` or ``complex``,
  the identifier if *kind* is ``ident`` and ``None`` in any other case.

:param eof_token: if true, will return a token with kind ``eof``
    when the input is exhausted; if false, will raise ``StopIteration``.


self._sort()<EOL>self._check()<EOL>rewritten, pos = [], <NUM_LIT:0><EOL>for range, replacement in self.ranges:<EOL><INDENT>rewritten.append(self.buffer.source[pos:range.begin_pos])<EOL>rewritten.append(replacement)<EOL>pos = range.end_pos<EOL><DEDENT>rewritten.append(self.buffer.source[pos:])<EOL>return Buffer("<STR_LIT>".join(rewritten), self.buffer.name, self.buffer.first_line)<EOL>

Return the rewritten source. May raise :class:`RewriterConflict`.


line, column = self.source_buffer.decompose_position(self.begin_pos)<EOL>return line<EOL>

Returns the line number of the beginning of this range.


if self.source_buffer != other.source_buffer:<EOL><INDENT>raise ValueError<EOL><DEDENT>if self.expanded_from == other.expanded_from:<EOL><INDENT>expanded_from = self.expanded_from<EOL><DEDENT>else:<EOL><INDENT>expanded_from = None<EOL><DEDENT>return Range(self.source_buffer,<EOL>min(self.begin_pos, other.begin_pos),<EOL>max(self.end_pos, other.end_pos),<EOL>expanded_from=expanded_from)<EOL>

Returns the smallest possible range spanning both this range and other.
Raises :exc:`ValueError` if the ranges do not belong to the same
:class:`Buffer`.


self.replace(range.end(), text)<EOL>


return "<STR_LIT>" %(self.source_buffer.name, self.begin_pos, self.end_pos, repr(self.expanded_from))<EOL>

Returns a human-readable representation of this range.


line_begins = self._extract_line_begins()<EOL>lineno = lineno - self.first_line<EOL>if lineno >= <NUM_LIT:0> and lineno + <NUM_LIT:1> < len(line_begins):<EOL><INDENT>first, last = line_begins[lineno:lineno + <NUM_LIT:2>]<EOL>return self.source[first:last]<EOL><DEDENT>elif lineno >= <NUM_LIT:0> and lineno < len(line_begins):<EOL><INDENT>return self.source[line_begins[-<NUM_LIT:1>]:]<EOL><DEDENT>else:<EOL><INDENT>raise IndexError<EOL><DEDENT>

Returns line ``lineno`` from source, taking ``first_line`` into account,
or raises :exc:`IndexError` if ``lineno`` is out of range.


return self.end_pos - self.begin_pos<EOL>

Returns the amount of characters spanned by the range.


return Range(self.source_buffer, self.begin_pos, self.begin_pos,<EOL>expanded_from=expanded_from)<EOL>

Returns a range identical to this one, but indicating that
it was expanded from the range `expanded_from`.


line_begins = self._extract_line_begins()<EOL>lineno = bisect.bisect_right(line_begins, offset) - <NUM_LIT:1><EOL>if offset >= <NUM_LIT:0> and offset <= len(self.source):<EOL><INDENT>return lineno + self.first_line, offset - line_begins[lineno]<EOL><DEDENT>else:<EOL><INDENT>raise IndexError<EOL><DEDENT>

Returns a ``line, column`` tuple for a character offset into the source,
orraises :exc:`IndexError` if ``lineno`` is out of range.


return [self.source_buffer.source_line(line)<EOL>for line in range(self.line(), self.end().line() + <NUM_LIT:1>)]<EOL>

Returns the lines of source code containing the entirety of this range.


return Range(self.source_buffer, self.end_pos, self.end_pos,<EOL>expanded_from=self.expanded_from)<EOL>

Returns a zero-length range located just after the end of this range.


self.replace(range, "<STR_LIT>")<EOL>


return Range(self.source_buffer, self.begin_pos, self.begin_pos,<EOL>expanded_from=self.expanded_from)<EOL>

Returns a zero-length range located just before the beginning of this range.


self.ranges.append((range, replacement))<EOL>

Remove `range` and replace it with string `replacement`.


def parse_buffer(buffer, mode="<STR_LIT>", flags=[], version=None, engine=None):

if version is None:<EOL><INDENT>version = sys.version_info[<NUM_LIT:0>:<NUM_LIT:2>]<EOL><DEDENT>if engine is None:<EOL><INDENT>engine = pythonparser_diagnostic.Engine()<EOL><DEDENT>lexer = pythonparser_lexer.Lexer(buffer, version, engine)<EOL>if mode in ("<STR_LIT>", "<STR_LIT>"):<EOL><INDENT>lexer.interactive = True<EOL><DEDENT>parser = pythonparser_parser.Parser(lexer, version, engine)<EOL>parser.add_flags(flags)<EOL>if mode == "<STR_LIT>":<EOL><INDENT>return parser.file_input(), lexer.comments<EOL><DEDENT>elif mode == "<STR_LIT>":<EOL><INDENT>return parser.single_input(), lexer.comments<EOL><DEDENT>elif mode == "<STR_LIT>":<EOL><INDENT>return parser.eval_input(), lexer.comments<EOL><DEDENT>

Like :meth:`parse`, but accepts a :class:`source.Buffer` instead of
source and filename, and returns comments as well.

:see: :meth:`parse`
:return: (:class:`ast.AST`, list of :class:`source.Comment`)
    Abstract syntax tree and comments


h = hash  <EOL>for _ in xrange(b.N):<EOL><INDENT>h('<STR_LIT>')<EOL><DEDENT>

Hashes the same value repeatedly to exercise any hash caching logic.


def _WriteXmlFile(filename, suite_duration, results):

xml_file = open(filename, '<STR_LIT:w>')<EOL>xml_file.write('<STR_LIT>'<EOL>'<STR_LIT>' %<EOL>(sys.argv[<NUM_LIT:0>], len(results), suite_duration))<EOL>for result in results:<EOL><INDENT>xml_file.write('<STR_LIT>'<EOL>'<STR_LIT>' %<EOL>(result.name, result.duration))<EOL>if result.properties:<EOL><INDENT>xml_file.write('<STR_LIT>')<EOL>for name in result.properties:<EOL><INDENT>value = result.properties[name]<EOL>if isinstance(value, float):<EOL><INDENT>formatted = '<STR_LIT>' % value<EOL><DEDENT>else:<EOL><INDENT>formatted = str(value)<EOL><DEDENT>xml_file.write('<STR_LIT>' %<EOL>(name, formatted))<EOL><DEDENT>xml_file.write('<STR_LIT>')<EOL><DEDENT>xml_file.write('<STR_LIT>')<EOL><DEDENT>xml_file.write('<STR_LIT>')<EOL>xml_file.close()<EOL>

Given a list of _BenchmarkResults, writes XML test results to filename.


if not os.environ.get('<STR_LIT>'):<EOL><INDENT>return map(lambda x: '<STR_LIT:%s>' % format(x).strip(), values)<EOL><DEDENT>return map(lambda x: u'<STR_LIT>' % (x, unichr(x)), sorted(values))<EOL>

Return string with unicodenames (unless that is disabled)


result = re.sub('<STR_LIT>', '<STR_LIT>', codepoint.text)<EOL>return Extension.convert_to_list_of_unicodes(result)<EOL>

Return list of unicodes for <scanning-codepoints>


def _loadNamelistIncludes(item, unique_glyphs, cache):

includes = item["<STR_LIT>"] = []<EOL>charset = item["<STR_LIT>"] = set() | item["<STR_LIT>"]<EOL>noCharcode = item["<STR_LIT>"] = set() | item["<STR_LIT>"]<EOL>dirname =  os.path.dirname(item["<STR_LIT>"])<EOL>for include in item["<STR_LIT>"]["<STR_LIT>"]:<EOL><INDENT>includeFile = os.path.join(dirname, include)<EOL>try:<EOL><INDENT>includedItem = readNamelist(includeFile, unique_glyphs, cache)<EOL><DEDENT>except NamelistRecursionError:<EOL><INDENT>continue<EOL><DEDENT>if includedItem in includes:<EOL><INDENT>continue<EOL><DEDENT>includes.append(includedItem)<EOL>charset |= includedItem["<STR_LIT>"]<EOL>noCharcode |= includedItem["<STR_LIT>"]<EOL><DEDENT>return item<EOL>

Load the includes of an encoding Namelist files.

    This is an implementation detail of readNamelist.


def codepointsInNamelist(namFilename, unique_glyphs=False, cache=None):

key = '<STR_LIT>' if not unique_glyphs else '<STR_LIT>'<EOL>internals_dir = os.path.dirname(os.path.abspath(__file__))<EOL>target = os.path.join(internals_dir, namFilename)<EOL>result = readNamelist(target, unique_glyphs, cache)<EOL>return result[key]<EOL>

Returns the set of codepoints contained in a given Namelist file.

    This is a replacement CodepointsInSubset and implements the "#$ include"
    header format.

    Args:
      namFilename: The path to the  Namelist file.
      unique_glyphs: Optional, whether to only include glyphs unique to subset.
    Returns:
      A set containing the glyphs in the subset.


results = []<EOL>for charset in _library.charsets:<EOL><INDENT>if self._charsets:<EOL><INDENT>cn = getattr(charset, '<STR_LIT>', False)<EOL>abbr = getattr(charset, '<STR_LIT>', False)<EOL>nn = getattr(charset, '<STR_LIT>', False)<EOL>naive = getattr(charset, '<STR_LIT>', False)<EOL>if cn and cn.lower() in self._charsets:<EOL><INDENT>results.append(charset)<EOL><DEDENT>elif nn and nn.lower() in self._charsets:<EOL><INDENT>results.append(charset)<EOL><DEDENT>elif naive and naive.lower() in self._charsets:<EOL><INDENT>results.append(charset)<EOL><DEDENT>elif abbr and abbr.lower() in self._charsets:<EOL><INDENT>results.append(charset)<EOL><DEDENT><DEDENT>else:<EOL><INDENT>results.append(charset)<EOL><DEDENT><DEDENT>for result in results:<EOL><INDENT>yield CharsetInfo(self, result)<EOL><DEDENT>

Returns list of CharsetInfo about supported orthographies


return "<STR_LIT>"<EOL>

TODO: Fix this so that pyfontaine falls back to using fontTools to get glyph names
if getGlyphNames() is really needed by the given mode of use.


@classmethod<EOL><INDENT>def linux(cls, path, argv=None, envp=None, entry_symbol=None, symbolic_files=None, concrete_start='<STR_LIT>', pure_symbolic=False, stdin_size=None, **kwargs):<DEDENT>

if stdin_size is None:<EOL><INDENT>stdin_size = consts.stdin_size<EOL><DEDENT>try:<EOL><INDENT>return cls(_make_linux(path, argv, envp, entry_symbol, symbolic_files, concrete_start, pure_symbolic, stdin_size), **kwargs)<EOL><DEDENT>except elftools.common.exceptions.ELFError:<EOL><INDENT>raise Exception(f'<STR_LIT>')<EOL><DEDENT>

Constructor for Linux binary analysis.

:param str path: Path to binary to analyze
:param argv: Arguments to provide to the binary
:type argv: list[str]
:param envp: Environment to provide to the binary
:type envp: dict[str, str]
:param entry_symbol: Entry symbol to resolve to start execution
:type envp: str
:param symbolic_files: Filenames to mark as having symbolic input
:type symbolic_files: list[str]
:param str concrete_start: Concrete stdin to use before symbolic input
:param int stdin_size: symbolic stdin size to use
:param kwargs: Forwarded to the Manticore constructor
:return: Manticore instance, initialized with a Linux State
:rtype: Manticore


with open(self.binary_path, '<STR_LIT:rb>') as f:<EOL><INDENT>elffile = ELFFile(f)<EOL>for section in elffile.iter_sections():<EOL><INDENT>if not isinstance(section, SymbolTableSection):<EOL><INDENT>continue<EOL><DEDENT>symbols = section.get_symbol_by_name(symbol)<EOL>if not symbols:<EOL><INDENT>continue<EOL><DEDENT>return symbols[<NUM_LIT:0>].entry['<STR_LIT>']<EOL><DEDENT>raise ValueError(f"<STR_LIT>")<EOL><DEDENT>

A helper method used to resolve a symbol name into a memory address when
injecting hooks for analysis.

:param symbol: function name to be resolved
:type symbol: string

:param line: if more functions present, optional line number can be included
:type line: int or None


return f'<STR_LIT>'<EOL>

Returns the string representation of the map mapping.

:rtype: str


def __init__(self, constraints, symbols=None, *args, **kwargs):

super().__init__(*args, **kwargs)<EOL>assert isinstance(constraints, ConstraintSet)<EOL>self._constraints = constraints<EOL>if symbols is None:<EOL><INDENT>self._symbols = {}<EOL><DEDENT>else:<EOL><INDENT>self._symbols = dict(symbols)<EOL><DEDENT>

Builds a memory.

:param constraints:  a set of constraints
:param symbols: Symbolic chunks


for page_addr in sorted(self._page2map.keys()):<EOL><INDENT>start = page_addr * self.page_size<EOL>end = start + self.page_size<EOL>for addr in range(start, end):<EOL><INDENT>yield addr<EOL><DEDENT><DEDENT>


for c in access:<EOL><INDENT>if c not in self.perms:<EOL><INDENT>return False<EOL><DEDENT><DEDENT>return True<EOL>

Check if there is enough permissions for access


def _import_concrete_memory(self, from_addr, to_addr):

logger.debug("<STR_LIT>".format(from_addr, to_addr, to_addr - from_addr))<EOL>for m in self.maps:<EOL><INDENT>span = interval_intersection(m.start, m.end, from_addr, to_addr)<EOL>if span is None:<EOL><INDENT>continue<EOL><DEDENT>start, stop = span<EOL>for addr in range(start, stop):<EOL><INDENT>if addr in self.backed_by_symbolic_store:<EOL><INDENT>continue<EOL><DEDENT>self.backing_array[addr] = Memory.read(self, addr, <NUM_LIT:1>)[<NUM_LIT:0>]<EOL>self.backed_by_symbolic_store.add(addr)<EOL><DEDENT><DEDENT>

for each address in this range need to read from concrete and write to symbolic
it's possible that there will be invalid/unmapped addresses in this range. need to skip to next map if so
also need to mark all of these addresses as now in the symbolic store

:param int from_addr:
:param int to_addr:
:return:


def _try_get_solutions(self, address, size, access, max_solutions=<NUM_LIT>, force=False):

assert issymbolic(address)<EOL>solutions = solver.get_all_values(self.constraints, address, maxcnt=max_solutions)<EOL>crashing_condition = False<EOL>for base in solutions:<EOL><INDENT>if not self.access_ok(slice(base, base + size), access, force):<EOL><INDENT>crashing_condition = Operators.OR(address == base, crashing_condition)<EOL><DEDENT><DEDENT>if solver.can_be_true(self.constraints, crashing_condition):<EOL><INDENT>raise InvalidSymbolicMemoryAccess(address, access, size, crashing_condition)<EOL><DEDENT>return solutions<EOL>

Try to solve for a symbolic address, checking permissions when reading/writing size bytes.

:param Expression address: The address to solve for
:param int size: How many bytes to check permissions for
:param str access: 'r' or 'w'
:param int max_solutions: Will raise if more solutions are found
:param force: Whether to ignore permission failure
:rtype: list


def __init__(self, start, size, perms, data_init=None, name=None, **kwargs):

super().__init__(start, size, perms, name, **kwargs)<EOL>self._data = bytearray(size)<EOL>if data_init is not None:<EOL><INDENT>assert len(data_init) <= size, '<STR_LIT>'<EOL>if isinstance(data_init[<NUM_LIT:0>], int):<EOL><INDENT>self._data[<NUM_LIT:0>:len(data_init)] = data_init<EOL><DEDENT>else:<EOL><INDENT>self._data[<NUM_LIT:0>:len(data_init)] = [ord(s) for s in data_init]<EOL><DEDENT><DEDENT>

Builds a concrete anonymous memory map.

:param start: the first valid address of the map.
:param size: the size of the map.
:param perms: the access permissions of the map.
:param data_init: the data to initialize the map.


if isinstance(c, int):<EOL><INDENT>return bytes([c])<EOL><DEDENT>elif isinstance(c, str):<EOL><INDENT>return bytes([ord(c)])<EOL><DEDENT>else:<EOL><INDENT>return c<EOL><DEDENT>

Convert a byte-like value into a canonical byte (a value of type 'bytes' of len 1)

:param c:
:return:


return self._end - self._start<EOL>


Split the current map into two mappings

:param address: The address at which to split the Map.


result = []<EOL>for m in self.maps:<EOL><INDENT>if isinstance(m, AnonMap):<EOL><INDENT>result.append((m.start, m.end, m.perms, <NUM_LIT:0>, '<STR_LIT>'))<EOL><DEDENT>elif isinstance(m, FileMap):<EOL><INDENT>result.append((m.start, m.end, m.perms, m._offset, m._filename))<EOL><DEDENT>else:<EOL><INDENT>result.append((m.start, m.end, m.perms, <NUM_LIT:0>, m.name))<EOL><DEDENT><DEDENT>return sorted(result)<EOL>

Returns a sorted list of all the mappings for this memory.

:return: a list of mappings.
:rtype: list


def __init__(self, addr, size, perms, filename, offset=<NUM_LIT:0>, overlay=None, **kwargs):

super().__init__(addr, size, perms, **kwargs)<EOL>assert isinstance(offset, int)<EOL>assert offset >= <NUM_LIT:0><EOL>self._filename = filename<EOL>self._offset = offset<EOL>with open(filename, '<STR_LIT:r>') as fileobject:<EOL><INDENT>fileobject.seek(<NUM_LIT:0>, <NUM_LIT:2>)<EOL>file_size = fileobject.tell()<EOL>self._mapped_size = min(size, file_size - offset)<EOL>self._data = mmap(fileobject.fileno(), offset, self._mapped_size)<EOL><DEDENT>if overlay is not None:<EOL><INDENT>self._overlay = dict(overlay)<EOL><DEDENT>else:<EOL><INDENT>self._overlay = dict()<EOL><DEDENT>

Builds a map of memory  initialized with the content of filename.

:param addr: the first valid address of the file map.
:param size: the size of the file map.
:param perms: the access permissions of the file map.
:param filename: the file to map in memory.
:param offset: the offset into the file where to start the mapping. \
        This offset must be a multiple of pagebitsize.


def write(self, address, value, force=False):

size = len(value)<EOL>if issymbolic(address):<EOL><INDENT>solutions = self._try_get_solutions(address, size, '<STR_LIT:w>', force=force)<EOL>for offset in range(size):<EOL><INDENT>for base in solutions:<EOL><INDENT>condition = base == address<EOL>self._symbols.setdefault(base + offset, []).append((condition, value[offset]))<EOL><DEDENT><DEDENT><DEDENT>else:<EOL><INDENT>for offset in range(size):<EOL><INDENT>if issymbolic(value[offset]):<EOL><INDENT>if not self.access_ok(address + offset, '<STR_LIT:w>', force):<EOL><INDENT>raise InvalidMemoryAccess(address + offset, '<STR_LIT:w>')<EOL><DEDENT>self._symbols[address + offset] = [(True, value[offset])]<EOL><DEDENT>else:<EOL><INDENT>if address + offset in self._symbols:<EOL><INDENT>del self._symbols[address + offset]<EOL><DEDENT>super().write(address + offset, [value[offset]], force)<EOL><DEDENT><DEDENT><DEDENT>

Write a value at address.
:param address: The address at which to write
:type address: int or long or Expression
:param value: Bytes to write
:type value: str or list
:param force: Whether to ignore permissions


def __init__(self, parent, offset=<NUM_LIT:0>, perms=None, size=None, **kwargs):

assert isinstance(parent, Map)<EOL>assert offset >= <NUM_LIT:0> and offset < len(parent)<EOL>if size is None:<EOL><INDENT>size = len(parent) - offset<EOL><DEDENT>assert parent.start + offset + size <= parent.end<EOL>if perms is None:<EOL><INDENT>perms = parent.perms<EOL><DEDENT>super().__init__(parent.start + offset, size, perms, **kwargs)<EOL>self._parent = parent<EOL>self._parent.__setitem__ = False<EOL>self._cow = {}<EOL>

A copy on write copy of parent. Writes to the parent after a copy on
write are unspecified.

:param parent: the parent map.
:param offset: an offset within the parent map from where to create the new map.
:param perms: Permissions on new mapping, or None if inheriting.
:param size: the size of the new map or max.


<EOL>addr = start<EOL>while addr < end:<EOL><INDENT>if addr not in self:<EOL><INDENT>addr += self.page_size<EOL><DEDENT>else:<EOL><INDENT>m = self._page2map[self._page(addr)]<EOL>yield m<EOL>addr = m.end<EOL><DEDENT><DEDENT>

Generates the list of maps that overlaps with the range [start:end]


Begin recording all writes. Retrieve all writes with `pop_record_writes()`


for addr in range(start, start + size):<EOL><INDENT>if len(self._symbols) == <NUM_LIT:0>:<EOL><INDENT>break<EOL><DEDENT>if addr in self._symbols:<EOL><INDENT>del self._symbols[addr]<EOL><DEDENT><DEDENT>super().munmap(start, size)<EOL>

Deletes the mappings for the specified address range and causes further
references to addresses within the range to generate invalid memory
references.

:param start: the starting address to delete.
:param size: the length of the unmapping.


if not self._in_range(index):<EOL><INDENT>raise IndexError('<STR_LIT>')<EOL><DEDENT>if isinstance(index, slice):<EOL><INDENT>index = slice(index.start - self.start, index.stop - self.start)<EOL><DEDENT>else:<EOL><INDENT>index -= self.start<EOL><DEDENT>return index<EOL>

Translates the index to the internal offsets.

self.start   -> 0
self.start+1 -> 1
...
self.end     -> len(self)


def read(self, address, size, force=False):

size = self._get_size(size)<EOL>assert not issymbolic(size)<EOL>if issymbolic(address):<EOL><INDENT>assert solver.check(self.constraints)<EOL>logger.debug(f'<STR_LIT>')<EOL>try:<EOL><INDENT>solutions = self._try_get_solutions(address, size, '<STR_LIT:r>', force=force)<EOL>assert len(solutions) > <NUM_LIT:0><EOL><DEDENT>except TooManySolutions as e:<EOL><INDENT>m, M = solver.minmax(self.constraints, address)<EOL>logger.debug(f'<STR_LIT>')<EOL>crashing_condition = True<EOL>for start, end, perms, offset, name in self.mappings():<EOL><INDENT>if start <= M + size and end >= m:<EOL><INDENT>if '<STR_LIT:r>' in perms:<EOL><INDENT>crashing_condition = Operators.AND(Operators.OR((address + size).ult(start), address.uge(end)), crashing_condition)<EOL><DEDENT><DEDENT><DEDENT>if solver.can_be_true(self.constraints, crashing_condition):<EOL><INDENT>raise InvalidSymbolicMemoryAccess(address, '<STR_LIT:r>', size, crashing_condition)<EOL><DEDENT>logger.info('<STR_LIT>')<EOL>condition = False<EOL>for base in e.solutions:<EOL><INDENT>condition = Operators.OR(address == base, condition)<EOL><DEDENT>from .state import ForkState<EOL>raise ForkState("<STR_LIT>", condition)<EOL><DEDENT>condition = False<EOL>for base in solutions:<EOL><INDENT>condition = Operators.OR(address == base, condition)<EOL><DEDENT>result = []<EOL>for offset in range(size):<EOL><INDENT>for base in solutions:<EOL><INDENT>addr_value = base + offset<EOL>byte = Operators.ORD(self.map_containing(addr_value)[addr_value])<EOL>if addr_value in self._symbols:<EOL><INDENT>for condition, value in self._symbols[addr_value]:<EOL><INDENT>byte = Operators.ITEBV(<NUM_LIT:8>, condition, Operators.ORD(value), byte)<EOL><DEDENT><DEDENT>if len(result) > offset:<EOL><INDENT>result[offset] = Operators.ITEBV(<NUM_LIT:8>, address == base, byte, result[offset])<EOL><DEDENT>else:<EOL><INDENT>result.append(byte)<EOL><DEDENT>assert len(result) == offset + <NUM_LIT:1><EOL><DEDENT><DEDENT>return list(map(Operators.CHR, result))<EOL><DEDENT>else:<EOL><INDENT>result = list(map(Operators.ORD, super().read(address, size, force)))<EOL>for offset in range(size):<EOL><INDENT>if address + offset in self._symbols:<EOL><INDENT>for condition, value in self._symbols[address + offset]:<EOL><INDENT>if condition is True:<EOL><INDENT>result[offset] = Operators.ORD(value)<EOL><DEDENT>else:<EOL><INDENT>result[offset] = Operators.ITEBV(<NUM_LIT:8>, condition, Operators.ORD(value), result[offset])<EOL><DEDENT><DEDENT><DEDENT><DEDENT>return list(map(Operators.CHR, result))<EOL><DEDENT>

Read a stream of potentially symbolic bytes from a potentially symbolic
address

:param address: Where to read from
:param size: How many bytes
:param force: Whether to ignore permissions
:rtype: list


start = self._floor(start)<EOL>end = self._ceil(start + size)<EOL>self.cpu._publish('<STR_LIT>', start, size)<EOL>for m in self._maps_in_range(start, end):<EOL><INDENT>self._del(m)<EOL>head, tail = m.split(start)<EOL>middle, tail = tail.split(end)<EOL>assert middle is not None<EOL>if head:<EOL><INDENT>self._add(head)<EOL><DEDENT>if tail:<EOL><INDENT>self._add(tail)<EOL><DEDENT><DEDENT>self.cpu._publish('<STR_LIT>', start, size)<EOL>logger.debug(f'<STR_LIT>')<EOL>


Reads a byte from an address or a sequence of bytes from a range of addresses

:param index: the address or slice where to obtain the bytes from.
:return: the character or sequence at the specified address.
:rtype: byte or array


@instruction<EOL><INDENT>def CMOVO(cpu, dest, src):<DEDENT>

dest.write(Operators.ITEBV(dest.size, cpu.OF, src.read(), dest.read()))<EOL>

Conditional move - Overflow.

Tests the status flags in the EFLAGS register and moves the source operand
(second operand) to the destination operand (first operand) if the given
test condition is true.

:param cpu: current CPU.
:param dest: destination operand.
:param src: source operand.


cpu.CF = True<EOL>


cpu.PC = Operators.ITEBV(cpu.address_bit_size, Operators.AND(False == cpu.ZF, cpu.SF == cpu.OF), target.read(), cpu.PC)<EOL>

Jumps short if not less or equal.

:param cpu: current CPU.
:param target: destination operand.


dest.write(Operators.ITEBV(dest.size, Operators.OR(cpu.ZF, cpu.SF != cpu.OF), <NUM_LIT:1>, <NUM_LIT:0>))<EOL>

Sets byte if not greater.

:param cpu: current CPU.
:param dest: destination operand.


@instruction<EOL><INDENT>def XADD(cpu, dest, src):<DEDENT>

MASK = (<NUM_LIT:1> << dest.size) - <NUM_LIT:1><EOL>SIGN_MASK = <NUM_LIT:1> << (dest.size - <NUM_LIT:1>)<EOL>arg0 = dest.read()<EOL>arg1 = src.read()<EOL>temp = (arg1 + arg0) & MASK<EOL>src.write(arg0)<EOL>dest.write(temp)<EOL>tempCF = Operators.OR(Operators.ULT(temp, arg0), Operators.ULT(temp, arg1))<EOL>cpu.CF = tempCF<EOL>cpu.AF = ((arg0 ^ arg1) ^ temp) & <NUM_LIT> != <NUM_LIT:0><EOL>cpu.ZF = temp == <NUM_LIT:0><EOL>cpu.SF = (temp & SIGN_MASK) != <NUM_LIT:0><EOL>cpu.OF = (((arg0 ^ arg1 ^ SIGN_MASK) & (temp ^ arg1)) & SIGN_MASK) != <NUM_LIT:0><EOL>cpu.PF = cpu._calculate_parity_flag(temp)<EOL>

Exchanges and adds.

Exchanges the first operand (destination operand) with the second operand
(source operand), then loads the sum of the two values into the destination
operand. The destination operand can be a register or a memory location;
the source operand is a register.
This instruction can be used with a LOCK prefix::

        TEMP  =  SRC + DEST
        SRC  =  DEST
        DEST  =  TEMP

:param cpu: current CPU.
:param dest: destination operand.
:param src: source operand.


@instruction<EOL><INDENT>def CMOVLE(cpu, dest, src):<DEDENT>

dest.write(Operators.ITEBV(dest.size, Operators.OR(cpu.SF ^ cpu.OF, cpu.ZF), src.read(), dest.read()))<EOL>

Conditional move - Less or equal/not greater.

Tests the status flags in the EFLAGS register and moves the source operand
(second operand) to the destination operand (first operand) if the given
test condition is true.

:param cpu: current CPU.
:param dest: destination operand.
:param src: source operand.


cpu.PC = Operators.ITEBV(cpu.address_bit_size, False == cpu.OF, target.read(), cpu.PC)<EOL>

Jumps short if not overflow.

:param cpu: current CPU.
:param target: destination operand.


def _PUNPCKL(cpu, dest, src, item_size):

assert dest.size == src.size<EOL>size = dest.size<EOL>dest_value = dest.read()<EOL>src_value = src.read()<EOL>mask = (<NUM_LIT:1> << item_size) - <NUM_LIT:1><EOL>res = <NUM_LIT:0><EOL>count = <NUM_LIT:0><EOL>for pos in range(<NUM_LIT:0>, size // item_size):<EOL><INDENT>if count >= size:<EOL><INDENT>break<EOL><DEDENT>item0 = Operators.ZEXTEND((dest_value >> (pos * item_size)) & mask, size)<EOL>item1 = Operators.ZEXTEND((src_value >> (pos * item_size)) & mask, size)<EOL>res |= item0 << count<EOL>count += item_size<EOL>res |= item1 << count<EOL>count += item_size<EOL><DEDENT>dest.write(res)<EOL>


def _PUNPCKH(cpu, dest, src, item_size):

assert dest.size == src.size<EOL>size = dest.size<EOL>dest_value = dest.read()<EOL>src_value = src.read()<EOL>mask = (<NUM_LIT:1> << item_size) - <NUM_LIT:1><EOL>res = <NUM_LIT:0><EOL>count = <NUM_LIT:0><EOL>for pos in reversed(range(<NUM_LIT:0>, size // item_size)):<EOL><INDENT>if count >= size:<EOL><INDENT>break<EOL><DEDENT>item0 = Operators.ZEXTEND((dest_value >> (pos * item_size)) & mask, size)<EOL>item1 = Operators.ZEXTEND((src_value >> (pos * item_size)) & mask, size)<EOL>res = res << item_size<EOL>res |= item1<EOL>res = res << item_size<EOL>res |= item0<EOL>count += item_size * <NUM_LIT:2><EOL><DEDENT>dest.write(res)<EOL>


@instruction<EOL><INDENT>def ADD(cpu, dest, src):<DEDENT>

cpu._ADD(dest, src, carry=False)<EOL>

Add.

Adds the first operand (destination operand) and the second operand (source operand)
and stores the result in the destination operand. When an immediate value is used as
an operand, it is sign-extended to the length of the destination operand format.
The ADD instruction does not distinguish between signed or unsigned operands. Instead,
the processor evaluates the result for both data types and sets the OF and CF flags to
indicate a carry in the signed or unsigned result, respectively. The SF flag indicates
the sign of the signed result::

        DEST  =  DEST + SRC;

:param cpu: current CPU.
:param dest: destination operand.
:param src: source operand.


@instruction<EOL><INDENT>def LSS(cpu, dest, src):<DEDENT>

raise NotImplementedError("<STR_LIT>")<EOL>

Loads far pointer.

Loads a far pointer (segment selector and offset) from the second operand
(source operand) into a segment register and the first operand (destination
operand). The source operand specifies a 48-bit or a 32-bit pointer in
memory depending on the current setting of the operand-size attribute
(32 bits or 16 bits, respectively). The instruction opcode and the destination
operand specify a segment register/general-purpose register pair. The
16-bit segment selector from the source operand is loaded into the segment
register specified with the opcode (DS, SS, ES, FS, or GS). The 32-bit
or 16-bit offset is loaded into the register specified with the destination
operand.
In 64-bit mode, the instruction's default operation size is 32 bits. Using a
REX prefix in the form of REX.W promotes operation to specify a source operand
referencing an 80-bit pointer (16-bit selector, 64-bit offset) in memory.
If one of these instructions is executed in protected mode, additional
information from the segment descriptor pointed to by the segment selector
in the source operand is loaded in the hidden part of the selected segment
register.
Also in protected mode, a null selector (values 0000 through 0003) can
be loaded into DS, ES, FS, or GS registers without causing a protection
exception. (Any subsequent reference to a segment whose corresponding
segment register is loaded with a null selector, causes a general-protection
exception (#GP) and no memory reference to the segment occurs.)::

        IF ProtectedMode
        THEN IF SS is loaded
            THEN IF SegementSelector  =  null
                THEN #GP(0);
                FI;
            ELSE IF Segment selector index is not within descriptor table limits
                OR Segment selector RPL  CPL
                OR Access rights indicate nonwritable data segment
                OR DPL  CPL
                THEN #GP(selector);
                FI;
            ELSE IF Segment marked not present
                THEN #SS(selector);
                FI;
                SS  =  SegmentSelector(SRC);
                SS  =  SegmentDescriptor([SRC]);
            ELSE IF DS, ES, FS, or GS is loaded with non-null segment selector
                THEN IF Segment selector index is not within descriptor table limits
                    OR Access rights indicate segment neither data nor readable code segment
                    OR Segment is data or nonconforming-code segment
                    AND both RPL and CPL > DPL)
                    THEN #GP(selector);
                    FI;
                ELSE IF Segment marked not present
                    THEN #NP(selector);
                    FI;
                    SegmentRegister  =  SegmentSelector(SRC) AND RPL;
                    SegmentRegister  =  SegmentDescriptor([SRC]);
                ELSE IF DS, ES, FS, or GS is loaded with a null selector:
                    SegmentRegister  =  NullSelector;
                    SegmentRegister(DescriptorValidBit)  =  0; (*hidden flag; not accessible by software*)
                FI;
            FI;
            IF (Real-Address or Virtual-8086 Mode)
            THEN
                SegmentRegister  =  SegmentSelector(SRC);
            FI;
            DEST  =  Offset(SRC);


@instruction<EOL><INDENT>def BTS(cpu, dest, src):<DEDENT>

if dest.type == '<STR_LIT>':<EOL><INDENT>value = dest.read()<EOL>pos = src.read() % dest.size<EOL>cpu.CF = value & (<NUM_LIT:1> << pos) == <NUM_LIT:1> << pos<EOL>dest.write(value | (<NUM_LIT:1> << pos))<EOL><DEDENT>elif dest.type == '<STR_LIT>':<EOL><INDENT>addr, pos = cpu._getMemoryBit(dest, src)<EOL>base, size, ty = cpu.get_descriptor(cpu.DS)<EOL>addr += base<EOL>value = cpu.read_int(addr, <NUM_LIT:8>)<EOL>cpu.CF = value & (<NUM_LIT:1> << pos) == <NUM_LIT:1> << pos<EOL>value = value | (<NUM_LIT:1> << pos)<EOL>cpu.write_int(addr, value, <NUM_LIT:8>)<EOL><DEDENT>else:<EOL><INDENT>raise NotImplementedError(f"<STR_LIT>")<EOL><DEDENT>

Bit test and set.

Selects the bit in a bit string (specified with the first operand, called
the bit base) at the bit-position designated by the bit offset operand
(second operand), stores the value of the bit in the CF flag, and sets
the selected bit in the bit string to 1.

:param cpu: current CPU.
:param dest: bit base operand.
:param src: bit offset operand.


@instruction<EOL><INDENT>def RCR(cpu, dest, src):<DEDENT>

OperandSize = dest.size<EOL>count = src.read()<EOL>countMask = {<NUM_LIT:8>: <NUM_LIT>,<EOL><NUM_LIT:16>: <NUM_LIT>,<EOL><NUM_LIT:32>: <NUM_LIT>,<EOL><NUM_LIT:64>: <NUM_LIT>}[OperandSize]<EOL>tempCount = Operators.ZEXTEND((count & countMask) % (src.size + <NUM_LIT:1>), OperandSize)<EOL>value = dest.read()<EOL>if isinstance(tempCount, int) and tempCount == <NUM_LIT:0>:<EOL><INDENT>new_val = value<EOL>dest.write(new_val)<EOL><DEDENT>else:<EOL><INDENT>carry = Operators.ITEBV(OperandSize, cpu.CF, <NUM_LIT:1>, <NUM_LIT:0>)<EOL>left = value >> (tempCount - <NUM_LIT:1>)<EOL>right = value << (OperandSize - tempCount)<EOL>new_val = (left >> <NUM_LIT:1>) | (carry << (OperandSize - tempCount)) | (right << <NUM_LIT:1>)<EOL>dest.write(new_val)<EOL>cpu.CF = Operators.ITE(tempCount != <NUM_LIT:0>, (left & <NUM_LIT:1>) == <NUM_LIT:1>, cpu.CF)<EOL>s_MSB = ((new_val >> (OperandSize - <NUM_LIT:1>)) & <NUM_LIT>) == <NUM_LIT:1><EOL>s_MSB2 = ((new_val >> (OperandSize - <NUM_LIT:2>)) & <NUM_LIT>) == <NUM_LIT:1><EOL>cpu.OF = Operators.ITE(tempCount == <NUM_LIT:1>,<EOL>s_MSB ^ s_MSB2, cpu.OF)<EOL><DEDENT>

Rotates through carry right (RCR).

Shifts (rotates) the bits of the first operand (destination operand) the number of bit positions specified in the
second operand (count operand) and stores the result in the destination operand. The destination operand can be
a register or a memory location; the count operand is an unsigned integer that can be an immediate or a value in
the CL register. In legacy and compatibility mode, the processor restricts the count to a number between 0 and 31
by masking all the bits in the count operand except the 5 least-significant bits.

Rotate through carry right (RCR) instructions shift all the bits toward less significant bit positions, except
for the least-significant bit, which is rotated to the most-significant bit location. The RCR instruction shifts the
CF flag into the most-significant bit and shifts the least-significant bit into the CF flag.

:param cpu: current CPU.
:param dest: destination operand.
:param src: count operand.


val = cpu.icount<EOL>cpu.RAX = val & <NUM_LIT><EOL>cpu.RDX = (val >> <NUM_LIT:32>) & <NUM_LIT><EOL>

Reads time-stamp counter.

Loads the current value of the processor's time-stamp counter into the
EDX:EAX registers.  The time-stamp counter is contained in a 64-bit
MSR. The high-order 32 bits of the MSR are loaded into the EDX
register, and the low-order 32 bits are loaded into the EAX register.
The processor increments the time-stamp counter MSR every clock cycle
and resets it to 0 whenever the processor is reset.

:param cpu: current CPU.


@instruction<EOL><INDENT>def XORPS(cpu, dest, src):<DEDENT>

res = dest.write(dest.read() ^ src.read())<EOL>

Performs a bitwise logical OR operation on the source operand (second operand) and the destination operand
(first operand) and stores the result in the destination operand. The source operand can be an MMX technology
register or a 64-bit memory location or it can be an XMM register or a 128-bit memory location. The destination
operand can be an MMX technology register or an XMM register. Each bit of the result is set to 1 if either
or both of the corresponding bits of the first and second operands are 1; otherwise, it is set to 0.


dest.write(Operators.ITEBV(dest.size, Operators.AND(cpu.ZF == False, cpu.SF == cpu.OF), <NUM_LIT:1>, <NUM_LIT:0>))<EOL>

Sets byte if not less or equal.

:param cpu: current CPU.
:param dest: destination operand.


return cpu.SAL(dest, src)<EOL>

The shift logical left.

The shift arithmetic left (SAL) and shift logical left (SHL) instructions perform the same operation.

:param cpu: current cpu.
:param dest: destination operand.
:param src: source operand.


cpu.PC = Operators.ITEBV(cpu.address_bit_size, (cpu.SF != cpu.OF), target.read(), cpu.PC)<EOL>

Jumps short if not greater or equal.

:param cpu: current CPU.
:param target: destination operand.


@instruction<EOL><INDENT>def SUB(cpu, dest, src):<DEDENT>

cpu._SUB(dest, src, carry=False)<EOL>

Subtract.

Subtracts the second operand (source operand) from the first operand
(destination operand) and stores the result in the destination operand.
The destination operand can be a register or a memory location; the
source operand can be an immediate, register, or memory location.
(However, two memory operands cannot be used in one instruction.) When
an immediate value is used as an operand, it is sign-extended to the
length of the destination operand format.
The SUB instruction does not distinguish between signed or unsigned
operands. Instead, the processor evaluates the result for both
data types and sets the OF and CF flags to indicate a borrow in the
signed or unsigned result, respectively. The SF flag indicates the sign
of the signed result::

    DEST  =  DEST - SRC;

:param cpu: current CPU.
:param dest: destination operand.
:param src: source operand.


raise Syscall()<EOL>

Calls to system

Executes a fast call to a level 0 system procedure or routine

:param cpu: current CPU.


@instruction<EOL><INDENT>def CMOVG(cpu, dest, src):<DEDENT>

dest.write(Operators.ITEBV(dest.size, Operators.AND(cpu.ZF == <NUM_LIT:0>, cpu.SF == cpu.OF), src.read(), dest.read()))<EOL>

Conditional move - Greater.

Tests the status flags in the EFLAGS register and moves the source operand
(second operand) to the destination operand (first operand) if the given
test condition is true.

:param cpu: current CPU.
:param dest: destination operand.
:param src: source operand.


cpu.PC = Operators.ITEBV(cpu.address_bit_size, False == cpu.PF, target.read(), cpu.PC)<EOL>

Jumps short if parity odd.

:param cpu: current CPU.
:param target: destination operand.


cpu.PC = Operators.ITEBV(cpu.address_bit_size, cpu.ZF, target.read(), cpu.PC)<EOL>

Jumps short if equal.

:param cpu: current CPU.
:param target: destination operand.


@instruction<EOL><INDENT>def PSHUFD(cpu, op0, op1, op3):<DEDENT>

size = op0.size<EOL>arg0 = op0.read()<EOL>arg1 = op1.read()<EOL>order = Operators.ZEXTEND(op3.read(), size)<EOL>arg0 = arg0 & <NUM_LIT><EOL>arg0 |= ((arg1 >> (((order >> <NUM_LIT:0>) & <NUM_LIT:3>) * <NUM_LIT:32>)) & <NUM_LIT>)<EOL>arg0 |= ((arg1 >> (((order >> <NUM_LIT:2>) & <NUM_LIT:3>) * <NUM_LIT:32>)) & <NUM_LIT>) << <NUM_LIT:32><EOL>arg0 |= ((arg1 >> (((order >> <NUM_LIT:4>) & <NUM_LIT:3>) * <NUM_LIT:32>)) & <NUM_LIT>) << <NUM_LIT:64><EOL>arg0 |= ((arg1 >> (((order >> <NUM_LIT:6>) & <NUM_LIT:3>) * <NUM_LIT:32>)) & <NUM_LIT>) << <NUM_LIT><EOL>op0.write(arg0)<EOL>

Packed shuffle doublewords.

Copies doublewords from source operand (second operand) and inserts them in the destination operand
(first operand) at locations selected with the order operand (third operand).

:param cpu: current CPU.
:param op0: destination operand.
:param op1: source operand.
:param op3: order operand.


dest.write(Operators.ITEBV(dest.size, cpu.PF == False, <NUM_LIT:1>, <NUM_LIT:0>))<EOL>

Sets byte if parity odd.

:param cpu: current CPU.
:param dest: destination operand.


@instruction<EOL><INDENT>def BTR(cpu, dest, src):<DEDENT>

if dest.type == '<STR_LIT>':<EOL><INDENT>value = dest.read()<EOL>pos = src.read() % dest.size<EOL>cpu.CF = value & (<NUM_LIT:1> << pos) == <NUM_LIT:1> << pos<EOL>dest.write(value & ~(<NUM_LIT:1> << pos))<EOL><DEDENT>elif dest.type == '<STR_LIT>':<EOL><INDENT>addr, pos = cpu._getMemoryBit(dest, src)<EOL>base, size, ty = cpu.get_descriptor(cpu.DS)<EOL>addr += base<EOL>value = cpu.read_int(addr, <NUM_LIT:8>)<EOL>cpu.CF = value & (<NUM_LIT:1> << pos) == <NUM_LIT:1> << pos<EOL>value = value & ~(<NUM_LIT:1> << pos)<EOL>cpu.write_int(addr, value, <NUM_LIT:8>)<EOL><DEDENT>else:<EOL><INDENT>raise NotImplementedError(f"<STR_LIT>")<EOL><DEDENT>

Bit test and reset.

Selects the bit in a bit string (specified with the first operand, called
the bit base) at the bit-position designated by the bit offset operand
(second operand), stores the value of the bit in the CF flag, and clears
the selected bit in the bit string to 0.

:param cpu: current CPU.
:param dest: bit base operand.
:param src: bit offset operand.


@instruction<EOL><INDENT>def BTC(cpu, dest, src):<DEDENT>

if dest.type == '<STR_LIT>':<EOL><INDENT>value = dest.read()<EOL>pos = src.read() % dest.size<EOL>cpu.CF = value & (<NUM_LIT:1> << pos) == <NUM_LIT:1> << pos<EOL>dest.write(value ^ (<NUM_LIT:1> << pos))<EOL><DEDENT>elif dest.type == '<STR_LIT>':<EOL><INDENT>addr, pos = cpu._getMemoryBit(dest, src)<EOL>base, size, ty = cpu.get_descriptor(cpu.DS)<EOL>addr += base<EOL>value = cpu.read_int(addr, <NUM_LIT:8>)<EOL>cpu.CF = value & (<NUM_LIT:1> << pos) == <NUM_LIT:1> << pos<EOL>value = value ^ (<NUM_LIT:1> << pos)<EOL>cpu.write_int(addr, value, <NUM_LIT:8>)<EOL><DEDENT>else:<EOL><INDENT>raise NotImplementedError(f"<STR_LIT>")<EOL><DEDENT>

Bit test and complement.

Selects the bit in a bit string (specified with the first operand, called
the bit base) at the bit-position designated by the bit offset operand
(second operand), stores the value of the bit in the CF flag, and complements
the selected bit in the bit string.

:param cpu: current CPU.
:param dest: bit base operand.
:param src: bit offset operand.


cpu.PC = Operators.ITEBV(cpu.address_bit_size, Operators.OR(cpu.ZF, cpu.SF != cpu.OF), target.read(), cpu.PC)<EOL>

Jumps short if less or equal.

:param cpu: current CPU.
:param target: destination operand.


CHEADER = '<STR_LIT>'<EOL>CBLUE = '<STR_LIT>'<EOL>CGREEN = '<STR_LIT>'<EOL>CWARNING = '<STR_LIT>'<EOL>CFAIL = '<STR_LIT>'<EOL>CEND = '<STR_LIT>'<EOL>pos = <NUM_LIT:0><EOL>result = "<STR_LIT>"<EOL>try:<EOL><INDENT>instruction = self.instruction<EOL>result += f"<STR_LIT>"<EOL><DEDENT>except BaseException:<EOL><INDENT>result += "<STR_LIT>"<EOL><DEDENT>regs = ('<STR_LIT>', '<STR_LIT>', '<STR_LIT>', '<STR_LIT>', '<STR_LIT>', '<STR_LIT>', '<STR_LIT>', '<STR_LIT>', '<STR_LIT>', '<STR_LIT>', '<STR_LIT>', '<STR_LIT>', '<STR_LIT>', '<STR_LIT>', '<STR_LIT>', '<STR_LIT>', '<STR_LIT>', '<STR_LIT>')<EOL>for reg_name in regs:<EOL><INDENT>value = self.read_register(reg_name)<EOL>if issymbolic(value):<EOL><INDENT>result += f'<STR_LIT>'<EOL><DEDENT>else:<EOL><INDENT>result += f"<STR_LIT>"<EOL><DEDENT>pos = <NUM_LIT:0><EOL><DEDENT>pos = <NUM_LIT:0><EOL>for reg_name in ('<STR_LIT>', '<STR_LIT>', '<STR_LIT>', '<STR_LIT>', '<STR_LIT>', '<STR_LIT>', '<STR_LIT>', '<STR_LIT>'):<EOL><INDENT>value = self.read_register(reg_name)<EOL>if issymbolic(value):<EOL><INDENT>result += f'<STR_LIT>'<EOL><DEDENT>else:<EOL><INDENT>result += f'<STR_LIT>'<EOL><DEDENT>pos = <NUM_LIT:0><EOL><DEDENT>for reg_name in ['<STR_LIT>', '<STR_LIT>', '<STR_LIT>', '<STR_LIT>', '<STR_LIT>', '<STR_LIT>']:<EOL><INDENT>base, size, ty = self.get_descriptor(self.read_register(reg_name))<EOL>result += f'<STR_LIT>'<EOL><DEDENT>for reg_name in ['<STR_LIT>', '<STR_LIT>', '<STR_LIT>', '<STR_LIT>', '<STR_LIT>', '<STR_LIT>', '<STR_LIT>', '<STR_LIT>', '<STR_LIT>']:<EOL><INDENT>value = getattr(self, reg_name)<EOL>result += f'<STR_LIT>'<EOL>pos = <NUM_LIT:0><EOL><DEDENT>return result<EOL>

Returns a string representation of cpu state

:rtype: str
:return: a string containing the name and current value for all the registers.


@instruction<EOL><INDENT>def LES(cpu, dest, src):<DEDENT>


cpu.RAX = Operators.SEXTEND(cpu.EAX, <NUM_LIT:32>, <NUM_LIT:64>)<EOL>


@instruction<EOL><INDENT>def SHRX(cpu, dest, src, count):<DEDENT>

OperandSize = dest.size<EOL>count = count.read()<EOL>countMask = {<NUM_LIT:8>: <NUM_LIT>,<EOL><NUM_LIT:16>: <NUM_LIT>,<EOL><NUM_LIT:32>: <NUM_LIT>,<EOL><NUM_LIT:64>: <NUM_LIT>}[OperandSize]<EOL>tempCount = Operators.ZEXTEND(count & countMask, dest.size)<EOL>tempDest = value = src.read()<EOL>res = dest.write(Operators.ITEBV(dest.size, tempCount == <NUM_LIT:0>, tempDest, value >> tempCount))<EOL>

The shift arithmetic right.

:param cpu: current CPU.
:param dest: destination operand.
:param src: count operand.


@instruction<EOL><INDENT>def PUNPCKLBW(cpu, dest, src):<DEDENT>

cpu._PUNPCKL(dest, src, <NUM_LIT:8>)<EOL>

Interleaves the low-order bytes of the source and destination operands.

Unpacks and interleaves the low-order data elements (bytes, words, doublewords, and quadwords)
of the destination operand (first operand) and source operand (second operand) into the
destination operand.

:param cpu: current CPU.
:param dest: destination operand.
:param src: source operand.


@instruction<EOL><INDENT>def PMAXUB(cpu, dest, src):<DEDENT>

dest_value = dest.read()<EOL>src_value = src.read()<EOL>result = <NUM_LIT:0><EOL>for pos in range(<NUM_LIT:0>, dest.size, <NUM_LIT:8>):<EOL><INDENT>itema = (dest_value >> pos) & <NUM_LIT><EOL>itemb = (src_value >> pos) & <NUM_LIT><EOL>result |= Operators.ITEBV(dest.size, itema > itemb, itema, itemb) << pos<EOL><DEDENT>dest.write(result)<EOL>

PMAXUB: returns maximum of packed unsigned byte integers in the dest operand

Performs a SIMD compare of the packed unsigned byte in the second source operand
and the first source operand and returns the maximum value for each pair of
integers to the destination operand.

Example :
$xmm1.v16_int8 = {..., 0xf2, 0xd1}
$xmm2.v16_int8 = {..., 0xd2, 0xf1}
# after pmaxub xmm1, xmm2, we get
$xmm1.v16_int8 = {..., 0xf2, 0xf1}


dest.write(Operators.ITEBV(dest.size, Operators.OR(cpu.ZF, cpu.SF != cpu.OF), <NUM_LIT:1>, <NUM_LIT:0>))<EOL>

Sets byte if less or equal.

:param cpu: current CPU.
:param dest: destination operand.


used_regs = (cpu.SF, cpu.ZF, cpu.AF, cpu.PF, cpu.CF)<EOL>is_expression = any(issymbolic(x) for x in used_regs)<EOL>def make_flag(val, offset):<EOL><INDENT>if is_expression:<EOL><INDENT>return Operators.ITEBV(<NUM_LIT:8>, val,<EOL>BitVecConstant(<NUM_LIT:8>, <NUM_LIT:1> << offset),<EOL>BitVecConstant(<NUM_LIT:8>, <NUM_LIT:0>))<EOL><DEDENT>else:<EOL><INDENT>return val << offset<EOL><DEDENT><DEDENT>cpu.AH = (make_flag(cpu.SF, <NUM_LIT:7>) |<EOL>make_flag(cpu.ZF, <NUM_LIT:6>) |<EOL>make_flag(<NUM_LIT:0>, <NUM_LIT:5>) |<EOL>make_flag(cpu.AF, <NUM_LIT:4>) |<EOL>make_flag(<NUM_LIT:0>, <NUM_LIT:3>) |<EOL>make_flag(cpu.PF, <NUM_LIT:2>) |<EOL>make_flag(<NUM_LIT:1>, <NUM_LIT:1>) |<EOL>make_flag(cpu.CF, <NUM_LIT:0>))<EOL>

Loads status flags into AH register.

Moves the low byte of the EFLAGS register (which includes status flags
SF, ZF, AF, PF, and CF) to the AH register. Reserved bits 1, 3, and 5
of the EFLAGS register are set in the AH register::

        AH  =  EFLAGS(SF:ZF:0:AF:0:PF:1:CF);

:param cpu: current CPU.
:param dest: destination operand.
:param src: source operand.


@instruction<EOL><INDENT>def CMOVP(cpu, dest, src):<DEDENT>

dest.write(Operators.ITEBV(dest.size, cpu.PF, src.read(), dest.read()))<EOL>

Conditional move - Parity/parity even.

Tests the status flags in the EFLAGS register and moves the source operand
(second operand) to the destination operand (first operand) if the given
test condition is true.

:param cpu: current CPU.
:param dest: destination operand.
:param src: source operand.


@instruction<EOL><INDENT>def PSLLD(cpu, op0, op1):<DEDENT>

arg0 = op0.read()<EOL>arg1 = op1.read()<EOL>res = <NUM_LIT:0><EOL>for i in range(<NUM_LIT:0>, op0.size, <NUM_LIT:32>):<EOL><INDENT>res |= ((Operators.EXTRACT(arg0, i, <NUM_LIT:32>) << arg1) & <NUM_LIT>) << i<EOL><DEDENT>op0.write(res)<EOL>

PSLLD: Packed shift left logical with double words

Shifts the destination operand (first operand) to the left by the number of bytes specified
in the count operand (second operand). The empty low-order bytes are cleared (set to all 0s).
If the value specified by the count operand is greater than 15, the destination operand is
set to all 0s. The count operand is an 8-bit immediate.

Example :
$xmm1.v16_int8 = {..., 0x00000003, 0x00000001}
# after pslld xmm1, 2, we get
$xmm1.v16_int8 = {..., 0x0000000c, 0x00000004}


cpu.PC = Operators.ITEBV(cpu.address_bit_size, Operators.AND(cpu.ZF == False, cpu.SF == cpu.OF), target.read(), cpu.PC)<EOL>

Jumps short if greater.

:param cpu: current CPU.
:param target: destination operand.


cpu.DF = True<EOL>

Sets direction flag.

Sets the DF flag in the EFLAGS register. When the DF flag is set to 1, string operations decrement
the index registers (ESI and/or EDI)::

    DF  =  1;

:param cpu: current CPU.


dest.write(Operators.ITEBV(dest.size, Operators.OR(cpu.CF, cpu.ZF) == False, <NUM_LIT:1>, <NUM_LIT:0>))<EOL>

Sets byte if above.

Sets the destination operand to 0 or 1 depending on the settings of the status flags (CF, SF, OF, ZF, and PF, 1, 0) in the
EFLAGS register. The destination operand points to a byte register or a byte in memory. The condition code suffix
(cc, 1, 0) indicates the condition being tested for::
        IF condition
        THEN
            DEST = 1;
        ELSE
            DEST = 0;
        FI;

:param cpu: current CPU.
:param dest: destination operand.


Not implemented.

Performs no operation.


<EOL>cpu.EAX, cpu.EDX = <NUM_LIT:7>, <NUM_LIT:0><EOL>

XGETBV instruction.

Reads the contents of the extended cont register (XCR) specified in the ECX register into registers EDX:EAX.
Implemented only for ECX = 0.

:param cpu: current CPU.


cpu.PC = Operators.ITEBV(cpu.address_bit_size, Operators.AND(cpu.CF == False, cpu.ZF == False), target.read(), cpu.PC)<EOL>

Jumps short if above.

:param cpu: current CPU.
:param target: destination operand.


def __init__(self, memory, *args, **kwargs):

super().__init__(AMD64RegFile(aliases={'<STR_LIT>': '<STR_LIT>', '<STR_LIT>': '<STR_LIT>', '<STR_LIT>': '<STR_LIT>'}, ),<EOL>memory,<EOL>*args,<EOL>**kwargs)<EOL>

Builds a CPU model.
:param memory: memory object for this CPU.


cpu.RCX = cpu.RIP<EOL>cpu.R11 = cpu.RFLAGS<EOL>raise Syscall()<EOL>

Calls to interrupt procedure.

The INT n instruction generates a call to the interrupt or exception handler specified
with the destination operand. The INT n instruction is the general mnemonic for executing
a software-generated call to an interrupt handler. The INTO instruction is a special
mnemonic for calling overflow exception (#OF), interrupt vector number 4. The overflow
interrupt checks the OF flag in the EFLAGS register and calls the overflow interrupt handler
if the OF flag is set to 1.

:param cpu: current CPU.


@instruction<EOL><INDENT>def SHLD(cpu, dest, src, count):<DEDENT>

OperandSize = dest.size<EOL>tempCount = Operators.ZEXTEND(count.read(), OperandSize) & (OperandSize - <NUM_LIT:1>)<EOL>arg0 = dest.read()<EOL>arg1 = src.read()<EOL>MASK = ((<NUM_LIT:1> << OperandSize) - <NUM_LIT:1>)<EOL>t0 = (arg0 << tempCount)<EOL>t1 = arg1 >> (OperandSize - tempCount)<EOL>res = Operators.ITEBV(OperandSize, tempCount == <NUM_LIT:0>, arg0, t0 | t1)<EOL>res = res & MASK<EOL>dest.write(res)<EOL>if isinstance(tempCount, int) and tempCount == <NUM_LIT:0>:<EOL><INDENT>pass<EOL><DEDENT>else:<EOL><INDENT>SIGN_MASK = <NUM_LIT:1> << (OperandSize - <NUM_LIT:1>)<EOL>lastbit = <NUM_LIT:0> != ((arg0 << (tempCount - <NUM_LIT:1>)) & SIGN_MASK)<EOL>cpu._set_shiftd_flags(OperandSize, arg0, res, lastbit, tempCount)<EOL><DEDENT>

Double precision shift right.

Shifts the first operand (destination operand) to the left the number of bits specified by the third operand
(count operand). The second operand (source operand) provides bits to shift in from the right (starting with
the least significant bit of the destination operand).

:param cpu: current CPU.
:param dest: destination operand.
:param src: source operand.
:param count: count operand


<EOL>size = src.size<EOL>v = src.read()<EOL>if size != <NUM_LIT:64> and size != cpu.address_bit_size // <NUM_LIT:2>:<EOL><INDENT>v = Operators.SEXTEND(v, size, cpu.address_bit_size)<EOL>size = cpu.address_bit_size<EOL><DEDENT>cpu.push(v, size)<EOL>

Pushes a value onto the stack.

Decrements the stack pointer and then stores the source operand on the top of the stack.

:param cpu: current CPU.
:param src: source operand.


@instruction<EOL><INDENT>def MOVSX(cpu, op0, op1):<DEDENT>

op0.write(Operators.SEXTEND(op1.read(), op1.size, op0.size))<EOL>

Moves with sign-extension.

Copies the contents of the source operand (register or memory location) to the destination
operand (register) and sign extends the value to 16::

        OP0  =  SignExtend(OP1);

:param cpu: current CPU.
:param op0: destination operand.
:param op1: source operand.


def _getMemoryBit(cpu, bitbase, bitoffset):

assert bitbase.type == '<STR_LIT>'<EOL>assert bitbase.size >= bitoffset.size<EOL>addr = bitbase.address()<EOL>offt = Operators.SEXTEND(bitoffset.read(), bitoffset.size, bitbase.size)<EOL>offt_is_neg = offt >= (<NUM_LIT:1> << (bitbase.size - <NUM_LIT:1>))<EOL>offt_in_bytes = offt // <NUM_LIT:8><EOL>bitpos = offt % <NUM_LIT:8><EOL>new_addr = addr + Operators.ITEBV(bitbase.size, offt_is_neg, -offt_in_bytes, offt_in_bytes)<EOL>return (new_addr, bitpos)<EOL>

Calculate address and bit offset given a base address and a bit offset
            relative to that address (in the form of asm operands)


dest.write(Operators.ITEBV(dest.size, cpu.CF == False, <NUM_LIT:1>, <NUM_LIT:0>))<EOL>

Sets byte if above or equal.

:param cpu: current CPU.
:param dest: destination operand.


@instruction<EOL><INDENT>def CMOVZ(cpu, dest, src):<DEDENT>

dest.write(Operators.ITEBV(dest.size, cpu.ZF, src.read(), dest.read()))<EOL>

Conditional move - Equal/zero.

Tests the status flags in the EFLAGS register and moves the source operand
(second operand) to the destination operand (first operand) if the given
test condition is true.

:param cpu: current CPU.
:param dest: destination operand.
:param src: source operand.


cpu.PC = Operators.ITEBV(cpu.address_bit_size, cpu.CF == False, target.read(), cpu.PC)<EOL>

Jumps short if not below.

:param cpu: current CPU.
:param target: destination operand.


cpu.PC = Operators.ITEBV(cpu.address_bit_size, cpu.SF, target.read(), cpu.PC)<EOL>

Jumps short if sign.

:param cpu: current CPU.
:param target: destination operand.


dest.write(Operators.ITEBV(dest.size, cpu.ZF, <NUM_LIT:1>, <NUM_LIT:0>))<EOL>

Sets byte if zero.

:param cpu: current CPU.
:param dest: destination operand.


source = dest.read()<EOL>res = dest.write(-source)<EOL>cpu._calculate_logic_flags(dest.size, res)<EOL>cpu.CF = source != <NUM_LIT:0><EOL>cpu.AF = (res & <NUM_LIT>) != <NUM_LIT><EOL>

Two's complement negation.

Replaces the value of operand (the destination operand) with its two's complement.
(This operation is equivalent to subtracting the operand from 0.) The destination operand is
located in a general-purpose register or a memory location::

        IF DEST  =  0
        THEN CF  =  0
        ELSE CF  =  1;
        FI;
        DEST  =  - (DEST)

:param cpu: current CPU.
:param dest: destination operand.


@instruction<EOL><INDENT>def SHRD(cpu, dest, src, count):<DEDENT>

OperandSize = dest.size<EOL>MASK = ((<NUM_LIT:1> << OperandSize) - <NUM_LIT:1>)<EOL>tempCount = Operators.ZEXTEND(count.read(), OperandSize) & (OperandSize - <NUM_LIT:1>)<EOL>if isinstance(tempCount, int) and tempCount == <NUM_LIT:0>:<EOL><INDENT>pass<EOL><DEDENT>else:<EOL><INDENT>arg0 = dest.read()<EOL>arg1 = src.read()<EOL>res = Operators.ITEBV(OperandSize, tempCount == <NUM_LIT:0>, arg0, (arg0 >> tempCount) | (arg1 << (dest.size - tempCount)))<EOL>res = res & MASK<EOL>dest.write(res)<EOL>lastbit = <NUM_LIT:0> != (arg0 >> (tempCount - <NUM_LIT:1>)) & <NUM_LIT:1><EOL>cpu._set_shiftd_flags(OperandSize, arg0, res, lastbit, tempCount)<EOL><DEDENT>

Double precision shift right.

Shifts the first operand (destination operand) to the right the number of bits specified by the third operand
(count operand). The second operand (source operand) provides bits to shift in from the left (starting with
the most significant bit of the destination operand).

:param cpu: current CPU.
:param dest: destination operand.
:param src: source operand.
:param count: count operand


@instruction<EOL><INDENT>def POPCNT(cpu, dest, src):<DEDENT>

count = <NUM_LIT:0><EOL>source = src.read()<EOL>for i in range(src.size):<EOL><INDENT>count += Operators.ITEBV(dest.size, (source >> i) & <NUM_LIT:1> == <NUM_LIT:1>, <NUM_LIT:1>, <NUM_LIT:0>)<EOL><DEDENT>dest.write(count)<EOL>cpu.OF = False<EOL>cpu.SF = False<EOL>cpu.AF = False<EOL>cpu.CF = False<EOL>cpu.PF = False<EOL>cpu.ZF = source == <NUM_LIT:0><EOL>

This instruction calculates of number of bits set to 1 in the second
operand (source) and returns the count in the first operand (a destination
register).
Count = 0;
For (i=0; i < OperandSize; i++) {
    IF (SRC[ i] = 1) // i'th bit
        THEN Count++;
    FI;
}
DEST = Count;
Flags Affected
OF, SF, ZF, AF, CF, PF are all cleared.
ZF is set if SRC = 0, otherwise ZF is cleared


cpu.PC = Operators.ITEBV(cpu.address_bit_size, False == cpu.PF, target.read(), cpu.PC)<EOL>

Jumps short if not parity.

:param cpu: current CPU.
:param target: destination operand.


@instruction<EOL><INDENT>def PADDD(cpu, op0, op1):<DEDENT>

arg0 = op0.read()<EOL>arg1 = op1.read()<EOL>res = <NUM_LIT:0><EOL>for i in range(<NUM_LIT:0>, op0.size, <NUM_LIT:32>):<EOL><INDENT>res |= ((Operators.EXTRACT(arg0, i, <NUM_LIT:32>) + Operators.EXTRACT(arg1, i, <NUM_LIT:32>)) & <NUM_LIT>) << i<EOL><DEDENT>op0.write(res)<EOL>

PADDD: Packed add with double words

Performs a SIMD add of the packed integers from the source operand (second operand)
and the destination operand (first operand), and stores the packed integer results
in the destination operand

Example :
$xmm1.v16_int8 = {..., 0x00000003, 0x00000001}
$xmm2.v16_int8 = {..., 0x00000004, 0x00000002}
# after paddd xmm1, xmm2, we get
$xmm1.v16_int8 = {..., 0x00000007, 0x00000003}


@instruction<EOL><INDENT>def CMOVNZ(cpu, dest, src):<DEDENT>

dest.write(Operators.ITEBV(dest.size, cpu.ZF == False, src.read(), dest.read()))<EOL>

Conditional move - Not equal/not zero.

Tests the status flags in the EFLAGS register and moves the source operand
(second operand) to the destination operand (first operand) if the given
test condition is true.

:param cpu: current CPU.
:param dest: destination operand.
:param src: source operand.


dest.write(Operators.ITEBV(dest.size, cpu.OF, <NUM_LIT:1>, <NUM_LIT:0>))<EOL>

Sets byte if overflow.

:param cpu: current CPU.
:param dest: destination operand.


dest = operands[<NUM_LIT:0>]<EOL>OperandSize = dest.size<EOL>reg_name_h = {<NUM_LIT:8>: '<STR_LIT>', <NUM_LIT:16>: '<STR_LIT>', <NUM_LIT:32>: '<STR_LIT>', <NUM_LIT:64>: '<STR_LIT>'}[OperandSize]<EOL>reg_name_l = {<NUM_LIT:8>: '<STR_LIT>', <NUM_LIT:16>: '<STR_LIT>', <NUM_LIT:32>: '<STR_LIT>', <NUM_LIT:64>: '<STR_LIT>'}[OperandSize]<EOL>arg0 = dest.read()<EOL>arg1 = None<EOL>arg2 = None<EOL>res = None<EOL>if len(operands) == <NUM_LIT:1>:<EOL><INDENT>arg1 = cpu.read_register(reg_name_l)<EOL>temp = (Operators.SEXTEND(arg0, OperandSize, OperandSize * <NUM_LIT:2>) *<EOL>Operators.SEXTEND(arg1, OperandSize, OperandSize * <NUM_LIT:2>))<EOL>temp = temp & ((<NUM_LIT:1> << (OperandSize * <NUM_LIT:2>)) - <NUM_LIT:1>)<EOL>cpu.write_register(reg_name_l,<EOL>Operators.EXTRACT(temp, <NUM_LIT:0>, OperandSize))<EOL>cpu.write_register(reg_name_h,<EOL>Operators.EXTRACT(temp, OperandSize, OperandSize))<EOL>res = Operators.EXTRACT(temp, <NUM_LIT:0>, OperandSize)<EOL><DEDENT>elif len(operands) == <NUM_LIT:2>:<EOL><INDENT>arg1 = operands[<NUM_LIT:1>].read()<EOL>arg1 = Operators.SEXTEND(arg1, OperandSize, OperandSize * <NUM_LIT:2>)<EOL>temp = Operators.SEXTEND(arg0, OperandSize, OperandSize * <NUM_LIT:2>) * arg1<EOL>temp = temp & ((<NUM_LIT:1> << (OperandSize * <NUM_LIT:2>)) - <NUM_LIT:1>)<EOL>res = dest.write(Operators.EXTRACT(temp, <NUM_LIT:0>, OperandSize))<EOL><DEDENT>else:<EOL><INDENT>arg1 = operands[<NUM_LIT:1>].read()<EOL>arg2 = operands[<NUM_LIT:2>].read()<EOL>temp = (Operators.SEXTEND(arg1, OperandSize, OperandSize * <NUM_LIT:2>) *<EOL>Operators.SEXTEND(arg2, operands[<NUM_LIT:2>].size, OperandSize * <NUM_LIT:2>))<EOL>temp = temp & ((<NUM_LIT:1> << (OperandSize * <NUM_LIT:2>)) - <NUM_LIT:1>)<EOL>res = dest.write(Operators.EXTRACT(temp, <NUM_LIT:0>, OperandSize))<EOL><DEDENT>cpu.CF = (Operators.SEXTEND(res, OperandSize, OperandSize * <NUM_LIT:2>) != temp)<EOL>cpu.OF = cpu.CF<EOL>

Signed multiply.

Performs a signed multiplication of two operands. This instruction has
three forms, depending on the number of operands.
    - One-operand form. This form is identical to that used by the MUL
    instruction. Here, the source operand (in a general-purpose
    register or memory location) is multiplied by the value in the AL,
    AX, or EAX register (depending on the operand size) and the product
    is stored in the AX, DX:AX, or EDX:EAX registers, respectively.
    - Two-operand form. With this form the destination operand (the
    first operand) is multiplied by the source operand (second
    operand). The destination operand is a general-purpose register and
    the source operand is an immediate value, a general-purpose
    register, or a memory location. The product is then stored in the
    destination operand location.
    - Three-operand form. This form requires a destination operand (the
    first operand) and two source operands (the second and the third
    operands). Here, the first source operand (which can be a
    general-purpose register or a memory location) is multiplied by the
    second source operand (an immediate value). The product is then
    stored in the destination operand (a general-purpose register).

When an immediate value is used as an operand, it is sign-extended to
the length of the destination operand format. The CF and OF flags are
set when significant bits are carried into the upper half of the
result. The CF and OF flags are cleared when the result fits exactly in
the lower half of the result. The three forms of the IMUL instruction
are similar in that the length of the product is calculated to twice
the length of the operands. With the one-operand form, the product is
stored exactly in the destination. With the two- and three- operand
forms, however, result is truncated to the length of the destination
before it is stored in the destination register. Because of this
truncation, the CF or OF flag should be tested to ensure that no
significant bits are lost. The two- and three-operand forms may also be
used with unsigned operands because the lower half of the product is
the same regardless if the operands are signed or unsigned. The CF and
OF flags, however, cannot be used to determine if the upper half of the
result is non-zero::

IF (NumberOfOperands == 1)
THEN
    IF (OperandSize == 8)
    THEN
        AX = AL * SRC (* Signed multiplication *)
        IF AL == AX
        THEN
            CF = 0; OF = 0;
        ELSE
            CF = 1; OF = 1;
        FI;
    ELSE
        IF OperandSize == 16
        THEN
            DX:AX = AX * SRC (* Signed multiplication *)
            IF sign_extend_to_32 (AX) == DX:AX
            THEN
                CF = 0; OF = 0;
            ELSE
                CF = 1; OF = 1;
            FI;
        ELSE
            IF OperandSize == 32
            THEN
                EDX:EAX = EAX * SRC (* Signed multiplication *)
                IF EAX == EDX:EAX
                THEN
                    CF = 0; OF = 0;
                ELSE
                    CF = 1; OF = 1;
                FI;
            ELSE (* OperandSize = 64 *)
                RDX:RAX = RAX * SRC (* Signed multiplication *)
                IF RAX == RDX:RAX
                THEN
                    CF = 0; OF = 0;
                ELSE
                   CF = 1; OF = 1;
                FI;
            FI;
        FI;
ELSE
    IF (NumberOfOperands = 2)
    THEN
        temp = DEST * SRC (* Signed multiplication; temp is double DEST size *)
        DEST = DEST * SRC (* Signed multiplication *)
        IF temp != DEST
        THEN
            CF = 1; OF = 1;
        ELSE
            CF = 0; OF = 0;
        FI;
    ELSE (* NumberOfOperands = 3 *)
        DEST = SRC1 * SRC2 (* Signed multiplication *)
        temp = SRC1 * SRC2 (* Signed multiplication; temp is double SRC1 size *)
        IF temp != DEST
        THEN
            CF = 1; OF = 1;
        ELSE
            CF = 0; OF = 0;
        FI;
    FI;
FI;

:param cpu: current CPU.
:param operands: variable list of operands.


@instruction<EOL><INDENT>def BSR(cpu, dest, src):<DEDENT>

value = src.read()<EOL>flag = Operators.EXTRACT(value, src.size - <NUM_LIT:1>, <NUM_LIT:1>) == <NUM_LIT:1><EOL>res = <NUM_LIT:0><EOL>for pos in reversed(range(<NUM_LIT:0>, src.size)):<EOL><INDENT>res = Operators.ITEBV(dest.size, flag, res, pos)<EOL>flag = Operators.OR(flag, (Operators.EXTRACT(value, pos, <NUM_LIT:1>) == <NUM_LIT:1>))<EOL><DEDENT>cpu.PF = cpu._calculate_parity_flag(res)<EOL>cpu.ZF = value == <NUM_LIT:0><EOL>dest.write(Operators.ITEBV(dest.size, cpu.ZF, dest.read(), res))<EOL>

Bit scan reverse.

Searches the source operand (second operand) for the most significant
set bit (1 bit). If a most significant 1 bit is found, its bit index is
stored in the destination operand (first operand). The source operand
can be a register or a memory location; the destination operand is a register.
The bit index is an unsigned offset from bit 0 of the source operand.
If the contents source operand are 0, the contents of the destination
operand is undefined::

        IF SRC  =  0
        THEN
            ZF  =  1;
            DEST is undefined;
        ELSE
            ZF  =  0;
            temp  =  OperandSize - 1;
            WHILE Bit(SRC, temp)  =  0
            DO
                temp  =  temp - 1;
                DEST  =  temp;
            OD;
        FI;

:param cpu: current CPU.
:param dest: destination operand.
:param src: source operand.


Not implemented.

Performs no operation.


Jumps short if above or equal.

:param cpu: current CPU.
:param target: destination operand.


@instruction<EOL><INDENT>def PSUBB(cpu, dest, src):<DEDENT>

result = []<EOL>value_a = dest.read()<EOL>value_b = src.read()<EOL>for i in reversed(range(<NUM_LIT:0>, dest.size, <NUM_LIT:8>)):<EOL><INDENT>a = Operators.EXTRACT(value_a, i, <NUM_LIT:8>)<EOL>b = Operators.EXTRACT(value_b, i, <NUM_LIT:8>)<EOL>result.append((a - b) & <NUM_LIT>)<EOL><DEDENT>dest.write(Operators.CONCAT(<NUM_LIT:8> * len(result), *result))<EOL>

Packed subtract.

Performs a SIMD subtract of the packed integers of the source operand (second operand) from the packed
integers of the destination operand (first operand), and stores the packed integer results in the
destination operand. The source operand can be an MMX(TM) technology register or a 64-bit memory location,
or it can be an XMM register or a 128-bit memory location. The destination operand can be an MMX or an XMM
register.
The PSUBB instruction subtracts packed byte integers. When an individual result is too large or too small
to be represented in a byte, the result is wrapped around and the low 8 bits are written to the
destination element.

:param cpu: current CPU.
:param dest: destination operand.
:param src: source operand.


@instruction<EOL><INDENT>def MOVHPD(cpu, dest, src):<DEDENT>

if src.size == <NUM_LIT>:<EOL><INDENT>assert dest.size == <NUM_LIT:64><EOL>dest.write(Operators.EXTRACT(src.read(), <NUM_LIT:64>, <NUM_LIT:64>))<EOL><DEDENT>else:<EOL><INDENT>assert src.size == <NUM_LIT:64> and dest.size == <NUM_LIT><EOL>value = Operators.EXTRACT(dest.read(), <NUM_LIT:0>, <NUM_LIT:64>)  <EOL>dest.write(Operators.CONCAT(<NUM_LIT>, src.read(), value))<EOL><DEDENT>

Moves high packed double-precision floating-point value.

Moves a double-precision floating-point value from the source operand (second operand) and the
destination operand (first operand). The source and destination operands can be an XMM register
or a 64-bit memory location. This instruction allows double-precision floating-point values to be moved
to and from the high quadword of an XMM register and memory. It cannot be used for register to
register or memory to memory moves. When the destination operand is an XMM register, the low quadword
of the register remains unchanged.

:param cpu: current CPU.
:param dest: destination operand.
:param src: source operand.


counter_name = {<NUM_LIT:16>: '<STR_LIT>', <NUM_LIT:32>: '<STR_LIT>', <NUM_LIT:64>: '<STR_LIT>'}[cpu.address_bit_size]<EOL>counter = cpu.write_register(counter_name, cpu.read_register(counter_name) - <NUM_LIT:1>)<EOL>cpu.PC = Operators.ITEBV(cpu.address_bit_size, counter != <NUM_LIT:0>, (cpu.PC + target.read()) & ((<NUM_LIT:1> << target.size) - <NUM_LIT:1>), cpu.PC + cpu.instruction.size)<EOL>

Loops if ECX counter is nonzero.

:param cpu: current CPU.
:param target: destination operand.


if imm is None:<EOL><INDENT>imm = <NUM_LIT:10><EOL><DEDENT>else:<EOL><INDENT>imm = imm.read()<EOL><DEDENT>cpu.AH = Operators.UDIV(cpu.AL, imm)<EOL>cpu.AL = Operators.UREM(cpu.AL, imm)<EOL>cpu._calculate_logic_flags(<NUM_LIT:8>, cpu.AL)<EOL>

ASCII adjust AX after multiply.

Adjusts the result of the multiplication of two unpacked BCD values
to create a pair of unpacked (base 10) BCD values. The AX register is
the implied source and destination operand for this instruction. The AAM
instruction is only useful when it follows a MUL instruction that multiplies
(binary multiplication) two unpacked BCD values and stores a word result
in the AX register. The AAM instruction then adjusts the contents of the
AX register to contain the correct 2-digit unpacked (base 10) BCD result.

The SF, ZF, and PF flags are set according to the resulting binary value in the AL register.

This instruction executes as described in compatibility mode and legacy mode.
It is not valid in 64-bit mode.::

        tempAL  =  AL;
        AH  =  tempAL / 10;
        AL  =  tempAL MOD 10;

:param cpu: current CPU.


dest.write(Operators.ITEBV(dest.size, Operators.AND(cpu.CF == False, cpu.ZF == False), <NUM_LIT:1>, <NUM_LIT:0>))<EOL>

Sets byte if not below or equal.

:param cpu: current CPU.
:param dest: destination operand.


dest.write(Operators.ITEBV(dest.size, cpu.SF == cpu.OF, <NUM_LIT:1>, <NUM_LIT:0>))<EOL>

Sets byte if greater or equal.

:param cpu: current CPU.
:param dest: destination operand.


cpu.PC = Operators.ITEBV(cpu.address_bit_size, (cpu.SF == cpu.OF), target.read(), cpu.PC)<EOL>

Jumps short if not less.

:param cpu: current CPU.
:param target: destination operand.


counter_name = {<NUM_LIT:16>: '<STR_LIT>', <NUM_LIT:32>: '<STR_LIT>', <NUM_LIT:64>: '<STR_LIT>'}[cpu.address_bit_size]<EOL>counter = cpu.write_register(counter_name, cpu.read_register(counter_name) - <NUM_LIT:1>)<EOL>cpu.PC = Operators.ITEBV(cpu.address_bit_size, counter == <NUM_LIT:0>, (cpu.PC + dest.read()) & ((<NUM_LIT:1> << dest.size) - <NUM_LIT:1>), cpu.PC + cpu.instruction.size)<EOL>

Loops according to ECX counter.

Performs a loop operation using the ECX or CX register as a counter.
Each time the LOOP instruction is executed, the count register is decremented,
then checked for 0. If the count is 0, the loop is terminated and program
execution continues with the instruction following the LOOP instruction.
If the count is not zero, a near jump is performed to the destination
(target) operand, which is presumably the instruction at the beginning
of the loop. If the address-size attribute is 32 bits, the ECX register
is used as the count register; otherwise the CX register is used::

        IF address_bit_size  =  32
        THEN
            Count is ECX;
        ELSE (* address_bit_size  =  16 *)
            Count is CX;
        FI;
        Count  =  Count - 1;

        IF (Count  0)  =  1
        THEN
            EIP  =  EIP + SignExtend(DEST);
            IF OperandSize  =  16
            THEN
                EIP  =  EIP AND 0000FFFFH;
            FI;
        ELSE
            Terminate loop and continue program execution at EIP;
        FI;

:param cpu: current CPU.
:param dest: destination operand.


cpu.PC = Operators.ITEBV(cpu.address_bit_size, cpu.ZF, target.read(), cpu.PC)<EOL>

Jumps short if zero.

:param cpu: current CPU.
:param target: destination operand.


dest.write(Operators.ITEBV(dest.size, cpu.CF, <NUM_LIT:1>, <NUM_LIT:0>))<EOL>

Sets byte if below.

:param cpu: current CPU.
:param dest: destination operand.


dest.write(Operators.ITEBV(dest.size, cpu.CF == False, <NUM_LIT:1>, <NUM_LIT:0>))<EOL>

Sets byte if not below.

:param cpu: current CPU.
:param dest: destination operand.


if op0.read() != <NUM_LIT>:<EOL><INDENT>logger.warning("<STR_LIT>")<EOL><DEDENT>raise Interruption(op0.read())<EOL>

Calls to interrupt procedure.

The INT n instruction generates a call to the interrupt or exception handler specified
with the destination operand. The INT n instruction is the  general mnemonic for executing
a software-generated call to an interrupt handler. The INTO instruction is a special
mnemonic for calling overflow exception (#OF), interrupt vector number 4. The overflow
interrupt checks the OF flag in the EFLAGS register and calls the overflow interrupt handler
if the OF flag is set to 1.

:param cpu: current CPU.
:param op0: destination operand.


arg0 = dest.read()<EOL>res = dest.write(arg0 + <NUM_LIT:1>)<EOL>res &= (<NUM_LIT:1> << dest.size) - <NUM_LIT:1><EOL>SIGN_MASK = <NUM_LIT:1> << (dest.size - <NUM_LIT:1>)<EOL>cpu.AF = ((arg0 ^ <NUM_LIT:1>) ^ res) & <NUM_LIT> != <NUM_LIT:0><EOL>cpu.ZF = res == <NUM_LIT:0><EOL>cpu.SF = (res & SIGN_MASK) != <NUM_LIT:0><EOL>cpu.OF = res == SIGN_MASK<EOL>cpu.PF = cpu._calculate_parity_flag(res)<EOL>

Increments by 1.

Adds 1 to the destination operand, while preserving the state of the
CF flag. The destination operand can be a register or a memory location.
This instruction allows a loop counter to be updated without disturbing
the CF flag. (Use a ADD instruction with an immediate operand of 1 to
perform an increment operation that does updates the CF flag.)::

        DEST  =  DEST +1;

:param cpu: current CPU.
:param dest: destination operand.


@instruction<EOL><INDENT>def ROR(cpu, dest, src):<DEDENT>

OperandSize = dest.size<EOL>count = src.read()<EOL>countMask = {<NUM_LIT:8>: <NUM_LIT>,<EOL><NUM_LIT:16>: <NUM_LIT>,<EOL><NUM_LIT:32>: <NUM_LIT>,<EOL><NUM_LIT:64>: <NUM_LIT>}[OperandSize]<EOL>tempCount = Operators.ZEXTEND((count & countMask) % (OperandSize), OperandSize)<EOL>value = dest.read()<EOL>newValue = (value >> tempCount) | (value << (OperandSize - tempCount))<EOL>dest.write(newValue)<EOL>cpu.CF = Operators.ITE(tempCount != <NUM_LIT:0>, ((newValue >> (OperandSize - <NUM_LIT:1>)) & <NUM_LIT>) == <NUM_LIT:1>, cpu.CF)<EOL>s_MSB = ((newValue >> (OperandSize - <NUM_LIT:1>)) & <NUM_LIT>) == <NUM_LIT:1><EOL>s_MSB2 = ((newValue >> (OperandSize - <NUM_LIT:2>)) & <NUM_LIT>) == <NUM_LIT:1><EOL>cpu.OF = Operators.ITE(tempCount == <NUM_LIT:1>, s_MSB ^ s_MSB2, cpu.OF)<EOL>

Rotates right (ROR).

Shifts (rotates) the bits of the first operand (destination operand) the number of bit positions specified in the
second operand (count operand) and stores the result in the destination operand. The destination operand can be
a register or a memory location; the count operand is an unsigned integer that can be an immediate or a value in
the CL register. In legacy and compatibility mode, the processor restricts the count to a number between 0 and 31
by masking all the bits in the count operand except the 5 least-significant bits.

The rotate right (ROR) instruction shift all the bits toward less significant bit positions, except
for the least-significant bit, which is rotated to the most-significant bit location.

:param cpu: current CPU.
:param dest: destination operand.
:param src: count operand.


cpu.PC = Operators.ITEBV(cpu.address_bit_size, cpu.RCX == <NUM_LIT:0>, target.read(), cpu.PC)<EOL>

Jumps short if RCX register is 0.

:param cpu: current CPU.
:param target: destination operand.


@instruction<EOL><INDENT>def VMOVDQU(cpu, dest, src):<DEDENT>

<EOL>dest.write(src.read())<EOL>

Move Unaligned Double Quadword

Moves 128 bits of packed integer values from the source operand (second operand)
to the destination operand (first operand). This instruction can be used to load
an XMM register from a 128-bit memory location, to store the contents of an XMM
register into a 128-bit memory location, or to move data between two XMM registers.
When the source or destination operand is a memory operand, the operand may be
unaligned on a 16-byte boundary without causing a general-protection exception
(#GP) to be generated.

    VMOVDQU (VEX.128 encoded version)
    DEST[127:0] <- SRC[127:0]
    DEST[VLMAX-1:128] <- 0
    VMOVDQU (VEX.256 encoded version)
    DEST[255:0] <- SRC[255:0]


dest.write(Operators.ITEBV(dest.size, cpu.PF, <NUM_LIT:1>, <NUM_LIT:0>))<EOL>

Sets byte if parity even.

:param cpu: current CPU.
:param dest: destination operand.


res = Operators.SEXTEND(cpu.RAX, <NUM_LIT:64>, <NUM_LIT>)<EOL>cpu.RAX = Operators.EXTRACT(res, <NUM_LIT:0>, <NUM_LIT:64>)<EOL>cpu.RDX = Operators.EXTRACT(res, <NUM_LIT:64>, <NUM_LIT:64>)<EOL>


dest.write(cpu.pop(dest.size))<EOL>

Pops a value from the stack.

Loads the value from the top of the stack to the location specified
with the destination operand and then increments the stack pointer.

:param cpu: current CPU.
:param dest: destination operand.


dest.write(Operators.ITEBV(dest.size, Operators.OR(cpu.CF, cpu.ZF), <NUM_LIT:1>, <NUM_LIT:0>))<EOL>

Sets byte if below or equal.

:param cpu: current CPU.
:param dest: destination operand.


@instruction<EOL><INDENT>def XCHG(cpu, dest, src):<DEDENT>

temp = dest.read()<EOL>dest.write(src.read())<EOL>src.write(temp)<EOL>

Exchanges register/memory with register.

Exchanges the contents of the destination (first) and source (second)
operands. The operands can be two general-purpose registers or a register
and a memory location. If a memory operand is referenced, the processor's
locking protocol is automatically implemented for the duration of the
exchange operation, regardless of the presence or absence of the LOCK
prefix or of the value of the IOPL.
This instruction is useful for implementing semaphores or similar data
structures for process synchronization.
The XCHG instruction can also be used instead of the BSWAP instruction
for 16-bit operands::

        TEMP  =  DEST
        DEST  =  SRC
        SRC  =  TEMP

:param cpu: current CPU.
:param dest: destination operand.
:param src: source operand.


@instruction<EOL><INDENT>def CMP(cpu, src1, src2):<DEDENT>

arg0 = src1.read()<EOL>arg1 = Operators.SEXTEND(src2.read(), src2.size, src1.size)<EOL>cpu._calculate_CMP_flags(src1.size, arg0 - arg1, arg0, arg1)<EOL>

Compares two operands.

Compares the first source operand with the second source operand and sets the status flags
in the EFLAGS register according to the results. The comparison is performed by subtracting
the second operand from the first operand and then setting the status flags in the same manner
as the SUB instruction. When an immediate value is used as an operand, it is sign-extended to
the length of the first operand::

        temp  =  SRC1 - SignExtend(SRC2);
        ModifyStatusFlags; (* Modify status flags in the same manner as the SUB instruction*)

The CF, OF, SF, ZF, AF, and PF flags are set according to the result.

:param cpu: current CPU.
:param dest: destination operand.
:param src: source operand.


cpu.push(cpu.EFLAGS, <NUM_LIT:16>)<EOL>

Pushes FLAGS register onto the stack.

:param cpu: current CPU.


Not implemented.

Performs no operation.


def __init__(self, regfile, memory, *args, **kwargs):

super().__init__(regfile, memory, *args, **kwargs)<EOL>self._segments = {}<EOL>

Builds a CPU model.
:param regfile: regfile object for this CPU.
:param memory: memory object for this CPU.


size = dest.size<EOL>cmp_reg_name_l = {<NUM_LIT:64>: '<STR_LIT>', <NUM_LIT>: '<STR_LIT>'}[size]<EOL>cmp_reg_name_h = {<NUM_LIT:64>: '<STR_LIT>', <NUM_LIT>: '<STR_LIT>'}[size]<EOL>src_reg_name_l = {<NUM_LIT:64>: '<STR_LIT>', <NUM_LIT>: '<STR_LIT>'}[size]<EOL>src_reg_name_h = {<NUM_LIT:64>: '<STR_LIT>', <NUM_LIT>: '<STR_LIT>'}[size]<EOL>cmph = cpu.read_register(cmp_reg_name_h)<EOL>cmpl = cpu.read_register(cmp_reg_name_l)<EOL>srch = cpu.read_register(src_reg_name_h)<EOL>srcl = cpu.read_register(src_reg_name_l)<EOL>cmp0 = Operators.CONCAT(size, cmph, cmpl)<EOL>src0 = Operators.CONCAT(size, srch, srcl)<EOL>arg_dest = dest.read()<EOL>cpu.ZF = arg_dest == cmp0<EOL>dest.write(<EOL>Operators.ITEBV(size, cpu.ZF,<EOL>Operators.CONCAT(size, srch, srcl),<EOL>arg_dest)<EOL>)<EOL>cpu.write_register(cmp_reg_name_l, Operators.ITEBV(size // <NUM_LIT:2>, cpu.ZF, cmpl,<EOL>Operators.EXTRACT(arg_dest, <NUM_LIT:0>, size // <NUM_LIT:2>)))<EOL>cpu.write_register(cmp_reg_name_h, Operators.ITEBV(size // <NUM_LIT:2>, cpu.ZF, cmph,<EOL>Operators.EXTRACT(arg_dest, size // <NUM_LIT:2>, size // <NUM_LIT:2>)))<EOL>

Compares and exchanges bytes.

Compares the 64-bit value in EDX:EAX (or 128-bit value in RDX:RAX if
operand size is 128 bits) with the operand (destination operand). If
the values are equal, the 64-bit value in ECX:EBX (or 128-bit value in
RCX:RBX) is stored in the destination operand.  Otherwise, the value in
the destination operand is loaded into EDX:EAX (or RDX:RAX)::

        IF (64-Bit Mode and OperandSize = 64)
        THEN
            IF (RDX:RAX = DEST)
            THEN
                ZF = 1;
                DEST = RCX:RBX;
            ELSE
                ZF = 0;
                RDX:RAX = DEST;
            FI
        ELSE
            IF (EDX:EAX = DEST)
            THEN
                ZF = 1;
                DEST = ECX:EBX;
            ELSE
                ZF = 0;
                EDX:EAX = DEST;
            FI;
        FI;

:param cpu: current CPU.
:param dest: destination operand.


CHEADER = '<STR_LIT>'<EOL>CBLUE = '<STR_LIT>'<EOL>CGREEN = '<STR_LIT>'<EOL>CWARNING = '<STR_LIT>'<EOL>CFAIL = '<STR_LIT>'<EOL>CEND = '<STR_LIT>'<EOL>pos = <NUM_LIT:0><EOL>result = "<STR_LIT>"<EOL>try:<EOL><INDENT>instruction = self.instruction<EOL>result += f"<STR_LIT>"<EOL><DEDENT>except BaseException:<EOL><INDENT>result += "<STR_LIT>"<EOL><DEDENT>regs = ('<STR_LIT>', '<STR_LIT>', '<STR_LIT>', '<STR_LIT>', '<STR_LIT>', '<STR_LIT>', '<STR_LIT>', '<STR_LIT>', '<STR_LIT>')<EOL>for reg_name in regs:<EOL><INDENT>value = self.read_register(reg_name)<EOL>if issymbolic(value):<EOL><INDENT>result += f'<STR_LIT>'<EOL><DEDENT>else:<EOL><INDENT>result += f'<STR_LIT>'<EOL><DEDENT>pos = <NUM_LIT:0><EOL><DEDENT>pos = <NUM_LIT:0><EOL>for reg_name in ['<STR_LIT>', '<STR_LIT>', '<STR_LIT>', '<STR_LIT>', '<STR_LIT>', '<STR_LIT>', '<STR_LIT>', '<STR_LIT>']:<EOL><INDENT>value = self.read_register(reg_name)<EOL>if issymbolic(value):<EOL><INDENT>result += f'<STR_LIT>'<EOL><DEDENT>else:<EOL><INDENT>result += f'<STR_LIT>'<EOL><DEDENT>pos = <NUM_LIT:0><EOL><DEDENT>for reg_name in ['<STR_LIT>', '<STR_LIT>', '<STR_LIT>', '<STR_LIT>', '<STR_LIT>', '<STR_LIT>']:<EOL><INDENT>base, size, ty = self.get_descriptor(self.read_register(reg_name))<EOL>result += f'<STR_LIT>'<EOL><DEDENT>for reg_name in ['<STR_LIT>', '<STR_LIT>', '<STR_LIT>', '<STR_LIT>', '<STR_LIT>', '<STR_LIT>', '<STR_LIT>', '<STR_LIT>', '<STR_LIT>']:<EOL><INDENT>value = getattr(self, reg_name)<EOL>result += f'<STR_LIT>'<EOL>pos = <NUM_LIT:0><EOL><DEDENT>return result<EOL>

Returns a string representation of cpu state

:rtype: str
:return: a string containing the name and current value for all the registers.


cpu.PC = Operators.ITEBV(cpu.address_bit_size, cpu.ECX == <NUM_LIT:0>, target.read(), cpu.PC)<EOL>

Jumps short if ECX register is 0.

:param cpu: current CPU.
:param target: destination operand.


@instruction<EOL><INDENT>def SAL(cpu, dest, src):<DEDENT>

OperandSize = dest.size<EOL>count = src.read()<EOL>countMask = {<NUM_LIT:8>: <NUM_LIT>,<EOL><NUM_LIT:16>: <NUM_LIT>,<EOL><NUM_LIT:32>: <NUM_LIT>,<EOL><NUM_LIT:64>: <NUM_LIT>}[OperandSize]<EOL>tempCount = Operators.ZEXTEND(count & countMask, dest.size)<EOL>tempDest = value = dest.read()<EOL>res = dest.write(Operators.ITEBV(dest.size, tempCount == <NUM_LIT:0>, tempDest, value << tempCount))<EOL>MASK = (<NUM_LIT:1> << OperandSize) - <NUM_LIT:1><EOL>SIGN_MASK = <NUM_LIT:1> << (OperandSize - <NUM_LIT:1>)<EOL>cpu.CF = Operators.OR(Operators.AND(tempCount == <NUM_LIT:0>, cpu.CF), Operators.AND(tempCount != <NUM_LIT:0>, (tempDest & (<NUM_LIT:1> << (OperandSize - tempCount)) != <NUM_LIT:0>)))<EOL>cpu.OF = Operators.ITE(tempCount != <NUM_LIT:0>, (cpu.CF) ^ (((res >> (OperandSize - <NUM_LIT:1>)) & <NUM_LIT>) == <NUM_LIT:1>), cpu.OF)<EOL>cpu.SF = Operators.OR(Operators.AND(tempCount == <NUM_LIT:0>, cpu.SF), Operators.AND(tempCount != <NUM_LIT:0>, (res & SIGN_MASK) != <NUM_LIT:0>))<EOL>cpu.ZF = Operators.OR(Operators.AND(tempCount == <NUM_LIT:0>, cpu.ZF), Operators.AND(tempCount != <NUM_LIT:0>, res == <NUM_LIT:0>))<EOL>cpu.PF = Operators.OR(Operators.AND(tempCount == <NUM_LIT:0>, cpu.PF), Operators.AND(tempCount != <NUM_LIT:0>, cpu._calculate_parity_flag(res)))<EOL>

The shift arithmetic left.

Shifts the bits in the first operand (destination operand) to the left or right by the number of bits specified in the
second operand (count operand). Bits shifted beyond the destination operand boundary are first shifted into the CF
flag, then discarded. At the end of the shift operation, the CF flag contains the last bit shifted out of the destination
operand.

:param cpu: current CPU.
:param dest: destination operand.
:param src: count operand.


cpu.PC = Operators.ITEBV(cpu.address_bit_size, False == cpu.ZF, target.read(), cpu.PC)<EOL>

Jumps short if not equal.

:param cpu: current CPU.
:param target: destination operand.


@instruction<EOL><INDENT>def PSRLQ(cpu, dest, src):<DEDENT>

count = src.read()<EOL>count = Operators.ITEBV(src.size, Operators.UGT(count, <NUM_LIT>), <NUM_LIT:64>, count)<EOL>count = Operators.EXTRACT(count, <NUM_LIT:0>, <NUM_LIT:64>)<EOL>if dest.size == <NUM_LIT:64>:<EOL><INDENT>dest.write(dest.read() >> count)<EOL><DEDENT>else:<EOL><INDENT>hi = Operators.EXTRACT(dest.read(), <NUM_LIT:64>, <NUM_LIT:64>) >> count<EOL>low = Operators.EXTRACT(dest.read(), <NUM_LIT:0>, <NUM_LIT:64>) >> count<EOL>dest.write(Operators.CONCAT(<NUM_LIT>, hi, low))<EOL><DEDENT>

Shift Packed Data Right Logical

        Shifts the bits in the individual quadword in the destination operand to the right by
        the number of bits specified in the count operand . As the bits in the data elements
        are shifted right, the empty high-order bits are cleared (set to 0). If the value
        specified by the count operand is greater than  63, then the destination operand is set
        to all 0s.

        if(OperandSize == 64) {
                        //PSRLQ instruction with 64-bit operand:
                        if(Count > 63) Destination[64..0] = 0;
                        else Destination = ZeroExtend(Destination >> Count);
                }
                else {
                        //PSRLQ instruction with 128-bit operand:
                        if(Count > 15) Destination[128..0] = 0;
                        else {
                                Destination[0..63] = ZeroExtend(Destination[0..63] >> Count);
                                Destination[64..127] = ZeroExtend(Destination[64..127] >> Count);
                        }
                }


cpu.PC = Operators.ITEBV(cpu.address_bit_size, Operators.AND(cpu.CF == False, cpu.ZF == False), target.read(), cpu.PC)<EOL>

Jumps short if not below or equal.

:param cpu: current CPU.
:param target: destination operand.


@instruction<EOL><INDENT>def PSRLDQ(cpu, dest, src):<DEDENT>

<EOL>temp = Operators.EXTRACT(src.read(), <NUM_LIT:0>, <NUM_LIT:8>)<EOL>temp = Operators.ITEBV(src.size, temp > <NUM_LIT:15>, <NUM_LIT:16>, temp)<EOL>dest.write(dest.read() >> (temp * <NUM_LIT:8>))<EOL>

Packed shift right logical double quadword.

Shifts the destination operand (first operand) to the right by the number
of bytes specified in the count operand (second operand). The empty high-order
bytes are cleared (set to all 0s). If the value specified by the count
operand is greater than 15, the destination operand is set to all 0s.
The destination operand is an XMM register. The count operand is an 8-bit
immediate::

    TEMP  =  SRC;
    if (TEMP > 15) TEMP  =  16;
    DEST  =  DEST >> (temp * 8);

:param cpu: current CPU.
:param dest: destination operand.
:param src: count operand.


res = dest.write(~dest.read())<EOL>

One's complement negation.

Performs a bitwise NOT operation (each 1 is cleared to 0, and each 0
is set to 1) on the destination operand and stores the result in the destination
operand location::

    DEST  =  NOT DEST;

:param cpu: current CPU.
:param dest: destination operand.


@instruction<EOL><INDENT>def SBB(cpu, dest, src):<DEDENT>

cpu._SUB(dest, src, carry=True)<EOL>

Integer subtraction with borrow.

Adds the source operand (second operand) and the carry (CF) flag, and
subtracts the result from the destination operand (first operand). The
result of the subtraction is stored in the destination operand. The
destination operand can be a register or a memory location; the source
operand can be an immediate, a register, or a memory location.
(However, two memory operands cannot be used in one instruction.) The
state of the CF flag represents a borrow from a previous subtraction.
When an immediate value is used as an operand, it is sign-extended to
the length of the destination operand format.
The SBB instruction does not distinguish between signed or unsigned
operands. Instead, the processor evaluates the result for both data
types and sets the OF and CF flags to indicate a borrow in the signed
or unsigned result, respectively. The SF flag indicates the sign of the
signed result.  The SBB instruction is usually executed as part of a
multibyte or multiword subtraction in which a SUB instruction is
followed by a SBB instruction::

        DEST  =  DEST - (SRC + CF);

:param cpu: current CPU.
:param dest: destination operand.
:param src: source operand.


dest.write(Operators.ITEBV(dest.size, cpu.SF, <NUM_LIT:1>, <NUM_LIT:0>))<EOL>

Sets byte if sign.

:param cpu: current CPU.
:param dest: destination operand.


@instruction<EOL><INDENT>def PXOR(cpu, dest, src):<DEDENT>

res = dest.write(dest.read() ^ src.read())<EOL>

Logical exclusive OR.

Performs a bitwise logical exclusive-OR (XOR) operation on the quadword
source (second) and destination (first) operands and stores the result
in the destination operand location. The source operand can be an MMX(TM)
technology register or a quadword memory location; the destination operand
must be an MMX register. Each bit of the result is 1 if the corresponding
bits of the two operands are different; each bit is 0 if the corresponding
bits of the operands are the same::

    DEST  =  DEST XOR SRC;

:param cpu: current CPU.
:param dest: destination operand.
:param src: quadword source operand.


cpu.PC = Operators.ITEBV(cpu.address_bit_size, cpu.OF, target.read(), cpu.PC)<EOL>

Jumps short if overflow.

:param cpu: current CPU.
:param target: destination operand.


@instruction<EOL><INDENT>def SHR(cpu, dest, src):<DEDENT>

OperandSize = dest.size<EOL>count = Operators.ZEXTEND(src.read() & (OperandSize - <NUM_LIT:1>), OperandSize)<EOL>value = dest.read()<EOL>res = dest.write(value >> count)  <EOL>MASK = (<NUM_LIT:1> << OperandSize) - <NUM_LIT:1><EOL>SIGN_MASK = <NUM_LIT:1> << (OperandSize - <NUM_LIT:1>)<EOL>if issymbolic(count):<EOL><INDENT>cpu.CF = Operators.ITE(count != <NUM_LIT:0>,<EOL>((value >> Operators.ZEXTEND(count - <NUM_LIT:1>, OperandSize)) & <NUM_LIT:1>) != <NUM_LIT:0>,<EOL>cpu.CF)<EOL><DEDENT>else:<EOL><INDENT>if count != <NUM_LIT:0>:<EOL><INDENT>cpu.CF = Operators.EXTRACT(value, count - <NUM_LIT:1>, <NUM_LIT:1>) != <NUM_LIT:0><EOL><DEDENT><DEDENT>cpu.ZF = Operators.ITE(count != <NUM_LIT:0>, res == <NUM_LIT:0>, cpu.ZF)<EOL>cpu.SF = Operators.ITE(count != <NUM_LIT:0>, (res & SIGN_MASK) != <NUM_LIT:0>, cpu.SF)<EOL>cpu.OF = Operators.ITE(count != <NUM_LIT:0>, ((value >> (OperandSize - <NUM_LIT:1>)) & <NUM_LIT>) == <NUM_LIT:1>, cpu.OF)<EOL>cpu.PF = Operators.ITE(count != <NUM_LIT:0>, cpu._calculate_parity_flag(res), cpu.PF)<EOL>

Shift logical right.

The shift arithmetic right (SAR) and shift logical right (SHR)
instructions shift the bits of the destination operand to the right
(toward less significant bit locations). For each shift count, the
least significant bit of the destination operand is shifted into the CF
flag, and the most significant bit is either set or cleared depending
on the instruction type. The SHR instruction clears the most
significant bit.

:param cpu: current CPU.
:param dest: destination operand.
:param src: count operand.


@instruction<EOL><INDENT>def ADC(cpu, dest, src):<DEDENT>

cpu._ADD(dest, src, carry=True)<EOL>

Adds with carry.

Adds the destination operand (first operand), the source operand (second operand),
and the carry (CF) flag and stores the result in the destination operand. The state
of the CF flag represents a carry from a previous addition. When an immediate value
is used as an operand, it is sign-extended to the length of the destination operand
format. The ADC instruction does not distinguish between signed or unsigned operands.
Instead, the processor evaluates the result for both data types and sets the OF and CF
flags to indicate a carry in the signed or unsigned result, respectively. The SF flag
indicates the sign of the signed result. The ADC instruction is usually executed as
part of a multibyte or multiword addition in which an ADD instruction is followed by an
ADC instruction::

        DEST  =  DEST + SRC + CF;

The OF, SF, ZF, AF, CF, and PF flags are set according to the result.

:param cpu: current CPU.
:param dest: destination operand.
:param src: source operand.


@instruction<EOL><INDENT>def CMOVNP(cpu, dest, src):<DEDENT>

dest.write(Operators.ITEBV(dest.size, cpu.PF == False, src.read(), dest.read()))<EOL>

Conditional move - Not parity/parity odd.

Tests the status flags in the EFLAGS register and moves the source operand
(second operand) to the destination operand (first operand) if the given
test condition is true.

:param cpu: current CPU.
:param dest: destination operand.
:param src: source operand.


@instruction<EOL><INDENT>def PALIGNR(cpu, dest, src, offset):<DEDENT>

dest.write(<EOL>Operators.EXTRACT(<EOL>Operators.CONCAT(dest.size * <NUM_LIT:2>, dest.read(), src.read()),<EOL>offset.read() * <NUM_LIT:8>,<EOL>dest.size))<EOL>

ALIGNR concatenates the destination operand (the first operand) and the source
            operand (the second operand) into an intermediate composite, shifts the composite
            at byte granularity to the right by a constant immediate, and extracts the right-
            aligned result into the destination.


@instruction<EOL><INDENT>def LDS(cpu, dest, src):<DEDENT>

raise NotImplementedError("<STR_LIT>")<EOL>


@instruction<EOL><INDENT>def PUNPCKLQDQ(cpu, dest, src):<DEDENT>

cpu._PUNPCKL(dest, src, <NUM_LIT:64>)<EOL>

Interleaves the low-order quad-words of the source and destination operands.

Unpacks and interleaves the low-order data elements (bytes, words, doublewords, and quadwords)
of the destination operand (first operand) and source operand (second operand) into the
destination operand.

:param cpu: current CPU.
:param dest: destination operand.
:param src: source operand.


cpu.DF = False<EOL>

Clears direction flag.
Clears the DF flag in the EFLAGS register. When the DF flag is set to 0, string operations
increment the index registers (ESI and/or EDI)::

    DF  =  0;

:param cpu: current CPU.


return GetNBits(value, width)<EOL>

Return integer value of `value` as a bitstring of `width` width.

:param value: The value to convert.
:type value: int or long or BitVec
:param int width: The width of the bitstring to consider
:return: The integer value
:rtype int or long or BitVec