Patent ID: 12256545

DETAILED DESCRIPTION

Hereinafter, embodiments of the present disclosure will be described as follows with reference to the accompanying drawings.

FIG.1is a plan view illustrating a plan view illustrating a semiconductor device according to example embodiments.

FIGS.2A and2Bare cross-sectional views illustrating a semiconductor device according to example embodiments.FIG.2Ais a cross-sectional view taken along line I-I′ inFIG.1.FIG.2Bis a cross-sectional view taken along line II-II′ inFIG.1.

FIGS.3A and3Bare an enlarged view illustrating a portion of a semiconductor device and a perspective view illustrating a semiconductor device according to example embodiments of the present disclosure, respectively.FIG.3Ais an enlarged view illustrating region “A” inFIG.2A, andFIG.3Bis a perspective view illustrating region “A.”

FIG.4is an enlarged view illustrating a portion of a semiconductor device according to example embodiments, illustrating region “B” inFIG.2A.

Referring toFIGS.1to4, a semiconductor device100may include a peripheral circuit region PERI, which may be a first semiconductor structure including a first substrate201, and a memory cell region CELL, which may be a second semiconductor structure including a second substrate101. The memory cell region CELL may be disposed on the peripheral circuit region PERI. In some example embodiments, the cell region CELL may be disposed below the peripheral circuit region PERI.

The peripheral circuit region PERI may include the first substrate201, source/drain regions205and device isolation layers210in the first substrate201, circuit devices220disposed on the first substrate201, circuit contact plugs270, circuit interconnection lines280, and peripheral region insulating layer290.

The first substrate201may have an upper surface extending in the X-direction and the Y-direction. An active region may be defined in the first substrate201by the device isolation layers210. The source/drain regions205including impurities may be disposed in a portion of the active region. The first substrate201may include a semiconductor material, such as, for example, a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI compound semiconductor. The first substrate201may be provided as a bulk wafer or an epitaxial layer.

The circuit devices220may include a planar transistor. Each of the circuit devices220may include a circuit gate dielectric layer222, a spacer layer224, and a circuit gate electrode225. The source/drain regions205may be disposed in the first substrate201on both sides of the circuit gate electrode225.

The circuit contact plugs270and the circuit interconnection lines280may form a circuit interconnection structure electrically connected to the circuit devices220and the source/drain regions205. The circuit contact plugs270may have a cylindrical shape, and the circuit interconnection lines280may have a linear shape. The circuit contact plugs270and the circuit interconnection lines280may include a conductive material, such as, for example, tungsten (W), copper (Cu), aluminum (Al), or similar, and each of the components may further include a diffusion barrier. However, in example embodiments, the number of layers of the circuit contact plugs270and the circuit interconnection lines280and the arrangements thereof may be varied.

The peripheral region insulating layer290may be disposed to cover the circuit device220on the first substrate201. The peripheral region insulating layer290may be formed of an insulating material and may include one or more insulating layers.

The memory cell region CELL may include the second substrate101having a first region R1and a second region R2, gate electrodes130stacked on the second substrate101, the interlayer insulating layers120alternately stacked with the gate electrodes130, the channel structures CH disposed to penetrate the stack structure of the gate electrodes130, separation regions MS extending by penetrating the stack structure of the gate electrodes130, contact plugs170connected to the pad regions130P of the gate electrodes130and extending vertically, and contact insulating layers160surrounding the contact plugs170.

The memory cell region CELL may include first and second horizontal conductive layers102and104disposed below the gate electrodes130on the first region R1, horizontal insulating layer110disposed below the gate electrodes130on the second region R2, upper separation regions SS penetrating a portion of the gate electrodes130, sacrificial insulating layers118on an external side of the gate electrodes130, a substrate contact175connected to the second substrate101, through-vias180penetrating the sacrificial insulating layers118, upper interconnections185on the contact plugs170, and a cell region insulating layer190covering the gate electrodes130.

In the first region R1of the second substrate101, the gate electrodes130may be vertically stacked and the channel structures CH may be disposed, and the first region R1may be a region in which memory cells may be disposed. In the second region R2of the second substrate101, the gate electrodes130may extend by different lengths, and the second region R2may be a region that electrically connects the memory cells to the peripheral circuit region PERI. The second region R2may be disposed on at least one end of the first region R1in at least one direction, such as, for example, the X-direction. The second substrate101may be in the form of a plating layer, and may function as at least a portion of a common source line of the semiconductor device100.

The second substrate101may have an upper surface extending in the X-direction and the Y-direction. The second substrate101may include a semiconductor material, such as, for example, a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI compound semiconductor. For example, a group IV semiconductor may include silicon, germanium, or silicon-germanium. The second substrate101may further include impurities. The second substrate101may be provided as a polycrystalline semiconductor layer such as a polycrystalline silicon layer or an epitaxial layer.

The first and second horizontal conductive layers102and104may be stacked in order on the upper surface of the first region R1of the second substrate101. The first horizontal conductive layer102may not extend to the second region R2of the second substrate101, and the second horizontal conductive layer104may extend to the second region R2. The first horizontal conductive layer102may function as a portion of a common source line of the semiconductor device100, and for example, may function as a common source line together with the second substrate101. As illustrated in the enlarged view inFIG.2B, the first horizontal conductive layer102may be directly connected to the channel layer140around the channel layer140. The second horizontal conductive layer104may be in contact with the second substrate101in regions in which the first horizontal conductive layer102and the horizontal insulating layer110are not disposed. The second horizontal conductive layer104may cover an end of the first horizontal conductive layer102or the horizontal insulating layer110in the regions and may be bent to extend to the second substrate101.

The first and second horizontal conductive layers102and104may include a semiconductor material, such as, for example polycrystalline silicon. In this case, at least the first horizontal conductive layer102may be doped with impurities of the same conductivity type as that of the second substrate101, and the second horizontal conductive layer104may be a doped layer or a layer including impurities diffused from the first horizontal conductive layer102. However, the material of the second horizontal conductive layer104is not limited to the semiconductor material, and may be replaced with an insulating layer.

The horizontal insulating layer110may be disposed on the second substrate101side by side with the first horizontal conductive layer102in at least a portion of the second region R2. The horizontal insulating layer110may include first and second horizontal insulating layers111and112alternately stacked on the second region R2of the second substrate101. The horizontal insulating layer110may be layers remaining after a portion of the first horizontal conductive layer102are replaced with the first horizontal conductive layers102in the process of manufacturing the semiconductor device100.

The horizontal insulating layer110may include silicon oxide, silicon nitride, silicon carbide, or silicon oxynitride. The first horizontal insulating layers111and the second horizontal insulating layer112may include different insulating materials. For example, the first horizontal insulating layers111may be formed of the same material as that of the interlayer insulating layers120, and the second horizontal insulating layer112may be formed of a material different from that of the interlayer insulating layers120.

The substrate insulating layer121may be disposed to penetrate through the second substrate101, the horizontal insulating layer110, and the second horizontal conductive layer104in at least a portion of the second region R2. Also, the substrate insulating layer121may be disposed in the third region R3of the memory cell region CELL from which the second substrate101is removed. The third region R3may be, for example, a through-interconnection region disposed on an external side of the second substrate101and/or in the first region R1and the second region R2. The lower surface of the substrate insulating layer121may be coplanar with the lower surface of the second substrate101or may be disposed on a level lower than a level of the lower surface of the second substrate101.

In the second region R2, the substrate insulating layer121may be disposed to surround the contact plugs170in a plan view. The substrate insulating layer121may be disposed to surround the entire contact plugs170in a plan view, but example embodiments thereof are not limited thereto. The contact plugs170may be electrically separated from each other by the substrate insulating layer121. The substrate insulating layer121may include an insulating material, such as, for example, silicon oxide, silicon nitride, silicon carbide, or silicon oxynitride.

The gate electrodes130may be vertically stacked and spaced apart on the second substrate101and may form a stack structure. The gate electrodes130may include lower gate electrodes forming a gate of a ground select transistor, memory gate electrodes forming the plurality of memory cells, and upper gate electrodes forming gates of string select transistors. The number of the memory gate electrodes included in the memory cells may be determined according to capacity of the semiconductor device100. According to example embodiments, each of the number of the upper gate electrodes and the number of the lower gate electrodes may be 1 to 4 or more, and may have a structure the same as, similar to, or different from the memory gate electrodes. In example embodiments, the gate electrodes130may further include an erase gate electrode disposed above the upper gate electrodes and/or below the lower gate electrodes and forming an erase transistor used in an erase operation using a gate induced drain leakage (GIDL) phenomenon. Also, a portion of the gate electrodes130, such as, for example, memory gate electrodes130adjacent to the upper or lower gate electrodes, may be dummy gate electrodes.

The gate electrodes130may be separated from each other in the Y-direction by the separation regions MS continuously extending from the first region R1and the second region R2of the separation regions MS. The gate electrodes130between the separation regions MS may form a single memory block, but example embodiments of the memory block are not limited thereto. A portion of the gate electrodes130, such as, for example, the memory gate electrodes may form a single layer in a single memory block.

The gate electrodes130may be vertically stacked and spaced apart from each other on the first region R1and the second region R2, may extend by different lengths from the first region R1to the second region R2, and may form a step structure having a staircase shape in a portion of the second region R2. The gate electrodes130may be disposed to have a step structure even in the Y-direction. Due to the step structure, among the gate electrodes130, the lower gate electrode130may extend longer than the upper gate electrode130, such that the gate electrodes130may have regions having upper surfaces exposed upwardly from the interlayer insulating layers120and the other gate electrodes130, and the above regions may be referred to as pad regions130P. In each gate electrode130, the pad region130P may be a region including an end of the gate electrode130in the X-direction. The pad region130P may be a region of an uppermost gate electrode130in each region among the gate electrodes130included in the stack structure in the second region R2. The gate electrodes130may be connected to the contact plugs170in the pad regions130P, respectively. The gate electrodes130may have an increased thickness in the pad regions130P.

As illustrated inFIGS.3A and3B, the gate electrodes130may extend from the first region R1toward the second region R2by a first thickness T1, and may have a second thickness T2and a third thickness T3greater than the first thickness T1in the pad region130P marked by a dotted line inFIGS.3A and3B. The pad region130P may include a first pad portion130P1including a region in contact with the contact plug170and having a third thickness T3, and a second pad portion130P2surrounding the first pad portion130P1and having a third thickness T2less than the third thickness T3. The first pad portion130P1may include a region overlapping the contact plug170in the Z-direction, and may include a region overlapping the contact insulating layers160. The first pad portion130P1may be formed in a process different from a process of forming the second pad portion130P2, such that a boundary between the first pad portion130P1and the second pad portion130P2may be distinct.

For example, the second thickness T2may be in a range from about 120% to about 180% of the first thickness T1. The second thickness T2may be greater than a thickness of the thickest gate electrode130in the first region R1among the gate electrodes130. Differently from the second pad portion130P2, the second gate dielectric layer145B may not be disposed in the first pad portion130P1. Accordingly, the first pad portion130P1may have a third thickness T3greater than the second pad portion130P2by the thickness of the second gate dielectric layers145B on the upper and lower surfaces of the second pad portion130P2. In example embodiments, the length L1of the second pad portion130P2in the X-direction on one side of the first pad portion130P1may be varied, and the length of the second pad portion130P2in the X-direction on the other side of the first pad portion130P1may be varied.

The pad region130P, particularly the first pad portion130P1, may protrude toward the contact plug170around the contact plug170together with the contact insulating layers160disposed therebelow. Accordingly, a portion of an upper surface, a side surface, and a portion of a lower surface of the pad region130P may be in contact with the contact plug170. Since the pad region130P may be continuously in contact with the contact plug170through three surfaces, contact resistance may be reduced as compared to the example in which the pad region130P is in contact with the contact plug170only through the side surfaces.

A length L2of the pad region130P protruding from the interlayer insulating layers120toward the contact plug170may be substantially the same as a length L3of the contact insulating layers160protruding therebelow. In example embodiments, “substantially the same” may indicate that the elements may be the same or there may be difference in the range of deviations occurring in the manufacturing process, and even when the expression “substantially” is omitted, the configuration may be interpreted in the same manner. The lengths L2and L3of the protrusion may be, for example, a length on the center in the Z-direction, and the degree protrusion may be varied in example embodiments. The area in which the upper surface of the pad region130P is in contact with the contact plug170may be larger than the area in which the lower surface of the pad region130P is in contact with the contact plug170, and the relative relationship between the contact areas may be varied depending on a width of the contact plug170on the pad region130P, an inclination of the contact plug170, or the like.

The gate electrodes130may have side surfaces in direct contact with the contact insulating layers160below the pad region130P. That is, as illustrated inFIG.3A, the second gate dielectric layer145B may not be interposed between the gate electrodes130and the contact insulating layers160.

The gate electrodes130may include a metal material, such as, for example, tungsten (W). In example embodiments, the gate electrodes130may include polycrystalline silicon or a metal silicide material. In example embodiments, the gate electrodes130may further include a diffusion barrier, such as, for example, tungsten nitride (WN), tantalum nitride (TaN), or titanium nitride (TiN), or a combination thereof.

The interlayer insulating layers120may be disposed between the gate electrodes130. Similarly to the gate electrodes130, the interlayer insulating layers120may be spaced apart from each other in a direction perpendicular to the upper surface of the second substrate101and may extend in the X-direction. The interlayer insulating layers120may include an insulating material such as silicon oxide or silicon nitride.

The sacrificial insulating layers118may be disposed on the same level as the level of the gate electrodes130may have the same thickness as that of the gate electrodes130in the third region R3, and the side surfaces may be in contact with the gate electrodes130in a region not illustrated. The sacrificial insulating layers118may be disposed to surround the through-vias180in a plan view, and may be connected to each other between the through-vias180adjacent to each other. The sacrificial insulating layers118may be disposed to have a width the same as or different from that of the lower substrate insulating layer121. The sacrificial insulating layers118may be formed of an insulating material different from that of the interlayer insulating layers120, and may include, for example, silicon oxide, silicon nitride, or silicon oxynitride.

The separation regions MS may be disposed to penetrate the gate electrodes130and may extend in the X-direction in the first region R1and the second region R2. As illustrated inFIG.1, the separation regions MS may be disposed parallel to each other. Some of the separation regions MS may extend as an integrated portion along the first region R1and the second region R2, and the other portion may extend only to a portion of the second region R2, or may be intermittently disposed in the first region R1and the second region R2. However, in example embodiments, the arrangement order of the separation regions MS and a distance between the separation regions MS may be varied. As illustrated inFIG.2B, the separation regions MS may penetrate the entire gate electrodes130stacked on the second substrate101and may be connected to the second substrate101. A separation insulating layer105may be disposed in the separation regions MS.

The upper separation regions SS may extend in the X-direction between the separation regions MS. The upper separation regions SS may be disposed in a portion of the second region R2and the first region R1to penetrate a portion of the gate electrodes130including the uppermost gate electrode130of the gate electrodes130. As illustrated inFIG.2B, the upper separation regions SS may separate, for example, three gate electrodes130from each other in the Y-direction. However, the number of gate electrodes130separated by the upper separation regions SS may be varied in example embodiments. The upper separation regions SS may include an upper separation insulating layer103.

Each of the channel structures CH may form a single memory cell string, and may be spaced apart from each other while forming rows and columns on the first region R1. The channel structures CH may form a grid pattern on an x-y plane or may be disposed in a zigzag pattern in one direction. Each of the channel structures CH may have a columnar shape, and may have an inclined side surface of which a width may decrease toward the second substrate101depending on an aspect ratio. As illustrated inFIG.1, dummy channels DCH may be disposed in the second region R2. The dummy channels DCH may also be disposed in the second region R2and may work as a support during the process of manufacturing the semiconductor device100, and may have a structure the same as, similar to, or different from the channel structures CH. In example embodiments, the channel structures CH disposed adjacent to the end of the first region R1may also be dummy channels which do not substantially form a memory cell string.

The channel structures CH may include vertically stacked first and second channel structures CH1and CH2. The channel structures CH may have a shape in which the lower first channel structures CH1and the upper second channel structures CH2are connected to each other, and may have a bent portion due to a difference in width in the connection region. However, in example embodiments, the number of channel structures stacked in the Z-direction may be varied.

Each of the channel structures CH may include a channel layer140, a first gate dielectric layer145A, a channel filling insulating layer150, and a channel pad155disposed in the channel hole. As illustrated in the enlarged view inFIG.2B, the channel layer140may be formed in an annular shape surrounding the channel filling insulating layer150therein, or in example embodiments, the channel layer140may have a columnar shape such as a cylinder or a prism without the channel filling insulating layer150. The channel layer140may be connected to the first horizontal conductive layer102in a lower portion. The channel layer140may include a semiconductor material such as polycrystalline silicon or single crystal silicon.

The first gate dielectric layer145A may be disposed between the gate electrodes130and the channel layer140together with the second gate dielectric layer145B. Although not specifically illustrated, the first gate dielectric layer145A may include a tunneling layer, a charge storage layer, and a blocking layer stacked in order from the channel layer140. The tunneling layer may tunnel electric charges into the charge storage layer, and may include, for example, silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), or a combination thereof. The charge storage layer may be a charge trap layer or a floating gate conductive layer. The blocking layer may include silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), a high-k dielectric material, or a combination thereof.

The channel pad155may be disposed only on the upper end of the upper second channel structure CH2. The channel pad155may include, for example, doped polycrystalline silicon.

The channel layer140, the gate dielectric layer145, and the channel filling insulating layer150may be connected to each other between the first channel structure CH1and the second channel structure CH2. The upper interlayer insulating layer having a relatively great thickness may be disposed between the first channel structure CH1and the second channel structure CH2. However, the thicknesses and shapes of the interlayer insulating layers120and the upper interlayer insulating layer125may be varied in the example embodiments.

The second gate dielectric layer145B may extend along external surfaces of the gate electrodes130. The second gate dielectric layer145B may horizontally extend along upper and lower surfaces of the gate electrodes130, and may cover side surfaces of the gate electrodes130facing the channel structure CH and side surfaces of ends of the gate electrodes130. As illustrated inFIG.3A, in the pad regions130P, the second gate dielectric layer145B may extend to the second pad portion130P2and may not extend to the first pad portion130P1. However, in example embodiments, the second gate dielectric layer145B may not be provided. In this case, a structure in which the gate electrodes130may expand and may be disposed in the regions in which the second gate dielectric layer145B is disposed may be formed inFIG.3A.

The contact plugs170may be connected to the pad regions130P of the uppermost gate electrodes130in the second region R2. The contact plugs170may penetrate at least a portion of the cell region insulating layer190and may be connected to each of the pad regions130P of the gate electrodes130exposed upwardly. The contact plugs170may penetrate the gate electrodes130below the pad regions130P, may penetrate the horizontal insulating layer110, the second horizontal conductive layer104, and the second substrate101, and may be connected to the circuit interconnection lines280disposed in the peripheral circuit region PERI. The contact plugs170may be spaced apart from the gate electrodes130disposed below the pad regions130P by the contact insulating layers160. The contact plugs170may be spaced apart from the horizontal insulating layer110, the second horizontal conductive layer104, and the second substrate101by the substrate insulating layer121.

The contact plugs170may include lower and upper contact plugs disposed on a level corresponding to a level of the first and second channel structures CH1and CH2, and a bent portion formed by changes in widths may be formed between the lower and upper contact plugs. The contact plugs170may have a cylindrical shape of which a width may decrease toward the second substrate101due to an aspect ratio. The width of the contact plug170may discontinuously change above and below the pad region130P. As illustrated inFIG.3A, a second diameter D2of the contact plug170on the lower surface of the first pad portion130P1may be smaller than a first diameter D1of the contact plug170on the upper surface of the first pad portion130P1. The difference between the first diameter D1and the second diameter D2may be greater than a difference in consideration of the inclination of the contact plug170, which may be due to a relative degree of etching between the cell region insulating layer190and the interlayer insulating layers120when the semiconductor device100is manufactured.

As illustrated inFIGS.3A and3B, the pad region130P and the contact insulating layers160may be configured to protrude into the contact plug170from the interlayer insulating layers120around the contact plug170. The pad region130P and the contact insulating layers160may horizontally protrude toward the contact plug170. Accordingly, the external surface of the contact plug170may have protrusions corresponding to the interlayer insulating layers120and protruding to an external side. The contact plug170may be in contact with a portion of the upper surface, the side surface, and/or a portion of the lower surface of the protruding pad region130P, and may be in contact with a portion of the upper surface, the side surface, and/or a portion of the lower surface of each of the protruding contact insulating layers160.

The contact plugs170may include a conductive material, such as, for example, at least one of tungsten (W), copper (Cu), aluminum (Al), and/or alloys thereof. In some example embodiments, the contact plugs170may have an air gap therein. The contact plugs170may be disposed to penetrate the gate electrodes130and may be self-aligned in the pad regions130P, and may be in contact with the upper surface, the side surface, and/or the lower surface of the pad region130P, such that contact area may be secured.

The contact insulating layers160may be disposed to surround side surfaces of the contact plugs170below the pad regions130P in a plan view. The contact insulating layers160may be disposed on the same level as a level of the gate electrodes130, and may be disposed such that side surfaces of the contact insulating layers160may be in contact with the gate electrodes130. The thickness of the contact insulating layer160may be substantially the same as the sum of the thickness of the gate electrodes130and the thickness of the second gate dielectric layers145B on the upper and lower surfaces of the gate electrodes130. The contact insulating layers160may be spaced apart from each other in the Z-direction by the interlayer insulating layers120. The contact insulating layers160may be spaced apart from each other even between the contact plugs170adjacent to each other.

As illustrated inFIG.3B, internal side surfaces of the contact insulating layers160may surround the contact plugs170, and external side surfaces of the contact insulating layers160may be surrounded by gate electrodes130. The contact plugs170may be physically and electrically connected to a single gate electrode130in the pad region130P by the contact insulating layers160, and may be electrically separated from the gate electrodes130disposed therebelow.

The contact insulating layers160may include an insulating material, and may include a material different from that of the interlayer insulating layer120. The contact insulating layers160may include, for example, at least one of silicon nitride and silicon oxynitride.

The substrate contact175may be connected to the second substrate101on the external side of the gate electrodes130. A lower end of the substrate contact175may be disposed in the second substrate101.

The through-vias180may be disposed in the third region R3, may penetrate the memory cell region CELL, and may extend to the peripheral circuit region PERI. The through-vias180may connect the upper interconnections185of the memory cell region CELL to the circuit interconnection lines280of the peripheral circuit region PERI. The through-vias180may penetrate the stack structure of the sacrificial insulating layers118and the interlayer insulating layers120in a region in which the sacrificial insulating layers118remain without being replaced with the gate electrodes130.

As illustrated inFIG.4, the sacrificial insulating layers118may have a shape protruding toward the through-via180further than the interlayer insulating layers120around the through-via180. Accordingly, the external surface of the through-via180may have protrusions corresponding to the interlayer insulating layers120. However, in example embodiments, the degree of protrusion of the sacrificial insulating layers118may be varied.

Similar to the contact plugs170, the substrate contacts175and/or the through-vias180may also have bent portions on a level corresponding to the boundary between the first and second channel structures CH1and CH2.

The substrate contacts175and the through-vias180may be formed in the same process as the process of forming the contact plugs170and may include the same material. compared to the material of the substrate contacts175and the through-vias180, the material of the contact plugs170described above may be similar to or different.

The upper interconnections185may form a cell interconnection structure electrically connected to memory cells in the memory cell structure CELL. The upper interconnections185may be connected to the channel structures CH, the contact plugs170, the substrate contact175, and the through-vias180, and may be electrically connected to the channel structures CH and the gate electrodes130. InFIGS.2A and2B, the upper interconnections185are illustrated in the form of plugs, but example embodiments thereof is not limited thereto, and the upper interconnections185may have a line form. In example embodiments, the number of plugs and interconnection lines included in the cell interconnection structure may be varied. The upper interconnections185may include a metal, such as, for example, tungsten (W), copper (Cu), and/or aluminum (Al).

The cell region insulating layer190may be disposed to cover or overlap the second substrate101, the gate electrodes130on the second substrate101, and/or the peripheral region insulating layer290. The cell region insulating layer190may be formed of an insulating material, or may include a plurality of insulating layers.

FIGS.5A to5Care enlarged view illustrating a portion of a semiconductor device according to example embodiments, illustrating region corresponding toFIG.3A.

Referring toFIG.5A, in a semiconductor device100a, the shape of the second gate dielectric layer145B may be different from the example inFIG.3Ain the region adjacent to the contact plug170. In example embodiments, the second gate dielectric layer145B may further extend to the upper and lower surfaces of the pad region130P corresponding to a portion of the first pad portion130P1inFIG.3A. However, in the region in contact with the contact plug170, the second gate dielectric layer145B may be removed and may not be disposed on the upper surface, the side surface, and the lower surface of the pad region130P.

This structure may be manufactured by not removing the second gate dielectric layer145B from the upper and lower surfaces of the gate electrode130during the process described with reference toFIG.11Ibelow, and by removing the second gate dielectric layer145B before the contact plugs170is formed in a subsequent process, for example.

Referring toFIG.5B, in a semiconductor device100b, the shape of the second gate dielectric layer145B in the region adjacent to the contact plug170may be different from the examples inFIGS.3A and5A. In example embodiments, the second gate dielectric layer145B may further extend to the upper and lower surfaces of the pad region130P corresponding to the first pad portion130P1inFIG.3Aand may expose only the side surfaces of the pad region130P. That is, the second gate dielectric layer145B may cover the upper and lower surfaces of the pad region130P even in a region overlapping the contact plug170.

This structure may be manufactured by not performing the process of removing the second gate dielectric layer145B from the upper and lower surfaces of the gate electrode130among the processes described with reference toFIG.11Ibelow.

Referring toFIG.5C, in a semiconductor device100c, the contact plug170cmay further include a barrier layer172on sidewalls and a bottom surface of the contact hole in which the contact plug170cis disposed. A layer filling the contact hole on the barrier layer172may be referred to as a contact conductive layer174. The barrier layer172may include, for example, at least one of titanium (Ti), titanium nitride (TiN), tantalum (Ta), and/or tantalum nitride (TaN). The contact conductive layer174may include, for example, at least one of tungsten (W), copper (Cu), aluminum (Al), and/or alloys thereof. In this case, similarly to the contact plugs170c, the substrate contacts175and the through-vias180inFIG.2Amay include a barrier layer and a conductive layer. The structure of the contact plug170cmay be applied to other example embodiments.

FIGS.6A and6Bare a cross-sectional view illustrating a semiconductor device and an enlarged view illustrating a portion of a semiconductor device according to example embodiments.FIG.6Aillustrating a region corresponding toFIG.2A, andFIG.6Billustrates a region corresponding toFIG.3A.

Referring toFIGS.6A and6B, in a semiconductor device100d, the pad region130P and the contact insulating layers160may not protrude toward the contact plug170. Accordingly, the pad region130P may be connected to the contact plug170only through the side surface. The side surface of the pad region130P, the side surfaces of the contact insulating layers160, and the side surfaces of the interlayer insulating layers120, that are in contact with the contact plug170, may be disposed on a linear line perpendicular to the Z-direction or inclined along the Z-direction. Also, in the contact plug170, the width on the upper surface and the width on the lower surface of the pad region130P may be the same or may have only a difference according to an inclination.

This structure may be manufactured by not performing the processes described with reference toFIGS.11M and11Nbelow, or alternatively, by not performing the processes described with reference toFIGS.11L to11Nbelow and forming the pad region130P together while forming the contact plug170described with reference toFIG.11O. Accordingly, the process of manufacturing the semiconductor device100dmay be simplified. In the latter example, since the contact plug170and the first pad portion130P1are formed together, the interfacial surface therebetween may not be distinct, and only the interfacial surface between the first pad portion130P1and the second pad portion130P2may be distinct.

FIG.7is a cross-sectional view illustrating a semiconductor device according to example embodiments, a cross-sectional view corresponding toFIG.2A.

Referring toFIG.7, in a semiconductor device100e, the contact plugs170may not extend into the peripheral circuit region PERI, and lower ends of the contact plugs170may be disposed in the substrate insulating layer121.

In some example embodiments, lower ends of the contact plugs170may be disposed on the upper surface of the substrate insulating layer121. In some example embodiments, lower ends of the contact plugs170may not be disposed in the substrate insulating layer121and may be disposed in the second substrate101in which the substrate insulating layer121is not formed. In this case, the second substrate101may be divided into a plurality of portions such that the contact plugs170are not electrically connected to each other in the second region R2. In some embodiments, the lower ends of the contact plugs170may be disposed in an insulating region in the second substrate101extending from the upper surface of the second substrate101.

In example embodiments, the contact plugs170may be electrically connected to the circuit devices220of the peripheral circuit region PERI through the upper interconnection structure including the upper interconnections185and the through-vias180.

FIG.8is a cross-sectional view illustrating a semiconductor device according to example embodiments, a cross-sectional view corresponding toFIG.2A.

Referring toFIG.8, in a semiconductor device100f, the through-vias180fand the substrate insulating layers121fmay have shapes and/or structures different from those of the example embodiments inFIGS.2A and4.

Specifically, the through-vias180fmay be disposed to penetrate the sacrificial insulating layers118and the interlayer insulating layers120without protrusions disposed on the side surface. Also, the through-vias180fmay not include the bent portion on a level corresponding to a level of the boundary between the first and second channel structures CH1and CH2. The internal structures and materials of the through-vias180fmay be the same as, similar to, or different from those of the contact plugs170. The structure of the through-vias180fmay be formed as the through-vias180fare formed separately from the contact plugs170in a different process. In example embodiments, the substrate contact175may also have a shape different from that of the contact plugs170.

The substrate insulating layers121fmay be spaced apart from each other to surround the contact plugs170in a plan view in the second region R2, respectively. The substrate insulating layers121fmay be disposed to surround the side surface of each of the contact plugs170in a plan view.

These structures of the through-vias180fand the substrate insulating layers121fmay be applied independently of each other in example embodiments, and may be applied independently of each other in in the other example embodiments.

FIG.9is a cross-sectional view illustrating a semiconductor device according to example embodiments, illustrating a region corresponding toFIG.2B.

Referring toFIG.9, in a semiconductor device100g, the memory cell structure CELL may not include first and second horizontal conductive layers102and104on the second substrate101, differently from the example embodiment inFIGS.2A and2B. Accordingly, the substrate insulating layer121may penetrate the second substrate101in the second region R2. Also, the channel structure CHg may further include an epitaxial layer107.

The epitaxial layer107may be disposed on the second substrate101on the lower end of the channel structure CHg, and may be disposed on a side surface of the at least one of the gate electrodes130. The epitaxial layer107may be disposed in the recessed region of the second substrate101. The level of the lower surface of the epitaxial layer107may be higher than the level of the upper surface of the lowermost gate electrode130and may be lower than the level of the lower surface of the gate electrode130disposed above the lowermost gate electrode130, but example embodiments thereof are not limited thereto. The epitaxial layer107may be connected to the channel layer140through the upper surface of the epitaxial layer107. A gate insulating layer141may be further disposed between the epitaxial layer107and the lowermost gate electrode130.

FIG.10is a cross-sectional view illustrating a semiconductor device according to example embodiments, a cross-sectional view corresponding toFIG.2A.

Referring toFIG.10, a semiconductor device100hmay have a structure in which the peripheral circuit region PERI and the memory cell region CELL are vertically bonded to each other using a wafer bonding method. To this end, the peripheral circuit region PERI may further include first bonding vias295and first bonding pads298, and the memory cell region CELL may include the cell interconnection lines192, the second bonding vias195, the second bonding pads198, and a passivation layer191on the second substrate101.

The first bonding vias295may be disposed above the uppermost circuit interconnection lines280and may be connected to the circuit interconnection lines280. At least a portion of the first bonding pads298may be connected to the first bonding vias295on the first bonding vias295. The first bonding pads298may be connected to the second bonding pads198of the memory cell region CELL. The first bonding pads298may provide an electrical connection path according to bonding of the peripheral circuit region PERI to the memory cell region CELL together with the second bonding pads198. The first bonding vias295and the first bonding pads298may include a conductive material, such as, for example, copper (Cu).

The cell interconnection lines192may be disposed below the upper interconnections185and may be connected to the second bonding vias195. The cell interconnection lines192may be formed of a conductive material, and may include, for example, at least one of tungsten (W), aluminum (Al), and/or copper (Cu).

The second bonding vias195and the second bonding pads198may be disposed below the lowermost cell interconnection lines192. The second bonding vias195may connect the cell interconnection lines192to the second bonding pads198, and the second bonding pads198may be bonded to the first bonding pads298of the peripheral circuit region PERI. The second bonding vias195and the second bonding pads198may include a conductive material, such as, for example, copper (Cu).

The peripheral circuit region PERI and the memory cell region CELL may form a semiconductor structure, and may be bonded by copper (Cu)-to-copper (Cu) bonding by the first bonding pads298and the second bonding pads198. In addition to the copper (Cu)-to-copper (Cu) bonding, the peripheral circuit region PERI and the memory cell region CELL may be further bonded by dielectric-to-dielectric bonding. The dielectric-to-dielectric bonding may be bonded by dielectric layers forming a portion of each of the peripheral region insulating layer290and the cell region insulating layer190and surrounding each of the first bonding pads298and the second bonding pads198. Accordingly, the peripheral circuit region PERI and the memory cell region CELL may be bonded to each other without an adhesive layer.

FIGS.11A to11Oare cross-sectional views illustrating a method of manufacturing a semiconductor device according to example embodiments, cross-sectional views corresponding toFIG.2A.

FIGS.12A to12Fare enlarged views illustrating a method of manufacturing a semiconductor device, illustrating a portion of a semiconductor device, according to example embodiments.FIGS.12A to12Fillustrate region “A” inFIGS.11I to11N.

Referring toFIG.11A, a peripheral circuit region PERI including circuit devices220and circuit interconnection structures may be formed on the first substrate201, and a second substrate101on which the memory cell region CELL is provided, a horizontal insulating layer110, a second horizontal conductive layer104, and a substrate insulating layer121may be formed on the peripheral circuit region PERI.

First, device isolation layers210may be formed in the first substrate201, and the circuit gate dielectric layer222and the circuit gate electrode225may be formed in order on the first substrate201. The device isolation layers210may be formed by, for example, a shallow trench separation (STI) process. The circuit gate dielectric layer222and the circuit gate electrode225may be formed using an atomic layer deposition (ALD) process or a chemical vapor deposition (CVD) process. The circuit gate dielectric layer222may be formed of silicon oxide, and the circuit gate electrode225may be formed of at least one of polycrystalline silicon or a metal silicide layer, but example embodiments thereof are not limited thereto. Thereafter, a spacer layer224and source/drain regions205may be formed on both sidewalls of the circuit gate dielectric layer222and the circuit gate electrode225. In example embodiments, the spacer layer224may be formed of a plurality of layers. Thereafter, the source/drain regions205may be formed by performing an ion implantation process.

The circuit contact plugs270of the circuit interconnection structures may be formed by partially forming the insulating layer290in the peripheral region, removing a portion thereof by etching, and filling the conductive material. The circuit interconnection lines280may be formed by, for example, depositing a conductive material and patterning the conductive material.

The peripheral region insulating layer290may include a plurality of insulating layers. A portion of the peripheral region insulating layer290may be formed in each of processes of forming the circuit interconnection structures and, by forming a portion thereof above the uppermost circuit interconnection line280, such that the peripheral region insulating layer290may be formed to cover the circuit devices220and the circuit interconnection structures.

Thereafter, the second substrate101may be formed on the peripheral region insulating layer290. The second substrate101may be formed of, for example, polycrystalline silicon, and may be formed by a CVD process. Polycrystalline silicon included in the second substrate101may include impurities.

The first and second horizontal insulating layers111and112included in the horizontal insulating layer110may be alternately stacked on the second substrate101. The horizontal insulating layer110may be partially replaced with the first horizontal conductive layer102inFIG.2Athrough a subsequent process. The first horizontal insulating layers111may include a material different from that of the second horizontal insulating layer112. For example, the first horizontal insulating layers111may be formed of the same material as that of the interlayer insulating layers120, and the second horizontal insulating layer112may be formed of the same material as that of the sacrificial insulating layers118formed in a subsequent process. The horizontal insulating layer110may be partially removed by a patterning process in some regions, that is, for example, in the second region R2of the second substrate101.

The second horizontal conductive layer104may be formed on the horizontal insulating layer110, and may be in contact with the second substrate101in a region from which the horizontal insulating layer110is removed. Accordingly, the second horizontal conductive layer104may be bent along end portions of the horizontal insulating layer110, may cover the ends, and may extend to the second substrate101.

The substrate insulating layer121may be formed to penetrate the second substrate101in regions in which the contact plugs170(seeFIG.2A) are disposed among the third region R3and the second region R2of the memory cell structure CELL. The substrate insulating layer121may be formed by removing a portion of the second substrate101, the horizontal insulating layer110, and the second horizontal conductive layer104, and filling the insulating material therein. After filling the insulating material, a planarization process may be further performed using a chemical mechanical polishing (CMP) process. Accordingly, the upper surface of the substrate insulating layer121may be substantially coplanar with the upper surface of the second horizontal conductive layer104.

Referring toFIG.11B, the sacrificial insulating layers118and the interlayer insulating layers120included in the lower stack structure may be alternately stacked on the second horizontal conductive layer104, a step structure may be formed, and the sacrificial pad regions118P may be formed.

In this process, sacrificial insulating layers118and interlayer insulating layers120may be formed in a region in which the first channel structures CH1(seeFIG.2A) is disposed. An upper interlayer insulating layer125having a relatively great thickness may be formed in the uppermost portion. The sacrificial insulating layers118may be replaced with the gate electrodes130(seeFIG.2A) through a subsequent process.

The sacrificial insulating layers118may be formed of a material different from that of the interlayer insulating layers120. For example, the interlayer insulating layer120and the upper interlayer insulating layer125may be formed of at least one of silicon oxide and silicon nitride, and the sacrificial insulating layers118may be formed of a material different from a material of the interlayer insulating layer120, selected from among silicon, silicon oxide, silicon carbide, and/or silicon nitride. In example embodiments, the thicknesses of the interlayer insulating layers120may not be the same. Also, the thickness of the interlayer insulating layers120and the sacrificial insulating layers118and the number of the interlayer insulating layers120and the sacrificial insulating layers118may be varied from the illustrated examples.

Thereafter, a photolithography process and an etching process may be repeatedly performed on the sacrificial insulating layers118using a mask layer such that the upper sacrificial insulating layers118may extend shorter than the lower sacrificial insulating layers118in the second region R2. Accordingly, the sacrificial insulating layers118may form a step structure in a staircase shape by a predetermined unit.

Thereafter, by further forming sacrificial insulating layers118on the step structure, sacrificial pad regions118P disposed in the uppermost portion may be formed in each region. The sacrificial pad regions118P may be formed by, for example, forming a nitride layer covering the exposed upper and side surfaces of the sacrificial insulating layers118along the staircase shape of the lower stack structure, and remaining the nitride layer only on the upper surfaces of the sacrificial insulating layers118by partially removing the nitride layer. The thickness of the nitride layer may be in the range of about 20% to about 110% of the thickness of the sacrificial insulating layers118, but example embodiments thereof are not limited thereto. The process of partially removing the nitride layer may be performed after changing properties of horizontally deposited regions of the nitride layer using, for example, plasma. Accordingly, the sacrificial insulating layers118may have a relatively large thickness in the sacrificial pad regions118P.

Referring toFIG.11C, first vertical sacrificial layers116apenetrating the lower stack structure may be formed.

Firstly, a portion of the cell region insulating layer190covering or overlapping the lower stack structure of the sacrificial insulating layers118and the interlayer insulating layers120may be formed.

Thereafter, the first vertical sacrificial layers116amay be formed in a region of the first region R1corresponding to the first channel structures CH1(seeFIG.2A), and may be formed in a region of the second region R2in which the contact plugs170, the substrate contact175, and the through-vias180are disposed. The first vertical sacrificial layers116amay be formed to have different sizes depending on the regions in which the first vertical sacrificial layers116aare formed.

The first vertical sacrificial layers116amay be formed by forming lower holes to penetrate the lower stack structure, and depositing a material forming the first vertical sacrificial layers116ain the lower holes. The first vertical sacrificial layers116amay include, for example, polycrystalline silicon.

Referring toFIG.11D, an upper stack structure may be formed, and second vertical sacrificial layers116bpenetrating the upper stack structure may be formed.

A step structure may be formed by alternately stacking the sacrificial insulating layers118and the interlayer insulating layers120included in the upper stack structure on the lower stack structure, and the sacrificial pad regions118P may be formed. In this process, in the upper region in which the second channel structures CH2(seeFIG.2A) is disposed, the same process for the lower stack structure described above with reference toFIG.11Bmay be performed.

Thereafter, a portion of the cell region insulating layer190covering the upper stack structure of the sacrificial insulating layers118and the interlayer insulating layers120may be further formed, and second vertical sacrificial layers116bmay be formed. The second vertical sacrificial layers116bmay be formed by forming upper holes penetrating the upper stack structure and exposing upper ends of the first vertical sacrificial layers116a, and depositing a material included in the second vertical sacrificial layers116bin the upper holes. The second vertical sacrificial layers116bmay include, for example, polycrystalline silicon.

Referring toFIG.11E, in the first region R1, the first and second vertical sacrificial layers116aand116bmay be removed and channel structures CH may be formed.

Firstly, an upper separation region SS (seeFIG.2B) may be formed by partially removing a portion of the sacrificial insulating layers118and the interlayer insulating layers120. To form the upper separation region SS, a region in which the upper separation region SS is formed may be exposed using a mask layer, a predetermined number of the sacrificial insulating layers118and the interlayer insulating layers118may be removed from an uppermost portion, an insulating material may be deposited, thereby forming the upper separation insulating layer103(seeFIG.2B).

Thereafter, a mask layer ML exposing the first region R1may be formed on the upper stack structure, and channel structures CH may be formed in the first region R1. The channel structures CH may be formed by forming channel holes by removing the first and second vertical sacrificial layers116aand116band filling the channel holes. Specifically, the channel structures CH may be formed by forming the first gate dielectric layer145A, the channel layer140, the channel filling insulating layer150, and the channel pads155in order in the channel holes. The channel layer140may be formed on the first gate dielectric layer145A in the channel structures CH. The channel filling insulating layer150may be formed to fill the channel structures CH, and may be an insulating material. However, in example embodiments, the space between the channel layers140may be filled with a conductive material instead of the channel filling insulating layer150. The channel pads155may be formed of a conductive material, such as, for example, polycrystalline silicon.

Referring toFIG.11F, the first horizontal conductive layer102may be formed by partially removing the horizontal insulating layer110, and the first tunnel portions TL1may be formed by removing the sacrificial insulating layers118.

Firstly, the cell region insulating layer190may be further formed, and openings penetrating the sacrificial insulating layers118and the interlayer insulating layers120and extending to the second substrate101may be formed in a position corresponding to the separation regions MS (seeFIG.1).

Thereafter, an etch-back process may be performed while forming separate sacrificial spacer layers in the openings, such that the second horizontal insulating layer112may be exposed in the first region R1. The second horizontal insulating layer112may be selectively removed from the exposed region, and the upper and lower first horizontal insulating layers111may be removed. The first and second horizontal insulating layers111and112may be removed by, for example, a wet etching process. In the process of removing the first and second horizontal insulating layers111and112, a portion of the first gate dielectric layer145A exposed in the region from which the second horizontal insulating layer112is removed may also be removed. The first horizontal conductive layer102may be formed by depositing a conductive material in the region from which the first and second horizontal insulating layers111and112are removed, and the sacrificial spacer layers may be removed from the openings. Through this process, the first horizontal conductive layer102may be formed in the first region R1.

Thereafter, the sacrificial insulating layers118including the sacrificial pad regions118P may be selectively removed with respect to the interlayer insulating layers120, the second horizontal conductive layer104, and the substrate insulating layer121using wet etching, for example.

Referring toFIG.11G, second gate dielectric layers145B and gate electrodes130may be formed in the first tunnel portions TL1.

Second gate dielectric layers145B and gate electrodes130may be formed in the first tunnel portions TL1from which the sacrificial insulating layers118are removed. The second gate dielectric layers145B may be deposited before the gate electrodes130and may cover external surfaces of the gate electrodes130, such as, for example, upper surfaces, lower surfaces, and side surfaces. The pad regions130P of the gate electrodes130may be formed in the sacrificial pad regions118P.

The gate electrodes130may include a conductive material, such as, for example, a metal, polycrystalline silicon, or a metal silicide material. After the gate electrodes130are formed, a separation insulating layer105(seeFIG.2B) may be formed in the openings formed in the separation regions MS.

Referring toFIG.11H, contact holes MCH may be formed by forming upper openings OP in the second region R2, and by removing the first and second vertical sacrificial layers116aand116b.

When the cell region insulating layer190and/or other layers are formed on the second vertical sacrificial layers116bin the second region R2during the process, the upper openings OP may be formed to expose the upper ones of the second vertical sacrificial layers116bby removing the cell region insulating layer190and/or other layers. Accordingly, the specific shape and depth of the upper openings OP may be varied in example embodiments.

The contact holes MCH may be formed by removing the first and second vertical sacrificial layers116aand116bexposed through the upper openings OP.

Referring toFIGS.11I and12A, the second tunnel portions TL2may be formed by laterally removing a portion of the gate electrodes130exposed through the contact holes MCH.

The second tunnel portions TL2may be formed by removing the gate electrodes130and the second gate dielectric layers145B exposed through the contact holes MCH around the contact holes MCH by a predetermined length in the X-direction by applying an etchant through the contact holes MCH. The gate electrodes130and the second gate dielectric layers145B may be removed by, for example, a wet etching process. The gate electrodes130and the second gate dielectric layers145B may be removed together in a single process or may be removed in order in a plurality of consecutive processes. The second tunnel portions TL2may be formed to have substantially the same length on side surfaces around the contact holes MCH. In a region from which a portion of the pad regions130P is removed in the uppermost region, the second tunnel portions TL2may be formed to have a relatively large height.

Referring toFIGS.11J and12B, a preliminary contact insulating layer160P forming the contact insulating layers160(seeFIG.2A) may be formed in the second tunnel portions TL2.

The preliminary contact insulating layer160P may be formed such that the preliminary contact insulating layer160P may not fill the uppermost second tunnel portions TL2, which may be the pad regions130P, and may entirely fill the second tunnel portions TL2below the uppermost second tunnel portions TL2. The thickness of the preliminary contact insulating layer160P may be selected to be equal to or greater than a half the height of the second tunnel portions TL2disposed below the uppermost second tunnel portions TL2, and to be less than a half the height of the uppermost second tunnel portions TL2. For example, the thickness of the preliminary contact insulating layer160P may be about 25 nm or less, such as, for example, about 15 nm or less.

Referring toFIGS.11K and12C, the contact insulating layers160may be formed by partially removing the preliminary contact insulating layer160P.

For example, the preliminary contact insulating layer160P may be removed by a predetermined thickness using a wet etching process. Accordingly, the preliminary contact insulating layer160P may be removed from the uppermost second tunnel portions TL2and internal side walls of the contact holes MCH, and the contact insulating layers160filling the second tunnel portions TL2below the uppermost second tunnel portions TL2may be formed.

Referring toFIGS.11L and12D, the pad conductive layer130PL forming the first pad portions130P1(seeFIG.3A) of the pad regions130P may be formed.

The pad conductive layer130PL may be formed to fill the uppermost second tunnel portions TL2and to cover or overlap the internal side walls of the contact holes MCH. The pad conductive layer130PL may be formed by, for example, an ALD process.

Referring toFIGS.11M and12E, the first pad portions130P1of the pad regions130P may be formed by partially removing the pad conductive layer130PL.

For example, the pad conductive layer130PL may be removed by a predetermined thickness using a wet etching process. Accordingly, the pad conductive layer130PL may fill the uppermost second tunnel portions TL2such that the first pad portions130P1of the pad regions130P may be formed, and the pad conductive layer130PL may be removed from the internal side walls of the contact holes MCH. As such, since the first pad portions130P1are formed by a process different from the processes of forming the other regions, an interfacial surface with the second pad portions130P2may be distinct. Also, in some example embodiments, the first pad portions130P1may include a material different from that of the second pad portions130P2and the lower gate electrodes130.

Referring toFIGS.11N and12F, the interlayer insulating layers120and the cell region insulating layer190may be partially removed around the contact holes MCH.

The interlayer insulating layers120and the cell region insulating layer190exposed through the contact holes MCH around the contact holes MCH may be removed by a predetermined length in the X-direction by applying an etchant through the contact holes MCH. The interlayer insulating layers120and the cell region insulating layer190may be selectively removed by, for example, a wet etching process. Accordingly, the interlayer insulating layers120may be recessed below the pad regions130P such that the gate electrodes130and the contact insulating layers160may protrude further than the interlayer insulating layers120.

The inflow of the etchant may be relatively large on the pad regions130P, such that a relatively large amount of the cell region insulating layer190may be removed, and a relatively small amount of the interlayer insulating layers120may be removed. However, in example embodiments, the cell region insulating layer190and the interlayer insulating layers120may be removed by similar lengths.

In this process, the substrate insulating layer121may also be recessed below the contact holes MCH. In a region corresponding to the substrate contact175, the second horizontal insulating layer112may also be partially recessed around the contact holes MCH. Also, in the third region R3, the interlayer insulating layers120, the cell region insulating layer190, and the substrate insulating layer121may be partially recessed around the contact holes MCH such that the sacrificial insulating layers118may relatively protrude.

Referring toFIG.11O, contact plugs170, a substrate contact175, and through-vias180may be formed by depositing conductive material in the contact holes MCH.

The contact plugs170, the substrate contact175, and the through-vias180may be formed together, such that the contact plugs170, the substrate contact175, and the through-vias180may include the same material and may have the same internal structure. In example embodiments, the first and second vertical sacrificial layers116aand116bmay be preferentially formed, and the processes inFIGS.11H to11Omay be performed to form the contact plugs170, such that the contact plugs170may be self-aligned on the gate electrodes130.

In example embodiments, the pad region130P and the contact plug170may be formed of the same material. However, even in this case, since the pad region130P and the contact plug170are formed through different processes, a boundary may be distinct due to discontinuity of the crystal structure on the interfacial surface, presence of oxide on the interfacial surface, or the like.

Thereafter, referring back toFIG.2A, upper interconnection structures such as upper interconnections185may be further formed on the contact plugs170, the substrate contact175, and the through-vias180, such that the semiconductor device100may be manufactured.

FIG.13is a view illustrating a data storage system including a semiconductor device according to example embodiments.

Referring toFIG.13, a data storage system1000may include a semiconductor device1100and a controller1200electrically connected to the semiconductor device1100. The data storage system1000may be implemented as a storage device including one or a plurality of semiconductor devices1100or an electronic device including a storage device. For example, the data storage system1000may be implemented as a solid state drive (SSD) device, a universal serial bus (USB), a computing system, a medical device, or a communication device, including one or a plurality of semiconductor devices1100.

The semiconductor device1100may be implemented as a nonvolatile memory device, and may be implemented as the NAND flash memory device described with reference toFIGS.1to10, for example. The semiconductor device1100may include a first semiconductor structure1100F and a second semiconductor structure1100S on the first semiconductor structure1100F. In example embodiments, the first semiconductor structure1100F may be disposed on the side of the second semiconductor structure1100S. The first semiconductor structure1100F may be configured as a peripheral circuit structure including a decoder circuit1110, a page buffer1120, and a logic circuit1130. The second semiconductor structure1100S may be configured as a memory cell structure including a bit line BL, a common source line CSL, word lines WL, first and second gate upper lines UL1and UL2, first and second gate lower lines LL1and LL2, and memory cell strings CSTR between the bit line BL and the common source line CSL.

In the second semiconductor structure1100S, each of the memory cell strings CSTR may include lower transistors LT1and LT2adjacent to the common source line CSL, upper transistors UT1and UT2adjacent to the bit line BL, and a plurality of memory cell transistors MCT disposed between the lower transistors LT1and LT2and the upper transistors UT1and UT2. The number of the lower transistors LT1and LT2and the number of the upper transistors UT1and UT2may be varied in example embodiments.

In example embodiments, the upper transistors UT1and UT2may include a string select transistor, and the lower transistors LT1and LT2may include a ground select transistor. The gate lower lines LL1and LL2may be gate electrodes of the lower transistors LT1and LT2, respectively. The word lines WL may be gate electrodes of the memory cell transistors MCT, and the gate upper lines UL1and UL2may be gate electrodes of the upper transistors UT1and UT2, respectively.

In example embodiments, the lower transistors LT1and LT2may include a lower erase control transistor LT1and a ground select transistor LT2connected to each other in series. The upper transistors UT1and UT2may include a string select transistor UT1and an upper erase control transistor UT2connected to each other in series. At least one of the lower erase control transistor LT1and the upper erase control transistor UT1may be used for an erase operation of erasing data stored in the memory cell transistors MCT using a GIDL phenomenon.

The common source line CSL, the first and second gate lower lines LL1and LL2, the word lines WL, and the first and second gate upper lines UL1and UL2may be electrically connected to the decoder circuit1110through first connection interconnections1115extending from the first semiconductor structure1100F to the second semiconductor structure1100S. The bit lines BL may be electrically connected to the page buffer1120through second connection interconnections1125extending from the first semiconductor structure1100F to the second semiconductor structure1100S.

In the first semiconductor structure1100F, the decoder circuit1110and the page buffer1120may perform a control operation on at least one selected memory cell transistor among the plurality of memory cell transistors MCT. The decoder circuit1110and the page buffer1120may be controlled by the logic circuit1130. The semiconductor device1100may communicate with the controller1200through an input and output pad1101electrically connected to the logic circuit1130. The input and output pad1101may be electrically connected to the logic circuit1130through an input and output connection interconnection1135extending from the first semiconductor structure1100F to the second semiconductor structure1100S.

The controller1200may include a processor1210, a NAND controller1220, and a host interface1230. In example embodiments, the data storage system1000may include a plurality of semiconductor devices1100, and in this case, the controller1200may control the plurality of semiconductor devices1100.

The processor1210may control overall operation of the data storage system1000including the controller1200. The processor1210may operate according to a predetermined firmware, and may access the semiconductor device1100by controlling the NAND controller1220. The NAND controller1220may include a NAND interface1221for processing communication with the semiconductor device1100. Control commands for controlling the semiconductor device1100, data to be written in the memory cell transistors MCT of the semiconductor device1100, and data to be read from the memory cell transistors MCT of the semiconductor device1100may be transmitted through the NAND interface1221. The host interface1230may provide a communication function between the data storage system1000and an external host. When a control command is received from an external host through the host interface1230, the processor1210may control the semiconductor device1100in response to the control command.

FIG.14is a perspective view illustrating a data storage system including a semiconductor device according to example embodiments.

Referring toFIG.14, a data storage system2000according to example embodiments may include a main substrate2001, a controller2002mounted on the main substrate2001, one or more semiconductor packages2003, and a DRAM2004. The semiconductor package2003and the DRAM2004may be connected to the controller2002by interconnection patterns2005formed on the main substrate2001.

The main substrate2001or main board may include a connector2006including a plurality of pins coupled to an external host. The number and the arrangement of the plurality of pins in the connector2006may be varied depending on a communication interface between the data storage system2000and the external host. In example embodiments, the data storage system2000may communication with the external host through one of a universal serial bus (USB), a peripheral component interconnect express (PCI-Express), a serial advanced technology attachment (SATA), and an M-phy for universal flash storage (UFS). In example embodiments, the data storage system2000may operate by power supplied from the external host through the connector2006. The data storage system2000may further include a power management integrated circuit (PMIC) for distributing power supplied from the external host to the controller2002and the semiconductor package2003.

The controller2002may write data in the semiconductor package2003or may read data from the semiconductor package2003, and may improve an operation speed of the data storage system2000.

The DRAM2004may be configured as a buffer memory for mitigating a difference in speeds between the semiconductor package2003, a data storage space, and an external host. The DRAM2004included in the data storage system2000may also operate as a cache memory, and may provide a space for temporarily storing data in a control operation for the semiconductor package2003. When the DRAM2004is included in the data storage system2000, the controller2002further may include a DRAM controller for controlling the DRAM2004in addition to the NAND controller for controlling the semiconductor package2003.

The semiconductor package2003may include first and second semiconductor packages2003aand2003bspaced apart from each other. Each of the first and second semiconductor packages2003aand2003bmay be configured as a semiconductor package including a plurality of semiconductor chips2200. Each of the first and second semiconductor packages2003aand2003bmay include a package substrate2100, semiconductor chips2200on the package substrate2100, adhesive layers2300disposed on a lower surface of each of the semiconductor chips2200, a connection structure2400electrically connecting the semiconductor chips2200to the package substrate2100, and a molding layer2500covering or overlapping the semiconductor chips2200and the connection structure2400on the package substrate2100.

The package substrate2100may be configured as a printed circuit substrate including the package upper pads2130. Each of the semiconductor chips2200may include an input and output pad2210. The input and output pad2210may correspond to the input and output pad1101inFIG.13. Each of the semiconductor chips2200may include gate stack structures3210and channel structures3220. Each of the semiconductor chips2200may include the semiconductor device described with reference toFIGS.1to10.

In example embodiments, the connection structure2400may be a bonding wire electrically connecting the input and output pad2210to the package upper pads2130. Accordingly, in each of the first and second semiconductor packages2003aand2003b, the semiconductor chips2200may be electrically connected to each other through a bonding wire method, and may be electrically connected to the package upper pads2130of the package substrate2100. In example embodiments, in each of the first and second semiconductor packages2003aand2003b, the semiconductor chips2200may be electrically connected to each other by a connection structure a through silicon via (TSV), instead of the connection structure2400of a bonding wire method.

In example embodiments, the controller2002and the semiconductor chips2200may be included in a single package. For example, the controller2002and the semiconductor chips2200may be mounted on a separate interposer substrate different from the main substrate2001, and the controller2002may be connected to the semiconductor chips2200by interconnections formed on the interposer substrate.

FIG.15is a cross-sectional view illustrating a semiconductor device according to example embodiments.FIG.15illustrates example embodiments of the semiconductor package2003inFIG.14, and illustrates the semiconductor package2003inFIG.14taken along line III-III′.

Referring toFIG.23, in the semiconductor package2003, the package substrate2100may be configured as a printed circuit board. The package substrate2100may include a package substrate body portion2120, package upper pads2130(seeFIG.14) disposed on an upper surface of the package substrate body portion2120, lower pads2125disposed on a lower surface of the package substrate body portion2120or exposed through the lower surface, and internal interconnections2135electrically connecting the package upper pads2130to the lower pads2125in the package substrate body portion2120. The package upper pads2130may be electrically connected to the connection structures2400. The lower pads2125may be connected to the interconnection patterns2005of the main substrate2010of the data storage system2000through conductive connection portions2800as inFIG.14.

Each of the semiconductor chips2200may include a semiconductor substrate3010and a first semiconductor structure3100and a second semiconductor structure3200stacked in order on the semiconductor substrate3010. The first semiconductor structure3100may include a peripheral circuit region including peripheral interconnections3110. The second semiconductor structure3200may include a common source line3205, a gate stack structure3210on the common source line3205, channel structures3220and separation structures3230penetrating the gate stack structure3210, bit lines3240electrically connected to the memory channel structures3220, and cell contact plugs3235electrically connected to the word lines WL (seeFIG.13) of the gate stack structure3210. As described with reference toFIGS.1to10, in each of the semiconductor chips2200, the contact plugs170may contact the upper surface, the side surface, and the lower surface of the pad regions130P of the gate electrodes130, and may extend through the gate stacked structure3210into the first semiconductor structure3100.

Each of the semiconductor chips2200may include a through interconnection3245electrically connected to the peripheral interconnections3110of the first semiconductor structure3100and extending into the second semiconductor structure3200. The through interconnection3245may be disposed on an external side of the gate stack structure3210, and may be further disposed to penetrate the gate stack structure3210. Each of the semiconductor chips2200may further include an input and output pad2210(seeFIG.14) electrically connected to the peripheral interconnections3110of the first semiconductor structure3100.

According to the aforementioned example embodiments, by including the structure in which the pad region of the gate electrode protrudes into the contact plug, a semiconductor device having improved electrical properties and reliability, and a data storage system including the same may be provided.

While the example embodiments have been illustrated and described above, it will be apparent to those skilled in the art that modifications and variations could be made without departing from the scope of the present disclosure as defined by the appended claims.