Patent ID: 12249365

DETAILED DESCRIPTION OF THE INVENTION

The following description is of the best-contemplated model of carrying out the invention. This description is made for the purpose of illustrating the general principles of the invention and should not be taken in a limiting sense. The scope of the invention is best determined by reference to the appended claims.

FIG.1is a schematic diagram showing a computing device according to an embodiment of the present invention. As shown inFIG.1, the computing device10comprises a central processing unit110and a memory device120. The central processing unit110is electrically connected to the memory device120. The memory device120is implemented by, for example, a dynamic random access memory (DRAM), but the invention is not limited thereto. The memory device120comprises, for example, a plurality of memory banks, and each memory bank comprises a plurality of memory cell arrays. Each memory cell array is implemented, for example, in a two-dimensional array (for example: M rows*N columns) arrangement. Each row of one memory cell array is connected to a corresponding word line, and each column thereof is connected to a bit line. In addition, each memory cell can store 1-bit or M-bit data, and M is an integer greater than 1.

The central processing unit110comprises, for example, a memory controller111, an arithmetic logic unit (ALU)112, and a cache memory113. The memory controller111is used to control access to the data in the memory device120. It should be noted that a control signal115that is transmitted from the memory controller111to the memory device120can control the memory device120to perform in-memory computing, such as performing a bitwise AND/OR operation. The memory controller111can further receive the data that has been processed by the bitwise operation from the memory device120or receive general data that is not processed by any logic operations.

The arithmetic logic unit112performs corresponding arithmetic operations and/or logical operations according to instructions executed by the central processing unit110. In some embodiments, in order to reduce the requirement of data bandwidth between the central processing unit110and the memory device120, the memory controller111of the central processing unit110will transmit a corresponding control signal115to the memory device120so that some of the logic operations (for example: the bitwise AND/OR operation) are executed by the memory device120. Then, the central processing unit110receives the data that has been processed by the above logic operations from the memory device120(for example, through the data bus116), and transmits the received data to the arithmetic logic unit112for subsequent processing.

The memory device120comprises, for example, a plurality of memory banks121-12N, and each of the memory banks121-121N comprises a plurality of memory cell arrays1211-121N.

FIG.2Ais a circuit diagram of a memory cell array according to the embodiment ofFIG.1of the present invention. Please refer toFIG.1andFIG.2Aat the same time.

InFIG.2A, the memory cell array1211is taken as an example for illustration. The circuit structures of the other memory cell arrays1212-121N are similar to the circuit structure shown inFIG.2A. The memory cell array1211comprises a plurality of memory cells201, which are arranged in a two-dimensional array. The memory cells201on each row are connected to a corresponding word line202, and the memory cells201on each column are connected to a corresponding bit line203. In addition, each of the bit lines203is connected to a corresponding sense amplifier204.

FIG.2Bis a circuit diagram of the memory cell according to the embodiment ofFIG.2Aof the present invention.FIG.2Cis a schematic diagram of a reading procedure of the memory cell in the embodiment ofFIG.2Bof the present invention.

Please refer toFIG.2B, the memory cell201comprises a transistor2011and a capacitor2012. The logic level of the word line202controls the transistor2011to be turned on and off. In addition,FIG.2Cshows schematic diagrams of States S1-S5in which the memory cell201performs an access program.

InFIG.2C, the capacitor2012of the memory cell201is fully charged. State S1represents the initial pre-charge state. At this time, the logic level of the word line202is “0”, the sense amplifier204is turned off, and the voltage level of the bit line203is pre-charged to a voltage of ½VDD. Next, the access operation for the memory cell201is triggered by the ACT command on the word line202corresponding to the memory cell201, and the reading procedure enters State S2. In State S2, the word line202is activated so that the voltage level of the word line202reaches the voltage of ½VDD. At this time, the sense amplifier204is still turned off. State S3represents a charge-sharing state in which the charge stored in the capacitor2012flow to the bit line203from the memory cell201so that the voltage level of the bit line203increases to the voltage of ½VDD+δ. At this time, the sense amplifier204is still turned off. In State S4, the sense amplifier204is turned on to sense the deviation value δ (which can be a positive deviation value or a negative deviation value) between the voltage level of the bit line203and the voltage of ½VDDand amplifies the deviation value δ until the voltage level of the bit line203reaches the voltage of ½VDD, which means that the reading procedure enters State S5. At this time, since the capacitor2012is still connected to the bit line203, the potential stored in the capacitor2012will be charged to the original fully charged state.

FIG.3is a schematic diagram of a memory cell array according to an embodiment of the present invention. Please refer toFIG.1andFIG.3at the same time.

The memory cell array1211comprises memory cells301A,301B and301C. The memory cells301A-301C are connected to the same bit line BL. The sense amplifier304is used to sense the voltage level of the bit line BL and the voltage level of the reverse bit line bBL. In addition, the corresponding word lines WLR, WL1and WL2of the memory cells301A-301C are activated simultaneously so that the memory cells301A-301C are connected to the bit-line BL. Therefore, charge-sharing is performed according to the charges stored in the capacitors CSR, CS1, and CS2in the memory cells301A-301C. The deviation value δ of the voltage level of the bit line BL after the charge-sharing will be towards the majority value of the voltage levels stored in capacitors CSR, CS1, and CS2of the three memory cells301A-301C.

For example, if at least two of the capacitors CSR, CS1, and CS2of the memory cells301A-301C are initially in the charged state, the voltage level of the bit line BL will have a positive deviation. On the contrary, if at most one of the capacitors CSR, CS1, and CS2of the memory cells301A-301C is initially in the charged state, the voltage level of the bit line BL will have a negative deviation.

In details, the memory cell301A can be regarded as a reference memory cell, and the voltage level R stored by the capacitor CSRcan be used to control the memory cell array1211to perform a bitwise AND operation or a bitwise OR operation. For the convenience of description, the voltage levels stored in the capacitors CS1and CS2are A and B, respectively, and the voltage levels R, A, and B can be regarded as the logic states of the memory cells301A,301B, and301C, respectively. Therefore, after the word lines WLR, WL1, and WL2are activated simultaneously, the logic state OUT detected by the sense amplifier304can be represented by Formula (1) or Formula (2):

OUT=RA+RB+AB(1)=R⁡(A+B)+R¯(AB)(2)OUT=RA+RB+AB(1)=R⁡(A+B)+R¯(AB)(2)

Therefore, if the initial logic state of the voltage level R is “1”, the logic state OUT of the bit line BL after the charge-sharing is determined by the bitwise OR operation performed on the voltage levels A and B. If the initial logic state of the voltage level R is “0”, the logic state OUT of the bit line BL after the charge-sharing is determined by the bitwise AND operation performed on the voltage levels A and B. Therefore, the truth tables of the bitwise AND operation and the bitwise OR operation performed by the memory cells301A-301C can be represented by Table 1 and Table 2 respectively:

TABLE 1bitwise AND operation (R = 0)ABOUT000010100111

TABLE 2bitwise OR operation (R = 1)ABOUT000011101111

The deviation value ΔVBLbetween the voltage level of the bit line BL and the voltage level of the reverse bit line bBL detected by the sense amplifier304inFIG.3can be expressed by Formula (3):

Δ⁢VBL=m⁢CS×VBLH+CBL×VBLEQn⁢C⁢s+CBL-VBLEQ=m⁢CS×VBLH-n⁢CS×VBLEQn⁢CS+CBL=m×VBLH-n×VBLEQn+CBL/CS(3)Δ⁢VBL=m⁢CS×VBLH+CBL×VBLEQn⁢C⁢s+CBL-VBLEQ=m⁢CS×VBLH-n⁢CS×VBLEQn⁢CS+CBL=m×VBLH-n×VBLEQn+CBL/CS(3)Δ⁢VBL=m⁢CS×VBLH+CBL×VBLEQn⁢C⁢s+CBL-VBLEQ=m⁢CS×VBLH-n⁢CS×VBLEQn⁢CS+CBL=m×VBLH-n×VBLEQn+CBL/CS(3)m represents the number of memory cells whose stored voltage levels are the level of VBLH(which represents a high logic state) before the charge-sharing. n represents the number of activated word lines on the same bit line, and n is an integer, for example, between 0 and 3. If three word lines are activated simultaneously, then n=3. If two word lines are activated simultaneously, then n=2. In some embodiments, the voltage VBLEQis equal to

12⁢VDD(VBLEQ=12⁢VDD).

In one embodiment, it is assumed that the voltage VDDis equal to 1V (VDD=1V), the voltage VBLHis equal to 1V (VBLH=1V), the values of the capacitor CS1and CS2are equal to 17 fF (CS1=CS2=17 fF), the value of the capacitor CBLis equal to 27 fF (CBL=27 fF), and the ratio of the values of the capacitors CBLand CS1is equal to

1.6(CBLCS⁢1≅1.6).
Table 1, Table 2, and Formula (3) can be used to derive the deviation value ΔVBLand the logic state OUT of the corresponding bit line BL that are detected by the sense amplifier204when the three word lines WLR, WL1and WL2are activated (i.e. n=3) simultaneously, for example, shown in Table 3 and Table 4 respectively:

TABLE 3bitwise AND operation (R = 0)when three word lines are activated (n = 3)ABmΔVBLOUT000−0.315 V0011−0.104 V0101−0.104 V0112+0.104 V1

TABLE 4bitwise OR operation (R = 1)when three word lines are activated (n = 3)ABmΔVBLOUT000−0.104 V0011+0.104 V1101+0.104 V1112+0.315 V1

FIG.4Ais a schematic diagram of a memory cell array according to another embodiment of the present invention.FIG.4Bis a circuit diagram of the voltage control circuit in the embodiment ofFIG.4Aaccording to the present invention. Please refer toFIG.1andFIGS.4A-4Bat the same time.

A memory cell array400comprises memory cells401and402, a sense amplifier404, a voltage control circuit405, and a word line decoding circuit406. The memory cells401and402are connected to the same bit line BL, and the sense amplifier404is used to sense the voltage level of bit line BL and the voltage level of the reverse bit line bBL. In addition, the corresponding word lines WL1and WL2of the memory cells401and402can be activated simultaneously so that the memory cells401and402are connected to the bit line BL. In the embodiment, the memory cell array400can perform charge-sharing on the data stored in the memory cells401and402through, for example, the voltage control circuit405and the word line decoding circuit406to achieve a bitwise AND operation or a bitwise OR operation.

The voltage control circuit405can select the detection voltage VBLEQprovided to the sense amplifier404according to, for example, the control signal115from the memory controller111. In some embodiments, the voltage control circuit405selects one of the voltages of

14⁢VBLH,12⁢VBLH,and⁢34⁢VBLH
to serve as the voltage level of the detection voltage VBLEQ, but the invention is not limited thereto. For example, the control signal115may comprise related control signals for memory operations and an address signal for activating a related word line of the memory cell array400. The related control signals for the above memory operations comprise a normal read control signal Normal_Read, or the related control signals for the above memory operations comprise an operation control signal OR_Cal and an operation control signal AND_Cal. At most one of the above three control signals is in a high logic state to enable the memory cell array400to execute a corresponding operation.

For example, when the normal read control signal Normal_Read is in the high logic state, the memory cell array400performs a normal read operation, which means that the word line decoding circuit406activates one of the word lines according to the related address signal in the control signal115for the access to the data in the memory cells on the word line. At this time, the transistor Q3A inFIG.4Bis turned on to cause the voltage of ½VBLHto serve as the detection voltage VBLEQ.

When the OR operation control signal OR_Cal is in the high logic state, the memory cell array400performs a bitwise OR operation. At this time, the address signal in the control signal115is also changed to simultaneously enable two word lines (for example, the word lines WL1and WL2) so that the bitwise OR operation is formed on the data stored in the corresponding memory cells (for example, the memory cells401and402). In addition, the transistor Q3B inFIG.4Bis turned on to cause the voltage of ¼VBLHto serve as the detection voltage VBLEQ.

When the AND operation control signal AND_Cal is in the high logic state, the memory cell array400performs a bitwise AND operation. At this time, the address signal in the control signal115is also changed to simultaneously enable two word lines (for example, the word lines WL1and WL2) so that the bitwise AND operation is performed on the data stored in the corresponding memory cells (for example, memory cells401and402). In addition, the transistor Q3C inFIG.4Bis turned on to cause the voltage of ¾VBLHto serve as the detection voltage VBLEQ.

No matter which one of the bitwise OR operation or the bitwise AND operation is performed by the memory cell array400, the charge-sharing mechanism of the memory cells401and402on the bit line BL may refer to Formula (3). However, in the embodiment, the word lines WL1and WL2are activated simultaneously, and, thus, the value of n is equal to 2.

In the embodiment shown inFIGS.4A-4B, it is assumed that the voltage levels A and B can be regarded as the logic states of the memory cells401and402respectively. According to the similar data in the embodiment shown inFIG.3, the voltage VDDis equal to 1V (VDD=1V), the voltage VBLHis equal to 1V (VBLH=1V), the values of the capacitor CS1and CS2are equal to 17 fF (CS1=CS2=17 fF), the value of the capacitor CBLis equal to (CBL=27 fF), and the ratio of the values of the capacitors CBLand CS1is equal to

1.6(CBLCS⁢1≅1.6).
Therefore, the deviation value ΔVBLand the logic state OUT of the corresponding bit line BL that are detected by the sense amplifier204can be derived when the two word lines WL1and WL2are activated (i.e. n=2) simultaneously, for example, shown in Table 5 and Table 6:

TABLE 5bitwise AND operation (AND_Cal = 1)when two word lines are activated (n = 2)ABmVBLEQΔVBLOUT00034⁢VBLH−0.417 V001134⁢VBLH−0.139 V010134⁢VBLH−0.139 V011234⁢VBLH+0.139 V1

TABLE 6bitwise OR operation (OR_Cal = 1)when two word lines are activated (n = 2)ABmVBLEQΔVBLOUT00014⁢VBLH−0.139 V001114⁢VBLH+0.139 V110114⁢VBLH+0.139 V111214⁢VBLH+0.417 V1

According to the embodiments inFIG.3andFIGS.4A-4B, it can be deduced that the influence of simultaneously activating three word lines and simultaneously activating two word lines on the deviation value ΔVBLis shown in Table 7:

TABLE 7bitwise|ΔVBL—2WL| −operationABΔVBL—3WLΔVBL—2WL|ΔVBL—3WL|AND00−0.315 V−0.417 V102 mV01−0.104 V−0.139 V35 mV10−0.104 V−0.139 V35 mV11+0.104 V+0.139 V35 mVOR00−0.104 V−0.139 V35 mV01+0.104 V+0.139 V35 mV10+0.104 V+0.139 V35 mV11+0.315 V+0.417 V102 mV

ΔVBL_2WLrepresents the deviation value ΔVBLinFIGS.4A-4B, and ΔVBL_3WLrepresents the deviation value ΔVBLinFIG.3. Therefore, it can be seen from Table 7 that in the cases where the memory cell array400performs the bitwise AND operation, when the voltage levels (A,B) are (0,0), (0,1), (1,0), and (1,1) respectively, the signal margin of the deviation value ΔVBL_2WLis larger than the signal margin of the deviation value ΔVBL_3WL. In addition, in the cases where the memory cell array400performs the bitwise OR operation, when the voltage levels (A,B) are (0,0), (0,1), (1,0), and (1, 1) respectively, the signal margin of the deviation value ΔVBL_2WLis also greater than the signal margin of the deviation value ΔVBL_3WL. In other words, compared with the memory cell array300inFIG.3, the memory cell array400inFIG.4Ahas a greater signal margin. Therefore, the sense amplifier404can determine the logic level of the bit line BL more easily and accurately, and there is a greater tolerance for semiconductor process variations.

According to the above embodiments, the present invention provides a memory device capable of performing in-memory computing that comprises a memory cell array. The memory device may activate several word lines simultaneously through a word line decoding circuit to perform charge-sharing on the corresponding memory cells. The memory device may further select an appropriate detection voltage through a voltage control circuit to perform a bitwise AND operation or a bitwise OR operation. Therefore, the memory cell array of the present invention may have a greater signal margin, and there is a greater tolerance to semiconductor process variations.

While the invention has been described by way of example and in terms of the preferred embodiments, it should be understood that the invention is not limited to the disclosed embodiments. On the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.