Patent ID: 12199805

DETAILED DESCRIPTION OF THE INVENTION

Referring now to the drawings wherein like reference numerals are used to identify identical components in the various views,FIG.1illustrates a tractor-trailer10. Tractor-trailer10(also referred to as a semi) contains a truck or tractor12and one or more trailers141. . .14N. Tractor12contains a power unit, such as an internal combustion engine, and steering and drive axles. Tractor12also contains a battery16for use in starting the power unit and in providing power to various accessory systems. Trailers141. . .14Nare provided to store freight and are detachably coupled to tractor12. Although a pair of trailers14are shown in the illustrated embodiment, it should be understood that the number of trailers14attached to tractor12may vary.

Tractor12and trailers14may include various fluid and power lines that extend between tractor12and trailers14including power line18. The fluid and power lines allow delivery of fluids and electrical power from tractor12to trailers14for use in, for example, tire pressure management, braking, and activation of tail lights on trailer14. Power line18also forms part of a network used to transmit communications between various electronic systems20,221. . .22Non tractor12and trailers14, respectively. Systems20,22may comprise any of a wide variety of systems commonly employed on tractor-trailer10including, for example, anti-lock braking systems, collision avoidance systems, tire pressure monitoring and control systems, trailer load monitoring systems, and lighting systems. Power line18may enable transmission of data from one or more systems22on trailers14to a system20on tractor12including, for example, sensor readings indicative of the operation of an anti-lock braking system, the location of surrounding vehicles and infrastructure, pressure within the tires on a trailer14, or a shift in the load carried by a trailer14. Power line18may also enable transmission of commands and data from tractor12to trailers14for use in controlling elements of an anti-lock braking system, tire pressure control system or lighting system on one or more of trailers14.

Messages containing data and/or commands may be transmitted along power line18between systems20,22using the communications protocol developed by the Society of Automotive Engineers (SAE) and set forth in the document number J2497 and titled “Power Line Carrier Communications for Commercial Vehicles.” In accordance with this protocol, messages may be encoded using chirp spread spectrum (CSS) modulation. In particular, a chirp generator will generate specific waveforms corresponding to predefined logic symbols that may be interpreted as one of two binary states. Referring toFIG.2A-2C, the generator may be configured to generate two waveforms that are one hundred and eighty (180) degrees out of phase, but that are otherwise identical. These waveforms correspond to logic symbols Superiorθ1 (FIG.2A) and Superiorθ2 (FIG.2B). The absence of any waveform further corresponds to a logic symbol Inferior (FIG.2C). Messages transmitted under the protocol include a preamble that is encoded through amplitude shift key (ASK) modulation using the Superiorθ2 and Inferior symbols and a data body that is encoded through phase reversal key (PRK) modulation using the Superiorθ1 and Superiorθ2 symbols. In particular, the preamble begins with less than two complete Superiorθ2 symbols, followed by a start bit consisting of the Superiorθ2 symbol, eight data bits with each data bit consisting of a Superiorθ2 or Inferior symbol, and a stop bit consisting of an Inferior symbol. The data body begins with a sync segment comprising five Superiorθ1 symbols, followed by one or more character segments each having a start bit consisting of a Superiorθ2 symbol, eight data bits with each data bit consisting of Superiorθ1 or Superiorθ2 symbol, a stop bit consisting of a Superiorθ1 symbol and a gap of between zero and four Superiorθ1 symbols, followed by an end of message segment consisting of five Superiorθ1 symbols.

Referring now toFIG.3, each system20,22may include a controller24and a system26for demodulating and decoding the data body in a message transmitted along the power line18in vehicle10in accordance with the teachings disclosed herein. Although not illustrated herein, it should be understood that each of systems20,22may further include a system for demodulating and decoding the preamble in a message transmitted along the power line18and a system for encoding and modulating messages for transmission along power line18to other systems20,22.

Controller24may perform a variety of actions in response to received messages depending on the purpose of the system20,22in which controller24and system26are employed. Controller24may comprise a programmable microprocessor or microcontroller or may comprise an application specific integrated circuit (ASIC). Controller24may include a memory28and a central processing unit (CPU)30. Controller24may also include an input/output (I/O) interface32including a plurality of input/output pins or terminals through which controller24may receive a plurality of input signals and transmit a plurality of output signals. The input signals may include signals received from system26while the output signals may include signals transmitted to system26as well as a system (not shown) for encoding and modulating messages for transmission along power line18to other systems20,22. In the illustrated embodiment, a single controller24is shown. It should be understood, however, that the functionality of controller24described herein may be divided among multiple sub-controllers.

System26is provided to demodulate and decode the data body in messages received by the system20or22that has been transmitted by other systems20or22along the power line18in vehicle10. System26implements phase reversal keying (PRK) demodulation of the message data body to demodulate the Superiorθ1 and Superiorθ2 logic symbols to bits of logic one and logic zero, respectively. System26may include a decoupling circuit34, a filter36, an amplifier38, a peak detector circuit40, a sampling circuit42, a comparator44, a rectifier46and a controller48. Decoupling circuit34prevents unwanted energy from power line18from being passed to other elements of system26. Circuit34may include a capacitor that couples the remaining elements of system26to power line18and a clamping diode (e.g., a Zener diode) downstream of the capacitor.

Filter36attenuates analog input signals outside of a predetermined frequency range (e.g., 100 KHz to 400 KHz). Filter36may comprise a band pass filter.

Amplifier38amplifies the analog signal output by filter36prior to delivery to peak detection circuit40. Amplifier38is conventional in the art.

Peak detector circuit40is configured to detect selected amplitude peaks in the data body of the message received through amplifier38. As noted hereinabove, the data body of the message is formed using Superiorθ1 (FIG.2A) and Superiorθ2 (FIG.2B) logic symbols. Referring toFIG.4A, each Superiorθ1 and Superiorθ2 logic symbol has a length of one hundred (100) microseconds (μs). Each Superiorθ1 and Superiorθ2 logic symbol has a generally sinusoidal waveform with an amplitude that varies between the start of the logic symbol and the end of the logic symbol. Each Superiorθ1 logic symbol further includes a distinctive negative peak50having a negative amplitude that represents the maximum possible negative amplitude among the Superiorθ1 and Superiorθ2 logic symbols and, therefore, within the data body of the message. Each Superiorθ2 logic symbol further includes a distinctive positive peak52having a positive amplitude that represents the maximum possible positive amplitude among the Superiorθ1 and Superiorθ2 logic symbols and, therefore, within the data body of the message. The distinctive negative and positive peaks50,52occur at the same point in time (about sixty-six (66) microseconds (μs)) after the start of the logic symbol. Therefore, the distinctive negative and positive peaks50,52in successive logic symbols occur one hundred (100) microseconds (μs) apart.

Referring toFIG.4B, peak detector circuit40includes a negative peak detector circuit and a positive peak detector circuit that generates a pair of peak envelope signals54,56outlining the extremes of the amplitude peaks in the data body. Signal54from the positive peak detector circuit tracks positive peaks in the data body. Referring toFIG.4A-B, the waveform of the Superiorθ1 logic symbol includes a positive peak with a relatively large amplitude proximate the start of the Superiorθ1 logic symbol. Therefore, the value of signal54increases to a value corresponding to that peak. Thereafter, no positive peak has the same or greater positive amplitude until the distinctive positive peak52in the Superiorθ2 logic symbol at which point the value of signal54increases to a value corresponding to the peak52. Signal56from the negative peak detector circuit tracks negative peaks within the data body. The waveform of the Superiorθ1 logic symbol includes a series of negative peaks having progressively increasing negative amplitudes proximate the start of the Superiorθ1 logic symbol. Therefore, the value of signal56increases (to a larger negative value) as each peak is reached. Thereafter, no negative peak has the same or greater negative amplitude until the distinctive negative peak50in the Superiorθ1 logic symbol at which point the value of signal56increases again to a value corresponding to the peak50. Following each distinctive negative or positive peak50,52, some level of discharge will occur from the circuit component (e.g., a capacitor) providing an indication of the amplitude of the distinctive negative or positive peak50,52such that the signals56,54, will provide an indication of each successive distinctive negative or positive peak50,52. The level discharge is insufficient, however, to allow the circuit to detect any peaks in the Superiorθ1 and Superiorθ2 logic symbols other than the distinctive negative and positive peaks50,52.

Referring now toFIG.4C, peak detector circuit40is conjured to generate a peak indicator signal58responsive to the peak envelope signals54,56shown inFIG.4B. The peak indicator signal58indicates each increase in the peak envelope signals54,56. In particular, the peak indicator signal58assumes a first value each time the data body defines a positive peak having a positive amplitude equal to or greater than a previously identified largest positive amplitude in the data body. The peak indicator signal58assumes a second value each time the data body defines a negative peak having a negative amplitude equal to or greater than a previously identified largest negative amplitude in the data body.

Referring again toFIG.3, sampling circuit42is provided to extract data from the peak indicator signal58corresponding to the distinctive negative and positive peaks50,52in the data body and thereby provide an indication of the presence of Superiorθ1 and Superiorθ2 logic symbols in the data body. Referring toFIG.4D, sampling circuit42generates a data signal60responsive to the peak indicator signal58(FIG.4C). Sampling circuit42ignores portions of the peak indicator signal58occurring prior to an indication in the peak indicator signal58of one of the distinctive negative or positive peaks50,52. Sampling circuit42may do so by combining a predefined masking signal with the peak indicator signal58to cancel those portions of the peak indicator signal58occurring prior to the first distinctive negative peak50or distinctive positive peak52in the peak indicator signal58. Sampling circuit42may include a masking signal generator (not shown) for generating the masking signal and the masking signal generator may be triggered to generate the masking signal by an indication (e.g., a signal from controller48) of the end of the preamble of the message. In one embodiment, the masking signal assumes a first predetermined value for a predetermined period of time. The predetermined period of time corresponds to a period of time prior to an occurrence of one of the distinctive negative or positive peaks50,52in the data body. Thereafter, the masking signal assumes a second predetermined value. Because the Superiorθ1 and Superiorθ2 logic symbols have predefined waveforms, the masking signal can be precisely configured to cancel out the initial, unwanted portion of the peak indicator signal58. In particular, the distinctive negative and positive peaks50,52occur at approximately sixty-six (66) microseconds (μs) from the beginning of the corresponding logic symbol. Therefore, in one embodiment the masking signal can be configured to assume a value of logic zero for about sixty-six (66) microseconds (μs) and a value of logic one thereafter. When the masking signal is combined with the peak indicator signal58(e.g., through a circuit implementing an AND logic relationship), the masking signal will cancel the value of the peak indicator signal58(FIG.4C) for the first sixty-six (66) microseconds (μs) and the data signal60(FIG.4D) will not reflect the value of the peak indicator signal58. Thereafter, however, the data signal60will correspond to the peak indicator signal58and therefore provide an indication of each logic symbol in the data body.

Referring again toFIG.3, comparator44compares the data signal60generated by sampling circuit42to threshold values to generate a data bit pattern for controller48. Comparator44may comprise a Schmitt trigger circuit. Comparator44is configured to generate an output signal that assumes one value indicative of the Superiorθ1 logic symbol when the value of the data signal60meets a predetermined condition relative to a predetermined negative threshold (e.g., is less than the predetermined negative threshold) and assumes another value indicative of the Superiorθ2 logic symbol when the value of the data signal60meets a predetermined condition relative to a predetermined positive threshold (e.g., is greater than the predetermined positive threshold).

Rectifier46converts the AC (alternating current) signal output by comparator44to a DC (direct current) signal. Rectifier46is conventional in the art.

Controller48is provided to decode received messages transmitted along power line18prior to transmission to controller24in which the data conveyed in the message is used or the command conveyed in the message is implemented. Controller48may comprise a programmable microprocessor or microcontroller or may comprise an application specific integrated circuit (ASIC). Controller48may include a memory62and a central processing unit (CPU)64. Controller48may also include an input/output (I/O) interface66including a plurality of input/output pins or terminals through which controller48may receive a plurality of input signals and transmit a plurality of output signals. The input signals may include signals received from rectifier46while the output signals may include signals transmitted to controller24of system20or22. In the illustrated embodiment, a single controller48is shown. It should be understood, however, that the functionality of controller48described herein may be divided among multiple sub-controllers.

A system26and method for demodulating and decoding the data body in a message transmitted along a power line18within a vehicle10in accordance the present teachings represent an improvement as compared to conventional systems and methods. In particular, the system26and method disclosed herein enable a vehicle10to receive messages along the power line18without use of the typical transceiver used within the industry that is in short supply and relatively expensive. The system26and method further allow demodulation and decoding of the data body independent of the duration of the preamble of the message, variations in the voltage range of the signal conveying the message and phase changes in the signal conveying the message. While the invention has been shown and described with reference to one or more particular embodiments thereof, it will be understood by those of skill in the art that various changes and modifications can be made without departing from the spirit and scope of the invention.