Patent ID: 12243840

DETAILED DESCRIPTION

The present disclosure is directed to a method and apparatus for placing an IC die in electrical communication with an external substrate wherein the IC die is configured for flip chip mounting, and the external substrate is configured for wirebonding. Accordingly, external substrates and circuit board layouts that are designed to be wirebonded to respective IC dies can be placed in electrical communication with IC dies that are configured for flip chip mounting and not for wirebond mounting.

As used herein, the singular forms “a,” “an,” and “the” include “at least one” and a plurality unless otherwise indicated. Further, reference to a plurality as used in the specification including the appended claims includes the singular “a,” “an,” “one,” and “the,” and further includes “at least one” unless otherwise indicated. Further still, reference to a particular numerical value in the specification including the appended claims includes at least that particular value, unless the context clearly dictates otherwise.

The term “plurality”, as used herein, means more than one. When a range of values is expressed, another example includes from the one particular value and/or to the other particular value. Similarly, when values are expressed as approximations, by use of the antecedent “substantially,” “approximately,” “about,” and derivatives thereof, it will be understood that the particular value forms another example. All ranges are inclusive and combinable.

Referring now toFIG.1, an IC die20in one example is configured to be flip chip mounted to an external substrate. The IC die20includes a die substrate24having an outer active surface26with electrical components formed therein comprising active circuitry. The die substrate24is typically made of silicon, though the die substrate24can be made from any suitable alternative semiconductor material, such as germanium, gallium arsenide, indium phosphide or other III-V or II-VI semiconductor materials. The outer active surface26can include one or more metallization layers disposed over a contact layer that is in electrical communication with the electrical components of the IC die20. Thus, in one example, the outer active surface26can include an electrically conductive contact layer30that is supported by the outer active surface26. In some examples, the contact layer30is disposed on the outer active surface26. In other examples, the contact layer30is disposed on at least one intermediate layer that, in turn, is disposed on the outer active surface26. The contact layer30can be any suitable metal, such as aluminum, copper, nickel, tungsten, palladium, gold, or the like. The contact layer30defines an inner surface30athat can face the outer active surface26, and an outer surface30bopposite the inner surface30aalong a transverse direction27. The outer active surface26can face away from the external substrate.

The outer active surface26can include a passivation layer32that extends along the outer surface26and further covers a portion of the outer surface30bof the contact layer30. For instance, the passivation layer32can cover an outer perimeter of the outer surface30b. Thus, the outer surface30bcan define a covered region31athat is covered by the passivation layer32, and an uncovered region31bthat is not covered by the passivation layer32. The covered region31acan surround the uncovered region31bin some examples. The outer active surface26can further include an under bump metallization (UBM) layer34or other electrically conductive layer that is in electrical communication with the contact layer30. In one example, the UBM layer34can extend along and contact the uncovered region31bof the outer surface30b. Further, the UBM layer34can include an overlap region that extends along a portion of the passivation layer32. For instance, the overlap region of the UBM layer34can extend along a portion of the passivation layer32that extends along the covered region31aof the outer surface30b. Thus, the passivation layer32defines a covered region33athat is covered by the UBM layer34, and an exposed region33badjacent the covered region33aand not covered by the UBM layer34.

The IC die20can further include an electrically conductive interface36that makes electrical contact with the active circuitry and provides a path for electrical signals to enter and exit the IC die20. For instance, the electrically conductive interface36can be mounted to the UBM layer34, and can further be mounted to an electrical contact pad of an external component that can be configured as an interposer40(seeFIG.2) so as to flip chip mount the IC die20to the interposer40. The electrically conductive interface36can be configured as a mass of solder, stud bump, or copper pillar, or any suitable alternative material and structure. Typically, the mass of solder can be constructed as a solder bump. In one example, the solder bump can be configured as a solder ball having a generally spherical shape, though the solder bump can define any suitable shape as desired. The solder bump can have a diameter or other maximum cross-sectional dimension that is in a range from approximately 30 microns to approximately 80 microns, such as approximately 40 microns. It should be appreciated, of course, that the solder bump can define any suitable size and shape as desired. In another example, the electrically conductive interface36can be made from copper and can be constructed generally in the shape of a pillar. The UBM layer34can thus be made of a material that is configured to bond with the electrically conductive interface36, such as aluminum or copper or the like.

The term “substantially,” “approximately,” “about,” and derivatives thereof, and words of similar import, when used to described sizes, shapes, spatial relationships, distances, directions, and other similar parameters includes the stated parameter in addition to a range up to 10% more and up to 10% less than the stated parameter, including up to 5% more and up to 5% less, including up to 3% more and up to 3% less, including up to 1% more and up to 1% less.

The IC die20can include a plurality of contact layers30, and the passivation layer32can cover respective portions of the contact layers30in the manner described herein. Alternatively, a plurality of passivation layers32can cover a portion of respective ones of the contact layers30. Further, a plurality of UBM layers34can extend over respective ones of the contact layers30in the manner described above. The IC die20can include a plurality of electrically conductive interfaces36that are placed onto and eventually bonded to the UBM layers34in the manner described herein. The electrically conductive interfaces36can define a grid array of solder bumps (which can be referred to as a ball grid array (or BGA) when the solder bumps are configured as solder balls) along the outer active surface26of the IC die substrate24that can define a mounting interface of the IC die substrate24. The electrically conductive interfaces36can be spaced from each other at a fine pitch. For instance, adjacent ones of the electrically conductive interfaces36can be spaced from each other at a pitch of less than 300 microns, though it is appreciated that electrically conductive interfaces36of any suitable pitch or size can be used.

In some examples, at least one IC die20can be integrated into an optical transceiver. The IC die20can define a laser diode driver for a VCSEL (vertical cavity surface emitting laser) array of the transceiver. Alternatively, the IC die20can define a transimpedance amplifier (TIA) designed to receive and condition electrical signals from a high speed photodetector array. The IC die20is not intended to be limited to this application, and the present disclosure is applicable to any flip chip packaged IC die, unless otherwise indicated. The IC die20may be singulated, that is the IC die20has been separated from a wafer containing a plurality of IC dies in a previous processing step.

As described above, the IC die20can be configured to be placed in electrical communication with an external component, such as an external substrate that can be configured as a printed circuit board, via a wirebond. Otherwise stated, an IC assembly including the IC die20can be configured for wirebonding. As illustrated inFIG.2, the IC assembly can further include an interposer40, whereby the IC die20(seeFIG.1) can be flip chip mounted to the interposer40. As will be appreciated from the description below, the interposer40can be double access, that is electrical connections may be made to the two opposed major surfaces or sides of the interposer40. A first side42aof the interposer40can be configured to be flip chip mounted to the IC die20, and a second side42bof the interposer40opposite the first side42aalong the transverse direction27can be configured to be wirebonded to an external component, such as an external substrate.

In particular, with continuing reference toFIG.2, the interposer40can include an electrically conductive layer44that defines a first or inner surface46aand a second or outer surface46bopposite the first surface46aalong the transverse direction27. The first surface46afaces the first side42aof the interposer40, and the second surface46bfaces the second side42b. Thus, the first side42ais configured to face the flip chip IC die20(seeFIG.3). The interposer40has a thickness from the first surface46ato the second surface46b. The thickness can be substantially equal to or less than approximately 200 microns. The electrically conductive layer44can be any suitable material, such as a metal. The metal can be copper or any suitable alternative material as desired. Further, the metal can include an electrically conductive coating on one or both sides of the copper or other metal. The electrically conductive layer44can have a thickness from the first surface46ato the second surface46bthat is in a range of approximately 1 micron to approximately 25 microns. It should be appreciated, of course, that the electrically conductive layer44can have any suitable alternative thickness as desired.

The electrically conductive layer44can be patterned so as to form a plurality of electrically conductive paths that are electrically insulated from each other. For instance, the interposer40can further include a first electrically insulative layer48and a second electrically insulative layer50, such that the electrically conductive layer44is positioned between the first and second electrically insulative layers48and50. In particular, the electrically conductive layer44can be attached to each of the first and second electrically insulative layers48and50. In one example, one of the first and second electrically insulative layers48and50can be laminated with the electrically conductive layer44. The electrically conductive layer44can be patterned and the unwanted material of the electrically conductive layer44can be etched away. The other of the first and second electrically insulative layers48and50can then be applied to the electrically conductive layer44, such that the patterned electrically conductive layer44is disposed between the first and second electrically insulative layers48and50,

The interposer40may be a thin organic laminate or a flexible printed circuit. The first electrically insulative layer48can extend from the first surface46a, or otherwise be disposed on the first surface46a, of the electrically conductive layer44. The second electrically insulative layer50can extend from the second surface46b, or otherwise be disposed on the second surface46b, of the electrically conductive layer44. The first electrically insulative layer48defines a first or inner surface49athat faces the IC die20, and a second or outer surface49bopposite the first surface49aalong the transverse direction27. The second surface49bfaces the electrically conductive layer44. In some examples, the second surface49bcan abut or attach to the first surface46aof the electrically conductive layer44. The second electrically insulative layer50defines a first or inner surface51athat faces the electrically conductive layer44, and a second or outer surface51bopposite the first surface51aalong the transverse direction27. In some examples, the first surface51acan abut the second surface46bof the electrically conductive layer44.

The first electrically insulative layer48can be a polyimide or any suitable alternative electrically insulative material as desired. The second electrically insulative layer50can be a liquid photoimageable (LPI) solder mask or any suitable photomask material in one example, or any suitable alternative electrically insulative material as desired. In one example, the second electrically insulative layer50can be conformable to the metal layer44after the metal layer44has been patterned in the manner described above. Thus, at locations where material of the metal layer44has been etched, the first and second electrically insulative layers48and50can contact each other. The second electrically insulative layer50can define the outermost layer of the interposer40in some examples with respect to the transverse direction27. Thus, the second surface51bcan define the outermost surface of the interposer40in some examples with respect to the transverse direction27.

The first electrically insulative layer48defines a thickness from the first surface49ato the second surface49balong the transverse direction27. and the second electrically insulative layer50can have a thickness range from approximately 0.1 micron to approximately 25 microns. In some examples, a chemical passivation layer can provide both an insulating layer and be used as a solder mask. Thus, either or both of the first and second electrically insulative layers48and50can be at least partially defined by a chemical passivation layer. In this case, the thickness of the insulating layer may be very thin, in the range of approximately 10 nm to 1 micron.

The first electrically insulative layer48can define at least one first hole52or a plurality of first holes that extends therethrough from the second surface49bto the first surface49aalong the transverse direction27. Thus, the first hole52extends through the first electrically insulative layer48to the electrically conductive layer44, and in particular to an electrically conductive pad45, which can be configured as a solder pad at the electrically conductive layer, which can thus either be disposed on the electrically conductive layer44or defined by the electrically conductive layer44. As will be appreciated from the description below, the electrically conductive contact pad45is configured to be flip chip mounted to the IC substrate24. The first hole52can therefore be referred to as a first through hole. The electrically conductive contact pad, or electrical contact pad45, can be disposed at the first surface46aof the electrically conductive layer44. That is, the electrical contact pad can be disposed on the first surface46aof the electrically conductive layer44, or can be defined by the first surface46aof the electrically conductive layer44. The first hole52can have any suitable cross-sectional dimension as desired, such that the first hole52is sized to receive the electrically conductive interface36, thereby establishing an electrical connection between the interposer40, and in particular the electrically conductive layer44, and the IC die20as will be described in more detail below. The first hole52can define a maximum cross-sectional dimension in a plane that is oriented perpendicular to the transverse direction27, whereby the maximum cross-sectional dimension can be in a range from approximately 20 microns to approximately 150 microns, such as from approximately 30 microns to approximately 100 microns, and in one example can be approximately 60 microns. It should be appreciated, of course, that the maximum cross-sectional dimension can have any size as desired. In some examples, the first hole52can have a circular cross-section, such that the maximum cross-sectional dimension is a diameter.

The second electrically insulative layer50can define at least one second hole or a plurality of second holes54that extend therethrough from the second surface51bto the first surface51aalong the transverse direction27. The second holes54can be spaced in their entireties from the first holes52along a direction that is perpendicular to the transverse direction27. In other examples, the second holes54can be at least partially or entirely aligned with the first holes52along the transverse direction27. Thus, the second hole54extends through the second electrically insulative layer50to the electrically conductive layer44. In particular, the second hole54can extend through the second electrically insulative layer to an electrically conductive wirebond pad53at the electrically conductive layer44. The second hole54can thus be referred to as a second through hole. Thus, exposed portions of the electrically conductive layer44, and in particular a plurality of electrically conductive wirebond pads53, can be said to be exposed through a respective plurality of second holes54in the second electrically insulative layer55. The electrically conductive wirebond pad53that can either be disposed on the electrically conductive layer44or defined by the electrically conductive layer44. The electrically conductive wirebond pad53can be disposed at the second surface46bof the electrically conductive layer44. For instance, the wirebond pad53can be disposed on the second surface46bor can be defined by the second surface46bof the electrically conductive layer44. The wirebond pads53are in electrical communication with respective ones of the electrical contact pads45.

In this regard, it should be appreciated that the electrically conductive layer44can define a double access layer in that the electrically conductive interface36and the wirebond56can be mounted to opposite sides of the electrically conductive layer44. Thus, the electrically conductive layer44can be electrically connected to both the electrically conductive interface36and the wirebond56. The second hole54can have any suitable cross-sectional dimension as desired, such that the second hole54is sized to receive a wirebond56, thereby establishing an electrical connection between the wirebond56and the interposer40. The second hole54can define a maximum cross-sectional dimension in a plane that is oriented perpendicular to the transverse direction27, whereby the maximum cross-sectional dimension can be in a range from approximately 20 microns to approximately 150 microns, such as from approximately 30 microns to approximately 100 microns, and in one example can be approximately 60 microns. It should be appreciated, of course, that the maximum cross-sectional dimension of the second hole54can have any size as desired. In some examples, the second hole54can have a circular cross-section, such that the maximum cross-sectional dimension is a diameter.

It is therefore appreciated that the first holes52and the second holes54can extend through the respective first and second electrically insulative layers48and50, respectively, so as to expose the respective first and second surfaces of the at least one electrically conductive layer. The at least one electrically conductive layer can be defined by the single electrically conductive layer44or by first and second electrically conductive layers62and64, respectively, as is described in more detail below.

The electrically conductive layer44is suitable for soldering or otherwise bonding to the electrically conductive interface36to the solder bump on its first side or surface46a, and is further suitable for wirebonding on its second side or surface46b. Thus, the electrically conductive layer44can be electrically connected to the IC die20through the electrically conductive interfaces36. As such, the electrically conductive layer44can have different coatings or surface preparations on its first and second surfaces46aand46b, respectively. When the electrically conductive interface36and the wirebond56are mounted to the electrically conductive layer44, the electrically conductive layer44places the wirebond56and the electrically conductive interface36in electrical communication with each other.

Because the electrically conductive layer44can bond with respective electrically conductive components (the interface36and the wirebond56) at the first and second sides46aand46b, respectively, the interposer40can be referred to as having a double access metal layer. Thus, the interposer can place the interface36and the wirebond56in electrical communication with each other without the use of an electrically conductive through via that extends from the first side42ato the second side42bthat places first and second opposed electrically conductive surfaces in electrical communication with each other. Thus, when the interface36and the wirebond56are mounted to the respective first and second surfaces, the via places the interface and the wirebond in electrical communication with each other. Though it is believed that avoiding such a via can improve high speed performance of the interposer, it is recognized, of course, that the interposer40can alternatively include such a via if desired. The interposer40can be configured to transfer data from the interface36to the wirebond56at high data transfer speeds up to approximately 56 Gbps, including approximately 28 Gbps.

Referring now toFIG.3, a wirebondable IC assembly58that includes the IC die20and the interposer40electrically connected to the IC die20. In particular, the interposer40can be mounted to the flip chip IC die20. Thus, the wirebondable IC assembly58includes a flip chip IC die20, and is configured to be wirebonded to an external component, such as an external substrate, so as to place the external component in electrical communication with the IC die20. The interposer40can have one or more first holes52that extend through the first electrically insulative layer48in the manner described above. Each of the holes52can be configured to receive a respective electrically conductive interface36that is configured to bond to a corresponding IC die and the electrically conductive layer44of the interposer40. That is, the first holes52and the exposed first electrical contact pads45of the electrically conductive layer44can be aligned with the respective UBM layer34of the IC die20along the transverse direction27.

To establish electrical connections with the IC die20, the interposer40can be positioned adjacent the UBM layer34, and the electrically conductive interfaces36can be placed between the electrical contact pads45of the electrically conductive layer44and the UBM layer34. The IC die20, the interposer40, and the electrically conductive interfaces36can then be placed into an oven, which raises the temperature of the electrically conductive interface34that causes the electrically conductive interface36to bond with the UBM layer34and the electrically conductive layer44of the interposer40, thereby mounting the interposer40to the IC die20and establishing a permanent electrical and mechanical connection between the IC die20and the interposer40. In particular, the electrically conductive layer44is placed in electrical communication with the UBM layer34, and thus with the IC die substrate24through the contact layer30. In one example, the electrically conductive interface34is a solder bump, and the oven is a solder reflow oven.

After the bonding step, an electrically insulative material such as a resin60can be placed in a gap that extends from the IC die20to the interposer40, for instance along the transverse direction27. The resin60can be an epoxy resin or any suitable alternative resin or other electrically insulative material. The resin60can serve as a underfill between the IC die20and the interposer40along the transverse direction27after the interposer40has been mounted to the IC die20. In particular, the resin60can extend from the exposed region33bof the passivation layer32to the first electrically insulative layer48of the interposer40. Alternatively or additionally, the resin60can extend from the outer active surface26of the IC die substrate24adjacent the passivation layer32to the first electrically insulative layer48of the interposer40. The resin60can further extend along a side surface of the IC die20that extends from the outer active surface away from the interposer40, for instance along the transverse direction27. It should be appreciated that the IC assembly58can define a wirebondable component. A wirebond can be mounted to the interposer40, and can be further mounted to an external component such as an external substrate, thereby placing the interposer40, and therefore the IC die20, in electrical communication with the external component. It is appreciated that the interposer40can include a plurality of first holes52, such that the interposer40is configured to be mounted to the IC die20at a plurality of electrically conductive interfaces36that extend into the first holes52as described above. The electrically conductive interfaces36can be mounted to different patterned structures of the electrically conductive layer44that are exposed through the first holes52. The electrically conductive interfaces36can define a grid array of solder bumps in some examples. The interposer40can further include a plurality of second holes54, such that the interposer40is configured to be mounted to a plurality of wirebonds56that are in electrical communication with respective ones of the electrically conductive interfaces36. The wirebonds56are configured to be mounted to the different patterned structures of the electrically conductive layer44that is exposed through the plurality of second holes54.

It should therefore be appreciated that a method is provided for converting a mounting interface of an IC die substrate24, defined by the grid array, such as that defined by the flip chip IC die20, to a wirebondable electrical component, such as that defined by a wirebondable IC die. Otherwise stated, the method can convert a grid array electrical interface of solder bumps to a wirebondable electrical interface. The method can include the step of mounting the interposer40to the IC die20in the manner described herein. In particular, the grid array interface on the flip chip IC die20is aligned with the first plurality of holes52in the first electrically insulative layer48of the interposer40. The IC die, the interposer40, and the electrically conductive interfaces36disposed between the IC die20and the interposer40can then be heated so that the electrically conductive interfaces36reflow and define an electrical and mechanical attachment between the interposer40and IC die20. The second side42bof the interposer40has the second plurality of holes54in the second electrically insulative layer50that expose wirebond pads in the electrically conductive layer44. These exposed wirebond pads can define an attachment location for attachment of the wirebond56.

Referring now toFIG.4A-4B, in another example, the first hole52can extend through the first electrically insulative layer48from the second surface49bto the first surface49aalong the transverse direction27as described above, and can further extend through the electrically conductive layer44from the first surface46ato the second surface46b. The hole52can further extend through the second electrically insulative layer50from the first surface51ato the second surface51b. Further, the second electrically insulative layer50can be spaced from the first hole52along a direction perpendicular to the transverse direction27, thereby exposing an exposed portion47of the second surface46bof the electrically conductive layer44. Thus, exposed portions47of the second surface46bof the electrically conductive layer can be said to be exposed through a respective plurality of first holes52in the second electrically insulative layer. In this regard, a first portion52aof the hole52that extends through the first electrically insulative layer48and the electrically conductive layer44can have a first cross-sectional dimension. The hole52defines a second portion52bthat extends through the second electrically insulative layer50can have a second cross-sectional dimension that is greater than the first cross-sectional dimension. The first and second cross-sectional dimensions can be measured in respective planes that are oriented perpendicular to the transverse direction27. Further, one or both of the first and second cross-sectional dimensions can be defined by diameters in some example. At least a portion up to an entirety of the hole52at the second electrically insulative layer50can be outwardly spaced from the hole52at the electrically conductive layer44.

Accordingly, when the electrically conductive interface36is melted during a reflow step, the material of the electrically conductive interface36can form an electrical and mechanical connection between the electrically conductive layer44and the IC die substrate24. The first insulating layer48can define a mask for the material of the electrically conductive interface36. Accordingly, during the reflow step, the electrically conductive interface36can extend through the first portion of the hole52, and wet and bond to the second surface46bof the electrically conductive layer44. While the IC die20can include various features on the active outer surface26in the manner described above, these features are not shown inFIGS.4A-4Bfor the purposes of clarity and convenience.

It is recognized that the interposer40can be constructed in accordance with any suitable embodiment as desired. For instance, as illustrated inFIGS.2-4B, the second or outer surface51bof the second electrically insulative layer50can define an outer external surface of the interposer40. In another example illustrated inFIG.5, the interposer40can include first and second electrically conductive layers62and64, respectively. The first electrically conductive layer62can be electrically connected to the IC die through the electrically conductive interfaces36. The first electrically conductive layer62can be defined by the electrically conductive layer44in any manner as described above. The second electrically conductive layer64can be disposed on the second surface51bof the electrically insulative layer50. In particular, the second electrically conductive layer64can define a first or inner surface65athat faces the second surface51bof the second electrically insulative layer50and can attach to the second surface51bof the second electrically insulative layer50, and a second or outer surface65bthat is opposite the first surface65aalong the transverse direction27. It should be appreciated that the second surface65bis also opposite the first surface46aof the first electrically conductive layer62. In some examples, the first surface65acan abut the second surface51bof the electrically insulative layer50.

Thus, the electrically insulative layer50can be disposed between the first and second electrically conductive layers62and64with respect to the transverse direction27. Further, the respective footprints defined by the first and second electrically conductive layers can be aligned with each other along the transverse direction27. The footprints extend along a plane that is perpendicular to the transverse direction27. The second electrically conductive layer64can be made of a second metal or other suitable electrically conductive material. The second electrically conductive layer64can be the same material as the first electrically conductive layer62or a different material than the first electrically conductive layer62. In some examples, the first and second layers62and64define first and second metal layers.

Either or both of the first and second electrically conductive layers62and64can be patterned as desired. Thus, the first electrically conductive layer62can include a plurality of discontinuous segments that are electrically isolated from each other. Similarly, the second electrically conductive layer64can include a plurality of discontinuous segments that are electrically isolated from each other. The second hole54extends through the second electrically insulative layer50to the first electrically conductive layer62. Thus, a wirebond56can extend through the second hole54and can electrically connect to the first electrically conductive layer62. The second electrically conductive layer64can define an electrical ground or electrical shield layer, or can route electrical signals as desired to and/or from the external substrate. If used as a ground layer, the second electrically conductive layer64may be a single continuous layer of electrically conductive metal. The layer64of conductive metal may have holes or gaps that allow electrical signals to be transmitted from or to the first electrically conductively layer62. If used to route electrical signals, the second electrically conductive layer64can be patterned as desired.

It is therefore appreciated that the electrically conductive interfaces36can be mounted to a first surface of at least one electrically conductive layer, and the wirebonds56can be mounted to a second surface of the at least one electrically conductive layer, wherein the second surface is opposite the first surface. The at least one electrically conductive layer, including the first and second surfaces, can be defined by the single electrically conductive layer44described above with respect toFIG.2. Alternatively, the at least one electrically conductive layer can be defined by the first and second electrically conductive layers62and64that define the first and second surfaces46aand65b, respectively.

Additionally, referring toFIGS.5-6, the interposer40, and thus the wirebondable IC assembly58, can include a stiffener66that is disposed on or otherwise supported by the second surface65bof the second electrically conductive layer64. The stiffener66defines a first or inner stiffener surface67athat faces or abuts the second surface65bof the second electrically conductive layer64, and a second or outer stiffener surface67bopposite the first stiffener surface67a. The first stiffener surface67acan attach to the second surface65bof the second electrically conductive layer64. Thus, the second electrically conductive layer64can be disposed between the stiffener66and the second electrically insulative layer50with respect to the transverse direction27. The stiffener66can be made of any suitable material, such as glass, ceramic, organic laminates, polymers such as a polyimide, a liquid crystal polymer (LCP), or the like.

The stiffener66can define a stiffener body69that is be recessed from at least a portion of an outer perimeter of the second electrically conductive layer64, so that the stiffener66does not interfere with wirebonds56that extend through the outer perimeter of the second electrically conductive layer64, wherein the outer perimeter is defined in the plane that is oriented perpendicular to the transverse direction27. In particular, at least a portion, up to an entirety, of an outer perimeter of the stiffener body69can be recessed with respect to at least a portion, up to an entirety, of the outer perimeter of the second electrically conductive layer64. The stiffener66can further include at least one or more protrusions71that extend out from the outer perimeter of the stiffener body66in a direction generally perpendicular to the transverse direction27. Further, the protrusions71can extend out from an outer surface of the outer perimeter of the stiffener body66in a direction generally perpendicular to the outer surface. At various locations along the perimeter of the stiffener one or protrusions may extend outward. The protrusions71can extend to the outer perimeter of the second electrically conductive layer64. The protrusions71can allow the interposer40to be fabricated in a panel of interconnected interposers, which are then singulated by cutting the protrusions71that join adjacent interposers40of the panel of interconnected interposers.

In some examples, the stiffener66can define a hole that extends from the first stiffener surface67ato the second stiffener surface67balong the transverse direction27. Thus, a wirebond can extend through the hole of the stiffener66, through a second hole of the second electrically insulative layer50of the type described above, and to the electrically conductive layer44. The hole of the stiffener66, in combination with the second hole of the second electrically insulative layer50, provides access to mount a wirebond to the electrically conductive layer44at a location spaced from the outer perimeter of the electrically conductive layer44. The stiffener66can define the outermost layer of the interposer40with respect to the transverse direction27. Thus, the second stiffener surface67bcan define the outermost surface of the interposer40.

The stiffener66can have any suitable stiffener thickness along the transverse direction27from the first stiffener surface67ato the second stiffener surface67b. In one example, the stiffener thickness can be in a range from approximately 20 microns to approximately 150 microns, such as approximately 75 microns. It is appreciated that the stiffener66can have any suitable alternative thickness as desired. The first electrically conductive layer62can define a first thickness along the transverse direction27from the first surface46ato the second surface46b. Similarly, the second electrically conductive layer64can define a second thickness along the transverse direction27from the first surface65ato the second surface65b. The first and second thicknesses can be substantially equal to each other. Alternatively, the first and second thicknesses can be different than each other. In one example, the first and second thicknesses can be in a range from approximately 1 micron to approximately 25 microns. The first and second thicknesses can define any suitable alternative dimension as desired.

At least a portion of the interposer40can extend outward with respect to at least a portion of the outer perimeter of the IC die substrate24along at least one direction that is perpendicular to the transverse direction27. For instance, the interposer40can extend outward with respect to an entirety of the outer perimeter of the IC die substrate24along all directions that are perpendicular to the transverse direction27. Accordingly, the wirebond pads53can be disposed at a location that is outwardly spaced from the IC die substrate24along the at least one up to all directions that are perpendicular to the transverse direction27. Otherwise stated, the IC die substrate26is not aligned with the wirebond pads53along the transverse direction27. This reduces the risk of damaging the IC die substrate24during wirebonding.

The electrical contact pads45of the first electrically conductive layer62can be disposed along at least a portion up to an entirety of the outer perimeter of the interposer40. The electrical contact pads45can extend along all sides of the interposer40or may be absent from one or more sides. As shown inFIG.6, the electrical contact pads45of the first electrically conductive layer62can be disposed on all sides of the interposer40that define the outer perimeter of the interposer. Likewise, electrical contact pads55of the second electrically conductive layer64can be disposed on one or more sides of the interposer40along its perimeter. For instance, the interposer40can include first opposed sides57and second opposed sides59that extend between the first opposed sides57. The first opposed sides57can have respective lengths that are longer than those of the second opposed sides59. The sides57and59define the outer perimeter of the interposer40.

In one example, the electrical contact pads45of the first electrically conductive layer62can be arranged along each of the sides of the first opposed sides57. The electrical contact pads55of the second electrically conductive layer64can be arranged along each of the sides of the second opposed sides59. Thus, it should be appreciated that one or more sides of the interposer40that at least partially define the outer perimeter of the interposer40can have only electrical contact pads45of the first electrically conductive layer62, whereas one or more other sides of the interposer40that at least partially define the outer perimeter of the interposer40can include the electrical contact pads55of the second electrically conductive layer64. Still one or more sides can include both the electrical contact pads45of the first electrically conductive layer62and electrical contact pads55of the second electrically conductive layer64in other examples. The electrical contact pads45can be referred to as first electrical contact pads, and the electrical contact pads55of the second electrically conductive layer64can be referred to as second electrical contact pads. The electrical contact pads arranged along a side of the interposer40can be aligned with each other along a straight line that extends parallel to the length of the side. In some examples, either or both of the electrical contact pads45of the first electrically conductive layer62and the electrical contact pads55of the second electrically conductive layer64can be disposed in the interior of the interposer40away from the outer perimeter of the interposer40.

Referring now toFIG.7, and as described above, an optical transceiver75can include at least one wirebondable IC assembly58. The optical transceiver75includes a host substrate72that is configured to transmit and receive high speed electrical signals (e.g., at the high data transfer speeds described above). The host substrate72can be configured as a printed circuit board (PCB). These high-speed signals may be electrically connected from one or more electrical contact pads on the host substrate72to a corresponding one or more electrical contact pad of the interposer40(such as one or more of the electrical contact pads45). In this example, the host substrate72can define the external substrate described above. Similarly, high speed electrical signals may be communicated between an electrical contact pad on an optical-to-electrical (O/E) element or an electrical-to-optical (E/O) element and a contact pad of the interposer40(such as one or more of the electrical contact pads45) using a wirebond56. These wirebonds56can be disposed on opposed sides of the interposer40as shown inFIG.7. It is recognized that during operation, most up to all of the contact pads56of the interposer40may have wirebond connections56.

In some examples, it can be desirable for the wirebonds56that attach to the electrical contact pads45of the first electrically conductive layer62to be shorter in length than the wirebonds56that attach to the electrical contact pads55of the second electrically conductive layer64. Accordingly, the wirebonds56that attach to the electrical contact pads45of the first electrically conductive layer62can be particularly suitable to transmit electrical signals at high speeds described herein greater than 10 gigabits per second, such as up to 56 gigabits per second. The wirebonds56that attach to the electrical contact pads55of the second layer64can be longer and thus configured to transmit power and/or control signals whose integrity is that less sensitive to the wirebond length compared to high speed electrical signals.

The high-speed electrical signals may be processed in the IC die substrate24. An example of an E/O element is a VCSEL (Vertical Cavity Surface Emitting Laser), which takes an incoming high-speed electrical signal and outputs a modulated light beam. An example of an O/E element is a photodetector, which receives an incoming modulated light beam and outputs a modulated electrical signal. Wirebonds56can further establish control and power electrical connections between the interposer40and host substrate72. The respective contact pads45that receive or transmit control and power electrical connections of the interposer40can be disposed on sides of the interposer40that are adjacent the sides of the interposer40having contact pads45that receive or transmit high speed electrical signals. The O/E and E/O elements and the IC die substrate24can be attached to a riser77that provides a heat transfer path to remove heat from these elements during operation. The IC die substrate24can be mounted such that the outer active surface26of the IC die substrate faces away from the riser and host substrate72.

To maintain good signal integrity at high data transfer speeds, (such as exceeding 10 gigabits per second (Gbps), it can be desirable to minimize the length of the wirebond56. In some examples, the wirebonds56can be less than approximately 2 mm, such as less than approximately 1 mm. It is recognized that the interposer40can have a small thickness along the transverse direction27can allow for short wirebond lengths. For instance, the interposer40can have a thickness along the transverse direction27that is in a range from 3 microns to 500 microns, for instance from approximately 50 microns to approximately 300 microns, including from approximately 100 microns to approximately 150 microns. In one particular example, the thickness of the interposer can be approximately 100 microns. In another particular example, the thickness of the interposer can be approximately 150 microns. It is recognized that these ranges of the interposer thickness are provided by way of example only, and that the interposer40can have any suitable alternative thickness as desired.

Referring now toFIGS.8A-8F, a method is provided for fabricating at least one of the wirebondable IC assemblies58, such as a plurality of the wirebondable IC assemblies58. In one example, a plurality of wirebondable IC assemblies58can be produced simultaneously and in a cost effective manner. As illustrated inFIG.8A, a plurality of interposers40can be formed on a single panel82and retained by a vacuum chuck84. The panel82can contain as many interposers40as desired, within a range from 1 to approximately 100, such as approximately 70 interposers40. As will now be described, a plurality of wirebondable IC die assemblies58equal in number to the interposers40of the panel82can be fabricated in parallel. Panels82with more than 100 individual interposers40are also envisioned.

In particular, the vacuum chuck84can have a flat surface86, and a vacuum can apply a force to the panel82that retains the interposers40and flattens the panel82of interposers40. The vacuum chuck84can, for instance, be coupled to the outermost layer of the interposers40, for instance at the outer surface of the outermost layer. As illustrated inFIG.8B, a normal flip chip attachment process using reflow, such as solder reflow, can be made between the interposers40and a respective plurality of IC dies20. Flux can be used to facilitate solder wetting. After attachment of the interposers40to the respective IC dies20, a cleaning step can be performed that removes the flux from the wirebondable IC assembly58. As illustrated inFIG.8C, an underfill, which can be configured as the epoxy resin60, can be injected into the gap between the IC die20and the interposer40. The underfill can increase the mechanical robustness of the wirebondable IC die assembly58. Referring now toFIG.8D, the panel82of interposers40of the wirebondable IC die assembly58can be removed from the vacuum chuck84, and mounted onto a backer layer88. Thus, the backer layer88can be mounted to the outermost layer of the interposers40, for instance at the outer surface of the outermost layer. The backer88can be configured as a glass backer having an ultraviolet (UV) light release bonding agent on an attachment surface to which the panel82of interposers40are bonded. As illustrated inFIG.8E, a singulation step can dice the panel82of interposers40into a plurality of singulated interposers40that are separated from each other. The singulated interposers40remain supported by the backer layer88. Referring toFIG.8F, the backer layer88can be exposed to UV light, which can release the individual and singulated wirebondable IC die assemblies58from the backer layer88. Thus, the wirebondable IC die assemblies58can be subsequently easily removed from the backer layer88.

Referring now toFIG.9, while examples have been described above as having a single IC die20electrically connected to an interposer40to define the wirebondable IC assembly58, it is recognized that the wirebondable IC assembly58can include multiple flip chip IC dies20that are electrically connected to a single interposer40. For instance, a first IC die20a, a second IC die20b, and a third IC die20ccan be mounted to a single interposer40. The IC dies20a-20ccan be attached to the interposer40as described above, but the reflow step can mount and secure all three dies IC20a-20cto the interposer40. It is appreciated that the electrical interfaces36and the wirebond pads53described above are not shown inFIG.9, as they are hidden from view.

In order to conserve valuable real estate on a substrate that accepts the interposer40, it can be desirable to limit the footprint of the interposer40to only slightly larger than the footprint of the IC die20along respective planes that are perpendicular to the transverse direction27. In some examples, the footprint of the interposer40is no more than approximately twice the size of the footprint of the one or more IC dies20that are flip-chip mounted to the interposer. For instance, in some examples, the footprint of the interposer40is no greater than approximately 50% larger than the footprint of the one or more IC dies20that are flip-chip mounted to the interposer40. In still other examples, the footprint of the interposer40is no more than 20% greater than the footprint of the one or more IC dies20that are flip-chip mounted to the interposer40. The footprints can refer to a two-dimensional outline or a size of a major surface of the element in a plane that is oriented perpendicular to the transverse direction27.

While the interposer40has been described above in accordance with certain examples, it is appreciated that the interposer40can be constructed in accordance with any suitable example as desired. For instance, referring now toFIG.10, in another example, it is recognized that the first and second electrically conductive layers62and64can be placed in electrical communication with each other in accordance with any suitable alternative examples as desired. For instance, the interposer40, and thus the wirebondable IC assembly58, can include at least one or more electrically conductive through vias68that place the first and second electrically conductive layers62and64in electrical communication with each other.

The second electrically insulative layer50can be disposed on or otherwise supported by the second electrically conductive layer64instead of the stiffener66or in addition to the stiffener66(seeFIG.5). The second electrically insulative layer50can be disposed on or otherwise supported by the second surface65bof the second electrically conductive layer64. For instance, the second electrically insulative layer50can extend along the second surface65b, and can further extend over a portion of the second surface65bof the second electrically conductive layer64. The second electrically insulative layer50can define the outermost layer of the interposer40with respect to the transverse direction27. The second electrically insulative layer50can further define the second holes54that extend from the first surface51ato the second surface51balong the transverse direction27, thereby exposing the second electrically conductive layer64, and in particular the second surface65bof the second electrically conductive layer. Accordingly, the second electrically insulative layer50can expose the second electrically conductive surface of the at least one electrically conductive layer. Thus, exposed portions of the second conductive layer64can be said to be exposed through a respective plurality of second holes54in the second electrically insulative layer50.

The interposer40can include a third electrically insulative layer70that extends between the first electrically conductive layer62and the second electrically conductive layer64. Further, the third electrically insulative layer70can attach to the first and second electrically conductive layers62and64. The third electrically insulative layer70can further extend between the first electrically conductive layer62and the second electrically insulative layer50, and can attach to the first electrically conductive layer62and the second electrically insulative layer50. Thus, the first surface65aof the second electrically conductive layer64and the second surface46bof the first electrically conductive layer62can face and attach to the third electrically insulative layer70. In particular, a first surface of the third electrically insulative layer70can face the first electrically conductive layer62, and a second surface of the third electrically insulative layer70can face the second electrically conductive layer64. Thus, the third electrically insulative layer70can electrically isolate the first electrically conductive layer62from the second electrically conductive layer64. The electrically conductive vias68can extend through the third electrically insulative layer70from the first electrically conductive layer62to the second electrically conductive layer64. At least a portion up to all of the each at least one electrically conductive via68can be oriented along the transverse direction27. The electrically conductive vias68can mate to each of the first and second electrically conductive layers62and64, respectively, thereby establishing an electrical connection between the first electrically conductive layer62and the second electrically conductive layer64.

The first and second electrically conductive layers62and64can be patterned, and unwanted material of the first and second electrically conductive layers62and64can be etched away with the third electrically insulative layer70disposed between the first and second electrically conductive layers62and64with respect to the transverse direction27. The third electrically insulative material can be configured as a polyimide or any suitable alternative electrically insulative material as desired The first and second electrically insulative layers48and50can each be a liquid photoimageable (LPI) solder mask that is conformable to the first and second electrically conductive layers62and64, respectively, after the first and second electrically conductive layers62and64have been patterned. In particular, the first and second electrically insulative layers48and50can be applied to the first and second electrically conductive layers62and64, respectively, after the first and second electrically conductive layers62and64have been patterned. Thus, at locations where material of the first electrically conductive layer62has been etched away, the first and third electrically insulative layers48and70can contact each other. Similarly, at locations where material of the second electrically conductive layer64has been etched away, the second and third electrically insulative layers50and70can contact each other.

Patterned portions of the first electrically conductive layer62are in electrical communication with a respective pattern portion of the second electrically conductive layer64through one or more electrically conductive vias68, and are electrically isolated from other patterned portions of the second electrically conductive layer64by the third electrically insulative layer70. The patterned portions of the first electrically conductive layer62can further be electrically isolated from each other by the first electrically insulative layer48. Conversely, patterned portions of the second electrically conductive layer64are in electrical communication with a respective pattern portion of the first electrically conductive layer62through a via68, and electrically isolated from other patterned portions of the first electrically conductive layer62by the third electrically insulative layer70. The patterned portions of the second electrically conductive layer64can further be electrically isolated from each other by the second electrically insulative layer50.

The interposer40, and thus the wirebondable IC assembly58, can include any number of vias68as desired. The vias can be spaced from each other along any suitable center-to-center pitch as desired. The pitch can be defined along any suitable direction perpendicular to the transverse direction27. The pitch can be in a range from approximately 200 microns to approximately 500 microns as desired. In one example, the pitch can be approximately 300 microns, thereby providing a relatively small footprint of the wirebondable IC assembly58in a plane that is oriented perpendicular to the transverse direction27. The wirebond56can thus be mounted to the second electrically conductive layer64, such that the wirebond56is in electrical communication with the first electrically conductive layer62through the via68. Thus, the second electrically conductive layer64can define one or more wirebond pads53.

As described above, the respective layers of the interposer40can be substantially planar along respective planes that are oriented perpendicular to the transverse direction27. However, in yet another example illustrated inFIG.11A, the interposer40constructed in accordance with another example can include an electrically insulative layer90that defines a first or inner surface91athat faces the IC die20, and a second or outer surface91bopposite the inner surface91aalong the transverse direction27. The interposer40can further include at least one electrically conductive structure92that extends along each of the first surface91aand the second surface91b. For instance, the at least one electrically conductive structure92can include a first electrically conductive layer94that extends along at least a portion of the first surface91a, and a second electrically conductive layer96that extends along at least a portion of the second surface91b. The electrically insulative layer90can thus be disposed between the first and second electrically conductive layers94and96along the transverse direction27. Further, the electrically insulative layer90can be attached to each of the first and second electrically conductive layers94and96, respectively. The first and second electrically conductive layers94and96can be patterned in the manner described above, as desired.

The interposer40can further include a third electrically conductive layer98can extends along an exterior side surface94of the electrically insulative layer90that extends from the first surface91ato the second surface91b. The third electrically conductive layer98can extend from the first electrically conductive structure92and the second electrically conductive layer94. Thus, the third electrically conductive layer98can be oriented perpendicular to each of the first and second electrically conductive layers94and96. The third electrically conductive layer98can be patterned as described above, such that patterned portions of the third electrically conductive layer98place respective pattered portions of the first electrically conductive layer94in electrical communication with respective patterned portions of the second electrically conductive layer94. Either or both of the first and second electrically conductive layers94and96can define through holes so as to expose respective portions of the first and second surfaces91aand91bof the electrically insulative layer90.

The first electrically conductive layer94can define or support the contact pad45, and the second electrically conductive layer96can define one or more wirebond pads53. The first, second, and third electrically conductive layers94,96, and98can be defined by the same material, such as a metal, and can be monolithic with each other. Alternatively, one or more up to all of the first, second, and third electrically conductive layers94,96, and98can be made of different materials. Alternatively or additionally, one or more up to all of the first, second, and third electrically conductive layers94,96, and98can define separate layers that are in electrical communication with each other. It should be appreciated that the at least one electrically conductive layer described above can be at least partially defined by the first and second electrically conductive layers94and96, alone or in combination with the third electrically conductive layer98.

The at least one electrically conductive structure92can thus be said to wrap around the electrically insulative layer90. The electrically conductive interface36can be placed between the first electrically conductive layer94and the flip chip IC die in the manner described above, and reflowed to mount the interposer40to the IC die. Thus, the first electrically conductive layer94can be disposed at the first side42aof the interposer40. A wirebond56can be mounted to the second electrically conductive layer96, thereby placing the wirebond56in electrical communication with the electrically conductive interface36. Thus, the second electrically conductive layer96can be disposed at the second side42bof the interposer40. It should therefore be appreciated that the interposer40can place a wirebond56in electrical communication with a flip chip die20without fabricating or otherwise providing holes that extend through the electrically insulative layer90. In other words, instead of the electrical connection between the electrically conductive interface36and the wirebond56(or between the contact pad45and wirebond pad53) extending through an electrically insulative layer in the manner described above, the electrical connection between the electrically conductive interface36and the wirebond56(or between the contact pad45and wirebond pad53) can extend around the electrically insulative layer90. In both examples, the electrical connection extends from a first side of an electrically insulative layer to a second side of an electrically insulative layer.

As described above, each of the first electrically conductive layer94and the second electrically conductive layer96can be patterned as desired. Each of the first and second electrically conductive layers94and96can define single access layers. That is, electrical connections defined by the electrically conductive interface36and the wirebond56are only made to a first side and a second side of the first electrically conductive layer94and the second electrically conductive layer96, respectively. The respective first and second sides of the first and second electrically conductive layers94and96can face away from the electrically insulative layer90and from each other. Having the first and second electrically conductive layers94and96each being a single access metal layer, may in some situations be advantageous as compared to a single metal layer with double access. For example, it may be easier to source a two metal layer laminate as compared to a single metal layer laminate. Bonding agents or protective films for the laminates may also be more readily available for a two metal layer laminate. As described above, the interposer40can include a plurality of electrically conductive structures92that place respective electrically conductive wirebond pads53in electrical communication with respective electrical contact pads45, and thus wirebonds56that are mounted to the wirebond pads53in electrical communication with electrical interfaces36that are mounted to the electrical contact pads45, respectively. The electrically conductive structures can be electrically isolated from each other by the electrically insulative layer90. As illustrated inFIG.11B, the interposer40can include a second electrically insulating layer61that is attached to the second electrically conductive layer96on a second side of the second electrically conductive layer46side that is opposite a first side of the second electrically conductive layer96that faces the electrically insulative layer90, which can be referred to as a first electrically insulative layer. The second insulating layer61can define through holes63that expose the wirebond pads53on the second electrically conductive layer96.

It should be appreciated that the illustrations and descriptions of the examples shown in the figures are for exemplary purposes only and should not be construed as limiting the disclosure. One skilled in the art will appreciate that the present disclosure contemplates various embodiments. For example, the stiffener may be used as a mounting surface for additional components, such as a heat sink or some other electrical component. Terms such as above and below are relative to the orientation of the various elements described in the figures and need not describe the orientation of the element in a final product. Additionally, it should be understood that the concepts described above with the above-described embodiments may be employed alone or in combination with any of the other embodiments described above. It should further be appreciated that the various alternative embodiments described above with respect to one illustrated embodiment can apply to all embodiments as described herein, unless otherwise indicated.