Patent ID: 12218083

The drawings are provided as examples and do not limit the invention. They are schematic representations intended to facilitate understanding of the invention and are not necessarily drawn to the scale of practical applications. In particular, the thicknesses and dimensions of the various layers, via holes, and patterns in the schematics are not representative of reality.

DETAILED DESCRIPTION

Before entering into a detailed review of embodiments of the invention, optional features which may possibly be used in combination or as alternatives are given below:

According to one example, the residual stress is compressive (σr<0). This promotes the occurrence of oscillations after trench etching.

According to one example, the thickness hmof the metal mask layer is greater than nm. This increases the amplitude of the oscillations.

According to one example, the walls have an aspect ratio of hd/l≥2. This increases the amplitude of the oscillations.

According to one example, the walls are substantially the same length. According to one example, the walls are continuous along the entire length thereof. According to one example, the walls have a length substantially corresponding to a dimension of the individualization zone. According to one example, the walls pass through the individualization zone.

According to one example, the ratio of the thicknesses of the at least one dielectric layer and of the metal mask layer is such that 2≥hd/hm≥1. This increases the amplitude of the oscillations.

According to one example, the thickness hdof the at least one dielectric layer is greater than 100 nm.

According to one example, the metal mask is made of or based on one of the following materials: Ti, TiN, TaN. It may also be made of any metal, the residual stress of which can be controlled during deposition, similarly to TiN.

According to one example, the at least one dielectric layer comprises a layer based on dense SiOCH or porous SiOCH (p-SiOCH), or based on SiO2.

According to one example, the line patterns are straight before etching of the at least one dielectric layer.

According to an alternative example covered by the present invention, the line patterns are curvilinear before etching of the at least one dielectric layer. The random oscillations created after etching are superimposed on the initial straight or curvilinear line pattern, that is, before etching.

According to one example, the second level of electrical tracks is formed in such a way that the electrical tracks of the second level also have random oscillations. Typically, the second level of electrical tracks is formed in a similar way to the formation of the first level of electrical tracks. This increases the probability of defective connections between the electrical tracks of the first and second levels.

According to one example, the chip has at least one other zone, separate from the individualization zone, intended to form a functional zone of the chip.

According to one example, the method further comprises the following steps:forming a protective mask in the individualization zone on the metal mask layer prior to formation of the line patterns,etching the metal mask layer in the functional zone, outside the individualization zone, so that the metal mask layer in the functional zone has a thickness hr<hm,removing the protective mask before forming the line patterns in the individualization zone.

According to one example, the line patterns are formed successively in the functional zone and in the individualization zone.

According to one example, the electrical tracks of the first level of the functional zone are straight.

The electrical tracks with random oscillations are only made in the at least one individualization zone. The integrated circuit has at least one other zone, separate from the individualization zone, that is preferably intended to form a functional zone for the integrated circuit. This other zone typically has a larger surface area than the surface area of the individualization zone. The first and the second levels of electrical tracks, as well as the level of interconnections, extend into said at least one other zone. As is conventional, the functional zone of the integrated circuit comprises logical inputs and outputs. This functional zone is intended to perform logical functions for the expected operation of the integrated circuit. Apart from the electrical tracks, this functional zone may comprise microelectronic structures such as, for example, transistors, diodes, MEMS, and so on.

As for the individualization zone, its function is to make each integrated circuit unique.

As part of the present invention, a so-called PUF individualization zone is perfectly differentiated from a functional zone intended, for example, to perform logical operations. As for the individualization zone, it primarily and preferably has the sole function of allowing for unique identification of the chip and therefore its authentication of the chip. The individualization zone is accessible separately from the functional zone. The individualization zone is located in a well-delimited zone of the chip. For example, the individualization zone has a polygonal shape, such as that of a rectangle. In this way, not any defective zone can be assimilated to a PUF individualization zone. Likewise, not any non-defective zone can be assimilated to a functional zone.

The functional zone typically has a surface area that is at least twice as large as that of the individualization zone. The individualization zone extends over at least 5% and preferably over at least 10% of the surface of the integrated circuit.

In the present application, the terms “chip” and “integrated circuit” are used as synonyms.

In the present application, the terms “oscillations” and “undulations” are used as synonyms. These terms refer to a sine wave shape consisting of alternating concave and convex curves. The oscillations are not necessarily periodic. They are superimposed over the line pattern initially conceived by the arrangement plan of the circuit or layout, which is the term commonly used to refer to such an arrangement plan. The expressions “arrangement plan” and “layout” are equivalent and can be used interchangeably.

The residual stress in the metal mask layer can depend on the material of the metal mask, the technique used to deposit the layer, and the deposited thickness. A person skilled in the art generally knows what residual stress will remain in such a layer, such as by means of nomograms. Various characterization techniques (for example, measuring the radius of curvature of a plate on which the layer is fully deposited) commonly used in the microelectronics industry also make it possible to measure this residual stress.

Note that, in the context of this invention, the term via hole encompasses all electrical connections such as pads, lines, and conductive structures which run, preferably perpendicularly, between two layers of the integrated circuit, whether adjacent or not, that is, between two levels of electrical tracks. Each level of electrical tracks lies primarily in a plane and can include functional micromechanical or microelectronic structures such as transistors, for example. Preferably, each via hole forms a pad with a substantially circular cross-section.

In the context of this invention, a via hole has a critical dimension CDvia, such as a diameter, taken according to a cross-section parallel to the various levels of the integrated electrical tracks. Preferably, CDviais less than 100 nm. Preferably, CDviais between 10 nm and 70 nm.

Note that, in the context of this invention, the terms “on,” “sits over,” “covers,” “underlying,” “opposite,” and equivalents thereof do not necessarily mean “in contact with.” For example, the deposition, addition, bonding, assembly, or application of a first layer on a second layer does not necessarily mean that the two layers are directly in contact with one another, but does mean that the first layer covers the second layer at least in part by being either directly in contact therewith or by being separated therefrom by at least one other layer or at least one other element.

Furthermore, a layer may be composed of a plurality of sub-layers of a same material or of different materials.

A substrate, film, layer, or structure “based” on a material A is understood to be a substrate, film, layer, or structure solely comprising said material A, or comprising this material A and possibly other materials, for example doping agents.

Several embodiments of the invention implementing successive steps of the manufacturing method are described below. Unless explicitly stated otherwise, the adjective “successive” does not necessarily mean that the steps immediately follow each other, even if that is generally the preferred meaning, and so there may be intermediate steps between them.

In addition, the term “step” refers to a portion of the method and may designate a set of sub-steps.

Furthermore, the term “step” does not necessarily means that the actions taken during a step are simultaneous or immediately follow each other. In particular, certain actions of a first step may be followed by actions associated with a different step, and other actions of the first step may be resumed later. Thus, the term step is not necessarily understood as unitary and inseparable actions over time and in the sequence of phases in the method.

Thus, according to one possibility, the formation of the first and second levels can be reversed and the second level can be formed before the first level. The designation of “first” level and “second” level is arbitrary. The method also covers the case in which the formation of the “second” level is configured so that the electrical tracks of the “second” level are a function of the random oscillations generated by the implementation of the method.

The word “dielectric” refers to a material with an electrical conductivity that is low enough in the given application to be used as an insulator. In the present invention, a dielectric material preferably has a dielectric constant of less than 7.

“Selective etching with respect to” or “etching having a selectivity with respect to” is understood as an etching configured to remove a material A or a layer A with respect to a material B or a layer B, and having an etch rate of material A that is greater than the etch rate of material B. The selectivity is the ratio between the etch rate of material A to the etch rate of material B.

In the context of this invention, an organic material or organo-mineral material which can be shaped by exposure to a beam of electrons, photons, or X-rays, or mechanically, is considered a resin.

As an example, let us mention resins typically used in microelectronics, resins based on polystyrene (PS), methacrylate (for example Polymethyl MethAcrylate, PMMA), Hydrogen Silsesquioxane (HSQ), polyhydroxystyrene (PHS), and so on. The interest of using a resin is that it is easy to deposit a large thickness of it measuring several hundred nanometers to several microns.

Anti-reflective layers and/or coatings can be associated with the resins. In particular, this helps to improve the lithographic resolution. In the remainder of this document, the various resin-based masks are preferably associated with such anti-reflective layers.

According to one example, the metal mask can be considered a hard mask. The metal mask layer can be considered a hard metal mask layer.

The mask is considered “hard” for the sake of differentiating it from resin-based masks. It withstands the etching customarily used for etching resin masks.

An orthonormal coordinate system comprising the x, y, and z axes is shown in the appended figures. When a single coordinate system is shown on the same plate of figures, the coordinate system applies to all the figures on the plate.

In the present patent application, the word thickness will preferably be used for a layer and the word depth for an etching. The thickness is measured in a direction perpendicular to the primary extension plane of the layer, and the depth is measured perpendicularly to the basal plane xy of the substrate. Thus, a layer lying parallel to the basal plane typically has a thickness in the z direction, and an etching also has a depth in the z direction. The relative terms “on,” “sits over,” “below,” and “underlying” refer to positions considered in the z direction.

An element located “above” or “at” another element means that the two elements are both on a same line perpendicular to a plane in which a lower or upper surface of a substrate extends, that is, on a same line oriented vertically in the figures.

FIG.1shows a schematic of a portion of an integrated circuit comprising a first level10A of electrical tracks10, and a second level20A of electrical tracks20. Each of these levels10A and20A lies primarily along a plane. These planes are substantially parallel to each other and to a substrate, not shown, on which this first level10A and this second level20A of electrical tracks10and20rest. The integrated circuit also comprises a level of interconnections30A or conductor layer30A configured to electrically connect tracks of the first level10A to tracks of the second level20A, possibly redundantly. This conductor layer30A comprises conductive portions generally considered to be via holes30. Note that via holes30can connect tracks of two levels that are not adjacent but which are themselves separated by one or more other levels.

FIGS.2A to2Eschematically show the conventional steps for forming a level of electrical tracks, typically a first level10A.

A stack in the z direction of dielectric layers200,201, and202is first formed on a substrate100(FIG.2A). This stack of dielectric layers200,201, and202has a thickness hdand may comprise the following layers starting with substrate100:Optionally, an etch stop layer201, for example based on SiCN. This SiCN layer201is typically applied by plasma-enhanced chemical vapor deposition (PECVD). It may have a thickness that is on the order of 20 nm.A dielectric layer200, such as a layer of silicon oxide doped with carbon, SiOCH. This SiOCH layer can be dense or porous (p-SiOCH), with, for example, a porosity on the order of 25%. It typically has a low dielectric constant such as on the order of 2.5. It can thus be considered a ULK (Ultra-Low k) layer. This SiOCH layer200can be deposited by PECVD. It may have a thickness that is typically between 50 nm and 300 nm.Optionally, a silicon oxide layer202. This layer202can be deposited by PECVD. It may have a thickness that is between 20 nm and 100 nm.

A hard metal mask layer300, also referred to as a hard metal mask300or simply mask300, is then formed on the stack of dielectric layers200,201, and202(FIG.2A). This mask300can be based on titanium, Ti, or titanium nitride, TiN, or tantalum nitride, TaN. According to one embodiment, the metal mask300is made of titanium nitride. It can be formed by physical vapor deposition (PVD). The mask300typically has a thickness hmand a residual stress σr. The residual stress σrgenerally depends on the deposition technique and/or parameters. It may be tensile (σr>0) or compressive (σr<0). Conventionally, the aim is to minimize this residual stress σr.

The metal mask300is structured by means of a mask400having openings401(FIG.2B). These openings401of the mask400serve, in particular, to open the metal mask300. Depending on the technique implemented to open the mask300, the mask400can be made of one or more layers. It can be based on a resin, for example photosensitive resin, for example with a positive tone. A bottom anti-reflective coating (BARC) is preferably placed between the metal mask300and the mask400. The mask400made of photosensitive resin can have a thickness of between 100 nm and 500 nm. The anti-reflective coating can have a thickness of between 20 nm and 80 nm.

Alternatively, the mask400may comprise two SOC (Spin On Carbon) and SiARC (Silicon Anti-Reflective Coating) layers, as well as a layer of photosensitive resin. The thicknesses of these three layers vary according to the type of products used and the dimensions of the via holes in question. They are typically on the order of 150 nm for SOC, 30 nm for SiARC, and about 100 nm for resin.

Preferably, the mask layer or layers400, and possibly the anti-reflective coating, are deposited using a conventional spin coating method.

The openings401of the mask400are made by implementing conventional lithography techniques such as optical lithography, electron beam (ebeam) lithograph, nanoimprint lithography, or any other lithography technique known to a person skilled in the art.

The anti-reflective coating and the metal mask300can be etched by plasma using chlorine-based etching chemistry, such as CI2/BCI3. This type of plasma makes it possible to use a mask400based on resin with a thin thickness, for example less than 200 nm.

Upon completion of this etching, the mask300comprises line patterns310, separated by mask openings301(FIG.2B). The line patterns310typically have a width l. They are intended to be transferred to the underlying stack of dielectric layers200,201, and202.

After opening of the mask300and removal of the mask400, typically by oxygen plasma, the stack of dielectric layers200,201, and202is etched so as to form trenches210(FIG.2C). The dielectric layers200and202are preferably etched by plasma, for example by fluorine plasma. To do this, fluorocarbon chemistry, C4Fa/N2/Ar/O2, can be used The etch stop layer201based on SiCN is typically opened by plasma based on CH3F/CF4/N2/Ar chemistry so as to expose the substrate100.

The trenches210are separated by walls211based on the layers200,201, and202. These walls211typically have a height hdand a width l (FIG.2C). The line patterns310are above them.

In a preferred but optional way, a barrier layer40is then deposited in a compliant way at the bottom of the trenches210, on the walls211and the line patterns310. The purpose of this barrier layer40is to avoid diffusion of the track metal in the dielectric layer200.

The trenches210are then filled with an electrically conductive material50—typically copper (FIG.2D).

A planarization step, for example by chemical-mechanical polishing, CMP, is performed after filling of the trenches210so as to remove the excess conductive material. This CMP also removes the line patterns310. The electrical tracks10of the first level10A are thus formed (FIG.2E).

By implementing this method typically known by the name “damascene,” a person skilled in the art can make straight electrical tracks10on a first level10A, as shown as a top view inFIG.3A.

These tracks10and10OKcan then be connected to via holes30and30OKof the conductor layer30A. The formation of these via holes30is already known. The tracks10OKand the via holes30OKare thus formed according to the layout of the integrated circuit. The via holes30OKare functional via holes electrically connected to the electrical tracks10OKof the first level10A.

In order to make an individualization zone of the integrated circuit, the manufacturing method described above is modified so as to form tracks10KOhaving oscillations or undulations and/or variations in width, as shown as a top view inFIG.3B.

The via holes formed according to the layout of the integrated circuit are no longer perfectly superimposed over the oscillating electrical tracks10KO. The via holes30then comprise functional via holes30OKand dysfunctional or inactive via holes30KO1and30KO2. The dysfunctional via holes30KO1typically are partially connected to the electrical tracks10KOof the first level. In particular, the electrical resistance thereof is much higher than the functional via holes30OK. The inactive via holes30KO2are typically connected to the electrical tracks10KOof the first level.

According to one possibility, the dysfunctional via holes30KO1are identified, for example, by measuring the resistance thereof. It is then preferable to deactivate them. This freezes their electrical behavior. This improves the stability of the integrated circuit's response curve overtime.

FIG.4is a top-view electron microscope image showing oscillations obtained in the line patterns310when etching the trenches210.

In order to obtain such oscillations, the method described above in reference toFIGS.2A to2Eis adapted by choosing the values of the parameters of the residual stress σr, width l, and thicknesses hdand hm. The values of the parameters preferably lie within the following ranges:

The residual stress v, is negative (tensile) and preferably less than 1000 MPa.

The width l of the line patterns310is less than 90 nm and preferably less than 70 nm.

The thickness hmof metal mask300is preferably greater than 15 nm.

The thickness hdof the at least one dielectric layer is preferably greater than 100 nm.

FIG.5contains curves c1, c2, c3, and c4defining regions where the undulation phenomenon occurs in the line patterns310when the trenches210are etched. These curves determine in part which residual stress σrvalues are necessary for a given width l of the line patterns310and for a given thickness hmof metal mask300. The curves c1, c2, c3, and c4ofFIG.5have been simulated for a height of wall211of hd=180 nm. These curves c1, c2, c3, and c4form a nomogram to which a person skilled in the art can refer to intentionally generate undulations when etching the trenches210.

Thus, for a height of wall211of hd=180 nm, the pairs of values (σr; l) located beneath each curve c1, c2, c3, and c4give rise to the occurrence of undulations when etching the trenches210. Curve c1corresponds to a thickness of mask300of hm=45 nm. Curve c2corresponds to a thickness of mask300of hm=35 nm.

Curve c3corresponds to a thickness of mask300of hm=25 nm.

Curve c4corresponds to a thickness of mask300of hm=15 nm.

Note that for a given height of wall211, typically hd=180 nm in the present case, the greater the width l of the line patterns310to be etched, the greater the thickness hmof mask300must be (for a constant residual stress σr) to generate oscillations. For a constant thickness hmof mask300, the greater the width l of the line patterns310, the greater the residual stress σrmust be (in negative values) to generate oscillations.

Furthermore, according to another nomogram of curves not shown, it must be noted that for a constant thickness hmof mask300, the greater the width l of the line patterns310, the greater the height hdof wall211must be to generate oscillations.

The parameters σr, l, hm, and hdcan be chosen, for example, as a function of the curves shown inFIG.5, in the form of a measured or simulated nomogram. Such a nomogram can be easily made by a person skilled in the art according to the desired wall height. This makes it possible to know whether the oscillations are actually generated or not as a function of the values of the other parameters. It is possible to obtain similar nomograms by setting another of the parameters, for example for a given mask thickness or for a given line width. In this way, for example, it is possible to evaluate the parametric range for obtaining oscillations for different wall heights.

The parameters can be chosen so as to obtain sufficient undulation amplitudes to allow for a poor connection of certain via holes to the electrical tracks created from said undulations. For instance, a sufficiently high residual stress σrcan be chosen to enable a deformation of the line patterns. According to one possibility, the critical dimension CDviaof the via holes (typically the diameter) is less than the width l of the line patterns310. This increases the probability of having a via hole not superimposed over the electrical track associated with it in the layout.

FIG.6shows an example of wall211with, above it, a line pattern310that gives rise to such undulations when the trenches210are etched. The wall211typically comprises an etch stop layer201made of SiCN with a thickness of 20 nm, a dielectric layer200made of p-SiOCH with a thickness of 120 nm, and a dielectric layer202made of SiO2 with a thickness of 40 nm. The wall211thus has a height hd=180 nm. This wall211has, above it, a line pattern310made of TiN with a thickness hm=35 nm. The wall211and the line pattern310typically have a width l≤50 nm.

The invention is typically implemented to make an individualization zone1(PUF zone) in an integrated circuit further comprising a functional zone2(non-PUF zone). In this case, the method for making the individualization zone is only implemented on a portion of the integrated circuit.

FIGS.7A to7Hshow an example of the fabrication of PUF and non-PUF zones on the same integrated circuit.

As shown inFIG.7A, the same stack comprising the at least one dielectric layer200,201,202and the metal mask300is formed in PUF1and non-PUF2zones. At this point, the metal mask300has the same thickness hmin each of the PUF1and non-PUF2zones. In order to modulate this thickness hmas a function of the PUF1and non-PUF2zones, a protective mask500is first deposited in the PUF1zone. This protective mask500can be based on resin, similarly to the mask400based on resin used for the lithography structuring of the metal mask300.

The thickness hfof metal mask300is reduced in the non-PUF zone2, while the PUF1zone remains protected (FIG.7B). This reduced thickness can be achieved by a full-plate etching step known by the name “etch-back.”

After the thickness hrof metal mask300has been reduced in the non-PUF zone2, the conventional “damascene” method of lithography/etching can be implemented in the non-PUF zone2while protecting the PUF1zone with a protective mask500(FIG.7C).

Trenches210are thus made in the stack of the non-PUF zone2(FIG.7D). The walls211with the line patterns310formed in this non-PUF zone2do not have oscillations. This makes it possible to form a level of functional metal tracks. The protective mask500is then removed from the PUF1zone so that the modified “damascene” lithography/etching method described earlier can be implemented in the PUF1zone. Trenches210are thus made in the stack of the PUF1zone, while the non-PUF2zone is protected by a protective mask500(FIG.7E). After etching of the trenches210, the walls211with, above them, line patterns310formed in this PUF1zone, have oscillations (FIG.7F). This makes it possible to form a level of dysfunctional metal tracks having width and/or position variations and/or undulations.

FIG.8shows a top-view schematic of the electrical tracks formed in zones PUF1and non-PUF2after filling of the trenches and planarization. The electrical tracks10OKof the first level of the non-PUF zone2are typically straight, whereas the electrical tracks10KOof the first level of the PUF1zone have random width undulations/variations.

Thus, when the via holes are formed according to the initial layout of the integrated circuit, the via holes of the non-PUF zone2are functional via holes30OK, and the via holes of the PUF zone1comprise dysfunctional or inactive via holes30KO1,30KO2(FIG.9). The via holes are typically formed simultaneously in the PUF1and non-PUF2zones.

FIG.10shows a top view schematic of the electrical tracks20OKof the second level formed in the PUF1and non-PUF2zones. The electrical tracks20OKof the second level are typically formed simultaneously in the PUF1and non-PUF2zones according to the initial layout of the integrated circuit.

In light of the foregoing description, it is clear that the proposed method offers a particularly effective solution for making a PUF individualization zone.

The invention is not limited to the embodiments described above and indeed extends to all the embodiments covered by the claims.

The embodiment described above is integrated into the manufacture of semiconducting compounds on the so-called “copper” back end. Nevertheless, the invention extends to embodiments using a conductive material other than copper. To that end, a person skilled in the art will know how to easily make the necessary adaptations in terms of the choice of materials and method steps.

Other embodiments of the method are obviously possible. For instance, the method can be implemented to generate oscillations in the first level10A of electrical tracks and/or in the second level20A of electrical tracks in an individualization zone. This further increases the probability that certain via holes of the conductor layer of an individualization zone will be poorly connected to the electrical tracks of one and/or the other of the first and second levels.

In addition, in the embodiments described in reference to the figures, the first level, the one in which the tracks are a function of the oscillations, is formed before the second level of electrical tracks. However, the invention covers those cases in which the first level, the one in which the tracks are a function of the oscillations, is formed after the second level of electrical tracks.

Furthermore, it is possible for the line patterns of the first and second levels not to be straight, as shown inFIGS.8to10, but instead curved.