Patent ID: 12206380

DETAILED DESCRIPTION

In the drawings, like reference numerals designate identical or corresponding parts throughout the several views. Further, as used herein, the words “a,” “an” and the like generally carry a meaning of “one or more,” unless stated otherwise.

Furthermore, the terms “approximately,” “approximate,” “about,” and similar terms generally refer to ranges that include the identified value within a margin of 20%, 10%, or preferably 5%, and any values therebetween.

Aspects of this disclosure are directed to a grounded positive and negative active inductor simulator (AIS) and impedance multiplier circuit. The grounded positive and negative active inductor simulator and impedance multiplier circuit can be configured as any one of an active inductor simulator, a capacitance multiplier, a positive resistance multiplier, a negative resistance multiplier, a negative active inductor simulator, and a negative capacitance multiplier by choosing the values of Z1and Z2. The described circuit includes only one second-generation voltage-mode conveyor (VCII+), one transconductance amplifier, OTA, and two passive elements.

In various aspects of the disclosure, non-limiting definitions of one or more terms that are used in the document are provided below.

The term “second-generation voltage-mode conveyor (VCII)” is defined as a dual circuit of a second-generation current conveyor (CCII), which provides the possibility of processing signals in the current domain while providing output signals in the voltage form. The VCII includes Y and X ports (input terminals) and Z port (output terminal). Y is a low-impedance current input port and X is a high-impedance current output port. For VCII, B is a current gain between the Y and X ports and α is a voltage gain between the X and Z ports. Vxand Vzare the voltages at the X and Z ports, respectively. IYand IXare the input current to the Y port and output current at the X port, respectively.

The term “plus type VCII (VCII+)” is defined as a second-generation voltage-mode conveyor (VCII) in which current in the X terminal flows in the same direction with respect to that related to the Y terminal. The VCII+ has +β (positive current gain).

The term “negative type VCII (VCII−)” is defined as a second-generation voltage-mode conveyor (VCII) in which current in the X terminal. The VCII− has −β (positive current gain).

The term “impedance simulator” is defined as a circuit that simulates an input impedance that may be one of inductive, capacitive and active (resistance). The impedance simulator is used for simulating the impedance of an electronic equipment under different power consumption platforms.

The term “capacitance multiplier” is defined as an electronic circuit that increases the value of a reference capacitor by a predefined multiplication factor, achieving a higher equivalent capacitance level in an IC form. The capacitor multipliers support design of complex integrated circuits possible that otherwise would be challenging with actual capacitors.

The term “impedance multiplier” is defined as a circuit that effectively magnifies the impedance presented by an external load. An example of impedance multiplier is an “impedance doubler”, which doubles the effective impedance of the external load. The impedance multiplier circuit includes an input impedance having a defined value of impedance and a circuit coupled to this input impedance for multiplying its value by a multiplication factor.

FIG.1is a high-level diagram illustrating an exemplary configuration of a tunable grounded positive and negative active inductor simulator and impedance multiplier circuit100(hereinafter referred to as the “circuit100”). Referring toFIG.1, the circuit100includes a second generation voltage-mode conveyor circuit (VCII+)110, a voltage source Vs, an operational transconductance amplifier (OTA)120and two passive components: a first impedance Z1, and a second impedance Z2.

The second generation voltage-mode conveyor circuit (VCII+)110includes a positive VCII+ input terminal Y, a first output terminal Z, and a second output terminal X. In an aspect, the VCII+110has a current gain β, and a voltage gain α. The voltage source Vsis configured to generate an output current Isat a frequency s.

The first impedance Z1is electrically connected between the voltage source Vsand the positive VCII+ input terminal Y. An internal circuit of the first impedance Z1includes a resistor R1and a capacitor C1, where the resistor R1is connected in parallel to the capacitor C1.

The second impedance Z2is electrically connected between the second output terminal X, and a ground terminal. An internal circuit of the second impedance Z2has a resistor R2and a capacitor C2, where the resistor R2is connected in parallel to the capacitor C2.

The operational transconductance amplifier (OTA)120is an amplifier whose differential input voltage produces an output current. For example, the OTA120is a voltage controlled current source (VCCS). In an aspect, the OTA120includes an additional input for a current to control a transconductance of the OTA120. In an example, the OTA120has a transconductance gain gm. The OTA120includes a positive OTA input terminal125, a negative OTA input terminal130, an OTA output terminal135, and a current bias IBinput terminal. In an aspect, the positive OTA input terminal125is connected to one of the first output terminal Z and the ground terminal. The negative OTA input terminal130is connected to one of the first output terminal Z and the ground terminal. The OTA output terminal135is connected to the first impedance Z1.

In an aspect, the grounded positive and negative active inductor simulator and impedance multiplier circuit100is configured to be tuned by a selection of a value for R1, a value for C1, a value for R2and a value for C2.

In an aspect, the OTA120is configured to generate an output current Io. In an example, the output current Iois given by Io=IxZ2gm=−IyZ2gm. The positive VCII+ input terminal Y is configured to receive an input current Iy. In an example, the Iyis equal to the difference between Isand I0. A voltage at the positive VCII+ input terminal Y is given by Vy, where Vy=0. The first output terminal Z is configured to generate a voltage Vz. The second output terminal X is configured to generate a voltage Vxacross the second impedance Z2. The second output terminal X is configured to generate a current ixthrough the second impedance, Z2, wherein ix=±βIyand Vz=αVx.

In one example configuration, the positive OTA input terminal125is electrically connected to the first output terminal Z, and the negative OTA input terminal130is connected to the ground terminal. In such configuration, an input impedance Zinof the VCII+110is given by

Zi⁢n=Z11+Z2⁢gm,where⁢Z2⁢gm⁢is≤1.

In an aspect, the circuit100is configured to operate as a tunable positive active inductor simulator by setting Z1=R1, C1=0, R2=0 and Z2=1/sC2, such that the input impedance is given by

Zi⁢n=s⁢C2⁢R120×IB=sL⁢where⁢L=C2⁢R120×IB.
In an aspect, a value of the inductor L can given by be tuned by the selection of the value of C2and the value of R1.

In an aspect, the circuit100is configured to operate as a tunable positive capacitance multiplier by setting Z1=1/sC1, R1=0, Z2=R2, and C2=0, such that the input impedance is given by

Zi⁢n=1s⁢C1(1+2⁢0×R2⁢IB),
in which the capacitance C1is multiplied by (1+20×R2IB). In an aspect, an amount of multiplication of C1is tuned by the selection of the value of R2.

In an aspect, the circuit100is configured to operate as a tunable positive resistance multiplier by setting Z1=R1, C1=0, Z2=R2, C2=0, such that the input impedance is given by

Zi⁢n=R1(1-2⁢0×R2⁢IB),
in which R1is multiplied by

1(1-2⁢0×R2⁢IB),where⁢0≤2⁢0×R2⁢IB<1.
In an aspect, an amount of multiplication of R1is tuned by the selection of the value of R2.

In one example configuration, the positive OTA input terminal125is connected to the ground terminal. The negative OTA input terminal130is connected to the first output terminal Z. The input impedance Zinof the VCII+ is given by

Zi⁢n=Z11+Z2⁢gm,where⁢Z2⁢gm>1.

In an aspect, the circuit100is configured to operate as a tunable negative active inductor simulator by setting Z1=R1, C1=0, R2=0 and Z2=1/sC2, such that the input impedance is given by

Zi⁢n=-s⁢C2⁢R120×IB=-sL⁢where⁢L=C2⁢R120×IB.
In an aspect, a value of the inductor L is tuned by the selection of the value of C2and the value of R1.

In an aspect, the circuit100is configured to operate as a tunable negative active capacitance multiplier is configured by setting Z1=1/sC1, R1=0, Z2=R2, and C2=0, such that the input impedance is given by

Zi⁢n=-1s⁢C1(1+2⁢0×R2⁢IB),
in which the capacitance, C1, is multiplied by (20×R2IB). In an aspect, an amount of multiplication of C1is tuned by the selection of the value of R2.

In an aspect, the circuit100is configured to operate as a tunable negative resistance multiplier by setting Z1=R1, C1=0, Z2=R2, and C2=0, such that the input impedance is given by

Zin=-R1(1-20×R2⁢IB),
in which R1is multiplied by

-1(1-20×R2⁢IB),where⁢0≤20×R2⁢IB<1.
In an aspect, an amount of multiplication of R1is tuned by the selection of the value of R2.

A relationship between voltage and currents terminals of VCII+110is represented as:
ix=±βiy,Vz=αVx,Vy=0,  (1)
where β is a current gain and α is a voltage gain.

The terminal characteristics of the VCII+110are high impedance at X node (input terminal) and low impedance at Y and Z nodes (output terminals).

With reference toFIG.1, the input impedance of the circuit100is given by:

Zin=VsIs=VsIy-Io,(2)i0=VZ×gm=ix⁢Z2⁢gm=-iy⁢Z2⁢gm.(3)

As, iy=Vs/Z1, the input impedance is given as:

Zin=Z11+Z2⁢gm,(4)
where, gm=20×IBis the OTA transconductance and IBis the OTA bias current.

From equation (4), the circuit100can be used to implement the tunable grounded active inductor and capacitance multiplier as follows:

I. Implementation as the Active Inductor Simulator (AIS)

If

Z1=R1,and⁢Z2=1sC2,
the input impedance is given by:

Zin=sC2⁢R120×IB=sL,(5)
where

L=C2⁢R120×IB.

Equation (5) implements the tunable AIS, and the value of the inductance is controlled using R1and IB.

II. Implementation as the Capacitance Multiplier

If

Z1=1sC1⁢and⁢Z2=R2,
then the input impedance is given by:

Zin=1sC1(1+20×R2⁢IB).(6)

The original capacitance (C1) is multiplied by (1+20×R2IB) and can be tuned using R2and IB.

FIG.2is an internal structure of a voltage-mode conveyor200, according to aspects of the present disclosure. For example, the voltage-mode conveyor200is a second-generation voltage conveyor (VCII). The VCII200includes a current buffer210and a voltage buffer220. The current buffer210is set up between the Y and X terminals, and the voltage buffer220set up between the X and Z terminals. Unlike a CCII, the Y terminal of the VCII200is a low impedance current input port with an ideal value of zero, X is a high impedance current output port (terminal) with an ideal value of infinite, and Z is a low impedance voltage output port with an ideal value of zero. The relationship between port voltages and currents is expressed as:

[ixVz]=[±β00α][iyVx](7)
where VCII+ and VCII− are identified by +β and −β, respectively (where β should be close to 1). For example, a VCII can act as a positive VCII+ and a negative VCII−. The function of the VCII is either positive or negative based on whether a current in the X terminal flows in the same direction (positive, VCII+) or in the opposite direction (negative, VCII−) with respect to that related to the Y terminal.

The voltage gain of the voltage buffer220is α (AV=α). In an example, the value of α is unity. As the Y terminal has an extremely low input impedance, the Y terminal can be considered as a virtual ground node. The main features of VCII200can be summarized as firstly, unlike other active blocks, a current summing operation can be easily performed at the current input low impedance Y port. Secondly, having a low impedance voltage output Z port allows the employment of the VCII200in a voltage mode workflow, giving the flexibility to easily perform current mode operations to the designer. Thirdly, positive and negative voltage gains are simply obtained by employing a VCII+ and a VCII−, respectively.

FIG.3is a schematic diagram illustrating an exemplary configuration of a tunable grounded negative active inductor simulator and resistance multiplier circuit300(hereinafter referred to as “the circuit300”). For example, the circuit300can be configured to implement any one of a tunable positive resistance multiplier, a tunable negative resistance multiplier, a negative active inductor simulator and a negative capacitance multiplier. Referring toFIG.3, the circuit300includes a second generation voltage-mode conveyor circuit (VCII+)310, a voltage source Vs, a first impedance Z1, a second impedance Z2, and an operational transconductance amplifier (OTA)320. The construction of circuit300is substantially similar to that of the circuit100, and thus the construction is not repeated here in detail for the sake of brevity.

With reference toFIG.3, the input impedance Zinis given by:

Zin=Z11-Z2⁢gm.(8)
I. Implementation as a Positive Resistance Multiplier

From Equation 8, if Z2gm<1, then Z1will be scaled up and if Z1=R1(the resistance to be scaled up), Z2=R2, then the input impedance is given by:

Zin=R1(1-20×R2⁢IB).(9)

In an aspect, a value of the 20×R2IBlies between 0 and 1.

II. Implementation as a Negative Resistance Multiplier

From Equation 8, if Z2gm>1, then a negative tunable resistance multiplier is obtained. If Z1=R1(the resistance to be scaled up), Z2=R2, then the input impedance is given by:

Zin=R1(-20×R2⁢IB).(10)
III. Implementation as a Negative Active Inductor Simulator

If

Z1=R1⁢and,Z2=1sC2,Z2⁢gm>1,
then a negative active inductor is obtained and is given by:

Zin=-sC2⁢R120×IB.(11)
IV. Implementation as the Negative Capacitance Multiplier

If

Z1=1sC1,and⁢Z2=R2,Z2⁢gm>1,
then the input impedance is given by:

Zin=-1sC1(20×R2⁢IB).(12)

The following examples are provided to illustrate further and to facilitate the understanding of the present disclosure.

Experimental Data and Analysis

First Experiment: Determining the functionality of the tunable grounded positive and negative active inductor simulator and impedance multiplier circuit100.

To confirm the functionality of the circuit100, the active inductor simulator (AIS) and the capacitor multiplier were used in the design of a high pass filter (HPF) and a low pass filter (LPF) respectively. The resistance multiplier was also used in the designing of the HPF.

Experiments were performed using a multisim professional tool (developed by National Instruments, located at NI. 11500 N Mopac Expwy, Austin, TX 78759-3504, USA). The multisim tool is an industry standard SPICE simulation and circuit design software for analog, digital, and power electronics in education and research. The multisim tool integrates industry standard SPICE simulation with an interactive schematic environment to instantly visualize and analyze electronic circuit behavior. The circuit100was experimentally tested by using an AD844 as the VCII+110. The AD844 is fabricated by Analog Devices, located at One Analog Way Wilmington, MA 01887, USA. In an example, an LM13700 is used as OTA120. The LM13700 is fabricated by Texas Instruments, located at 12500 TI Blvd., Dallas, Texas 75243, USA. In an example, the circuit100is powered with VCC=−VSS=5V.

FIG.4Aillustrates a circuit diagram of the HPF410using the AIS. An RL circuit acts as the HPF410as shown inFIG.4A. In the circuit, the resistor R is a series component and the equivalent inductor Leqis a shunt component. For confirming the functionality of the AIS, the high pass filter circuits shown inFIG.4Awas simulated with R=1 kΩ and the active impedance parameters were R1=10 kΩ, and C2=1 nF.

FIG.4Billustrates a circuit diagram of a LPF420based on the capacitance multiplier. The resistor R is the series component and an equivalent capacitor Ceqis the shunt component. The resistor R is placed in series with the power source and the equivalent capacitor Ceqis placed in parallel to that same power source. An RC circuit as shown inFIG.4Bforms the LPF420because of the reactive properties of the capacitor Ceq. The equivalent capacitor Ceqoffers very high resistance or impedance to low frequency signals. Conversely, the equivalent capacitor Ceqoffers lower resistance as the frequency of the signal increases. Thus, the equivalent capacitor Ceqoffers very low impedance to a very high frequency signal. As the equivalent capacitor Ceqoffers low impedance to high-frequency signals, high frequency signals normally go through the equivalent capacitor Ceq, as the equivalent capacitor Ceqrepresents a low-impedance path. Thus, high-frequency signals pass via the capacitor path, while low-frequency signals do not take the capacitor path. Instead, the low-frequency signals are transmitted to output.

FIG.4Cillustrates a circuit diagram of a HPF430based on the resistance multiplier. Two passive elements, that is, equivalent resistor Reqand capacitor C are connected in series combination to allow the frequencies higher than the cut-off frequency of a signal. The output voltage is obtained across the equivalent resistor Reqby applying input voltage across the capacitor C.

FIG.5shows the frequency response500of the HPF410based on the AIS. During simulation, the value of resistance R was set to 1 k (2. The active inductor (AI) parameters were: R1=10 kΩ, and C2=1 nF. The OTA bias current IBwas varied from 0.2 mA to 2 mA. The inductance was varied from 0.5 mH-to-5 mH. Curve502represents the frequency response of the HPF410, when value of bias current IBwas 0.2 mA. Curve504represents the frequency response of the HPF410, when value of bias current IBwas 2 mA. Curves506and508represent the intermediate frequency response of the HPF410. It is reflected from theFIG.5, that the described AIS is working accurately.

FIG.6shows the transient response600of the HPF410based on the AIS. As known, after an external excitation is applied, the transient response is a response of a circuit that fades out with time. The transient response is followed by a steady state response, which is the behavior of the circuit for a long time. In an example, a transient analysis of the HPF410was carried out using 300 kHz input signal with 1V amplitude and the bias current IBof 1 mA. Curve602represents an input voltage supplied to the HPF410. Curve604represents an output voltage. It is reflected from theFIG.6, that the described AIS is working accurately.

FIG.7shows a frequency range700of the AIS. Curve702represents an ideal inductance frequency response of the HPF410. Curve704represents a simulated inductance frequency repose in the HPF410. The active inductor simulator was configured to work in the range of 100 Hz to 1 MHz as shown inFIG.7. The frequency range may be changed by varying the value of the capacitance used.

FIG.8is an exemplary illustration800of the frequency response of the LPF420based on the capacitance multiplier. To test the functionality of the described capacitance multiplier, the described capacitance multiplier was used in the design of an RC low pass filter420with R=1 kΩ, R1=10 kΩ and C=1 nF. The bias current IBof the OTA was varied from 0.2 mA to 2 mA. Curve802represents the frequency response of the LPF420, when value of bias current IBwas 0.2 mA. Curve804represents the frequency response of the LPF420, when value of bias current IBwas 2 mA. Curves806and808represent the intermediate frequency response of the LPF420.FIG.8illustrates that the LPF420works properly with tunable-3 dB frequency. Curves806,808, and810represent the intermediate frequency response of the LPF420.

FIG.9shows the transient response900of the LPF420based on the capacitance multiplier. In an example, a transient analysis of the LPF420was performed. Curve902represents an input voltage supplied to the LPF420. Curve904represents a bias current IB=2 mA.FIG.9illustrates that the capacitance multiplier performs accurately. Curves906,908, and910represent the intermediate frequency response of the LPF420.

FIG.10shows the frequency response1000of the HPF430based on the resistance multiplier. To test the functionality of the described resistance multiplier, the described resistance multiplier is used in the design of an RC HPF430. The HPF430has Z1=R1=100Ω, is the resistor to be scaled up and Z2=R2=100Ω and IBcan be varied such that the denominator is not zero. Curve1002represents the frequency response of HPF430, when value of bias current IBwas 0.2 mA. Curve804represents the frequency response of the HPF430, when value of bias current IBwas 2 μA. Curves1006,1008, and1010represent the intermediate frequency response of the HPF430.

FIG.11A-FIG.11Cillustrate the transient response of the HPF410for different bias current IB. To verify the functionality of the circuit100experimentally, the AIS of the present disclosure was used in the design of a tunable HPF with R=1 kΩ and the active impedance parameters R1=10 kΩ and C2=1 nF (measured 1.2 nF). In an aspect, the transient response for different bias currents using 15 mV signal at the −3 dB frequency are shown inFIG.11A-FIG.11C.

FIG.11Ais an exemplary illustration1100of the transient response of the HPF410when the bias current IB=0.2 mA. Curve1102represents the input voltage supplied to the HPF410. Curve1104represents the output voltage.

FIG.11Bis an exemplary illustration1110of the transient response of the HPF410for bias current IB=1 mA. Curve1112represents the input voltage and curve1114represents the output voltage.

FIG.11Cis an exemplary illustration1120of the transient response of the HPF410for bias current IB=2 mA. Curve1122represents the input voltage and curve1124represents the output voltage.

The HPF circuit410using AIS was simulated for total harmonic distortion (THD) using different bias currents (For example, IB=0.2 mA, 1 mA, and 2 mA). The observed THD was 0.484%, 0.019%, and 0.005% respectively which is within the acceptable range. The frequency response was also carried out for the bias current of 0.2 mA.FIG.12Ais an exemplary illustration of the frequency response of the HPF410for bias current IB=0.2 mA. Curve1210represents the frequency response of the HPF410with respect to gain of the HPF410.

FIG.12Bis another exemplary illustration of the frequency response of the HPF for bias current IB=0.2 mA. Curve1220represents the frequency response of the HPF410with respect to phase of the HPF410. It can be observed fromFIG.12A-FIG.12Bthat there is a small deviation, due to parasitic effects on the low frequency side.

The performance of the present circuit100is compared with the existing circuits and is summarized in Table 1. It can be observed from the comparison table that the present circuit100is efficient in comparison to all cited existing circuits.

TABLE 1Summary of performance comparisonNumber of passiveelementsNo. of# of RImpedance/active# of CSimulatedbuildingGrounded (Floating)Frequency(±AIS, ±RCircuitsblockelementsPowerTechnologyrange& ±Cused:(ABB)G(F)G(F)supplyμm(Hz)multiplier)Conventional1 VCII±0.90.18(2)11 KHz-10±AIS onlysimulatedMHzinductor withreduced seriesresistors usinga singleVCII+Conventional3 CFOANANA2(1)1(0)1 uHz-1±AIS onlysimulatedMHzinductors withreducedparasiticimpedanceeffectsConventional1 CFOA±15NA1(1)0(1)NA±AIS onlylossless andlossygroundedinductorsimulatorsConventional2CFOA±5NAactive devicebasedgroundedinductorsimulator anduniversalfilterConventional1 E-VCII±0.30.180(1)80 Hz-40±CextremelyKHzmultiplierLow poweronlytemperatureinsensitiveelectronicallytunable VCII-BasedGroundedCapacitanceMultiplier1 INIC,±0.750.130(2)1(0)100 Hz-50±AISConventional1 VNICMHzsimulatedgroundedinductorbased on twoNICs, tworesistors and agroundedcapacitorConventional1 MD±0.750.130(2)1(0)±AISInvertingVCCVoltageBuffer BasedLosslessGroundedInductorSimulatorsPresent circuit1 VCII±5NA1(1)1100 Hz-10All100and 1MHzOTA

The first embodiment is illustrated with respect toFIG.1-FIG.4C. The first embodiment describes a tunable grounded positive and negative active inductor simulator and impedance multiplier circuit100. The circuit100includes a second generation voltage-mode conveyor circuit (VCII+)110, a voltage source Vs, a first impedance Z1, a second impedance Z2, and an operational transconductance amplifier OTA120. The second generation voltage-mode conveyor circuit (VCII+)110is configured with a positive VCII+ input terminal Y, a first output terminal Z, and a second output terminal X. The VCII+110has a current gain β, and a voltage gain α. The voltage source Vsis configured to generate an output current Is,| at a frequency s. The first impedance Z1is connected between the voltage source and the positive VCII+ input terminal Y, wherein an internal circuit of the first impedance Z1, includes a resistor R1, in parallel with a capacitor, C1. The second impedance Z2is connected between the second output terminal X, and a ground terminal, wherein an internal circuit of the second impedance Z2, includes a resistor R2, in parallel with a capacitor C2. The OTA120is configured to have a transconductance gain gm, wherein the OTA includes a positive OTA input terminal125, a negative OTA input terminal130, an OTA output terminal135, and a current bias IB, input terminal. The positive OTA input terminal125is connected to one of the first output terminal Z and the ground terminal. The negative OTA input terminal130is connected to one of the first output terminal Z and the ground terminal. The OTA output terminal135is connected to the first impedance Z1. The grounded positive and negative active inductor simulator and impedance multiplier circuit is configured to be tunable by a selection of a value for R1, a value for C1, a value for R2and a value for C2.

In an aspect, the OTA120is configured to generate an output current Io. The positive VCII+ input terminal Y is configured to receive an input current Iy, equal to the difference between Isand I0. The first output terminal Z is configured to generate a voltage, Vz. The second output terminal X is configured to generate a voltage Vx, across the second impedance Z2, and a current ix, through the second impedance Z2, wherein ix=±βIyand Vz=αVx. The output current Iois given by Io=IxZ2gm=−IyZ2gm, and a voltage at the positive VCII+ input terminal Y, is given by Vy, where Vy=0.

In an aspect, the positive OTA input terminal125is connected to the first output terminal Z. The negative OTA input terminal130is connected to the ground terminal, such that an input impedance Zin, of the VCII+ is given by

Zin=Z11+Z2⁢gm,where⁢Z2⁢gm⁢is≤1.

In an aspect, a tunable positive active inductor simulator is configured by setting Z1=R1, C1=0, R2=0 and Z2=1/sC2, such that the input impedance is given by

Zin=sC2⁢R120×IB=sL
where

L=C2⁢R120×IB,
and a value of the inductor, L, is tuned by the selection of the value of C2and the value of R1.

In an aspect, a tunable positive capacitance multiplier is configured by setting Z1=1/sC1, R1=0, Z2=R2, and C2=0, such that the input impedance is given by

Zin=1sC1(1+20×R2⁢IB),
in which the capacitance, C1, is multiplied by (1+20×R2IB), and an amount of multiplication of C1is tuned by the selection of the value of R2.

In an aspect, a tunable positive resistance multiplier is configured by setting Z1=R1, C1=0, Z2=R2, C2=0, such that the input impedance is given by

Zin=R1(1-20×R2⁢IB),
in which R1is multiplied by

1(1-20×R2⁢IB),
where 0≤20×R2IB<1, and an amount of multiplication of R1is tuned by the selection of the value of R2.

In an aspect, the positive OTA input terminal125is connected to the ground terminal, the negative OTA input terminal130is connected to the first output terminal Z, and an input impedance Zin, of the VCII+ is given by

Zin=Z11+Z2⁢gm,where⁢Z2⁢gm>1.

In an aspect, a tunable negative active inductor simulator is configured by setting Z1=R1, C1=0, R2=0 and Z2=1/sC2, such that the input impedance is given by

Zin=-sC2⁢R120×IB=-sL⁢where⁢L=C2⁢R120×IB,
and a value of the inductor, L, is tuned by the selection of the value of C2and the value of R1.

In an aspect, a tunable negative active capacitance multiplier is configured by setting Z1=1/sC1, R1=0, Z2=R2, and C2=0, such that the input impedance is given by

Zin=-1sC1(1+20×R2⁢IB),
in which the capacitance C1is multiplied by (20×R2IB), and an amount of multiplication of C1is tuned by the selection of the value of R2.

In an aspect, a tunable negative resistance multiplier is configured by setting Z1=R1, C1=0, Z2=R2, C2=0, such that the input impedance is given by

Zin=-R1(1-20×R2⁢IB),
in which R1is multiplied by

-1(1-20×R2⁢IB),
where 0≤20×R2IB<1, and an amount of multiplication of R1is tuned by the selection of the value of R2.

The second embodiment is illustrated with respect toFIG.1-FIG.4C. The second embodiment describes a method for implementing a tunable grounded positive and negative active inductor simulator and impedance multiplier circuit100. The method includes selecting one second generation voltage-mode conveyor circuit VCII+110, configured with a positive VCII+ input terminal Y, a first output terminal Z, and a second output terminal X, wherein the VCII+ has a current gain, β; and a voltage gain, α. The method includes connecting a first impedance Z1, to the positive VCII+ input terminal Y, wherein an internal circuit of the first impedance Z1, includes a resistor R1, in parallel with a capacitor C1. The method includes connecting a voltage source Vsto the first impedance Z1, wherein the voltage source Vsis configured to generate an output current Isat a frequency s. The method further includes connecting a second impedance Z2between the second output terminal X, and a ground terminal. The method further includes selecting one operational transconductance amplifier OTA120configured to have a transconductance gain gm, wherein the OTA120includes a positive OTA input terminal125, a negative OTA input terminal130, and an OTA output terminal135. The method further includes connecting the positive OTA input terminal125to one of the first output terminal Z, and the ground terminal, connecting the negative OTA input terminal130to one of the first output terminal Z, and the ground terminal, connecting the OTA output terminal135to the first impedance Z1, such that: the OTA is configured to generate an output current Io, the positive VCII+ input terminal is configured to receive an input current Iy, equal to the difference between Isand I0. The first output terminal Z is configured to generate a voltage Vz. The second output terminal X is configured to generate a voltage Vx, across the second impedance Z2, and a current ix, through the second impedance Z2, wherein ix=±βIyand Vz=αVx. The output current Iois given by Io=IxZ2gm=−IyZ2gm, and a voltage at the positive VCII+ input terminal Y is given by Vy, where Vy=0.

The method further includes connecting the positive OTA input terminal125to the first output terminal Z, and connecting the negative OTA input terminal130to the ground terminal, such that an input impedance, Zin, of the VCII+ is given by

Zin=Z11+Z2⁢gm,where⁢Z2⁢gm⁢is≤1.

The method further includes configuring a tunable positive active inductor simulator by setting Z1=R1, C1=0, R2=0 and Z2=1/sC2, such that the input impedance is given by

Zin=sC2⁢R120×IB=sL⁢where⁢L=C2⁢R120×IB,
and tuning a value of the inductor, L, by selecting the value of C2and the value of R1.

The method further includes configuring a tunable positive capacitance multiplier by setting Z1=1/sC1, R1=0, Z2=R2, and C2=0, such that the input impedance is given by

Zin=1sC1(1+20×R2⁢IB),
in which the capacitance, C1, is multiplied by (1+20×R2IB), and tuning an amount of multiplication of C1by selecting the value of R2.

The method further includes configuring a tunable positive resistance multiplier by setting Z1=R1, C1=0, Z2=R2, C2=0, such that the input impedance is given

Zin=R1(1+20×R2⁢IB),
in which R1is multiplied by

1(1-20×R2⁢IB),
where 0≤20×R2IB<1, and tuning an amount of multiplication of R1by selecting the value of R2.

The method further includes connecting the positive OTA input terminal125is connected to the ground terminal, connecting the negative OTA input terminal130is connected to the first output terminal, Z, such that an input impedance, Zin, of the VCII+ is given by

Zin=Z11+Z2⁢gm,where⁢Z2⁢gm>1.

The method further includes a tunable negative active inductor simulator is configured by setting Z1=R1, C1=0, R2=0 and Z2=1/sC2, such that the input impedance is given by

Zin=-sC2⁢R120×IB=-sL⁢where⁢L=C2⁢R120×IB,
and a value of the inductor, L, is tuned by the selection of the value of C2and the value of R1.

The method further includes a tunable negative active capacitance multiplier is configured by setting Z1=1/sC1, R1=0, Z2=R2, and C2=0, such that the input impedance is given by

Zin=-1sC1(1+20×R2⁢IB),
in which the capacitance, C1, is multiplied by (20× R2IB), and an amount of multiplication of C1is tuned by the selection of the value of R2.

The method further includes a tunable negative resistance multiplier is configured by setting Z1=R1, C1=0, Z2=R2, C2=0, such that the input impedance is given by

Zin=-R1(1-20×R2⁢IB),
in which R1is multiplied by

-1(1-20×R2⁢IB),
where 0≤20×R2IB<1, and an amount of multiplication of R1is tuned by the selection of the value of R2.

The third embodiment is illustrated with respect toFIG.1-FIG.4C. The third embodiment describes a system for configuring a tunable grounded positive and negative active inductor simulator and impedance multiplier circuit100. The system includes one second generation voltage-mode conveyor circuit (VCII+)110, configured with a positive VCII+ input terminal Y, a first output terminal Z, and a second output terminal X, wherein the VCII+ has a current gain β; and a voltage gain α, a voltage source Vs, configured to generate an output current Is, at a frequency s, a first impedance Z1, connected between the voltage source and the positive VCII+ input terminal Y, wherein an internal circuit of the first impedance Z1, comprises a resistor R1, in parallel with a capacitor C1, a second impedance Z2, connected between the second output terminal X, and a ground terminal, wherein an internal circuit of the second impedance Z2, comprises a resistor R2, in parallel with a capacitor C2, and an operational transconductance amplifier OTA120, configured to have a transconductance gain gm, wherein the OTA120includes a positive OTA input terminal125, a negative OTA input terminal130, an OTA output terminal135, and a current bias IB, input terminal, wherein: the positive OTA input terminal is connected to one of the first output terminal Z and the ground terminal, the negative OTA input terminal is connected to one of the first output terminal, Z and the ground terminal, and the OTA output terminal is connected to the first impedance Z1, wherein the grounded positive and negative active inductor simulator and impedance multiplier circuit is configured to be tunable by a selection of a value for R1, a value for C1, a value for R2and a value for C2. The OTA is configured to generate an output current, Io. The positive VCII+ input terminal is configured to receive an input current Iy, equal to the difference between Isand I0. The first output terminal Z is configured to generate a voltage Vz. The second output terminal X is configured to generate a voltage Vx, across the second impedance Z2, and a current ix, through the second impedance, Z2, wherein ix=±βIyand Vz=αVx. The output current Iois given by Io=IxZ2gm=−IyZ2gm, and a voltage at the positive VCII+ input terminal Y, is given by Vy, where Vy=0. The positive OTA input terminal is connected to the first output terminal Z and the negative OTA input terminal is connected to the ground terminal, an input impedance Zin, of the VCII+ is given by

Zin=Z11+Z2⁢gm,
where Z2gmis ≤1. The system is configured to implement any one of: a tunable positive active inductor simulator by setting Z1=R1, C1=0, R2=0 and Z2=1/sC2, such that the input impedance is given by

Zin=sC2⁢R120×IB=-sL⁢where⁢L=C2⁢R120×IB,
and a value of the inductor, L, is tuned by the selection of the value of C2and the value of R1, a tunable positive capacitance multiplier by setting Z1=1/sC1, R1=0, Z2=R2, and C2=0, such that the input impedance is given by

Zin=1sC1(1+20×R2⁢IB),
in which the capacitance, C1, is multiplied by (1+20×R2IB), wherein an amount of multiplication of C1is tuned by the selection of the value of R2, and a tunable positive resistance multiplier by setting Z1=R1, C1=0, Z2=R2, C2=0, such that the input impedance is given by

Zin=R1(1-20×R2⁢IB),
in which R1is multiplied by

1(1-20×R2⁢IB),
where 0≤20×R2IB<1, wherein an amount of multiplication of R1is tuned by the selection of the value of R2; and when the positive OTA input terminal is connected to the ground terminal, the negative OTA input terminal is connected to the first output terminal, Z, such that an input impedance, Zin, of the VCII+ is given by

Zin=Z11+Z2⁢gm,where⁢Z2⁢gm>1,
the system is configured to implement any one of: a tunable negative active inductor simulator by setting Z1=R1, C1=0, R2=0 and Z2=1/sC2, such that the input impedance is given by

Zin=-sC2⁢R120×IB=-sL⁢where⁢L=C2⁢R120×IB,
wherein a value of the inductor, L, is tuned by the selection of the value of C2and the value of R1, a tunable negative active capacitance multiplier by setting Z1=1/sC1, R1=0, Z2=R2, and C2=0, such that the input impedance is given by

Zi⁢n=-1s⁢C1(1+2⁢0×R2⁢IB),
in which the capacitance, C1, is multiplied by (20×R2IB), wherein an amount of multiplication of C1is tuned by the selection of the value of R2, and a tunable negative resistance multiplier by setting Z1=R1, C1=0, Z2=R2, C2=0, such that the input impedance is given by

Zi⁢n=-R1(1-2⁢0×R2⁢IB),
in which R1is multiplied by

-1(1-2⁢0×R2⁢IB),
where 0≤20×R2IB<1, wherein an amount of multiplication of R1is tuned by the selection of the value of R2.

Obviously, numerous modifications and variations of the present disclosure are possible in light of the above teachings. It is therefore to be understood that within the scope of the appended claims, the disclosure may be practiced otherwise than as specifically described herein.