Patent ID: 12218675

DETAILED DESCRIPTION

For simplicity and illustrative purposes, the present invention is described by referring mainly to an exemplary embodiment thereof. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, it will be readily apparent to one of ordinary skill in the art that the present invention may be practiced without limitation to these specific details. In this description, well known methods and structures have not been described in detail so as not to unnecessarily obscure the present invention.

FIG.1depicts a hybrid PLL, comprising both analog components, shown in solid line, and digital components, indicated by dashed lines. The analog PLL operates conventionally. The digital circuits are activated for calibration and characterization.

In normal operation, a voltage controlled oscillator (VCO) generates a high-frequency periodic output signal. A frequency divider (DIV) divides the output signal by an integer value. A delta-sigma modulator (ΔΣ) enables division by fractional values by controlling the instantaneous integer value of the DIV. The divided VCO output signal is compared to an accurate reference signal in the phase frequency detector (PFD). The PFD generates charge-up (CU) or charge-down (CD) current demand pulses, depending on the direction of phase error. The length of these pulses indicates the charge required from the charge pump (CP). The CP generates a corresponding current, and injects it into (or sinks it from) a capacitor in the loop filter (LF). The LF converts the charge on the capacitor into a control voltage, which controls the frequency of the VCO output signal.

A time to digital converter (TDC) measures the duration of CU and/or CD current demand pulses. The digital control circuit reads the TDC, and accumulates the sum TDCSUMof the pulses during a commanded frequency step. The sum TDCSUMis proportional to an integral of current, and corresponds to the charge injected into the loop filter by the charge pump. More specifically, the charge injected into the loop filter is proportional to TDCSUMmultiplied by the charge pump current ICP. To achieve the step in control voltage corresponding to the commanded frequency step, this charge is also proportional to the loop filter capacitance, and inversely proportional to the VCO frequency tuning sensitivity KVCO. TDCSUMcan thus be written as

TDCSUM∼cKVCO·ICP(1)

A digital calibration circuit (CAL) calibrates the RC time constant of the PLL loop filter to a predetermined value, based on an accurate reference frequency (REF). With a calibrated loop filter RC constant, the loop filter pole and zero are close to their nominal values. This facilitates estimation of the charge pump current adjustment ratio for achieving the nominal transfer function. The cumulative sum TDCSUMshould be made as close as possible to its nominal value, which means that
KVCO·ICP˜C(2)

For example, if TDCSUMis 20% lower than the nominal value, the charge pump current ICPshould be reduced by 20%, and vice versa.

In nominal conditions the bandwidth of the PLL is proportional to the VCO tuning sensitivity, the charge pump current, and the loop filter resistance
BW˜KVCO·ICP·R(3)

Combining equations (2) and (3), the bandwidth of the PLL then becomes proportional to the RC product of the loop filter, which was previously calibrated by the digital circuit CAL. The transfer function of the PLL will thus be close to nominal, with both bandwidth and loop filter pole and zero calibrated. By comparing the measured integrated TDCSUMto the nominal value, the actual charge pump current ICPis adjusted, achieving the desired BW independently of variations in the VCO tuning sensitivity KVCO. This process is referred to herein as characterizing the PLL.

By characterizing the PLL in this manner, high phase/frequency modulation accuracy is obtained. The PLL output signal can be modulated using the delta-sigma modulator A controlling the variable modulus frequency divider DIV in the feedback path. Due to the accurately known transfer function, accurate digital pre-emphasis can also be applied, even if a desired modulation bandwidth exceeds that of the PLL.

Embodiments of the present invention thus enjoy benefits of both analog and digital PLLs. The digital circuitry (Control, TDC, CAL) is only activated during frequency acquisition and calibration/characterization, and will thus be insignificant to average power consumption. The loop filter RC calibration is performed at start-up, and then occasional re-calibrations may be needed due to temperature drift. Characterization to set the BW may be needed after frequency changes, and if the temperature drifts.

Loop Filter Calibration

As discussed above, the Digital Control circuit activates the loop filter calibration circuit CAL at PLL power-on, or when the temperature has changed significantly. The calibration process adjusts the value of the loop filter resistor and/or capacitors, to set the RC product of the loop filter to a predetermined value. This ensures that the loop filter pole and zero occur close to their targeted frequencies. After calibration, a digital value is stored in flip-flops connected to the loop filter, which maintains the calibrated resistor or capacitor value, and thus the predetermined RC product. The Digital Control block then deactivates the CAL circuit.

A suitable CAL circuit is shown inFIG.2. An inverter, created by stacked NMOS and PMOS transistors, inverts an accurate frequency clock signal and applies it to a variable capacitor. The effective resistance of the clocked (switched) capacitor is then compared to a known resistance R1, by comparing voltages Vp and Vm at the inputs to a comparator. In response to this comparison, a digital control word (ctrl) adjusts the value of the variable capacitor, such as a switched capacitor bank, until its effective resistance at the reference frequency matches that of R1. The digital control word (ctrl) is then stored in flip-flops, and applied to an identical capacitor bank in the loop filter, yielding a known capacitance and hence RC product. Those of skill in the art will readily recognize that a variable resistor could instead be adjusted in the same manner, and a corresponding variable resistor in the loop filter set to the calibrated value. In either case, the calibration circuit CAL is deactivated after the calibration process, so it does not dissipate power or impact performance of the PLL. Only the flip-flops holding the digital control word (ctrl) remain powered, but they do not switch, and hence are insignificant to power consumption.

The circuit inFIG.2was simulated for R=9 kΩ, and initial C=1 pF. A 7-bit binary capacitor bank was used to adjust the total capacitance at the inverter output node, with the maximum added capacitance of around 4.5 pF in the nominal case (no capacitance variation). Therefore, the digital control word (ctrl) controlling the capacitor bank has the same length, namely 7-bit (ctrl<6:0> inFIGS.3and4). A ±30% variation was assumed for the resistance, and ±20% variation for the capacitance. Simulation results are shown inFIGS.3and4, for the four cases presenting the largest variation, namely (Cvar, Rvar)=[(−20%, −30%); (−20%, +30%); (+20%, −30%); (+20%, +30%)], which are denoted for simplicity Case1, Case2, Case3, and Case4, respectively. In addition, R1=1 kΩ, C1=25 pF, and fref=40 MHz. The supply voltage VDD is set to 1 V, resulting in Vm≈500 mV, and the window comparator thresholds were set at ±5 mV with respect to Vm when a rising clock edge is seen at the input of the inverter. The results inFIG.3show that when convergence is achieved, the digital control word ctrl settles to a fixed value, the maximum amplitude of the inverter output signal vcp is stable, the positive input of the comparator Vp settles within the ±5 mV thresholds at the rising clock edge of fref, and the negative input of the comparator Vm remains fixed at ˜500 mV. In addition,FIG.4shows greater detail of the loop filter calibrated signals, after the circuit has settled (i.e., at the right side ofFIG.3).

When assuming ±30% variation for the resistance, and ±20% variation for the capacitance, the resulting calibrated RC product variation is ˜±5% using the inventive calibration process, as shown inFIG.5A. In contrast,FIG.5Bdepicts the RC product variation of ˜±50% without calibration. Comparison ofFIGS.5A and5Bshow that the inventive calibration reduces the RC product variation by a factor of approximately ten. Those of skill in the art will recognize that the RC product variation can be further improved (i.e., lower than ±5%) with additional circuit optimization.

PLL Bandwidth Characterization

After the loop filter RC product has been calibrated, the Digital Control circuit configures the PLL for BW characterization. The BW characterization may also be repeated when the commanded PLL output center frequency or the temperature has changed significantly since last BW characterization. The TDC is activated to monitor the CU/CD current demand pulses output by the PFD. The BW characterization process proceeds by performing a PLL output frequency step, by changing the Frequency Control Word, and monitoring the TDC outputs. The frequency step could be taken in coordination with a frequency change that caused the need for BW characterization. For example, the frequency could be changed to a frequency at a suitable distance from the final target. Then a frequency step is taken to the final frequency while measuring the TDC outputs. The step size should not be too small, so as not to lose accuracy due to TDC quantization. However, it should not be too large, as the BW characterization result will then be less valid at the final frequency, due to the frequency dependency of VCO tuning sensitivity. Those of skill in the art may readily ascertain an appropriate frequency step for a given PLL configuration, given the teachings of the present disclosure. In any event, high accuracy is achieved over a wide range of frequency step sizes. If a temperature change necessitates a BW characterization, a suitable time for the characterization must first be found when the PLL output is not actively used. Two frequency steps are then taken, first one for the measurement, and then one back to the original output frequency, or vice versa.

First, a frequency step is taken by commanding a new digital frequency control word to the PLL. The resulting CU or CD current demand pulses are measured by the TDC, and the result is integrated by cumulative summation. This integral over the step response is proportional to the total loop filter capacitance, divided by the gain of the VCO (KVCO) and the charge pump current (ICP), as shown in equation (1).

The PLL ofFIG.1was simulated in a Cadence environment with the following initial parameters: for the LF filter depicted inFIG.6, Rp=32 kΩ, Cp=50 pF, C2=5 pF, and ICP=25 μA. The gain of the VCO (KVCO) was varied between 120 MHz/V and 280 MHz/V, with a step size of 20 MHz/V. For each case, the cumulative sum TDCSUMwas calculated based on the simulated outputs of the TDC, which measure the quantized length of CU or CD current demand pulses. A 6-bit TDC resolution was used for all simulations. The results are plotted inFIG.7and underline the nearly linear dependency of the integral (cumulative sum) with respect to Ct/Kv, where Ctis the total filter capacitance, and Kv=KVCO*ICP.

Second, an estimate is made of a ratio by which the charge pump current must be changed to achieve the targeted bandwidth. As equation (3) states, the bandwidth of the PLL is proportional to the VCO gain, charge pump current, and loop filter resistor, when the bandwidth is correct so that the loop filter is resistive at the cut-off frequency. The PLL bandwidth (BW) is obtained as the −3 dB bandwidth in a Bode magnitude plot of the PLL closed-loop function

Gcl=ICP·KVCON·C2·s+1τ1s3+1τ2·s2+ICP·KVCON·C2·(s+1τ1)(4)
where τ1=Rp*Cp, τ2=τ1*(Cp/C2+1), and N is the integer frequency division number.

FIG.8plots the PLL bandwidth against the R*Kvproduct (Kv=KVCO*ICP) for a ±40% KVCOvariation.

The PLL bandwidth is proportional to the loop filter RC product divided by the measured integral TDCSUM. This relationship is plotted inFIG.9. Up to a certain bandwidth, in this case about 700 kHz, there is a linear dependency between the bandwidth and R*Ct/Integral, which is independent of the KVCOvariation. However, the results deviate for larger bandwidths, when the PLL bandwidth is outside the range for which the loop filter is designed. In this case, the loop filter is no longer mainly resistive at the cut-off frequency. However, this will not affect the end result of the BW characterization, since as long as the PLL is stable during the BW characterization, the loop filter will be resistive at the cut-off frequency after the characterization, and the result will be unaffected.

FIG.10shows that for large fractional frequency steps, the PLL bandwidth as function of the R*Ct/Integral product is almost the same (less than 1.5% variation at 600 kHz PLL bandwidth), up to a certain PLL bandwidth (where the loop filter is no longer mainly resistive at the cut-off frequency).FIG.10shows the PLL bandwidth with respect to R*Ct/Integral product for two different frequency step sizes, step1=32 and step2=43. The unit frequency step is equivalent to fu=N*fref/2Nfw, where Nfwis the resolution (number of bits) used in the frequency control word to set the fractional division number. For all simulation, a 6-bit resolution was used to set the fractional division number. In this case, a maximum fractional step value of 64 corresponds to an integer step of size one. The R*Ct/Integral product is multiplied by a factor alfa which is introduced in order to normalize the step value, namely alfa=step/stepmax (stepmax is set to 64 in this case and corresponds to the fractional frequency resolution). Note that for the same TDC resolution, the smaller the frequency steps, the larger the errors due to the TDC quantization, but with larger step size the BW characterization becomes more uncertain in frequency.

Since the loop filter RC product has already been tuned to the correct value, the value of the integral (cumulative sum) corresponding to the desired bandwidth is used to calculate a ratio between the desired value of the integral and the measured integral TDCSUM. By adjusting the charge pump current ICPaccording to this ratio, the correct bandwidth is maintained independently of KVCOvariations.

FIG.11plots the ratio of charge pump current to the ratio of KVCOvariations. In this simulation, a nominal bandwidth of 620 kHz and an RC product of 1.76 μs were used. KVCOvariations of +−40% were simulated. Using the step response simulations, the corresponding cumulative sum values were obtained (1080 in the nominal case), which depend also on the TDC resolution. Next, the ratio between the desired value of the integral and the measured cumulative sum TDCSUMis derived. This ratio is then used to adjust the charge pump current, as shown inFIG.11. This graph shows the expected inverse proportionality between KVCOand charge pump current ICP.

Finally, the charge pump current ICPis adjusted by the calculated ratio. In one embodiment, this is achieved via a programmable charge pump current, for example using switched current sources. High resolution is not necessary, and binary weighting can be used for simplicity. After setting the charge pump current, the bandwidth of the PLL is close to the targeted bandwidth.

FIG.12shows the results of the BW characterization. The solid line plots the PLL bandwidth calculated based on the transfer function. The dashed line plots the PLL bandwidth before BW characterization based on the PLL simulation in Cadence, using the System Identification Toolbox in MATLAB. The dotted line plots the PLL bandwidth after BW characterization, as simulated in Cadence with the adjusted charge pump current values. The simulated bandwidth deviation after BW characterization is less than 2% with respect to the desired PLL bandwidth, when the KVCOvariation is ±40%.

FIG.13plots the simulated VCO control voltage (vctrl) and the output of the TDC (updn_v), without correction, for a KVCOvariation of ±40%, which reveals different step responses as expected. The different time durations of the step responses correspond to different PLL bandwidths.

FIG.14plots the simulated PLL step response after BW characterization, for the same KVCOvariation range as inFIG.13. It is evident that after the charge pump current ICPis adjusted to compensate for the KVCOvariations, the output of the TDC is almost the same, regardless of KVCOvariations. This translates to almost constant PLL bandwidth and phase margin.

FIGS.15A and15Bcompare the simulated step responses with and without BW characterization. It is clear that without correction, the PLL bandwidth increases as KVCOincreases (FIG.15a), whereas after BW characterization, all step responses are almost identical (FIG.15b). This proves the utility and efficiency of the inventive PLL bandwidth characterization method. Based on the result after BW characterization, the simulated bandwidth deviation is estimated to be actually even lower than the value of 2% obtained with the System Identification Toolbox in MATLAB (FIG.12).

FIG.16is a flow diagram depicting the steps in a method100of controlling the bandwidth of a digitally augmented analog Phase Locked Loop (PLL). An analog PLL includes a Phase Frequency Detector (PFD), a Charge Pump (CP), a loop filter (LF), a Voltage Controlled Oscillator (VCO), and a frequency divider (DIV). In a digital control circuit, the loop filter is calibrated to have a predetermined RC product (block102). Also in the digital control circuit, the PLL is bandwidth characterized, based on the predetermined RC product, to yield a desired bandwidth (block104).

FIG.17is a flow diagram of a method200of digitally calibrating the loop filter in an analog PLL to have a predetermined RC product, according to one embodiment. The method200is one implementation of block102of the method100described above. A reference frequency clock signal is applied to a variable calibration switched capacitor (block202). An effective resistance of the variable calibration switched capacitor is compared to a predetermined calibration resistance, and a digital command word based on the difference is generated (block204). The capacitance of the variable calibration capacitor is adjusted by applying the digital command word (block206), until the variable calibration capacitor's effective resistance matches the predetermined resistance, within a tolerance (block208). The digital command word is then stored (block210). The digital command word is applied to one or more loop filter variable capacitances (block212) and the digital control circuit disables the digital loop filter calibration circuit for analog PLL operation. The predetermined calibration resistance is chosen such that after calibration, the loop filter RC product has a predetermined value. Those of skill in the art will readily recognize that a substantially similar method could calibrate a variable resistance against a predetermined calibration capacitance chosen to achieve the predetermined RC product.

FIG.18is a flow diagram of a method300of digitally bandwidth characterizing an analog PLL. The method300is an implementation of block104of the method100described above. An output frequency of the PLL is changed by changing a division value of the frequency divider (block302). An integrated PFD output signal resulting from the frequency change is measured by summing outputs of a Time to Digital Converter connected to charge-up and charge-down signals output by the phase frequency detector to the charge pump (block304). A target integrated PFD output signal is determined based on the predetermined RC product and desired bandwidth (block306). A ratio of determined target integrated PFD output signal to measured integrated PFD output signal is calculated (block308). The charge pump current is adjusted by the calculated ratio (block310). The bandwidth of the analog PLL is then constant, regardless of variations in the gain of the VCO. The digital control circuit then disables the TDCs.

An important application (although by no means the only important one) of high-frequency, bandwidth-accurate PLLs is in transceivers in wireless communications systems and devices. In particular, current and planned future generations of wireless communication networks operate at high frequencies (e.g., 1-100 GHz), and employ advanced communication techniques, including spatial diversity and/or spatial multiplexing; beamforming; and frequency hopping.

Spatial diversity refers to transmitting the same signal on different propagations paths (e.g., different transmit/receive antennas), which increases robustness against fading, co-channel interference, and other deleterious effects of RF signal transmission. Spatial multiplexing also uses multiple transmit and receive antennas, and refers to transmitting different portions of data on different propagation paths, using space-time coding, to increase data rates. These techniques are collectively referred to as Multiple Input, Multiple Output, or “MIMO.”

Beamforming refers to the use of antennas having increased and controllable directionality, whereby an RF transmission is narrow, and is “aimed” in a specific direction. This may be accomplished by the use of a phased-array antenna comprising a large plurality of antenna elements. The relative phases of transmit signals sent to each antenna element are controlled to create constructive or destructive interference in different directions, and hence controlling the direction in which the beam is transmitted. Similar phase manipulation of signals from antenna elements in a receive antenna can also result in beamforming the sensitivity of a phased-array antenna in receiving signals.

As the term implies, frequency hopping refers to RF transmission by rapidly changing the carrier frequency, in a predetermined or calculable manner, among one or more sets of distinct frequencies within a frequency band. Frequency hopping minimizes the effect of interference at any given frequency, such as from conventional narrowband communications, as transmission and reception occur at that frequency for only a brief duration. Conversely, a frequency hopping transmitter imposes minimal interference on the conventional narrowband system, for the same reason. Frequency hopping minimizes the probability of interference among transmitters in the same network, as they are unlikely to hop on the same pattern at the same time. The technique also improves security, as the signal cannot be intercepted without knowledge of the frequency hopping pattern.

Another important technique in wireless communications is direct modulation of phase- and/or frequency-modulated signals by a PLL. For example, the Bluetooth standard of ad hoc wireless networking benefits from this approach. An accurate and steady PLL transfer function is critical to achieve accurate modulation in such designs.

All of these advanced communications techniques require highly precise, agile, phase-accurate periodic signal generators, such as PLLs. Due to the very high frequencies, large numbers of PLLs that may be required, and strict power budgets (particularly in battery-operated devices), analog PLL designs are preferred. As described herein, augmenting the analog PLLs with digital circuits to perform loop filter calibration and PLL bandwidth characterization ensures an accurate PLL bandwidth, even as component values and VCO sensitivity vary, such as by temperature drift.

FIG.19depicts a wireless device10operative in a wireless communication network, such a 3GPP LTE or NR network; a wireless LAN, such as Wi-Fi; an ad hoc wireless network, such as Bluetooth; or the like. A wireless device10is any type device capable of communicating with a network node, access point, and/or other wireless device using radio signals. A wireless device10may therefore refer to a machine-to-machine (M2M) device, a machine-type communications (MTC) device, a Narrowband Internet of Things (NB IoT) device, etc. The wireless device10may also be a User Equipment (UE), such as a cellular telephone or “smartphone.” A wireless device10may also be referred to as a radio device, a radio communication device, a radio network device, a wireless terminal, or simply a terminal—unless the context indicates otherwise, the use of any of these terms is intended to include device-to-device UEs or devices, machine-type devices, or devices capable of machine-to-machine communication, sensors equipped with a radio network device, wireless-enabled table computers, mobile terminals, smart phones, laptop-embedded equipped (LEE), laptop-mounted equipment (LME), USB dongles, wireless customer-premises equipment (CPE), etc. In the discussion herein, the terms machine-to-machine (M2M) device, machine-type communication (MTC) device, wireless sensor, and sensor may also be used. It should be understood that these devices may be UEs, but may be configured to transmit and/or receive data without direct human interaction.

In some embodiments, the wireless device10includes a user interface (display, touchscreen, keyboard or keypad, microphone, speaker, and the like); in other embodiments, such as in many M2M, MTC, or NB IoT scenarios, the wireless device10may include only a minimal, or no, user interface. The wireless device10also includes processing circuitry12; memory14; and communication circuits16. According to embodiments of the present invention, the communication circuits16include a digitally augmented analog PLL18, as described herein. The communication circuits16connect to one or more antennas19, to effect wireless communication across an air interface to one or more radio network nodes, access points, and/or other wireless devices. As indicated by the dashed lines, the antenna(s)19may protrude externally from the wireless device10, or the antenna(s)19may be internal. In various embodiments, the wireless device10may include a sophisticated user interface, and may additionally include features such as one or more cameras, an accelerometer, satellite navigation signal receiver circuitry, a vibrating motor, and the like (not depicted inFIG.19).

FIG.20illustrates a network node20as implemented in accordance with one or more embodiments. The network node20may comprise a base station or an access point of a wireless communication network. As shown, the network node20includes processing circuitry22, memory24, and communication circuitry26. According to embodiments of the present invention, the communication circuitry26includes a digitally augmented analog PLL28, as described herein. The communication circuitry26is configured to transmit and/or receive information to and/or from one or more wireless devices10, or other network nodes. The communication circuitry26is operatively connected to one or more antennas29. As indicated by the broken connection, the antenna(s)29may be located remotely, such as on a tower or building. Although the memory14is depicted as being separate from the processing circuitry12, those of skill in the art understand that the processing circuitry12includes internal memory, such as a cache memory or register file. Those of skill in the art additionally understand that virtualization techniques allow some functions nominally executed by the processing circuitry12to actually be executed by other hardware, perhaps remotely located (e.g., in the so-called “cloud”).

In all embodiments, the processing circuitry12,22may comprise any sequential state machine operative to execute machine instructions stored as machine-readable computer programs in memory14,24, such as one or more hardware-implemented state machines (e.g., in discrete logic, FPGA, ASIC, etc.); programmable logic together with appropriate firmware; one or more stored-program, general-purpose processors, such as a microprocessor or Digital Signal Processor (DSP), or any combination of the above.

In all embodiments, the memory14,24may comprise any non-transitory machine-readable media known in the art or that may be developed, including but not limited to magnetic media (e.g., floppy disc, hard disc drive, etc.), optical media (e.g., CD-ROM, DVD-ROM, etc.), solid state media (e.g., SRAM, DRAM, DDRAM, ROM, PROM, EPROM, Flash memory, solid state disc, etc.), or the like.

In all embodiments, the communication circuits16,26may comprise one or more transceivers used to communicate with one or more other transceivers via a Radio Access Network (RAN) according to one or more communication protocols known in the art or that may be developed, such as IEEE 802.xx, CDMA, WCDMA, GSM, LTE, UTRAN, WiMax, NB-IoT, Bluetooth, or the like. The communication circuitry16,26implements transmitter and receiver functionality appropriate to the RAN links (e.g., frequency allocations and the like).

Those skilled in the art will also appreciate that embodiments described herein further include corresponding computer programs. A computer program comprises instructions which, when executed on at least one processor of an apparatus, cause the apparatus to carry out any of the respective processing described above. A computer program in this regard may comprise one or more code modules corresponding to the means or units described above.

Embodiments further include a carrier containing such a computer program. This carrier may comprise one of an electric signal, optical signal, radio signal, or computer readable storage medium.

In this regard, embodiments herein also include a computer program product stored on a non-transitory computer readable (storage or recording) medium and comprising instructions that, when executed by a processor or Digital Control circuit, cause the apparatus to perform as described above.

Embodiments of the present invention present numerous advantages over the prior art. By using a low complexity analog PLL architecture, the benefits of low design effort, high frequency, and low power consumption are retained, while the digital calibration and BW compensation circuits add the benefits of a digital PLL architecture. The loop filter calibration ensures the correct RC product, so that the pole and zero occur at the correct frequencies, regardless of component variation or temperature drift. The BW characterization ensures that the PLL operates at the design bandwidth, regardless of variations in VCO gain sensitivity (which is also temperature dependent). After the loop filter calibration and BW characterization procedures, the PLL can be used for phase/frequency modulation with high accuracy. The digital circuitry is powered down during steady-state (i.e., most of the time), thus causing negligible additional power consumption and having no influence on spectral purity; accordingly, the design of the digital circuits is not critical. The analog PLL can be designed independently of the digital circuits, using well established design methods. Also, the digital enhancements can be added to existing analog PLL designs. The TDCs and Digital Control circuitry can also be used to perform fast frequency hops, as described in PCT Patent Application No. PCT/EP2020/054601.

Generally, all terms used herein are to be interpreted according to their ordinary meaning in the relevant technical field, unless a different meaning is clearly given and/or is implied from the context in which it is used. All references to a/an/the element, apparatus, component, means, step, etc. are to be interpreted openly as referring to at least one instance of the element, apparatus, component, means, step, etc., unless explicitly stated otherwise. The steps of any methods disclosed herein do not have to be performed in the exact order disclosed, unless a step is explicitly described as following or preceding another step and/or where it is implicit that a step must follow or precede another step. Any feature of any of the embodiments disclosed herein may be applied to any other embodiment, wherever appropriate. Likewise, any advantage of any of the embodiments may apply to any other embodiments, and vice versa. Other objectives, features and advantages of the enclosed embodiments will be apparent from the description.

The term unit may have conventional meaning in the field of electronics, electrical devices and/or electronic devices and may include, for example, electrical and/or electronic circuitry, devices, modules, processors, memories, logic solid state and/or discrete devices, computer programs or instructions for carrying out respective tasks, procedures, computations, outputs, and/or displaying functions, and so on, as such as those that are described herein.

Some of the embodiments contemplated herein are described more fully with reference to the accompanying drawings. Other embodiments, however, are contained within the scope of the subject matter disclosed herein. The disclosed subject matter should not be construed as limited to only the embodiments set forth herein; rather, these embodiments are provided by way of example to convey the scope of the subject matter to those skilled in the art.

The present invention may, of course, be carried out in other ways than those specifically set forth herein without departing from essential characteristics of the invention. The present embodiments are to be considered in all respects as illustrative and not restrictive, and all changes coming within the meaning and equivalency range of the appended claims are intended to be embraced therein.