Patent ID: 12212323

It is hereby noted that in the embodiments described below, the same reference numerals are sometimes used between different drawings to denote the same parts or the parts of the same functions, and repeated description thereof is omitted. In this specification, similar reference numerals and letters are used to represent similar items. Therefore, once an item is defined in one drawing, the item does not need to be further discussed in subsequent drawings.

For ease of understanding, the position, dimensions, range, and the like of each structure shown in the drawings sometimes do not represent the actual position, dimensions, range, and the like. Therefore, the disclosed invention is not limited to the positions, dimensions, ranges, and the like disclosed in the drawings and the like.

DETAILED DESCRIPTION

Various exemplary embodiments of the present disclosure will now be described in detail with reference to the drawings. It is hereby noted that, unless otherwise specifically specified, the relative arrangement of parts and steps, numerical expressions, and numerical values set forth in these embodiments do not limit the scope of the present disclosure. In addition, the technologies, methods, and devices known to a person of ordinary skill in the related art may be described without going into details, but as appropriate, such technologies, methods, and devices are regarded as a part of the granted specification.

It should be understood that the following description of at least one exemplary embodiment is merely illustrative, and is in no way intended as a limitation on the present disclosure and the application or the use thereof. Further, it should also be understood that any implementation described exemplarily herein is not necessarily meant to be preferred or advantageous over other implementations. The present disclosure is not limited by any expressly stated or implied theory described in the preceding technical field, background, summary, or detailed description.

In this specification, “tri-state logic” means a logic circuit of which an output assumes three states: a logic-high state, a logic-low state, and a high-impedance state, depending on the input and the control signal. The control signal may be, for example, a clock signal.

In this specification, “tri-state gate” means a “minimum-level” logic gate (or referred to as a logic gate circuit) of which an output can implement the three states (logic-high state, logic-low state, and high-impedance state). The “minimum-level logic gate” herein means no independent logic gate or logic unit as a part of the logic gate (tri-state gate) can be separated therefrom.

In addition, for reference purposes only, some terms may be used in the following description without being hereby intended as a limitation. For example, unless otherwise expressly specified in the context, the terms “first”, “second”, and other such numerical terms referring to structures or elements do not imply a sequence or order.

It should also be understood that the terms “include” and “comprise” when used herein mean existence of the feature, entirety, step, operation, unit and/or component indicated, but do not preclude the existence or addition of one or more other features, entireties, steps, operations, units, and/or components, and/or combinations thereof.

Compared with a static latch, a dynamic latch removes a positive feedback circuit used to maintain the working state, and thus has a significantly simplified circuit structure, thereby not only reducing the area of the chip, but also reducing the power consumption of the chip. However, because there is a node that has a floating potential part of the time in the dynamic latch, a parasitic capacitor at the node needs to maintain a correct voltage state during such period of time.

FIG.9shows a circuit diagram of a dynamic latch according to the related art.FIG.10shows a schematic equivalent circuit diagram used for illustrating operations of the dynamic latch in the related art. The dynamic latch includes a transmission gate101and an inverter102that are connected in series between an input terminal D and an output terminal QN. A node A is formed between the transmission gate101and the inverter102, and data is temporarily stored on the node A and/or the node QN through a parasitic capacitor of the inverter102. However, the node A and the node QN generates dynamic current leakage, resulting in loss of the temporarily stored data.

Referring toFIG.9andFIG.10, when CLKP is at a low level and CLKN is at a high level (denoted as CKP and CKN respectively inFIG.9), the transmission gate101is turned on to transmit data to the node A, so that the data is written into the parasitic capacitor100of the node A. When CLKP becomes a high level and CLKN becomes a low level, the transmission gate101is turned off, and the data transmitted by the transmission gate is held in the parasitic capacitor100of the node A. When the data stored at the node A is “0” and the data at the input terminal D is “1”, a pull-up leakage path (left part inFIG.10) is formed through the transmission gate101to charge the parasitic capacitor100. When the clock frequency is relatively low, that is, when a time period in which CKP=1 and CLKN=0 is long enough, the voltage of the node A will change from “0” to “1”, resulting in data loss. When the data stored at the node A is “1” and the data at the input terminal D is “0”, a pull-down leakage path (right part inFIG.10) is formed through the transmission gate101to discharge the parasitic capacitor100. When the clock frequency is relatively low, that is, when a time period in which CKP=1 and CLKN=0 is long enough, the voltage of the node A will change from “1” to “0”, resulting in data loss.

Assuming that an amount of charges stored on the parasitic capacitor100is Q, a capacitance value of the parasitic capacitor100is C, and a voltage across electrode plates of the parasitic capacitor is V, then Q=C×V.

If a leakage current is Ileakage, a leakage time T is T=Q/Ileakage=C×V/Ileakage, the leakage time is proportional to a clock cycle, then
clock frequencyFclk∝1/T=Ileakage/(C×V).

Therefore, dynamic current leakage limits a minimum working frequency of an existing dynamic latch.

On the other hand, in order to reduce or avoid the impact caused by device current leakage to the voltage of the node, a circuit device connected to the node needs to be a low-current-leakage device. The low-current-leakage device is usually a high-threshold device, and is of a lower speed than a low-threshold device, thereby also influencing the speed of the latch. In addition, the latch needs to work at a relatively high frequency to prevent malfunction. In some states (for example, sleep or idle state) of a processor, the latch may work at a relatively low frequency, in which case the latch in the related art may incur malfunction.

To solve one or more of the problems described above, the present disclosure provides a semi-static latch, a processor including the latch, and a computing apparatus.

In contrast to the dynamic latch, the semi-static latch according to the present disclosure has a feedback stage added therein, and thus can work at a relatively low working frequency without being limited by the minimum frequency. In addition, the speed of the latch may be increased by using some low-threshold devices.

The latch according to embodiments of the present disclosure can stably maintain the potential of the floating node, and reduce power consumption of the latch. The latch according to embodiments of the present disclosure can work both at a relatively low frequency and at a relatively high frequency, thereby providing flexibility for design of a processor and reducing power consumption.

The processor and computing apparatus according to the present disclosure are applicable to related calculations of digital currency (for example, Bitcoin, Litecoin, Ethereum, and other digital currencies).

FIG.1shows a schematic block diagram of a semi-static latch according to some embodiments of the present disclosure. As shown inFIG.1, a latch100according to an embodiment of the present disclosure includes an input stage101configured to receive an input (IN), and an output stage105configured to output a latch output (OUT).

The latch100also has an intermediate node (A) disposed between an output of the input stage and an input of the output stage. During operation, the potential of the intermediate node A may be floating in a part of a clock cycle.

In the embodiment shown inFIG.1, the intermediate node A may be connected to the output of the input stage, and the input of the output stage105may be connected to the intermediate node A.

The latch100further includes a feedback stage107configured to receive the latch output OUT and provide a feedback to the intermediate node A. According to an embodiment of the present disclosure, the feedback stage107assumes a logic-high state, a logic-low state, and a high-impedance state.

In addition, one or more of components of the latch100may receive corresponding clock signals. As shown inFIG.1, the input stage101, an optional intermediate stage (if any), the feedback stage107, and the like each receive a corresponding clock. Here, it should be understood that the clock CKs is merely exemplary and does not mean that the input stage101, the feedback stage107, and other components (if any) all receive the same clock signal. Further, although in the embodiment shown inFIG.1, the output stage105shown does not receive the clock signal, the present disclosure is not limited to this.

FIG.2Ashows a circuit diagram of a semi-static latch according to some embodiments of the present disclosure. As shown inFIG.2A, a latch200A according to an embodiment of the present disclosure includes an input stage201, an output stage205, an intermediate node A, and a feedback stage207. The intermediate node A is disposed between an output of the input stage and an input of the output stage. During operation, the potential at the intermediate node A may be floating in a part of a frequency cycle.

The input stage201receives an input D and provides an output to the intermediate node A. Here, the input stage201receives an input D (also referred to as a latch input) and provides an output to the intermediate node A. In some embodiments, as shown inFIG.2A, the input stage201is implemented as a transmission gate. As shown inFIG.2A, CMOS (Complementary Metal Oxide Semiconductor) transistors533and537constitute the transmission gate, the input of which is connected to the latch input and the output of which is connected to the intermediate node A. Two control terminals of the transmission gate (that is, the gates of the CMOS transistors533and537) receive the clock signal CLKP and the clock signal CLKN respectively. The clock signal CLKN and the clock signal CLKP are inverted from each other, i.e., the clock signal CLKN and the clock signal CLKP are the inverse of each other. Here, the gate of the transistor533is connected to the clock signal CLKP, and the gate of the transistor537is connected to the clock signal CLKN.

The output stage205receives the signal (voltage) at the node A as an input, and the output of the output stage serves as a latch output QN. In this embodiment, the output stage is implemented as an inverter that includes CMOS transistors511and513connected with each other in series. The transistor511is a PMOS transistor, and the transistor513is an NMOS transistor. The transistor511has a control terminal (a gate) connected to the node A, a source connected to a power supply voltage VDD, and a drain connected to a drain of the transistor513and connected to the output QN. The transistor513has a gate connected to the node A, and a source connected to a low potential (for example, a ground GND). In this specification, depending on the context, “output QN” may denote an output signal or an output terminal. Similarly, “input D” may denote an input signal or an input terminal.

In this embodiment, because the input stage201is a transmission gate and the output stage205is an inverter, the output QNis inverted from the input D. Therefore, the latch200A may also be referred to as an inverting latch.

The feedback stage207receives the latch output QNas an input, and provides a feedback to the intermediate node A. Here, the feedback stage207is implemented as a tri-state logic. In the embodiment shown inFIG.2A, the feedback stage207is implemented as a tri-state gate that assumes a logic-high state, a logic-low state, and a high-impedance state.

Specifically, as shown inFIG.2A, the tri-state gate of the feedback stage207is implemented by CMOS transistors. The tri-state gate includes: transistors521to527that are sequentially connected in series. The transistors521,523,525, and527are herein referred to as first to fourth transistors respectively. The first transistor521and the second transistor523are PMOS transistors, and the third transistor525and the fourth transistor527are NMOS transistors.

The first transistor521and the second transistor523are connected with each other in series. One end (here, a drain) of the transistor521is connected to one end (here, a source) of the transistor523. A control terminal (a gate) of one of the first transistor521and the second transistor523is connected to the latch output QN, and a control terminal of the other of the first transistor521and the second transistor523is connected to the clock signal CLKN. Here, in the embodiment shown inFIG.2A, the gate of the first transistor521is connected to the latch output QN, and the gate of the second transistor523is connected to the clock signal CLKN. The other end (here, a source) of the transistor521is connected to the power supply voltage VDD.

The drain of the PMOS transistor523and the drain of the NMOS transistor525are connected to each other and connected to the intermediate node A. The third transistor525and the fourth transistor527are connected with each other in series. One end (here, a source) of the transistor525is connected to one end (here, a drain) of the transistor527. A control terminal (a gate) of one of the third transistor525and the fourth transistor527is connected to the latch output QN, and a control terminal (a gate) of the other of the third transistor525and the fourth transistor527is connected to the clock signal CLKP. The clock signal CLKN is the inverse of the clock signal CLKP. Here, in the embodiment shown inFIG.2A, the gate of the third transistor525is connected to the clock signal CLKP, and the gate of the fourth transistor527is connected to the latch output QN. The other end (here, a source) of the transistor527is connected to the ground GND.

A node at which the second transistor523and the third transistor525are connected with each other is connected to the intermediate node A. Here, the drain of the transistor523is connected to the drain of the transistor525, and connected to the intermediate node A.

it shall be understood that, although in the embodiment shown inFIG.2A, the feedback stage207is implemented as a tri-state gate, the feedback stage207may be implemented in a variety of other ways in other embodiments.

The timing of the latch according to an embodiment of the present disclosure will be described below with reference toFIG.7andFIG.2A.FIG.7shows a timing diagram of a schematic signal waveform of a latch according to an embodiment of the present disclosure. The clock signals CLKN and CLKP may be obtained from a clock signal CK in a manner shown inFIG.5, for example (to be detailed later). Without considering delay, the clock signal CLKP and the clock signal CLKN are inverted from each other, one of which may be basically identical to the clock signal CK. For example, here, the clock signal CLKP is basically identical to the clock signal CK, and the clock signal CLKN is the inverse of the clock signal CLKP (or the clock signal CK).

In contrast to the dynamic latch, the embodiment of the present disclosure adds a feedback stage207(here, implemented as a tri-state gate) used for feedback control. When the clock CK is at a low level, the transmission gate201is turned on, the tri-state gate207is turned off, and the input signal D is transmitted to the output QN. When the clock becomes a high level, the transmission gate201is turned off, and the tri-state gate207is turned on, so as to latch the signal at the node A and prevent current leakage from changing the signal level of the node. In this way, the latch according to the embodiments of the present disclosure is not limited by the minimum working frequency.

The following gives a detailed description with reference toFIG.7.FIG.7shows five complete clock cycles T1to T5, a part of a clock cycle preceding T1, and a part of a clock cycle T6., in which vertical dotted lines show how the clock cycles T1to T6correspond to time t1to t12.

As shown inFIG.7, at the time t1, the clock signal CK changes from logic high to logic low. Accordingly, the clock signal CLKP changes from high to low, and the clock signal CLKN changes from low to high. In a time period from the time t1to the time t2, the input D is high, the clock signal CLKP is low, CLKN is high, the transmission gate201is turned on, and the node A is high. In this way, the output (that is, the output QN) of the inverter205is low.

In the time period from the time t1to the time t2, the output QNis low, the clock signal CLKP is low, and the clock signal CLKN is high. Therefore, the transistors525and523are cut off, and the tri-state gate207is in a high-impedance state, so that the node A is maintained at a high potential by the input D.

At the time t2in the first cycle T1of the clock CK, the clock signal CK toggles to high, the clock signal CLKP toggles to high, and the clock signal CLKN toggles to low. Therefore, in a time period from the time t2to the time t3, the transmission gate201is turned off. Moreover, because the clock signals CLKP and CLKN are high and low respectively, the transistor523and the transistor525in the tri-state gate207are turned on. At this time, the output QNis low, thereby holding (latching) the signal high at the node A.

Subsequently, in a time period from the time t3to the time t4, D is held high, so the circumstance is similar to that of the time period from t1to t2, and the output QNis held low. The node A is held high.

Before the time t5, the input signal D changes from high to low. However, in a time period from the time t4to the time t5, similar to the time period from the time t2to the time t3, the signal at the node A is latched (held at the high potential) so that the output QNis held low without changing with the change of the input D.

At the time t5, the clock signal CK changes from logic high to logic low again; accordingly, the clock signal CLKP changes from high to low, and the clock signal CLKN changes from low to high. At this time, the input D is low. Therefore, in a time period from the time t5to the time t6, the input D is low, CLKP is low, and the clock signal CLKN is high. Therefore, the transmission gate201is turned on; the input D is low, and therefore, the node A is low. In this way, the output (that is, the output QN) of the inverter205is high.

In the time period from the time t5to the time t6, the clock signal CLKP is low, the clock signal CLKN is high, and the output QNis high. Therefore, the transistors523and525in the feedback stage207are turned off, and the node A is held low by the input D.

Subsequently, at the time t6, the clock signal CK toggles to high, the clock signal CLKP toggles to high, and the CLKN toggles to low. Therefore, in a time period from the time t6to the time t7, the transmission gate201is turned off. Moreover, because the clock signals CLKP and CLKN are high and low respectively and the output QNis high, the transistor525and the transistor523in the tri-state gate207are turned on, such that the tri-state gate207is turned on and the signal at the node A is held (latched) low. Therefore, the output QNis held high.

Subsequently, at the time t7, the clock signal CK changes from logic high to logic low again; accordingly, the clock signal CLKP changes from high to low, and the clock signal CLKN changes from low to high. At this time, the input D is still low. Therefore, the circumstance of a time period from the time t7to the time t8is similar to the circumstance of the time period from the time t5to the time t6, details of which are omitted here.

Before the time t9, the input D changes from low to high. Because the feedback stage207is turned on and the signal at the node A is held low, the output QNis held high. The output QNdoes not change with the change of the input D.

The circumstance from the time t9to the time t12is similar to the circumstance from the time t1to the time t4, details of which are omitted here.

According to embodiments of the present disclosure, a stage of feedback (the feedback stage207) is added, thereby providing a semi-static latch. The semi-static latch according to the embodiments of the present disclosure can stably maintain the potential of the floating node (such as the node A), and reduce power consumption of the semi-static latch. The semi-static latch according to the embodiments of the present disclosure is not limited by the minimum working frequency of the dynamic latch, and the working speed of the latch may be configured to be between a working speed of a dynamic latch and a working speed of a static latch, thereby eliminating the limitation of the minimum working frequency and achieving an optimized trade-off between speed and power consumption.

In addition, in the semi-static latch according to the embodiments of the present disclosure, because the potential of the floating node can be maintained, the use of high-threshold devices (such as high-threshold transistors) is avoided. In this way, transistors in the semi-static latch can be configured to have basically identical thresholds. Here, person skilled in the art would understand that, although the transistor devices in the semi-static latch are designed to have basically identical thresholds, variations in the manufacturing process may lead to some deviations of the thresholds of the devices that are practically manufactured. Generally, in this specification, thresholds are regarded as basically identical when the variations between the thresholds fall within ±20%, or ±15%, or ±10%, or ±5% of the designed or target threshold, for example.

However, the present disclosure is not limited to this. In some embodiments, in order to shorten a clock-to-output delay, the input stage201may use a low-threshold device to increase the speed of the latch, and the feedback stage207may use a high-threshold device to reduce the power consumption and the current leakage.

In addition, the number of transistors used in the semi-static latch according to the embodiments of the present disclosure is minimized. In a calculation-intensive processor (for example, a processor for digital currency), a large number of latches may exist. Therefore, even reduction of one transistor in the latch is still meaningful to reduction of the area and power consumption of the chip.

In addition, the semi-static latch according to the embodiments of the present disclosure can effectively maintain the potential of the floating node, so malfunction is avoided even when the latch works at a relatively low frequency. The semi-static latch according to the embodiments of the present disclosure can also work at a relatively high frequency, thereby providing flexibility for design of a processor and reducing power consumption.

It should also be understood that, although the above examples are described by using embodiments where a high level is active, other embodiments of the present disclosure can also be implemented in a manner where a low level is active. In this case, waveforms of the clock signals CLKN and CLKP will be inverted.

FIG.2Bshows a circuit diagram of a latch according to some embodiments of the present disclosure. The latch200B in the embodiment shown inFIG.2Bdiffers from the latch200A shown inFIG.2Aonly in the clock signal provided to the latch. In the latch200A shown inFIG.2A, when the clock CK is low (at this time, the clock signal CLKP is low and the clock signal CLKN is high), the transmission gate of the input stage is turned on to transmit the signal, while the feedback stage is turned off; when the clock CK is high (at this time, the clock signal CLKP is high and the clock signal CLKN is low), the feedback stage is active, thereby latching the signal at the node A. The case is opposite for the latch200B shown inFIG.2B.

As shown inFIG.2B, in the latch200B: in the input stage201, the gate of the transistor533is connected to the clock signal CLKN, and the gate of the transistor537is connected to the clock signal CLKP; in the feedback stage, the gate of the transistor523is connected to the clock signal CLKP, and the gate of the transistor525is connected to the clock signal CLKN.

FIG.8shows a timing diagram of a schematic signal waveform for use in the latch200B. As shown inFIG.8, in the latch200B, when the clock CK is high (at this time, the clock signal CLKP is high and the clock signal CLKN is low), the transmission gate of the input stage is turned on to transmit the signal, while the feedback stage is turned off; when the clock CK is low (at this time, the clock signal CLKP is low and the clock signal CLKN is high), the feedback stage is active, thereby latching the signal at the node A.

Other components or configurations of the latch200B shown inFIG.2Bare the same as those of the latch200A shown inFIG.2A, and the description made above with reference toFIG.2Ais equally or adaptively applicable to the latch200B, details of which are thus omitted here.

FIG.3Ashows a schematic circuit diagram of a semi-static latch according to some other embodiments of the present disclosure. The semi-static latch300A shown inFIG.3Adiffers from the latch200A shown inFIG.2Aonly in the feedback stage. The feedback stage307in the semi-static latch300A differs from the feedback stage207inFIG.2Ain the transistors that receive the clock signals CLKN and CLKP and the latch output QN.

In the embodiment shown inFIG.3A, the gate of the first transistor521is connected to the clock signal CLKN, and the gate of the second transistor523is connected to the latch output QN. The gate of the third transistor525is connected to the latch output QN, and the gate of the fourth transistor527is connected to the clock signal CLKP.

It's apparent for a person of ordinary skill in the art that the operations and logic level changes described above with respect toFIG.2Aare equally or adaptively applicable here. In addition, remaining components inFIG.3Aare identical to the corresponding components inFIG.2A, further details of which are thus omitted here. It is hereby noted that, in contrast to the embodiment shown inFIG.3A, the connection manner of the clock signals in the feedback mode shown inFIG.2Acan achieve a higher working speed.

FIG.3Bshows a schematic circuit diagram of a semi-static latch according to some other embodiments of the present disclosure. The semi-static latch300B shown inFIG.3Bdiffers from the semi-static latch300A shown inFIG.3Aand the latch200A shown inFIG.2Aonly in the feedback stage. In the semi-static latch300B, the tri-state logic of the feedback stage307is implemented as an inverter and a transmission gate connected in series.

As shown inFIG.3B, the CMOS transistors521and527constitute an inverter, and CMOS transistors523and525constitute a transmission gate. The input of the inverter is connected to the latch output node (QN), and the output of the inverter is connected to the input (node F) of the transmission gate. The output of the transmission gate is connected to the intermediate node (node A). Two control terminals of the transmission gate (that is, gates of the CMOS transistors523and525) receive the clock signal CLKN and the clock signal CLKP respectively.

In the latch300B, when the clock CK is low (at this time, the clock signal CLKP is low and the clock signal CLKN is high), the transmission gate of the input stage is turned on to transmit the signal, and the feedback stage is turned off; when the clock CK is high (at this time, the clock signal CLKP is high and the clock signal CLKN is low), the transmission gate of the input stage is turned off, and the feedback stage is active, thereby latching the signal at the node A.

In the embodiment shown inFIG.3B, the node F may be used as an output to output the inverse Q of the latch output QN.

FIG.3Cshows a schematic circuit diagram of a semi-static latch according to some other embodiments of the present disclosure. The semi-static latch300C shown inFIG.3Cdiffers from the semi-static latch300A shown inFIG.3Aonly in the clock signal provided to the latch. In the latch300C shown inFIG.3C, when the clock CK is high (at this time, the clock signal CLKP is high and the clock signal CLKN is low), the transmission gate of the input stage is turned on to transmit the signal, and the feedback stage is turned off; when the clock CK is low (at this time, the clock signal CLKP is low and the clock signal CLKN is high), the feedback stage is active, thereby latching the signal at the node A. Other components or configurations of the latch300C shown inFIG.3Care the same as those of the latch300A shown inFIG.3A, and the description made above with reference toFIG.2A,FIG.2B, andFIG.3Ais equally or adaptively applicable to the latch300C, details of which are thus omitted here.

FIG.3Dshows a schematic circuit diagram of a semi-static latch according to some other embodiments of the present disclosure. The semi-static latch300D shown inFIG.3Ddiffers from the semi-static latch300B shown inFIG.3Bonly in the clock signal provided to the latch. In the latch300D shown inFIG.3D, when the clock CK is low (at this time, the clock signal CLKP is low and the clock signal CLKN is high), the transmission gate of the input stage is turned off and the feedback stage is active, so as to latch the signal at the node A; when the clock CK is high (at this time, the clock signal CLKP is high and the clock signal CLKN is low), the transmission gate of the input stage is turned on to transmit the signal, and the feedback stage is turned off. Other components or configurations of the latch300D shown inFIG.3Dare the same as those of the latch300B shown inFIG.3B, and the description made above with reference toFIG.2A,FIG.2B,FIG.3A, andFIG.3Bis equally or adaptively applicable to the latch300D, details of which are thus omitted here.

According to the present disclosure, a processor is further provided.FIG.4shows a schematic block diagram of a processor that includes a clock circuit and a semi-static latch according to some embodiments of the present disclosure. As shown inFIG.4, a processor400includes at least one semi-static latch401. The semi-static latch may be the semi-static latch according to any one of the embodiments of the present disclosure. The processor400may further include a clock circuit403configured to provide a desired clock signal to each semi-static latch. As shown inFIG.4, the clock circuit403receives a clock signal CK (which may be a system clock signal, or a clock signal received from outside), and outputs different clock signals CLKN and CLKP. As mentioned above, in some embodiments, the clock signals CLKN and CLKP are opposite in phase.

FIG.5shows a schematic block diagram of a clock circuit according to some embodiments of the present disclosure. The clock circuit500includes a first inverter551and a second inverter553connected in series. The first inverter551receives a clock signal (for example, a system clock) CK and outputs a first clock signal (for example, the clock signal CLKN or CLKP). The second inverter receives the first clock signal and outputs a second clock signal (for example, the clock signal CLKP or CLKN). In this way, the first clock signal and the second clock signal are inverted from each other. The first clock signal and the second clock signal may be provided to one or more of the plurality of semi-static latches.

FIG.6shows a schematic block diagram of a processor that includes a clock circuit and a plurality of semi-static latches according to some embodiments of the present disclosure. As shown inFIG.6, a processor600includes a plurality of semi-static latches601and a clock circuit602that provides a clock signal to the plurality of semi-static latches601. The clock circuit602receives a clock CK and outputs clock signals CLKN and CLKP to each of the semi-static latchs601. The clock circuit602may be, for example, the clock circuit shown inFIG.4.

According to the present disclosure, a computing apparatus is further provided, which may include the processor according to any one of the embodiments of the present disclosure. In some embodiments, the computing apparatus may be a computing apparatus for digital currency. The digital currency may be, for example, digital RMB, Bitcoin, Ethereum, Litecoin, or the like.

A person skilled in the art should appreciate that the boundaries between the operations (or steps) described in the above embodiments are merely illustrative. A plurality of operations may be combined into a single operation, and a single operation may be distributed among additional operations, and the operations may be performed in time periods that at least partly overlap. Moreover, alternative embodiments may include a plurality of instances of particular operations, and the order of operations may be changed in other various embodiments. However, other modifications, changes, and substitutions are also possible. Therefore, this specification and the drawings appended hereto are intended as illustrative rather than restrictive.

Although the present disclosure has been described in detail with regard to some specific embodiments by using examples, a person skilled in the art shall understand that the examples are merely intended to be illustrative rather than restrict the scope of the present disclosure. The embodiments disclosed herein may be combined arbitrarily without departing from the spirit and scope of the present disclosure. A person skilled in the art shall also understand that various modifications may be made to the embodiments without departing from the spirit and scope of the present disclosure. The scope of the present disclosure is defined by the claims appended hereto.