Patent ID: 12199157

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “over,” “on,” “top,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

FIGS.1-12Zillustrate various stages of manufacturing a semiconductor device structure100in accordance with various embodiments of this disclosure. It is understood that additional operations can be provided before, during, and after processes shown byFIGS.1-12Zand some of the operations described below can be replaced or eliminated, for additional embodiments of the method. The order of the operations/processes may be interchangeable.

FIGS.1-4are perspective views of the semiconductor device structure100, in accordance with some embodiments. InFIG.1, a first semiconductor layer104is formed on a substrate102. The substrate may be a part of a chip in a wafer. In some embodiments, the substrate102is a bulk semiconductor substrate, such as a semiconductor wafer. For example, the substrate102is a silicon wafer. The substrate102may include silicon or another elementary semiconductor material such as germanium. In some other embodiments, the substrate102includes a compound semiconductor. The compound semiconductor may include gallium arsenide, silicon carbide, indium arsenide, indium phosphide, another suitable semiconductor material, or a combination thereof. In some embodiments, the substrate102is a semiconductor-on-insulator (SOI) substrate. The SOI substrate may be fabricated using a separation by implantation of oxygen (SIMOX) process, a wafer bonding process, another applicable method, or a combination thereof.

The substrate102may be doped with P-type or N-type impurities. As shown inFIG.1, the substrate102has a P-type metal-oxide-semiconductor region102P (PMOS region102P) and an N-type metal-oxide-semiconductor region102N (NMOS region102N) adjacent to the PMOS region102P, in accordance with some embodiments. While not shown in scale in some figures, the PMOS region102P and NMOS region102N belong to a continuous substrate102. In some embodiments of the present disclosure, the PMOS region102P is used to form a PMOS structure thereon, whereas the NMOS region102N is used to form an NMOS structure thereon. In some embodiments, an N-well region103N and a P-well region103P are formed in the substrate102, as shown inFIG.1. For example, the N-well region103N is formed in the substrate102in the PMOS region102P, whereas the P-well region103P is formed in the substrate102in the NMOS region102N. The P-well region103P and the N-well region103N may be formed by any suitable technique, for example, by separate ion implantation processes in some embodiments. By using two different implantation mask layers (not shown), the P-well region103P and the N-well region103N can be sequentially formed in different ion implantation processes.

The first semiconductor layer104is deposited over the substrate102, as shown inFIG.1. The first semiconductor layer104may be made of any suitable semiconductor material, such as silicon, germanium, III-V semiconductor material, or combinations thereof. In some embodiments, the first semiconductor layer104is substantially made of silicon. The first semiconductor layer104may be formed by an epitaxial growth process, such as metal-organic chemical vapor deposition (MOCVD), metal-organic vapor phase epitaxy (MOVPE), plasma-enhanced chemical vapor deposition (PECVD), remote plasma chemical vapor deposition (RP-CVD), molecular beam epitaxy (MBE), hydride vapor phase epitaxy (HVPE), liquid phase epitaxy (LPE), chloride vapor phase epitaxy (CI-VPE), or any other suitable process.

InFIG.2, the portion of the first semiconductor layer104disposed over the N-well region103N is removed, and a second semiconductor layer106is formed over the N-well region103N and adjacent the portion of the first semiconductor layer104disposed over the P-well region103P. A patterned mask layer (not shown) may be first formed on the portion of the first semiconductor layer104disposed over the P-well region103P, and the portion of the first semiconductor layer104disposed over the N-well region103N may be exposed. A removal process, such as a dry etch, wet etch, or a combination thereof, may be performed to remove the portion of the first semiconductor layer104disposed over the N-well region103N, and the N-well region103N may be exposed. The removal process does not substantially affect the mask layer (not shown) formed on the portion of the first semiconductor layer104disposed over the P-well region103P, which protects the portion of the first semiconductor layer104disposed over the P-well region103P. Next, the second semiconductor layer106is formed on the exposed N-well region103N. The second semiconductor layer106may be made of any suitable semiconductor material, such as silicon, germanium, III-V semiconductor material, or combinations thereof. In some embodiments, the second semiconductor layer106is substantially made of silicon germanium. The second semiconductor layer106may be formed by the same process as the first semiconductor layer104. For example, the second semiconductor layer106may be formed on the exposed N-well region103N by an epitaxial growth process, which does not form the second semiconductor layer106on the mask layer (not shown) disposed on the first semiconductor layer104. As a result, the first semiconductor layer104is disposed over the P-well region103P in the NMOS region102N, and the second semiconductor layer106is disposed over the N-well region103N in the PMOS region102P.

Portions of the first semiconductor layer104may serve as channels in the subsequently formed NMOS structure in the NMOS region102N. Portions of the second semiconductor layer106may serve as channels in the subsequently formed PMOS structure in the PMOS region102P. In some embodiments, the NMOS structure and the PMOS structure are FinFETs. While embodiments described in this disclosure are described in the context of FinFETs, implementations of some aspects of the present disclosure may be used in other processes and/or in other devices, such as planar FETs, nanostructure FETs, Horizontal Gate All Around (HGAA) FETs, Vertical Gate All Around (VGAA) FETs, and other suitable devices.

InFIG.3, a plurality of fins108a,108b,110a,110bare formed from the first and second semiconductor layers104,106. The fins108a,108b,110a,110bmay be patterned by any suitable method. For example, the fins108a,108b,110a,110bmay be patterned using one or more photolithography processes, including double-patterning or multi-patterning processes. Generally, double-patterning or multi-patterning processes combine photolithography and self-aligned processes, allowing patterns to be created that have, for example, pitches smaller than what is otherwise obtainable using a single, direct photolithography process. For example, in one embodiment, a sacrificial layer (not shown) is formed over a substrate and patterned using a photolithography process. Spacers (not shown) are formed alongside the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers may then be used to pattern the substrate and form the fins.

The fins108a,108bmay each include the first semiconductor layer104, and a portion of the first semiconductor layer104may serve as an NMOS channel. Each fin108a,108bmay also include the P-well region103P. Likewise, the fins110a,110bmay each include the second semiconductor layer106, and a portion of the second semiconductor layer106may serve as a PMOS channel. Each fin110a,110bmay also include the N-well region103N. A mask (not shown) may be formed on the first and second semiconductor layers104,106, and may remain on the fins108a-band110a-b.

Next, an insulating structure112is formed between adjacent fins108a-b,110a-b. The insulating structure112may be first formed between adjacent fins108a-b,110a-band over the fins108a-b,110a-b, so the fins108a-b,110a-bare embedded in the insulating structure112. The insulating structure112may include an oxygen-containing material, such as silicon oxide, carbon or nitrogen doped oxide, or fluorine-doped silicate glass (FSG); a nitrogen-containing material, such as silicon nitride, silicon oxynitride (SiON), SiOCN, SiCN; a low-K dielectric material (e.g., a material having a K value lower than that of silicon dioxide); or any suitable dielectric material. The insulating structure112may be formed by any suitable method, such as low-pressure chemical vapor deposition (LPCVD), plasma enhanced CVD (PECVD) or flowable CVD (FCVD).

Next, a planarization process, such as a chemical-mechanical polishing (CMP) process may be performed to expose the top of the fins108a-b,110a-b. In some embodiments, the planarization process exposes the top of the mask (not shown) disposed on the fins108a-band110a-b. The insulating structure112is then recessed by removing portions of the insulating structure112located on both sides of each fin108a-b,110a-b. The recessed insulating structure112may be shallow trench isolation (STI) region.

The insulating structure112may be recessed by any suitable removal process, such as dry etch or wet etch that selectively removes portions of the insulating structure112but does not substantially affect the semiconductor materials of the fins108a-b,110a-b.

InFIG.4, one or more sacrificial gate stacks128are formed on a portion of the fins108a-b,110a-b. Each sacrificial gate stack128may include a sacrificial gate dielectric layer130, a sacrificial gate electrode layer132, and a mask structure134. The sacrificial gate dielectric layer130may include one or more layers of dielectric material, such as SiO2, SiN, a high-K dielectric material, and/or other suitable dielectric material. In some embodiments, the sacrificial gate dielectric layer130may be deposited by a CVD process, a sub-atmospheric CVD (SACVD) process, a FCVD process, an ALD process, a PVD process, or other suitable process. The sacrificial gate electrode layer132may include polycrystalline silicon (polysilicon). The mask structure134may include an oxygen-containing layer and a nitrogen-containing layer. In some embodiments, the sacrificial gate electrode layer132and the mask structure134are formed by various processes such as layer deposition, for example, CVD (including both LPCVD and PECVD), PVD, ALD, thermal oxidation, e-beam evaporation, or other suitable deposition techniques, or combinations thereof.

The sacrificial gate stacks128may be formed by first depositing blanket layers of the sacrificial gate dielectric layer130, the sacrificial gate electrode layer132, and the mask structure134, followed by pattern and etch processes. For example, the pattern process includes a lithography process (e.g., photolithography or e-beam lithography) which may further include photoresist coating (e.g., spin-on coating), soft baking, mask aligning, exposure, post-exposure baking, photoresist developing, rinsing, drying (e.g., spin-drying and/or hard baking), other suitable lithography techniques, and/or combinations thereof. In some embodiments, the etch process may include dry etch (e.g., RIE), wet etch, other etch methods, and/or combinations thereof. By patterning the sacrificial gate stacks128, the fins108a-b,110a-bare partially exposed on opposite sides of the sacrificial gate stacks128. Portions of the insulating structure112are exposed as a result of the etch process(s) to form the sacrificial gate stacks128. While three sacrificial gate stacks128are shown inFIG.4, it can be appreciated that they are for illustrative purpose only and any number of the sacrificial gate stacks128may be formed.

FIGS.5A-10Aare cross-sectional side views of various stages of manufacturing the semiconductor device structure100ofFIG.4taken along line A-A, in accordance with some embodiments.FIGS.5B-10Bare cross-sectional side views of various stages of manufacturing the semiconductor device structure100ofFIG.4taken along line B-B, in accordance with some embodiments.FIGS.5C-10Care cross-sectional side views of various stages of manufacturing the semiconductor device structure100ofFIG.4taken along line C-C, in accordance with some embodiments.

FIGS.5A-5Cillustrate a stage after the sacrificial gate stacks128are formed on a portion of the fins108a-b,110a-b. InFIGS.6A-6C, a spacer140is formed on the sacrificial gate stacks128and the exposed portions of the first and second semiconductor layers104,106. The spacer140may be conformally deposited on the exposed surfaces of the semiconductor device structure100. The conformal spacer140may be formed by ALD or any suitable processes. The term “conformal” may be used herein for ease of description upon a layer having substantial same thickness over various regions. An anisotropic etch is then performed on the spacer140using, for example, RIE. During the anisotropic etch process, most of the spacer140is removed from horizontal surfaces, such as tops of the sacrificial gate stacks128and tops of the fins108a-b,110a-b, leaving the spacer140on the vertical surfaces, such as on opposite sidewalls of the sacrificial gate stacks128. The spacers140may partially remain on opposite sidewalls of the fins108a-b,110a-b, as shown inFIG.6A. In some embodiments, the spacers140formed on the source/drain regions of the fins108a-b,110a-bare fully removed.

The spacer140may be made of a dielectric material such as silicon oxide (SiO2), silicon nitride (Si3N4), silicon carbide (SiC), silicon oxynitride (SiON), silicon carbon-nitride (SiCN), silicon oxycarbide (SiOC), silicon oxycarbonitride (SiOCN), air gap, and/or any combinations thereof. In some embodiments, the spacer140include one or more layers of the dielectric material discussed above.

In various embodiments where the spacer140includes multiple layers, the top portion of the fins108a-b,110a-bnot covered by the sacrificial gate stacks128may have a taper profile149, as shown inFIGS.6B,6C. The taper profile149may be formed as a result of multiple exposure of the first and second semiconductor layers104,106to etchants used during formation of the spacer140. The taper profile149between adjacent sacrificial gate stacks128forms a shallow V-shaped top surface in the first and second semiconductor layers104,106, respectively.

InFIGS.7A-7C, the first and second semiconductor layers104,106of the fins108a-b,110a-bnot covered by the sacrificial gate stacks128and the spacers140are recessed, and source/drain (S/D) epitaxial features152,154are formed. The etchant for recessing of the first and second semiconductor layers104,106is selected so different materials have different etch rates. For example, the first semiconductor layer104of the fins108a-bmay have a first etch rate by the etchant, and the second semiconductor layer106of the fins110a-bmay have a second etch rate by the etchant. In the embodiments where the first semiconductor layer104in the NMOS region102N and the second semiconductor layer106in the PMOS region102P each includes different materials (e.g., first semiconductor layer104in the NMOS region102N is SiGe and second semiconductor layer106in the PMOS region102P is Si), the first etch rate is faster than the second etch rate. A portion of the P-well region103P of the fins108a-bcan be slightly etched before the second semiconductor layer106in the PMOS region102P is fully etched away. As a result, a top surface109of the fins108a-bat the NMOS region102N is at a level below (e.g., about 2 nm to about 10 nm below) a top surface111of the fins110a-bat the PMOS region102P, resulting in a deeper S/D junction depth in the NMOS region102N than that of the PMOS region102P. While not shown, it is contemplated that such a difference between the top surface109and the top surface111is applicable to various embodiments of this disclosure.

For devices in the NMOS region102N, each S/D epitaxial features152may include one or more layers of Si, SiP, SiC, SiCP, SiAs, or a group III-V material (InP, GaAs, AlAs, InAs, InAlAs, InGaAs). In some embodiments, each S/D epitaxial feature152includes two or more layers of Si, SiP, SiC, SiCP or the group III-V material, and each layer may have a different silicon concentration. Each S/D epitaxial feature152may include N-type dopants, such as phosphorus (P), arsenic (As), or other suitable N-type dopants. The S/D epitaxial features152may be formed by any suitable method, such as CVD, CVD epitaxy, MBE, or other suitable method. The S/D epitaxial features152may be formed on the exposed surface of the fins108a-bon both sides of each sacrificial gate stack128, as shown inFIG.7B. In some embodiments, the portions of the first semiconductor layer104on both sides of each sacrificial gate stack128are completely removed, and the S/D epitaxial features152are formed on the P-well region103P of the fins108a-b. The S/D epitaxial features152may grow both vertically and horizontally to form facets, which may correspond to crystalline planes of the material used for the substrate102. In some embodiments, the S/D epitaxial features152formed on the P-well region103P of the fins108aand108bare merged, as shown inFIG.7A. The S/D epitaxial features152may each have a top surface at a level higher than a top surface of the first semiconductor layer104, as shown inFIG.7B.

For devices in the PMOS region102P, each S/D epitaxial features154may include one or more layers of Si, SiGe, SiGeB, Ge, or a group III-V material (InSb, GaSb, InGaSb), and each layer may have a different silicon or germanium concentration. Each S/D epitaxial feature154may include P-type dopants, such as boron (B) or other suitable P-type dopants. In some embodiments, the S/D epitaxial features152in the NMOS region102N and the S/D epitaxial features154in the PMOS region102P are both Si. In some embodiments, the S/D epitaxial features152in the NMOS region102N are Si and the S/D epitaxial features154in the PMOS region102P are SiGe. The S/D epitaxial features154may be formed by any suitable method, such as CVD, CVD epitaxy, MBE, or other suitable method. In some embodiments, the portions of the second semiconductor layer106on both sides of each sacrificial gate stack128are completely removed, and the S/D epitaxial features154are formed on the N-well region103N of the fins110a-b. The S/D epitaxial features154may grow both vertically and horizontally to form facets, which may correspond to crystalline planes of the material used for the substrate102. In some embodiments, the S/D epitaxial features154formed on the N-well region103N of the fins110aand110bare merged, as shown inFIG.7A. The S/D epitaxial features154may each have a top surface at a level higher than a top surface of the second semiconductor layer106, as shown inFIG.7C.

InFIGS.8A-8C, a contact etch stop layer (CESL)160is conformally formed on the exposed surfaces of the semiconductor device structure100. The CESL160covers the sidewalls of the sacrificial gate stacks128, the insulating structure112, and the S/D epitaxial features152,154. The CESL160may include an oxygen-containing material or a nitrogen-containing material, such as silicon nitride, silicon carbon nitride, silicon oxynitride, carbon nitride, silicon oxide, silicon carbon oxide, or the like, or a combination thereof, and may be formed by CVD, PECVD, ALD, or any suitable deposition technique. Next, a first interlayer dielectric (ILD) layer162is formed on the CESL160. The materials for the ILD layer164may include compounds comprising Si. O. C. and/or H, such as SiOCH, oxide formed using tetraethylorthosilicate (TEOS), un-doped silicate glass, silicon oxide, or doped silicon oxide such as borophosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron doped silicon glass (BSG), and/or other suitable dielectric materials. The first ILD layer162may be deposited by a PECVD process or other suitable deposition technique.

After the formation of the first ILD layer162, a planarization process is performed to expose the sacrificial gate electrode layer132. The planarization process may be any suitable process, such as a CMP process. The planarization process removes portions of the first ILD layer162and the CESL160disposed on the sacrificial gate stacks128. The planarization process may also remove the mask structure134.

InFIGS.9A-9C, the mask structure134(if not removed during CMP process), the sacrificial gate electrode layers132(FIG.8B), and the sacrificial gate dielectric layers130(FIG.8B) are removed. The sacrificial gate electrode layers132and the sacrificial gate dielectric layers130may be removed by one or more etch processes, such as dry etch process, wet etch process, or a combination thereof. The one or more etch processes selectively remove the sacrificial gate electrode layers132and the sacrificial gate dielectric layers130without substantially affects the spacer140, the CESL160, and the first ILD layer162. The removal of the sacrificial gate electrode layers132and the sacrificial gate dielectric layers130exposes a top portion of the first and second semiconductor layers104,106in the channel region.

InFIGS.10A-10C, replacement gate structures177are formed. The replacement gate structure177may include a gate dielectric layer166and a gate electrode layer168p,168nformed on the gate dielectric layer166. As can be seen inFIGS.10B and10C, the gate dielectric layer166is formed on the first and second semiconductor layers104,106. The gate dielectric layer166may include one or more dielectric layers and may include the same material(s) as the sacrificial gate dielectric layer130. In some embodiments, the gate dielectric layers166may be deposited by one or more ALD processes or other suitable processes. The gate electrode layer168p,186nmay include one or more layers of electrically conductive material, such as polysilicon, aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, tantalum nitride, nickel silicide, cobalt silicide, TiN, WN, AlTi, AlTiO, AlTiC, AlTiN, TaCN, TaC, TaSiN, metal alloys, other suitable materials, and/or combinations thereof. For devices in the NMOS region102N, the gate electrode layer168nmay be AlTiO. AlTiC, or a combination thereof. For devices in the PMOS region102P, the gate electrode layer168pmay be AlTiO, AlTiC, AlTiN, or a combination thereof. The gate electrode layers168may be formed by PVD, CVD, ALD, electro-plating, or other suitable method.

A metal gate etching back (MGEB) process is performed to remove portions of the spacer140, the gate dielectric layer166, and the gate electrode layer168p,168n. The MGEB process may be a plasma etching process employing one or more etchants such as chlorine-containing gas, a bromine-containing gas, and/or a fluorine-containing gas. After the MGEB process, a top surface of the gate electrode layer168p,168nmay be lower than a top surface of the gate dielectric layer166. In some embodiments, as shown inFIGS.10B and10C, the spacers140and the gate dielectric layer166are at the same level after the MGEB process. In some embodiments, portions of the spacers140are etched back so that the top surface of the spacers140is higher than the top surfaces of the gate dielectric layer166and the gate electrode layers168p,168n. A cap layer169is selectively formed on the gate electrode layers168p,168nafter the MGEB process. The cap layer169may include an electrically conductive material, such as a metal. In some embodiments, the cap layer169includes fluorine-free tungsten (FFW).

Then, trenches formed above the spacers140, the gate dielectric layer166, and the gate electrode layer168p,168nas a result of the MGEB processes are filled with a mask layer179. The mask layer179can be formed of any material that has different etch selectivity than the CESL160and the first ILD layer162. In some embodiments, the mask layer179includes silicon, SiN, or a low-K dielectric material. The mask layer179may be formed by any suitable process. In some embodiments, the mask layer179is formed by ALD, and a scam180may be formed in the mask layer179as a result of the ALD process. The seam180may have a width ranging from about 0 nm to about 3 nm. A CMP process is then performed to remove excess deposition of the mask layer179until the top surface of the first ILD layer162is exposed.

FIG.11is a cross-sectional view of one of various stages of manufacturing a semiconductor device structure200, in accordance with some embodiments. As shown inFIG.11, the semiconductor device structure200includes a substrate202, the gate electrode layers168, the gate dielectric layers166, the spacers140, the cap layer169, the mask layer179, the CESL160, and the first ILD layer162. The substrate202includes a plurality of devices (not shown) formed thereon. In some embodiments, the plurality of devices are FinFETs. For example, the semiconductor device structure200is the semiconductor device structure100shown inFIGS.11A-11C, and the substrate202includes the first semiconductor layer104and the S/D epitaxial features152(or the second semiconductor layer106and the S/D epitaxial features154). In some embodiments, the plurality of devices of nanostructure FETs, such as nanosheet FETs. For example, the substrate202includes channel regions each includes a stack of semiconductor layers, and the gate electrode layer168surrounds each semiconductor layer. In some embodiments, other types of the devices are disposed on the substrate202.

FIGS.12A-12Zare cross-sectional views of various stages of manufacturing the semiconductor device structure200ofFIG.11, in accordance with some embodiments. As shown inFIG.12A, a second ILD layer204is formed on the first ILD layer162, the mask layer179, and the CESL160. The second ILD layer204may include the same material as the first ILD layer162and may be formed by the same process as the first ILD layer162. The second ILD layer204has a thickness T1ranging from about 50 nm to about 250 nm. The mask layer179has a thickness T2ranging from about 5 nm to about 60 nm. In some embodiments, as shown inFIG.12A, the second ILD layer204is not formed in the scam180due to the small dimensions of the seam180. In some embodiments, the second ILD layer204is formed in the seam180.

As shown inFIG.12B, a hard mask layer206is formed on the second ILD layer204. The hard mask layer206may include a material that has different etch selectivity than the second ILD layer204. In some embodiments, the hard mask layer206includes silicon or SiN. The hard mask layer206has a thickness T3ranging from about 5 nm to about 20 nm. As shown inFIG.12C, the hard mask layer206is patterned. As a result, one or more openings208are formed in the hard mask layer206. The openings208may be formed by any suitable process, such as a dry etch process, a wet etch process, or a combination thereof. The opening208has a width W1ranging from about 0.3 microns to about 2 microns. The opening208may be disposed over one or more portions of the first ILD layer162. In some embodiments, as shown inFIG.12B, the opening208is formed over a portion of the first ILD layer162disposed between two adjacent mask layers179. In some embodiments, the opening208is formed over multiple portions of the first ILD layer162disposed between multiple adjacent mask layers179. The opening208exposes a portion of the second ILD layer204.

As shown inFIG.12D, the opening208is enlarged by removing the exposed portion of the second ILD layer204and the portion of the first ILD layer162. In some embodiments, the first and second ILD layers162,204include the same material. As a result, the portions of the first and second ILD layers162,204are selectively removed by a removal process. The removal process may be any suitable process, such as a dry etch process, a wet etch process, or a combination thereof. The removal process does not substantially affect the mask layers179and the CESL160. As a result of the removal process, a portion of each of the adjacent mask layers179is exposed, and a portion of the CESL160disposed between the adjacent mask layers179is exposed. In some embodiments, the seam180formed in the mask layer179is also exposed. The opening208may include a bottom portion210and an upper portion212. The bottom portion210may be a trench having a depth D1and a width W2. In some embodiments, the depth D1ranges from about 20 nm to about 80 nm, and the width W2ranges from about 10 nm to about 50 nm.

As shown inFIG.12E, the exposed portion of the CESL160is removed by any suitable process. In some embodiments, the exposed portion of the CESL160is removed by a selective etching process that does not substantially affect the mask layer179, the spacers140, and the S/D epitaxial features152(FIG.10B) or the S/D epitaxial features154(FIG.10C). As shown inFIG.12F, a liner214is formed in the opening208. In some embodiments, the liner214includes a material having a lower K value than the CESL160. For example, the liner214may include SiC, SiCO, SiCON, SiON, or a low-K dielectric material, which has a lower K value compared to the SiN of the CESL160. The material of the liner214also has different etch selectivity compared to the material of the mask layer179. In some embodiments, the liner214is a conformal layer formed by ALD. The liner214may have a thickness ranging from about 1 nm to about 10 nm. In some embodiments, as shown inFIG.12F, the liner214is not formed in the seam180due to the small dimensions of the seam180. In some embodiments, the liner214is formed in the seam180.

As shown inFIG.12G, portions of the liner214are removed. In some embodiments, an anisotropic etching process is performed to remove the portions of the liner214disposed on horizontal surfaces, while the portions of the liner214disposed on vertical surfaces are not substantially affected. For example, the remaining portions of the liner214may be disposed on the side surfaces of the mask layers179and side surfaces of the spacers140. The liner214has a lower K value compared to the CESL160. Thus, parasitic capacitance is reduced. As a result of the anisotropic etching process, the S/D epitaxial features152(FIG.10B) or the S/D epitaxial features154(FIG.10C) are exposed.

As shown inFIG.12H, a glue layer216is formed in the opening208. In some embodiments, the glue layer216includes an electrically conductive material, such as TiN or TaN. In some embodiments, the glue layer216is a conformal layer formed by ALD, and the seams180are filled with the glue layer216due to the ALD process. The glue layer216may be also formed on the hard mask layer206. The glue layer216may have a thickness ranging from about 1 nm to about 10 nm. In some embodiments, the glue layer216is optional and may not be present. As shown inFIG.12I, a conductive material218is formed in the opening208and over the hard mask layer206. The conductive material218may include an electrically conductive material, such as a metal. In some embodiments, the conductive material218includes Ru, Co, W, Cu, Mo, or other suitable metal. The conductive material218may be formed by any suitable process, such as ECP or PVD.

As shown inFIG.12J, a planarization process is performed to expose the mask layers179. The planarization process may be a CMP process. The CMP process may remove the portions of the conductive material218, the glue layer216, and the liner214disposed over the mask layers179. In addition, the hard mask layer206and the second ILD layer204are removed by the CMP process. The remaining conductive material218disposed in the bottom portion210of the opening208(FIG.12D) may have a top surface at a level below a top surface of the mask layer179due to the dishing effect. The remaining conductive material218is electrically connected to the S/D epitaxial features152(or S/D epitaxial features154) (FIGS.10B and10C), and the remaining conductive material218may be a conductive feature, such as a conductive plug or conductive contact.

As shown inFIG.12K, the mask layers179are removed. The mask layers179may be removed by any suitable process. In some embodiments, the mask layers179are removed by a selective etching process. The selective etching process does not substantially affect the CESL160, the liner214, the glue layer216, and the conductive material218. The glue layer216formed in the seam180(FIG.12G) may be also removed as a result of the removal of the mask layers179. After the removal of the mask layers179, the spacers140, the gate dielectric layers166, and the cap layers169are exposed in openings220.

As shown inFIG.12L, a hard mask layer222is formed in the openings220and on the first ILD layer162, the CESL160, the spacers140, the gate dielectric layers166, and the cap layers169. The hard mask layer222may include a porous dielectric material, such as porous SiN, SiC, SiCO, SiCON, SiCN, or a low-K dielectric material. In some embodiments, the hard mask layer222includes porous SiN. The hard mask layer222may be a non-conformal layer having different thicknesses in different areas. For example, in some embodiments, each portion of the hard mask layer222disposed on the liner214, the glue layer216, the CESL160, and the first ILD layer162has a thickness T4, each portion of the hard mask layer222disposed on the spacers140, the gate dielectric layers166, and the cap layers169has a thickness T5substantially less than the thickness T4, and each portion of the hard mask layer222disposed on the side surfaces of the CESL160has a thickness T6substantially less than the thickness T5. In some embodiments, the thickness T4ranges from about 5 nm to about 30 nm, the thickness T5ranges from about 1 nm to about 20 nm, and the thickness T6ranges from about 1 nm to about 10 nm. The hard mask layer222may be formed by a non-conformal process, such as a CVD process.

As shown inFIG.12M, a treatment process is performed on the portions of the hard mask layer222. The treatment process may be a plasma treatment process. The plasma treatment process may utilize one or more gases, such as Ar, Ge, B, As, or any suitable gas, to change the physical properties of the treated portions of the hard mask layer222. The species in the plasma may be implanted or doped into the portions of the hard mask layer222disposed on horizontal surfaces as a result of directional plasma treatment process. For example, a bia power may be applied to the substrate202, and the direction of the species223in the plasma is substantially perpendicular to the top surface of the hard mask layer222. As a result, the portions of the hard mask layer222disposed on the liner214, the glue layer216, and the conductive material218, the portions of the hard mask layer222disposed on the CESL160and the first ILD layer162, and the portions of the hard mask layer222disposed on the spacers140, the gate dielectric layers166, and the cap layers169are treated, while the portions of the hard mask layer222disposed on the side surfaces of the CESL160are not treated. After the treatment process, the hard mask layer222includes treated portions226,228and untreated portions224, as shown inFIG.12M. Each treated portion226has the thickness T4, each treated portion228has the thickness T5, and each untreated portion224has the thickness T6. The untreated portions224include a porous dielectric material, such as porous SiN, and the treated portions226,228include a dielectric material implanted with an impurity, such as Ar, Ge, B, As, or any suitable impurity. The treated portions226,228and the untreated portions224have different etch selectivity. The treated portions226,228each includes a dielectric material, such as SiN, and is doped with a dopant, such as Ar, Ge, B, or As.

As shown inFIG.12N, the untreated portions224of the hard mask layer222are selectively removed. The removal of the untreated portions224of the hard mask layer222may be performed by any suitable process. In some embodiments, a wet etching process is performed to remove the untreated portions224. The wet etching process does not substantially affect the treated portions226,228of the hard mask layer222and the CESL160. As shown inFIG.12O, a hard mask layer230is formed in the openings220(FIG.12N) and on the treated portions226of the hard mask layer222. The hard mask layer230may include a material different from the treated portions226,228of the hard mask layer222. In some embodiments, the hard mask layer230includes the same material as the first ILD layer162. The hard mask layer230includes SiCO, SiO2, SiC, SiCON, SiN, SiCN, or a low-K dielectric material. In some embodiments, the hard mask layer230includes SiCO.

As shown inFIG.12P, a planarization process is performed to expose the treated portions226of the hard mask layer222. The planarization process may be a CMP process, and the portion of the hard mask layer230disposed on the treated portions226of the hard mask layer222are removed by the CMP process. As a result of the CMP process, the top surfaces225of the treated portions226and the top surfaces229of the hard mask layers230may be substantially coplanar. As shown inFIG.12Q, an etch stop layer232is formed on the treated portions226and the hard mask layer230, and an ILD layer234is formed on the etch stop layer232. The etch stop layer232may include the same material as the CESL160, and the ILD layer234may include the same material as the first ILD layer162. In some embodiments, the ILD layer234includes the same material as the hard mask layer230. In some embodiments, the ILD layer234includes a material different from the hard mask layer230and the treated portions226, and the etch stop layer232is not present, as shown inFIG.12R.

As shown inFIG.12S, an opening236is formed in the ILD layer234and the etch stop layer232. The openings236may be formed by one or more etching processes. For example, the opening236may be formed by removing a portion of the ILD layer234to expose a portion of the etch stop layer232by a first etching process, removing the exposed portion of the etch stop layer232to expose portions of the hard mask layer230and a treated portion226of the hard mask layer222by a second etch process, and removing the exposed treated portion226by a third etch process. Because the treated portion226and the hard mask layer230include different materials having different etch selectivity, the third etch process does not substantially affect the exposed portions of the hard mask layer230. As a result, the opening236does not extend to a level close to the gate electrode layer168. In some embodiments, the opening236is formed by a dual-damascene process. For example, the opening236includes an upper portion238and a lower portion240. The upper portion238may be formed in the ILD layer234and the etch stop layer232, and the upper portion238may be a trench. The lower portion240may be formed in a portion of the treated portion226of the hard mask layer222, and the lower portion240may be a via. The opening236exposes the conductive material218, the glue layer216, and the liner214. As shown inFIG.12T, a conductive material239is formed in the opening236. The conductive material239may include the same material as the conductive material218and may be formed by the same process as the conductive material218. The conductive material239may be in contact with the conductive material218, which is electrically connected to the S/D epitaxial feature152(FIG.10B) or the S/D epitaxial features154(FIG.10C). The conductive material239provides electrical path for the S/D epitaxial feature152(FIG.10B) or the S/D epitaxial feature154(FIG.10C) to an interconnect structure (not shown) disposed over the semiconductor device structure200. Because the opening236(FIG.12S) does not extend to a level close to the gate electrode layer168, the conductive material239is not close to the gate electrode layer168. As a result, the risk of having a short circuit is substantially reduced.

In order to electrically connect the gate electrode layer168to the interconnect structure (not shown), an opening242is formed in the ILD layer234, the etch stop layer232, the hard mask layer230, and the treated portion228of the hard mask layer222to expose the cap layer169, which is in contact with the gate electrode layer168, as shown inFIG.12U. The opening242and the opening236(FIG.12S) may be offset along the Y-axis. The openings242may be formed by one or more etching processes. For example, the opening242may be formed by removing a portion of the ILD layer234to expose a portion of the etch stop layer232by a first etching process, removing the exposed portion of the etch stop layer232to expose a portion of the hard mask layer230and the treated portions226of the hard mask layer222by a second etch process, removing the exposed portion of the hard mask layer230to expose a treated portion228of the hard mask layer222by a third etch process, and removing the exposed treated portion228of the hard mask layer222to expose the cap layer169by a fourth etch process. Because the treated portion226and the hard mask layer230include different materials having different etch selectivity, the third etch process does not substantially affect the exposed treated portions226of the hard mask layer222. Furthermore, because the treated portion226is substantially thicker than the treated portion228, the fourth etch process removes a small portion of the treated portions226in addition to removing the treated portion228. As a result, the opening242does not extend to a level close to the conductive material218. In some embodiments, the opening242is formed by a dual-damascene process. For example, the opening242includes an upper portion244and a lower portion246. The upper portion244may be formed in the ILD layer234and the etch stop layer232, and the upper portion244may be a trench. The lower portion246may be formed in the hard mask layer230and the treated portion228of the hard mask layer222, and the lower portion246may be a via. The opening242exposes the cap layer169. As shown inFIG.12V, a conductive material248is formed in the opening242. The conductive material248may include the same material as the conductive material218and may be formed by the same process as the conductive material218. The conductive material248may be in contact with the cap layer169, which is in contact with the gate electrode layer168. The conductive material248may be a gate contact. The conductive material248provides electrical path for the gate electrode layer168to the interconnect structure (not shown) disposed over the semiconductor device structure200. Because the opening242(FIG.12U) does not extend to a level close to the conductive material218, the conductive material248is not close to the conductive material248. As a result, the risk of having a short circuit is substantially reduced.

In some embodiments, the opening236exposes a plurality of portions of the conductive material218, as shown inFIG.12W. The upper portion238formed in the ILD layer234and the etch stop layer232exposes a plurality of treated portions226of the hard mask layer222, and then portions of the exposed plurality of treated portions226are removed to form the plurality of lower portions240to expose the plurality of portions of the conductive material218. As shown inFIG.12X, the conductive material239is in contact with the plurality of portions of the conductive material218. As a result, multiple S/D epitaxial features152(FIG.10B) or the S/D epitaxial features154(FIG.10C) are electrically connected to the conductive material239. The conductive material239may be a rail type conductive feature.

Similarly, in some embodiments, the opening242exposes a plurality the cap layers169, as shown inFIG.12Y. The upper portion244formed in the ILD layer234and the etch stop layer232exposes a plurality of portions of the hard mask layer230, and then portions of the exposed plurality of portions of the hard mask layer230are removed to form the plurality of lower portions246to expose the plurality of cap layers169. As shown inFIG.12Z, the conductive material248is in contact with the plurality of cap layers169. As a result, multiple gate electrode layers168are electrically connected to the conductive material248. The conductive material248may be a rail type conductive feature.

The present disclosure in various embodiments provides a semiconductor device structure and methods of forming the same. In some embodiments, the structure includes a treated portion226of a hard mask layer222disposed over a S/D epitaxial feature152(or S/D epitaxial feature154) and a hard mask layer230disposed over a gate electrode layer168. The treated portion226has different etch selectivity compared to the hard mask layer230. Furthermore, a liner214is formed to replace a portion of a CESL160, and the liner214has a lower K value compared to the CESL160. Some embodiments may achieve advantages. For example, the treated portion226and the hard mask layer230having different etch selectivity may lead to minimizing a short circuit. In addition, the liner214has a lower K value than the CESL160, and parasitic capacitance may be reduced.

An embodiment is a semiconductor device structure. The structure includes a gate electrode layer disposed over a substrate, a source/drain epitaxial feature disposed over the substrate, a first hard mask layer disposed over the gate electrode layer, and a contact etch stop layer (CESL) disposed over the source/drain epitaxial feature. The contact etch stop layer is disposed adjacent and in contact with the first hard mask layer. The structure further includes a first interlayer dielectric (ILD) layer disposed on the CESL and a first treated portion of a second hard mask layer disposed on the CESL and the first ILD layer. A top surface of the first hard mask layer and a top surface of the first treated portion of the second mask layer are substantially coplanar. The structure further includes an etch stop layer disposed on the first hard mask layer and the first treated portion of the second mask layer.

Another embodiment is a semiconductor device structure. The structure includes a gate electrode layer disposed over a substrate, a first hard mask layer disposed over the gate electrode layer, a first source/drain epitaxial feature disposed over the substrate, and a contact etch stop layer (CESL) disposed over the first source/drain epitaxial feature. The CESL is in contact with the first hard mask layer. The structure further includes an interlayer dielectric (ILD) layer disposed on the CESL and a first treated portion of a second hard mask layer disposed on the CESL and the ILD layer. The first treated portion of the second hard mask layer includes a dielectric material doped with Ar, Ge, B, or As, and the first treated portion of the second hard mask layer is in contact with the first hard mask layer. The structure further includes an etch stop layer disposed on the first hard mask layer and the first treated portion of the second hard mask layer.

A further embodiment is a method. The method includes forming a contact etch stop layer (CESL) over a source/drain epitaxial feature and between two sacrificial gate electrode layers, forming a first interlayer dielectric (ILD) layer on the CESL, replacing the two sacrificial gate electrode layers with two gate electrode layers, removing the first ILD layer, removing the CESL, forming a liner over the source/drain epitaxial feature and between the two gate electrode layers, removing a portion of the liner disposed over the source/drain epitaxial feature, forming a conductive material between remaining portions of the liner, forming a first hard mask layer over the two gate electrode layers, the liner, and the first conductive material, performing a treatment process to form first treated portions of the first hard mask layer, second treated portions of the first hard mask layer, and untreated portions of the first hard mask layer, removing the untreated portions of the first hard mask layer, and forming a second hard mask layer over the gate electrode layers. The second hard mask layer is in contact with the liner, the first treated portions of the first hard mask layer, and the second treated portions of the first hard mask layer.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.