Patent ID: 12205662

DETAILED DESCRIPTION

Various embodiments of the present invention will be described below in more detail with reference to the accompanying drawings. The present invention may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present invention to those skilled in the art. Throughout this disclosure, like reference numerals refer to like parts throughout the various figures and embodiments of the present invention.

It will be understood that when an element is referred to as being “coupled” or “connected” to another element, it may mean that the two are directly coupled or the two are electrically connected to each other with another circuit intervening therebetween. It will be further understood that the terms “comprise”, “include”, “have”, etc. when used in this specification, specify the presence of stated features, numbers, steps, operations, elements, components, and/or combinations of them but do not preclude the presence or addition of one or more other features, numbers, steps, operations, elements, components, and/or combinations thereof. In the present disclosure, the singular forms are intended to include the plural forms as well, unless the context clearly indicates otherwise.

FIG.1is a block diagram illustrating a memory system10in accordance with an embodiment of the present invention.

Referring toFIG.1, the memory system10may store data or read the stored data in response to a request REQ provided from a host (i.e., an external device). The memory system10may be used as a main storage device or an auxiliary storage device of the host. The memory system10may be used as a device to store data under the control of the host, such as a mobile phone, a smartphone, an MP3 player, a laptop computer, a desktop computer, a game console, TV, a tablet PC, or an in-vehicle infotainment system.

The host may include one or more independent and substantial processors, each of which may be referred to as a core. The host may be implemented with a single core processor or a multi-core processor including two or more cores. The host may communicate with the memory system10using at least one of various communication standards or interfaces such as, for example, Universal Serial Bus (USB), Serial AT Attachment (SATA), Serial Attached SCSI (SAS), High Speed Interchip (HSIC), Small Computer System Interface (SCSI), Peripheral Component Interconnection (PCI), PCI express (PCIe of PCI-e), Non-Volatile Memory express (NVMe), Universal Flash Storage (UFS), Secure Digital (SD), MultiMedia Card (MMC), embedded MMC (eMMC), Dual In-line Memory Module (DIMM), Registered DIMM (RDIMM), and Load Reduced DIMM (LRDIMM) communication methods.

The memory system may include a memory controller100and a plurality of memory devices211to215. In an embodiment, the memory controller100and the memory devices211to215may constitute a memory module. The memory module may include any one selected from a dual-inline memory module (DIMM), a registered DIMM (RDIMM), a load reduced DIMM (LRDIMM), a non-volatile DIMM (NVDIMM).

The memory controller100may control an overall operation of the memory system10and control a data exchange between the host and the memory devices211to215. The memory controller100may generate a command/address signal C/A and provide it to the memory devices211to215according to the request REQ from the host. In an embodiment, the memory controller100may provide a clock to the memory devices211to215together with the command/address signal C/A. The memory controller100may provide data signals DQ1to DQ5and data strobe signals DQS1to DQS5corresponding to host data HDATA provided from the host to the memory devices211to215, during a write operation. The memory controller100may receive data signals DQ1to DQ5and data strobe signals DQS1to DQS5read from the memory devices211to215to the host as host data HDATA, during a read operation.

The memory devices211to215may perform an active operation, a precharge operation, a refresh operation, a write operation, a read operation, an error check operation, an error correction operation, and an error logging operation, according to the command/address signal C/A and/or the data signals DQ1to DQ5and data strobe signals DQS1to DQS5, which are provided from the memory controller100. Hereinafter, for convenience of description, a case where first to fifth memory devices211to215are arranged and the fifth memory device215stores an error correction code ECC will be described as an example.

In detail, the memory controller100may include a host interface110, a processor120, an error correction module140, a memory interface150, a training control module160, and a bus170.

The host interface110may communicate with the host coupled to the memory system10under the control of the processor120. For example, the host interface110may receive the request REQ and the host data HDATA from the host, and provide the host data HDATA to the host by receiving the first to fifth data signals DQ1to DQ5respectively read from the first to fifth memory devices211to215through the memory interface150.

The processor120may perform various types of computational and/or other operations for controlling the first to fifth memory devices211to215, and/or may execute instructions in the form of firmware or other types of software. The processor120may receive the request REQ and the host data HDATA provided from the host through the host interface110. The processor120may generate various commands (e.g., an active command, a precharge command, a refresh command, a refresh management command, a read command, a write command, a mode register command, an error check command, and an error information request command) corresponding to the request REQ, and addresses (e.g., a bank address, a row address, and a column address). The processor120may change an order of the operation to be instructed to the first to fifth memory devices211to215to be different from an order in which the request REQ is received from the host, in order to improve the performance of the first to fifth memory devices211to215. For example, the processor120may adjust the order so that a write operation is performed before a read operation, even if the host requests the read operation of the first to fifth memory devices211to215first and the write operation later. The processor120may control operations of the host interface110, the error correction module140, the memory interface150, and the training control module160.

The error correction module140may generate an error correction code ECC using the host data HDATA during a write operation. In the embodiment ofFIG.1, the unit of the host data HDATA processed during one write operation or one read operation, that is, a chunk size, is 256-bit, and the number of bits of the error correction code ECC is 64-bit. During the write operation, only the error correction code ECC is generated, but the error correction operation is not performed, so the 256-bit host data HDATA may be respectively transmitted to the first to fourth memory devices211to214as the data signals DQ1to DQ4, each for 64-bit, and the 64-bit error correction code ECC may be transmitted to the fifth memory device215.

In addition, the error correction module140may correct errors in the data signals DQ1to DQ4transmitted from the first to fourth memory devices211to214using the error correction code ECC corresponding to the data signal DQ5, respectively transmitted from the fifth memory device215, during the read operation. In an embodiment, errors in the data signals DQ1to DQ4transmitted from the first to fourth memory devices211to214as well as the data signal DQ5transmitted from the fifth memory device215may be corrected. The error-corrected data signal may be transferred to the host as the 256-bit host data HDATA. In an embodiment, the error correction module140may generate error location information (ERR_P inFIG.2) by verifying error locations of the first to fifth data signals DQ1to DQ5respectively transmitted from the first to fifth memory devices211to215during the read operation. A detailed configuration of the error correction module140will be described inFIG.3.

The memory interface150may communicate with the first to fifth memory devices211to215under the control of the processor120. For example, the memory interface150may respectively transmit the command/address signal C/A, the first to fifth data signals DQ1to DQ5and the first to fifth data strobe signals DQS1to DQS5to the first to fifth memory devices211to215, during a write operation. The memory interface150may respectively receive the first to fifth data signals DQ1to DQ5read from the first to fifth memory devices211to215according to the first to fifth data strobe signals DQS1to DQS5, during a read operation. In an embodiment, the memory interface150may respectively receive the first to fifth data signals DQ1to DQ5according to delay values set by first to fifth time codes (T_CODE1 to T_CODE5 shown inFIG.2) provided from the training control module160during a read operation. A detailed configuration and operation of the memory interface150will be described with reference toFIGS.4and5.

The training control module160may set the first to fifth time codes T_CODE1 to T_CODE5 by performing an initial training operation during boot-up. In addition, the training control module160may generate a plurality of error pattern maps by collecting the error location information ERR_P for the first to fifth data signals DQ1to DQ5provided from the error correction module140. In this case, the training control module160may generate a plurality of error pattern maps for each time code by collecting the error location information ERR_P for each of the first to fifth data signals DQ1to DQ5. The training control module160may adjust the first to fifth time codes T_CODE1 to T_CODE5, respectively, based on the error pattern maps and the first to fifth data signals DQ1to DQ5during a read operation. Each of the first to fifth time codes T_CODE1 to T_CODE5 may be a signal including multi-bits. A detailed configuration and operation of the training control module160will be described inFIG.2.

The processor120may transmit data between the host interface110, the error correction module140, the memory interface150and the training control module160via the bus170. In an embodiment, the host interface110, the error correction module140, the memory interface150and the training control module160may communicate with each other independently without passing through the bus170. For example, the training control module160and the host interface110may communicate directly with each other without passing through the bus170. The training control module160and the memory interface150may communicate with each other directly without passing through the bus170. The host interface110and the memory interface150may also communicate directly with each other without passing through the bus170.

As described above, in accordance with an embodiment of the present invention, in the memory system10, the time codes may be adjusted based on the error location information for the data signals transmitted from the memory devices during the read operation, and the data signals may be latched according to the time codes. That is, the time codes may be adjusted in real time during the read operation without entering a separate training mode. Accordingly, by performing the training operation in real time during the read operation, the data input/output timing may be optimized without performance degradation even if the data input/output timing is changed due to various factors after the initial training operation.

Hereinafter, a detailed configuration of the memory system10in accordance with an embodiment will be described.

FIG.2is a configuration diagram illustrating the memory controller100in accordance with an embodiment of the present invention.

InFIG.2, a detailed configuration of the error correction module140, the memory interface150and the training control module160is shown.

The memory interface150may include first to fifth data input/output (I/O) circuits151to155respectively corresponding to the first to fifth memory devices211to215. The first to fifth data I/O circuits151to155may transmit and receive the first to fifth data signals DQ1to DQ5and the first to fifth data strobe signals DQS1to DQS5, respectively, to and from the first to fifth memory devices211to215, during a write operation and a read operation. During the write operation, the first to fifth data I/O circuits151to155may transmit the first to fifth data signals DQ1to DQ5corresponding to internal data DIN to the first to fifth memory devices211to215in synchronization with the first to fifth data strobe signals DQS1to DQS5. During the read operation, the first to fifth data I/O circuits151to155may receive the first to fifth data signals DQ1to DQ5transmitted from the first to fifth memory devices211to215as the internal data DIN in synchronization with the first to fifth data strobe signals DQS1to DQS5, according to a delay value set by the first to fifth time codes T_CODE1 to T_CODE5.

WhileFIG.2illustrates that the memory interface150includes only the first to fifth data I/O circuits151to155, the memory interface150may further include a transmit circuit for transmitting the command/address signal C/A to the first to fifth memory devices211to215.

For reference, each memory device may transmit and receive serial data of a preset length through a plurality of data pads/pins in a write operation and a read operation. The preset length may be set by a burst length (BL) defined in the specification. The number of the data pads/pins and the burst length (BL) may determine a size of a data signal. In the following embodiment, a case where 8 data pads/pins of each memory device are arranged, and 8-bit data are transmitted and received in series (i.e., BL=8) through each data pad/pin at each write operation and read operation is described as an example. Each of the first to fifth data I/O circuits151to155may transmit and receive the 64-bit data signal at a time to and from the corresponding memory device.

The error correction module140may, in response to a write command WT, generate the 64-bit error correction code ECC using the 256-bit host data HDATA received from the host interface110, and output the 256-bit host data HDATA and the 64-bit error correction code ECC as the internal data DIN of 320-bit. The internal data DIN may include first to fourth internal data signal DIN1to DIN4corresponding to the host data HDATA and a fifth internal data signal DIN5corresponding to the error correction code ECC. The error correction module140may, in response to a read command RD, correct errors in the first to fifth internal data signals DIN1to DIN5using the fifth internal data signal DIN5of the 320-bit internal data DIN to output the error-corrected data signal to the host interface110as the 256-bit host data HDATA. In addition, the error correction module140may, in response to the read command RD, verify error locations of the first to fifth internal data signals DIN1to DIN5, generate the error location information ERR_P, and transmit the error location information ERR_P and the internal data DIN to the training control module160.

The training control module160may include an initial training circuit161, an error pattern collection circuit162, and a time code control circuit164.

The initial training circuit161may perform an initial training operation during boot-up to set the first to fifth time codes T_CODE1 to T_CODE5. The initial training operation may be performed in the same manner as known training operations. For example, the initial training circuit161may enter a training mode in response to a boot-up signal BOOT_UP (or a training mode signal) and set the first to fifth time codes T_CODE1 to T_CODE5 by comparing the first to fifth internal data signals DIN1to DIN5with target data. In order to perform the actual training operation, the initial training circuit161may receive additional control signals, but this will be omitted in order to focus on the essence of the invention.

The error pattern collection circuit162may generate the error pattern maps by collecting the error location information ERR_P provided from the error correction module140. The error pattern collection circuit162may generate the error pattern maps for each of the first to fifth time codes T_CODE1 to T_CODE5 set by the initial training circuit161during boot-up. The error pattern collection circuit162may generate the error pattern maps by mapping the error location information ERR_P to each of the set time codes. The error pattern collection circuit162may provide map information P_MAP including the error pattern maps of each time code to the time code control circuit164. The error pattern maps collected by the error pattern collection circuit162will be described with reference toFIGS.6A to6E.

The time code control circuit164may compare the error location information ERR_P corresponding to each of the first to fifth internal data signals DIN1to DIN5with the error pattern maps of each time code, included in the map information P_MAP, to thereby calculate a similarity therebetween, in response to the read command RD. The time code control circuit164may adjust the first to fifth time codes T_CODE1 to T_CODE5 according to the calculated similarity. For example, the time code control circuit164may adjust the first time code T_CODE1 by comparing the error pattern maps for the first time code T_CODE1 with the error location information ERR_P for the first internal data signal DIN1, adjust the second time code T_CODE2 by comparing the error pattern maps for the second time code T_CODE2 with the error location information ERR_P for the second internal data signal DIN2, adjust the third time code T_CODE3 by comparing the error pattern maps for the third time code T_CODE3 with the error location information ERR_P for the third internal data signal DIN3, adjust the fourth time code T_CODE4 by comparing the error pattern maps for the fourth time code T_CODE4 with the error location information ERR_P for the fourth internal data signal DIN2, and adjust the fifth time code T_CODE5 by comparing the error pattern maps for the fifth time code T_CODE5 with the error location information ERR_P for the fifth internal data signal DIN5. A detailed configuration of the time code control circuit164will be described with reference toFIG.7.

FIG.3is a detailed block diagram illustrating the error correction module140shown inFIG.2.

Referring toFIG.3, the error correction module140may include an error correction code generation circuit142and an error correction circuit144.

InFIG.3, for convenience of description, the host data HDATA is divided into host write data HWD for a write operation and host read data HRD for a read operation, and the internal data DIN is divided into internal write data WDIN for a write operation and the error correction code ECC, and internal read data RDIN for a read operation and the error correction code ECC. In this case, the internal write data WDIN and the internal read data RDIN correspond to the first to fourth internal data signals DIN1to DIN4, and the error correction code ECC may correspond to the fifth internal data signal DIN5.

The error correction code generation circuit142may generate the error correction code ECC using the host write data HWD in response to the write command WT and output the internal write data WDIN and the error correction code ECC. The host write data HWD may be the same as the internal write data WDIN, since only the error correction code ECC is generated during the write operation without performing an error correction operation.

The error correction circuit144may correct errors in the internal read data RDIN using the error correction code ECC in response to the read command RD and output the error-corrected data as the host read data HRD.

In detail, the error correction circuit144may include a syndrome generator210, an error location detector220, and an error corrector230, which operate according to the read command RD.

The syndrome generator210may generate a preliminary error correction code using the internal read data RDIN, and may generate syndrome data SYN, as encoding error location information, by bitwise comparing the preliminary error correction code with the error correction code ECC.

The error location detector220may detect the error locations in the internal read data RDIN and/or the error correction code ECC based on the syndrome data SYN. The error location detector220may decode the syndrome data SYN to generate the error location information ERR_P for the internal read data RDIN and/or the error correction code ECC. For example, the error location information ERR_P may include bits equal to the number of bits in the internal read data RDIN and/or the error correction code ECC, indicating which bits in the internal read data RDIN and/or the error correction code ECC are in error.

The error corrector230may correct errors in the internal read data RDIN and/or the error correction code ECC based on the error location information ERR_P to output the error-corrected data as the host read data HRD. For example, the error corrector230may include a plurality of XOR gates that perform a logic XOR operation on bits of the error location information ERR_P and bits of the internal read data RDIN and/or the error correction code ECC.

FIG.4is a detailed circuit diagram illustrating the first data I/O circuit151shown inFIG.2. Since the first to fifth data I/O circuits151to155have substantially the same configuration, the configuration of the first data I/O circuit151will be described by way of example.

For reference, the first data I/O circuit151may include a data output circuit for a write operation (not shown) and a data input circuit151′ for a read operation, and only the data input circuit151′ for a read operation will be described herein.

Referring toFIG.4, the data input circuit151′ may include a delay circuit310and a sampling circuit320.

The delay circuit310may include a plurality of delay cells whose delay is adjusted according to the first time code T_CODE1. Each of the delay cells may operate according to a corresponding bit of the first time code T_CODE1. Accordingly, the delay circuit310may delay the first data strobe signal DQS1by a delay value set by the first time code T_CODE1 to generate a first sampling signal S_DQS1. For example, the delay value may be sequentially decreased whenever the first time code T_CODE1 is downcounted, and the delay value may be sequentially increased whenever the first time code T_CODE1 is upcounted.

The sampling circuit320may sample the first data signal DQ1input from the first memory device211in synchronization with the first sampling signal S_DQS1during the read operation to generate the first internal data signal DIN1of the internal data DIN. Although not shown, the sampling circuit320may operate in response to a read command RD.

FIG.5is a timing diagram for describing an operation of the first data input circuit151′ shown inFIG.4.FIGS.6A to6Eare tables illustrating examples of error pattern maps generated by the error pattern collection circuit162, according to an embodiment of the present invention.

Referring toFIG.5, the first data input circuit151′ may determine an effective window according to the delay value set by the first time code T_CODE1, and latch the first data signal DQ1in synchronization with a rising edge and a falling edge of the first data strobe signal DQS1within the determined effective window to generate the first internal data signal DIN1.

For example,FIG.5illustrates a case where the first time code T_CODE1 is set to an optimal code value of “3” by the initial training operation. The first data input circuit151′ may receive serial data in 8-bit units for each burst length BL. When the first time code T_CODE1 is set to the optimal code value of “3”, the first data input circuit151′ may normally receive the first internal data signal DIN1in the order of A-B-C-D-E-F-G-H. Accordingly, as shown inFIG.6A, the error pattern collection circuit162may generate a target map for the first time code T_CODE1 having the optimal code value of “3” set by the initial training operation.

When the first time code T_CODE1 is a code value of “1”, the first data input circuit151′ may abnormally receive the first internal data signal DIN1in the order of XX-XX-A-B-C-D-E-F. Accordingly, the error correction circuit144may generate the error location information ERR_P for first and second burst lengths BL0 and BL1, and the error pattern collection circuit162may generate a first error pattern map for the first time code T_CODE1 having the code value of “1”, as shown inFIG.6B.

When the first time code T_CODE1 is a code value of “2”, the first data input circuit151′ may abnormally receive the first internal data signal DIN1in the order of XX-A-B-C-D-E-F-G. Accordingly, the error correction circuit144may generate the error location information ERR_P for a first burst length BL0, and the error pattern collection circuit162may generate a second error pattern map for the first time code T_CODE1 having the code value of “2”, as shown inFIG.6C. When the first time code T_CODE1 is a code value of “4”, the first data input circuit151′ may abnormally receive the first internal data signal DIN1in the order of B-C-D-E-F-G-H-XX. Accordingly, the error correction circuit144may generate the error location information ERR_P for an eighth burst length BL7, and the error pattern collection circuit162may generate a third error pattern map for the first time code T_CODE1 having the code value of “4”, as shown inFIG.6D.

When the first time code T_CODE1 is a code value of “5”, the first data input circuit151′ may abnormally receive the first internal data signal DIN1in the order of C-D-E-F-G-H-XX-XX. Accordingly, the error correction circuit144may generate the error location information ERR_P for seventh and eighth burst lengths BL6 and BL7, and the error pattern collection circuit162may generate a fourth error pattern map for the first time code T_CODE1 having the code value of “5”, as shown inFIG.6E.

In the same manner as described above, the error pattern collection circuit162may generate the error pattern maps for each time code.

FIG.7is a detailed configuration diagram illustrating the time code control circuit164shown inFIG.2.

Referring toFIG.7, the time code control circuit164may include a counter control circuit510, first to fifth counter groups521to525, and a code control circuit530.

The first to fifth counter groups521to525may correspond to the first to fifth memory devices211to215, i.e., the first to fifth time codes T_CODE1 to T_CODE5, respectively. Each of the first to fifth counter groups521to525may have a plurality of counters corresponding to the error pattern maps. For example, if four error pattern maps are present, as described inFIGS.6A to6E, each of the first to fifth counter groups521to525may have four counters. The first to fifth counter groups521to525may initialize the counters in response to first to fifth initialization signals RST1to RST5, respectively.

The counter control circuit510may compare the error location information ERR_P for each of the first to fifth internal data signals DIN1to DIN5with the error pattern maps included in the map information P_MAP, to thereby calculate a similarity therebetween, in response to the read command RD. The counter control circuit510may adjust counting values P_CNT11 to P_CNT54 of the first to fifth counter groups521to525by selecting an error pattern map and an internal data signal whose calculated similarity is higher than a first threshold value. For example, the first threshold may be set to a percentage between 51% and 100%.

The counter control circuit510may increase a counting value of a counter corresponding to the selected error pattern map among counters of a counter group corresponding to the selected internal data signal, while decreasing or maintaining counting values of the remaining counters of the same counter group. For example, if the first threshold is set to 70%, the counter control circuit510may calculate a similarity between the error location information ERR_P for the first internal data signal DIN1and the first error pattern map shown inFIG.6B, to be 75%, to select a first counter of the first counter group521, where the first counter corresponds to the first error pattern map and the first counter group521corresponds to the first internal data signal DIN1. The counter control circuit510may increase the counting value P_CNT11 of the first counter of the first counter group521, by “+1”, while decreasing the counting values P_CNT12 to P_CNT14 of the remaining counters522of the first counter group521by “−1”.

The counter control circuit510may decrease the counting values of all counters in a corresponding counter group when an error pattern map and an internal data signal, for which the calculated similarity is higher than the first threshold, do not exist. For example, the counter control circuit510may decrease the counting values P_CNT11 to P_CNT14 of all counters in the first counter group521by “−1” when the similarity between all error pattern maps and the error location information ERR_P for the first internal data signal DIN1is not greater than 70%.

The code control circuit530may adjust the code values of the first to fifth time codes T_CODE1 to T_CODE5 according to the counting values P_CNT11 to P_CNT54 of the first to fifth counter groups521to525. The code control circuit530may include first to fifth code controllers531to535corresponding to the first to fifth counter groups521to525, respectively. Each of the first to fifth code controllers531to535may compensate a code value of a corresponding time code based on a counting value greater than a second threshold, among code values of a corresponding counter group. For example, the first code controller531may compensate the code value of the first time code T_CODE1 based on the second error pattern map corresponding to the second counter when the second counting value P_CNT12 is greater than the second threshold value, among the counting values P_CNT11 to P_CNT14 of the first counter group.

Meanwhile, the first to fifth code controllers531to535may generate the first to fifth initialization signals RST1to RST5, respectively, after the code value of the corresponding time code is compensated. For example, the first code controller531may activate the first initialization signal RST1after compensating the code value of the first time code T_CODE1.

Hereinafter, with reference toFIGS.1to11, an operation of the memory system10according to an embodiment of the present invention will be described.

FIGS.8and9are flowcharts for describing an operating method of the memory system10in accordance with an embodiment of the present invention.

Referring toFIG.8, during boot-up, the initial training circuit161of the training control module160may set the first to fifth time codes T_CODE1 to T_CODE5 through an initial training operation (at S810). The error pattern collection circuit162may generate the error pattern maps for each of the first to fifth time codes T_CODE1 to T_CODE5 set by the initial training circuit161(at S820). As described inFIGS.6A to6E, the error pattern collection circuit162may generate the error pattern maps by mapping the error location information ERR_P to each of the set time codes.

Thereafter, the first to fifth memory devices211to215may perform a read operation in response to a request REQ from the host (at S830). In the read operation, the first to fifth data I/O circuits151to155operate according to a delay value set by the first to fifth time codes T_CODE1 to T_CODE5, the first to fifth data signals DQ1to DQ5transmitted from the first to fifth memory devices211to215may be received as the first to fifth internal data signals DIN1to DIN5in synchronization with the first to fifth data strobe signals DQS1to DQS5. The error correction circuit144may, in response to the read command RD, correct errors in the first to fifth internal data signals DIN1to DIN5to output the host data HDATA and generate the error location information ERR_P by verifying the error locations of the first to fifth internal data signals DIN1to DIN5.

The counter control circuit510of the time code control circuit164may compare the error location information ERR_P with the error pattern maps corresponding to each of the first to fifth internal data signals DIN1to DIN5, to thereby calculate the similarity therebetween (at S840). The counter control circuit510may adjust the counting values P_CNT11 to P_CNT54 of the first to fifth counter groups521to525according to the calculated similarity (at S850).

More specifically, referring toFIG.9, the counter control circuit510may determine whether an error pattern map exists in which the similarity to a specific internal data signal is higher than a first threshold TH1 (at S910). When an error pattern map whose similarity to the specific internal data signal is higher than the first threshold TH1 exists (“YES” in S910), the counter control circuit510may increase a counting value of a counter corresponding to the error pattern map, among the counters in a counter group corresponding to the specific internal data signal (at S920), and decrease or maintain the counting values of the remaining counters in the same counter group (at S930). On the other hand, when an error pattern map whose similarity to a specific internal data signal is higher than the first threshold TH1 does not exist (“NO” in S910), the counter control circuit510may decrease the counting values of all counters in the corresponding counter group (at S940). Referring back toFIG.8, each of the first to fifth code controllers531to535may determine whether a counting value greater than a second threshold TH2 exists among the counting values of the corresponding counter group (at S860).

When no counting value greater than the second threshold TH2 exists (“NO” in S860), the first to fifth code controllers531to535may terminate the operation without adjusting the time codes.

On the other hand, when a counting value greater than the second threshold TH2 exists (“YES” in S860), each of the first to fifth code controllers531to535may adjust and compensate a code value of a corresponding time code based on an error pattern map corresponding to a counter whose counting value is greater than the second threshold TH2 (at S870). Thereafter, the first to fifth code controllers531to535may generate the first to fifth initialization signals RST1to RST5, respectively, after the code value of the corresponding time code is compensated (at S880). For example, the first code controller531may activate the first initialization signal RST1after compensating the code value of the first time code T_CODE1.

FIGS.10and11are diagrams which illustrate an operation shown inFIG.8.

Referring toFIG.10, a case in which the first time code T_CODE1 is set to an optimum delay value of “1” through the initial training operation is illustrated. According to the delay value set by the first time code T_CODE1, the first data I/O circuit151has received the first data signal DQ1transmitted from the first memory device211as the first internal data signal DIN1in the order of A-B-C-D-E-F-G-H in synchronization with the first data strobe signal DQS1. However, since the data input/output timing may become skewed over time, the first data input circuit151′ may abnormally receive the first internal data signal DIN1in the order of XX-XX-A-B-C-D-E-F.

The counter control circuit510may detect a first error pattern map (seeFIG.6B) whose similarity to the first internal data signal DIN1is higher than the first threshold TH1 and increase the counting value P_CNT11 of the first counter of the first counter group, while decreasing or maintaining the counting values P_CNT12 to P_CNT14 of the remaining counters of the first counter group. In this way, after several read operations are performed, when the counting value P_CNT11 of the first counter exceeds the second threshold TH2, the first code controller531may compensate the code value of the first time code T_CODE1 by “+2” to an optimal delay value of “3” based on the first error pattern map corresponding to the first counter.

Referring toFIG.11, in a case where the first time code T_CODE1 is set to an optimum delay value of “4” through the initial training operation is illustrated. However, since the data input/output timing may become skewed over time, the first data input circuit151′ may abnormally receive the first internal data signal DIN1in the order of B-C-D-E-F-G-H-XX.

The counter control circuit510may detect a third error pattern map (seeFIG.6D) whose similarity to the first internal data signal DIN1is higher than the first threshold TH1 and increase the counting value P_CNT13 of the third counter of the first counter group, while decreasing or maintaining the counting values P_CNT11, P_CNT12 and P_CNT14 of the remaining counters of the first counter group. When the counting value P_CNT13 of the third counter exceeds the second threshold TH2, the first code controller531may compensate the code value of the first time code T_CODE1 by “−1” to an optimal delay value of “3” based on the third error pattern map corresponding to the third counter.

In the above embodiment, a case in which the first to fifth time codes T_CODE1 to T_CODE5 are each set to an absolute value is described as an example, but the present invention is not limited thereto. In an embodiment, the time code (e.g., the first time code T_CODE1) having the optimal code value among the first to fifth time codes T_CODE1 to T_CODE5 may be set to a reference value of “0”, and the remaining time codes may be set to relative values (e.g., “−2”, “−1”, “+1”, “+2”) to the reference value. For example, inFIG.11, the first code controller531may compensate for the code value (e.g., “+1”) of the first time code T_CODE1 to an optimal delay value of “0” by adjusting the code value by “−1”.

As described above, in accordance with the embodiment, the memory system may perform the training operation in real time during the read operation, so that the data input/output timing may be optimized without performance degradation even if the data input/output timing is changed after the initial training operation.

Various embodiments of the present disclosure have been described in the drawings and specification. Although specific terminologies are used here, the terminologies are only to describe the embodiments of the present disclosure. Therefore, the present disclosure is not restricted to the above-described embodiments and many variations are possible within the spirit and scope of the present disclosure. It should be apparent to those skilled in the art that various modifications can be made on the basis of the technological scope of the present disclosure in addition to the embodiments disclosed herein. The embodiments may be combined to form additional embodiments.

It should be noted that although the technical spirit of the disclosure has been described in connection with embodiments thereof, this is merely for description purposes and should not be interpreted as limiting. It should be appreciated by one of ordinary skill in the art that various changes may be made thereto without departing from the technical spirit of the disclosure and the following claims.

For example, for the logic gates and transistors provided as examples in the above-described embodiments, different positions and types may be implemented depending on the polarity of the input signal.