Patent ID: 12211464

DETAILED DESCRIPTION

The invention will be described more fully hereinafter with reference to the accompanying drawings, in which embodiments of the invention are shown. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the invention.

Parts that are irrelevant to the description will be omitted to clearly describe the invention, and like reference numerals designate like elements throughout the specification.

Further, in the drawings, the size and thickness of each element are arbitrarily illustrated for ease of description, but the invention is not limited to those illustrated in the drawings. In the drawings, the thicknesses of layers, films, panels, regions, etc., are exaggerated for clarity. In the drawings, for ease of description, the thicknesses of some layers and areas are exaggerated.

It will be understood that when an element such as a layer, film, region, or substrate is referred to as being “on” another element, it can be directly on the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly on” another element, there are no intervening elements present.

In the specification, unless explicitly described to the contrary, the word “comprise” and variations such as “comprises” or “comprising” will be understood to imply the inclusion of stated elements but not the exclusion of any other elements.

In the drawings, as symbols used for indicating directions, “x” is a first direction, “y” is a second direction perpendicular to the first direction, and “z” is a third direction perpendicular to the first direction and the second direction. The first direction x, the second direction y, and the third direction z may correspond to a horizontal direction, a vertical direction, and a thickness direction of the display device, respectively.

“About” or “approximately” as used herein is inclusive of the stated value and means within an acceptable range of deviation for the particular value as determined by one of ordinary skill in the art, considering the measurement in question and the error associated with measurement of the particular quantity (i.e., the limitations of the measurement system). For example, “about” can mean within one or more standard deviations, or within ±30%, 20%, 10%, 5% of the stated value.

Hereinafter, a display device (a light emitting display device as an example) according to embodiments will be described with reference to the drawings.

First, an exemplary embodiment of a display device will be described with reference toFIGS.1and2.FIG.1illustrates a schematic top plan view of an exemplary embodiment of a display device1, andFIG.2illustrates a schematic cross-sectional view of an exemplary embodiment of the display device1.

Referring toFIGS.1and2, the display device1may include a display panel10, a flexible printed circuit film20connected to the display panel10, a driving device including an integrated circuit (“IC”) chip30, and an optical member40.

The display panel10may include a display area DA for displaying an image and a non-display area NA surrounding the display area DA. The display area DA may correspond to a screen, and the non-display area NA may correspond to a bezel. Pixels PX are arranged in a matrix form in the display area DA. Circuits and/or signal lines for generating and/or transmitting various signals to be applied to the display area DA are disposed in the non-display area NA. A scan line, an emission control line, a data line, a driving voltage line, and the like are connected to each pixel PX, and the pixel PX may receive a scan signal, an emission control signal, a data signal, a driving voltage, and the like from these lines.

The display area DA includes a first display area DA1and a second display area DA2. The second display area DA2has higher transmittance than that of the first display area DA1so as to be able to perform another function in addition to a unique function of displaying an image. To this end, a density of the pixels PX may be lower in the second display area DA2than in the first display area DA1. Here, the transmittance means transmittance of light through the display panel10in the third direction z. The light may be light having a wavelength other than the wavelength of visible light, for example, infrared light, but may also include visible light.

A ratio of an area where an image may be displayed in the second display area DA2, that is, an area occupied by a pixel area, may be smaller than that of an area occupied by the pixel area in the first display area DA1. In an exemplary embodiment, the second display area DA2includes the pixel area and a transmission area, and the transmission area has higher transmittance than that of the pixel area, for example. The pixel PX may not be disposed in the transmission area. Here, the pixel PX is a minimum unit for forming a screen, that is, a minimum unit for displaying an image, and each pixel PX may display a specific color, for example, any one of red, green, and blue colors at various luminance levels, according to an input image signal.

The second display area DA2may be disposed above the first display area DA1.

Both sides of the second display area DA2may be the first display area DA1as shown, but the second display area DA2may be variously positioned. In an exemplary embodiment, the second display area DA2may completely cross an upper end of the display area DA to be disposed along the first direction x, for example. The second display area DA2may be surrounded by the first display area DA1. The second display area DA2may be disposed at a left or right side of the upper end of the display area DA, and may not be disposed at a central portion of the upper end of the display area DA but may be separately disposed at the left and right sides. The second display area DA2may be substantially rectangular. In an exemplary embodiment, the second display area DA2may have various shapes such as a trapezoid, a circle, and an ellipse.

A driving unit for generating and/or processing various signals for driving the display panel10may be disposed in the non-display area NA of the display panel10. The driving unit includes a data driver for applying a data signal to data lines, a scan driver for applying a scan signal to scan lines, an emission driver for applying an emission control signal to emission control lines, and a signal controller for controlling the data driver, the scan driver, and the emission driver. The scan driver and the emission driver may be integrated in the display panel10, and may be disposed at the left and right sides of the display area DA or at one side thereof. The data driver and the signal controller may be provided as an IC chip (also referred to as a driving IC chip)30, and the IC chip30may be disposed (e.g., mounted) on the flexible printed circuit film20to be electrically connected to the display panel10. The IC chip30may be disposed (e.g., mounted) on the non-display area NA of the display panel10.

The display panel10may include a substrate110, and the pixels PX may be disposed on the substrate110. The substrate110may be continuously disposed over the first display area DA1and the second display area DA2. The display panel10may include an encapsulation layer210entirely covering the pixels PX. The encapsulation layer210may seal the first display area DA1and the second display area DA2to prevent water or oxygen from penetrating into the display panel10. When the encapsulation layer210is in a form of a substrate, the substrate110and the encapsulation layer210may be bonded together by a sealant. An anti-reflection layer300for reducing external light reflection may be disposed on the encapsulation layer210, and the anti-reflection layer300may include a polarization layer and/or a retardation layer.

The optical member40may be disposed on a back surface of the display panel10. In an exemplary embodiment, the optical member40may be a sensor, a camera, a flash, or the like. When the optical member40is a sensor, the optical member40may be a proximity sensor or an illuminance sensor. Light of a wavelength used by the optical member40may pass through the display panel10at higher transmittance through the second display area DA2. Various electronic devices may be disposed on the back surface of the display panel10in addition to the optical member40.

The optical member40may emit light L in a predetermined wavelength range toward an object OB disposed on a front surface of the display panel10or receive light L reflected from the object OB. The light L having the predetermined wavelength may be light having a wavelength that may be processed by the optical member40, and may be light having a wavelength other than the wavelength in a visible light region, which corresponds to a region of light of an image displayed by the pixel PX. The light L of the predetermined wavelength may mainly pass through a transmission area disposed in the second display area DA2. In an exemplary embodiment, when the optical member40uses infrared light, the light of the predetermined wavelength may have a wavelength range of about 900 nanometers (nm) to about 1000 nm, for example. The optical member40may receive light of a predetermined wavelength to be irradiated onto the front surface of the display panel10. The light of the predetermined wavelength may include visible light. The optical member40may be disposed corresponding to all of the second display area DA2, or may be disposed corresponding to only some of the second display area DA2. A plurality of optical members40may be disposed in the second display area DA2.

The first display area DA1and the second display area DA2of the display device1in the exemplary embodiment will now be described with reference toFIGS.3to5together with the above-described drawings.

FIGS.3,4, and5illustrate schematic plan views of an exemplary embodiment of the first display area DA1and the second display area DA2of the display device.FIG.3illustrates a schematic plan view of pixel areas PA1and PA2and the transmission area TA,FIG.4specifically illustrates a pixel that may be included in the pixel areas PA1and PA2, andFIG.5illustrates some signal lines disposed in the pixel areas PA1and PA2.

Referring toFIG.3, the first display area DA1includes the first pixel areas PA1, and the second display area DA2includes the second pixel areas PA2and the transmission areas TA. A size of one first pixel area PA1and a size of one second pixel area PA2may be the same or different.

In the first display area DA1, the first pixel areas PA1may be arranged in a matrix form in the first direction x and the second direction y which are different directions. In the second display area DA2, the second pixel areas PA2and the transmission areas TA may be arranged in a matrix form. The second pixel areas PA2and the transmission areas TA may be arranged in a checkerboard pattern so that the second pixel areas PA2and the transmission areas TA may be uniformly mixed. That is, the transmission areas TA are adjacent to one second pixel area PA2in the first direction x and the second direction y, and the second pixel area PA2may be adjacent to one transmission area TA in the first direction x and the second direction y. A size of one second pixel area PA2and a size of one transmission area TA may be the same or different. Respective transmission areas TA may have the same size or may be different from each other in size. An arrangement and size of the second pixel areas PA2and the transmission areas TA may be variously changed.

Each of the pixel areas PA1and PA2may include one or more pixels PX. In the exemplary embodiment shown inFIGS.4and5, each of the pixel areas PA1and PA2may include one red pixel R, two green pixels G, and one blue pixel B. Respective transmission areas TA may have sizes corresponding to the four pixels.

The pixels R, G, and B included in the pixel areas PA1and PA2form pixel rows Rj, Rj+1, Rj+2, . . . , Rj+7in the first direction x where j is a natural number. AlthoughFIGS.4and5each show eight pixel rows, the display area DA may include a number of pixel rows corresponding to a predetermined resolution. In each pixel row, the pixels R, G, and B are substantially arranged in a line in a direction parallel to the first direction x. The pixels R, G, and B in each pixel row are repeatedly arranged in an order of the blue pixel B, the green pixel G, the red pixel R, and the green pixel G in the first direction x, or in an order of the red pixel R, the green pixel G, the blue pixel B, and the green pixel G. In each pixel row of the second display area DA2, the transmission area TA may be disposed between adjacent second pixel areas PA2. The arrangement of the pixels R, G, and B included in one pixel row may be variously changed. In an exemplary embodiment, the pixels R, G, and B may be repeatedly arranged in an order of the red pixel R, the blue pixel B, the green pixel G, and the blue pixel B in the first direction x, for example.

The pixels R, G, and B included in the pixel areas PA1and PA2also form pixel columns Ci, Ci+1, Ci+2, . . . , Ci+7in the second direction y where i is a natural number. AlthoughFIG.4shows 16 pixel columns andFIG.5shows 8 pixel columns, the display area DA may include a number of pixel columns corresponding to a predetermined resolution. In each pixel column, the pixels R, G, and B are substantially arranged in a line in a direction parallel to the second direction y. In an exemplary embodiment, the pixel column Cishown at a leftmost side inFIG.5includes the blue pixel B, the blue pixel B, the blue pixel B, the red pixel R, the blue pixel B, and the red pixel R, for example. Due to the transmission area TA in the second display area DA2, the pixel column Cimay not include the red pixel R in the second display area DA2. In other words, no pixels are disposed at a position where the red pixel R is to be disposed in the second display area DA2. The pixel column Ci+1adjacent to the pixel column Ciincludes only the green pixels G. A pixel column Ci+2includes the red pixel R, the red pixel R, the red pixel R, the blue pixel B, the red pixel R, and the blue pixel B. Due to the transmission area TA in the second display area DA2, the pixel column Ci+2may not include the blue pixel B in the second display area DA2. A pixel column Ci+3includes only the green pixels G. Such a pixel arrangement may be repeated in the first direction x with four pixel columns Ci, Ci+1, Ci+2, and Ci+3as a basic unit. The arrangement of the pixels R, G, and B included in one pixel column may be variously changed.

Scan lines SL1and SL2and an emission control line EL may extend in the first direction x along respective pixel rows Rj, Rj+1, Rj+2, . . . , Rj+7, and data lines DLa and DLb may extend in the second direction y along respective pixel columns Ci, Ci+1, Ci+2, . . . , Ci+7.

The data lines DLa and DLb, which are signal lines for transmitting a data signal, may include a first data line DLa and a second data line DLb which are paired with each other. In each pixel column, one of the pair of data lines DLa and DLb may be connected to the pixels disposed on an odd-numbered pixel row, and the other may be connected to the pixels disposed on an even-numbered pixel row. In an exemplary embodiment, in the pair of data lines DLa and DLb, the first data line DLa may be connected to the pixels disposed on the odd-numbered pixel row, and the second data line DLb may be connected to the pixels disposed on the even-numbered pixel row, for example. In contrast, in the pair of data lines DLa and DLb, the first data line DLa may be connected to the pixels disposed on the even-numbered pixel row, and the second data line DLb may be connected to the pixels disposed on the odd-numbered pixel row.

The data lines DLa and DLb in each pixel column are disposed in both the first display area DA1and the second display area DA2, but one of the data lines DLa and DLb is substantially disposed only in the first display area DA1and is not disposed in the second display area DA2. In an exemplary embodiment, the second data line DLb is not disposed in the second display area DA2in the pixel column Ci, and the first data line DLa is not disposed in the second display area DA2in the pixel column Ci+1, for example. As such, even though only one of the pair of data line DLa and DLb extends to the second display area DA2, since the pixel is disposed only in even-numbered or odd-numbered rows for each pixel column in the second display area DA2, the pixels disposed in the second display area DA2may receive a data signal through the data line extending to the second display area DA2. In addition, since only one data line is disposed in the transmission area TA of the second display area DA2in each pixel column, it is possible to increase transmittance of each transmission area TA and transmittance of the second display area DA2.

FIG.6illustrates a plan view of an exemplary embodiment of a second display area DA2of a display device.

FIG.6illustrates an example in which the first display areas DA1are disposed at opposite sides of the second display area DA2and the transmission areas TA are not the same but are changed. Each second pixel area PA2may include one pixel. In the shown embodiment, although each second pixel area PA2includes the red pixel R, it may include the blue pixel B or the green pixel G, and it may display a single color (e.g., a red, blue, or green color). Each second pixel area PA2may include two or more of the red pixel R, the green pixel G, and the blue pixel B.

A pixel (e.g., the red pixel R) may be disposed only in the even-numbered pixel row or the odd-numbered pixel row in each pixel column. A pixel is not disposed in a pixel column (e.g., the fourth pixel column from the left side, the third pixel column from the right side), and only the transmission area TA may be disposed therein. The transmission area TA may have a size corresponding to one pixel, a size corresponding to two pixels, or a size corresponding to three pixels. In the shown embodiment, the transmission areas TA having the size corresponding to three pixels occupy the majority of the area thereof. The transmission area TA may have a size corresponding to three or more pixels.

As such, by reducing the number of the pixels included in each second pixel area PA2, a ratio of the transmission areas TA may be increased in the second display area DA2, thereby increasing the transmittance of the second display area DA2. However, a density of the pixels is lowered, thus a resolution of the second display area DA2may be decreased. Only one of the data lines DLa and DLb described above may extend in each pixel column in the second display area DA2to be connected to the pixels disposed in the odd-numbered pixel row or the even-numbered pixel row. Thus, a data voltage may be applied to the pixels disposed in the second display area DA2, and it is possible to increase the transmittance of the transmission area TA. Both of the data lines DLa and DLb may not extend in the pixel column that does not include a pixel in the second display area DA2, and it is possible to further increase the transmittance of the second display area DA2.

FIG.7illustrates a circuit diagram of an exemplary embodiment of one pixel of a display device.

Referring toFIG.7, one pixel PX includes transistors T1, T2, T3, T4, T5, T6, and T7, a capacitor Cst, and a light emitting diode ED that are connected to signal lines151,152,153,154,161,171, and172.

The signal lines151,152,153,154,161,171, and172may include scan lines151,152, and154, an emission control line153, a data line171, a driving voltage line172, and an initialization voltage line161.

The scan lines151,152, and154may transmit scan signals GWn, GIn, and GI(n+1), respectively. The scan signals GWn, GIn, and GI(n+1) may transmit a gate-on voltage and a gate-off voltage that may turn on and turn off the transistors T2, T3, T4, and T7included in the pixel PX.

The scan lines151,152, and154connected to one pixel PX may include a first scan line151capable of transmitting the scan signal GWn, a second scan line152capable of transmitting the scan signal GIn having a gate-on voltage at different timing from that of the first scan line151, and a third scan line154capable of transmitting the scan signal GI(n+1). The second scan line152may transmit the gate-on voltage at earlier timing than the first scan line151. In an exemplary embodiment, when the scan signal GWn is an n-th scan signal among the scan signals applied during one frame, the scan signal GIn may be a previous scan signal such as an (n−1)-th scan signal and the like, and the scan signal GI(n+1) may be the n-th scan signal, for example. In another exemplary embodiment, the scan signal GI(n+1) may be a different scan signal from the n-th scan signal.

The emission control line153may transmit an emission control signal EM to be able to control light emission of the light emitting diode ED. The emission control signal EM may include a gate-on voltage and a gate-off voltage.

The data line171, which is one of the data lines DLa and DLb described above, may transmit a data signal Dm. The driving voltage line172may transmit a driving voltage ELVDD. The data signal Dm may have a different voltage level depending on an image signal inputted to the display device, and the driving voltage ELVDD may have a substantially constant level. The initialization voltage line161may transmit a constant voltage such as an initialization voltage Vint.

The display device may include a driving device (e.g., a scan driver, an emission driver, a data driver, a signal controller, etc.) for generating signals transmitted to the signal lines151,152,153,154,161,171, and172.

The transistors T1, T2, T3, T4, T5, T6, and T7included in one pixel PX may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a seventh transistor T7.

The first scan line151may transmit the scan signal GWn to the second transistor T2and the third transistor T3. The second scan line152may transmit the scan signal GIn to the fourth transistor T4. The third scan line154may transmit the scan signal GI(n+1) to the seventh transistor T7. The emission control line153may transmit the emission control signal EM to the fifth transistor T5and the sixth transistor T6. Respective transistors T1, T2, T3, T4, T5, T6, and T7may include respective source electrodes S1, S2, S3, S4, S5, S6, and S7, respective drain electrodes D1, D2, D3, D4, D5, D6, and D7, and respective gate electrodes G1, G2, G3, G4, G5, G6, and G7, and may be connected as shown.

The first transistor T1may receive the data signal Dm transmitted from the data line171according to a switching operation of the second transistor T2, and may supply a driving current Id to the light emitting diode ED.

The second transistor T2may be turned on depending on the scan signal GWn transmitted through the first scan line151to transmit the data signal Dm transmitted from the data line171to the source electrode S1of the first transistor T1.

The third transistor T3may be turned on depending on the scan signal GWn transmitted through the first scan line151to connect the gate electrode G1and the drain electrode D1of the first transistor T1to each other to diode-connect the first transistor T1.

The fourth transistor T4is turned on depending on the scan signal GIn transmitted through the second scan line152to transmit the initialization voltage Vint to the gate electrode G1of the first transistor T1, thereby performing an initialization operation of initializing the voltage of the gate electrode G1of the first transistor T1.

The fifth transistor T5and the sixth transistor T6are simultaneously turned on depending on the emission control signal EM transmitted through the emission control line153, thereby the driving voltage ELVDD is compensated through the diode-connected first transistor T1to be transmitted to the light emitting diode ED.

The transistors T1, T2, T3, T4, T5, T6, and T7may be P-type channel transistors such as a P-type metal-oxide semiconductor (“PMOS”), and at least one of the transistors T1, T2, T3, T4, T5, T6, and T7may be an N-type channel transistor.

One end of the capacitor Cst may be connected to the gate electrode G1of the first transistor T1, and the other end thereof may be connected to the driving voltage line172. A cathode of the light emitting diode ED may be connected to a common voltage (ELVSS) terminal for transmitting a common voltage ELVSS to receive the common voltage ELVSS.

The number of transistors and the number of capacitors that are included in one pixel PX and a connection relationship thereof may be variously modified.

An operation of the display device in the exemplary embodiment will be briefly described as follows. When the scan signal GIn of the gate-on voltage level is supplied through the second scan line152during an initialization period (the scan signal GIn may be an (n−1)-th scan signal), the fourth transistor T4is turned on, the initialization voltage Vint is transmitted to the gate electrode G1of the first transistor T1through the fourth transistor T4, and the first transistor T1is initialized by the initialization voltage Vint.

Subsequently, when the scan signal GWn of the gate-on voltage level is supplied through the first scan line151during a data programming and compensation period (the scan signal GWn may be an n-th scan signal), the second transistor T2and the third transistor T3are turned on. The first transistor T1is diode-connected by the turned-on third transistor T3and is biased in a forward direction. Accordingly, a compensation voltage that is decreased by a threshold voltage Vth of the first transistor T1from the data signal Dm supplied from the data line171is applied to the gate electrode G1of the first transistor T1. The driving voltage ELVDD and the compensation voltage are respectively applied to opposite terminals of the capacitor Cst, and the capacitor Cst is charged with a charge corresponding to a voltage difference of the opposite terminals.

Next, when the emission control signal EM supplied from the emission control line153is changed from the gate-off voltage level to the gate-on voltage level during the light emission period, the fifth transistor T5and the sixth transistor T6are turned on, the driving current Id corresponding to a voltage difference between a gate voltage of the gate electrode G1of the first transistor T1and the driving voltage ELVDD is generated, and the driving current Id is supplied to the light emitting diode ED through the sixth transistor T6, thus a current Ted flows through the light emitting diode ED.

During an initialization period, the seventh transistor T7receives the scan signal GI(n+1) of the gate-on voltage level through the third scan line154to be turned on. The scan signal GI(n+1) may be the n-th scan signal. Some of the driving current Id flows out through the turned-on seventh transistor T7as a bypass current Ibp.

Hereinafter, a detailed structure of the display device in the exemplary embodiment will be described with reference toFIGS.8to12. For better understanding and ease of description, layers will be described in a stacked order in a cross-sectional view, and a planar structure thereof will be described in a description of each layer.

FIGS.8and9respectively illustrate a partial plan view of an exemplary embodiment of a first display area DA1of a display device,FIG.10illustrates a cross-sectional view taken along line X-X′ ofFIG.8,FIG.11illustrates a cross-sectional view taken along line XI-XI′ ofFIG.8, andFIG.12illustrates a plan view of an exemplary embodiment of a pixel electrode layer of a display device.FIG.9separately illustrates a portion (third conductive layer) of elements shown inFIG.8.

The planar structure shown inFIG.8is a structure for two pixels PX1and PX2neighboring in the first direction x. One pixel PX1or PX2may include the transistors T1, T2, T3_1, T3_2, T4_1, T4_2, T5, T6, and T7and the capacitor Cst that are connected to the scan lines151and152, the emission control line153, one of a pair of data lines171aand171b, and the driving voltage line172. The structure shown inFIG.8may be repeatedly arranged in the first direction x and the second direction y. The structures of two neighboring pixels PX1and PX2may be symmetric in the first direction x. Two neighboring pixels in the second direction y may have left-right reversed shapes.

The display device includes a substrate110and various layers, wires, and elements disposed thereon. In an exemplary embodiment, the substrate110may include an insulating material such as a polymer such as a polyimide, glass, or the like.

A buffer layer120, which is an insulating layer, may be disposed on the substrate110, and an active pattern130may be disposed on the buffer layer120. The active pattern130may be bent to have various shapes. The active pattern130disposed in one pixel PX1or PX2may form one continuum.

The active pattern130may include a plurality of channel regions having a semiconductor property and a plurality of conductive regions. The channel region includes channel regions131a,131b,131c_1,131c_2,131d_1,131d_2,131e,131f, and131gforming respective channels of the transistors T1, T2, T3_1, T3_2, T4_1, T4_2, T5, T6, and T7. The conductive regions disposed at opposite sides of the respective channel regions131a,131b,131c_1,131c_2,131d_1,131d_2,131e,131f, and131gmay be source regions and drain regions of corresponding transistors T1, T2, T3_1, T3_2, T4_1, T4_2, T5, T6, and T7.

In an exemplary embodiment, the active pattern130may include a semiconductor material such as amorphous silicon, polycrystalline silicon, or an oxide semiconductor.

A first insulating layer140may be disposed on the active pattern130. A first conductive layer including the scan lines151and152, the emission control line153, and a driving gate electrode155amay be disposed on the first insulating layer140.

The scan lines151and152and the emission control line153may substantially extend in the first direction x, respectively. The first scan line151may include a gate electrode155c_1protruding in the vicinity of a boundary between two adjacent pixels PX1and PX2. The third scan line154shown inFIG.7may be a scan line of the same type as the second scan line152, and may transmit a scan signal of a next stage after a scan signal transmitted by the second scan line152.

The driving gate electrode155amay be disposed in each of the pixels PX1and PX2, and may be disposed between the first scan line151and the emission control line153in a plan view.

A second insulating layer141may be disposed on the first conductive layer. A second conductive layer including the initialization voltage line161, a storage line162, and a conductive pattern163may be disposed on the second insulating layer141. The storage line162may be included in the above-described signal lines. The initialization voltage line161and the storage line162may substantially extend in the first direction x.

The initialization voltage line161may transmit the initialization voltage Vint. The storage line162may overlap most of the driving gate electrode155ain each of the pixels PX1and PX2, and an opening62may be defined in the storage line162to correspond to each of the pixels PX1and PX2. Each opening62may overlap the driving gate electrode155a. The conductive pattern163may be disposed between the initialization voltage line161and the storage line162in a plan view, and conductive patterns163respectively disposed in two adjacent pixels PX1and PX2may be connected to each other at a boundary of the two pixels PX1and PX2to form one continuum disposed to correspond to the two pixels PX1and PX2. The storage line162and the conductive pattern163may transmit the driving voltage ELVDD.

Each channel of the transistors T1, T2, T3_1, T3_2, T4_1, T4_2, T5, T6, and T7may be disposed inside one active pattern130.

The first transistor T1may include a channel region131aof the active pattern130, a source region136aand a drain region137adisposed at opposite sides of the channel region131a, and a driving gate electrode155aoverlapping the channel region131ain a plan view. The channel region131amay be bent at least once. In an exemplary embodiment, the channel region131amay have a meandering shape or a zigzag shape, and may have a vertically inverted U-shape as shown inFIG.8, for example.

The second transistor T2may include a channel region131b, a source region136band a drain region137bdisposed at opposite sides of the channel region131b, and a gate electrode155bthat is a portion of the scan line151overlapping the channel region131b. The drain region137bmay be connected to the source region136aof the first transistor T1.

The third transistor T3may be provided in two portions to prevent a leakage current. That is, the third transistor T3may include a third transistor first portion T3_1and a third transistor second portion T3_2that are connected to each other.

The third transistor first portion T3_1may include a channel region131c_1, a source region136c_1and a drain region137c_1disposed at opposite sides of the channel region131c_1, and a gate electrode155c_1which is a protruding portion of the scan line151overlapping the channel region131c_1.

The third transistor second portion T3_2may include a channel region131c_2, a source region136c_2and a drain region137c_2disposed at opposite sides of the channel region131c_2, and a gate electrode155c_2which is a portion of the scan line151overlapping the channel region131c_2. The source region136c_2of the third transistor second portion T3_2may be connected to the drain region137aof the first transistor T1, and the drain region137c_2thereof may be connected to the source region136c_1of the third transistor first portion T3_1.

The fourth transistor T4may also be provided in two portions to prevent a leakage current. That is, the fourth transistor T4may include a fourth transistor first portion T4_1and a fourth transistor second portion T4_2that are connected to each other.

The fourth transistor first portion T4_1may include a channel region131d_1, a source region136d_1and a drain region137d_1disposed at opposite sides of the channel region131d_1, and a gate electrode155d_1which is a portion of the scan line152overlapping the channel region131d_1. The drain region137d_1may be connected to the drain region137c_1of the third transistor first portion T3_1. The conductive region of the active pattern130may further include an extension137extending from a point where the drain region137d_1and the drain region137c_1of the third transistor first portion T3_1meet.

The fourth transistor second portion T4_2may include a channel region131d_2, a source region136d_2and a drain region137d_2disposed at opposite sides of the channel region131d_2, and a gate electrode155d_2which is a portion of the scan line152overlapping the channel region131d_2. The drain region137d_2may be connected to the source region136d_1of the fourth transistor first portion T4_1.

The fifth transistor T5may include a channel region131e, a source region136eand a drain region137edisposed at opposite sides of the channel region131e, and a gate electrode155ethat is a portion of the emission control line153overlapping the channel region131e. The drain region137emay be connected to the source region136aof the first transistor T1.

The sixth transistor T6may include a channel region131f, a source region136fand a drain region137fdisposed at opposite sides of the channel region131f, and a gate electrode155fthat is a portion of the emission control line153overlapping the channel region131f. The source region136fmay be connected to the drain region137aof the first transistor T1.

The seventh transistor T7includes a channel region131g, a source region136gand a drain region137gdisposed at opposite sides of the channel region131g, and a gate electrode155gthat is a portion of the scan line (the scan line152or154that is disposed at a lower portion inFIG.8) overlapping the channel region131g.

The conductive region of the active pattern130may further include an extension138extending from the source region136d_2of the fourth transistor second portion T4_2. The extension138may substantially extend in the first direction x.

The driving gate electrode155aand the storage line162overlapping each other may form the capacitor Cst capable of maintaining the voltage of the driving gate electrode155a. The second insulating layer141disposed between the driving gate electrode155aand the storage line162may function as a dielectric of the capacitor Cst.

A third insulating layer142may be disposed on the second conductive layer.

Contact holes42,43,45,47, and49disposed on the conductive region of the active pattern130may be defined in the first insulating layer140, the second insulating layer141, and the third insulating layer142. The second insulating layer141and the third insulating layer142may include a contact hole41disposed on the first conductive layer. The third insulating layer142may include contact holes44,46, and48disposed on the second conductive layer.

In an exemplary embodiment, the first insulating layer140, the second insulating layer141, and the third insulating layer142may include an inorganic insulating material such as a silicon nitride (SiNx), a silicon oxide (SiOx), and a silicon oxynitride (SiON), and/or an organic insulating material.

A third conductive layer including the driving voltage line172and connecting members72,74,75, and78may be disposed on the third insulating layer142.

The driving voltage line172may transmit the driving voltage ELVDD, and may receive the driving voltage ELVDD through a pad portion of the display device. The driving voltage line172may overlap a boundary between two adjacent pixels PX1and PX2, and it may include a portion substantially extending in the second direction y, transverse portions172adisposed in respective pixels PX1and PX2and substantially extending in the first direction x, and an extension172bconnected to ends of respective transverse portions172a.

The driving voltage line172may be electrically connected to a portion163bdisposed at the boundary between the two adjacent pixels PX1and PX2of the conductive pattern163through the contact hole46. The extension172bof the driving voltage line172may be electrically connected to the source region136eof the fifth transistor T5through the contact hole47, and may be electrically connected to the storage line162through the contact hole48. Accordingly, the source region136eof the fifth transistor T5and the storage line162may be electrically connected to the driving voltage line172to receive the driving voltage ELVDD.

The connecting member72may be electrically connected to the source region136bof the second transistor T2through the contact hole42. The connecting member72may include a portion extending in an oblique direction with respect to the first direction x and the second direction y.

The connecting member74may substantially extend in the second direction y to cross the scan line151. One end of the connecting member74may be electrically connected to the driving gate electrode155athrough the contact hole41. The contact hole42may be defined in the opening62of the storage line162. The other end of the connecting member74may be electrically connected to the extension137of the active pattern130connected to the drain region137d_1of the fourth transistor first portion T4_1and the drain region137c_1of the third transistor first portion T3_1through the contact hole43. Therefore, the drain region137d_1of the fourth transistor first portion T4_1and the drain region137c_1of the third transistor first portion T3_1may be electrically connected to the driving gate electrode155athrough the connecting member74. The connecting member74may correspond to a driving gate node GN shown inFIG.7together with the driving gate electrode155a.

The connecting member75may substantially extend in the second direction y. One end of the connecting member75may be electrically connected to the initialization voltage line161through the contact hole44, and the other end thereof may be connected to the portion (referred to as the first conductive region) of the extension138of the active pattern130connected to the drain region137gof the seventh transistor T7through the contact hole45. Accordingly, the drain region137gof the seventh transistor T7may be electrically connected to the initialization voltage line161to receive the initialization voltage Vint.

The connecting member78may be electrically connected to the drain region137fof the sixth transistor T6through the contact hole49.

A fourth insulating layer180and a fifth insulating layer181may be disposed on the third conductive layer. A contact hole87defined on the connecting member72and a contact hole88defined on the connecting member78may be defined in the fourth insulating layer180and the fifth insulating layer181.

In an exemplary embodiment, the fourth insulating layer180may include an inorganic insulating material and/or an organic insulating material, and the fifth insulating layer181may include an organic insulating material such as a polyimide, an acrylic polymer, and a siloxane polymer. In another exemplary embodiment, the fourth insulating layer180may be omitted.

A fourth conductive layer including the data lines171aand171band a connecting member79may be disposed on the fifth insulating layer181.

The data lines171aand171bcorrespond to the pair of data lines DLa and DLb described above, and they may substantially extend in the second direction y in a plan view and cross the scan lines151and152and the emission control line153. The two data lines171aand171bmay be correspondingly disposed in each of the pixels PX1and PX2. In an exemplary embodiment, a pair of data lines171aand171bmay be disposed to correspond to one pixel PX1, and a pair of data lines171aand171bmay be disposed to correspond to one pixel PX2, for example. A shape of the first data line171aat a left side and a shape of the second data line171bat a right side may be symmetrical with respect to the boundary between the two adjacent pixels PX1and PX2, and the shape of the first data line171aand the shape of the second data line171bmay be symmetrical to each other.

The data lines171aand171bmay include an extension71overlapping the connecting member72. The extension71may be electrically connected to the connecting member72through a contact hole87. Therefore, the source region136bof the second transistor T2may be electrically connected to the data lines171aand171bthrough the connecting member72to receive the data signal Dm.

The connecting member79may be electrically connected to the connecting member78of the third conductive layer through the contact hole88. In a plan view, the connecting member79may be disposed between the pair of data lines171aand171bcorresponding to the respective pixels PX1and PX2.

In an exemplary embodiment, the first conductive layer, the second conductive layer, the third conductive layer, and the fourth conductive layer may include a conductive material such as copper (Cu), aluminum (Al), molybdenum (Mo), titanium (Ti), and tantalum (Ta), or a conductive material such as a metal alloy.

A sixth insulating layer182may be disposed on the fourth conductive layer. A contact hole89defined on the connecting member79may be defined in the sixth insulating layer182. In an exemplary embodiment, the sixth insulating layer182may include an organic insulating material such as a polyacrylic-based resin, a polyimide-based resin, or the like.

A pixel electrode layer including pixel electrodes191aand191band a voltage line192may be disposed on the sixth insulating layer182. The pixel electrode layer may include a reflective or semi-transmittable conductive material.

Each of the pixel electrodes191aand191bmay correspond to each of the pixels PX1and PX2. Each of the pixel electrodes191aand191bis connected to the connecting member79and the connecting member78through the contact hole89to be electrically connected to the drain region137fof the sixth transistor T6, thereby receiving a voltage.

The arrangement of pixel electrodes191a,191b, and191cthat may be arranged in the first display area DA1is shown inFIG.12. The pixel electrodes191a,191b, and191cmay be arranged in a Pentile matrix form. The pixel electrode191aand the pixel electrode191cmay be alternately arranged in the first direction x. The pixel electrode191aand the pixel electrode191bmay be alternately arranged in a diagonal direction inclined with respect to the first direction x and the second direction y. The pixel electrode191cand the pixel electrode191bmay be arranged alternately in another diagonal direction. The pixel electrode191amay be smaller than the pixel electrode191c, and the pixel electrode191bmay be smaller than the pixel electrode191a. The pixel electrode191amay be a pixel electrode of the red pixel R, the pixel electrode191bmay be a pixel electrode of the green pixel G, and the pixel electrode191cmay be a pixel electrode of the blue pixel B. The arrangement and shape of the pixel electrodes191a,191b, and191cmay be variously changed.

Each of the voltage lines192may substantially extend in the first direction x and may be bent along edges of the pixel electrodes191a,191b, and191c. The voltage lines192may cross the data lines171aand171b. The voltage lines192may be connected to a wire that may be disposed in the non-display area NA, and may transmit a constant voltage such as the initialization voltage Vint, the driving voltage ELVDD, and the common voltage ELVSS.

The voltage line192may overlap at least a portion of the channel region131c_1of the third transistor first portion T3_1and at least a portion of the channel region131d_1of the fourth transistor first portion T4_1. Accordingly, external light is blocked from being incident on the channel region131c_1of the third transistor first portion T3_1and the channel region131d_1of the fourth transistor first portion T4_1, which are directly connected to the driving gate electrode155a, thereby preventing a leakage current from occurring. In addition, since a voltage variation at the driving gate electrode155adue to the external light may be prevented, it is possible to prevent display defects such as a luminance change of an image and a color coordinate variation.

A seventh insulating layer350may be disposed on the pixel electrode layer. An opening355overlapping each of the pixel electrodes191a,191b, and191cmay be defined in the seventh insulating layer350.

A light emitting layer370may be disposed on the pixel electrodes191a,191b, and191c. The light emitting layer370may include an organic light emitting material or an inorganic light emitting material.

A common electrode270may be disposed on the light emitting layer370. The common electrode270is also disposed on the seventh insulating layer350, and may extend over the pixels PX1and PX2. The common electrode270may transmit the common voltage ELVSS.

The pixel electrodes191a,191b, and191c, the light emitting layer370, and the common electrode270together form the light emitting diode ED. The pixel electrodes191a,191b, and191cmay be anodes of the light emitting diode ED, and the common electrode270may be a cathode of the light emitting diode ED.

An encapsulation layer for protecting the light emitting diode ED may be disposed on the common electrode270, and the encapsulation layer may include at least one inorganic layer and may further include at least one organic layer.

The relationship between the connecting member75for transmitting the initialization voltage Vint and the data lines171aand171bwill be described below. The data lines171aand171bmay include a bent portion71abent in the direction away from the connecting member75in the vicinity of the connecting member75. By disposing the data lines171aand171bin the fourth conductive layer which is different from the third conductive layer in which the connecting member75is disposed, the data lines171aand171bmay be further separated from the connecting member75. Accordingly, a parasitic capacitance between the connecting member75and the data lines171aand171bmay be reduced, and coupling between the initialization voltage Vint and the data signal Dm may be prevented, thereby preventing defective display such as horizontal line spot.

The conductive pattern163may include a shielding portion163adisposed between the connecting member75and the data lines171aand171b. The shielding portion163amay overlap a portion (referred to as the second conductive region) disposed between the data lines171aand171band the connecting member75of the extension138of the active pattern130which is electrically connected to the connecting member75and transmits the initialization voltage Vint, and thus may shield between the data lines171aand171band the extension138of the active pattern130. Therefore, the coupling between the data signal Dm and the initialization voltage Vint, which the data lines171aand171btransmit, may be further prevented.

A constant voltage other than the initialization voltage Vint, for example, the driving voltage ELVDD or the common voltage ELVSS, is applied to the voltage line192disposed in the pixel electrode layer, so that the coupling between the data signal Dm and the initialization voltage Vint may be further reduced by overlapping of the voltage line192(which crosses the data lines171aand171b) and the data lines171aand171b.

Now, a specific structure of the second display area DA2of the display device will be described with a focus on differences from the exemplary embodiment described above with reference toFIGS.13and14.

FIGS.13and14respectively illustrate a partial plan view of an exemplary embodiment of a second display area DA2of a display device.FIG.13illustrates a planar structure of the second pixel area PA2, andFIG.14illustrates a planar structure of the transmission area TA.

FIG.13illustrates two adjacent pixels PX1and PX2disposed in the second pixel area PA2of the second display area DA2, which are substantially the same as the pixel structure shown inFIG.8. However, only one data line171aor171bis correspondingly disposed in each pixel PX1or PX2. That is, only the first data line171aof the pair of data lines171aand171bis disposed in the pixel PX1, and only the second data line171bof the pair of data lines171aand171bis disposed in the pixel PX2. The pixel PX1may receive the data signal Dm from the first data line171a, and the pixel PX2may receive the data signal Dm from the second data line171b.

The pixels PX1and PX2shown inFIG.13are, for example, pixels of the pixel columns Ciand Ci+1as shown inFIG.5. In an alternative exemplary embodiment, when the pixels PX1and PX2are pixels of the pixel columns (e.g., Ci+1and Ci+2inFIG.5) that receive the data signal Dm from the second data line171bof the pair of data lines171aand171b, only the second data line171bmay be disposed in the pixels PX1and PX2. When the pixel PX1is a pixel of a pixel column (e.g., Ci+2inFIG.5) that receives the data signal from the second data line171band the pixel PX2is a pixel of a pixel column (e.g., Ci+3inFIG.5) that receives the data signal Dm from the first data line171a, only the second data line171bis disposed in the pixel PX1and only the first data line171ais disposed in the pixel PX2.

FIG.14illustrates an area corresponding to approximately two pixels in the transmission area TA of the second display area DA2. A structure of the transmission area TA is substantially the same as that shown inFIG.8, but only one of of the pair of data lines171aand171bis correspondingly disposed at each of adjacent pixel columns (for example, Ci+2and Ci+3inFIG.5). In addition, the pixel electrodes191a,191b, and191cshown inFIGS.8and12may not be disposed in the transmission area TA. As such, by excluding the conductive layers that may lower the transmittance of the transmission area TA from the transmission area TA, the transmittance of the transmission area TA may be improved.

In order to further improve the transmittance of the transmission area TA, it may be advantageous to eliminate both of the pair of data lines171aand171b, but in this case, the data signal Dm cannot be transmitted to a pixel disposed above the transmission area TA. When the pixel is not disposed above the transmission area TA, both data lines171aand171bmay not be disposed.

Unlike the shown structure, when two adjacent pixels disposed below or above the transmission area TA are pixels of two pixel columns (for example, Ciand Ci+1inFIG.5) that sequentially receive the data signal Dm from the first data line171aand the second data line171bfrom the left, only the first data line171aor the second data line171bmay be disposed in the transmission areas TA of the corresponding pixel columns. When two adjacent pixels disposed below or above the transmission area TA are pixels of two pixel columns (for example, Ci+1and Ci+2inFIG.5) that receive the data signal Dm from the second data line171b, only the second data line171bmay be disposed in the transmission areas TA of the corresponding pixel columns.

In the pixel electrode layer, the pixel electrodes191a,191b, and191cmay be removed from the transmission area TA, as described above. However, the voltage line192is desired to be substantially and continuously provided in the first direction x across the second pixel area PA2adjacent to the left and right of the transmission area TA so that the voltage transmitted through the voltage line192may be applied to the pixels of the pixel column. Thus, the voltage line192may also be provided in the transmission area TA. In this case, when the voltage line192is not provided in the zigzag shape as shown inFIG.8but most of the voltage line192is provided to overlap the second scan line152as shown inFIG.14, a decrease in transmittance due to the voltage line192may be minimized. In the area where the second scan line152is disposed, since light is previously blocked by the second scan line152, it is advantageous to improve the transmittance of the transmission area TA by forming the voltage line192to overlap the conductive layer. In the transmission area TA, the voltage line192may be provided to overlap another signal line substantially extending in the first direction x, for example, the first scan line151, in addition to the second scan line152.

Finally, an exemplary embodiment of a display device and a driving method thereof will be described with reference toFIGS.15and16together with the above-described drawings.

FIG.15illustrates an exemplary embodiment of a circuit diagram of a circuit connected to a data line of a display device, andFIG.16illustrates a waveform diagram of an exemplary embodiment of a driving signal of a display device.

Referring toFIG.15, the display device in the exemplary embodiment includes a data driver400for applying the data signal Dm. The data driver400may be connected to the data lines171aand171b, and may output the data signal Dm to the data lines171aand171b.

The display area DA may include the pixels R, G, and B, the data lines171aand171b, and scan lines151_1and151_2. Each of the scan lines151_1and151_2may correspond to the scan line151described above.

The pixels R, G, and B may be connected to the corresponding data lines171aand171band the corresponding scan lines151_1and151_2, respectively. A transistor connected to the data line171aor171band the scan line151_1or151_2in each of the pixels R, G, and B may be the second transistor T2described above.

When the pixels R, G, and B are substantially arranged in a matrix form, the pair of data lines171aand171bmay be disposed in each of the pixel columns C1, C2, C3, . . . , C8to be connected to the pixels R, G, and B of the corresponding pixel columns C1, C2, C3, . . . , C8. The pixels R, G, and B of each of the pixel columns C1, C2, C3, . . . , C8may be alternately connected to the pair of data lines171aand171b.

A demultiplexer circuit including transmission gate lines TG1, TG2, TG3, and TG4and switching elements Q may be disposed between the data driver400and the display area DA. The transmission gate lines TG1, TG2, TG3, and TG4may transmit a transmission gate signal, and may cross the data lines171aand171b. Each of the data lines171aand171bis connected to a switching element Q connected to at least one of the transmission gate lines TG1, TG2, TG3and TG4, and then, when a gate-on voltage is applied to the transmission gate lines TG1, TG2, TG3, and TG4, the data signal Dm from the data driver400may be applied to the corresponding data lines171aand171b.

Referring toFIGS.15and16, when a gate-on voltage Von (here, a low level) is applied to the transmission gate line TG1during about half (H/2) of a horizontal period in a first period P1, the data lines171aand171bconnected to the switching element Q connected to the transmission gate line TG1are charged with a voltage of the data signal Dm.

Then, when the gate-on voltage Von is applied to the transmission gate line TG2during about half (H/2) of the horizontal period in a second period P2, the data lines171aand171bconnected to the switching element Q connected to the transmission gate line TG2are charged with the voltage of the data signal Dm. Similarly, the gate-on voltage Von may be sequentially applied to the transmission gate line TG3and the transmission gate line TG4in a third period P3and a fourth period P4, respectively.

Then, when the gate-on voltage Von is applied to the scan line151_1during about one horizontal period1H in the third period P3and the fourth period P4, the voltages charged in the corresponding data lines171aand171bare applied to the pixels R, G, and B of pixel groups PG1and PG2connected to the data lines171aand171bconnected through the transmission gate lines TG1and TG2and the switching elements Q while being connected to the scan line151_1.

Then, when the gate-on voltage Von is applied to the scan line151_2during about one horizontal period1H in a fifth period P5and a sixth period P6, the voltages charged in the corresponding data lines171aand171bare applied to the pixels R, G, and B of pixel groups PG3and PG4connected to the data lines171aand171bconnected through the transmission gate lines TG3and TG4and the switching elements Q while being connected to the scan line151_2.

According to the above-described driving method, since there is a period in which the data voltage is first charged in one of the data lines171aand171band the data voltage is charged in the other of data lines171aand171bin a state of being floated from the data driver400, a ripple of the initialization voltage Vint coupled with the data signal Dm of the data lines171aand171baffects data voltages of the other of the data lines171aand171bin a floating state, which may result in display defects such as horizontal line spots. However, the display device in the exemplary embodiments may prevent the coupling between the initialization voltage Vint and the data signal Dm to prevent the display defects as described above.

While this invention has been described in connection with what is presently considered to be practical embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.