Patent ID: 12217972

DETAILED DESCRIPTION

The following embodiments describe systems and methods for multi-state pulsing for achieving a balance between bow control and mask selectivity. It will be apparent that the present embodiments may be practiced without some or all of these specific details. In other instances, well known process operations have not been described in detail in order not to unnecessarily obscure the present embodiments.

FIG.1is a diagram of an embodiment of a system100to illustrate three-state pulsing of multiple radiofrequency (RF) signals to achieve the balance between bow control and mask selectivity. The system100includes an RF generator RFGx, another RF generator RFGy, an impedance matching network IMN, a plasma chamber106, and a host computer110.

An example of the RF generator RFGx is a low frequency RF generator, such as an RF generator having an operating frequency of 400 kilohertz (kHz) or 2 megahertz (MHz), or 13.56 MHz. An example of the RF generator RFGy is a high frequency RF generator, such as an RF generator having an operating frequency of 27 MHz or 60 MHz. It should be noted that the operating frequency of the high frequency RF generator is greater than the operating frequency of the low frequency RF generator.

The impedance matching network IMN is a network of circuit components, such as inductors, capacitors, and resistors. For example, the impedance matching network is a circuit that includes a shunt capacitor and a series capacitor. The shunt capacitor is coupled to the series capacitor at one end of the shunt capacitor and an opposite end of the shunt capacitor is coupled to a ground potential. The series capacitor is coupled between an input, such as an input I2x or an input I2y, of the impedance matching network IMN and an output O2 of the impedance matching network IMN. As another example, one or more circuit components of the impedance matching network IMN are coupled in series or in parallel to one or more circuit components of the impedance matching network IMN. The impedance matching network IMN has a branch including one or more circuit components and the branch is coupled between the input I2x and the output O2. Similarly, the impedance matching network IMN has another branch including one or more circuit components and the branch is coupled between the input I2y and the output O2.

The plasma chamber106includes a substrate support104, such as a chuck. The chuck includes a lower electrode embedded within the chuck, a facility plate located below the lower electrode, and a ceramic plate located over the lower electrode. The plasma chamber106further includes an upper electrode118, which is coupled to the ground potential. Examples of the host computer110include a desktop computer, a laptop computer, a controller, a tablet, and a smartphone.

The RF generator RFGx includes a digital signal processor (DSP) DSPx, a power controller PWRS1x, another power controller PWRS2x, yet another power controller PWRS0x, an auto frequency tuner (AFT) AFTx, and a power supply PSx. Examples of a DSP, as used herein, include a controller that includes a microprocessor, an application specific integrated circuit (ASIC), or a programmable logic device (PLD). The controller of the DSP also includes a memory device that is able to fetch multiple data or instructions at the same time. The memory device of the DSP is coupled to the microprocessor, the ASIC, or the PLD of the DSP. Examples of a memory device, as used herein, include a read-only memory (ROM), a random access memory (RAM), a flash memory, a storage disk array, a hard disk, etc.

An example of a power controller, as used herein, includes a microcontroller. To illustrate, the power controller includes a microprocessor, an ASIC, or a PLD. The power controller further includes a memory device that is coupled to the microprocessor, the ASIC, or the PLD of the power controller.

An example of a tuner, as used herein, includes a microcontroller. To illustrate, the tuner includes a microprocessor, an ASIC, or a PLD. The tuner further includes a memory device that is coupled to the microprocessor, the ASIC, or the PLD of the tuner.

An example of a power supply, as used herein, includes an electronic oscillator or an RF oscillator that produces a periodic, oscillating electronic signal, such as a sine wave RF signal.

The digital signal processor DSPx is coupled to the power controllers PWRS1x, PWRS2x, and PWRS0x, and to the auto frequency tuner AFTx. Moreover, each of the power controllers PWRS1x, PWRS2x, and PWRS0x is coupled to the power supply PSx. Also, the auto frequency tuner AFTSx is coupled to the power supply PSx.

The RF generator RFGy includes a digital signal processor DSPy, a power controller PWRS1y, another power controller PWRS2y, yet another power controller PWRS0y, an auto frequency tuner AFTy, and a power supply PSy. The digital signal processor DSPy is coupled to the power controllers PWRS1y, PWRS2y, and PWRS0y, and to the auto frequency tuner AFTy. Moreover, each of the power controllers PWRS1y, PWRS2y, and PWRS0y is coupled to the power supply PSy. Also, the auto frequency tuner AFTSy is coupled to the power supply PSy.

The host computer includes a processor112and a memory device114. The processor112is coupled to the memory device114. Examples of a processor, as used herein, include a microprocessor, an ASIC, a central processing unit (CPU), or a PLD.

The processor112is coupled via a transfer cable120xto the digital signal processor DSPx and is coupled via another transfer cable120yto the digital signal processor DSPy. Examples of a transfer cable, as used herein, include a parallel transfer cable for facilitating a parallel transfer of data between the processor112and a DSP, a serial transfer cable for facilitating a transfer of data in series between the processor112and the DSP, and a universal serial bus (USB) transfer cable that facilitates a transfer of data between the processor112and the DSP by applying an USB standard.

The power supply PSx is coupled via an RF cable102xto the input I2x of the impedance matching network IMN. For example, an output O1x of the RF generator RFG x is coupled via the RF cable120xto the input I2x. Moreover, the power supply PSy is coupled via an RF cable102yto the input I2y of the impedance matching network IMN. For example, an output O1y of the RF generator RFGy is coupled via the RF cable120yto the input I2y.

The output O2 of the impedance matching network IMN is coupled via an RF transmission line122to the lower electrode of the substrate support104. An example of the RF transmission line122includes a conductor that is surrounded by an insulator that is surrounded by an RF sleeve, such as an aluminum solid bar. The insulator can be a dielectric material, such as Teflon™. Another example of the RF transmission line122includes the conductor that is coupled via one or more RF straps to an RF cylinder having an inner conductive rod and an outer housing. The inner conductive rod of the RF cylinder is coupled to the lower electrode. As described in the preceding example, the conductor is surrounded by the insulator that is surrounded by the RF sleeve. The conductor of the RF transmission line122is coupled to the output O2 of the impedance matching network IMN.

The processor112generates a clock signal and a digital pulsed signal108in synchronization with the clock signal. Examples of the clock signal and the digital pulsed signal108are provided below. The digital pulsed signal108has three states, such as a state S1, a state S2, and a state S0, which are illustrated below.

The processor112accesses, such as reads or obtains, from the memory device114, a power level for the state S1of an RF signal102xto be generated by the RF generator RFGx, a power level for the state S2of the RF signal102x, and a power level for the state S0of the RF signal102x. Moreover, the processor112accesses from the memory device114a power level for the state S1of an RF signal102yto be generated by the RF generator RFGy, a power level for the state S2of the RF signal102y, a power level for the state S0of the RF signal102y. Each RF signal102xand102yis a sinusoidal signal.

It should be noted that in one embodiment, a power level of an RF signal for a state is a power level that is achieved by the RF signal during the state. For example, a power level for a state S1of the RF signal is the power level that is achieved during an instance of the state S1of the digital pulsed signal108, a power level for a state S2of the RF signal is the power level that is achieved during an instance of the state S2of the digital pulsed signal108, and a power level for a state S0of the RF signal is the power level that is achieved during an instance of the state S0of the digital pulsed signal108.

The processor112sends the power levels for the states S1, S2, and S0of the RF signal102xto be generated, via the transfer cable120xto the digital signal processor DSPx within an identity of each of the states S1, S2, and S0. Upon receiving the power levels for the states S1, S2, and S0of the RF signal102xwith the identities of the states S1, S2, and S0, the digital signal processor DSPx accesses from a memory device of the digital signal processor DSPx a correspondence, such as a one-to-one mapping or a link or a one-to-one relationship, between the identities of the states S1through S0and the power controllers PWRS1x, PWRS2x, and PWRS0x, and sends the power level for the state S1to the power controller PWRS1x, sends the power level for the state S2to the power controller PWRS2x, and sends the power level for the state S0to the power controller PWRS0x. Each power controller PWRS1x, PWRS2x, and PWRS0x stores a respective power level received from the digital signal processor DSPx in a memory device of the power controller.

Similarly, the processor112sends the power levels for the states S1, S2, and S0of the RF signal102yto be generated via the transfer cable120yto the digital signal processor DSPy within the identity of each of the states S1, S2, and S0. Upon receiving the power levels for the states S1, S2, and S0of the RF signal102ywith the identities of the states S1, S2, and S0, the digital signal processor DSPy accesses from a memory device of the digital signal processor DSPy a correspondence, such as a one-to-one mapping or a link or a one-to-one relationship, between the identities of the states S1, S2, and S0and the power controllers PWRS1y, PWRS2y, and PWRS0y, and sends the power level for the state S1to the power controller PWRS1y, sends the power level for the state S2to the power controller PWRS2y, and sends the power level for the state S0to the power controller PWRS0y. Each power controller PWRS1y, PWRS2y, and PWRS0y stores a respective power level received from the digital signal processor DSPy in a memory device of the power controller.

The processor112sends the digital pulsed signal108via the transfer cable120xto the digital signal processor DSPx and simultaneously sends the digital pulsed signal108via the transfer cable120yto the digital signal processor DSPy. In response to receiving the digital pulsed signal108, the digital signal processor DSPx identifies a state of the digital pulsed signal108from a logic level of the digital pulsed signal108. For example, the digital signal processor DSPx identifies a state of the digital pulsed signal108to be S1upon determining that the logic level of the digital pulsed signal108is zero, identifies a state of the digital pulsed signal108to be S2upon determining that the logic level of the digital pulsed signal108is one, and identifies a state of the digital pulsed signal108to be S0upon determining that the logic level of the digital pulsed signal108is two.

During the state S1of the digital pulsed signal108, upon identifying the state of the digital pulsed signal108to be S1, the digital signal processor DSPx sends a control signal to the power controller PWRS1x. In response to receiving the control signal during the state S1of the digital pulsed signal108, the power controller PWRS1x accesses the power level for the state S1from the memory device of the power controller PWRS1x, generates a signal including the power level for the state S1, and sends the signal to the power supply PSx. During the state S1of the digital pulsed signal108, in response to receiving the signal including the power level for the state S1from the power controller PWRS1x, the power supply PSx generates a portion of the RF signal102xhaving the power level for the state S1.

Similarly, during the state S2of the digital pulsed signal108, upon identifying the state of the digital pulsed signal108to be S2, the digital signal processor DSPx sends a control signal to the power controller PWRS2x. Upon receiving the control signal during the state S2of the digital pulsed signal108, the power controller PWRS2x accesses the power level for the state S2from the memory device of the power controller PWRS2x, generates a signal including the power level for the state S2, and sends the signal to the power supply PSx. During the state S2of the digital pulsed signal108, in response to receiving the signal having the power level for the state S2from the power controller PWRS1x, the power supply PSx transitions the RF signal102xfrom the power level for the state S1to the power level for the state S2to generate a portion of the RF signal102xhaving the power level for the state S2.

Also, during the state S0of the digital pulsed signal108, upon identifying the state of the digital pulsed signal108to be S0, the digital signal processor DSPx sends a control signal to the power controller PWRS0x. Upon receiving the control signal during the state S0of the digital pulsed signal108, the power controller PWRS0x accesses the power level for the state S0from the memory device of the power controller PWRS0x, generates a signal including the power level for the state S0, and sends the signal to the power supply PSx. During the state S0of the digital pulsed signal108, in response to receiving the signal having the power level for the state S0from the power controller PWRS0x, the power supply PSx transitions the RF signal102xfrom the power level for the state S2to the power level for the state S0to generate a portion of the RF signal102xhaving the power level for the state S0.

In a similar manner, in response to receiving the digital pulsed signal108, the digital signal processor DSPy identifies a state of the digital pulsed signal108from a logic level of the digital pulsed signal108in the same manner, described above, in which the digital signal processor DSPx identifies the state of the digital pulsed signal108. For example, the digital signal processor DSPy identifies a state of the digital pulsed signal108to be S1upon determining that the logic level of the digital pulsed signal108is zero, identifies a state of the digital pulsed signal108to be S2upon determining that the logic level of the digital pulsed signal108is one, and identifies a state of the digital pulsed signal108to be S0upon determining that the logic level of the digital pulsed signal108is two.

During the state S1of the digital pulsed signal108, upon identifying the state of the digital pulsed signal108to be S1, the digital signal processor DSPy sends a control signal to the power controller PWRS1y. Also, upon receiving the control signal during the state S1of the digital pulsed signal108, the power controller PWRS1y accesses the power level for the state S1from the memory device of the power controller PWRS1y, generates a signal including the power level for the state S1, and sends the signal to the power supply PSy. During the state S1of the digital pulsed signal108, in response to receiving the signal having the power level for the state S1from the power controller PWRS1y, the power supply PSy generates a portion of the RF signal102yhaving the power level for the state S1.

Similarly, during the state S1of the digital pulsed signal108, upon identifying the state of the digital pulsed signal108to be S2, the digital signal processor DSPy sends a control signal to the power controller PWRS2x. Upon receiving the control signal during the state S2of the digital pulsed signal108, the power controller PWRS2y accesses the power level for the state S2from the memory device of the power controller PWRS2y, and generates a signal including the power level for the state S2, and sends the signal to the power supply PSy. During the state S2of the digital pulsed signal108, in response to receiving the signal having the power level for the state S2from the power controller PWRS1y, the power supply PSy transitions the RF signal102yfrom the power level for the state S1to the power level for the state S2to generate a portion of the RF signal102yhaving the power level for the state S2.

Also, during the state S0of the digital pulsed signal108, upon identifying the state of the digital pulsed signal108to be S0, the digital signal processor DSPy sends a control signal to the power controller PWRS0y. In response to receiving the control signal during the state S0of the digital pulsed signal108, the power controller PWRS0y accesses the power level for the state S0from the memory device of the power controller PWRS0y, generates a signal including the power level for the state S0, and sends the signal to the power supply PSy. During the state S0of the digital pulsed signal108, in response to receiving the signal having the power level for the state S0from the power controller PWRS0y, the power supply PSy transitions the RF signal102yfrom the power level for the state S2to the power level for the state S0to generate a portion of the RF signal102yhaving the power level for the state S0.

The RF signal102xis supplied by the power supply PSx via the output O1x and the RF cable116xto the input I2x of the impedance matching network IMN. Also, the RF signal102yis supplied by the power supply PSy via the output O1y and the RF cable116yto the input I2y of the impedance matching network IMN. The impedance matching network IMN receives the RF signal102xat the input I2x, and as the RF signal102xis transferred via the branch circuit of the impedance matching network IMN that is coupled to the input I2x, an impedance of the RF signal RF102xis modified by the branch circuit to output a first modified RF signal. Similarly, the impedance matching network IMN receives the RF signal102xat the input I2y and as the RF signal102yis transferred via the branch circuit of the impedance matching network IMN that is coupled to the input I2y, an impedance of the RF signal RF102yis modified by the branch circuit to output a second modified RF signal. The impedances of the RF signals102xand102yare modified to match an impedance of a load coupled to the output O2 with an impedance of a source coupled to the inputs I2x and I2y. An example of the load coupled to the output O2 includes the RF transmission line122and the plasma chamber106. An example of the source coupled to the inputs I2x and I2y include the RF cables116xand116yand the RF generators RFGx and RFGy. The branch circuit coupled to the input I2x is connected at the output O2 to the branch circuit coupled to the input I2y to combine the first and second modified RF signals to output a combined modified RF signal124at the output O2.

The combined modified RF signal124is sent via the RF transmission line122from the output O2 of the impedance matching network IMN to the lower electrode of the substrate support104. In addition, one or more process gases, such as a fluorine containing gas, or an oxygen containing gas, or a combination thereof, are supplied to a gap between the upper electrode118and the substrate support104within the plasma chamber106. When the combined modified RF signal124and the one or more process gases are simultaneously supplied to the plasma chamber106, plasma is stricken or maintained within the gap to process a substrate S. Examples of the substrate S include a semiconductor wafer that is formed on a substrate layer, and a substrate stack that is formed on a substrate layer. Examples of processing the substrate S include depositing one or more materials, such as an oxide layer, a nitride layer, a silicon nitride layer, a mask layer, or a combination of two or more thereof, on a substrate layer. Other examples of processing the substrate include etching the substrate S or sputtering the substrate S or cleaning the substrate S.

In one embodiment, the lower electrode of the substrate support104is coupled to the ground potential and the upper electrode118is coupled to the output O2 of the impedance matching network IMN.

In an embodiment, one or more RF generators are coupled via an impedance matching network to the upper electrode118in addition to the RF generators RFGx and RFGy being coupled via the impedance matching network IMN to the lower electrode of the substrate support104.

In one embodiment, the functions or operations described herein as being performed by one or more of the digital signal processor DSPx, the power controller PWRS1x, the power controller PWRS2x, the power controller PWRS0x, and the auto frequency tuner AFTSx are performed by a controller or a processor of the RF generator RFGx. For example, functions described herein as being performed by the power controller PWRS1x, the power controller PWRS2x, the power controller PWRS0x, and the auto frequency tuner AFTx are performed by the digital signal processor DSPx.

Similarly, in an embodiment, functions or operations described herein as being performed by one or more of the digital signal processor DSPy, the power controller PWRS1x, the power controller PWRS2y, the power controller PWRS0y, and the auto frequency tuner AFTSy are performed by a controller or a processor of the RF generator RFGy. For example, functions described herein as being performed by the power controller PWRS1y, the power controller PWRS2y, the power controller PWRS0y, and the auto frequency tuner AFTy are performed by the digital signal processor DSPy.

In an embodiment, functions or operations described herein as being performed by one or more of the digital signal processor DSPx, the power controller PWRS1x, the power controller PWRS2x, the power controller PWRS0x, the auto frequency tuner AFTSx, the digital signal processor DSPy, the power controller PWRS1y, the power controller PWRS2y, the power controller PWRS0y, and the auto frequency tuner AFTSy are performed by the processor112.

In one embodiment, the clock signal is generated by a clock source instead of the processor112.

FIG.2Ais an embodiment of a graph202of a clock signal204, which is the clock signal described above. The clock signal204is generated by the processor112. The graph202plots a logic level on a y-axis and a time t on an x-axis. The y-axis of the graph202includes a logic level 0 and a logic level 1. The x-axis of the graph202includes multiple times t0, t1, t2, t3, t4, and t5.

A time interval between any two consecutive times on the x-axis of the graph202is the same. For example, a time interval between the times t0 and t1 is equal to a time interval between the times t1 and t2, and the time interval between the times t1 and t2 is equal to a time interval between the times t2 and t3. The time interval between times t3 and t4 is equal to a time interval between the times t2 and t3, and the time interval between times t4 and t5 is equal to a time interval between the times t3 and t4. The time t1 is consecutive to the time t0. Similarly, the time t2 is consecutive to the time t1, the time t3 is consecutive to the time t2, the time t4 is consecutive to the time t3, and the time t5 is consecutive to the time t4.

The clock signal204periodically transitions between the logic levels 0 and 1. For example, during a first half of a cycle1of the clock signal204, the clock signal204is at the logic level 1. At the time t1, the clock signal204transitions from the logic level 1 to the logic level 0. During a second half of the cycle1of the clock signal204, the clock signal204has the logic level 0. At the time t2, the clock signal204transitions from the logic level 0 to the logic level 1. During a first half of a cycle2of the clock signal204, the clock signal204is at the logic level 1. At the time t3, the clock signal204transitions from the logic level 1 to the logic level 0. During a second half of the cycle2of the clock signal204, the clock signal is that the logic level 0. At the time t4, the clock signal204transitions from the logic level 0 to the logic level 1.

The cycle2of the clock signal204is consecutive to the cycle1of the clock signal204. For example, there are no other clock cycles between the cycles1and2of the clock signal204. The cycle1occurs from the time t0 to the time t2 and the cycle2occurs from the time t2 to the time t4.

FIG.2Bis a diagram of an embodiment of a graph206to illustrate an embodiment of a digital pulsed signal208. The digital pulsed signal208is an example of the digital pulsed signal108ofFIG.1. The graph206plots a logic level of the digital pulsed signal208on a y-axis and the time t on an x-axis. The y-axis of the graph206includes the logic levels 0, 1, and 2. The x-axis of the graph206includes the time t0, a time t0a, a time t0b, the time t1, the time t2, a time t2a, a time t2b, and the times t3 and t4. The time t0a occurs between the times t0 and t0b, and the time t0b occurs between the times t0a and t1. Moreover, the time t2a occurs between the times t2 and t2b and the time t2b occurs between the times t2a and t3.

The digital pulsed signal208periodically transitions among its states S1, S2, and S0. For example, the digital pulsed signal208has the state S1, which is defined by the logic level 0, from the time t0 to the time t0a. To illustrate, during the state S1of the digital pulsed signal208, the digital pulsed signal208is at the logic level 0. The digital pulsed signal208transitions from the logic level 0 to the logic level 1 at the time t0a. The state S2of the digital pulsed signal208is defined by the logic level 1. To illustrate, during the state S2of the digital pulsed signal208, the digital pulsed signal208is at the logic level 1.

The digital pulsed signal208has the state S2from the time t0a to the time t0b. At the time t0b, the digital pulsed signal208transitions from the state S2to the state S0, which is defined by the logic level 2. To illustrate, during the state S0of the digital pulsed signal208, the digital pulsed signal208is at the logic level 2. The digital pulsed signal208has the state S0from the time t0b to the time t2. At the time t2, the digital pulsed signal208transitions from the state S0back to the state S1.

The digital pulsed signal208has the state S1from the time t2 to the time t2a. The digital pulsed signal208transitions from the state S1to the state S2at the time t2a. The digital pulsed signal208has the state S2from the time t2a to the time t2b. At the time t2b, the digital pulsed signal208transitions from the state S2to the state S0. The digital pulsed signal208has the state S0from the time t2b to the time t4. At the time t4, the digital pulsed signal208transitions from the state S0back to the state S1.

It should be noted that multiple instances of each of the states S1, S2, and S0of the digital pulsed signal208occur. For example, a first instance of the state S1of the digital pulsed signal208occurs between the times t0 and t0a, and a second instance of the state S1of the digital pulsed signal208occurs between the times t2 and t2a. As another example, a first instance of the state S2of the digital pulsed signal208occurs between the times t0a and t0b, and a second instance of the state S2of the digital pulsed signal208occurs between the times t2a and t2b. As yet another example, a first instance of the state S0of the digital pulsed signal208occurs between the times t0b and t2, and a second instance of the state S0of the digital pulsed signal208occurs between the times t2a and t4. As another example, the first instance of the state S2of the digital pulsed signal208is consecutive to the first instance of the state S1of the digital pulsed signal208and the first instance of the state S0of the digital pulsed signal208is consecutive to the first instance of the state S2of the digital pulsed signal208. The second instance of the state S1of the digital pulsed signal208is consecutive to the first instance of the state S0of the digital pulsed signal208. Also, the second instance of the state S2of the digital pulsed signal208is consecutive to the second instance of the state S1of the digital pulsed signal208and the second instance of the state S0of the digital pulsed signal208is consecutive to the second instance of the state S2of the digital pulsed signal208.

FIG.2Cis an embodiment of a graph210to illustrate an embodiment of an RF signal212generated by the RF generator RFGx (FIG.1) and an embodiment of an RF signal214generated by the RF generator RFGy (FIG.1). The RF signal212is an example of the RF signal102x(FIG.1), and the RF signal214is an example of the RF signal102y(FIG.1).

The RF signals212and214are synchronized to the digital pulsed signal208. For example, each of the RF signals212and214initiate a transition from the state S1to the state S2at the time t0a of transition of the digital pulsed signal208from the state S1the state S2. As another example, each of the RF signals212and214initiate a transition from the state S2to the state S0at the time t0b of transition of the digital pulsed signal208from the state S2the state S0. As yet another example, each of the RF signals212and214initiate a transition from the state S0to the state S1at the time t2 of transition of the digital pulsed signal208from the state S0the state S1.

The graph210plots power levels of the RF signals212and214. For example, the y-axis of the graph210includes power levels P0, P1, P2, P3, and P4. The power level P1 is greater than the power level P0. Also, the power level P2 is greater than the power level P1 and the power level P3 is greater than the power level P2. The power level P4 is greater than the power level P3.

A power level, as used herein, is an envelope, such as a peak-to-peak amplitude, of an RF signal. For example, the power levels P4, P2, and P0 are envelopes of the RF signal102xand the power levels P1, P3, and P0 are envelopes of the RF signal102y. As another example, a power level includes one or more peak-to-peak power values that are within a predetermined range from the power level, such as greater than or less than a value of the power level. As yet another example, the power level is a statistical value, such as an average or a median, of all the peak-to-peak power values of the power level. As another example, the power level is a highest of all peak-to-peak power values of the power level. As yet another example, the power level is a lowest of all peak-to-peak power values of the power level.

Also, a first power level is different from a second power level. For example, one or more power values of the power level P0 are exclusive of one or more power values of the power level P1 and one or more power values of the power level P2 are exclusive of the one or more power values of each of the power levels P0 and P1.

Also, the graph210plots the time t on an x-axis. For example, the x-axis of the graph210includes the times t0, t0a, t0b, t1, t2, t2a, t2b, t3, and t4.

The RF signal212periodically transitions among the states S1, S2, and S0of the RF signal212in a manner described below. Similarly, the RF signal214periodically transitions among the states S1, S2, and S0of the RF signal214in a manner described below

The state S1of the RF signal212is defined by the power level P4. For example, during the state S1of the digital pulsed signal208or the RF signal212, the RF signal212has the power level P4.

The RF signal212transitions from the state S1to the state S2within a time window from the time t0a. The state S2of the RF signal212is defined by the power level P2. For example, during the state S2of the digital pulsed signal208or the RF signal212, the RF signal212has the power level P2.

It should be noted that an RF signal, described herein, does not transition from one state to a consecutive state instantaneously. For example, a transition of the RF signal212from the state S1to the state S2is not instantaneous. To illustrate, the transition of the RF signal212from the state S1to the state S2occurs within the time window. As another example, a time window of transition from a time, as used herein, is a time period that occurs during a state after the time. To illustrate, the time window from the time t0a is a time period that occurs during the state S2of the digital pulsed signal208after the time t0a. The time period after the time t0a occurs during the state S2of the digital pulsed signal208from the time t0a to a time between the times t0a and t0b.

The RF signal212transitions from the state S2to the state S0within a time window from the time t0b. The state S0of the RF signal212is defined by the power level P0. For example, during the state S0of the digital pulsed signal208or the RF signal212, the RF signal212has the power level P0.

The RF signal212transitions from the state S0to the state S1within a time window from the time t2. The RF signal212transitions from the state S1to the state S2within a time window from the time t2a and transitions from the state S2to the state S0within a time window from the time t2b.

Similarly, during the state S1of the digital pulsed signal208, the RF signal214has the power level P1. The state S1of the RF signal214is defined by the power level P1. For example, during the state S1of the digital pulsed signal208or the RF signal214, the RF signal214has the power level P1.

The RF signal214transitions from the state S1to the state S2within a time window from the time t0a. The state S2of the RF signal214is defined by the power level P3. For example, during the state S2of the digital pulsed signal208or the RF signal214, the RF signal214has the power level P3.

The RF signal214transitions from the state S2to the state S0within a time window from the time t0b. The state S0of the RF signal214is defined by the power level P0. For example, during the state S0of the digital pulsed signal208or the RF signal214, the RF signal214has the power level P0.

The RF signal214transitions from the state S0to the state S1within a time window from the time t2. The RF signal214transitions from the state S1to the state S2within a time window from the time t2a and transitions from the state S2to the state S0within a time window from the time t2b.

The state S1of the RF signal212between the times t0 and t0a is a first instance of the state S1of the RF signal212and the state S1of the RF signal212between the times t2 and t2a is a second instance of the state S1of the RF signal212. Similarly, the state S2of the RF signal212between the times t0a and t0b is a first instance of the state S2of the RF signal212and the state S2of the RF signal212between the times t2a and t2b is a second instance of the state S2of the RF signal212. Also, the state S0of the RF signal212between the times t0b and t2 is a first instance of the state S0of the RF signal212and the state S0of the RF signal212between the times t2b and t4 is a second instance of the state S0of the RF signal212.

Similarly, the state S1of the RF signal214between the times t0 and t0a is a first instance of the state S1of the RF signal214and the state S1of the RF signal214between the times t2 and t2a is a second instance of the state S1of the RF signal214. Similarly, the state S2of the RF signal214between the times t0a and t0b is a first instance of the state S2of the RF signal214and the state S2of the RF signal214between the times t2a and t2b is a second instance of the state S2of the RF signal214. Also, the state S0of the RF signal214between the times t0b and t2 is a first instance of the state S0of the RF signal214and the state S0of the RF signal214between the times t2b and t4 is a second instance of the state S0of the RF signal214.

FIG.2Dis an embodiment of a graph215to illustrate an embodiment of an RF signal216generated by the RF generator RFGx (FIG.1) and an embodiment of an RF signal218generated by the RF generator RFGy (FIG.1). The RF signal216is an example of the RF signal102x(FIG.1), and the RF signal218is an example of the RF signal102y(FIG.1).

The graph215plots power levels of the RF signals216and218. Also, the graph215plots the time t on an x-axis. For example, the x-axis of the graph215includes the times t0, t2, t2, t3, and t4. It should be noted that duty cycles of the states S1through S3of the RF signals216and218are different than the duty cycles of the states S1through S3illustrated inFIG.2C. For example, the duty cycle of the state S1of the RF signals216and218is 25%, the duty cycle of the state S2of the RF signals216and218is 40%, and the duty cycle of the state S3of the RF signals216and218is 35%.

FIG.3Ais an embodiment of a graph302to illustrate a zoom-in of a portion of the RF signal212. The graph302plots the power levels of the RF signal212versus the time t. The RF signal212transitions from the power level P4 to the power level P2 within a time window from the time t0a. For example, the RF signal212transitions from the power level P4 to the power level P2 during a time period between the time t0a and a time t0a1. The time t0a1 occurs during the state S2of the RF signal212or of the digital pulsed signal208(FIG.2B), and occurs between the times t0a and t0b. Similarly, the RF signal212transitions from the power level P2 to the power level P0 within a time window from the time t0b.

FIG.3Bis an embodiment of a graph304to illustrate a zoom-in of a portion of the RF signal214. The graph304plots the power levels of the RF signal214versus the time t. The RF signal214transitions from the power level P1 to the power level P3 within a time window from the time t0a. For example, the RF signal214transitions from the power level P1 to the power level P3 during a time period between the time t0a and a time t0a2. The time t0a2 occurs during the state S2of the RF signal214or of the digital pulsed signal208(FIG.2B), and occurs between the times t0a and t0b. Similarly, the RF signal214transitions from the power level P3 to the power level P0 within a time window from the time t0b.

FIG.4Ais a in an embodiment of the graph202of the clock signal204.

FIG.4Bis a diagram of an embodiment of a graph402to illustrate an embodiment of a digital pulsed signal404. The digital pulsed signal404is an example of the digital pulsed signal108ofFIG.1. The graph402plots a logic level of the digital pulsed signal404on a y-axis and the time t on an x-axis. The y-axis of the graph402includes the logic levels 0, 1, and 2. The x-axis of the graph402includes the time t0, the time t0a, the time t1, a time t1a, the time t2, the time t2a, the time t3, a time t3a, and the time t4. The time t1a occurs between the times t1 and t2, and the time t3a occurs between the times t3 and t4.

The digital pulsed signal404periodically transitions among the states S1, S0, and S2. For example, the digital pulsed signal404has the state S1, which is defined by the logic level 0, from the time t0 to the time t0a. To illustrate, during the state S1, the digital pulsed signal208is at the logic level 0. The digital pulsed signal404transitions from the logic level 0 to the logic level 2 at the time t0a. The state S0of the digital pulsed signal404is defined by the logic level 2. To illustrate, during the state S0, the digital pulsed signal404is at the logic level 2.

The digital pulsed signal404has the state S0from the time t0a to the time t1a. At the time t1a, the digital pulsed signal404transitions from the state S0to the state S2, which is defined by the logic level 1. To illustrate, during the state S2, the digital pulsed signal404is at the logic level 1.

At the time t2, the digital pulsed signal404transitions from the state S2back to the state S1. The digital pulsed signal404has the state S1from the time t2 to the time t2a. The digital pulsed signal404transitions from the state S1to the state S0at the time t2a. The digital pulsed signal404has the state S0from the time t2a to the time t3a. At the time t3a, the digital pulsed signal404transitions from the state S0to the state S2. The digital pulsed signal404has the state S2from the time t3a to the time t4. At the time t4, the digital pulsed signal404transitions from the state S2back to the state S1.

It should be noted that multiple instances of each of the states S1, S0, and S2of the digital pulsed signal404occur. For example, a first instance of the state S1of the digital pulsed signal404occurs between the times t0 and t0a, and a second instance of the state S1of the digital pulsed signal404occurs between the times t2 and t2a. As another example, a first instance of the state S0of the digital pulsed signal404occurs between the times t0a and t1a, and a second instance of the state S0of the digital pulsed signal404occurs between the times t2a and t3a. As yet another example, a first instance of the state S2of the digital pulsed signal404occurs between the times t1a and t2, and a second instance of the state S2of the digital pulsed signal404occurs between the times t3a and t4. As another example, the first instance of the state S0is consecutive to the first instance of the state S1of the digital pulsed signal404and the first instance of the state S2of the digital pulsed signal404is consecutive to the first instance of the state S0. The second instance of the state S1of the digital pulsed signal404is consecutive to the first instance of the state S2of the digital pulsed signal404. Also, the second instance of the state S0of the digital pulsed signal404is consecutive to the second instance of the state S1of the digital pulsed signal404and the second instance of the state S2of the digital pulsed signal404is consecutive to the second instance of the state S0of the digital pulsed signal404.

FIG.4Cis an embodiment of a graph406to illustrate an embodiment of an RF signal408generated by the RF generator RFGx (FIG.1) and an embodiment of an RF signal410generated by the RF generator RFGy (FIG.1). The RF signal408is an example of the RF signal102x(FIG.1), and the RF signal410is an example of the RF signal102y(FIG.1).

The RF signals408and410are synchronized to the digital pulsed signal404. For example, each of the RF signals408and410initiate a transition from the state S1to the state S0at a time of transition of the digital pulsed signal404from the state S1the state S0. As another example, each of the RF signals408and410initiate a transition from the state S0to the state S2at a time of transition of the digital pulsed signal404from the state S0the state S2. As yet another example, each of the RF signals408and410initiate a transition from the state S2to the state S1at a time of transition of the digital pulsed signal404from the state S2the state S1.

The graph406plots power levels of the RF signals408and410. For example, the y-axis of the graph406includes power levels P0, P1, P2, P3, and P4. Also, the graph406plots the time t on an x-axis. For example, the x-axis of the graph406includes the times t0, t0a, t1, t1a, t2, t2a, t3, t3a, and t4.

The RF signal408periodically transitions among the states S1, S0, and S2of the RF signal408in a manner described below. Similarly, the RF signal410periodically transitions among the states S1, S0, and S2of the RF signal410in a manner described below

The state S1of the RF signal408is defined by the power level P4. For example, during the state S1of the digital pulsed signal404or the RF signal408, the RF signal408has the power level P4.

The RF signal408transitions from the state S1to the state S0within a time window from the time t0a. The state S0of the RF signal408is defined by the power level P0. For example, during the state S0of the digital pulsed signal404or the RF signal408, the RF signal408has the power level P0.

The RF signal408transitions from the state S0to the state S2within a time window from the time t1a. The state S2of the RF signal408is defined by the power level P2. For example, during the state S2of the digital pulsed signal404or the RF signal408, the RF signal408has the power level P2.

The RF signal408transitions from the state S2to the state S1within a time window from the time t2. The RF signal408transitions from the state S1to the state S0within a time window from the time t2a and transitions from the state S0to the state S2within a time window from the time t3a.

Similarly, during the state S1of the digital pulsed signal404, the RF signal410has the power level P1. The state S1of the RF signal410is defined by the power level P1. For example, during the state S1of the digital pulsed signal404or the RF signal410, the RF signal410has the power level P1.

The RF signal410transitions from the state S1to the state S0within a time window from the time t0a. The state S0of the RF signal410is defined by the power level P0. For example, during the state S0of the digital pulsed signal404or the RF signal410, the RF signal410has the power level P0.

The RF signal410transitions from the state S0to the state S2within a time window from the time t1a. The state S2of the RF signal410is defined by the power level P3. For example, during the state S2of the digital pulsed signal404or the RF signal410, the RF signal410has the power level P3.

The RF signal410transitions from the state S2to the state S1within a time window from the time t2. The RF signal410transitions from the state S1to the state S0within a time window from the time t2a and transitions from the state S0to the state S2within a time window from the time t3a.

The state S1of the RF signal408between the times t0 and t0a is a first instance of the state S1of the RF signal408and the state S1of the RF signal408between the times t2 and t2a is a second instance of the state S1of the RF signal408. Similarly, the state S0of the RF signal408between the times t0a and t1a is a first instance of the state S0of the RF signal408and the state S0of the RF signal408between the times t2a and t3a is a second instance of the state S0of the RF signal408. Also, the state S2of the RF signal408between the times t1a and t2 is a first instance of the state S2of the RF signal408and the state S2of the RF signal408between the times t3a and t4 is a second instance of the state S2of the RF signal408.

Similarly, the state S1of the RF signal410between the times t0 and t0a is a first instance of the state S1of the RF signal410and the state S1of the RF signal410between the times t2 and t2a is a second instance of the state S1of the RF signal410. Similarly, the state S0of the RF signal410between the times t0a and t1a is a first instance of the state S0of the RF signal410and the state S0of the RF signal410between the times t2a and t3a is a second instance of the state S0of the RF signal410. Also, the state S2of the RF signal410between the times t1a and t2 is a first instance of the state S2of the RF signal410and the state S2of the RF signal410between the times t3a and t4 is a second instance of the state S2of the RF signal410.

FIG.4Dis an embodiment of a graph411to illustrate an embodiment of an RF signal412generated by the RF generator RFGx (FIG.1) and an embodiment of an RF signal414generated by the RF generator RFGy (FIG.1). The RF signal414is an example of the RF signal102x(FIG.1), and the RF signal416is an example of the RF signal102y(FIG.1).

The graph411plots power levels of the RF signals414and416. Also, the graph411plots the time t on an x-axis. For example, the x-axis of the graph411includes the times t0, t2, t2, t3, and t4. It should be noted that duty cycles of the states S1through S3of the RF signals414and416are different than the duty cycles of the states S1through S3illustrated inFIG.4C. For example, the duty cycle of the state S1of the RF signals414and416is 25%, the duty cycle of the state S2of the RF signals414and416is 40%, and the duty cycle of the state S3of the RF signals414and416is 35%.

FIG.5Ais an embodiment of a graph502to illustrate a zoom-in of a portion of the RF signal408. The graph502plots the power levels of the RF signal408versus the time t. The RF signal408transitions from the power level P4 to the power level P0 within a time window from the time t0a. For example, the RF signal408transitions from the power level P4 to the power level P0 during a time period between the time t0a and the time t0a1. The time t0a1 occurs during the state S0of the RF signal408and the digital pulsed signal404(FIG.4B) and occurs between the times t0a and t1a. Similarly, the RF signal408transitions from the power level P0 to the power level P2 within a time window from the time t1a.

FIG.5Bis an embodiment of a graph504to illustrate a zoom-in of a portion of the RF signal410. The graph504plots the power levels of the RF signal410versus the time t. The RF signal410transitions from the power level P1 to the power level P0 within a time window from the time t0a. For example, the RF signal410transitions from the power level P1 to the power level P0 during a time period between the time t0a and the time t0a2. The time t0a2 occurs during the state S0of the RF signal410and the digital pulsed signal404(FIG.4B), and occurs between the times t0a and t1a. Similarly, the RF signal214transitions from the power level P0 to the power level P3 within a time window from the time t1a.

FIG.6is a diagram of an embodiment of a table600to illustrate duty cycles associated with the states S1, S2, and S0, and power levels during the states S1, S2, and S0. As an example, a duty cycle of the state S1of the RF signal102x(FIG.1) or the digital pulsed signal108(FIG.1) ranges from and including 3% to 25% of a cycle of the clock signal204(FIG.2A). To illustrate, the duty cycle of the state S1of the RF signal102xor the digital pulsed signal108ranges from and including 3% to 5% of the cycle of the clock signal204. As another example, a duty cycle of the state S1of the RF signal102y(FIG.1) or the digital pulsed signal108ranges from and including 3% to 25% of the cycle of the clock signal204(FIG.2A). To illustrate, the duty cycle of the state S1of the RF signal102yor the digital pulsed signal108ranges from and including 3% to 5% of the cycle of the clock signal204.

As yet another example, a duty cycle of the state S2of the RF signal102xor the digital pulsed signal108ranges from and including 3% to 50% of the cycle of the clock signal204. To illustrate, the duty cycle of the state S1of the RF signal102xor the digital pulsed signal108ranges from and including 3% to 5% of the cycle of the clock signal204. As another example, a duty cycle of the state S2of the RF signal102yor the digital pulsed signal108ranges from and including 3% to 50% of the cycle of the clock signal204. To illustrate, the duty cycle of the state S2of the RF signal102yor the digital pulsed signal108ranges from and including 3% to 5% of the cycle of the clock signal204.

As still another example, a duty cycle of the state S0of the RF signal102xor the digital pulsed signal108ranges from and including 25% to 94% of the cycle of the clock signal204. As another example, a duty cycle of the state S2of the RF signal102yor the digital pulsed signal108ranges from and including 25% to 94% of the cycle of the clock signal204.

As another example, during the state S1, a ratio between a power level of the RF signal102xand a power level of the RF signal102yranges from and including 6 to 10. To illustrate, a power level of the RF signal102xis 10 kilowatts (kW) and a power level of the RF signal102yis 1 kW. It should be noted that the duty cycles of the state S1of the RF signals102xand102yand the power level ratios between the RF signals RF102xand102yduring the state S1increases mask selectivity, which is further described below. As yet another example, during the state S2, a ratio between a power level of the RF signal102xand a power level of the RF signal102yranges from and including 0.2 to 1. As another example, during the state S2, a ratio between a power level of the RF signal102xand a power level of the RF signal102yranges from and including 0.2 to less than 1. An example of the ratio less than one is 0.4 or 0.45 or 0.5 or 0.8 or 0.9. To illustrate, during the state S2, a power level of the RF signal102xis 2 kW and a power level of the RF signal102yis 5 kW. As another illustration, during the state S2, a power level of the RF signal102xis between 20% and 100% of the power level of the RF signal102y. As yet another illustration, during the state S2, a power level of the RF signal102xis between 20% and less than 100% of the power level of the RF signal102y. As another illustration, during the state S2, a power level of the RF signal102xis not approximately zero and a power level of the RF signal102yis not approximately zero. To further illustrate, a power level of the RF signal102xduring the state S2does not range between 0 and 300 watts and a power level of the RF signal102yduring the state S2does not range between 0 and 300 watts. It should be noted that the duty cycles of the state S2of the RF signals102xand102yand the power level ratios between the RF signals RF102xand102yduring the state S2increases bow passivation, which is further described below. As another example, during the state S0, a power level of the RF signal102xranges from and including 0 watts to 300 watts, and a power level of the RF signal102yranges from and including 0 watts to 300 watts.

It should be noted that the power levels of the RF signals102xand102yduring the state S0of the RF signals102xand102yare approximately equal. For example, the power levels of the RF signals102xand102yduring the state S0of the RF signals102xand102yare within a pre-determined range from each other. To illustrate, the power level of the RF signal102xduring the state S0of the RF signal102xranges between 0 and 300 watts and the power level of the RF signal102yduring the state S0of the RF signal102yranges between 0 and 300 watts. As another example, the power levels of the RF signals102xand102yduring the state S0of the RF signals102xand102yare zero.

It should further be noted that a sum or a total of the duty cycles of the states S1through S3of the RF signal102xis equal to 100 percent of a clock cycle of the clock signal204. For example, first instances of the states S1, S2, and S0of each of the RF signals102xand102yoccupy the cycle1(FIG.2A) of the clock signal204and second instances of the states S1, S2, and S0of each of the RF signals102xand102yoccupy the cycle2(FIG.2A) of the clock signal204.

In one embodiment, a duty cycle of a state of an RF signal is a time period during which the RF signal has a unique power level during the time period. For example, the duty cycle of the state S1of the RF signal212is a time period between the times t0 and t0a during which the RF signal212has the power level P4. As another example, the duty cycle of the state S2of the RF signal212is a time period between the times t0a and t0b during which the RF signal212has the power level P2. As yet another example, the duty cycle of the state S0of the RF signal212is a time period between the times t0b and t2 during which the RF signal212has the power level P0. As another example, the duty cycle of the state S1of the RF signal214for the state S1is a time period between the times t0 and t0a during which the RF signal214has the power level P1. As still another example, the duty cycle of the state S2of the RF signal214is a time period between the times t0a and t0b during which the RF signal214has the power level P3. As yet another example, the duty cycle of the state S0of the RF signal214is a time period between the times t0b and t2 during which the RF signal214has the power level P0.

FIG.7Ais a diagram of an embodiment of a substrate stack700. The substrate stack700is an example of the substrate S before being processed in the plasma chamber106(FIG.1). The substrate stack700includes a substrate layer714, made from silicon. The substrate stack700further includes a stop layer712overlaid on top of the substrate layer714. An example of the stop layer712is an etch stop layer that is fabricated from a dielectric, such as an oxide or nitride. An oxide layer710is deposited on top of the stop layer712. Also, a silicon nitride (SiN) layer708is overlaid on top of the oxide layer710, an oxide layer706is deposited on top of the silicon nitride layer708, another silicon nitride layer704is deposited on top of the oxide layer706, and a mask layer702is deposited on top of the silicon nitride layer704. The mask layer702is a photolithography mask, which is an opaque plate or film.

In an embodiment, instead of the oxide layer706, a nitride layer is used. Similarly, in one embodiment, instead of the oxide layer710, a nitride layer is used.

FIG.7Bis a diagram of an embodiment of a substrate stack720to illustrate a balance between a passivation layer722deposited on a feature702B of the mask layer702(FIG.7A) and a passivation layer724deposited on a feature704B of the silicon nitride layer704(FIG.7A). The substrate stack720includes a feature702A of the mask layer702, the feature702B, a feature704A of the silicon nitride layer704, the feature704B, features706A and706B of the oxide layer706(FIG.7A), the silicon nitride layer708, and the oxide layer710. The remaining layers712and714(FIG.7A) of the substrate stack720are not shown inFIG.7B.

The substrate stack720is fabricated by etching the substrate stack700ofFIG.7Awithin the plasma chamber106(FIG.1). The substrate stack720is an example of the substrate S (FIG.1) after some etching of the substrate stack700. By supplying the combined modified RF signal124(FIG.1) that is generated based on the RF signals102xand102y(FIG.1) to the plasma chamber106, the substrate stack700is etched to achieve a balance between the passivation layer722and the passivation layer724. For example, the balance between the passivation layers722and724is achieved when the passivation layers722and724are deposited in a substantially equal manner to cover the respective features of the mask layer702and the silicon nitride layer704. To illustrate, a width of the passivation layer722is substantially equal to a width of the passivation layer724.

The substantially equal passivation of the passivation layer724results in bow control. For example, because of the substantially equal passivation of the passivation layer724, a bow is not formed on sidewalls of the features of the silicon nitride layer704. As an example, a passivation layer is a layer that is deposited on or around another layer when the modified RF signal124is applied to the substrate S. To illustrate, the passivation layers722and724include a combination of materials, such as silicon nitride and oxide, that are a part of the substrate stack720, and a combination of materials of the one or more process gases.

In two-state pulsing, an RF signal periodically alternates between a first state and a second state during one clock cycle of a clock signal. During the first state of the two-state pulsing, there is high mask selectivity, a high level of passivation of the feature702B, and negligible or minimal passivation of the feature704B. Also, during the first state, because of the high level of passivation of the feature702B and because of the negligible or minimal passivation of the feature704B, a bow is created in the feature704B. The bow is undesirable. Moreover, in the second state of the two-state pulsing, there is lower mask selectivity compared to the first state, a high level of passivation of the feature704B, and minimal or negligible passivation of the feature702B. As such, during the two-state pulsing, there is a lack of balance between passivation of the feature702B and passivation of the feature704B and the bow is created. The lack of balance occurs because there is a comparatively high amount of passivation of the feature702B compared to the feature704B during the first state and a comparatively high amount of passivation of the feature704B compared to the feature704A during the second state. By pulsing the RF signals102xand102yin a manner illustrated with reference toFIGS.2A-2CorFIGS.4A-4C, the balance between passivation of the features702B and704B is achieved and the bow is reduced or not created.

In addition, the pulsing of the RF signals102xand102yillustrated with reference toFIG.2A-2C or4A-4Cincreases mask selectivity compared to the two-state pulsing. An example of the mask selectivity includes a ratio of an etch rate of etching any of the layers704-710of the substrate stack700(FIG.7A) compared to an etch rate of etching of the mask layer702. The greater the mask selectivity, the faster the substrate stack700(FIG.7A) is etched and the lower the mask selectivity, the slower the substrate stack700is etched.

The pulsing of the RF signals102xand102yillustrated with reference toFIG.2A-2C or4A-4Cfacilitates achieving a balance between the mask selectivity and bow control. The bow control is achieved by passivation of sidewalls, such as a sidewall734, of features of the silicon nitride layer704. For example, a lower amount of passivation of the mask layer702achieved by pulsing the RF signals102xand102yin a manner illustrated with reference toFIG.2A-2C or4A-4Ccompared to that achieved by the two-state pulsing increases the mask selectivity. Moreover, an increased amount of passivation of the sidewalls of the features created by etching the silicon nitride layer704is achieved with the combined modified RF signal124(FIG.1) compared to an amount of passivation of the sidewalls achieved by applying the two-state pulsing. The increased amount of passivation of the sidewalls of the features created by etching the silicon nitride layer704reduces or eliminates bows within the sidewalls of the features created by etching the silicon nitride layer704and the reduction or elimination of the bows increases the mask selectivity.

The pulsing of the RF signals102xand102yfacilitates bow control and mask selectivity to be realized concurrently. By managing the pulsing of the RF signals102xand102y, an optimal balance can be achieved to effect both bow control and mask selectivity, while minimizing any trade-offs or compromises associated with the two-state pulsing.

FIG.7Cis a zoom-in view of a portion730of the substrate stack720(FIG.7B). The portion730includes the feature702B of the mask layer702(FIG.7A), the feature704B of the silicon nitride layer704(FIG.7A), and the feature706B of the oxide layer706(FIG.7A). Also illustrated inFIG.7Cis a bow732, that is shown as dashed. The bow732is created on the sidewall734of the feature704B. The sidewall734of the feature704B faces a sidewall726(FIG.7B) of the feature704A and a gap is created between the sidewalls726and734when the substrate stack700(FIG.7A) is etched. It should be noted that the bow732is created when the two-state pulsing is applied to the substrate S. However, the bow732is reduced or not created when the pulsing of the RF signals102xand102yillustrated with reference toFIG.2A-2C or4A-4Cis applied to the substrate S via the combined modified RF signal124(FIG.1). The bow732is reduced or not created when a balance between passivation of the features702B and704B is achieved with the pulsing of the RF signals102xand102y, illustrated with reference toFIGS.2A-2C and4A-4C.

Bow control is achieved when the bow732is reduced or not created so as to achieve or maintain a pre-determined critical dimension. For example, the pre-determined critical dimension (CD), which is a pre-determined width between the sidewall734of the feature704B and a sidewall, similar to the sidewall734, of the feature704A of the silicon nitride layer704is achieved due to effective bow control. The pre-determined width is less than a width, such as a horizontal distance, between the bow732and a bow, similar to the bow, created within the sidewall of the feature704A.

FIG.7Dis a diagram of an embodiment of a substrate stack740after processing the substrate stack700(FIG.7A) by applying the method illustrated with reference toFIGS.2A-2CorFIGS.4A-4C. The substrate stack740is an example of the substrate stack S after pulsing of the RF signals102xand102yillustrated with reference toFIGS.2A-2CorFIGS.4A-4Cis applied to the substrate stack700.

The substrate stack740includes features of the mask layer702(FIG.7A), features of the silicon nitride layer704(FIG.7A), features of the oxide layer706(FIG.7A), features of the silicon nitride layer708(FIG.7A), features of the oxide layer710(FIG.7A), and features of the stop layer712(FIG.7A). A passivation layer742, which includes multiple passivation portions, such as the passivation layer722(FIG.7C) and the passivation layer724(FIG.7C), is deposited on the features702B,704B,706B, a feature708B of the silicon nitride layer708, a feature710B of the oxide layer710, and a feature712B of the stop layer712. The passivation layer742is deposited when the combined modified RF signal124that is generated based on the RF signals102xand102yillustrated with reference toFIGS.2A-2CorFIGS.4A-4Cis applied to the substrate stack700.

FIG.8is a high level flow chart of an embodiment. A stack is provided (step804).FIG.9Ais a schematic cross-sectional view of a stack904processed according to an embodiment. The stack904comprises a substrate908. One or more intermediate layers912, such as an etch stop layer, may be over the substrate908. A first silicon oxide (SiO2) layer916is over the one or more intermediate layers912. A first silicon nitride (SiN) layer920is over the first SiO2layer916. A second SiO2layer924is over the first SiN layer920. A second SiN layer928is over the second SiO2layer924. A patterned mask932is over the second SiN layer928. In various embodiments, one or more layers may be between the patterned mask932and the second SiN layer928. Various embodiments may have additional alternating SiN layers and SiO2layers. Other embodiments may have layers of other materials. In various embodiments, the stack904has silicon containing layers. In this embodiment the patterned mask932is a hardmask, such as polysilicon.

The stack904may be placed in the plasma chamber106. An etch gas is flowed into the plasma chamber106(step808). In this embodiment, the etch gas comprises a metal fluoride or tungsten containing passivant and an etch component. In this embodiment, the metal fluoride or tungsten containing passivant is tungsten hexafluoride (WF6). In this embodiment, the etch component comprises oxygen (O2) and a fluorocarbon, such as hexafluorobutadiene (C4F6) and/or octafluorocyclobutane (C4F8).

A multi-state pulsing scheme is effected to form the etch gas into a plasma that etches the stack904. In this embodiment, the multi-state pulsing scheme comprises generating a primary RF signal at a first frequency range and a secondary RF signal at a second frequency range where the first frequency range is less than the second frequency range. The primary RF signal and the secondary RF signal pulse among at least three states, including a first state, a second state, and a third state. In an example, the primary RF signal has a frequency of 400 kHz and the secondary RF signal has a frequency of 60 MHz. The first state has a duty cycle of 3% to 20%, where the primary RF signal has a power level of 17 kW to 30 kW and the secondary RF signal has a power level of greater than 5 kW. In a more specific example, the first state has a duty cycle of 3% to 5%, where the primary RF has a power level of 29 kW. The second state has a duty cycle of 3% to 40%, where the primary RF signal has a power level of greater than 8 kW and the secondary RF signal has a power level of greater than 3 kW. In a more specific example, the second state has a duty cycle of 3% to 5%, where the primary RF signal has a power level of 13 kW and the secondary RF signal has a power level of 5 kW. The third state has a duty cycle of 40% to 94%, where the primary RF signal has a power level of less than 2 kW and the secondary RF signal has a power level of 1 kW. In a specific example, the third state has a duty cycle of 90% to 94%, where the primary RF signal has a power level of 0 kW and the secondary RF signal has a power level of 0 kW. In an embodiment, a ratio of the power level of the primary RF signal during the first state to the power level of the secondary RF signal during the first state is greater than 1, and a ratio of the power level of the primary RF signal during the second state to the power level of the secondary RF signal during the second state is less than 1.

FIG.9Bis a schematic cross-sectional view of a stack904after the etch is completed. Features940have been etched into the stack904by the etch process of the flowing the etch gas (step808) and providing the multi-state pulsing scheme described above. In this embodiment, the features940are contact holes. In this embodiment, a single etch recipe is able to selectively etch the first and second silicon oxide layers916,924and the first and second silicon nitride layers920,928. Without the metal fluoride or tungsten-containing passivant, bowing indicated by dotted lines948may result. The addition of the metal fluoride or tungsten containing passivant alone would cause necking as indicated by dotted lines944. The combination of the metal fluoride or tungsten-containing passivant and the multi-state pulsing scheme provides a tuning that is able to prevent necking and bowing with a high etch selectivity at the same time. It is believed that the multi-state pulsing scheme of the embodiment with three power levels provides an ion flux and bias energy that is able to prevent necking while using a metal fluoride or tungsten-containing passivant. In this embodiment, the etch selectivity for etching the dielectric stack with respect to a polysilicon mask is at least 2 to 1. More specifically, the etch selectivity for etching the dielectric stack with respect to a polysilicon mask is between 2:1 to 3:1.

In other embodiments, the power level of the primary RF signal during the second state is less than 80% of the power level of the primary RF signal during the first state. The power level of the primary RF signal during the third state is less than 20% of the power level of the primary RF signal during the second state. The power level of the secondary RF signal during the third state is less than 20% of the power level of the secondary RF signal during the second state. The first state has a duty cycle of 3% to 25%. The second state has a duty cycle of 3% to 50%. The third state has a duty cycle of 25% to 94%. In some embodiments, the duty cycle of the first state is less than the duty cycle of the third state. The duty cycle of the second state is less than the duty cycle of the third state.

In various embodiments, the first frequency range may be a frequency range between 80 kHz to 14 MHz. The first frequency range is used to create a bias for ion bombardment. The second frequency range may be a frequency range between 15 MHz and 120 MHz. The second frequency range is used to energize the plasma and may be used to control plasma density, ion flux, and degree of plasma dissociation. In various embodiments, the metal fluoride or tungsten-containing passivant is a tungsten fluoride. The tungsten fluoride may include tungsten hexafluoride, tungsten chloride pentafluoride (WClF5), and tungsten dichloride tetrafluoride (WCl2F4). In other embodiments, another tungsten-containing passivant is a tungsten fluoride, WFxCly, where x+y=4,5,6, or WOxFy, where 2x+y=4,5,6. For example, a tungsten-containing passivant may be WO2F2or WOF4, or WCl2F4.

In various embodiments, the stack has at least one silicon oxide layer. The stack comprises a silicon-based layer. In various embodiments, the mask is a hardmask, such as polysilicon. In other embodiments, the stack comprises alternating layers of silicon oxide and silicon nitride. Various embodiments provide high aspect ratio (HAR) features with height to width ratios greater than 20:1.

In various embodiments, the etch gas has a tungsten-containing passivant to total etch gas flow rate ratio of between 1 to 10 and 1 to 100, by number of moles.

FIG.10is a schematic view of an etch reactor that may be used in an embodiment. In one or more embodiments, a plasma processing system1000comprises a gas distribution plate1006providing a gas inlet and an electrostatic chuck (ESC)1008, within a plasma processing chamber1049, enclosed by a chamber wall1052. Within the plasma processing chamber1049, a stack1018is positioned on over the ESC1008. The ESC1008may provide a bias from the ESC source1048. The primary RF signal from the ESC source1048provides a bias at the ESC1008. An etch gas source1010is connected to the plasma processing chamber1049through the gas distribution plate1006. In this embodiment, the etch gas source1010may comprise a polymer passivant source1012, an etch component gas source1017, and a WF6(or tungsten-containing passivant) source1016. An ESC temperature controller1050is connected to a chiller1014. In this embodiment, the chiller1014provides a coolant to channels1005in or near the ESC1008. A radio frequency (RF) source1030provides RF power to a lower electrode and/or an upper electrode, which in this embodiment are the ESC1008and the gas distribution plate1006. In this embodiment, the secondary RF signal may be provided by the RF source1030. The secondary RF signal may be used to provide energy to form a plasma. In an exemplary embodiment, 400 kHz, 60 MHz, and optionally 2 MHz, 27 MHz power sources make up the RF source1030and the ESC source1048. The RF source1030and the ESC source1048may include the RF generator RFGx, the RF generator RFGy, and the impedance matching network IMN, shown inFIG.1. In this embodiment, the upper electrode is grounded. In this embodiment, one generator is provided for each frequency. In other embodiments, the generators may be in separate RF sources, or separate RF generators may be connected to different electrodes. For example, the upper electrode may have inner and outer electrodes connected to different RF sources. Other arrangements of RF sources and electrodes may be used in other embodiments. A controller1035is controllably connected to the RF source1030, the ESC source1048, an exhaust pump1020, and the etch gas source1010. An example of such an etch chamber is a modified Exelan Flex™ etch system manufactured by Lam Research Corporation of Fremont, CA The process chamber can be a CCP (capacitively coupled plasma) reactor or an ICP (inductively coupled plasma) reactor. Other embodiments may use other types of plasma processing chambers such as dielectric and conductive etch chambers or deposition chambers.

Other embodiments may have chambers of different dimensions. Such chambers may use different relative powers. For example, a larger chamber may use RF powers as high as or higher than 120 kW. In other embodiments, other states may be added, so that there may be a fourth or fifth state.

Embodiments, described herein, may be practiced with various computer system configurations including hand-held hardware units, microprocessor systems, microprocessor-based or programmable consumer electronics, minicomputers, mainframe computers and the like. The embodiments, described herein, can also be practiced in distributed computing environments where tasks are performed by remote processing hardware units that are linked through a computer network.

In some embodiments, a controller is part of a system, which may be part of the above-described examples. The system includes semiconductor processing equipment, including a processing tool or tools, chamber or chambers, a platform or platforms for processing, and/or specific processing components (a wafer pedestal, a gas flow system, etc.). The system is integrated with electronics for controlling its operation before, during, and after processing of a semiconductor wafer or substrate. The electronics is referred to as the “controller,” which may control various components or subparts of the system. The controller, depending on processing requirements and/or a type of the system, is programmed to control any process disclosed herein, including a delivery of process gases, temperature settings (e.g., heating and/or cooling), pressure settings, vacuum settings, power settings, RF generator settings, RF matching circuit settings, frequency settings, flow rate settings, fluid delivery settings, positional and operation settings, wafer transfers into and out of a tool and other transfer tools and/or load locks connected to or interfaced with the system.

Broadly speaking, in a variety of embodiments, the controller is defined as electronics having various integrated circuits, logic, memory, and/or software that receive instructions, issue instructions, control operation, enable cleaning operations, enable endpoint measurements, and the like. The integrated circuits include chips in the form of firmware that store program instructions, DSPs, chips defined as ASICs, PLDs, one or more microprocessors, or microcontrollers that execute program instructions (e.g., software). The program instructions are instructions communicated to the controller in the form of various individual settings (or program files), defining operational parameters for carrying out a process on or for a semiconductor wafer. The operational parameters are, in some embodiments, a part of a recipe defined by process engineers to accomplish one or more processing steps during the fabrication of one or more layers, materials, metals, oxides, silicon, silicon dioxide, surfaces, circuits, and/or dies of a wafer.

The controller, in some embodiments, is a part of or coupled to a computer that is integrated with, coupled to the system, otherwise networked to the system, or a combination thereof. For example, the controller is in a “cloud” or all or a part of a fab host computer system, which allows for remote access for wafer processing. The controller enables remote access to the system to monitor current progress of fabrication operations, examines a history of past fabrication operations, examines trends or performance metrics from a plurality of fabrication operations, to change parameters of current processing, to set processing steps to follow a current processing, or to start a new process.

In some embodiments, a remote computer (e.g. a server) provides process recipes to the system over a computer network, which includes a local network or the Internet. The remote computer includes a user interface that enables entry or programming of parameters and/or settings, which are then communicated to the system from the remote computer. In some examples, the controller receives instructions in the form of settings for processing a wafer. It should be understood that the settings are specific to a type of process to be performed on a wafer and a type of tool that the controller interfaces with or controls. Thus as described above, the controller is distributed, such as by including one or more discrete controllers that are networked together and working towards a common purpose, such as the fulfilling processes described herein. An example of a distributed controller for such purposes includes one or more integrated circuits on a chamber in communication with one or more integrated circuits located remotely (such as at a platform level or as part of a remote computer) that combine to control a process in a chamber.

Without limitation, in various embodiments, a plasma system, described herein, includes a plasma etch chamber, a deposition chamber, a spin-rinse chamber, a metal plating chamber, a clean chamber, a bevel edge etch chamber, a physical vapor deposition (PVD) chamber, a chemical vapor deposition (CVD) chamber, an atomic layer deposition (ALD) chamber, an atomic layer etch (ALE) chamber, an ion implantation chamber, a track chamber, or any other semiconductor processing chamber that is associated or used in fabrication and/or manufacturing of semiconductor wafers.

It is further noted that although the above-described operations are described with reference to a parallel plate plasma chamber, e.g., a capacitively coupled plasma chamber, etc., in some embodiments, the above-described operations apply to other types of plasma chambers, e.g., a plasma chamber including an inductively coupled plasma (ICP) reactor, a transformer coupled plasma (TCP) reactor, conductor tools, dielectric tools, a plasma chamber including an electron cyclotron resonance (ECR) reactor, etc. For example, an X MHz RF generator, a Y MHz RF generator, and a Z MHz RF generator are coupled to an inductor within the ICP plasma chamber.

As noted above, depending on a process operation to be performed by the tool, the controller communicates with one or more of other tool circuits or modules, other tool components, cluster tools, other tool interfaces, adjacent tools, neighboring tools, tools located throughout a factory, a main computer, another controller, or tools used in material transport that bring containers of wafers to and from tool locations and/or load ports in a semiconductor manufacturing factory.

With the above embodiments in mind, it should be understood that some of the embodiments employ various computer-implemented operations involving data stored in computer systems. These computer-implemented operations are those that manipulate physical quantities.

Some of the embodiments also relate to a hardware unit or an apparatus for performing these operations. The apparatus is specially constructed for a special purpose computer. When defined as a special purpose computer, the computer performs other processing, program execution or routines that are not part of the special purpose, while still being capable of operating for the special purpose.

In some embodiments, the operations, described herein, are performed by a computer selectively activated, or are configured by one or more computer programs stored in a computer memory, or are obtained over a computer network. When data is obtained over the computer network, the data may be processed by other computers on the computer network, e.g., a cloud of computing resources.

One or more embodiments, described herein, can also be fabricated as computer-readable code on a non-transitory computer-readable medium. The non-transitory computer-readable medium is any data storage hardware unit, e.g., a memory device, etc., that stores data, which is thereafter read by a computer system. Examples of the non-transitory computer-readable medium include hard drives, network attached storage (NAS), ROM, RAM, compact disc-ROMs (CD-ROMs), CD-recordables (CD-Rs), CD-rewritables (CD-RWs), magnetic tapes and other optical and non-optical data storage hardware units. In some embodiments, the non-transitory computer-readable medium includes a computer-readable tangible medium distributed over a network-coupled computer system so that the computer-readable code is stored and executed in a distributed fashion.

Although some method operations, described above, were presented in a specific order, it should be understood that in various embodiments, other housekeeping operations are performed in between the method operations, or the method operations are adjusted so that they occur at slightly different times, or are distributed in a system which allows the occurrence of the method operations at various intervals, or are performed in a different order than that described above.

It should further be noted that in an embodiment, one or more features from any embodiment described above are combined with one or more features of any other embodiment without departing from a scope described in various embodiments described in the present disclosure.

Although the foregoing embodiments have been described in some detail for purposes of clarity of understanding, it will be apparent that certain changes and modifications can be practiced within the scope of appended claims. Accordingly, the present embodiments are to be considered as illustrative and not restrictive, and the embodiments are not to be limited to the details given herein, but may be modified within the scope and equivalents of the appended claims.