Patent ID: 12206253

DETAILED DESCRIPTION

In the following description, numerous specific details are set forth, such as particular structures, components, materials, dimensions, processing steps and techniques, in order to provide an understanding of the various embodiments of the present application. However, it will be appreciated by one of ordinary skill in the art that the various embodiments of the present application may be practiced without these specific details. In other instances, well-known structures or processing steps have not been described in detail in order to avoid obscuring the present application.

FIG.1is a diagram showing an example system that can implement full bridge rectifier and voltage doubler in wireless power application in one embodiment. System100can include power devices, such as a transmitter110and a receiver120, that are configured to wirelessly transfer power and data therebetween via inductive coupling. While described herein as transmitter110and receiver120, each of transmitter110and receiver120may be configured to both transmit and receive power or data therebetween via inductive coupling. Transmitter110can be referred to as a wireless power transmitter and receiver120can be referred to as a wireless power receiver.

Transmitter110is configured to receive power from one or more power supplies and to transmit AC power130to receiver120wirelessly. For example, transmitter110may be configured for connection to a power supply116such as, e.g., an adapter or a DC power supply. Transmitter110can be a semiconductor device including a controller112and a power driver114.

Controller112can be configured to control and operate power driver114. Controller112can include, for example, a processor, central processing unit (CPU), field-programmable gate array (FPGA) or any other circuitry that is configured to control and operate power driver114. While described as a CPU in illustrative embodiments, controller112is not limited to a CPU in these embodiments and may comprise any other circuitry that is configured to control and operate power driver114. In an example embodiment, controller112can be configured to control power driver114to drive a coil TX of the power driver114to produce a magnetic field. Power driver114can be configured to drive coil TX at a range of frequencies and configurations defined by wireless power standards, such as, e.g., the Wireless Power Consortium (Qi) standard, the Power Matters Alliance (PMA) standard, the Alliance for Wireless Power (A for WP, or Rezence) standard or any other wireless power standards.

Receiver120can be configured to receive AC power130transmitted from transmitter110and to supply the power to one or more loads126or other components of a destination device140. Load126may comprise, for example, a battery charger that is configured to charge a battery of the destination device140, a DC-DC converter that is configured to supply power to a processor, a display, or other electronic components of the destination device140, or any other load of the destination device140. Destination device140may comprise, for example, a computing device, mobile device, mobile telephone, smart device, tablet, wearable device or any other electronic device that is configured to receive power wirelessly. In an illustrative embodiment, destination device140can include receiver120. In other embodiments, receiver120may be separate from destination device140and connected to destination device140via a wire or other component that is configured to provide power to destination device140.

Receiver120can be a semiconductor device including a controller122, a resonant circuit123, and a power rectifier124. Controller122can be an integrated circuit including, for example, a digital controller such as a microcontroller, a processor, CPU, FPGA or any other circuitry that may be configured to control and operate power rectifier124. Resonant circuit123can include a coil RX and one or more capacitors, inductors, resistors, that can form circuitry for outputting communication packets136and conveying AC power130, received from transmitter110, to power rectifier124. Power rectifier124can include rectifier circuits such as half-bridge rectifiers, full bridge rectifiers, or other types of rectifier circuits that can be configured to rectify power received via resonant coil RX of resonant circuit123into a power type as needed for load126. Power rectifier124is configured to rectify AC power130into DC power132which may then be supplied to load126. Controller122can be configured to execute application specific programs and/or firmware to control and operate various components, such as resonant circuit123and power rectifier124, of receiver120.

As an example, when receiver120is placed in proximity to transmitter110, the magnetic field produced by coil TX of power driver114induces a current in coil RX of resonant circuit123. The induced current causes AC power130to be inductively transmitted from power driver114to power rectifier124, via resonant circuit123. Power rectifier124receives AC power130and converts AC power130into DC power132. DC power132is then provided by power rectifier124to load126.

Transmitter110and receiver120are also configured to exchange information or data, e.g., messages, via the inductive coupling of power driver114and resonant circuit123. For example, before transmitter110begins transferring power to receiver120, a power contract may be agreed upon and created between receiver120and transmitter110. For example, receiver120may send communication packets136or other data to transmitter110that indicate power transfer information such as, e.g., an amount of power to be transferred to receiver120, commands to increase, decrease, or maintain a power level of AC power130, commands to stop a power transfer, or other power transfer information. In another example, in response to receiver120being brought in proximity to transmitter110, e.g., close enough such that a transformer may be formed by coil TX and coil RX to allow power transfer, receiver120may be configured to initiate communication by sending a signal to transmitter110that requests a power transfer. In such a case, transmitter110may respond to the request by receiver120by establishing the power contract or beginning power transfer to receiver120, e.g., if the power contract is already in place. Transmitter110and receiver120may transmit and receive communication packets136, data or other information via the inductive coupling of coil TX and coil RX. In some embodiments, communication between transmitter110and receiver120can occur before power transfer stage using various protocols such as near field communication (NFC), Bluetooth, etc.

Details of power rectifier124is shown inFIG.1. In an example, in response to receiving AC power130, power rectifier124can rectify AC power130into DC voltage in order to supply DC power132to load126. AC power130can be received through the AC1and AC2nodes of power rectifier124. Four transistors HS1, HS2, LS1, LS2, which can be metal-oxide-semiconductor field-effect transistors (MOSFETs), can form a rectifier circuit that enable supplying the rectifier voltage (VRECT) to rectify the AC power130.

The power transfer efficiency of system100, such as the ratio of the output power delivered to126and the input power provided by116, can be limited by the resistance of the coil RX. A number of wire or windings turns of the coil RX can be reduced to reduce the receiver coil resistance, but the voltage being induced on the coil RX would also diminish, hence reducing VRECT. VRECT has to reach a minimum voltage in order to power up the system100, and this minimum voltage can be in the order of 3 to 5 volts (V).

The systems and methods described herein can allow receiver120to operate under different modes to address these challenges caused by implementation of low resistance receiver coils. The modes that can be switched by controller122can include a full bridge rectifier (FBR) mode and a voltage doubler (VD) mode. A circuit150can be integrated, between power rectifier124and controller122. Circuit150can include a plurality of comparators configured to detect current and/or voltage events at power rectifier124. For example, circuit150can detect voltages at different parts of power rectifier124(e.g., across transistors HS1, HS2, LS1, LS2, nodes AC1, AC2, and/or other nodes) and, in response to specific values of the detected current and/or voltages, notify controller122to selectively switch the transistors HS1, HS2, LS1, LS2on or off to operate receiver120under different modes.

FIG.2is a diagram showing a circuit that can implement full bridge rectifier and voltage doubler in wireless power application in one embodiment. In an example shown inFIG.2, circuit150can include a plurality of comparators C1, C2, C3, C4, C5, C6. Outputs from comparators C1, C2, C3, C4, C5can be inputs to a finite state machine204being implemented by controller122. States and transition conditions of finite state machine204can be stored in a memory of controller122. In one embodiment, comparators C1, C2, C3, C4, C5, C6in circuit150can be Schmitt triggers.

Comparator C1can receive a voltage level measured across transistor HS1as inputs, and output a signal HS1_ON. In one embodiment, signal HS1_ON can have a voltage level representing a binary value (e.g., logic HIGH or LOW, or binary one or zero). Controller122can be configured to input HS1_ON into finite state machine204and finite state machine204can output a state based on the voltage level of signal HS1_ON. Controller122, based on the state outputted by finite state machine204and based on a current state of transistors HS1, HS2, LS1, LS2, can determine which transistors among HS1, HS2, LS1, LS2to selectively switch on, switch off, and maintain a current on or off state. In one embodiment, controller122can be configured to use signal HS1_ON under the VD mode. Controller122can be connected to input terminals of a gate driver202. Output terminals of gate driver202can be connected to gate terminals of transistors HS1, HS2, LS1, LS2. In response to determining to switch on transistor HS1, controller122can send a drive voltage V_HS1to gate driver202and gate driver202can drive a gate terminal of transistor HS1using V_HS1to switch on transistor HS1.

Comparators C2, C3can each receive a voltage level measured across transistor LS2as inputs. Comparator C2can output a signal transistor LS2_ON and comparator C3can output a signal transistor LS2_OFF. In one embodiment, each one of signal LS2_ON and LS2_OFF can have a respective voltage level representing a binary value (e.g., logic HIGH or LOW, or binary one or zero). LS2_ON and LS2_OFF may not have the same value or voltage level. In one embodiment, comparator C3can be auto-calibrated to output LS2_OFF indicating a need to switch off transistor LS2in response to a detection of zero current at node AC1. Controller122can be configured to input LS2_ON and LS2_OFF into finite state machine204, and finite state machine204can output a state based on the voltage levels of signal LS2_ON and/or LS2_OFF. For example, if signal LS2_ON has a voltage level indicating to switch on LS2and signal LS2_OFF has zero voltage (e.g., indicating no change), then finite state machine204can output a state that is based on the voltage level of signal LS2_ON. Controller122, based on the state outputted by finite state machine204and based on a current state of transistors HS1, HS2, LS1, LS2, can determine which transistors among HS1, HS2, LS1, LS2to selectively switch on, switch off, and maintain a current on or off state. In one embodiment, controller122can be configured to use signals LS2_ON and LS2_OFF under both FBR and VD modes. In response to determining to switch on transistor LS2, controller122can send a drive voltage V_LS2to gate driver202and gate driver202can drive a gate terminal of transistor LS2using V_LS2to switch on transistor LS2. In response to determining to switch off transistor LS2, controller122can adjust a voltage level of V_LS2to zero, or to a voltage below a threshold voltage of transistor LS2, and send the adjusted V_LS2to gate driver202such that transistor LS2can be switched off.

Comparators C4, C5can each receive a voltage level measured across transistor LS1as inputs. Comparator C4can output a signal transistor LS1_ON and comparator C5can output a signal transistor LS1_OFF. In one embodiment, each one of signal LS1_ON and LS1_OFF can have a respective voltage level representing a binary value (e.g., logic HIGH or LOW, or binary one or zero). LS1_ON and LS1_OFF may not have the same value or voltage level. In one embodiment, comparator C5can be auto-calibrated to output LS1_OFF indicating a need to switch off transistor LS1in response to a detection of zero current at node AC2. Controller122can be configured to input LS1_ON and LS1_OFF into finite state machine204, and finite state machine204can output a state based on the voltage levels of signal LS1_ON and/or LS1_OFF. For example, if signal LS1_ON has a voltage level indicating to switch on LS1and signal LS1_OFF has zero voltage (e.g., indicating no change), then finite state machine204can output a state that is based on the voltage level of signal LS1_ON. Controller122, based on the state outputted by finite state machine204and based on a current state of transistors HS1, HS2, LS1, LS2, can determine which transistors among HS1, HS2, LS1, LS2to selectively switch on, switch off, and maintain a current on or off state. In one embodiment, controller122can be configured to use signals LS1_ON and LS1_OFF under the FBR and VD modes. In response to determining to switch on transistor LS1, controller122can send a drive voltage V_LS1to gate driver202and gate driver202can drive a gate terminal of transistor LS1using V_LS1to switch on transistor LS1. In response to determining to switch off transistor LS1, controller122can adjust a voltage level of V_LS1to zero, or to a voltage below a threshold voltage of transistor LS1, and send the adjusted V_LS1to gate driver202such that transistor LS1can be switched off.

Comparator C6can receive a voltage level of VRECT and an overvoltage threshold (OV_THR) as inputs, and output a signal VRECT_OV. The overvoltage threshold OV_THR can be a predetermined value or voltage level stored in a memory of controller122. Controller122can be configured to read a value, or voltage level, of the signal VRECT_OV and based on the value, determine whether to enable a charge pump210. Controller122can output a signal QP to charge pump210, and charge pump210can be enabled or disabled based on a value or voltage level of signal QP. Charge pump210, when enabled, can boost the voltage level VRECT during the power-up to a level that may be sufficient to start up system100(seeFIG.1). In one embodiment, signal QP can be a disable signal (or an enable negate signal) that disables charge pump210. In one embodiment, charge pump210can be enabled when VRECT is zero, and controller122can disable charge pump210in response to VRECT reaching a specific voltage level. In one embodiment, a transistor212, which can be a MOSFET, can be connected between charge pump210and transistor LS2in order to short AC2to ground (GND). In one embodiment, transistor212can have a smaller transistor size than transistor LS1.

In another embodiment, transistor212may be removed and charge pump210can be connected to a gate terminal of transistor LS1. Charge pump can generate a gate-source voltage based on voltage level at AC1and VRECT, and the generated gate-source voltage can be sufficient to switch on transistor LS1. In one embodiment, in response to the voltage level at AC1being in proximity to VRECT, charge pump210can generate the gate source voltage. The generated gate-source voltage can boost VRECT. In one embodiment, if system100starts up when receiver120is operating in VD mode, then the voltage induced on the coil RX may increase VRECT to a level higher than OV_THR, and controller122can disable charge pump210based on signal VRECT_OV indicating there may be an overvoltage protection.

FIG.3Ais a diagram showing a circuit that can implement a full bridge rectifier mode in a wireless power receiver in one embodiment. A circuit300shown inFIG.3Acan include power rectifier124and comparators C2, C3, C4, C5. Under FBR mode, controller122can alternately switch the pair of transistors HS1, LS1and the pair of transistors HS2, LS2. For instance, transistors HS1, LS1can be switched on while transistors HS2, LS2are switched off, and transistors HS1, LS1can be switched off while transistors HS2, LS2are switched on. In response to transistors HS1, LS1being switched on, a current path can be formed from ground to VRECT and current can flow from AC2to AC1. In response to transistors HS2, LS2being switched on, a current path can be formed from ground to VRECT and current can flow from AC1to AC2. Controller122can be configured to generate a drive signal SNS1that can be used for switching on transistors HS1, LS1. Further, controller122can be configured to generate a drive signal SNS2that can be used for switching on transistors HS2, LS2. Drive signals SNS1and SNS2can be nonoverlapping signals (e.g., will not have the same values or voltage levels). In one embodiment, under the FBR mode, controller122can output drive signal SNS1, as V_HS1and V_LS1, to drive transistors HS1, LS1, via gate driver202, using SNS1. Controller122can output drive signal SNS2, as V_HS2and V_LS2, to drive transistors HS2, LS2, via gate driver202, using SNS2.

FIG.3Bis a state diagram of the full bridge rectifier mode ofFIG.3Ain one embodiment. A state diagram301of finite state machine204(seeFIG.2) is shown inFIG.3B. State302can be an initial state of state diagram301, where transistors HS1, HS2, LS1, LS2are switched off (e.g., indicated as binary zero). In response to transistor LS2being switched on for a predetermined amount of delay, state302can transition to state304. At state304, transistor HS2can be switched on (e.g., indicated as binary one) along with transistor LS2, and transistors HS1, LS1remains switched off. In response to transistor LS2being switched off, state304can transition to state306. At state306, transistors HS1, HS2, LS1, LS2can be switched off. In response to transistor LS1being switched on, state306can transition to state308. At state308, transistor HS1can be switched on along with transistor LS1, and transistors HS2, LS2remains switched off. State308can return to state302in response to transistor LS1being switched off. Finite state machine204can output one of states302,304,306,308in response to receiving one of the outputs from a comparator in circuit150(seeFIG.2), and controller122can use the outputted state to selectively switch on and switch off one or more specific transistors among transistors HS1, HS2, LS1, LS2.

FIG.4Ais a diagram showing a circuit that can implement a voltage doubler mode in a wireless power receiver in one embodiment. A circuit400shown inFIG.4Acan include power rectifier124and comparators C1, C2, C3, C5. Under VD mode, transistor LS1can remain switched on, transistor HS2can remain switched off, and controller122can alternately switch transistors HS1, LS2. For example, in a first cycle, transistor LS1and transistor HS1(transistor LS2will be off) can be switched on simultaneously to form a current path from ground to VRECT and current can flow from AC2to AC1. In the first cycle, controller122can set SNS1to a voltage level that can switch on transistor HS1. Further, in the first cycle, since transistor LS1needs to remain switched on, controller122can output SNS1, as V_HS1, to drive transistor HS1via gate driver202, and can output another signal V_on, as V_LS1, to switch on transistor LS1. Signal V_on can have a constant voltage level that is sufficient to drive a gate terminal of transistor LS1to switch on transistor LS1. In a second cycle, transistor LS1and transistor LS2can be switched on (transistor HS1will be off) and node AC1can be shorted to ground. Further, in the second cycle, since transistor HS2needs to remain switched off, controller122can output SNS2, as V_LS2, to drive transistor LS2via gate driver202, and can output a signal V_off as V_HS2. Signal V_off can be zero volts (e.g., controller122may not apply any voltage to the signal trace for V_HS2) or a voltage that is below a threshold voltage of transistor HS2.

FIG.4Bis a state diagram of a voltage doubler mode ofFIG.4Ain one embodiment. A state diagram401of finite state machine204(seeFIG.2) is shown inFIG.4B. State402can be an initial state of state diagram401, where transistors HS1, HS2, transistor LS2are switched off (e.g., indicated as binary zero) and transistor LS1is switched on (e.g., indicated as binary one). In response to transistor HS1being switched on for a predetermined amount of delay, state402can transition to state404. At state404, transistor HS1can be switched on, transistor LS1remains switched on, and transistors HS1, LS1remains switched off. In response to transistor HS1being switched off, state404can transition to state406. At state406, transistor HS1can be switched off, transistor LS1remains switched on, and transistors HS1, LS1remains switched off. In response to transistor LS2being switched on, state406can transition to state408. At state408, transistor LS2can be switched on along with transistor LS1, and transistors HS1, HS2remains switched off. State408can return to state402in response to transistor LS2being switched off. Finite state machine204can output one of states402,404,406,408in response to receiving one of the outputs from a comparator in circuit150(seeFIG.2), and controller122can use the outputted state to selectively switch on and switch off one or more specific transistors among transistors HS1, HS2, LS1, LS2

FIG.5Ais a flow diagram illustrating a process500of switching from a full bridge rectifier mode to a voltage doubler mode in one embodiment. The process500may include one or more operations, actions, or functions as illustrated by one or more of blocks502,504, and/or506. Although illustrated as discrete blocks, various blocks can be divided into additional blocks, combined into fewer blocks, eliminated, or performed in parallel, and/or performed in different order, depending on the desired implementation. Descriptions of process500can refer to components ofFIG.1-4.

Process500can start at block502, wherein a wireless power receiver (e.g., receiver120) can operate under a full bridge rectifier mode. Process500can proceed from block502to block504. At block504, a controller (e.g., controller122) of the wireless power receiver can monitor a voltage level at the node AC2. Process500can proceed from block504to block506. At block506, the controller can switch operation of the wireless power receiver in response to a detection of a rising edge of signal LS1_ON. The rising edge of signal LS1_ON can indicate that a voltage at node AC2is zero (or AC2is pulled to ground). Using the detection of the rising edge of signal LS1_ON to trigger a mode switch from FBR mode to VD mode can ensure a zero-voltage switching that provides digital synchronization across the transistors HS1, HS2, LS1, LS2. For example, the switching from FBR mode to VD mode in response to the rising edge of signal LS1_ON can ensure that transistor HS2is being switched off during the mode switch since the VD mode requires transistor HS2to remain switched off. Hence, HS2will not be accidentally switched on after the mode switch from FBR mode to VD mode.

FIG.5Bis a diagram illustrating voltage level changes in response to a mode switch from a full bridge rectifier mode to a voltage doubler mode in one embodiment. In the diagram shown inFIG.5B, during FBR mode, the voltage at node AC1(V_AC1) and the voltage at node AC2(V_AC2) can vary alternately and VRECT can be maintained at a voltage level V. In response to switching from FBR mode to VD mode, VRECT can be increased to voltage levels greater than V. Hence, VD mode can be used for increasing VRECT.

FIG.6Ais a flow diagram illustrating a process600of switching from a voltage doubler mode to a full bridge rectifier mode in one embodiment. The process600may include one or more operations, actions, or functions as illustrated by one or more of blocks602,604, and/or606. Although illustrated as discrete blocks, various blocks can be divided into additional blocks, combined into fewer blocks, eliminated, or performed in parallel, and/or performed in different order, depending on the desired implementation. Descriptions of process600can refer to components ofFIGS.1-4.

Process600can start at block602, wherein a wireless power receiver (e.g., receiver120) can operate under a voltage doubler mode. Process600can proceed from block602to block604. At block604, a controller (e.g., controller122) of the wireless power receiver can monitor a current flowing through transistor LS1. Process600can proceed from block604to block606. At block606, the controller can switch operation of the wireless power receiver in response to a detection of a rising edge of signal LS1_OFF. The rising edge of signal LS1_OFF can indicate zero current at transistor LS1. Using the detection of the rising edge of LS1_OFF to trigger a mode switch from VD mode to FBR mode can ensure a zero-current switching that provides digital synchronization across the transistors HS1, HS2, LS1, LS2. The switching from VD mode to FBR mode in response to the rising edge of signal LS1_OFF can ensure that nodes AC1and AC2are complementary (e.g., their voltage levels are opposite, either 0V or VRECT, from the switching point).

FIG.6Bis a diagram illustrating voltage level changes in response to a mode switch from a voltage doubler mode to a full bridge rectifier mode in one embodiment. In the diagram shown inFIG.6B, during VD mode, the voltage at node AC1(V_AC1) can vary periodically in response to alternately switching on transistors HS1and LS2while V_AC2remains at 0V (e.g., since HS2is switched off in VD mode). In response to switching from VD mode to FBR mode, VRECT can be decreased to a steady state voltage level and voltages V_AC1and V_AC2can vary alternately.

FIG.7Ais a diagram showing a transition into a full bridge rectifier mode for overvoltage protection in one embodiment. In one embodiment, during start up or power up of receiver120(seeFIG.1), VRECT can start at zero volts. VRECT may need to reach a minimum voltage in order to power up receiver120. In the example shown inFIG.7, if receiver120starts power up under the FBR mode, the voltages V_AC1and V_AC2increases VRECT at a relatively slow pace. The charge pump210is able to produce sufficient gate-source voltage (VGS) to turn on212at a time T1to switch from FBR mode to VD mode. In response to the mode switch at T1, V_AC2can remain at zero volts but V_AC1can increase at a relatively higher pace, effectively increasing VRECT as well. The VD mode can increase VRECT relatively faster than FBR mode, hence decreasing a power up time of receiver120.

FIG.7Bis a diagram showing details of a charge pump that can be implemented in a voltage doubler mode in one embodiment. In the example shown inFIG.7B, charge pump210can receive the voltage V_AC1, VRECT, and a signal QP as inputs. Referring toFIG.7A, as receiver120powers up, V_AC1and VRECT can increase gradually. As V_AC1and VRECT increase to nonzero voltage levels (e.g., 1V, 1.5V, or other predefined voltage thresholds), controller122(seeFIG.2) can enable charge pump210. In response to receiving signal QP, a gate driver702in charge pump210can switch on transistor212to short node AC2to ground in order to operate receiver120in VD mode. In embodiments where transistor212is installed in the receiver120, the output of gate driver702can be connected to a gate terminal of LS1and gate driver702can switch on LS1to short node AC2to ground. If VRECT increases to a voltage level greater than the overvoltage threshold OV_THR (seeFIG.2), then controller122can disable charge pump210by setting signal QP to a disable value (e.g., binary zero or one, depending on charge pump210). In response to charge pump being disabled, receiver120can operate under FBR mode, or under VD mode that is not being trigger by charge pump210.

FIG.8is a flow diagram illustrating a process of implementing full bridge rectifier and voltage doubler in wireless power application in one embodiment. The process800may include one or more operations, actions, or functions as illustrated by one or more of blocks802,804,806and/or808. Although illustrated as discrete blocks, various blocks can be divided into additional blocks, combined into fewer blocks, eliminated, or performed in parallel, and/or performed in different order, depending on the desired implementation.

Process800can be performed by a controller (e.g., controller122described herein) of a wireless power receiver (e.g., receiver120described herein). Process800can begin at block802. At block802, the controller can receive a plurality of signals that is based on measurements of voltage levels across a plurality of transistors of a power rectifier. In one embodiment, the controller can receive the plurality of signals from a plurality of comparators. The plurality of signals can be based on measurements of voltage levels across a first high side transistor, a second high side transistor, a first low side transistor, and a second low side transistor of the power rectifier.

Process800can proceed from block802to block804. At block804, the controller can, based on the plurality of signals, selectively switching one or more of the plurality of transistors of the power amplifier. In one embodiment, the controller can selectively switch one or more of the first high side transistor, the second high side transistor, the first low side transistor, and the second low side transistor of the power rectifier. In one embodiment, the controller can input the plurality of signals to a finite state machine. The controller can, based on an output of the finite state machine, selectively switch on one or more of the first high side transistor, the second high side transistor, the first low side transistor, and the second low side transistor.

Process800can proceed from block804to either one of block806or block808, depending on the transistors being switched on at block804. At block806, the controller can operate the wireless power receiver under a full bridge rectifier mode. At block808, the controller can operate a wireless power receiver under a voltage doubler mode. In one embodiment, the controller can enable the voltage doubler mode to power up the wireless power receiver. In one embodiment, the controller can enable the voltage doubler mode by enabling a charge pump to short a node between the second high side transistor and the first low side transistor to ground. In one embodiment, the transistor being switched on by the charge pump can be the first low side transistor.

In one embodiment, the controller can switch an operation mode of the wireless power receiver from the full bridge rectifier mode to the voltage doubler mode in response to a detection of a zero voltage event at a node between the second high side transistor and the first low side transistor, and in response to an indication to switch on the first low side transistor. In one embodiment, the controller can switch the operation mode of the wireless power receiver from the voltage doubler mode to the full bridge rectifier mode in response to a detection of a zero current event at a node between the first high side transistor and the second low side transistor, and in response to an indication to switch off the first low side transistor.

The flowchart and block diagrams in the Figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of instructions, which comprises one or more executable instructions for implementing the specified logical function(s). In some alternative implementations, the functions noted in the blocks may occur out of the order noted in the Figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems that perform the specified functions or acts or carry out combinations of special purpose hardware and computer instructions.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

The corresponding structures, materials, acts, and equivalents of all means or step plus function elements, if any, in the claims below are intended to include any structure, material, or act for performing the function in combination with other claimed elements as specifically claimed. The description of the present invention has been presented for purposes of illustration and description, but is not intended to be exhaustive or limited to the invention in the form disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the invention. The embodiment was chosen and described in order to best explain the principles of the invention and the practical application, and to enable others of ordinary skill in the art to understand the invention for various embodiments with various modifications as are suited to the particular use contemplated.