Patent ID: 12237770

DETAILED DESCRIPTION

Specific structural or functional descriptions of embodiments according to the concept of the present disclosure in this specification are only illustrated for the purpose of explaining the embodiments according to the concept of the present disclosure, and the embodiments according to the concept of the present disclosure may be embodied in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present disclosure to those skilled in the art.

Various modifications may be made to the embodiments according to the concept of the present disclosure and the embodiments can have various forms, and thus the embodiments are illustrated in the drawings and described in detail in this specification. However, this is not intended to limit the embodiments according to the concept of the present disclosure to specific disclosure forms, and includes all modifications, equivalents, or substitutes included in the spirit and technical scope of the present disclosure.

Unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which the present disclosure belongs. Terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with the meaning in the context of the prior art, and should not be interpreted in an ideal or excessively formal meaning unless explicitly defined in the present application.

Hereinafter, one or more embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

FIG.1is a diagram illustrating a 3-level buck-boost converter in accordance with one or more embodiments of the present disclosure.

Referring toFIG.1, one or more embodiments of the present disclosure is a 3-level buck-boost converter including a flying capacitor voltage balancing circuit, and is configured to include an inductor L, a first switch QA, a second switch QB, a third switch QC, a fourth switch QD, a flying capacitor CFLY, balancing switches QBAL1and QBAL2, a top balancing capacitor CFLY_BAL_T, and a bottom balancing capacitor CFLY_BAL_B.

In the following description, the first switch QA, the second switch QB, the third switch QC, the fourth switch QD, and the balancing switches QBAL1and QBAL2may be field effect transistors, but are not limited thereto.

The inductor L is connected in series between a switching node SW and a ground terminal.

An output capacitor COUTis connected between an output terminal VOUT from which an output voltage VOUTis output and a ground terminal.

The first switch QAis connected between an input terminal VIN to which an input voltage VINis input and a top plate node CP.

The second switch QBis connected between the top plate node CP and the switching node SW.

The third switch QCis connected between the switching node SW and a bottom plate node CN.

The fourth switch QDis connected between the bottom plate node CN and the output terminal VOUT.

The flying capacitor CFLYis connected between the top plate node CP and the bottom plate node CN.

The balancing switches QBAL1and QBAL2are connected between the switching node SW and a balancing node BA.

The top balancing capacitor CFLY_BAL_Tis connected between the input terminal and the balancing node BA.

The bottom balancing capacitor CFLY_BAL_Bis connected between the balancing node BA and the output terminal VOUT.

For example, the flying capacitor CFLYmay be configured to be connected in parallel with the top balancing capacitor CFLY_BAL_Tfor at least a period of time during operation of the 3-level buck-boost converter, and to be connected in parallel with the bottom balancing capacitor CFLY_BAL_Bfor another period of time during operation of the 3-level buck-boost converter.

For example, a configuration may be made such that a voltage VCFLYof the flying capacitor CFLY, a voltage of the top balancing capacitor CFLY_BAL_T, and a voltage of the bottom balancing capacitor CFLY_BAL_Bmay have substantially same values.

For example, a configuration may be made such that the voltage VCFLYof the flying capacitor CFLY, the voltage of the top balancing capacitor CFLY_BAL_T, and the voltage of the bottom balancing capacitor CFLY_BAL_Bmaintains a value obtained by dividing a value obtained by subtracting the output voltage from the input voltage by 2.

Hereinafter, a specific and non-limiting operation configuration of the 3-level buck-boost converter according to one or more embodiments of the present disclosure will be described.

For example, when the 3-level buck-boost converter according to one or more embodiments of the present disclosure operates at a duty ratio D less than approximately 0.5, a configuration is made such that 1) during a first time, the first switch QA, the third switch QC, and the balancing switches QBAL1and QBAL2are turned on, and the second switch QBand the fourth switch QDare turned off; thus the flying capacitor CFLY and the top balancing capacitor CFLY_BAL_Tare connected in parallel; 2) after the first time has elapsed, during a second time following the first time, the third switch QCand the fourth switch QDare turned on, and the first switch QA, the second switch QB, and the balancing switches QBAL1and QBAL2are turned off; 3) after the second time has elapsed, during a third time equal to the first time, the second switch QB, the fourth switch QD, and the balancing switches QBAL1and QBAL2are turned on, and the first switch QAand the third switch QCare turned off; thus the flying capacitor CFLYand the bottom balancing capacitor CFLY_BAL_Bare connected in parallel; and 4) after the third time has elapsed, during a fourth time equal to the second time, the third switch QCand the fourth switch QDare turned on, and the first switch QA, the second switch QB, and the balancing switches QBAL1and QBAL2are turned off.

Such configuration will be described in more detail with further reference toFIGS.2to4.

FIG.2is an operation timing diagram when the duty ratio D is less than approximately 0.5 in accordance with one or more embodiments of the present disclosure,FIG.3is a diagram illustrating a circuit diagram of each operation mode when the duty ratio is less than approximately 0.5 in accordance with one or more embodiments of the present disclosure, andFIG.4is a diagram illustrating a simplified circuit diagram of each operation mode when the duty ratio is less than approximately 0.5 in accordance with one or more embodiments of the present disclosure.

Referring toFIGS.2to4, first, during the first time, when the first switch QA, the third switch QC, and the balancing switches QBAL1and QBAL2are turned on and the second switch QBand the fourth switch QDare turned off so that the flying capacitor CFLYand the top balancing capacitor CFLY_BAL_Tare connected in parallel, a voltage VCPof the top plate node CP rises to an input voltage VIN, a voltage VSWof the switching node SW rises to a value (VIN− VCFLY) obtained by subtracting the voltage VCFLYof the flying capacitor CFLYfrom the input voltage VIN, and this value (VIN−VCFLY) is approximated to a value ((VIN+VOUT)/2) obtained by dividing the sum of the input voltage VINand the output voltage VOUTby 2; thus these values are substantially the same. In addition, the voltage VCNof the bottom plate node CN rises to the value (VIN−VCFLY) obtained by subtracting the voltage VCFLYof the flying capacitor CFYfrom the input voltage VIN, and a current IL of the inductor L gradually rises.

Next, after the first time has elapsed, during the second time following the first time, when the third switch QCand the fourth switch QDare turned on and the first switch QA, the second switch QB, and the balancing switches QBAL1and QBAL2are turned off, the voltage VCPof the top plate node CP falls to a value (VCFLY+VOUT) obtained by summing the voltage VCFLYof the flying capacitor CFLYand the output voltage VOUT, and this value (VCFLY+VOUT) is approximated to the value ((VIN+VOUT)/2) obtained by dividing the sum of the input voltage VINand the output voltage VOUTby 2; thus these values become substantially the same. In addition, the voltage VSWof the switching node SW and the voltage VCNof the bottom plate node CN fall to the output voltage VOUT, and the current ILof the inductor L gradually falls.

Next, after the second time has elapsed, during the third time equal to the first time, when the second switch QB, the fourth switch QD, and the balancing switches QBAL1and QBAL2are turned on and the first switch QAand the third switch QCare turned off so that the flying capacitor CFLYand the bottom balancing capacitor CFLY_BAL_Bare connected in parallel, the voltage VCPof the top plate node CP maintains the value (VCFLY+VOUT) obtained by summing the voltage VCFLYof the flying capacitor CFLYand the output voltage VOUT, the voltage VSWof the switching node SW rises to the value (VCFLY+VOUT) obtained by summing the voltage VCFLYof the flying capacitor CFLYand the output voltage VOUT, the voltage VCNof the bottom plate node CN maintains the output voltage VOUT, and the current ILof the inductor L gradually rises.

Next, after the third time has elapsed, during the fourth time equal to the second time, when the third switch QCand the fourth switch QDare turned on and the first switch QA, the second switch QB, and the balancing switches QBAL1and QBAL2are turned off, the voltage VCPof the top plate node CP maintains the value (VCFLY+VOUT) obtained by summing the voltage VCFLYof the flying capacitor CFLYand the output voltage VOUT, the voltage VSWof the switching node SW falls to the output voltage VOUT, the voltage VCNof the bottom plate node CN maintains the output voltage VOUT, and the current ILof the inductor L gradually falls.

For example, when the 3-level buck-boost converter according to one or more embodiments of the present disclosure operates at a duty ratio of approximately 0.5, a configuration is made such that 1) during a fifth time, the first switch QA, the third switch QC, and the balancing switches QBAL1and QBAL2are turned on, and the second switch QBand the fourth switch QDare turned off; thus the flying capacitor CFLYand the top balancing capacitor CFLY_BAL_Tare connected in parallel; and 2) after the fifth time has elapsed, during a sixth time equal to the fifth time, the second switch QB, the fourth switch QD, and the balancing switches QBAL1, and QBAL2are turned on, and the first switch QAand the third switch QCare turned off; thus the flying capacitor CFLYand the bottom balancing capacitor CFLY_BAL_Bare connected in parallel.

Such configuration will be described in more detail with further reference toFIGS.5to7.

FIG.5is an operation timing diagram when the duty ratio is approximately 0.5 in accordance with one or more embodiments of the present disclosure,FIG.6is a diagram illustrating a circuit diagram of each operation mode when the duty ratio is approximately 0.5 in accordance with one or more embodiments of the present disclosure, andFIG.7is a diagram illustrating a simplified circuit diagram of each operation mode when the duty ratio is approximately 0.5 in accordance with one or more embodiments of the present disclosure.

Referring toFIGS.5to7, first, during the fifth time, when the first switch QA, the third switch QC, and the balancing switches QBAL1and QBAL2are turned on and the second switch QBand the fourth switch QDare turned off and thus the flying capacitor CFLYand the top balancing capacitor CFLY_BAL_Tare connected in parallel, the voltage VCPof the top plate node CP rises to the input voltage VIN, the voltage VSWof the switching node SW maintains the value (VIN−VCFLY) obtained by subtracting the voltage VCFLYof the flying capacitor CFLYfrom the input voltage VIN, and this value (VIN−VCFLY) is a value approximated to zero. In addition, the voltage VCNof the bottom plate node CN rises to the value (VIN−VCFLY) obtained by subtracting the voltage VCFLYof the flying capacitor CFLYfrom the input voltage VIN, that is, a value approximated to 0, and the current ILof the inductor L maintains a constant value.

Next, after the fifth time has elapsed, during the sixth time equal to the fifth time, when the second switch QB, the fourth switch QD, and the balancing switches QBAL1and QBAL2are turned on, and the first switch QAand the third switch QCare turned off; thus the flying capacitor CFLYand the bottom balancing capacitor CFLY_BAL_Bare connected in parallel, the voltage VCPof the top plate node CP falls to the value (VOUT+VCFLY) obtained by summing the output voltage VOUTand the voltage VCFLYof the flying capacitor CFLY, that is, a value approximated to 0, and the voltage VSWof the switching node SW becomes the value (VOUT+VCFLY) obtained by summing the output voltage VOUTand the voltage VCFLYof the flying capacitor CFLY. This value (VOUT+VCFLY) is a value approximated to zero. The voltage VCNof the bottom plate node CN falls to the output voltage VOUT, and the current ILof the inductor L maintains a constant value.

For example, when the 3-level buck-boost converter according to one or more embodiments of the present disclosure operates at a duty ratio greater than approximately 0.5, a configuration is made such that 1) during a seventh time, the first switch QA, the third switch QC, and the balancing switches QBAL1and QBAL2are turned on, and the second switch QBand the fourth switch QDare turned off; thus the flying capacitor CFLYand the top balancing capacitor CFLY_BAL_Tare connected in parallel; 2) after the seventh time has elapsed, during an eighth time following the seventh time, the first switch QAand the second switch are QBturned on, and the third switch QC, the fourth switch QD, and the balancing switches QBAL1and QBAL2are turned off; 3) after the eighth time has elapsed, during an ninth time equal to the seventh time, the second switch QB, the fourth switch QD, and the balancing switches QBAL1and QBAL2are turned on, and the first switch QAand the third switch QCare turned off; thus the flying capacitor CFLYand the bottom balancing capacitor CFLY_BAL_Bare connected in parallel; and 4) after the ninth time has elapsed, during a tenth time equal to the eighth time, the first switch QAand the second switch QBare turned on, and the third switch QC, the fourth switch QD, and the balancing switches QBAL1and QBAL2are turned off.

Such configuration will be described in more detail with further reference toFIGS.8to10.

FIG.8is an operation timing diagram when the duty ratio D is greater than approximately 0.5 in accordance with one or more embodiments of the present disclosure,FIG.9is a diagram illustrating a circuit diagram of each operation mode when the duty ratio is greater than approximately 0.5 in accordance with one or more embodiments of the present disclosure, andFIG.10is a diagram illustrating a simplified circuit diagram of each operation mode when the duty ratio is greater than approximately 0.5 in accordance with one or more embodiments of the present disclosure.

Referring toFIGS.8to10, first, during the seventh time, when the first switch QA, the third switch QC, and the balancing switches QBAL1and QBAL2are turned on, and the second switch QBand the fourth switch QDare turned off; thus the flying capacitor CFLYand the top balancing capacitor CFLY_BAL_Tare connected in parallel, the voltage VCPof the top plate node CP maintains the input voltage VIN, the voltage VSWof the switching node SW falls to the value (VIN−VCFLY) obtained by subtracting the voltage VCFLYof the flying capacitor CFLYfrom the input voltage VIN, and this value (VIN−VCFLY) is approximated to the value ((VIN+VOUT)/2) obtained by dividing the sum of the input voltage VINand the output voltage VOUTby 2; thus these values are substantially the same. In addition, the voltage VCNof the bottom plate node CN maintains the value (VIN−VCFLY) obtained by subtracting the voltage VCFLYof the flying capacitor CFLYfrom the input voltage VIN, and the current ILof the inductor L gradually falls.

Next, after the seventh time has elapsed, during the eighth time following the seventh time, when the first switch QAand the second switch QBare turned on and the third switch QC, the fourth switch QD, and the balancing switches QBAL1and QBAL2are turned off, the voltage VCPof the top plate node CP maintains the input voltage VIN, the voltage VSWof the switching node SW rises to the input voltage VIN, the voltage VCNof the bottom plate node CN maintains the value (VIN−VCFLY) obtained by subtracting the voltage VCFLYof the flying capacitor CFLYfrom the input voltage VIN, and the current ILof the inductor L gradually rises.

Next, after the eighth time has elapsed, during the ninth time equal to the seventh time, when the second switch QB, the fourth switch QD, and the balancing switches QBAL1and QBAL2are turned on and the first switch QAand the third switch QCare turned off and thus the flying capacitor CFLYand the bottom balancing capacitor CFLY_BAL_Bare connected in parallel, the voltage VCPof the top plate node CP falls to the value (VCFLY+VOUT) obtained by summing the voltage VCFLYof the flying capacitor CFLYand the output voltage VOUT, the voltage VSWof the switching node SW falls to the value (VCFLY+VOUT) obtained by summing the voltage VCFLYof the flying capacitor CFLYand the output voltage VOUT, and this value (VCFLY+VOUT) is approximated to the value ((VIN+VOUT)/2) obtained by dividing the sum of the input voltage VINand the output voltage VOUTby 2; thus these values are substantially the same. In addition, the voltage VCNof the bottom plate node CN falls to the output voltage VOUT, and the current IL of the inductor L gradually falls.

Next, after the ninth time has elapsed, during the tenth time equal to the eighth time, when the first switch QAand the second switch QBare turned on and the third switch QC, the fourth switch QD, and the balancing switches QBAL1and QBAL2are turned off, the voltage VCPof the top plate node CP and the voltage VSWof the switching node SW rise to the input voltage VIN, the voltage VCNof the bottom plate node CN rises to the value (VIN−VCFLY) obtained by subtracting the voltage VCFLYof the flying capacitor CFLYfrom the input voltage VIN, and the current ILof the inductor L gradually rises.

As described in detail above, according to the present disclosure, efficiency can be improved by allowing the voltages across switches to be equally applied and reducing the inductor current ripple by implementing the flying capacitor voltage balancing with a simple circuit in the 3-level buck-boost converter.

In addition, there is an effect of achieving the flying capacitor voltage balancing at high speed.

According to the present disclosure, the efficiency can be improved by allowing voltages across switches to be equally applied and reducing inductor current ripple by implementing flying capacitor voltage balancing with a simple circuit in the 3-level buck-boost converter.

In addition, there is an effect of achieving the flying capacitor voltage balancing at high speed.

Although the a 3-level buck-boost converter with a flying capacitor voltage balancing circuit has been described with reference to the specific embodiments, it is not limited thereto. Therefore, it will be readily understood by those skilled in the art that various modifications and changes can be made thereto without departing from the spirit and scope of the present disclosure defined by the appended claims.