Patent ID: 12210125

DETAILED DESCRIPTION

Embodiments are described in greater detail below with reference to the accompanying drawings.

In the following description, like drawing reference numerals are used for like elements, even in different drawings. The matters defined in the description, such as detailed construction and elements, are provided to assist in a comprehensive understanding of the example embodiments. However, it is apparent that the example embodiments can be practiced without those specifically defined matters. Also, well-known functions or constructions are not described in detail since they would obscure the description with unnecessary detail.

As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items. Expressions such as “at least one of,” when preceding a list of elements, modify the entire list of elements and do not modify the individual elements of the list. For example, the expression, “at least one of a, b, and c,” should be understood as including only a, only b, only c, both a and b, both a and c, both b and c, all of a, b, and c, or any variations of the aforementioned examples.

The phrases “in some embodiments” or “in one embodiment” appearing in various places in this specification are not necessarily all referring to the same embodiment.

Some embodiments of the present disclosure may be expressed as functional block configurations and various processing operations. Some or all of the functional blocks may be realized by various numbers of hardware and/or software that perform specific functions. For example, the functional blocks of the present disclosure may be realized by one or more microprocessors or by circuit configurations for a given function. Also, for example, the functional blocks of the present disclosure may be realized in various programming or scripting languages. The functional blocks may be realized in algorithms executing on one or more processors. In addition, the present disclosure may employ techniques of the related art for electronic environment setting, signal processing, and/or data processing. Terms such as “mechanism”, “element”, “means” and “configurations” may be widely used, and are not limited to mechanical and physical configurations.

In addition, the connecting lines or connecting members between the components shown in the drawings are merely illustrative of functional connections and/or physical or circuit connections. In a practical device, the connections between the components may be represented by various functional connections, physical connections, or circuit connections that may be replaced or added.

FIG.1is a block diagram showing a configuration of a LiDAR device100according to an example embodiment.

Referring toFIG.1, the LiDAR device100may include a light transmitter110, a light receiver120and a processor130. The LiDAR device100may further include other general-purpose components in addition to the components shown inFIG.1.

The light transmitter110may include at least one light source that radiates light. For example, the light source may radiate light in an infrared band. When light in the infrared band is used, mixing with natural light in a visible band including sunlight may be prevented. However, the present embodiment is not necessarily limited thereto, and the light transmitter110may include a light source irradiating light in various wavelength bands.

The light transmitter110may include a light source, such as a laser diode (LD), an edge emitting laser, a vertical-cavity surface emitting laser (VCSEL), a distributed feedback laser, a light emitting diode (LED), a light emitting diode (SLD), etc. However, the present embodiment is not limited thereto.

The light transmitter110may radiate light toward an object OBJ under the control of the processor130. For example, the processor130may set a radiation direction or a radiation angle of light generated from the light source.

The light transmitter110may radiate pulsed light or continuous light. Also, the light transmitter110may transmit light toward the object OBJ a plurality of times.

The processor130may generate a start signal at the time of transmitting light and provide the start signal to a time-to-digital converter (TDC)400(refer toFIG.2). The start signal may be used for calculating a time of flight (ToF) of the light.

The light receiver120may receive reflected light of the light radiated toward the object OBJ. To this end, the light receiver120may include a detector array121configured to include a plurality of pixels PX1, PX2, PX3, . . . PXn. A light detection element may be disposed in each of the plurality of pixels PX1, PX2, PX3, . . . PXn. According to an example embodiment, the light receiver120may further include an optical element for collecting reflected light of light radiated toward the object OBJ in a predetermined pixel.

When the reflected light is received, the light receiver120may convert the reflected light into a stop signal. The stop signal may be used for calculating a flight time of light together with the start signal. The light receiver120may include a TDC for measuring a time of flight (ToF) of light detected in each of the plurality of light detection elements. In another example embodiment, the TDC may be provided separately from the light receiver120, in the LiDAR device100.

The plurality of light detection elements are sensors capable of detecting light, and may be, for example, light receiving elements that generate electrical signals by light energy.

In one embodiment, each of the light detection element may be a single photon avalanche diode (SPAD) having high sensing sensitivity.

The processor130may perform a signal processing for obtaining information on the object OBJ by using the light detected by the light receiver120. The processor130may determine, for example, a distance to the object OBJ based on a flight time of light reflected from the object OBJ, and perform data processing for analyzing a location and shape analysis of the object OBJ.

Information analyzed by the processor130, that is, information about the shape and location of the object OBJ may be transmitted to another unit to be used. For example, such information may be transmitted to a controller of an autonomous driving device, such as a driverless vehicle or drone in which the LiDAR device100is employed. Besides above, such information may be utilized in smartphones, cell phones, personal digital assistants (PDAs), laptops, personal computers (PCs), various wearable devices, and other mobile or non-mobile computing devices.

On the other hand, when the light detection element includes an SPAD, there is a problem that the sensing sensitivity is high while noise is also increased. Accordingly, in order to calculate a reliable flight time of light by using the SPAD, the light is radiated multiple times toward the object OBJ, a histogram of light reflected from the object OBJ is generated, and then, a process of statistically analyzing the histogram is necessary.

In the related art, a method of generating a histogram by using an off-chip digital signal processor or an off-chip processor has been mainly performed. However, in the off-chip method, since the number of TDCs increases corresponding to the number of pixels, the number of TDC channels may increase as the number of pixels increases. In addition, since the increase in the channel causes the increase in a sample rate, there is a problem that a bottleneck phenomenon occurs when data is read out.

In order to solve this problem, a digital counter may be integrated into a sensor chip, but when a histogram is generated by using only digital circuits to realize a multi-channel, a chip size rapidly increases.

Hereinafter, a method of significantly reducing the chip size while implementing a TDC in an on-chip manner by generating a histogram through an analog memory will be described.

FIG.2is a block diagram showing a configuration of a TDC included in a LiDAR device according to an example embodiment.

Referring toFIG.2, the TDC400according to an example embodiment may include a memory210including is a plurality of memory cells HIST MEM #1, HIST MEM #2, HIST MEM #3, . . . HIST MEM #n (211, when there is no need to distinguish below), a selector circuit220for sequentially selecting each of the plurality of memory cells211, a power supply230supplying power to the plurality of memory cells211based on a stop signal, and a processor130for calculating a time of flight (ToF) of light based on accumulated power accumulated in the plurality of memory cells211.

The memory210may include a plurality of memory cells211. The memory210may be realized by a volatile memory or flash memory, such as dynamic random access memory (DRAM), static random access memory (SRAM), or by a non-volatile memory, such as phase-change random access memory (PRAM), magnetic random access memory (MRAM), and resistive random access memory (ReRAM), and ferroelectrics random access memory (FRAM), but is not limited thereto.

The memory210may store a histogram. The histogram may denote a graph of distribution of a stop signal over time.

Each memory cell may store distribution information for each section of a stop signal. Accordingly, each memory cell may correspond to a histogram bin. In other words, each memory cell may denote a time bin for a section of an entire time, and the processor130may distinguish each of the memory cells211by assigning a number to each of the plurality of memory cells211. In addition, the processor130may obtain a total histogram by synthesizing histograms for each section stored in each of the memory cells211.

The histogram bins may be determined by the selector circuit220and may be generated based on a periodic signal synchronized to the start signal.

The memory210may store a coarse histogram and a fine histogram.

The coarse histogram may be a graph representing the distribution of a stop signal at a first resolution. The fine histogram may be a graph representing the distribution of a stop signal at a second resolution greater than the first resolution. For example, the first histogram bin of the first resolution may be 10 ns, and the second histogram bin of the second resolution may be 0.625 ns.

The memory210may be reset by the processor130after storing the coarse histogram. Also, the memory210may store a fine histogram based on the coarse histogram.

The processor130may acquire a coarse reception time of a stop signal through a coarse histogram, and then, obtain a fine reception time of the stop signal through a fine histogram.

Meanwhile, the memory210may be an analog memory, and the coarse histogram and the fine histogram may be accumulated as analog values by the power supply230and a capacitor C1(refer toFIG.4). A method of generating a histogram will be described more in detail below inFIG.4.

The selector circuit220may select a memory cell for supplying power by directly connecting to the memory cell211or connecting to the power supply230.

The selector circuit220may sequentially select each of the plurality of memory cells211based on a coarse clock synchronized with a start signal generated when light is transmitted. A selection time of the selector circuit220may correspond to a time bin, and thus, each memory cell may correspond to a histogram bin. In other words, the histogram bins may be generated as the selector circuit220sequentially selects each of the plurality of memory cells211. The processor130may distinguish each histogram bin by assigning a unique number to each memory cell in an ascending or descending order in the order of the memory cells selected by the selector circuit220.

The selector circuit220may shift a start signal corresponding to a period of a coarse clock coarse_clk in a coarse mode (e.g., shifting the start signal at the start/end of each period/cycle of the coarse clock coarse_clk) for generating a coarse histogram. The coarse clock coarse_clk and the start signal start may be input to the power supply230through a coarse window path.

In order to prevent signal delay due to a serial connection of pulse generators231, the selector circuit220may include a coarse clock distributor240that simultaneously distributes the coarse clock coarse_clk to each of the plurality of memory cells211. The coarse clock distributor240may be formed in a tree structure.

The selector circuit220may sequentially select each of the plurality of memory cells211based on a shifted start signal in a coarse mode in which a coarse histogram is generated. Since the start signal is shifted in response to a period of the coarse clock, any one memory cell among the plurality of memory cells211may be selected from a rising edge or a falling edge of the coarse clock. In addition, since the selector circuit220selects corresponding memory cells by a period of the coarse clock, the period of the coarse clock in the coarse mode may correspond to a width of the coarse histogram bin.

In a coarse mode, according to the sequential selection of the selector circuit220, a coarse histogram bin may be generated. For example, when the LiDAR device100detects a stop signal ranging from 0 ns to 160 ns in a coarse mode and a period of the coarse clock is 10 ns, 16 coarse histogram bins may be generated by dividing the range of 0 ns to 160 ns at every 10 ns.

The selector circuit220may delay a stop signal at a predetermined interval in a fine mode in which a fine histogram is generated. The selector circuit220may include a plurality of delay cells DC #1, DC #2, DC #3, . . . DC #n (221, when there is no need to distinguish) to delay a stop signal STOP. A delayed stop signal STOP may be input to the plurality of delay cells221through a fine window path.

The plurality of delay cells221are disposed on a delay line222and may be controlled by a control voltage VCTRL. Also, the plurality of delay cells221may output a stop signal STOP by delaying as much as a preset delay time Td. For example, when a stop signal passes through one delay cell, the stop signal may be delayed by Td, and when a stop signal passes through two delay cells, the stop signal may be delayed by 2×Td. In other words, the delay time of the stop signal may be increased corresponding to the number of passes of the delay cell.

Since a start signal and a coarse clock are synchronized with each other, the stop signal also needs to be synchronized with the period of the coarse clock to calculate a reception time of light. The selector circuit220may include a delay locked loop223for synchronizing a delayed stop signal to a period of a coarse clock to calculate a reception time of light.

The LiDAR device100of the present disclosure may have a structure in which one delay locked loop223is shared by two column TDCs. As the LiDAR device100includes a delay locked loop DLL223rather than a phase locked loop PLL, low power driving of the TDC400is possible, and a high resolution histogram may be generated.

In a fine mode in which a fine histogram is generated, the selector circuit220may sequentially select each of the plurality of memory cells211based on a delayed stop signal. The selector circuit220may select any one memory cell among the plurality of memory cells211for each output of a delay cell. Since the selector circuit220selects a corresponding memory cell by a delay time Td of a delay cell, the delay time Td of the delay cell in a fine mode may correspond to a width of a fine histogram bin.

In the fine mode, according to the sequential selection of the selector circuit220, a fine histogram bin may be generated. For example, when the LiDAR device100precisely detects a stop signal received in a range of 70 ns to 80 ns in a fine mode and a delay time of a delay cell is 0.625 ns, 16 fine histogram bins may be generated by dividing the range of 70 ns to 80 ns at every 0.625 ns. Accordingly, a delay time Td of a delay cell in a fine mode may be related to the resolution of a flight time.

The power supply230may supply power to the plurality of memory cells211based on a stop signal generated when light is received. In one embodiment, the power source may denote a current. To this end, the power supply230may include a plurality of pulse generators PG #1, PG #2, PG #3, . . . PG #n, (231, when there is no need to distinguish) to generate a current pulse.

Each pulse generator231may be connected to the selector circuit220and receive a selection signal of a memory cell from the selector circuit220. Also, each pulse generator may be connected to an input terminal of each of the plurality of memory cells211to supply a current pulse to each of the plurality of memory cells211based on a stop signal.

The power supply230may generate a coarse histogram and a fine histogram by supplying power to each of the plurality of memory cells211. The power supply230may supply power to any one memory cell among the plurality of memory cells211based on a stop signal. Histograms may be accumulated in each histogram bin by power supplied from the power supply230.

In a coarse mode, the power supply230may supply a current to a memory cell selected by the selector circuit220at a time when a stop signal is received. To this end, the selector circuit220may include a stop signal distributor250that simultaneously distributes a stop signal to each of a plurality of memory cells211. The stop signal distributor250may have a tree structure.

In a fine mode, the power supply230may supply a current to a memory cell selected by the selector circuit220at a time when a time window generated based on a coarse histogram ends.

A method of power supply of the power supply230in a coarse mode and a fine mode will be described more in detail below with reference toFIG.3.

The processor130may calculate a flight time of light based on accumulated power information accumulated in the plurality of memory cells211. The accumulated power information may be a coarse histogram and a fine histogram accumulated as analog values in the plurality of memory cells211.

The processor130may calculate an approximate flight time of light based on first information of accumulated power accumulated in the plurality of memory cells211in a coarse mode. When a coarse flight time of light is calculated, the processor130may reset all of the plurality of memory cells211. The processor130may accurately calculate the flight time of light based on second information of accumulated power information accumulated in the plurality of memory cells211in a fine mode.

The processor130may determine a distance to an object based on a precise flight time of light and perform a data processing for analyzing a position and shape of the object.

The memory210, the selector circuit220, the power supply230, and the processor130ofFIG.2may be configured in an on-chip type and integrated into a single chip.

FIG.3shows an example circuit configuration of the TDC ofFIG.2.

Referring toFIG.3, the TDC according to an example embodiment may include the selector circuit220, the pulse generator231, the memory cell211, and a comparator circuit260.

The selector circuit220may include a shift register224and a multiplexer225.

The shift register224may output an output signal Q by synchronizing an input signal D with a coarse clock coarse_clk. In one embodiment, the shift register224may include a D flip-flop DFF that shifts a start signal in response to a period of the coarse clock coarse_clk (e.g., at the start/end of the period of the coarse clock coarse_clk).

An input node of the shift register224may be connected to an output node of the shift register224included in a previous TDC. Accordingly, in the case of a first TDC, an input signal D input to the shift register224is a start signal START, and in the case of a TDC after the first TDC, an input signal D input to the shift register224may be an output signal output by the shift register224included in the previous TDC.

The shift register224may synchronize a coarse clock coarse_clk at the time of optical transmission by synchronizing a start signal D and the coarse clock coarse_clk. The shift register224may output a first selection signal for selecting any one memory cell among the plurality of memory cells211whenever the coarse clock coarse_clk rises.

Meanwhile, as shown inFIG.2, the selector circuit220may include a plurality of delay cells221and a delay fixed loop223, and whenever a stop signal is delayed, may output a second selection signal for selecting any one memory cell among the plurality of memory cells211.

The multiplexer225may select a coarse mode for generating a coarse histogram or a fine mode for generating a fine histogram based on a mode input signal MODE. The multiplexer225may output a first selection signal output by the shift register224in a coarse mode (mode ‘0’), and may output a second selection signal output by a delay cell in a fine mode (mode ‘1’).

The pulse generator231may include a D flip-flop330and a delay cell340. The D flip-flop330may determine the supply of a current pulse to the memory cell211, and the delay cell340may determine a holding time t of the current pulse. The holding time t of the current pulse may be substantially the same as the delay time t of the delay cell340. The pulse generator231may supply a current pulse to the memory cell211based on a first selection signal or a second selection signal.

The memory cell211may include a first switch S1connected to the pulse generator231, a capacitor C1connected to the first switch S1and accumulating voltages generated by the current pulse, a second switch S2connected in parallel to the capacitor C1and discharging the capacitor C1, and a third switch S3connected in parallel to the first switch S1and maintaining a constant voltage at an input terminal. The memory cell211may store a histogram for each section as an analog value based on a current pulse. The histogram for each section may be an accumulated voltage VHIST of the power (or energy) that is accumulated in the capacitor C1.

The comparator circuit260is connected to the output terminal of the memory cell211and compares the accumulated voltage VHIST accumulated in the capacitor C1with a reference voltage VREF=VF+Vth. When the accumulated voltage VHIST is greater than or equal to the reference voltage VREF, the comparator circuit260may output the accumulated voltage VHIST. To this end, the comparator circuit260may include a fourth switch S4for maintaining the reference voltage VREF and a fifth switch S5connected to the fourth switch S4and operating above the reference voltage VREF. The fourth switch S4and the fifth switch S5may be a bipolar junction transistor (BJT) or a field-effect transistor (FET), but are not limited thereto. As the comparator circuit260is configured as a2-T (transistor), circuit integration may be improved.

The processor130may calculate a coarse reception time of a stop signal based on an accumulated voltage VHIST output by the comparator circuit260in a coarse mode. Also, the processor130may generate a time window for a coarse reception time of a stop signal. In addition, the processor130may calculate a precise reception time of a stop signal within a time window based on an accumulated voltage VHIST output by the comparator circuit260through a fine mode.

Although, a selection signal is changed according to a coarse mode and a fine mode, but operating methods of the pulse generator231, the memory cell211, and the comparator circuit260may be the same in the coarse mode and the fine mode.

When reviewing an operating method of the TDC in a coarse mode and a fine mode, the processor130may output a coarse mode selection signal to the multiplexer225, and the multiplexer225may output a first selection signal based on the coarse mode selection signal.

In the coarse mode, a first selection signal is high whenever the coarse clock coarse_clk rises and a stop signal STOP may rise when light is detected.

Meanwhile, as depicted inFIG.2, since the plurality of memory cells211share a stop signal through a tree structure, when the TDC receives a stop signal, a stop signal may rise at the same time regardless of the location of the plurality of memory cells211.

When a stop signal rises in a memory cell in which a first selection signal is high, the pulse generator231may generate an injection signal INJ as much as the delay time t of the delay cell340. Also, the injection signal INJ may be transmitted to the memory cell211.

Meanwhile, whenever the injection signal INJ is applied to the memory cell211, a charge of I1×t (?) may be charged in the capacitor C1. Accordingly, a voltage may be accumulated in the capacitor C1as an analog value in proportion to the number n of injections of the injection signal INJ. In other words, the capacitor C1may store the accumulated voltage VHIST proportional to the number n of injections of the injection signal INJ.

When the fourth switch S4of the comparator circuit260is a P-type metal-oxide-semiconductor (PMOS), an output node O may be high by a precharge voltage. At this time, a voltage of the output node O may be a reference voltage VREF. The comparator circuit260may output the accumulated voltage VHIST when the accumulated voltage VHIST of the memory cell211is greater than or equal to the reference voltage VREF.

The processor130may store information about the memory cell211outputting an accumulated voltage VHIST equal to or greater than the reference voltage VREF in a coarse mode. The memory cell211outputting an accumulated voltage VHIST equal to or greater than the reference voltage VREF in a coarse mode may be referred to as a coarse memory cell. The meaning that the processor130stores information about the coarse memory cell in a coarse mode may be the same as the meaning of storing a coarse histogram bin.

After storing information about the coarse memory, the processor130may reset the accumulated voltage accumulated in each of the plurality of memory cells211. In other words, after storing information about the coarse memory, the processor130may erase the entire coarse histogram stored in the plurality of memory cells211.

The processor130may generate a time window corresponding to information about a coarse memory cell. Since the information about the coarse memory cell corresponds to a coarse histogram bin, a lower limit of the time window may be the same as a lower limit of the coarse histogram bin, and an upper limit of the time window may be the same as an upper limit of the coarse histogram bin.

After erasing all of the plurality of memory cells211, the processor130may output a fine mode selection signal to the multiplexer225for mode change. The multiplexer225may output a second selection signal based on the fine mode selection signal.

In the fine mode, the second selection signal may be propagated through the delay cell221included in the selection unit220and may be terminated when the time window ends. Any one memory cell of the plurality of memory cells211may be selected according to the propagation of the second selection signal. The selector circuit220may select the memory cell211in which the second selection signal is high.

The pulse generator231may supply a current pulse to the memory cell211in which the second selection signal is high when the time window ends.

A method of supplying a current pulse and a method of generating a fine histogram in a fine mode are the same as the method of supplying a current pulse and the method of generating a coarse histogram bin in a coarse mode. In other words, in the fine mode, the pulse generator231may transmit an injection signal INJ as much as a delay time t to the memory cell211in which the second selection signal is high when the time window ends. Also, whenever the injection signal INJ is applied to the memory cell211, a charge of I1×t may be charged in the capacitor C1. Accordingly, a voltage may be accumulated in the capacitor C1as an analog value in proportion to the number n of injections of the injection signal INJ.

In addition, the operating method of the comparator circuit260in a fine mode is the same as the operating method of the comparator circuit260in a coarse mode. In other words, when the accumulated voltage VHIST of the memory cell211is equal to or greater than the reference voltage VREF, the comparator circuit260may output the accumulated voltage VHIST.

The processor130may store information about the memory cell211that outputs an accumulated voltage VHIST equal to or greater than the reference voltage VREF in a fine mode. In a fine mode, the memory cell211that outputs an accumulated voltage VHIST equal to or greater than the reference voltage VREF may be referred to as a fine memory cell. The meaning that the processor130stores information about the coarse memory cell in a fine mode may be the same as the meaning that the processor130stores a fine histogram bin.

The processor130may calculate a flight time of light based on information about at least one fine memory cell that outputs an accumulated voltage VHIST equal to or greater than the reference voltage VREF among the plurality of memory cells211.

FIG.4shows an example circuit configuration of the memory cell211ofFIG.2.

Referring toFIG.3, the memory cell211may include: a first switch S1connected to the pulse generator231; a capacitor C1connected to the first switch S1and accumulating a voltage generated by a current pulse; a second switch S2that is connected in parallel to the capacitor C1and discharges the capacitor C1, and a third switch S3connected in parallel to the first switch S1and maintaining a constant voltage at an input terminal. The first switch S1, the second switch S2, and the third switch S3may be bipolar junction transistors (BJTs) or field effect transistors (FETs), but are not limited thereto.

The first switch S1may be turned on or off based on an injection signal INJ.FIG.4illustrates that, when the first switch S1is a PMOS, a reverse bias of an injection signal INJ is applied to a gate.

Whenever an injection signal INJ is applied to the first switch S1, the first switch S1is turned on, and accordingly, a charge of I1×t may be charged to the capacitor C1. As the capacitor C1is charged, an accumulated voltage VHIST according to Equation 1 below may be measured at both ends of the capacitor C1.

VHIST=n×I⁢1×t⁢1C[Equation⁢1]

Here, n is the number of injections of the injection signal INJ, I1is power supplied by the power supply230, t1is power supply time of the power supply230, C is a capacitance of the capacitor C1.

In the LiDAR device100of the present disclosure, since a voltage is accumulated in the capacitor C1as an analog value in proportion to the number n of injections of the injection signal INJ, a digital counter is unnecessary. Accordingly, a TDC may be manufactured in an on-chip form, and circuit integration is significantly increased.

The second switch S2may discharge the capacitor C1. The second switch S2may connect both ends of the capacitor C1based on a discharge signal RST. When information about a coarse memory cell is obtained, the processor130may discharge the capacitor C1by outputting the discharge signal RST to the memory cell211.

The third switch S3is turned on and off based on an injection signal INJ, and may maintain a constant voltage at an input terminal.

FIG.5is a diagram illustrating a coarse histogram generated by the LiDAR device100according to an example embodiment.

InFIG.5, the horizontal axis may represent the number of the memory cells211. Since each memory cell211denotes a time bin for a certain section of an entire time, it may denote that the larger the number of the memory cells211, the slower the detection time of light.

InFIG.5, the vertical axis denotes a level of an accumulated voltage stored in the memory cell211. It may denote that the larger the level of the accumulated voltage, the greater the number n of injections of the injection signal INJ.

FIG.5illustrates a coarse histogram in which the processor130sets a range between 0 ns and 160 ns as a total detection time, and divides the range of 0 ns to 160 ns at every 10 ns. Therefore, 16 coarse histogram bins are generated, and a width of each coarse histogram bin is 10 ns. InFIG.5, the coarse histogram for each section is stored in each memory cell211. However, the coarse histogram ofFIG.5is an example, and the total detection time, the width of the coarse histogram bin, etc. may be increased or decreased according to the number of memory cells, the period of the coarse clock, etc.

Referring toFIG.5, in a coarse mode, each memory cell211may store a coarse histogram for each section. The processor130may identify a coarse memory cell based on the coarse histogram for each section, and store information about the coarse memory cell. InFIG.5, since the memory cell that outputs an accumulated voltage VHIST equal to or greater than the reference voltage VREF is number7, the processor130may store information about the coarse histogram bin of the memory cell7.

The processor130may calculate that the coarse histogram bin of the coarse memory cell is a coarse reception time of a stop signal. The coarse reception time of the stop signal may be referred to as a coarse time. InFIG.5, since the coarse histogram bin of the memory cell7is 60 ns to 70 ns, the processor130may calculate that the stop signal has a coarse time of 60 ns to 70 ns.

After storing information about the coarse memory, the processor130may erase the entire coarse histogram stored in the plurality of memory cells211. Also, the processor130may generate a time window corresponding to information about the coarse memory cell. InFIG.5, the processor130may generate a time window ranging from 60 ns to 70 ns.

On the other hand, since the coarse time refers to a coarse reception time of a stop signal, it is necessary to generate a fine histogram in order to calculate a precise reception time of the stop signal. Hereinafter, a method of calculating a precise reception time of a stop signal through a fine histogram will be described.

FIG.6is a diagram for explaining a method of calculating a reception time of a stop signal in a time window according to an example embodiment.

FIG.6illustrates pulses of a stop signal620received within a time window610. InFIG.6, a reception time of the stop signal620received in the time window610may be derived by calculating a first time (ta) from a lower limit t0of the time window610to a first rising edge tr of the stop signal620or by calculating a second time tb from an upper limit t1of the time window610to a rising edge tr of the stop signal620.

Hereinafter, a method of calculating a reception time of the stop signal620by using the second time tb will be described, but the LiDAR device100of the present disclosure may calculate a reception time of the stop signal620by using the first time ta.

FIG.7is a diagram for explaining a method of generating a fine histogram according to an example embodiment.

Referring toFIG.7, the plurality of delay cells221may output the stop signal620with delay. The delay time of the stop signal620may increase as the number of delay cells through which the stop signal620passes increases. InFIG.7, a first stop signal621that is the stop signal620delayed once, a second stop signal622that is the stop signal620delayed twice, a third stop signal623that is the stop signal620delayed three times, and a fourth stop signal624that is the stop signal620delayed four times are depicted.

As the stop signal620passes through the plurality of delay cells221, the memory cell211in which the stop signal620is high may be changed, and the selector circuit220may sequentially select the memory cells211in which the stop signal620is high.

The pulse generator231may supply a current pulse to the memory cell211selected by the selector circuit220at the end of the time window610. InFIG.7, the pulse generator231may supply a current pulse to the memory cell211corresponding to the third stop signal623and the memory cell211corresponding to the fourth stop signal624.

Whenever a current pulse is supplied to the memory cell211, a voltage may be accumulated in the capacitor C1. A fine histogram may be generated by the accumulated voltage accumulated in the capacitor C1.

FIG.8is a diagram illustrating a fine histogram generated by the LiDAR device according to an example embodiment.

InFIG.8, the number of the memory cells211in the horizontal axis is the same as the number of the memory cells inFIG.5. Also, the level of the accumulated voltage on the vertical axis inFIG.8is the same as the level of the accumulated voltage inFIG.5.

FIG.8illustrates a fine histogram in which a range between 60 ns and 70 ns is set as a time window, and the range of 60 ns to 70 ns is divided by every 0.625 ns. Accordingly, 16 fine histogram bins are generated, and a width of each fine histogram bin is 0.625 ns. InFIG.8, fine histograms for each section are stored in each memory cell211. However, the fine histogram ofFIG.8is an example, and the time window, the width of the fine histogram bin, etc. may be increased or decreased according to the number of memory cells, the delay time of the delay cells221, etc.

Referring toFIG.8, in a fine mode, a fine memory cell may be identified. InFIG.8, since the number of a memory cell that outputs an accumulated voltage VHIST equal to or greater than the reference voltage VREF is 12, the processor130may store information about the fine histogram bin of the memory cell12.

The processor130may calculate a time from an upper limit of the time window to a rising edge of a stop signal based on the fine histogram bin. InFIG.8, since the fine histogram bin of memory cell12is 6.875 ns to 7.5 ns, the processor130may calculate that the time from the upper limit of the time window to the rising edge of the stop signal is 6.875 ns to 7.5 ns.

The processor130may calculate a precise reception time of the stop signal based on the time window and the fine histogram bin. The precise reception time of the stop signal may be referred to as a fine time. InFIG.8, since the time window in is 60 ns to 70 ns, the processor may calculate that the fine time of the stop signal is 62.5 ns to 63.125 ns.

As described above, since the LiDAR device100of the present disclosure does not require a separate memory cell for storing the fine histogram, miniaturization of the TDC is possible. In addition, the LiDAR device100of the present disclosure generates a coarse histogram and a fine histogram through the pulse generator231and the capacitor C1without a digital counter, thereby enabling on-chip of the TDC.

While not restricted thereto, an example embodiment can be embodied as computer-readable code on a computer-readable recording medium. The computer-readable recording medium is any data storage device that can store data that can be thereafter read by a computer system. Examples of the computer-readable recording medium include read-only memory (ROM), random-access memory (RAM), CD-ROMs, magnetic tapes, floppy disks, and optical data storage devices. The computer-readable recording medium can also be distributed over network-coupled computer systems so that the computer-readable code is stored and executed in a distributed fashion. Also, an example embodiment may be written as a computer program transmitted over a computer-readable transmission medium, such as a carrier wave, and received and implemented in general-use or special-purpose digital computers that execute the programs. Moreover, it is understood that in example embodiments, one or more units of the above-described apparatuses and devices can include circuitry, a processor, a microprocessor, etc., and may execute a computer program stored in a computer-readable medium.

The foregoing exemplary embodiments are merely exemplary and are not to be construed as limiting. The present teaching can be readily applied to other types of apparatuses. Also, the description of the exemplary embodiments is intended to be illustrative, and not to limit the scope of the claims, and many alternatives, modifications, and variations will be apparent to those skilled in the art.