Patent ID: 12211757

DETAILED DESCRIPTION

Various embodiments of the present invention will be explained below in detail with reference to the accompanying drawings. The following detailed description refers to the accompanying drawings that show, by way of illustration, specific aspects and embodiments in which the present invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the present invention. Other embodiments may be utilized, and structure, logical and electrical changes may be made without departing from the scope of the present invention. The various embodiments disclosed herein are not necessary mutually exclusive, as some disclosed embodiments can be combined with one or more other disclosed embodiments to form new embodiments.

Hereinafter, a semiconductor device and a method of forming the same according to the embodiments will be described with reference to the drawings. In the following description, dynamic random-access memory (hereinafter referred to as DRAM) is given as an example of the semiconductor device. In the following description, the semiconductor device is also referred to as a semiconductor chip. In the description of the plurality of embodiments, common or related elements or elements that are substantially the same are denoted with the same signs or names, and the description thereof will be reduced or omitted. In the drawings described hereinafter, the dimensions and dimensional ratios of each unit in each of the drawings do not necessarily match the actual dimensions and dimensional ratios in the embodiments, unless specifically noted otherwise. In the following description, the Z direction is the direction perpendicular to the X-Y plane defined as the plane of a semiconductor substrate, and the direction in which the semiconductor substrate exists may be referred to as the downward or lower direction, while the reverse direction may be referred to as the upward or higher direction in some cases.

First Embodiment

Hereinafter, a semiconductor device according to the first embodiment will be described.

As illustrated inFIG.1, the planar shape of the semiconductor device101is substantially rectangular. The semiconductor device101is disposed on a semiconductor substrate described later. The semiconductor device illustrated inFIG.1is an enlarged view of one semiconductor device101from among a plurality of semiconductor devices formed on a semiconductor wafer not illustrated.

The semiconductor device101is provided with a plurality of memory mats16in an active region11provided on the semiconductor substrate. The memory mats16are disposed in a matrix on the surface of the semiconductor device101. The active region11is surrounded by a scribe region12. The central part of the scribe region12is a dicing part14, and the semiconductor substrate is divided into a plurality of semiconductor chips by cutting in the dicing part14later.

A plurality of ODP (on Die Param) pad electrodes20are disposed at the edges of the semiconductor device101. The plurality of ODP pad electrodes20are disposed in the active region11of the semiconductor device101, and are arranged in a straight line along the outer edge of the active region11.

As illustrated inFIG.2, in the region A ofFIG.1, an ODP pad electrode20, connection wiring211drawn out from the ODP pad electrode20, a contact40that connects the connection wiring211to a wiring portion30of a lower wiring layer, and a contact41that connects the wiring portion30of the lower wiring layer to metal wiring231. The metal wiring231leads to the scribe region12, and a test component50is connected to the metal wiring231. The test component50includes a test element for measuring the electrical performance of the circuit elements used in a semiconductor circuit. Between the metal wiring231and the connection wiring211, power supply wirings26and27are disposed extending in the X direction. The wiring portion30of the lower wiring layer, which connects the test component50and the ODP pad electrode20and which is disposed straddling the active region11and the scribe region12, forms an interconnection structure that crosses the power supply wirings26and27.

The power supply wirings26and27are used as power supply trunk lines, and is disposed along the outermost edge of the semiconductor device101. Large currents flow through the power supply wirings26and27, and therefore the power supply wirings26and27are formed to have a low resistance by, for example, widening or thickening the wiring. The power supply wirings26and27extend along the border between the active region11and the scribe region12.

As illustrated inFIG.3, the semiconductor device101is provided with a semiconductor substrate64and an insulating film66disposed to cover the top of the semiconductor substrate64. Also, in the semiconductor device101, the wiring portion30of the lower wiring layer as well as the contacts40and41connected at either end of the wiring portion30of the lower wiring layer are provided inside the insulating film66. The metal wiring231connected to the contact40, the connection wiring211connected to the contact41, and the ODP pad electrode20connected to the connection wiring211are disposed on top of the insulating film66. The power supply wirings26and27are disposed on top of the insulating film66, between the metal wiring231and the connection wiring211.

The power supply wirings26and27are disposed on top of the insulating film66, above the wiring portion30of the lower wiring layer. The connection wiring211, the metal wiring231, and the power supply wirings26and27include the upper wiring layer in the same layer. The power supply wirings26and27are disposed in the active region11, and extend between the test component50and the ODP pad electrode20. The power supply wirings26and27include a conductive layer above the wiring portion30of the lower wiring layer. The power supply wirings26and27are disposed directly above the wiring portion30of the lower wiring layer. The power supply wirings26and27are the wiring closest to the border between the active region11and the scribe region12.

The semiconductor substrate64includes a disc-shaped single-crystal silicon wafer provided with a main surface that has been given a mirror finish, for example. The insulating film66contains silicon dioxide, for example. The wiring portion30of the lower wiring layer contains aluminum (Al), for example. The contact40and the contact41contain a metal. The connection wiring211, the metal wiring231, and the power supply wirings26and27contain aluminum, for example. The wiring portion30of the lower wiring layer includes a conductive film in a different layer from the connection wiring211, the metal wiring231, and the power supply wirings26and27.

As illustrated inFIG.4, the semiconductor device101is provided with a plurality of data lines68extending in the Y direction. The data lines68include signal lines that supply signals to sub-mats18disposed in the semiconductor device101. The plurality of sub-mats18are included in the memory mats16illustrated inFIG.1, and are arranged in a matrix inside the memory mats16.

The data lines68are connected to a column decoder (YDEC) not illustrated, for example. The column decoder decodes column addresses and supplies a column select signal to each corresponding sub-mat18through the data lines68. Each of the data lines68terminates at a destination sub-mat18to be supplied with a signal. The data lines68extend in a direction going from the center of the semiconductor device101toward the edge. Consequently, at the edge of the semiconductor device101in the Y direction, there are additional empty regions B where the data lines68do not exist. The ODP pad electrode20sare disposed in these empty regions B.

The data lines68include a lower conductive layer provided below the wiring layer included in the power supply wirings26and27and the like. The data lines68include the same lower conductive layer as the wiring portion30of the lower wiring layer, for example. In the empty regions B, the same lower conductive layer as the data lines68can be used to form the wiring portion30of the lower wiring layer.

As described above, the power supply wirings26and27extend between the scribe region12and the ODP pad electrode20. The metal wiring231connected to the test component50in the scribe region12is connected to the ODP pad electrode20through the wiring portion30of the lower wiring layer one level below, for example. However, the wiring portion30of the lower wiring layer is not limited to being one level below the power supply wirings26and27, and may also be in a deeper wiring layer.

The power supply wirings26and27, the ODP pad electrode20, and the metal wiring231include the upper wiring layer in the same layer. Accordingly, the power supply wirings26and27can be disposed without having to avoid the wiring that connects the ODP pad electrode20to the scribe region12. With this arrangement, because the power supply wirings26and27can be laid out without raising the resistance values of the power supply wirings26and27, a high-performance semiconductor device101can be provided.

Second Embodiment

Next, a semiconductor device and a method of forming the same according to the second embodiment will be described with reference toFIG.5,FIGS.6A and6B,FIGS.7A,7B, and7C,FIGS.8A,8B, and8C,FIGS.9A,9B, and9C,FIG.10, andFIG.11.

As illustrated inFIG.5, a semiconductor device102according to the second embodiment is provided with, in the active region11, a bonding pad221, connection wiring212connected to the bonding pad221, a contact44that connects the connection wiring212to a wiring portion30of a lower wiring layer, and a contact45that connects the wiring portion30of the lower wiring layer to metal wiring232. The metal wiring232extends to the scribe region12.

Wiring54is connected to the bonding pad221on the opposite side from the connection wiring212in the Y direction. The wiring54is connected to various signal lines, for example. Note that the wiring54may be provided in some cases, even when using the bonding pad221as the ODP pad electrode20of the semiconductor device101according to the first embodiment.

The semiconductor device102is provided with, in the scribe region12, a test component52, lower wiring31connected to the test component52, a TEG pad24connected to the lower wiring31, and a fuse element701. The lower wiring31includes the same wiring layer as the wiring portion30of the lower wiring layer. The test component52includes test elements referred to as a test element group (TEG) for measuring electrical properties and the like. The test component52also includes a test circuit for measuring the functional properties of an electronic circuit mounted on the semiconductor device102.

The TEG pad24is electrically connected to the test component52through the lower wiring31. The lower wiring31and the metal wiring232are connected at the fuse element701. In other words, the fuse element701functions as a contact that connects the lower wiring31and the metal wiring232. As described later, after the fuse element701is electrically blown, the metal wiring232and the lower wiring31are physically severed, and the electrical connection is broken. In this way, the fuse element701is disposed between the wiring portion30of the lower wiring layer and the test component52, and is capable of breaking the electrical connection between the bonding pad221and the test component52.

In the semiconductor device102, the active region11is surrounded by the scribe region12. The power supply wirings26and27extend between the scribe region12and the bonding pad221. The metal wiring232connected to the test component52in the scribe region12is connected to the bonding pad221through the wiring portion30of the lower wiring layer in a lower layer.

The bonding pad221disposed in the active region11and the test component52disposed in the scribe region12are connected through the wiring portion30of the lower wiring layer disposed below the power supply wirings26and27. The power supply wirings26and27, the bonding pad221, and the metal wiring232include the upper wiring layer in the same layer.

On the outermost periphery of the active region11, a guard ring60is provided along the outer edge of the active region11. The guard ring60protects the active region11against the intrusion of moisture from the outside and physical shocks.

In the semiconductor device102, the active region11, including the power supply wirings26and27, and also the fuse element701are covered by a cover film62. An opening62ain the cover film62is provided above the bonding pad221, leaving the top surface of the bonding pad221exposed through the opening62a. By placing a probe on the bonding pad221, the bonding pad221and the probe are electrically connected, thereby making it possible to pass a predetermined current to the bonding pad221.

In the scribe region12, the tops of the TEG pad24, the test component52, and the lower wiring31are covered by an insulating film. An opening24ain the insulating film is provided above the TEG pad24, leaving the top surface of the TEG pad24exposed through the opening24a. The top surface of the TEG pad24is exposed through the opening24a. By placing a probe on the TEG pad24, the TEG pad24and the probe are electrically connected, thereby making it possible to pass a predetermined current to the TEG pad24.

As illustrated inFIGS.6A and6B, the semiconductor device102is provided with the semiconductor substrate64, the insulating film66provided on top of the semiconductor substrate64, and the wiring portions30and31of the lower wiring layer and the guard ring60on top of the insulating film66. The guard ring60is provided with a first portion60a, a second portion60b, and a third portion60cdisposed in the vertical direction, for example. The first portion60a, the second portion60b, and the third portion60cinclude a conductive material, for example. In this case, the wiring portion30of the lower wiring layer, the lower wiring31, and the third portion60care included in the same wiring layer.

An insulating film67is provided on top of the wiring portions30and31of the lower wiring layer and the guard ring60. The bonding pad221, the metal wiring232, and the power supply wirings26and27provided between the bonding pad221and the metal wiring232are disposed on top of the insulating film67. The bonding pad221and the wiring portion30of the lower wiring layer are connected through the contact44. The metal wiring232and the wiring portion30of the lower wiring layer are connected through the contact45.

As illustrated inFIG.5andFIGS.6A and6B, the fuse element701is provided inside a fuse contact hole74, which is an opening provided in the insulating film67. Here, the sides on either end of the fuse contact hole74in the Y direction are referred to as the X-direction sides74a, while the sides on either end of the fuse contact hole74in the X direction are referred to as the Y-direction sides74b. The dimension of the fuse contact hole74in the Y direction is shorter than the dimension in the X direction. A metal thin film72is provided on a portion of a floor74cas well as on the X-direction sides74aof the fuse contact hole74. The floor74cis positioned on the top surface of the lower wiring31.

The metal thin film72is not provided on the Y-direction sides74bof the fuse contact hole74. The region enclosed between the X-direction sides74aand the Y-direction sides74bof the fuse contact hole74is a cavity63. On the surface of the semiconductor device102, the bonding pad221, the power supply wirings26and27, the metal wiring232, and the fuse element701are covered by the cover film62. An opening62ain the cover film62is provided above the bonding pad221, leaving the top surface of the bonding pad221exposed through the opening62a.

As described later, the bonding pad221, the power supply wirings26and27, the metal wiring232, and the metal thin film72are formed in the same processing step and include the same upper wiring layer. The thickness of the metal thin film72inside the fuse contact hole74is thinner than the thickness of the bonding pad221, the power supply wirings26and27and the metal wiring232outside the fuse contact hole74. The electrical resistance of the metal thin film72in the fuse contact hole74is greater than the electrical resistance of the bonding pad221, the power supply wirings26and27, and the metal wiring232. Consequently, when a current runs through the fuse element701, the metal thin film72can be ruptured by melting, thereby breaking the electrical connection.

Next,FIGS.6A and6BtoFIGS.9A,9B, and9Cwill be referenced to describe a method of forming the fuse element701of the semiconductor device102according to the second embodiment.

First, as illustrated inFIGS.7A,7B, and7C, the insulating film66on the semiconductor substrate64, the lower wiring31patterned on top of the insulating film66, and the insulating film67covering the insulating film66and the lower wiring31are formed. Next, the fuse contact hole74is formed as a hole penetrating through the insulating film67. The top surface of the lower wiring31is exposed at the floor of the fuse contact hole74. The insulating film66and the insulating film67contain silicon dioxide for example, and are formed by CVD, for example. As described later, the fuse element701is formed inside the fuse contact hole74.

The lower wiring31contains aluminum (Al) for example, and is formed by sputtering or CVD, for example. Thereafter, the lower wiring31is patterned by using known lithography techniques and anisotropic dry etching. The wiring portion30of the lower wiring layer and the third portion60cillustrated inFIG.6Aand the like are formed in the same processing step as the lower wiring31.

The fuse contact hole74is patterned by using known lithography techniques and anisotropic dry etching. The fuse contact hole74includes the X-direction sides74aand the Y-direction sides74b. As illustrated inFIGS.7A,7B, and7C, a dimension W1of the fuse contact hole74in the Y direction is formed smaller than a dimension W2of the fuse contact hole74in the X direction.

Next, as illustrated inFIGS.8A,8B, and8C, a metal film23is formed on the top surface of the insulating film67so as to cover the floor74c, the X-direction sides74a, and the Y-direction sides74bof the fuse contact hole74. The metal film23contains aluminum and is formed by sputtering, for example. At this point, the dimension W1of the fuse contact hole74in the Y direction is formed smaller than the dimension W2of the fuse contact hole74in the X direction.

Sputtering is a film deposition method with poor step coverage of the film to be formed. For this reason, in the case of forming the metal film23by sputtering, the metal film23is not formed conformally inside the fuse contact hole74, and the metal thin film72that is thinner compared to other regions is formed inside the fuse contact hole74, namely on the X-direction sides74a, the Y-direction sides74b, and the floor74c. Here, the metal film23may also be formed by CVD under conditions with poor step coverage.

Next, a patterned resist76is formed on the metal film23. The resist76is formed to cover the fuse element701and the region where the metal wiring232is expected to be formed. The resist76is formed so as not to cover the X-direction sides74a. The resist76is formed so as to cover a portion of the Y-direction sides74bof the fuse contact hole74. The resist76is patterned using known lithography techniques. Also, although not illustrated, the resist76is also formed on the bonding pad221formed at the same time as the resist76, and on the regions where the power supply wirings26and27are expected to be formed.

Next, as illustrated inFIGS.9A,9B, and9C, the resist76is used as a mask to etch the metal film23by anisotropic dry etching. The metal film23underneath the resist76remains, thereby forming the metal wiring232and the metal thin film72of the fuse element701. In the fuse element701, the metal thin film72is not disposed in a region74don either side, in the X direction, of the metal thin film72on the floor74c. The metal thin film72is disposed on the X-direction sides74aand the central portion of the floor74c.

Note that, although not illustrated, the bonding pad221and the power supply wirings26and27are also formed similarly. Next, the resist76is removed to form the structure illustrated inFIGS.9A,9B, and9C.

Next, as illustrated inFIGS.6A and6B, the cover film62is formed on top of the bonding pad221, the power supply wirings26and27, the metal wiring232, and the fuse element701, and the opening62ais formed in the cover film62. Through the above steps, the semiconductor device102according to the second embodiment is formed. The cover film62contains polyimide, for example.

Next,FIGS.10and11will be referenced to describe the blowing of the fuse element701in the semiconductor device102according to the second embodiment. Probes80and82are placed on the bonding pad221and the TEG pad24. Next, a predetermined current is passed through the probes80and82, which causes a current to flow through the fuse element701. The probes80and82supply a current sufficient to rupture the metal thin film72. The metal thin film72of the fuse element701has a high resistance value and is therefore ruptured and removed by the current, and a ruptured part75is formed on the X-direction sides74aand the floor74c. Due to the ruptured part75, the metal wiring232and the lower wiring31are severed from each other both physically and electrically. As a result, the fuse element701is blown.

Thereafter, the wafer on which a plurality of semiconductor devices102are mounted is cut in the dicing part14to form individual semiconductor chips. The cut surfaces of components such as the lower wiring31are exposed on the cut surface of each semiconductor chip.

According to the semiconductor device102according to the second embodiment, effects similar to the effects exhibited by the semiconductor device101according to the first embodiment are obtained.

In addition, according to the semiconductor device102according to the second embodiment, the metal wiring232is physically severed in the fuse element701. Consequently, even if moisture or chemicals intrude from the exposed lower wiring31on the side faces of the semiconductor chips, an intrusion that propagates along the metal wiring232and reaches the interior of the semiconductor device102can be suppressed. With this arrangement, a failure-resistant semiconductor device102can be provided.

Also, according to the semiconductor device according to the second embodiment, because the fuse element701is covered by the cover film62, the intrusion of moisture or chemicals from the fuse element701can be suppressed. With this arrangement, a failure-resistant semiconductor device102can be provided.

Also, according to the method of forming a semiconductor device according to the second embodiment, the metal thin film72that corresponds to the electrode of the fuse element701is deposited under conditions with poor step coverage. Moreover, the fuse contact hole74is formed having a small dimension W1in the Y direction and a small opening in the fuse contact hole74. With this arrangement, the metal thin film72that is thinner than other regions can be formed on the sides and floor of the fuse contact hole74. As the method of forming the metal thin film72, sputtering or CVD performed under conditions of poor step coverage can be used. With this arrangement, the metal thin film72that is thinner than the metal wiring232on the insulating film67can be formed without adding a separate processing step.

Third Embodiment

Next, a semiconductor device103according to a third embodiment will be described with reference toFIG.12.

The semiconductor device103according to the third embodiment differs from the semiconductor device102according to the second embodiment in that a probe pad78is provided between the bonding pad221and the contact44. The probe pad78is provided with a structure similar to the bonding pad221. The probe pad78includes the upper wiring layer in the same layer as the connection wiring211, the metal wiring231, and the power supply wirings26and27. An opening in the cover film62is formed above the probe pad78, leaving the top surface of the probe pad78exposed through the opening.

When blowing the fuse element701, probes80and82like the ones illustrated inFIG.10are placed on the TEG pad24and the probe pad78. Next, a predetermined current is passed through the probes80and82, which causes a current to flow through the fuse element701, thereby rupturing the fuse element701and causing the fuse element701to be blown. The rest of the configuration is similar to the semiconductor device102according to the second embodiment.

According to the semiconductor device103according to the third embodiment, effects similar to the effects exhibited by the semiconductor device102according to the second embodiment are obtained. According to the semiconductor device103according to the third embodiment, the probe pad78different from the bonding pad221is provided, and when blowing the fuse element701, the probes80and82are placed on the TEG pad24and the probe pad78.

With this arrangement, because a probe is not placed on the bonding pad221when blowing the fuse element701, a probe mark is not left behind on the bonding pad221. A bonding wire is connected to the bonding pad221afterward, and since a probe mark is not left behind, the occurrence of bond peeling on the bonding pad221can be reduced.

Fourth Embodiment

Next, a semiconductor device104according to a fourth embodiment will be described with reference toFIGS.13A and13B.

The semiconductor device104according to the fourth embodiment differs from the semiconductor device102according to the second embodiment in that a fuse element702is formed by wiring of smaller width compared to other portions. The semiconductor device104according to the fourth embodiment also differs from the semiconductor device102according to the second embodiment in that the lower wiring31connected to the test component52is connected from the bonding pad221to contact portion wiring312through the contact44, the wiring portion30of the lower wiring layer, the contact45, the metal wiring232, and a contact46, and the fuse element702is provided between the contact portion wiring312and the lower wiring31.

The fuse element702, the contact portion wiring312, and the lower wiring31include the same conductive layer as the wiring portion30of the lower wiring layer disposed underneath the power supply wirings26and27. The rest of the configuration is the same as the semiconductor device102according to the second embodiment.

As illustrated inFIG.13B, the width W3of the fuse element702is smaller than the width W4of a connecting part311connected to the fuse element702. Also, the width W3of the fuse element702is smaller than the width W5of the contact portion wiring312connected to the fuse element702. The widths W3, W4, and W5are all dimensions in the X direction. By reducing the width W3of the fuse element702, a highly resistive fuse element702can be provided.

The fuse element702is blown by placing probes on the bonding pad221and the TEG pad24and passing a predetermined current through the probes, similarly to the second embodiment.

The semiconductor device104according to the fourth embodiment exhibits effects similar to the semiconductor device102according to the second embodiment.

As above, DRAM is described as an example of the semiconductor device according to the embodiments, but the above description is merely one example and not intended to be limited to DRAM. Memory devices other than DRAM, such as static random-access memory (SRAM), flash memory, erasable programmable read-only memory (EPROM), magnetoresistive random-access memory (MRAM), and phase-change memory for example can also be applied as the semiconductor device. Furthermore, devices other than memory, including logic ICs such as a microprocessor and an application-specific integrated circuit (ASIC) for example are also applicable as the semiconductor device according to the foregoing embodiments.

Although this invention has been disclosed in the context of certain preferred embodiments and examples, it will be understood by those skilled in the art that the inventions extend beyond the specifically disclosed embodiments to other alternative embodiments and/or uses of the inventions and obvious modifications and equivalents thereof. In addition, other modifications which are within the scope of this invention will be readily apparent to those of skill in the art based on this disclosure. It is also contemplated that various combination or sub-combination of the specific features and aspects of the embodiments may be made and still fall within the scope of the inventions. It should be understood that various features and aspects of the disclosed embodiments can be combined with or substituted for one another in order to form varying mode of the disclosed invention. Thus, it is intended that the scope of at least some of the present invention herein disclosed should not be limited by the particular disclosed embodiments described above.