Patent ID: 12262523

DETAILED DESCRIPTION

To make the objectives, technical solutions, and advantages of the embodiments of the present disclosure clearer, the following clearly and completely describes the technical solutions in the embodiments of the present disclosure with reference to the accompanying drawings in the embodiments of the present disclosure. Apparently, the described embodiments are some but not all of the embodiments of the present disclosure. All other embodiments obtained by those skilled in the art based on the embodiments of the present disclosure without creative efforts should fall within the protection scope of the present disclosure. It should be noted that the embodiments in the present disclosure and features in the embodiments may be combined with each other in a non-conflicting manner.

A DRAM is a semiconductor memory that randomly writes and reads data at high speed, and is widely used in data storage devices or apparatuses. The DRAM includes a plurality of memory cells disposed repeatedly, and each of the memory cells includes a transistor and a capacitor. The capacitor is connected to a source and a drain of the transistor through a capacitor contact region and a capacitor contact structure. As electronic products are increasingly becoming lighter, thinner, shorter, and smaller, components of the DRAM are also designed toward the trend of high integration, high density, and miniaturization.

In a semiconductor structure, the transistor can be understood as a current switch structure made of a semiconductor material. A metal gate is disposed between the source and the drain of the transistor, and the metal gate can be used to control on/off of a current between the source and the drain. A gate-all-around (GAA) transistor adopts a GAA technology. With the development of semiconductor processes, a size of a semiconductor device is becoming smaller. In addition, GIDL occurs in a process of forming a structure of the GAA transistor, reducing performance and a yield of the semiconductor structure.

In a manufacturing method of a semiconductor structure and a semiconductor structure provided in the embodiments of the present disclosure, a first gate oxide layer is formed on sidewalls of a second segment and a third segment of an active pillar, and a second gate oxide layer is formed on the first gate oxide layer, so as to increase a thickness of a gate oxide layer of the active pillar and a charge storage capability of the gate oxide layer, and effectively reduce a GIDL current and interband tunneling. In addition, a length of the second gate oxide layer is less than that of the first gate oxide layer, a thickness of the second gate oxide layer is greater than that of the first gate oxide layer, and a top surface of the second gate oxide layer is flush with that of the third segment, such that two gate oxide layers with different thickness are formed at different positions of the second segment, and a thickness of a gate oxide layer formed on the third segment is the same as that of the thicker gate oxide layer on the second segment, to make potentials at both ends of the second segment different. This is conducive to controlling a turn-off current of a semiconductor structure and effectively improving performance and a yield of the semiconductor structure.

Exemplary embodiments of the present disclosure provide a manufacturing method of a semiconductor structure. The following describes the manufacturing method of a semiconductor structure with reference toFIG.1toFIG.28.

There are no limits made on the semiconductor structure in the embodiments. The semiconductor structure is described below by a DRAM as an example, but is not limited thereto in the embodiments. Alternatively, the semiconductor structure in the embodiments may be another structure, for example, a GAA transistor or a vertical gate-all-around (VGAA) transistor.

As shown inFIG.1, an exemplary embodiment of the present disclosure provides a manufacturing method of a semiconductor structure, including the following steps:

Step S100: Provide a substrate.

Step S200: Form a plurality of silicon pillars on the substrate, where the silicon pillars are arranged as an array.

Step S300: Preprocess the silicon pillar to form an active pillar, where along a first direction, the active pillar includes a first segment, a second segment, and a third segment that are sequentially connected.

Step S400: Form a first gate oxide layer on sidewalls of the second segment and the third segment.

Step S500: Form a second gate oxide layer on the first gate oxide layer, where along the first direction, a length of the second gate oxide layer is less than that of the first gate oxide layer, a top surface of the second gate oxide layer is flush with that of the third segment, and a thickness of the second gate oxide layer is greater than that of the first gate oxide layer.

According to an exemplary embodiment, this embodiment is a further description of step S100described above.

As shown inFIG.2, the substrate10is provided. The substrate10serves as a support member of a DRAM and is configured to support other components provided thereon. The substrate10may be made of a semiconductor material. The semiconductor material may be one or more of silicon, germanium, a silicon-germanium compound, and a silicon-carbon compound. In this embodiment, the substrate10is made of silicon. The use of silicon as the substrate10in this embodiment is to facilitate understanding of a subsequent forming method by those skilled in the art, rather than to constitute a limitation. In an actual application process, an appropriate material of the substrate may be selected as required.

According to an exemplary embodiment, this embodiment is a further description of step S200described above.

As shown inFIG.3, the silicon pillars20are formed on the substrate10. The silicon pillars20are arranged as the array on the substrate10, in other words, the silicon pillars20can be arranged in a plurality of rows and a plurality of columns. With a plane parallel to the first direction X as a cross section, a cross-sectional shape of the silicon pillar20includes a square. Referring toFIG.3, using an orientation shown in the figure as an example, the first direction X is an extension direction from a bottom surface of the substrate10to a top surface of the substrate10.

Referring toFIG.2andFIG.3, in some embodiments, the silicon pillars20arranged as the array may be formed on the substrate10by the following method:

At first, a plurality of bit line isolation trenches30are formed in the substrate10, and the bit line isolation trenches30are disposed at intervals along a second direction Y. The substrate10between adjacent ones of the bit line isolation trenches30forms a strip body40.

In a process of forming the bit line isolation trench30on the substrate10, a mask layer with a mask pattern can be first formed on the substrate10, a direction from the top surface of the substrate10to the bottom surface of the substrate10is taken as an extension direction, and along the extension direction, a part of the substrate10is removed based on the mask pattern to form the bit line isolation trenches30disposed at intervals along the second direction Y.

Then, a plurality of word line isolation trenches50are formed in the substrate10. The word line isolation trenches50are disposed at intervals along a third direction Z. The strip body40is separated into the silicon pillars20by the word line isolation trenches50disposed along the third direction Z. In this embodiment, along the first direction X, a depth of the word line isolation trench50is less than that of the bit line isolation trench30.

Referring toFIG.2, using an orientation shown in the figure as an example, the third direction Z is an extension direction parallel to a front side face of the substrate10. The second direction Y intersects the third direction Z on a same horizontal plane, where the second direction Y may intersect the third direction Z at a predetermined angle, for example, the second direction Y is mutually perpendicular to the third direction Z.

In a process of forming the word line isolation trench50on the substrate10, a mask layer with a mask pattern can be first formed on the substrate10, the direction from the top surface of the substrate10to the bottom surface of the substrate10is taken as an extension direction, and along the extension direction, a part of the substrate10is removed based on the mask pattern to form the word line isolation trenches50disposed at intervals along the third direction Z.

The bit line isolation trenches30and the word line isolation trenches50are formed on the substrate10, such that the silicon pillars20arranged in the plurality of rows and plurality of columns are formed on the substrate10. The word line isolation trench50and the bit line isolation trench30facilitate subsequent formation of other functional layers of a semiconductor structure on the substrate10, and the process of forming the silicon pillar20is simple, which facilitates control of a size of the subsequently formed active pillar60.

It should be noted that, in some embodiments, the silicon pillar20may alternatively be formed on the top surface of the substrate10by a silicon epitaxial growth process, or by depositing a multi-layer functional layer on the top surface of the substrate10, and a part of the functional layer is removed through etching, such that the silicon pillars20arranged in the plurality of rows and plurality of columns are formed on the substrate10.

According to an exemplary embodiment, this embodiment is a further description of step S300described above.

As shown inFIG.4toFIG.6, the silicon pillar20is preprocessed to form the active pillar60.

The preprocessing includes oxidation processing. That is, the silicon pillar20is etched or cleaned after the oxidization processing, such that the silicon pillar20forms the active pillar60. Edges and corners of the silicon pillar20are passivated through the oxidation processing, such that the cross-sectional shape of the silicon pillar20changes from the square to a circle or an ellipse. It should be noted that in some embodiments, the oxidation processing includes thermal oxidation or steam oxidation. In the oxidation processing, the silicon pillar20is exposed to the outside. Through thermal oxidation or steam oxidation, an oxide layer, such as monox, is formed on a surface of the silicon pillar20, and then the oxide layer can be removed through etching or cleaning, so as to passivate the edges and the corners of the silicon pillar20.

After the oxidization processing is completed for the silicon pillar20, an ion implantation process is performed on the silicon pillar20with a circular or elliptical cross-section to form the active pillar60. As an example, the method of processing the silicon pillar20by the ion implantation process, to form a drain and a source of the subsequent active pillar60is known to those skilled in the art, and details are not described herein again. It should be noted that the silicon pillar20processed by the ion implantation process forms the active pillar60in this step. Along the first direction X, the active pillar60includes the first segment601, the second segment602, and the third segment603that are sequentially connected, and a bottom surface of the first segment601is connected to the substrate10. The first segment601can form the source or the drain, the second segment602can form a gate, and the third segment603can form the source or the drain. In this embodiment, the first segment601forms the drain, and the third segment603forms the source.

In this embodiment, the edges and the corners of the silicon pillar20are passivated through the oxidation processing, which can improve an adhesion capability of the subsequent active pillar60, such that the subsequently formed functional layers such as a dielectric layer, a word line, and a bit line can be well connected to the active pillar60, thereby improving performance and a yield of the semiconductor structure.

As shown inFIG.12, in some embodiments, after the oxidation processing is performed on the silicon pillar20and the active pillar60is formed, in order to facilitate subsequent formation of a plurality of bit lines disposed at intervals along the second direction Y in the substrate10and realize insulation between adjacent ones of the bit lines, a bit line isolation structure70can be formed in the substrate10.

In some embodiments, the bit line isolation structure70may be formed by the following method:

At first, referring toFIG.7andFIG.8, a first initial dielectric layer81, an initial bit line91, and a second initial dielectric layer101that are stacked are successively formed in the bit line isolation trench30and the word line isolation trench50.

A first sacrificial dielectric layer (not shown in the figure) can be deposited in the bit line isolation trench30and the word line isolation trench50by an ALD process, a physical vapor deposition (PVD) process, or a chemical vapor deposition (CVD) process. The first sacrificial dielectric layer fills the bit line isolation trench30and the word line isolation trench50. Along the first direction X, a part of the first sacrificial dielectric layer is removed through etching, and the reserved first sacrificial dielectric layer forms the first initial dielectric layer81. A top surface of the first initial dielectric layer81is lower than a bottom surface of the word line isolation trench50.

After the first initial dielectric layer81is formed, a first bit line (not shown in the figure) is formed on the first initial dielectric layer81by the ALD process, the PVD process, or the CVD process. A top surface of the first bit line is flush with that of the bit line isolation trench30. Along the first direction X, a part of the first bit line is removed through etching, where an etching endpoint of the first bit line is flush with the bottom surface of the word line isolation trench50. The reserved first bit line forms the initial bit line91, in other words, the initial bit line91is only filled in the bit line isolation trench30.

After the initial bit line91is formed, the second initial dielectric layer101is formed on the initial bit line91by the ALD process, the PVD process, or the CVD process. A top surface of the second initial dielectric layer101is flush with that of the bit line isolation trench30.

After that, referring toFIG.9, a part of the second initial dielectric layer101, a part of the initial bit line91, and a part of the first initial dielectric layer81are removed through etching along the first direction X to form a plurality of first trenches110disposed at intervals along the second direction Y. The reserved first initial dielectric layer81forms a first dielectric layer80, the reserved initial bit line91forms a bit line90, and the reserved second initial dielectric layer101forms a second intermediate dielectric layer102. A material of the first dielectric layer80includes, but is not limited to, silicon nitride, silicon dioxide, or silicon oxynitride. A material of the bit line90includes, but is not limited to, cobalt silicide (CoSi) or platinum nickel silicide (PtNiSi).

Then, referring toFIG.10, a first initial isolation layer121is formed in the first trench110by the ALD process, the PVD process, or the CVD process.

Finally, referring toFIG.11andFIG.12, a part of the second intermediate dielectric layer102and a part of the first initial isolation layer121are removed through etching along the first direction X. It should be noted that etching endpoints of the second intermediate dielectric layer102and the first initial isolation layer121may be flush with a junction between the second segment602and the first segment601of the active pillar60. The reserved second intermediate dielectric layer102forms a second dielectric layer100. The reserved first initial isolation layer121forms a first isolation layer120.

A material of the second dielectric layer100includes, but is not limited to, silicon nitride, silicon dioxide, or silicon oxynitride. It should be noted that in an embodiment, a material of the first dielectric layer80may be the same as that of the second dielectric layer100to reduce process complexity and process costs.

A material of the first isolation layer120includes, but is not limited to, monox or silicon nitride. In this embodiment, the first dielectric layer80and the first isolation layer120form the bit line isolation structure70.

In some embodiments, the bit line isolation structure70may alternatively be an oxide-nitride-oxide (ONO) structure, but is not limited thereto.

The bit line isolation structure70formed in the substrate10can realize an insulation effect between adjacent bit lines90, and ensure the performance and the yield of the semiconductor structure.

In addition, the bit line forming method in this embodiment is simple and easy to control and operate. It should be noted that the bit line can be connected to the drain of the subsequently formed active pillar60. In a transistor, a gate is connected to a word line, and a source is connected to a capacitor structure. A voltage signal on the word line controls the transistor to turn on or off, and then data information stored in the capacitor structure is read through the bit line, or data information is written into the capacitor structure through the bit line for storage.

According to an exemplary embodiment, this embodiment is a further description of step S400described above.

As shown inFIG.13andFIG.14, the first gate oxide layer130is formed on the sidewalls of the second segment602and the third segment603of the active pillar60.

After the bit line isolation structure70is formed, the first gate oxide layer130is formed on the sidewall of the second segment602and on the sidewall and the top surface of the third segment603of the active pillar60by the ALD process.

In some embodiments, a first initial gate oxide layer (not shown in the figure) may be formed on the second segment602and the third segment603of the active pillar60by the ALD process. The first initial gate oxide layer is formed on the sidewall of the second segment602, the sidewall and the top surface of the third segment603, and top surfaces of the second dielectric layer100and the bit line isolation structure70. Then, the first initial gate oxide layer on the top surfaces of the second dielectric layer100and the bit line isolation structure70is removed through etching, and the first initial gate oxide layer on the sidewall of the second segment602and the sidewall and the top surface of the third segment603is reserved. The reserved first initial gate oxide layer forms the first gate oxide layer130. A material of the first gate oxide layer130may include, but is not limited to, silicon dioxide, silicon monoxide, hafnium oxide, or titanium oxide.

In this embodiment, the ALD process is characterized by a low deposition rate, high density of a deposited film layer, and good step coverage. The ALD process is used to form a relatively thin first gate oxide layer130, which can effectively isolate and protect the second segment602, namely, the gate, of the active pillar, and can avoid occupying large space, thereby facilitating subsequent filling or formation of another structure layer.

According to an exemplary embodiment, this embodiment is a further description of step S500described above.

As shown inFIG.19andFIG.20, the second gate oxide layer140is formed on the first gate oxide layer130. Along the first direction X, the length of the second gate oxide layer140is less than that of the first gate oxide layer130, the top surface of the second gate oxide layer140is flush with that of the third segment603, and the thickness of the second gate oxide layer140is greater than that of the first gate oxide layer130.

In some embodiments, the second gate oxide layer140may be formed by the following method:

At first, referring toFIG.14, after the first gate oxide layer130is formed, a filling region150is formed between the top surface of the second dielectric layer100and a sidewall of the first gate oxide layer130.

Referring toFIG.15andFIG.16, an initial sacrificial layer (not shown in the figure) is formed in the filling region150by the ALD process, the PVD process, or the CVD process. The initial sacrificial layer fills the filling region150. After that, a part of the initial sacrificial layer is removed through etching, where an etching endpoint of the initial sacrificial layer is flush with a preset position of the second segment602. The reserved initial sacrificial layer forms a sacrificial layer160. In this step, the preset position of the second segment602may be one-third to two-thirds of a height of the second segment602. In an embodiment, the preset position of the second segment602is a half of the height of the second segment602. In this embodiment, along the first direction X, a part that is of the second segment602and corresponds to a height of the sacrificial layer160forms a first sub-segment, and a remaining part that is of the second segment602and does not correspond to the sacrificial layer160forms a second sub-segment, such that the subsequently formed second gate oxide layer140forms gate oxide layers with different thicknesses at different positions of the second segment602.

After that, as shown inFIG.17andFIG.18, the first gate oxide layer130located on the top of the third segment603is removed through chemical mechanical polishing or etching, to expose the top surface of the active pillar60.

Still referring toFIG.17andFIG.18, the second gate oxide layer140is formed on a part of the sidewall of the second segment602and on the sidewall of the third segment603, in other words, the second gate oxide layer140is disposed on an outer side of a part that is of the first gate oxide layer130and corresponds to the second sub-segment and on an outer side of the first gate oxide layer130on the sidewall of the third segment603. A bottom surface of the second gate oxide layer140is connected to a top surface of the sacrificial layer160.

In some embodiments, the second gate oxide layer140may be formed on a sidewall of the second sub-segment of the second segment602and the sidewall of the third segment603by the ALD process.

Finally, referring toFIG.19andFIG.20, the sacrificial layer160is removed through etching. A sidewall of the second gate oxide layer140and a sidewall of the first gate oxide layer130originally covered by the sacrificial layer160form a second trench170.

In this embodiment, the ALD process is used to form the second gate oxide layer140on the second sub-segment of the second segment602and the sidewall of the first gate oxide layer130corresponding to the third segment603. A material of the second gate oxide layer140may include, but is not limited to, silicon dioxide, silicon monoxide, hafnium oxide, or titanium oxide. The second gate oxide layer140and the first gate oxide layer130may be made of a same material or different materials.

Before the second gate oxide layer140is formed, the sacrificial layer160is formed in the filling region150, and the sacrificial layer160covers a part of the second segment602, such that the length of the second gate oxide layer140in the first direction X is less than that of the first gate oxide layer130. In addition, in a process of forming the second gate oxide layer140, the thickness of the second gate oxide layer140is controlled to be greater than that of the first gate oxide layer130.

In the semiconductor structure, a GIDL current exists in a GAA transistor. The reason for this kind of transistor to generate the GIDL current is that a thickness of a gate oxide layer is small, which reduces a charge storage capability of the gate oxide layer. When the GAA transistor is in a static state, electrons generated by a gate or a small quantity of carrier fluids enter a drain of the transistor through the gate oxide layer, which causes a high electric field effect to the drain of the transistor, resulting in a leakage current at the drain. In this embodiment, the first gate oxide layer130and the second gate oxide layer140are successively formed on the sidewall of the second segment602of the active pillar60, such that the thicknesses of the gate oxide layers at different positions on the second segment602are different. This improves the charge storage capability of the gate oxide layer, prevents the electrons generated by the gate in the semiconductor structure or the small quantity of carrier fluids from entering the source or the drain of the semiconductor structure through the gate oxide layer, and reduces the GIDL current, thereby improving the performance and the yield of the semiconductor structure.

As shown inFIG.28, after the second gate oxide layer140is formed, a word line isolation structure180can further be formed in the second trench170. There are a plurality of word line isolation structures180that are disposed at intervals along the third direction Z.

In some embodiments, the word line isolation structure180may be formed by the following method:

Referring toFIG.21andFIG.22, an initial word line191is formed in the second trench170by the ALD process, the PVD process, or the CVD process. The initial word line191fills the second trench170. There are a plurality of initial word lines191that are disposed at intervals along the third direction Z.

Referring toFIG.23andFIG.24, a part of the initial word line191is removed through etching along the first direction X. An etching endpoint of the initial word line191is flush with a junction between the second segment602and the third segment603. The reserved initial word line191forms an intermediate word line192. A third trench200is formed between the intermediate word line192and the sidewall of the second gate oxide layer140.

Referring toFIG.25andFIG.26, a third initial dielectric layer211is formed in the third trench200by the ALD process, the PVD process, or the CVD process.

As shown inFIG.27, a part of the third initial dielectric layer211and a part of the intermediate word line192are removed through etching along the first direction X to form a plurality of fourth trenches220disposed at intervals along the third direction Z. A bottom of the fourth trench220exposes the top surface of the second dielectric layer100. The reserved third initial dielectric layer211forms a third dielectric layer210. The reserved intermediate word line192forms two word lines190disposed at intervals. A material of the third dielectric layer210includes, but is not limited to, silicon nitride, silicon dioxide, or silicon oxynitride. A material of the word line190includes, but is not limited to, tungsten or polycrystalline silicon. It should be noted that a thickness of a word line made of a material such as tungsten or polycrystalline silicon does not affect a potential of the word line.

As shown inFIG.28, the word line isolation structure180is formed in the fourth trench220by the ALD process, the PVD process, or the CVD process. A material of the word line isolation structure180includes a nitride, an oxide, a high-k dielectric material, or another suitable insulating material.

In some embodiments, a gate structure with dual work functions is generally obtained by depositing word line metal layers of different materials at the gate, but a process required for depositing the metal layers of different materials is relatively complex, and an isolation layer is required between the metal layers of different materials due to a diffusion problem.

In this embodiment, the word line190is formed by one deposition process and is made of metallic tungsten or polycrystalline silicon. In addition, the first gate oxide layer130is formed on the sidewalls of the second segment602and the third segment603, and then the second gate oxide layer140is formed on the first gate oxide layer130on the sidewall corresponding to the second sub-segment of the second segment602and on the sidewall corresponding to the third segment603, such that the thicknesses of the gate oxide layers at different positions of the segment section602are different, so as to achieve an effect of the dual work functions. This is not only simple in processing technology, but also is easier to control and realize. A thickness of a gate oxide layer that is of the second segment602and close to the third segment603is greater than that of a gate oxide layer that is of the second segment602and close to the first segment601. Therefore, when the transistor formed by the semiconductor structure in this embodiment, such as the GAA transistor, is used, a thickness of a gate oxide layer that is of the gate and close to the source increases. In order to turn on the transistor, an additional turn-on voltage VT of a source terminal increases, which correspondingly increases a potential of a part that is of the word line190and close to the third segment603, thereby forming a potential difference between the word lines190at two ends of the second segment602.

Further, when the additional turn-on voltage VT of the source terminal increases, a source voltage Vs of the source terminal increases. A relationship shown in the following formula exists between the turn-off current (I off) and the source voltage Vs, namely:
I off∝e−(Vs*ε/kt)

In the above formula, ε/kt represents a constant, which is about 0.0256. Therefore, when the source voltage Vs of the source terminal increases, the turn-off current (I off) decreases. Since the turn-off current and the source voltage Vs meet an exponential relationship of e, when the thickness of the gate oxide layer of the source terminal of the transistor increases, the turn-off current decreases exponentially, so as to facilitate the control of the turn-off current of the semiconductor structure, thereby reducing the GIDL current and interband tunneling of the semiconductor structure and improving the performance and the yield of the semiconductor structure.

Referring toFIG.28, in some embodiments, the thickness of the second gate oxide layer140is 1 to 2 times that of the first gate oxide layer130. Therefore, in this embodiment, the thickness of the gate oxide layer that is of the second segment602and close to the third segment603is 2 to 3 times that of the gate oxide layer that is of the second segment602and close to the first segment601. In a specific embodiment, the thickness of the second gate oxide layer140is 1.5 times that of the first gate oxide layer130. The above thickness ratio is set, such that the turn-off current of the semiconductor structure can be reduced by 6 orders of magnitude. In addition, the GIDL current and interband tunneling of the semiconductor structure are also reduced, thereby improving the performance and the yield of the semiconductor structure.

As shown inFIG.26andFIG.28, an exemplary embodiment of the present disclosure provides a semiconductor structure. The semiconductor structure includes a substrate10, an active pillar60, a first gate oxide layer130, and a second gate oxide layer140.

For example, there are a plurality of active pillars60that are arranged as an array in the substrate10. Along a first direction X, the active pillar60includes a first segment601, a second segment602, and a third segment603that are sequentially connected.

The first gate oxide layer130covers sidewalls of the second segment602and the third segment603.

The second gate oxide layer140is disposed on an outer side of the first gate oxide layer130. Along the first direction X, a length of the second gate oxide layer140is less than that of the first gate oxide layer130. A top surface of the second gate oxide layer140is flush with that of the third segment603. A thickness of the second gate oxide layer140is greater than that of the first gate oxide layer130. In some embodiments, the thickness of the second gate oxide layer140is 1 to 2 times that of the first gate oxide layer130.

In this embodiment, the first gate oxide layer is formed on the sidewalls of the second segment and the third segment of the active pillar, and the second gate oxide layer is formed on the first gate oxide layer, so as to increase a thickness of a gate oxide layer of the active pillar and a charge storage capability of the gate oxide layer, and effectively reduce a GIDL current and interband tunneling. In addition, the length of the second gate oxide layer is less than that of the first gate oxide layer, the thickness of the second gate oxide layer is greater than that of the first gate oxide layer, and the top surface of the second gate oxide layer is flush with that of the third segment, such that two gate oxide layers with different thickness are formed at different positions of the second segment, and a thickness of a gate oxide layer formed on the third segment is the same as that of the thicker gate oxide layer on the second segment, to make potentials at both ends of the second segment different. This is conducive to controlling a turn-off current of the semiconductor structure and effectively improving performance and a yield of the semiconductor structure.

As shown inFIG.26, in some embodiments, the semiconductor structure further includes a plurality of bit lines90disposed on the substrate10. The bit lines90are disposed at intervals along a second direction Y, and are located below the active pillars60. The bit line90is connected to first segments601of a plurality of active pillars60that are along a third direction Z and in a same straight line. A top surface of the bit line90is provided with a second dielectric layer100.

As shown inFIG.26, in some embodiments, the semiconductor structure further includes a plurality of bit line isolation structures70disposed on the substrate10. The bit line isolation structures70are disposed at intervals along the second direction Y. The bit line isolation structure70includes a first dielectric layer80and a first isolation layer120. The first dielectric layer80is located between the substrate10and the bit line90. The first isolation layer120is located between adjacent bit lines90. The bit line isolation is structure70is used to realize insulation between adjacent bit lines90subsequently formed in the substrate10, and ensure the performance and the yield of the semiconductor structure.

As shown inFIG.28, in some embodiments, the semiconductor structure further includes word lines190disposed in the substrate10. Each of the word lines190is disposed around the second segment602of the active pillar60. The word lines190include a first word line and a second line, a bottom surface of the first word line is close to the first segment601, and a top surface of the second word line is close to the third segment603. With a plane perpendicular to the second direction Y as a longitudinal section, area of a longitudinal section of the first word line is greater than that of a longitudinal section of the second word line. It should be noted that a junction between the first word line and the second word line may be flush with a bottom surface of the second gate oxide layer140.

The first word line and the second word line may be formed by one deposition process or by a plurality of deposition processes. In some embodiments, the first word line and the second word line are made of a same material.

As shown inFIG.28, in some embodiments, the semiconductor structure further includes a plurality of word line isolation structures180disposed in the substrate10. The word line isolation structure180is located between adjacent word lines190, a top surface of the word line190is provided with a third dielectric layer210, and a top surface of the third dielectric layer210is flush with a top surface of the active pillar60. The word line isolation structure180is used to realize insulation between adjacent word lines190, and ensure the performance and the yield of the semiconductor structure.

It should be noted that in the description of the present disclosure, the terms such as “center”, “top”, “bottom”, “left”, “right”, “vertical”, “horizontal”, “inner” and “outer” indicate the orientation or position relationships based on the accompanying drawings. These terms are merely intended to facilitate description of the present disclosure and simplify the description, rather than to indicate or imply that the mentioned apparatus or element must have a specific orientation and must be constructed and operated in a specific orientation. Therefore, these terms should not be construed as a limitation to the present disclosure.

It can be understood that the terms such as “first” and “second” used in the present disclosure can be used to describe various structures, but these structures are not limited by these terms. Instead, these terms are merely intended to distinguish one structure from another.

The same elements in one or more accompanying drawings are denoted by similar reference numerals. For the sake of clarity, various parts in the accompanying drawings are not drawn to scale. In addition, some well-known parts may not be shown. For the sake of brevity, a structure obtained by implementing a plurality of steps may be shown in one figure. In order to understand the present disclosure more clearly, many specific details of the present disclosure, such as the structure, material, size, processing process, and technology of the device, are described below. However, as those skilled in the art can understand, the present disclosure may not be implemented according to these specific details.

Finally, it should be noted that the above embodiments are merely intended to explain the technical solutions of the present disclosure, rather than to limit the present disclosure. Although the present disclosure is described in detail with reference to the above embodiments, those skilled in the art should understand that they may still modify the technical solutions described in the above embodiments, or make equivalent substitutions of some or all of the technical features recorded therein, without deviating the essence of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present disclosure.

INDUSTRIAL APPLICABILITY

In the manufacturing method of a semiconductor structure and the semiconductor structure provided in the embodiments of the present disclosure, two gate oxide layers with different thicknesses are formed at different positions on a second segment of an active pillar, and a thickness of a gate oxide layer formed on a third segment is the same as that of the thicker gate oxide layer on the second segment, to effectively reduce a GIDL current, and improve performance and a field of the semiconductor structure.