Patent ID: 12224261

DETAILED DESCRIPTION

One or more embodiments are described with reference to the enclosed figures. While specific configurations and arrangements are depicted and discussed in detail, it should be understood that this is done for illustrative purposes only. Persons skilled in the relevant art will recognize that other configurations and arrangements are possible without departing from the spirit and scope of the description. It will be apparent to those skilled in the relevant art that techniques and/or arrangements described herein may be employed in a variety of other systems and applications other than what is described in detail herein.

Reference is made in the following detailed description to the accompanying drawings, which form a part hereof and illustrate exemplary embodiments. Further, it is to be understood that other embodiments may be utilized, and structural and/or logical changes may be made without departing from the scope of claimed subject matter. It should also be noted that directions and references, for example, up, down, top, bottom, and so on, may be used merely to facilitate the description of features in the drawings. Therefore, the following detailed description is not to be taken in a limiting sense and the scope of claimed subject matter is defined solely by the appended claims and their equivalents.

In the following description, numerous details are set forth. However, it will be apparent to one skilled in the art, that the embodiments herein may be practiced without these specific details. In some instances, well-known methods and devices are shown in block diagram form, rather than in detail, to avoid obscuring the embodiments herein. Reference throughout this specification to “an embodiment” or “one embodiment” or “some embodiments” means that a particular feature, structure, function, or characteristic described in connection with the embodiment is included in at least one embodiment herein. Thus, the appearances of the phrase “in an embodiment” or “in one embodiment” or “some embodiments” in various places throughout this specification are not necessarily referring to the same embodiment. Furthermore, the particular features, structures, functions, or characteristics may be combined in any suitable manner in one or more embodiments. For example, a first embodiment may be combined with a second embodiment anywhere the particular features, structures, functions, or characteristics associated with the two embodiments are not mutually exclusive.

As used in the description and the appended claims, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will also be understood that the term “and/or” as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.

The terms “coupled” and “connected,” along with their derivatives, may be used herein to describe functional or structural relationships between components. It should be understood that these terms are not intended as synonyms for each other. Rather, in particular embodiments, “connected” may be used to indicate that two or more elements are in direct physical, optical, or electrical contact with each other. “Coupled” may be used to indicated that two or more elements are in either direct or indirect (with other intervening elements between them) physical or electrical contact with each other, and/or that the two or more elements co-operate or interact with each other (e.g., as in a cause and effect relationship).

The terms “over,” “under,” “between,” and “on” as used herein refer to a relative position of one component or material with respect to other components or materials where such physical relationships are noteworthy. For example, in the context of materials, one material or material disposed over or under another may be directly in contact or may have one or more intervening materials. Moreover, one material disposed between two materials or materials may be directly in contact with the two layers or may have one or more intervening layers. In contrast, a first material or material “on” a second material or material is in direct contact with that second material/material. Similar distinctions are to be made in the context of component assemblies.

As used throughout this description, and in the claims, a list of items joined by the term “at least one of” or “one or more of” can mean any combination of the listed terms. For example, the phrase “at least one of A, B or C” can mean A; B; C; A and B; A and C; B and C; or A, B and C.

The term “circuit” or “module” may refer to one or more passive and/or active components that are arranged to cooperate with one another to provide a desired function. The term “signal” may refer to at least one current signal, voltage signal, or magnetic signal. The terms “substantially”, “close”, “approximately”, “near”, and “about” generally refer to being within +/−10 percent of a target value.

Various implementations of the embodiments herein may be formed or carried out on a substrate, such as a package substrate. In some embodiments, a package substrate may comprise any suitable type of substrate capable of providing electrical communications between an electrical component, such as an integrated circuit (IC) die, and a next-level component to which an IC package may be coupled (such as a circuit board, for example). In other embodiments, the substrate may comprise any suitable type of substrate capable of providing electrical communication between an IC die and an upper IC package coupled with a lower IC/die package, and in some embodiments, a substrate may comprise any suitable type of substrate capable of providing electrical communication between an upper IC package and a next-level component to which an IC package is coupled.

A substrate may also provide structural support for a device, such as a die. By way of example, in some embodiments, a substrate may comprise a multi-layer substrate—including alternating layers of a dielectric material and metal—built-up around a core layer (either a dielectric or a metal core), and may include through via structures that extend through the core. In other embodiments, a substrate may comprise a coreless multi-layer substrate, in which case through via structures may be absent. Other types of substrates and substrate materials may also find use with the disclosed embodiments (e.g., ceramics, sapphire, glass, etc.). Further, according to some embodiments, a substrate may comprise alternating layers of dielectric material and metal that are built-up over a die itself—this process is sometimes referred to as a “bump-less build-up process.” Where such an approach is utilized, conductive interconnects may or may not be needed (as the build-up layers may be disposed directly over a die/device, in some cases).

A die may include a front-side and an opposing back-side, and may be an integrated circuit die and/or an integrated circuit device, in some embodiments. In some embodiments, one or both of the front-side or the back-side of a die may be referred to as the “active surface” of the die. A number of interconnects may extend from the die's front-side and/or back-side to an underlying substrate and/or and overlaying substrate respectively, and these interconnects may electrically couple the die and one or more substrates. In some cases a die may be directly coupled to a board, such as a motherboard. Interconnects/traces may comprise any type of structure and materials capable of providing electrical communication between a die and substrate/board. In some embodiments, a die may be disposed on a substrate in a flip-chip arrangement. In some embodiments, interconnects comprise an electrically conductive terminal on a die (e.g., a pad, bump, stud bump, column, pillar, or other suitable structure or combination of structures) and a corresponding electrically conductive terminal on the substrate (e.g., a pad, bump, stud bump, column, pillar, or other suitable structure or combination of structures).

Solder (e.g., in the form of balls or bumps) may be on the terminals of a substrate and/or die, and these terminals may then be joined using a solder reflow process, for example. Of course, it should be understood that many other types of interconnects and materials are possible (e.g., wirebonds extending between a die and a substrate). In some embodiments herein, a die may be coupled with a substrate by a number of interconnects in a flip-chip arrangement. However, in other embodiments, alternative structures and/or methods may be utilized to couple a die with a substrate, where solder may not be used, as will be further described herein.

Described herein are embodiments of microelectronic package structures having mixed hybrid bonding interfaces. In an embodiment, a composite organic dielectric layer may be on a substrate, such as a low CTE carrier substrate, for example. The composite organic dielectric layer may comprise an organic dielectric layer filled with an inorganic filler material, such as silica, for example. One or more conductive substrate interconnect structures may be disposed within the composite organic dielectric layer. A die may be on the composite organic dielectric layer, the die having one or more conductive die interconnect structures within a die dielectric material/layer. The one or more conductive die interconnect structures are directly bonded to the one or more conductive substrate interconnect structures, and the inorganic filler material of the composite organic dielectric material is directly bonded (e.g.,covalently) to the die dielectric material, wherein the covalent bonding occurs after subsequent temperature processing of the microelectronic package structure. The metal to metal bonding of the conductive interconnect structures (which takes place after the dielectric covalent bonding is created) is accomplished without the use of solder or underfill materials. The composite organic dielectric layer comprises a CTE, in a direction normal to the bonding interface, that is substantially lower than a CTE of the conductive interconnect structures of the die and substrate. Pitch scaling between die interconnect structures is enabled for pitches well below 50 microns.

The composite organic dielectric layer may have a CTE, in a direction normal to the bonding interface plane, that is substantially lower than a CTE of the conductive interconnect structures of the die and substrate. The CTE of the composite organic dielectric layer in the in-plane direction may be optimized to reduce the CTE mismatch between the die and the substrate. By decreasing the CTE mismatch, yield and reliability are improved and the pitch of the interconnects may be reduced. Direct metal to metal bonding of the conductive substrate interconnect structures to the conductive die interconnect structures is enabled, without the use of solder or underfill materials after the dielectric bonds between the two interface surfaces are formed. Pitch scaling between die interconnect structures is enabled for pitches below 50 microns.

FIG.1Ais a cross-sectional view of a portion of a mixed hybrid bonding structure10, arranged in accordance with some embodiments of the present disclosure. The mixed hybrid bonding structure10comprises a substrate104and a die114. The die114, which may comprise any suitable type of die/device may include any number of circuit elements, such as any type of transistor elements and/or passive elements. The die114may comprise N-type and/or P-type transistors, which may include materials such as silicon, germanium, indium, antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide, for example. The die may include such structures as planar transistors and/or nonplanar transistors, FinFET transistors, nanowire transistors and/or nanoribbon transistors.

The die114may comprise a die bonding layer120. The die bonding layer may comprise an inorganic dielectric material116with conductive die interconnect structures disposed118therein, in an embodiment. The inorganic dielectric material116may comprise any suitable inorganic dielectric material, such as inorganic dielectric materials comprising silicon, nitrogen, carbon or oxygen, and combinations thereof, for example. One or more conductive die interconnect structures118may be within the inorganic dielectric layer116. The one or more conductive die interconnect structures118may comprise any suitable conductive material, such as copper, ruthenium, titanium, tantalum, or cobalt, for example, and combinations thereof. Individual ones of the one or more conductive die interconnect structures118may comprise a surface126. In an embodiment, the surface126may be slightly recessed below surface124of the dielectric material116of the die bonding layer120. For example, the surface126may be about 1 nm to about 10 nm below the surface124of the die dielectric material116, in some cases.

The one or more conductive die interconnect structures118are separated from each other by the inorganic dielectric material116. In an embodiment, a pitch129between adjacent individual ones of the conductive die interconnect structures118may comprise about 50 microns or below. In other embodiments, the pitch129may be greater than 50 microns, depending upon the particular application. The substrate104may comprise a substrate bonding layer102that is on a platform119. The platform119may comprise any suitable platform, such as a carrier or a handle wafer, and may comprise such materials as silicon, a glass material, III-V materials, or multi-layer organic materials on a low CTE carrier. The substrate bonding layer102of the substrate104may comprise a composite organic dielectric layer107and one or more conductive substrate interconnect structures112. The one or more conductive substrate interconnect structures112may comprise any suitable conductive material, such as copper, ruthenium, titanium, tantalum, or cobalt, for example, and combinations thereof. Individual ones of the one or more conductive substrate interconnect structures112may comprise a top surface113.

A composite dielectric layer107(which has a top surface110) comprises a plurality of inorganic filler material/particles108that are disposed within an organic dielectric material/layer106. The organic dielectric material106may comprise such materials as mold compounds, epoxy resin systems such as build up materials, aromatic polymers, polyimides, perflourocyclobutane (PFCB) materials, benzocyclobutene (BCB) materials, or combinations thereof. In other embodiments, the organic dielectric material106may comprise spin on glass or sol-gel systems with low CTE filler material.

In an embodiment, the inorganic filler materials108may comprise silica materials, such as silica particles, low CTE dielectric fibers, dielectric particles, or platelets, silicon nitride, silicon dioxide, silicon carbide, silicon carbide nitride, aluminum oxide, diamond particles (such as CVD diamond particles), or combinations thereof. In an embodiment, the composite dielectric layer107may comprise between about 70 to about 95 percent by weight of the inorganic filler material108. The percentage by weight of the inorganic filler material108can be optimized to produce a low CTE of the composite dielectric layer107of the substrate bonding layer102. In an embodiment, the CTE of the composite dielectric layer107may comprise between about 0.5 ppm per degrees Celsius to about 10 ppm per degrees Celsius. The CTE of the composite dielectric layer107is optimized to be significantly smaller than the CTE of the conductive interconnects112,118in the bonding direction (out of plane). Furthermore, the in-plane CTE mismatch between the die114and the substrate104is minimized, in some cases by the use of a low CTE carrier substrate119, to enable smaller conductive interconnect bonding layer pitch129. In an embodiment, the CTE of the conductive interconnects118,112is greater than about 30 percent of the CTE of the composite organic dielectric layer107in the bonding direction. The die bonding layer120is directly on and electrically coupled to the substrate bonding layer102.

InFIG.1B(depicting a cross-sectional portion of the interface between the die bonding layer120and the substrate bonding layer102), a covalent bonding region130is disposed between the top surface124of the inorganic dielectric material116of the die bonding layer120and the top surface110of the substrate bonding layer102. In an embodiment, one or more of the plurality of inorganic filler material108of the substrate bonding layer102may form inorganic covalent bonds131with the inorganic dielectric material116of the die bonding layer120. Additionally, the conductive die interconnect structures118and the conductive substrate interconnect structures112form direct metallic bonds133with each other in a metallic bond region132. Thus, by utilizing a mixed hybrid bonding process according to the embodiments described herein, wherein the substrate and die are bonded together using both metallic bonds133and inorganic dielectric bonds131, bonding may occur without the use of solder materials at die to organic interfaces. There is an absence of underfill materials and an absence of seed layer plating materials on the conductive die and substrate interconnect structures (as well as between the die bonding layer120and substrate bonding layer120interface127), since plating, solder and underfill materials are not necessary to bond the conductive interconnect structures to each other. The composite dielectric layer107comprises a CTE121, in a direction normal to the plane of the bonding interface127, that is substantially lower than a CTE123(in a direction normal to the plane of the bonding interface127) of the conductive interconnect structures of the die and the substrate.

InFIG.1C, a cross-sectional view of a portion of a mixed hybrid bonding structure12is depicted in accordance with some embodiments of the present disclosure. The mixed hybrid bonding structure12comprises a substrate104and a die114. The die114comprises a die bonding layer120comprising an inorganic dielectric material116, wherein or more conductive die interconnect structures118are disposed within the inorganic dielectric layer116. The one or more conductive die interconnect structures118comprise a top surface126, wherein the top surfaces126may be directly on the top surfaces113of the conductive substrate interconnect structures112.

In an embodiment, a coating layer111, which may comprise an inorganic layer111, may be on the surface of the composite dielectric layer107(which is similar to the composite dielectric material ofFIG.1A, for example). The inorganic layer111may comprise a thickness of between about 10 nm to about 1600 nm, in an embodiment. The coating layer111may comprise such materials as silicon, oxygen, nitrogen, or carbon, and combinations thereof, in an embodiment. The coating layer111may comprise a such materials as a physical vapor deposition (PVD) material, an atomic layer deposition (ALD) material, a chemical vapor deposition (CVD) and in some instances include pulsed laser annealing, or a spin on dielectric material. The coating layer111may be directly on the organic dielectric material106, which includes the inorganic filler material108, such that particles of the inorganic filler material108may be in direct contact with the coating layer111, and may be covalently bonded to the coating layer111.

In an embodiment, the coating layer111is on the organic dielectric material106, but is not on the top surfaces113of the conductive substrate interconnect structures112, and is on a portion of the sidewalls of the conductive substrate interconnect structures112. The coating layer111is on the top surface of the die bonding layer120. The inorganic layer111is covalently bonded to the inorganic dielectric material116, and the die interconnect structures118are directly bonded to the substrate interconnect structures112, without the use of solder or underfill materials. The CTE of the composite dielectric layer107including the plurality of inorganic filler material108, is less than the CTE of the conductive interconnect structures of the die and substrate112,118in the direction normal to the bond-interface plane.

InFIG.1D, a cross-sectional view of a portion of a hybrid bonding structure14is depicted in accordance with some embodiments of the present disclosure. The mixed hybrid bonding structure14comprises a substrate104and a die114. The die114comprises a die bonding layer120comprising a composite dielectric layer107, wherein a plurality of inorganic filler material108is disposed within an organic dielectric material106. In an embodiment, the composite dielectric layer107of the die bonding layer120and the composite dielectric layer of the substrate bonding layer102may comprise between about 70 to about 95 percent by weight of the inorganic filler material108. One or more conductive die interconnect structures118are within the composite dielectric layer107of the die bonding layer120.

The one or more conductive die interconnect structures118are separated from each other by the composite dielectric layer107. The substrate bonding layer102of the substrate104comprises the composite dielectric layer107, wherein a plurality of inorganic filler material108is within the organic dielectric material106. The composite dielectric layer107of the die bonding layer120is on the top surface110of the substrate bonding layer102, wherein the inorganic filler material108of the die bonding layer120is covalently bonded to the inorganic filler material108of the substrate bonding layer102, and the die interconnect structures118are directly bonded to the substrate interconnect structures112, without the use of solder or underfill materials. The CTE of the composite dielectric layer107of the substrate bonding layer and the CTE of the composite dielectric layer107of the die bonding layer120are less than the CTE of the conductive interconnect structures of the die and substrate112,118in the direction normal to the bond-interface plane.

In an embodiment, the composite dielectric layer107of the die bonding layer120may comprise substantially the same materials as the composite dielectric layer107of the substrate bonding layer, but in other embodiments, the materials may be different from each other. Thus, by utilizing a hybrid bonding process according to the embodiments described herein, wherein the substrate and die are bonded together using both metallic bonds and inorganic dielectric bonds, bonding may occur without the use of solder materials at die to organic interfaces. There is an absence of underfill materials, solder materials and an absence of seed layer plating materials at the die bonding layer120and substrate bonding layer102interface, since these materials are not necessary to bond the conductive interconnect structures to each other.

InFIG.1E, a cross-sectional view of a portion of a mixed hybrid bonding structure16is depicted in accordance with some embodiments of the present disclosure. The mixed hybrid bonding structure16comprises a substrate104and a die114. The die114comprises a die bonding layer120comprising an inorganic dielectric material116. One or more conductive die interconnect structures118are disposed within the inorganic dielectric material116. The one or more conductive die interconnect structures118may comprise a top surface126.

The one or more conductive die interconnect structures118are separated from each other by the inorganic dielectric material116. In an embodiment, the substrate bonding layer102of the substrate104comprises a first portion115, wherein the first portion115comprises a composite dielectric material107, wherein a plurality of inorganic filler material108is disposed within an organic dielectric material106. A second portion125of the substrate bonding layer102comprises an inorganic dielectric material117that is free of the inorganic filler material108. In an embodiment, the inorganic filler materials108of the first portion115of the substrate bonding layer102may comprise silica materials, such as silica particles, low CTE dielectric fibers, particles, or platelets, silicon nitride, silicon oxide, silicon carbide, silicon carbide nitride. In an embodiment, the composite dielectric layer107of the first portion115of the substrate bonding layer102may comprise between about 70 to about 95 percent by weight of inorganic filler materials. The CTE of the composite dielectric layer107of the first portion115of the substrate bonding layer102may be optimized according to a particular device/system design requirements.

The inorganic dielectric layer116of the die bonding layer120is on the top surface of the substrate bonding layer102, wherein the inorganic dielectric material116of the die bonding layer120is covalently bonded to the inorganic filler material108of the first portion115of the substrate bonding layer102, and the inorganic dielectric layer116of the die bonding layer120is also covalently bonded to the inorganic dielectric material117of the second portion125of the substrate bonding layer102. The die interconnect structures118are directly bonded to the substrate interconnect structures112, without the use of solder or underfill materials. The CTE of the composite dielectric layer107of the substrate bonding layer102is less than the CTE of the conductive interconnect structures of the die and substrate112,118in the direction normal to the bonding interface plane. Additionally, the conductive die interconnect structures118and the conductive substrate interconnect structures112form direct metallic bonds to each other. There is an absence of underfill materials and an absence of seed layer plating materials on the conductive die and substrate interconnect structures (at the interfaces between top surfaces126and113of the die and substrate conductive interconnect structures118,112), since plating is not necessary to bond the conductive interconnect structures to each other.

InFIG.1F, a perspective view of a package structure151is depicted, according to an embodiment. A first die140is embedded within a composite dielectric layer or layers107, wherein the first die140may be coupled, both electrically and physically, to interconnect structures (not shown) that are within the composite dielectric layer107This composite organic dielectric layer107is attached to a package substrate150. A first side156of the composite layer107is on the package substrate150. The composite dielectric layer107may comprise a die bonding layer on a second side156, opposite side158, according to any of the embodiments described herein. A second and third die142,142′ are on the second side158of the composite dielectric layer107, and are physically and electrically coupled to interconnect structures (not shown) within the composite dielectric layer107. The second and third die142,142′ may include die bonding layers120,120′, wherein the die bonding layers120,120′ are on the second side158of the composite dielectric layer107(FIG.1G, cross-sectional view). The die bonding layers120,120′ may encompass any of the embodiments of the die bonding layers120described herein. A dielectric layer of the die bonding layer120may be covalently bonded to an organic filler material (not shown) of the composite dielectric layer107. Conductive interconnect structures (not shown, but encompassing any of the embodiments of the die bonding layers included herein) within the die bonding layers of the die142,142′ and conductive interconnect structures within the composite dielectric layer107(not shown) are bonded together with metal bonding, as shown onFIG.1B, for example.

InFIG.1H, a perspective view of a package structure153is depicted, according to an embodiment. A first side156of a composite dielectric layer107is physically and electrically coupled by interconnect structures (not shown) within the composite dielectric layer107to a package substrate150. A first die142and a second die142′ are embedded within the composite dielectric layer107, and may be adjacent to each other. The composite dielectric layer107may comprise a substrate bonding layer102according to any of the embodiments described herein. A third die143may comprise a die bonding layer120according to any of the embodiments herein, wherein the die bonding layer120is on the substrate bonding layer102of the organic composite layer107(FIG.1I, cross-sectional view). Dielectric layers of the die bonding layer120may be covalently bonded to the inorganic filler material (not shown) of the composite dielectric layer107. Conductive interconnect structures within the die bonding layer120and conductive substrate interconnect structures within the composite dielectric layer107are bonded together with dielectric and metal bonding, as shown inFIG.1B, for example.

InFIG.1J, a perspective view of a package structure155is depicted, according to an embodiment. A first die142and a second die142′ are on a second side158of a composite dielectric layer107, and are physically and electrically coupled by interconnect structures (not shown) within the composite dielectric layer107. A first side156of the composite dielectric layer107is physically and electrically coupled by interconnect structures (not shown) within the composite dielectric layer107to a package substrate150. The first and second die142,142′ may comprise die bonding layers120,120′, wherein the die bonding layers120,120′ are on the second side158of the composite dielectric layer107(FIG.1IK, cross-sectional view). The die bonding layers120,120′ may include any of the embodiments of the die bonding layers120described herein. The dielectric layers of the die bonding layer120may be covalently bonded to the inorganic filler material (not shown) of the composite dielectric layer107. The conductive interconnect structures of the die and the composite dielectric layer107(not shown) are bonded together with dielectric and metal bonding, as shown onFIG.1B, for example.

FIGS.2A-2Edepict cross-sectional views of a method of forming mixed hybrid bonding package structures according to embodiments. InFIG.2A, a portion of a package structure204is shown. A build up substrate162, such as a damascene build up or a redistribution layer, for example, may be on a carrier/handle160, such as a silicon carrier, or any other suitable carrier material. The build up substrate162may comprise conductive and dielectric materials, which may be patterned according to a particular application, in some embodiments. For example, the build up substrate162may include conductive interconnect structures/routing layers219that are within dielectric layer(s), which may be configured to route electrical signals between any number of dice, in some embodiments.

For example, interconnect structures may include routing structures such as pads or traces configured to receive electrical signals to and from devices. In some embodiments, conductive interconnect structures/routing layers comprise trenches, ground planes, power planes, re-distribution layers (RDLs), and/or any other appropriate electrical routing features. The build up substrate162may also provide structural support for discrete components and/or any other type of device. A die264, may be on the build up substrate162. The die264may comprise any suitable die such as a central processing unit. In some embodiments, the die264, may include a processing system (either single core or multi-core). In some embodiments, the die106may be a microprocessor, a graphics processor, a signal processor, a network processor, a chipset, a memory device, or any type of passive device etc. In some embodiments, the die264may be a system-on-chip (SoC) having multiple functional units (e.g. one or more processing units, one or more graphics units, one or more communications units, one or more signal processing units, one or more security units, etc.). Adjacent to the die264, and on the build up substrate262, are one or more substrate conductive interconnect structures212.

InFIG.2B, a formation process201, such as a composite dielectric material formation process201, may be employed to form a composite dielectric layer107, which comprises an organic dielectric material106filled with inorganic filler material, such as an inorganic filler material comprising silica materials, such as silica particles, low CTE dielectric fibers, dielectric particles, or platelets, silicon nitride, silicon dioxide, silicon carbide, silicon carbide nitride, aluminum oxide, diamond particles, or combinations thereof, for example. The CTE of the composite dielectric layer107is much less than the CTE of the conductive interconnect structures212. The formation process201may include such formation techniques as CVD, PVD, ALD, spin on techniques, layer-by-layer deposition with laser pulsed annealing or thermal annealing, transfer or compression molding, or vacuum lamination, and may utilize such materials as mold compound materials, epoxy materials, silsesquioxane, spin on glass materials, which are filled with an inorganic filler material such as silica particles, for example. The composite dielectric layer107may comprise a thickness of about 5 to about 200 microns, and may comprise about 70 to about 95 percent by weight of the inorganic filler material108. Individual particles of the inorganic filler material108may comprise a diameter of between about 0.002 microns to about 12 microns.

InFIG.2C, a planarization process203may be performed on a top surface110of the composite dielectric layer107, and on the top surface213of the substrate interconnect structures212as well as on the die264. The planarization process203may comprise a chemical mechanical polishing (CMP) process, in an embodiment, where a topography of the surfaces of the die, composite dielectric layer107, and the substrate interconnect structures212may be optimized for a particular application. For example, a smoothness of the surface110of the composite dielectric layer107and the inorganic dielectric layer of264may be tuned by varying such planarization parameters as slurry composition, rotation rate, pressure, and/or time, etc. In an embodiment, the amount of root-mean-square roughness of the composite dielectric layer107may be less than about 0.5 nm, but is dependent upon optimization of the planarization process203. The amount of dishing recess of the surface213of the conductive interconnect structures212and interconnect structures on the die264may be tuned as well by varying the planarization process203parameters, such as the slurry chemistry, for example. Upon performing the planarization process203, some of the inorganic filler material108at the surface of the composite dielectric layer107may be exposed, and the surfaces of the conductive substrate interconnect structures212may be exposed as well. The surfaces of the conductive substrate interconnect structures may be recessed slightly from the surface of the composite dielectric layer107and from the inorganic dielectric layer of the die264.

InFIG.2D, a die attach process205may be employed to attach a die114to the portion of the substrate204. The die114may comprise a die bonding layer120, similar to the die bonding layer120ofFIG.1A, in an embodiment. The die bonding layer120may include a dielectric layer116, which may be an inorganic dielectric layer, and one or more die interconnect structures118. A top surface126of the conductive die interconnect structure118may be bonded, by metallic bonding, with a top surface213of the substrate conductive interconnect structure212.

A top surface110of the composite dielectric layer107may be bonded with a top surface124of the dielectric material116of the die bonding layer120. In an embodiment, the dielectric material116of the die bonding layer120and the inorganic filler material108of the composite dielectric layer107(and of the dielectric of die264, in some embodiments) may form covalent bonds with each other initially, and then the conductive metal bonding of the die and conductive interconnect structures118,112may occur during subsequently prescribed temperature processing. In this manner, by utilizing both inorganic covalent bonding within an organic dielectric and metal to metal bonding with which to bond the die114to the substrate204, the use of solder and underfill material is not necessary, since the die attach process205is completed by the use of the mixed hybrid bonding processes disclosed herein.FIG.2Edepicts an embodiment of a portion of a package structure270wherein the carrier160has been removed, and a plurality of solder interconnect structures152are formed between a package substrate170and the conductive interconnects of the organic substrate204.

FIG.2Fdepicts an embodiment wherein a coating layer267may be selectively formed on the composite dielectric layer107, or where the coating layer267may be formed over the entire surface of the substrate204, and then subsequently patterned and/or planarized. The coating layer267may comprise an inorganic material, such as an inorganic dielectric material, for example. The coating layer267may be formed at a temperature below the degradation temperature of the organic dielectric material106of the composite dielectric layer107, or at a temperature surpassing the degradation temperature but for extremely short durations (such as micro-seconds) typical of a pulsed laser annealing process, for example The coating layer267may be formed by one or more of a PVD, an ALD, a CVD, or a spin on process, with or without a thermal anneal. Subsequent to formation of the coating layer267, the coating layer267may be optionally pulse laser annealed. The coating layer267forms a bond with the composite dielectric layer107. InFIG.2G, a die attach process205may be employed to attach a die114to the portion of the substrate204and the die264, including the coating layer267that spans the two features. The die114may comprise a die bonding layer120, similar to the die bonding layer120ofFIG.1A, in an embodiment. The die bonding layer120may include a dielectric layer116, which may be an inorganic dielectric layer, and one or more die interconnect structures118. A top surface126of the conductive die interconnect structure118may be bonded, by metallic bonds, with a top surface213of the substrate conductive interconnect structure212. The coating layer267may bond with the inorganic dielectric116of the die114.

FIGS.3A-3Fdepict cross-sectional views of a method of forming hybrid bonding package structures according to embodiments. InFIG.3A, a portion of a substrate structure304is shown. A build up substrate162, such as a damascene build up or a redistribution layer (RDL) for example, may be on a carrier/handle160, such as a silicon carrier, or any other suitable carrier material. The build up substrate162may comprise conductive and dielectric materials, which may be patterned according to design requirements of a particular application, in some embodiments. A die364, may be on the build up substrate162. The die364may comprise any suitable die such as a cpu, for example.

InFIG.3B, a formation process301, such as a composite dielectric material formation process301, may be employed to form a composite dielectric layer107, which comprises an organic dielectric material filled with inorganic filler material, such as an inorganic filler material108comprising silica particles, for example. The CTE of the composite dielectric layer107is much less than the CTE of conductive interconnect structures to be formed subsequently in the direction normal to the interface plane. The formation process301may include such formation techniques as CVD, PVD, ALD, spin on techniques, transfer or compression mold, and/or vacuum lamination, and may utilize such materials as mold compound materials, epoxy materials, silsesquioxane, spin on glass materials, which are filled with an inorganic filler material such as silica particles, for example.

InFIG.3C, a removal process303, such as an etching process, for example, may be employed to remove a portion of the composite dielectric layer107to form one or more openings366. The removal process303may expose one or more conductive traces163in the build up layer162. InFIG.3D, a metal formation process305may be employed. In an embodiment, a thin seed layer and optionally a barrier layer (not shown) may first be formed within the one or more openings366. The seed layer and/or barrier layers may comprise any suitable conductive materials such as copper alloy materials, titanium, tantalum, tantalum nitride, or combinations thereof, for example, and may be formed by a sputtering process, a physical deposition process, or any other suitable formation process. The seed layer may comprise a thickness of 10 nm to 400 nm, in an embodiment, and may comprise a conductive metal such as a copper alloy. A subsequent electroplating process then fills the one or more openings366with a conductive material, such as copper, to form one or more substrate conductive interconnect structures312. A portion of the conductive metal367may be over the top surface368of the portion of the substrate304.

InFIG.3E, a metal planarization process307may be performed on the top surface368of the conductive material367, so that top surfaces of the conductive interconnect structures312and those of the die264may be slightly recessed from the top surface110of the composite dielectric layer107as well as slightly recessed from the top surface of the dielectric material of the die264. The planarization process307may comprise a chemical mechanical polishing (CMP) process, in an embodiment, where a topography of the top surfaces108of the conductive interconnect structures and the composite dielectric layer107may be optimized for a particular application. For example, a smoothness of the surface108of the composite dielectric material may be tuned by varying such planarization parameters as slurry composition, rotation rate, time, etc.

In an embodiment, the amount of root-mean-square roughness of the composite dielectric layer107may be less than about 0.5 nm. Similarly, the amount of recess or dishing of the surface of the conductive interconnect structures312may be tuned as well by varying the planarization process307parameters, such as the slurry chemistry, for example. Upon performing the planarization process307, some of the inorganic filler material108at the surface of the composite dielectric layer107may be exposed as well as the dielectric of the die364, and the surfaces of the conductive substrate interconnect structures312may be exposed as well those on die364. In some cases, the surfaces of the conductive substrate interconnect structures may be recessed slightly from the surface of the composite dielectric material.

InFIG.3F, a die attach process309may be employed to attach a die114to the portion of the substrate204. The die114may comprise a die bonding layer120, similar to the die bonding layer120ofFIG.1A, in an embodiment. The die bonding layer120may include a dielectric layer116, which may be an inorganic dielectric layer, and one or more die interconnect structures118. A top surface126of the conductive die interconnect structure118may be bonded, by metallic bonds, with a top surface113of the substrate conductive interconnect structure312.

A top surface110of the composite dielectric material106and that of the die364may be bonded with a top surface124of the dielectric material116of the die bonding layer120. In an embodiment, the dielectric material116of the die bonding layer and the inorganic filler material108of the composite dielectric layer107may form covalent bonds with each other. During subsequent temperature processing, metallic bonding between the conductive interconnects118,112is formed. In this manner, by utilizing both an inorganic covalent bond and a metal to metal bond with which to bond the die114to the substrate204and die364, the use of solder and underfill material is not necessary, since the die attach process is completed by the use of the hybrid bonding processes disclosed herein. In an embodiment, the carrier160has been removed and the organic substrate is attached to a package substrate, wherein a plurality of solder interconnect structures152is formed between the package substrate170and interconnect structures within the organic substrate304.

FIGS.4A-4Hdepict cross-sectional views of a method of forming hybrid bonding package structures according to an embodiment. InFIG.4A, a portion of a substrate structure404is shown. A build up substrate162, such as a damascene build up or an RDL for example, may be disposed on a carrier/handle160, such as a silicon carrier, or any other suitable carrier material. The build up substrate162may comprise conductive and dielectric materials, which may be patterned according to design requirements of a particular application, in some embodiments. An etch stop layer420may be patterned selectively across the build up substrate162.

InFIG.4B, a formation process401, such as a composite dielectric material formation process401, may be employed to form a composite dielectric layer107on the build up substrate162. The composite dielectric layer107comprises an organic dielectric material filled with inorganic filler material, such as an inorganic filler material comprising silica particles, for example. The CTE of the composite dielectric layer107is much less than the CTE of conductive interconnect structures to be formed subsequently in the direction normal to the bonding interface plane. The formation process301may include such formation techniques as CVD, PVD, ALD, spin on techniques, transfer or compression mold, and/or vacuum lamination utilizing such materials as mold compound materials, epoxy materials, silsesquioxane, spin on glass materials build up materials or combinations thereof, which are filled with an inorganic filler material such as silica particles, for example.

InFIG.4C, a removal process403, such as an etching process, for example, may be employed to remove a portion of the composite dielectric layer107to form one or more openings466. The removal process403may expose one or more conductive traces or pads163in the build up layer162. InFIG.4D, a metal formation process405may be employed. In an embodiment, a thin seed layer and optionally a barrier layer (not shown) may first be formed within the one or more openings466. The formation process405then fills the one or more openings466with a conductive material, such as copper or copper alloys, to form one or more substrate conductive interconnect structures412via electroplating, paste printing, cold spray or similar such processes.

InFIG.4E, a removal process407, such as an etching process, for example, may be employed to remove a portion of the composite dielectric layer107to form an opening368. The selective etch stop layer420may be utilized to prevent damage of the underlying dielectric surface. The selective etch stop may be removed during process407with an additional selective etch step, in an embodiment. InFIG.4F, a die464may be attached, by utilizing process409, to the build up substrate162. A gap470may be adjacent the die464. The gap470may be filled with a dielectric layer472(FIG.4G), and a die114may be attached to the substrate404(FIG.4H) after preparation of the top surface e.g. by chemical mechanical polish, depicted inFIG.4Gto meet particular design requirements. A die attach process may be employed to attach the die114to the portion of the substrate404. The die114may comprise a die bonding layer120, similar to the die bonding layer120ofFIG.1A, in an embodiment. The die bonding layer120may include a dielectric layer116, which may be an inorganic dielectric layer, and one or more die interconnect structures118. A surface of the one or more conductive die interconnect structures118may be bonded, by metallic bonds, with a surface of the substrate conductive interconnect structure412including those of die464.

A top surface of the composite dielectric material106and the dielectric surface of464may be bonded with a top surface of the dielectric material116of the die bonding layer120. In an embodiment, the dielectric material116of the die bonding layer and the inorganic filler material108of the composite dielectric material106as well as the dielectric of the die464may form covalent bonds with each other, and during subsequent temperature processing the bonding between conductive interconnects412,118are formed. In this manner, by utilizing both an inorganic covalent bond and a metal to metal bond with which to bond the die114to the substrate204, the use of solder and underfill material is not necessary, since the die attach process is completed by the use of the hybrid bonding processes disclosed herein. In an embodiment, the carrier160has been removed and the organic substrate404is attached to a package substrate170, wherein a plurality of solder interconnect structures152are formed between the package substrate170and the conductive features of the organic substrate404.

FIG.5depicts a flow chart of an embodiment of a method500of forming mixed hybrid bonding structures, as disclosed herein. The mixed hybrid bonding structures described in the embodiment enable higher density interconnects, with finer pitch assembly. The need for solder is eliminated, and removal of underfill or mold around solder is alleviated as well. Less warpage is achieved, and the need for solder plating and lithography is eliminated. Power delivery and reliability is improved with the removal of solder from systems incorporating the embodiments described in the present application. The method500may share any or all characteristics with any other methods discussed herein, such as, but not limited to, the methods disclosed inFIGS.2A-2G,3A-3F, and4A-4H, for example, which may show cross-sectional views of structures employing any of the operations described in method500. It should be noted that the order of the operations of method500may be varied, according to a particular application.

At operation502, a composite dielectric material may be formed on at least a portion of a substrate, wherein the composite dielectric material comprises an organic dielectric material and is filled with a plurality of inorganic filler material. In an embodiment, the composite dielectric material may be formed on the substrate using any suitable formation process, such as has been described in the embodiments herein. The plurality of inorganic filler material may be added to a suitable organic dielectric material, such as has been described in the embodiments, in order to reduce the overall CTE of an organic substrate in the direction normal to the bonding interface plane relative to the CTE of the metal interconnects.

At operation504, one or more conductive substrate interconnect structures may be formed within the composite dielectric material. In an embodiment, top surfaces of the one or more conductive substrate interconnect structures may be slighty recessed with a top surface of the composite dielectric material. In other embodiments, the top surfaces of the one or more conductive substrate interconnect structures may be dished or slightly recessed from the surface of the composite dielectric material, depending upon design requirements. Surface topography of the composite dielectric material and conductive structures can be tuned with a CMP process, for example and typically the root-mean-square roughness of the dielectric must be less than 0.5 nm.

At operation506, a die may be attached to the top surface of the composite dielectric material, wherein the die may comprise one or more conductive die interconnect structures within a die dielectric material. The die dielectric material may comprise an inorganic material, or may comprise a composite dielectric material having an organic dielectric material filled with inorganic filler particles.

At operation508, the one or more conductive die interconnect structures are directly bonded to the one or more conductive substrate interconnect structures by metal to metal bonds. The composite dielectric material of the substrate is covalently bonded with the die, as described herein.

FIG.6is a schematic of a computing device600that may be implemented incorporating the package structures described in any of the embodiments herein comprising mixed hybrid bonding structures. The mixed hybrid bonding structures of the packaged devices herein provide a smaller pitch and absence of solder and underfill materials, such as the mixed hybrid bonding structure depicted inFIG.1A, for example. In an embodiment, the computing device600houses a board602, such as a motherboard602for example. The board602may include a number of components, including but not limited to a processor604, an on-die memory606, and at least one communication chip608. The processor604may be physically and electrically coupled to the board602. In some implementations the at least one communication chip608may be physically and electrically coupled to the board602. In further implementations, the communication chip608is part of the processor604.

Depending on its applications, computing device600may include other components that may or may not be physically and electrically coupled to the board602, and may or may not be communicatively coupled to each other. These other components include, but are not limited to, volatile memory (e.g., DRAM)609, non-volatile memory (e.g., ROM)610, flash memory (not shown), a graphics processor unit (GPU)612, a chipset614, an antenna616, a display618such as a touchscreen display, a touchscreen controller620, a battery622, an audio codec (not shown), a video codec (not shown), a global positioning system (GPS) device626, an integrated sensor628, a speaker630, a camera632, an amplifier (not shown), compact disk (CD) (not shown), digital versatile disk (DVD) (not shown), and so forth). These components may be connected to the system board602, mounted to the system board, or combined with any of the other components.

The communication chip608enables wireless and/or wired communications for the transfer of data to and from the computing device600. The term “wireless” and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non-solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not. The communication chip608may implement any of a number of wireless or wired standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, long term evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, Ethernet derivatives thereof, as well as any other wireless and wired protocols that are designated as 3G, 4G, 5G, and beyond.

The computing device600may include a plurality of communication chips608. For instance, a first communication chip may be dedicated to shorter range wireless communications such as Wi-Fi and Bluetooth and a second communication chip may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others. The term “processor” may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.

In various implementations, the computing device600may be a laptop, a netbook, a notebook, an ultrabook, a smartphone, a tablet, a personal digital assistant (PDA), an ultra-mobile PC, a wearable device, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder. In further implementations, the computing device400may be any other electronic device that processes data.

Embodiments of the device structures described herein may be implemented as a part of one or more memory chips, controllers, CPUs (Central Processing Unit), microchips or integrated circuits interconnected using a motherboard, an application specific integrated circuit (ASIC), and/or a field programmable gate array (FPGA).

While certain features set forth herein have been described with reference to various implementations, this description is not intended to be construed in a limiting sense. Hence, various modifications of the implementations described herein, as well as other implementations, which are apparent to persons skilled in the art to which the present disclosure pertains are deemed to lie within the spirit and scope of the present disclosure.

It will be recognized that the embodiments herein are not limited to the embodiments so described, but can be practiced with modification and alteration without departing from the scope of the appended claims.

However, the above embodiments are not limited in these regards and, in various implementations, the above embodiments may include the undertaking only a subset of such features, undertaking a different order of such features, undertaking a different combination of such features, and/or undertaking additional features than those features explicitly listed. The scope of the embodiments herein should, therefore, be determined with reference to the appended claims, along with the full scope of equivalents to which such claims are entitled.