Patent ID: 12225728

DETAILED DESCRIPTION

Various embodiments of the present teachings will be described in greater detail with reference to the accompanying drawings. The drawings are schematic illustrations of various embodiments (and intermediate structures). As such, variations from the configurations and shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, the described embodiments should not be construed as being limited to the particular configurations and shapes illustrated herein but may include deviations in configurations and shapes which do not depart from the spirit and scope of the present teachings as defined in the appended claims.

The present teachings are described herein with reference to cross-section and/or plan illustrations of idealized embodiments of the present teachings. However, embodiments of the present teachings should not be construed as limiting the inventive concept. Although a few embodiments of the present teachings will be shown and described, it will be appreciated by those of ordinary skill in the art that changes may be made in these embodiments without departing from the principles and spirit of the present teachings.

Hereinafter, a semiconductor memory device and a method of manufacturing the same in accordance with example embodiments may be illustrated in detail. In example embodiments, a first direction D1may be an x-direction or a row direction, and a second direction D2may be a y-direction or a column direction substantially perpendicular to the x-direction D1. A third direction D3may be a z-direction or a vertical direction substantially perpendicular to the first direction D1and the second direction D2. Alternatively, the first direction D1may be the y-direction and the second direction D2may be the x-direction.

FIGS.1A and1Bare block diagrams illustrating a semiconductor memory device in accordance with example embodiments.

Referring toFIGS.1A and1B, the semiconductor memory device may include a peripheral circuit PC and a cell array CA on a substrate SUB.

The substrate SUB may include a single crystalline semiconductor substrate. For example, the substrate SUB may include a bulk silicon substrate, a silicon-on-insulator (SOI) substrate, a germanium substrate, a germanium-on-insulator (GOI) substrate, a silicon-germanium substrate, an epitaxial substrate formed by a selective epitaxial growth (SEG) process, etc.

The cell array CA may include a plurality of memory blocks. Each of the memory blocks may include a plurality of cell strings. Each of the cell strings may be electrically connected to a bit line, a source line, word lines, and selection lines. Each of the cell strings may include memory cells and selection transistors serially connected with each other. Each of the selection lines may be used as a gate electrode of corresponding selection transistor. Each of the word lines may be used as a gate electrode of a corresponding memory cell.

The peripheral circuit PC may include NMOS transistor, PMOS transistors, a register and a capacitor electrically connected with the cell array CA. The NMOS transistors, the PMOS transistors, the register, and the capacitor may be used as elements of a row decoder, a column decoder, a page buffer, and a control circuit.

As shown inFIG.1A, the cell array CA and the peripheral circuit PC on the substrate SUB may be arranged adjacent to each other.

Alternatively, as shown inFIG.1B, the peripheral circuit PC and the cell array CA may be sequentially stacked on the substrate SUB. In this case, the peripheral circuit PC may be overlapped with the cell array CA to decrease an area of the substrate SUB on which the cell array CA and the peripheral circuit PC may occupy.

FIG.2is a view illustrating memory blocks of a semiconductor memory device in accordance with example embodiments.

Referring toFIG.2, the cell array CA of the semiconductor memory device may include a plurality of memory blocks BLK1˜BLKz. The memory blocks BLK1˜BLKz may be spaced apart from each other along the second direction D2corresponding to an extending direction of bit lines BL1˜BLm. For example, the first to zth memory blocks BLK1˜BLKz may be spaced apart from each other in the second direction D2. The first to zth memory blocks BLK1˜BLKz may include memory cell stacked in the third direction D3.

FIG.3is an equivalent circuit diagram illustrating a memory block of a semiconductor memory device in accordance with example embodiments.

Referring toFIG.3, the cell array CA of the semiconductor memory device may include the memory blocks. Each of the memory blocks may include the cell strings SR. Each of the cell strings SR may include at least one source selection transistor SST, a plurality of memory cell transistors MC1˜MCn, and at least one drain selection transistor DST serially connected with each other.FIG.3may show one cell string SR including one source selection transistor SST and one drain selection transistor DST. Alternatively, each of the source selection transistor SST and the drain selection transistor DST may include a plurality of selection transistors serially connected with each other. Numbers of the serially connected source selection transistors may be substantially the same as numbers of the serially connected drain selection transistors. Alternatively, the numbers of the serially connected source selection transistors may be more than the numbers of the serially connected drain selection transistors.

The cell strings SR may be arranged along the first direction D1and the second direction D2in a matrix shape to form an array. The cell strings SR on a same line in the second direction D2may be connected to a same bit line. The cell strings SR on a same line in the first direction D1may be commonly connected to gate lines SSL, WL1˜WLn and DSL.

The source selection transistor SST, the memory cell transistors MC1˜MCn and the drain selection transistor DST in one cell string ST may be configured to share one channel layer. The cell strings SR may be arranged between the bit lines BL1˜BLm and a source line SL. The gate lines SSL, WL1˜WLn and DSL may be stacked between the bit lines BL1˜BLm and the source line SL. Each of the gate lines SSL, WL1˜WLn and DSL may be electrically isolated from each other.

The source selection line SSL may be used as a gate electrode of the source selection transistor SST. The source selection transistors SST in the memory block may share one source selection line SSL. The word lines WL1˜WLn may be used as gate electrodes of the memory cell transistors MC1˜MCn. Drain selection lines DSL1and DSL2may be used as a gate electrode of the drain selection transistor DST. The drain selection lines DSL1and DSL2may be separated into a first drain selection line DSL1and a second drain selection line DSL2by a gate separation layer. A part of the drain selection transistors DST in the memory block may share the first drain selection line DSL1. The rest of the drain selection transistors DST may share the second drain selection line DSL2. The source selection line SSL may be arranged under the word lines WL1˜WLn. The drain selection line DSL may be arranged over the word lines WL1˜WLn.

Each of the bit lines BL1˜BLm may be connected to the drain selection transistors DST of the cell string SR arranged along the second direction D2. For example, the cell strings SR commonly connected to one drain selection line DSL may be connected with different bit lines BL1˜BLm. Thus, when any one of the drain selection lines DSL and any one of the bit lines BL1˜BLm may be selected, any one of the cell strings SR may also be selected.

The source lines SL may be electrically connected with a common source line CSL. The source line SL may be configured to transmit an operational voltage, which may be applied to the common source line CSL, to the cell strings SR. The operational voltage may be selectively transmitted to the cell strings SR in accordance with a voltage level of the source selection line SSL.

FIG.4Ais a plan view illustrating a semiconductor memory device in accordance with a first example embodiment,FIG.4Bis a plan view illustrating a modified semiconductor memory device in accordance with the first example embodiment,FIG.5is a cross-sectional view taken along a line I-I′ inFIG.4A, andFIG.6is a view illustrating a planar shape of a first channel post adjacent to a gate separation layer in the semiconductor memory device in accordance with the first example embodiment.

Referring toFIGS.4A,5, and6, a semiconductor memory device of the first example embodiment may include a source line layer102, an electrode structure110, a plurality of channel posts120, at least one gate separation layer130, and a slit structure140.

The source line layer102may be formed on a substrate100. The electrode structure110may include insulating interlayer104and gate conductive layers106alternately stacked on the source line layer102. The channel posts120may be formed through the electrode structure110. The gate separation layer130may be formed between the channel posts120to separate an uppermost gate conductive layer106among the gate conductive layers106. The slit structure140may be formed through the electrode structure110to divide memory blocks BLK. A first channel post120A among the channel posts120adjacent to the gate separation layer130may have a gibbous moon shape in a planar view. Further, as shown inFIG.4B, a third channel post120C adjacent to the slit structure140may also have the gibbous moon shape.

The source line layer102on the substrate100may have a plate shape corresponding to the memory block BLK. The source line layer102may be electrically connected to the channel posts120. The source line layer102may function as a junction region of the source selection transistor SST. The source line layer102may include a doped semiconductor layer. For example, the source line layer102may include a silicon layer doped with n type impurities. Although not depicted in drawings, when a structure together with the peripheral circuit may be formed under the source line layer102, an insulation layer may be formed between the substrate100and the source line layer102.

The electrode structure110may include the insulating interlayers104and the gate conductive layers106alternately stacked. The insulating interlayers104may be positioned at an uppermost layer and a lowermost layer in the electrode structure110. The uppermost insulating interlayer104may have a thickness thicker than thicknesses of other insulating interlayers104. The uppermost insulating interlayers104may include stacked insulation layers. The stacked insulation layers may include a same insulation material. The lowermost gate conductive layer106in the electrode structure110may function as a gate or the source selection line SSL of the source selection transistor SST. The uppermost gate conductive layer106may function as a gate or the drain selection line DSL of the drain selection transistor DST. The gate conductive layers106between the gate of the source selection transistor SST and the gate of the drain selection transistor DST may function as a gate or a word line of the memory cell MC.

The channel posts120may be arranged in a matrix shape. Particularly, the channel posts120may be aligned with each other in the first direction D1. The channel posts120may be arranged in a zigzag shape in the second direction D2.

Each of the channel posts120may include an opening121, a memory layer122, a channel layer123, a core layer124, and a capping layer125. The opening121may be formed through the electrode structure110. The opening121may be partially extended into the source line layer102. The memory layer122may be formed on an inner surface of the opening121. The channel layer123may be formed on the memory layer122. The core layer124may be formed on the channel layer123to partially fill the opening121. The capping layer125may be formed on the core layer124to fully fill the opening121. The memory layer122may include a tunnel insulation layer, a charge-trapping layer and a block layer sequentially stacked. The tunnel insulation layer and the blocking layer may include oxide. The charge-trapping layer may include nitride. For example, the channel layer123may include a semiconductor layer such as a silicon layer. The channel layer123may be electrically connected with the source line layer102. The core layer124may include an insulation layer. The capping layer125may include a doped semiconductor layer, for example, a silicon layer doped with n type impurities. The capping layer125may function as a junction region of the drain selection transistor DST. An interface between the core layer124and the capping layer125may be higher than an upper surface of the uppermost gate conductive layer106.

The channel posts120may include the first channel post120A adjacent to the gate separation layer130and remaining second channel posts120B. The planar shape of the first channel post120A may be the gibbous moon shape. A planar shape of the second channel posts120B may be a circular shape or an elliptical shape. The planar gibbous moon shape of the first channel post120A may reduce a size of the memory block BLK to increase an integration degree of the semiconductor memory device. Further, the similar shapes of the first channel post120A and the second channel posts120B may function as to prevent characteristic deviations between the transistors of the memory cell MC from being generated. InFIG.6, a dotted line may represent a full moon shape or a circular shape corresponding to the planar shape of the second channel posts120B so as to definitely show the gibbous moon shape of the first channel post120A.

Referring toFIG.6, the planar gibbous moon shape of the first channel post120A may have a simple closed curve. The simple closed curve may have at least two curves C1and C2having different curvatures. Particularly, the planar gibbous moon shape of the first channel post120A may include a first sector and a second sector combined with each other. In order to ensure a space between the first channel post120A and the gate separation layer130, a first distance L1between a center point of a curve C1in the first sector and the center point P of the first sector may be longer than a second distance L2between a center point of a curve C2in the second sector and the center point P of the second sector. The curve C2in the second sector may face a sidewall of the gate separation layer130. Alternatively, as shown inFIG.4B, the curve C2in the second sector may face a sidewall of the slit structure140.

When a sidewall of the first channel post120A may make contact with the sidewall of the gate separation layer130or the first channel post120A may be partially overlapped with the gate separation layer130due to increasing of the integration degree, the gate conductive layer106, which may act as the gate of the drain selection transistor DST, may have a structure configured to partially surround the first channel post120A, not fully surround the first channel post120A to deteriorate operational characteristics of the drain selection transistor DST. However, when the first channel post120A may have the gibbous moon shape, the space between the first channel post120A and the gate separation layer130may be ensured to provide the gate conductive layer106, which may act as the gate of the drain selection transistor DST, with a gate all around (GAA) structure configured to fully surround the first channel post120A. Thus, the operational characteristics of the drain selection transistor DST may be improved. Further, the drain selection line DSL may be stably separated using the gate separation layer130.

The gate separation layer130may be configured to separate the gate of the drain selection transistor DST or the drain selection line DSL in the memory block BLK. The gate separation layer130may have a linear shape extended in the first direction D1. The gate separation layer130may include a trench132and a separating insulation layer134. The trench132may be formed in the electrode structure110to separate the uppermost gate conductive layer106in the electrode structure110. The separating insulation layer134may be formed in the trench132. The trench132may have a sidewall spaced apart from the sidewall of the first channel post120A adjacent to the gate separation layer130. That is, the sidewall of the trench132may be adjacent to the sidewall of the first channel post120A adjacent to the gate separation layer130by a gap. The separating insulation layer134in the trench132may include an insulation material substantially the same as the insulation material of the insulating interlayer104. According to the first example embodiment, one gate separation layer130may be positioned at a central portion of one memory block BLK. Further, numbers of the channel posts120at one side of the gate separation layer130may be substantially the same numbers of the channel posts120at the other side of the gate separation layer130. Alternatively, at least two gate separation layers130may be arranged in one memory block BLK. For example, when the channel posts120may be arranged in one memory block BLK in sixteen rows along the second direction D2, total three gate separation layers130by four row units may be arranged.

The slit structure140may function as to divide the memory blocks BLK. The slit structure140may have a linear shape extended in the first direction D1. The slit structures140may be arranged spaced apart from each other by a uniform gap in the second direction D2. The slit structure140may include a slit trench142, a spacer144and a slit conductive layer146. The slit trench142may be formed through the electrode structure110. The slit trench142may be partially extended into the source line layer102. The spacer144may be formed on a sidewall of the slit trench142. The slit conductive layer146may be formed in the slit trench142. The slit conductive layer146in the slit trench142may be electrically connected to the source line layer102. Further, the slit conductive layer146may function as the common source line CSL.

As indicated above, because the first channel post120A adjacent to the gate separation layer130may have the gibbous moon shape in the planar view, the space between the gate separation layer130and the first channel post120may be ensured and the integration degree of the memory block BLK may be increased. The uppermost gate conductive layer106separated by the gate separation layer130may have the GAA structure configured to fully surround the first channel post120A adjacent to the gate separation layer130due to the planar shape of the first channel post120A to prevent the operational deteriorations of the semiconductor memory device caused by the increased integration degree.

Further, the similar planar shapes of the first channel post120A and the second channel posts120B may prevent the characteristic deviation between the transistors of the memory cell MC in the memory block BLK.

Furthermore, according to the first example embodiment, the third channel post120C adjacent to the slit structure140may have the gibbous moon shape together with the first channel post120A adjacent to the gate separation layer130to more increase the integration degree of the memory block BLK.

FIGS.7A to7Eare cross-sectional views, which are taken along the line I-I′ inFIG.4A, illustrating a method of manufacturing a semiconductor memory device in accordance with the first example embodiment.

Referring toFIG.7A, a preliminary source line layer18may be formed on a substrate10. The preliminary source line layer18may include a first source line layer12, a sacrificial layer14, and a second source line layer16sequentially stacked. The first source line layer12and the second source line layer16may include a doped semiconductor layer. For example, the first source line layer12and the second source line layer16may include a silicon layer doped with n type impurities. The sacrificial layer14may include a material having an etching selectivity with respect to the first source line layer12and the second source line layer16. For example, the sacrificial layer14may include an oxide layer, a nitride layer, an oxynitride layer, etc.

A stack structure20may be formed on the preliminary source line layer18. The stack structure20may include first layers22and second layers24alternately stacked. The first layers22may be positioned at a lowermost layer and an uppermost layer of the stack structure20. The uppermost first layer22may have a thickness thicker than thicknesses of the remaining first layers22. The second layers24may include the sacrificial layer for forming a conductive layer including a word line, a selection line, a pad, etc. The first layer22may include an insulation interlayer for insulating the stacked conductive layers from each other. The first layer22may include an insulation material having an etching selectivity with respect to an insulation material of the second layer24. For example, the first layers22may include oxide layers and the second layers24may include nitride layers having an etching selectivity with respect to the oxide layer.

A mask pattern may be formed on the stack structure20. A trench26may be formed in the stack structure using the mask pattern as an etch barrier. The trench26may have a linear shape extended in the first direction D1. The trench26may be formed through the uppermost second layer24. Numbers of the second layers24through which the trench26may be formed from the uppermost second layer24may be determined in accordance with numbers of the drain selection transistors DST serially connected with each other in the cell string. The first example embodiment may include one drain selection transistor DST in the cell string.

After removing the mask pattern, a separating insulation layer28may be formed in the trench26. The separating insulation layer28may include an oxide layer, a nitride layer, an oxynitride layer, etc. The separating insulation layer28may include a material substantially the same as that of the first layer22. For example, the separating insulation layer28may include the oxide layer.

Thus, before forming channel posts40, a gate separation layer30including the trench26and the separating insulation layer28may be formed.

Referring toFIG.7B, a mask pattern may then be formed on the stack structure20. The stack structure20, the second source line layer16, the sacrificial layer14, and the first source line layer12may be etched using the mask pattern as an etch barrier to form openings32. The openings32may be formed through the stack structure20, the second source line layer16, and the sacrificial layer14. The openings32may have a hole type shape extended into the first source line layer12.

An opening among the openings32adjacent to the gate separation layer30may have a gibbous moon shape in a planar view. Each of the opening32adjacent to the gate separation layer30may have a sidewall spaced apart from a sidewall of the gate separation layer30. The remaining openings32may have a circular shape or an elliptical shape.

After removing the mask pattern, a memory layer34may be formed on an inner surface of the opening32. The memory layer34may include a tunnel insulation layer, a charge-trapping layer, and a blocking layer sequentially stacked. The tunnel insulation layer and the blocking layer may include oxide. The charge-trapping layer may include nitride.

A channel layer36may be formed on the memory layer34. The channel layer36may include a semiconductor layer. For example, the channel layer36may include a silicon layer.

A core layer37may be formed on the channel layer36to fill the opening32. The core layer37may include an oxide layer, a nitride layer, an oxynitride layer, etc.

The core layer37may be partially removed to form a recessed portion. A capping layer38may be formed in the recessed portion. The capping layer38may include a doped semiconductor layer. For example, the capping layer38may include a silicon layer doped with n type impurities. An interface between the core layer37and the capping layer38may be higher than the upper surface of the uppermost second layer24in the stack structure20.

A plurality of channel posts40may be formed through the stack structure20. Each of the channel posts40may include the opening32, the memory layer34, the channel layer36, the core layer37, and the capping layer38.

Referring toFIG.7C, a mask pattern may be formed on the stack structure20. The stack structure20may be etched using the mask pattern as an etch barrier to form a slit structure42. The slit structure42may have a linear pattern extended in the first direction D1. The slit structure42may be positioned at both sides of the gate separation layer30in the second direction D2. The slit structure42may be formed through the stack structure20and the second source line layer16. The slit structure42may be partially extended into the sacrificial layer14.

After removing the mask pattern, the second layer24may be removed from the stack structure20through the slit structure42. A conductive material may be formed in a space formed by removing the second layer24to form a plurality of gate conductive layers44, thereby forming an electrode structure20A. The electrode structure20A may include the first layers22as the insulating interlayer and the gate conductive layers44alternately stacked.

Referring toFIG.7D, a spacer46may be formed on a sidewall of the slit structure42. The spacer46may include a single layer including any one selected from the group of an oxide layer, a nitride layer, and an oxynitride layer or may include a multilayer including at least two selected from the group of an oxide layer, a nitride layer, and an oxynitride layer.

The sacrificial layer14of the preliminary source line layer18may be removed through the slit trench42. The memory layer34exposed by removing the sacrificial layer14may then be etched to expose the channel layer36of each of the channel posts40.

Referring toFIG.7E, a conductive material may be formed in a space formed by removing the sacrificial layer14to form a third source line layer48. The third source line layer48may be electrically connected with the first source line layer12, the second source line layer16, and the channel layer36. Thus, a source line layer18A including the first to third source line layers12,16, and48may be formed.

A slit conductive layer52may be formed in the slit trench42. The slit conductive layer52may be electrically connected to the source line layer18A. The slit conductive layer52may function as the common source line CSL.

Therefore, a slit structure50including the slit trench42, the spacer46, and the slit conductive layer52may be formed. A semiconductor memory device may be completed using general processes for forming the semiconductor memory device.

FIG.8Ais a plan view illustrating a semiconductor memory device in accordance with a second example embodiment,FIG.8Bis a plan view illustrating a modified semiconductor memory device in accordance with the second example embodiment, andFIG.9is a cross-sectional view taken along a line II-II′ inFIG.8A.

A semiconductor memory device of this example embodiment may include elements substantially the same as those of the semiconductor memory device of the first example embodiment except for a gate separation layer. Thus, the same reference numerals may refer to the same elements and any further illustrations with respect to the same elements may be omitted herein for brevity.

Referring toFIGS.8A and9, a semiconductor memory device of the second example embodiment may include a source line layer102, an electrode structure110, a plurality of channel posts120, a gate separation layer200, and a slit structure140.

The source line layer102may be formed on a substrate100. The electrode structure110may include insulating interlayer104and gate conductive layers106alternately stacked on the source line layer102. The channel posts120may be formed through the electrode structure110. The gate separation layer200may be formed between the channel posts120to separate an uppermost gate conductive layer106among the gate conductive layers106. The slit structure140may be formed through the electrode structure110to divide memory blocks BLK. A first channel post120A among the channel posts120adjacent to the gate separation layer200may have a gibbous moon shape in a planar view. Further, as shown inFIG.8B, a third channel post120C adjacent to the slit structure140may also have the gibbous moon shape.

The gate separation layer200may be configured to separate the gate of the drain selection transistor DST or the drain selection line DSL in the memory block BLK. The gate separation layer200may have a linear pattern extended in the first direction D1. The gate separation layer200may have a T shaped cross-sectional shape.

The gate separation layer200may include a first trench202, a spacer206, a second trench204, and a separating insulation layer208. The first trench202may be formed in the uppermost insulating interlayer104. The spacer206may be formed on a sidewall of the first trench202. The second trench204may be extended from a bottom surface of the first trench202to separate the uppermost gate conductive layer106. The second trench204may have a width narrower than a width of the first trench202. The separating insulation layer208may be formed in the first trench202and the second trench204. The sidewall of the first trench202may be configured to make contact with the sidewall of the first channel post120A adjacent to the gate separation layer200. The second trench204may have a sidewall spaced apart from the sidewall of the first channel post120A adjacent to the gate separation layer200by a gap. The separating insulation layer208in the first trench202and the second trench204may include an insulation material substantially the same as the insulation material of the insulating interlayer104. The spacer206on the sidewall of the first trench202may include a single layer of any one selected from the group consisting of an oxide layer, a nitride layer, and an oxynitride layer or may include a multilayer of at least two selected from the group consisting of an oxide layer, a nitride layer, and an oxynitride layer. The spacer206on the sidewall of the first trench202may include a material substantially the same as that of the separating insulation layer208and the insulating interlayer104.

According to the second example embodiment, one gate separation layer200may be positioned at a central portion of one memory block BLK. Further, numbers of the channel posts120at one side of the gate separation layer200may be substantially the same numbers of the channel posts120at the other side of the gate separation layer200. Alternatively, at least two gate separation layers200may be arranged on one memory block BLK. For example, when the channel posts120may be arranged in one memory block BLK in sixteen rows along the second direction D2, total three gate separation layers200by four row units may be arranged.

As indicated above, because the first channel post120A adjacent to the gate separation layer200may have the gibbous moon shape in the planar view, the space between the gate separation layer200and the first channel post120may be ensured and the integration degree of the memory block BLK may be increased. The uppermost gate conductive layer106separated by the gate separation layer200may have the GAA structure configured to fully surround the first channel post120A adjacent to the gate separation layer200due to the planar shape of the first channel post120A to prevent the operational deteriorations of the semiconductor memory device caused by the increased integration degree.

Further, the similar planar shapes of the first channel post120A and the second channel posts120B may prevent the characteristic deviation between the transistors of the memory cell MC in the memory block BLK.

Furthermore, according to the second example embodiment, the third channel post120C adjacent to the slit structure140may have the gibbous moon shape together with the first channel post120A adjacent to the gate separation layer200to more increase the integration degree of the memory block BLK.

Additionally, the T-shaped gate separation layer200may include the first trench202, the spacer206, the second trench204, and the separating insulation layer208to readily increase the integration degree of the memory block and to effectively prevent the operational deteriorations of the semiconductor memory device caused by the increased integration degree.

FIGS.10A to10Care cross-sectional views, which are taken along the line II-II′ inFIG.8A, illustrating a method of manufacturing a semiconductor memory device in accordance with the second example embodiment.

Referring toFIG.10A, a preliminary source line layer18may be formed on a substrate10. The preliminary source line layer18may include a first source line layer12, a sacrificial layer14, and a second source line layer16sequentially stacked.

A stack structure20may be formed on the preliminary source line layer18. The stack structure20may include first layers22and second layers24alternately stacked. For example, the first layers22may include oxide layers and the second layers24may include nitride layers.

A mask pattern may be formed on the stack structure20. A first trench62may be formed in the stack structure20using the mask pattern as an etch barrier. The first trench62may have a linear shape extended in the first direction D1. The first trench62may be formed through the uppermost first layer22. That is, the first trench62may have a bottom surface higher than an upper surface of the uppermost second layer24.

A spacer64may be formed on a sidewall of the first trench62. The spacer64may include a single layer of any one selected from the group consisting of an oxide layer, a nitride layer, and an oxynitride layer or may include a multilayer of at least two selected from the group consisting of an oxide layer, a nitride layer, and an oxynitride layer.

Referring toFIG.10B, the stack structure20may be etched using a mask pattern and the spacer64as an etch barrier to form a second trench66. The second trench66may be configured to separate the uppermost second layer24. The second trench66may have a width narrower than a width of the first trench62. The first trench62and the second trench64may be connected with each other to form a T shaped cross-sectional shape.

After removing the mask pattern, a separating insulation layer68may be formed in the first trench62and the second trench66. The separating insulation layer68may include an oxide layer, a nitride layer, an oxynitride layer, etc. The separating insulation layer68may include a material substantially the same as that of the first layer22. For example, the separating insulation layer28may include the oxide layer.

Thus, before forming channel posts40, a T-shaped gate separation layer60including the first trench62, the spacer64, the second trench66, and the separating insulation layer68may be formed.

Referring toFIG.10C, a mask pattern may then be formed on the stack structure20. The stack structure20, the second source line layer16, the sacrificial layer14, and the first source line layer12may be etched using the mask pattern as an etch barrier to form openings32. The openings32may be formed through the stack structure20, the second source line layer16, and the sacrificial layer14. The openings32may have a hole type shape extended into the first source line layer12.

An opening among the openings32adjacent to the gate separation layer60may have a gibbous moon shape in a planar view. Each of the opening32adjacent to the gate separation layer60may have a sidewall making contact with the sidewall of the first trench62and spaced apart from the sidewall of the second trench66. That is, during the stack structure20may be etched to form the openings32, the spacer64on the sidewall of the first trench62and the separating insulation layer68in the first trench62may also be partially etched. The remaining openings32may have a circular shape or an elliptical shape.

After removing the mask pattern, a memory layer34may be formed on an inner surface of the opening32. The memory layer34may include a tunnel insulation layer, a charge-trapping layer, and a blocking layer sequentially stacked. The tunnel insulation layer and the blocking layer may include oxide. The charge-trapping layer may include nitride.

A channel layer36may be formed on the memory layer34. The channel layer36may include a semiconductor layer. For example, the channel layer36may include a silicon layer.

A core layer37may be formed on the channel layer36to fill the opening32. The core layer37may include an oxide layer, a nitride layer, an oxynitride layer, etc.

The core layer37may be partially removed to form a recessed portion. A capping layer38may be formed in the recessed portion. The capping layer38may include a doped semiconductor layer. For example, the capping layer38may include a silicon layer doped with n type impurities. An interface between the core layer37and the capping layer38may be higher than the upper surface of the uppermost second layer24in the stack structure20.

A plurality of channel posts40may be formed through the stack structure20. Each of the channel posts40may include the opening32, the memory layer34, the channel layer36, the core layer37, and the capping layer38.

As indicated above with reference toFIGS.7C to7E, a semiconductor memory device may be completed using general processes for forming the semiconductor memory device.

FIG.11Ais a plan view illustrating a semiconductor memory device in accordance with a third example embodiment,FIG.11Bis a plan view illustrating a modified semiconductor memory device in accordance with the third example embodiment, andFIG.12is a cross-sectional view taken along a line III-III′ inFIG.11A.

A semiconductor memory device of this example embodiment may include elements substantially the same as those of the semiconductor memory device of the first example embodiment except for a gate separation layer. Thus, the same reference numerals may refer to the same elements and any further illustrations with respect to the same elements may be omitted herein for brevity.

Referring toFIGS.11A and12, a semiconductor memory device of the third example embodiment may include a source line layer102, an electrode structure110, a plurality of channel posts120, a gate separation layer300, and a slit structure140.

The source line layer102may be formed on a substrate100. The electrode structure110may include insulating interlayer104and gate conductive layers106alternately stacked on the source line layer102. The channel posts120may be formed through the electrode structure110. The gate separation layer300may be formed between the channel posts120to separate an uppermost gate conductive layer106among the gate conductive layers106. The slit structure140may be formed through the electrode structure110to divide memory blocks BLK. A first channel post120A among the channel posts120adjacent to the gate separation layer300may have a gibbous moon shape in a planar view. Further, as shown inFIG.11B, a third channel post120C adjacent to the slit structure140may also have the gibbous moon shape.

The gate separation layer300may be configured to separate the gate of the drain selection transistor DST or the drain selection line DSL in the memory block BLK. The gate separation layer300may have a linear pattern extended in the first direction D1. The gate separation layer300may be partially overlapped with the first channel post120A to have a wave shape.

Particularly, the gate separation layer300may include a trench302and a separating insulation layer304. The trench302may be formed in the electrode structure110to separate the uppermost gate conductive layer106. The separating insulation layer304may be formed in the trench302. The trench302may have a sidewall configured to make contact with the sidewall of the first channel post120A adjacent to the gate separation layer300. Because the sidewall of the gate separation layer300may make contact with the sidewall of the first channel post120A adjacent to the gate separation layer300, the uppermost gate conductive layer106in the electrode structure110may be configure to partially surround the first channel post120A. Therefore, a bias applied to the first channel post120A may be different from a bias applied to the remaining channel posts120, i.e., the second channel post120B and the third channel post120C.

As indicated above, because the sidewall of the gate separation layer300may make contact with the sidewall of the first channel post120A, the integration degree of the memory block BLK may be easily increased.

Further, because the first channel post120A adjacent to the gate separation layer300may have the gibbous moon shape in the planar view, although previously forming the gate separation layer300before the channel posts120, the gate separation layer300may not be excessively lost to improve structural stability.

Further, the similar planar shapes of the first channel post120A and the second channel posts120B may prevent the characteristic deviation between the transistors of the memory cell MC in the memory block BLK.

Furthermore, according to the third example embodiment, the third channel post120C adjacent to the slit structure140may have the gibbous moon shape together with the first channel post120A adjacent to the gate separation layer300to more increase the integration degree of the memory block BLK.

The semiconductor device in accordance with the present embodiment can be fabricated through the above-described process, and processes which are not described may be performed through publicly known technology.

FIG.13is a block diagram of the configuration of a memory system1000according to an embodiment.

As illustrated inFIG.13, the memory system1000may include a memory device1200and a controller1100.

The memory device1200may be used to store various data types such as text, graphic and software code. The memory device1200may be a non-volatile memory. The memory device1200may be the semiconductor device described above with reference toFIGS.4A to12. In addition, the memory device1200may include an electrode structure including insulating interlayers and gate conductive layers alternately stacked; a plurality of channel posts formed through the electrode structure; and at least one gate separation layer arranged between the channel posts to separate an uppermost gate conductive layer among the gate conductive layers in the stack structure, wherein channel posts among the channel posts adjacent to the gate separation layer have a gibbous moon shape in a planar view. Because the memory device1200is formed and manufactured in the above-described manner, a detailed description thereof will be omitted.

The controller1100may be couple to a host and the memory device1200, and may access the memory device1200in response to a request from the host. For example, the controller1100may control read, write, erase, and background operations of the memory device1200.

The controller1100may include a random access memory (RAM)1110, a central processing unit (CPU)1120, a host interface1130, an error correction code (ECC) circuit1140, and a memory interface1150.

The RAM1110may function as an operation memory of the CPU1120, a cache memory between the memory device1200and the host, and a buffer memory between the memory device1200and the host. The RAM1110may be replaced by a static random access memory (SRAM) or a read only memory (ROM).

The host interface1130may be interface with the host. For example, the controller1100may communicate with the host through one of various interface protocols including a Universal Serial Bus (USB) protocol, a multimedia card (MMC) protocol, a peripheral component interconnection (PCI) protocol, a PCI express (PCI-E) protocol, an Advanced Technology Attachment (ATA) protocol, a Serial-ATA protocol, a Parallel-ATA protocol, a small computer small interface (SCSI) protocol, an enhanced small disk interface (ESDI) protocol, an Integrated Drive Electronics (IDE) protocol, and a private protocol.

The ECC circuit1140may detect and correct errors included in data read from the memory device1200by using error correction codes (ECCs).

The memory interface1150may interface with the memory device1200. For example, the memory interface1150may include a NAND interface or a NOR interface.

For example, the controller1100may further include a buffer memory (not illustrated) configured to temporarily store data. The buffer memory may temporarily store data, externally transferred through the host interface1130, or temporarily store data, transferred from the memory device1200through the memory interface1150. In addition, the controller1100may further include ROM storing code data to interface with the host.

As described above, because the memory system1000is easy to manufacture and includes the memory device1200having a stable structure and improved characteristics, the characteristics of the memory system1000may also be improved.

FIG.14is a block diagram of the configuration of a memory system1000′ according to an embodiment. Hereinafter, a description of common contents with the earlier described embodiment is omitted.

As illustrated inFIG.14, the memory system1000′ may include a memory device1200′ and the controller1100. In addition, the controller1100may include the RAM1110, the CPU1120, the host interface1130, the ECC circuit1140, and the memory interface1150.

The memory device1200′ may be a non-volatile memory device. The memory device1200′ may be the semiconductor device described above with reference toFIGS.4A to12. In addition, the memory device1200′ may include an electrode structure including insulating interlayers and gate conductive layers alternately stacked; a plurality of channel posts formed through the electrode structure; and at least one gate separation layer arranged between the channel posts to separate an uppermost gate conductive layer among the gate conductive layers in the stack structure, wherein channel posts among the channel posts adjacent to the gate separation layer have a gibbous moon shape in a planar view. Because the memory device1200′ is formed and manufactured in the above-described manner, a detailed description thereof will be omitted.

In addition, the memory device1200′ may be a multi-chip package composed of a plurality of memory chips. The plurality of memory chips may be divided into a plurality of groups. The plurality of groups may communicate with the controller1100through first to k-th channels CH1to CHk. In addition, memory chips, included in a single group, may be suitable for communicating with the controller1100through a common channel. The memory system1000′ may be modified so that a single memory chip may be coupled to a single channel.

As described above, because the memory system1000′ is easy to manufacture and includes the memory device1200′ having a stable structure and improved characteristics, the characteristics of the memory system1000′ may also be improved. In addition, the data storage capacity of the memory system1000′ may be further increased by forming the memory device1200′ using a multi-chip package.

FIG.15is a block diagram of the configuration of a computing system2000according to an embodiment. Hereinafter, a description of common contents with the earlier described embodiments is omitted.

As illustrated inFIG.15, the computing system2000may include a memory device2100, a CPU2200, a random-access memory (RAM)2300, a user interface2400, a power supply2500, and a system bus2600.

The memory device2100may store data, which is input through the user interface2400, and data, which is processed by the CPU2200. In addition, the memory device2100may be electrically coupled to the CPU2200, the RAM2300, the user interface2400, and the power supply2500. For example, the memory device2100may be coupled to the system bus2600through a controller (not illustrated) or directly coupled to the system bus2600. When the memory device2100is directly coupled to the system bus2600, functions of the controller may be performed by the CPU2200and the RAM2300.

The memory device2100may be a non-volatile memory. In addition, the memory device2100may be the semiconductor memory device described above with reference toFIGS.4A to12. The memory device2100may include an electrode structure including insulating interlayers and gate conductive layers alternately stacked; a plurality of channel posts formed through the electrode structure; and at least one gate separation layer arranged between the channel posts to separate an uppermost gate conductive layer among the gate conductive layers in the stack structure, wherein channel posts among the channel posts adjacent to the gate separation layer have a gibbous moon shape in a planar view. Because the memory device2100is formed and manufactured in the above-described manner, a detailed description thereof will be omitted.

In addition, as described above with reference toFIG.14, the memory device2100may be a multi-chip package composed of a plurality of memory chips.

The computing system2000having the above-described configuration may be one of various components of an electronic device, such as a computer, an ultra mobile PC (UMPC), a workstation, a net-book, personal digital assistants (PDAs), a portable computer, a web tablet, a wireless phone, a mobile phone, a smart phone, an e-book, a portable multimedia player (PMP), a portable game machine, a navigation device, a black box, a digital camera, a three-dimensional (3D) television, a digital audio recorder, a digital audio player, a digital picture recorder, a digital picture player, a digital video recorder, a digital video player, a device for transmitting/receiving information in wireless environment, one of various electronic devices for home network, one of various electronic devices for computer network, one of various electronic devices for telematics network, an RFID device, and/or one of various devices for computing systems, etc.

As described above, because the computing system2000is easy to manufacture, and includes a memory device2100having a stable structure and improved characteristics, the characteristics of the computing system2000may also be improved.

FIG.16is a block diagram of a computing system3000according to an embodiment.

As illustrated inFIG.16, the computing system3000may include a software layer that has an operating system3100an application3200, a file system3300, and a translation layer3400. In addition, the computing system3000may include a hardware layer such as a memory system3500.

The operating system3100manages software and hardware resources of the computing system3000. The operating system3100may control program execution of a central processing unit. The application3200may include various application programs executed by the computing system3000. The application3200may be a utility executed by the operating system3100.

The file system3300may refer to a logical structure configured to manage data and files present in the computing system3000. The file system3300may organize files or data to be stored in the memory device3500according to rules. The file system3300may be determined depending on the operating system3100that is used in the computing system3000. For example, when the operating system3100is a Microsoft Windows-based system, the file system3300may be a file allocation table (FAT) or an NT file system (NTFS). In addition, when the operating system3100is a Unix/Linux-based system, the file system3300may be an extended file system (EXT), a Unix file system (UFS), or a journaling file system (IFS).

FIG.16illustrates the operating system3100, the application3200, and the file system3300in separate blocks. However, the application3200and the file system3300may be included in the operating system3100.

The translation layer3400may translate an address to be suitable for the memory device3500in response to a request from the file system3300. For example, the translation layer3400may translate a logic address, generated by the file system3300, into a physical address of the memory device3500. Mapping information of the logic address and the physical address may be stored in an address translation table. For example, the translation layer3400may be a flash translation layer (FTL), a universal flash storage link layer (ULL), or the like.

The memory device3500may be a non-volatile memory. The memory device3500may be the semiconductor memory device described above with reference toFIGS.4A to12. In addition, the memory device3500may include an electrode structure including insulating interlayers and gate conductive layers alternately stacked; a plurality of channel posts formed through the electrode structure; and at least one gate separation layer arranged between the channel posts to separate an uppermost gate conductive layer among the gate conductive layers in the stack structure, wherein channel posts among the channel posts adjacent to the gate separation layer have a gibbous moon shape in a planar view. Because the memory device3500is formed and manufactured in the above-described manner, a detailed description thereof will be omitted.

The computing system3000having the above-described configuration may be divided into an operating system layer that is operated in an upper layer region and a controller layer that is operated in a lower level region. The operating system3100, the application3200, and the file system3300may be included in the operating system layer and driven by an operation memory. In addition, the translation layer3400may be included in the operating system layer or the controller layer.

As described above, because the computing system3000is easy to manufacture, and includes a memory device3500having a stable structure and improved characteristics, the characteristics of the computing system3000may also be improved.

The above described embodiments of the present teachings are intended to illustrate and not to limit the present invention. Various alternatives and equivalents are possible. The present teachings are not limited by the embodiments described herein. Nor are the present teachings limited to any specific type of semiconductor device. Other additions, subtractions, or modifications are possible in view of the present disclosure and are intended to fall within the scope of the appended claims.