Patent ID: 12242407

Throughout the drawings, identical reference characters and descriptions indicate similar, but not necessarily identical, elements. While the exemplary implementations described herein are susceptible to various modifications and alternative forms, specific implementations have been shown by way of example in the drawings and will be described in detail herein. However, the exemplary implementations described herein are not intended to be limited to the particular forms disclosed. Rather, the instant disclosure covers all modifications, equivalents, and alternatives falling within the scope of the appended claims.

DETAILED DESCRIPTION OF EXEMPLARY IMPLEMENTATIONS

The present disclosure describes various apparatuses, systems, and methods for conducting mission-mode testing on high-speed links. In some examples, SLT can be used to assess and/or test one or more functionalities of high-speed links and/or data fabric devices for quality-control purposes prior to release and/or shipment. Some SLT technologies include and/or involve somewhat expensive mechanical handlers or gantries that have limited space and/or capacity for certain resources, components, and/or endpoints, such as peripheral component interconnect express (PCIe) cards and/or additional sockets. Accordingly, due to these limitations and/or deficiencies, these SLT technologies could be unable to conduct comprehensive and/or robust testing on some data fabric devices that incorporate such resources, components, and/or endpoints.

Moreover, data fabric devices continue to evolve and/or advance in terms of resources and/or functionalities. As a result of such evolution and/or advancement, the size of some data fabric devices and/or the number of high-speed communication links implemented by these data fabric devices can increase and/or expand, thereby potentially impairing the testing of such devices further with the traditional SLT technologies. To address and/or counteract these limitations or deficiencies, the various apparatuses, systems, and methods described herein can provide a self-contained solution for conducting mission-mode testing on high-speed links facilitated, provided, and/or supported by data fabric devices without the need to modify the mechanical handlers or gantries included and/or involved in the existing SLT technologies. By doing so, these apparatuses, systems, and methods can improve the SLT of high-speed links and/or data fabric devices and significantly reduce the costs necessary to achieve this improved SLT by avoiding superfluous endpoint purchases and/or increasing (e.g., doubling) the board density of the mechanical handlers and/or gantries.

As will be described in greater detail below, an exemplary self-contained solution for SLT of high-speed links and/or data fabric devices can include and/or involve diverting traffic destined for a specific endpoint from the typical data path to a worst-case data path (or scenic route) as the high-speed links undergo training in mission mode. As used herein, the terms “mission mode” and “mission-mode testing” generally refer to training and/or testing that mimic and/or simulate the mode of operation implemented by high-speed links and/or data fabric devices upon field deployment and/or user operation. In one example, this solution includes and/or involves changing the programmed routing of the data fabric to route data and/or traffic to a socket-to-socket global memory interconnect (xGMI) controller. By doing so, this solution enables the data and/or traffic to travel and/or traverse high-speed communication links (e.g., SerDes links, physical layer links, etc.) for training and/or testing purposes. In certain implementations, the high-speed communication links and/or endpoints can constitute and/or represent components of the data fabric.

In some examples, this solution can modify the xGMI controller to interpret the data and/or traffic directed to those high-speed communication links differently via a design-for-test (DFT) feature. For example, this solution can include and/or involve the xGMI controller sending traffic from one high-speed communication link to another through a wire-to-wire connection. In this example, the DFT feature can cause the xGMI controller to spoof an address of the traffic to specify and/or indicate a remote socket, thereby leading the xGMI controller to interpret the outgoing traffic as exiting the data fabric for a remote socket. However, instead of actually going to a remote socket, the traffic is diverted to another xGMI controller on the data fabric via the other high-speed communication link.

In some examples, as the traffic arrives at the other xGMI controller, the DFT feature can cause the other xGMI controller to replace the spoofed address of the traffic with another address that specifies a local socket. In such examples, the other xGMI controller then sends the traffic toward the specific endpoint based on the other address as part of the SLT. In one example, to force the traffic from the typical data path to the worst-case data path, the DFT feature can cause the addresses of attached double data rate (DDR) memory devices to be interleaved relative to one another. By doing so, the DFT feature can cause the traffic to go across and/or pass through the high-speed communication links to reach a remote node of DDR memory on the socket. This forced diversion of the traffic can essentially make the physical layer of the Open Systems Interconnection (OSI) model appear as part of the data fabric.

In some examples, a data fabric device includes a first traffic moderator configured to receive traffic destined for a specific endpoint accessible via a plurality of data paths and/or divert the traffic from a first data path included in the data paths to a second data path included in the data paths. In such examples, the data fabric device includes a first interconnect controller that resides within the second data path and is configured to forward the traffic to the specific endpoint via a first communication link to test a functionality of the first communication link.

In some examples, the first interconnect controller is configured to spoof an address of the traffic to specify a remote socket and then send the traffic toward the specific endpoint via the first communication link based at least in part on the spoofed address of the traffic. In one example, the data fabric device also includes a second interconnect controller that resides within the second data path and is configured to receive the traffic destined for the specific endpoint via a second communication link and replace the spoofed address of the traffic with an additional address that specifies a local socket. In this example, the second interconnect controller is further configured to send the traffic further toward the specific endpoint based at least in part on the additional address. In certain implementations, the first communication link and the second communication link are communicatively coupled to one another.

In some examples, the data fabric device also includes a plurality of memory devices whose addresses are interleaved relative to one another. In such examples, the specific endpoint represents a specific memory device included in the memory devices.

In some examples, the data fabric device also includes a processing device that directs the first traffic moderator to enable a system-level test (SLT) mode. In such examples, the first traffic moderator diverts the traffic from the first data path to the second data path due at least in part to the SLT mode being enabled.

In some examples, the first traffic moderator is further configured to perform an address lookup for the traffic in SLT mode and/or identify an address corresponding to the specific endpoint via the second data path. In such examples, the first traffic moderator is also configured to apply the address to the traffic to direct the traffic along the second data path to the first interconnect controller.

In some examples, the processing device is further configured to direct the first traffic moderator to disable the SLT mode upon completion of a system test. In such examples, the first traffic moderator is configured to disable the SLT mode in response to the direction from the processing device by clearing a register responsible for setting the SLT mode. In one example, the processing device is further configured to achieve the disabling of the SLT mode without rebooting the data fabric device.

In some examples, the data fabric device also includes a second traffic moderator configured to receive additional traffic destined for an additional endpoint accessible via a plurality of additional data paths and/or divert the traffic from a first data path included in the additional data paths to a second data path included in the additional data paths. In such examples, the data fabric device further includes a second interconnect controller that resides within the second data path and is configured to forward the additional traffic to the additional endpoint via a second communication link to test a functionality of the second communication link.

In some examples, the data fabric device also includes a first network socket implemented in connection with the first traffic moderator and the first interconnect controller. In such examples, the data fabric device further includes a second network socket implemented in connection with the second traffic moderator and the second interconnect controller. In one example, the first communication link and second communication link collectively form and/or facilitate a socket-to-socket connection for testing the first network socket and the second network socket by simulating communication at an operational speed.

In some examples, the data fabric device, also includes a first integrated circuit (IC) die that implements the first network socket and a second IC die that implements the second network socket. In such examples, the socket-to-socket connection spans across the first IC die and the second IC die.

In some examples, the first traffic moderator constitutes a cache-coherent moderator, and the first interconnect controller constitutes a coherent socket extender. In one example, the data fabric device also includes at least one global memory interconnect (GMI) that is communicatively coupled to the first traffic moderator and configured to connect at least one processing device to the specific endpoint via the first traffic moderator, the first interconnect controller, and/or the first communication link. In this example, the GMI is further configured to receive the traffic from the processing device and/or feed the traffic to the first traffic moderator for transmission to the specific endpoint via the first communication link. In certain implementations, the specific endpoint constitutes a DDR memory device, and/or the first communication link constitutes a SerDes link.

In some examples, a system includes a test board, at least one endpoint device installed on the test board, and/or a data fabric device installed on the test board. In such examples, the data fabric device includes a first traffic moderator configured to receive traffic destined for the endpoint device and/or divert the traffic from a first data path to a second data path. In one example, the data fabric device also includes a first interconnect controller that resides within the second data path and is configured to forward the traffic to the endpoint via a first communication link to test a functionality of the first communication link.

In some examples, a method includes receiving, by a traffic moderator of a data fabric, traffic destined for a specific endpoint accessible via a plurality of data paths. In such examples, the method also includes diverting, by the traffic moderator of the data fabric, the traffic from a first data path included in the data paths to a second data path included in the data paths. In one example, the method further includes forwarding, by an interconnect controller of the data fabric that resides within the second data path, the traffic to the specific endpoint via a communication link to test a functionality of the first communication link.

The following will provide, with reference toFIGS.1-6, detailed descriptions of exemplary apparatuses, devices, systems, and/or corresponding implementations for conducting mission-mode testing on high-speed links. Detailed descriptions of an exemplary method for conducting mission-mode testing on high-speed links will be provided in connection withFIG.7.

FIG.1illustrates a portion of an exemplary data fabric device100capable of conducting self-contained mission-mode testing. As illustrated inFIG.1, exemplary data fabric device100includes and/or represents various traffic moderators, switches, interconnect controllers, and/or endpoints. For example, data fabric device100can include and/or represent traffic moderators102(1)-(N),112(1)-(N),122(1)-(N), and/or132(1)-(N). In this example, data fabric device100can also include and/or represent switches104(1),104(2),104(3),104(4),104(5),104(6), and/or104(7). Additionally or alternatively, data fabric device100can include and/or represent interconnect controllers114(1)-(N) and/or124(1)-(N) as well as endpoints106(1)-(N),116(1)-(N),126(1)-(N), and/or136(1)-(N). In certain implementations, interconnect controllers114(1)-(N) can be communicatively coupled to one another via high-speed links144, and/or interconnect controllers124(1)-(N) can be communicatively coupled to one another via high-speed links146.

In some examples, switch104(1) is communicatively coupled between traffic moderators102(1)-(N), endpoints106(1)-(N), and/or switch104(2). In such examples, switch104(1) provides, facilitates, and/or supports communication among traffic moderators102(1)-(N), endpoints106(1)-(N), and/or switch104(2). In one example, switch104(1) can perform packet switching and/or data standardization for data and/or traffic exchanged between traffic moderators102(1)-(N), endpoints106(1)-(N), and/or switch104(2).

In some examples, switch104(3) is communicatively coupled between traffic moderators132(1)-(N), endpoints136(1)-(N), and/or switch104(2). In such examples, switch104(3) provides, facilitates, and/or supports communication among traffic moderators132(1)-(N), endpoints136(1)-(N), and/or switch104(2). In one example, switch104(3) can perform packet switching and/or data standardization for data and/or traffic exchanged between traffic moderators132(1)-(N), endpoints136(1)-(N), and/or switch104(2).

In some examples, switch104(6) is communicatively coupled between traffic moderators112(1)-(N), endpoints116(1)-(N), and/or switch104(5). In such examples, switch104(6) provides, facilitates, and/or supports communication among traffic moderators112(1)-(N), endpoints116(1)-(N), and/or switch104(5). In one example, switch104(6) can perform packet switching and/or data standardization for data and/or traffic exchanged between traffic moderators112(1)-(N), endpoints116(1)-(N), and/or switch104(5).

In some examples, switch104(7) is communicatively coupled between traffic moderators122(1)-(N), endpoints126(1)-(N), and/or switch104(5). In such examples, switch104(7) provides, facilitates, and/or supports communication among traffic moderators122(1)-(N), endpoints126(1)-(N), and/or switch104(5). In one example, switch104(3) can perform packet switching and/or data standardization for data and/or traffic exchanged between traffic moderators122(1)-(N), endpoints126(1)-(N), and/or switch104(5).

In some examples, switch104(4) is communicatively coupled between interconnect controllers114(1)-(N), interconnect controllers124(1)-(N), and/or switches104(2) and104(5). In such examples, switch104(4) provides, facilitates, and/or supports communication among interconnect controllers114(1)-(N), interconnect controllers124(1)-(N), and/or switches104(2) and104(5). In one example, switch104(4) can perform packet switching and/or data standardization for data and/or traffic exchanged between traffic moderators122(1)-(N), endpoints126(1)-(N), and/or switch104(5).

In some examples, data fabric device100implements and/or applies a DFT feature that, when activated, can cause one or more of traffic moderators102(1)-(N),112(1)-(N),122(1)-(N), and/or132(1)-(N) to modify and/or divert data or traffic to the worst-case data path. By doing so, the DFT feature enables data fabric device100to comprehensively test certain functionalities and/or features of high-speed links144and146, which lie outside the typical data path for such traffic, as part of an SLT.

In some examples, traffic arrives at traffic moderator102(1) from one or more processing devices, such as a central processing unit (CPU) and/or a graphics processing unit (GPU). In one example, this traffic is destined for a specific endpoint included in and/or connected to data fabric device100. For example, traffic destined for endpoint126(N) can arrive at traffic moderator102(1). In this example, if the DFT feature is activated as part of an SLT, traffic moderator102(1) receives the traffic destined for endpoint126(N), which is accessible via at least data paths138and140, and then diverts the traffic from data path138to data path140. In other words, traffic moderator102(1) can reroute traffic destined for endpoint126(N) to take one or more of high-speed links144to reach endpoint126(N), instead of simply traversing straight across switches104(2),104(4), and/or104(6), when the DFT feature is activated for training and/or testing purposes.

In some examples, data path138can constitute and/or represent the typical and/or best-case data path for traffic travelling and/or traversing from traffic moderator102(1) to endpoint126(N). In one example, data path138includes and/or represents the route and/or path across traffic moderator102(1), switch104(1), switch104(2), switch104(4), switch104(5), switch104(7), and/or endpoint126(N). In this example, data path138constitutes and/or represents this sequence and/or order of traversal from traffic moderator102(1) to endpoint126(N). Accordingly, data path138excludes and/or omits interconnect controllers114(1)-(N) and124(1)-(N) as well as high-speed links144and146.

In contrast, data path140can constitute and/or represent the scenic route and/or worst-case data path for traffic travelling and/or traversing from traffic moderator102(1) to endpoint126(N). In one example, data path140includes and/or represents the route and/or path across traffic moderator102(1), switch104(1), switch104(2), switch104(4), interconnect controller114(1), one or more of high-speed links144, interconnect controller114(N), switch104(4), switch104(5), switch104(7), and/or endpoint126(N). In this example, data path140constitutes and/or represents this sequence and/or order of traversal from traffic moderator102(1) to endpoint126(N). Accordingly, in contrast to data path138, data path140includes and/or represents interconnect controllers114(1) and114(N) as well as high-speed links144and146.

In some examples, when the DFT feature is activated, one or more components of data fabric device200can implement and/or apply an SLT mode in which high-speed links144and146are trained and/or tested. In SLT mode, traffic moderator102(1) can perform an address lookup for the traffic destined for endpoint126(N). In one example, as part of this address lookup, traffic moderator102(1) identifies an address corresponding to endpoint126(N) via and/or along data path140. In this example, traffic moderator102(1) then applies this address to the traffic to direct the traffic along data path140toward interconnect controller114(1), thus forcing the traffic to pass through one or more of high-speed links144on the way to endpoint126(N).

In some examples, interconnect controller114(1) resides within and/or along data path140but not within and/or along data path138. In one example, interconnect controller114(1) is configured to forward and/or send the traffic toward endpoint126(N) via one or more of high-speed links144. By doing so, interconnect controller114(1) can contribute to and/or facilitate training and/or testing the functionality (e.g., communication, speed, connectivity, and/or reliability) of high-speed links144.

In some examples, the processes and/or features described above in connection with data paths138and140can also be applied and/or iterated across all routes and/or data paths of data fabric device100to facilitate a comprehensive SLT in mission mode. For example, traffic moderator102(1) can divert test data and/or traffic to comparable worst-case data paths to reach endpoints via all of high-speed links144and/or high-speed links146for SLT purposes. Similarly, traffic moderators102(N),112(1)-(N),122(1)-(N), and132(1)-(N) can also divert test data and/or traffic to worst-case data paths to reach endpoints via all of high-speed links144and/or high-speed links146for SLT purposes.

As a specific example, traffic moderator112(N) can receive traffic destined for endpoint106(1) from one or more processing devices, such as a CPU core and/or a GPU core. In this example, if the DFT feature is activated as part of an SLT, traffic moderator112(N) can divert traffic from the typical and/or best-case data path to a scenic route and/or worst-case data path via one or more of high-speed links144or146on the way to endpoint106(1). For example, traffic moderator112(N) can force traffic along the scenic route and/or worst-case data path to endpoint106(1) via high-speed links144or146when the DFT feature is activated as part of the SLT. In one example, interconnect controller114(N) can forward and/or send the traffic toward endpoint106(1) via one of high-speed links144to test its functionality. Additionally or alternatively, interconnect controller124(N) can forward and/or send the traffic toward endpoint106(1) via one of high-speed links146to test its functionality.

In some examples, the DFT feature that enables the SLT mode can cause multiple memory devices to implement an interleaved address configuration. For example, endpoints106(1)-(N),116(1)-(N),126(1)-(N), and/or136(1)-(N) can include and/or represent DDR dynamic random access memory (DRAM) devices and/or sticks. In this example, the addresses of the DDR DRAM devices and/or channels can be interleaved relative to one another.

In some examples, the memory for a particular workload can be diced up and/or distributed equally across all the DDR DRAM devices and/or channels during the SLT. In such examples, this equal dicing and/or distribution of memory across all the DDR DRAM devices and/or channels causes traffic to travel and/or traverse across all the various routes and/or data paths when executing and/or running a certain program and/or application.

In some examples, data fabric device100can constitute and/or represent a portion of a larger microprocessor. For example, data fabric device100can constitute and/or represent circuitry in a microprocessor that includes various CPU and/or GPU cores, IC dies, physical layer devices and/or circuits (sometimes referred to as “PHYs”), interfaces, memory devices, sockets, GMIs, along with various additional circuits, devices, and/or features. Additionally or alternatively, data fabric device100can constitute and/or represent a standalone interconnection architecture that facilitates connecting, standardizing, and/or integrating various devices and/or protocols with one another.

In some examples, traffic moderators102(N),112(1)-(N),122(1)-(N), and132(1)-(N) can each include and/or represent a cache-coherent moderator. Additionally or alternatively, traffic moderators102(N),112(1)-(N),122(1)-(N), and132(1)-(N) can each include and/or represent a request agent and/or interface. In one example, traffic moderators102(N),112(1)-(N),122(1)-(N), and132(1)-(N) are responsible for issuing DRAM requests and/or facilitating coherent data transports between processing cores.

In some examples, interconnect controllers114(1)-(N) and124(1)-(N) can each include and/or represent a coherent socket extender and an xGMI controller. In such examples, interconnect controllers114(1)-(N) and124(1)-(N) can interface and/or connect different sockets and/or dies together or with one another via high-speed links144and/or146. In one example, interconnect controllers114(1)-(N) and124(1)-(N) can encode certain data and/or traffic requests into serialized packets for transmission via high-speed links144and/or146. Additionally or alternatively, interconnect controllers114(1)-(N) and124(1)-(N) can decode certain data and/or traffic responses received via high-speed links144and/or146into deserialized packets.

In some examples, switches104(1)-(7) can each include and/or represent a network-on-chip (NoC) switch. Additionally or alternatively, switches104(1)-(7) can each include and/or represent a crossbar switch. In one example, switches104(1)-(7) each have the routing function to transmit packets from a source to a destination.

In some examples, high-speed links144and146can each include and/or represent SerDes interfaces, connections, and/or links. Additionally or alternatively, high-speed links144and146can each include and/or represent physical layer links and/or “PHY” devices and/or circuits. In one example, high-speed links144can be formed and/or established by interfacing interconnect controllers114(1) and114(N) to one another, and/or high-speed links146can be formed and/or established by interfacing interconnect controllers124(1) and124(N) to one another. In this example, the physical layer links and/or “PHY” devices and/or circuits can appear to be part of the data fabric.

In some examples, endpoints106(1)-(N),116(1)-(N),126(1)-(N), and/or136(1)-(N) can each include and/or represent a memory device incorporated into and/or connected to data fabric device100. For example, endpoints106(1)-(N),116(1)-(N),126(1)-(N), and/or136(1)-(N) can each include and/or represent a DDR DRAM device. In one example, each DDR DRAM device can be installed and/or inserted into a test board that holds data fabric device100for the SLT. Additionally or alternatively, endpoints106(1)-(N),116(1)-(N),126(1)-(N), and/or136(1)-(N) can each include and/or represent a coherent station and/or home agent.

FIG.2illustrates a portion of an exemplary data fabric device200capable of conducting self-contained mission-mode testing. As illustrated inFIG.2, exemplary data fabric device200(like data fabric device100inFIG.1) includes and/or represents various traffic moderators, switches, interconnect controllers, and/or endpoints. In some examples, data fabric device200can include and/or represent certain components and/or features that perform and/or provide functionalities that are similar and/or identical to those described above in connection withFIG.1. In one example, data fabric device200can implement, facilitate, and/or establish various network sockets in connection with different components, IC dies, and/or processing devices.

In some examples, data fabric device200can implement and/or instantiate a socket204(1) in connection with one or more of traffic moderators102(1)-(N), endpoints106(1)-(N), and/or interconnect controller114(1). In such examples, data fabric device200can implement and/or instantiate a socket204(2) in connection with one or more of traffic moderators112(1)-(N), endpoints116(1)-(N), and/or interconnect controller114(N). In one example, data fabric device200can implement and/or instantiate a socket204(3) in connection with one or more of traffic moderators122(1)-(N), endpoints126(1)-(N), and/or interconnect controller124(N). Additionally and/or alternatively, data fabric device200can implement and/or instantiate a socket204(4) in connection with one or more of traffic moderators132(1)-(N), endpoints136(1)-(N), and/or interconnect controller124(1).

In some examples, high-speed links144between interconnect controllers114(1) and114(N) can form, constitute, and/or represent a socket-to-socket connection for training and/or testing sockets204(1) and204(2) by simulating communication at operational speed (e.g., the same speed used during field deployment). In some examples, high-speed links146between interconnect controllers124(1) and124(N) can form, constitute, and/or represent a socket-to-socket connection for training and/or testing sockets204(3) and204(4) by simulating communication at operational speed (e.g., the same speed used during field deployment).

In some examples, data fabric device200can be distributed and/or disposed across multiple IC dies. For example, one IC die can implement and/or instantiate socket204(1), and another IC die can implement and/or instantiate socket204(2). Additionally or alternatively, one IC die can implement and/or instantiate socket204(3), and another IC die can implement and/or instantiate socket204(4). Accordingly, the socket-to-socket connection can span across multiple dies. As a result, data fabric device200can implement and/or provide die-to-die communication via high-speed links144and146.

FIG.3illustrates an exemplary implementation of exemplary socket204. As illustrated inFIG.3, exemplary socket204(1) can include and/or represent certain components and/or features that perform and/or provide functionalities that are similar and/or identical to those described above in connection withFIG.1or2. In some examples, socket204(1) can include and/or represent processing devices302(1)-(N) and/or GMIs304(1)-(N) and GMI306. In one example, GMIs304(1)-(N) are communicatively coupled between processing device302(1) and traffic moderator102(1). Additionally or alternatively, GMI306is communicatively coupled between processing device302(N) and traffic moderator102(N).

In some examples, one or more of processing devices302(1)-(N) can direct and/or cause one or more of traffic moderators102(1)-(N) to enable and/or activate the DFT feature and/or the SLT mode via firmware and/or a basic input/output system (BIOS). In one example, one or more of traffic moderators102(1)-(N) can divert traffic from typical and/or best-case data paths to scenic routes and/or worst-case data paths due at least in part to the DFT feature and/or SLT mode being enable and/or activated.

In some examples, upon completion of the SLT, one or more of processing devices302(1)-(N) can direct and/or cause one or more of traffic moderators102(1)-(N) to disable and/or deactivate the DFT feature and/or the SLT mode via the firmware and/or BIOS. In response, one or more of traffic moderators102(1)-(N) can disable and/or deactivate the DFT feature and/or the SLT mode by clearing a register responsible for engaging the DFT feature and/or setting the SLT mode. In one example, processing devices302(1)-(N) and/or traffic moderators102(1)-(N) can achieve and/or complete the disabling and/or deactivation of the DFT feature or SLT mode without rebooting data fabric device100. In this example, the traffic subsequently originating from processing devices302(1)-(N) can travel and/or traverse along the typical and/or best-case data paths and/or avoid the scenic routes and/or worst-case data paths.

In some examples, GMIs304(1)-(N) can effectively connect processing device302(1) to one or more of endpoints106(1)-(N),116(1)-(N),126(1)-(N), and/or136(1)-(N) via traffic moderator102(1), and GMI306can effectively connect processing device302(1) to such endpoints via traffic moderator102(N). As a specific example, GMI304(1) can receive the traffic destined for endpoint126(N) and/or feed that traffic to traffic moderator102(1) for transmission to endpoint126(N) via data path140and/or one or more of high-speed links144.

In some examples, processing devices302(1)-(N) can each include and/or represent any type or form of hardware-implemented device and/or circuit capable of generating data and/or traffic for transmission across high-speed links144or146. For example, one or more of processing devices302(1)-(N) can include and/or represent a GPU and/or a GPU core. In another example, one or more of processing devices302(1)-(N) can include and/or represent a CPU and/or a CPU core. Additional examples of processing devices302(1)-(N) include, without limitation, parallel accelerated processors, tensor cores, microprocessors, microcontrollers, field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), systems on a chip (SoCs), integrated circuits, chiplets, portions of one or more of the same, variations or combinations of one or more of the same, and/or any other suitable processing devices.

FIG.4illustrates a portion of exemplary data fabric device400. As illustrated inFIG.4, data fabric device400can include and/or represent certain components and/or features that perform and/or provide functionalities that are similar and/or identical to those described above in connection with any ofFIGS.1-3. In some examples, data fabric device400can include and/or represent interconnect controllers114(1),114(2),114(3),114(4),124(1),124(2),124(3), and/or124(4) that are all communicatively coupled to switch104(4). In one example, high-speed links144inFIG.1correspond to and/or represent communication links402(1),402(2),402(3), and/or402(4) inFIG.4. In this example, high-speed links146inFIG.1correspond to and/or represent communication links412(1),412(2),412(3), and/or412(4) inFIG.4.

In some examples, interconnect controllers114(1)-(4) and124(1)-(4) can spoof the address of traffic to specify a remote socket (e.g., one apparently external to data fabric device100and/or the underlying processor) when the DFT feature is activated and/or the SLT mode is enabled. For example, interconnect controller114(1) scrubs and/or removes an existing address from the traffic destined for endpoint126(N). Additionally or alternatively, interconnect controller114(1) can replace that address in the traffic with a different address that appears to correspond to a remote socket, thereby leading interconnect controller114(1) to believe that this outgoing traffic is exiting data fabric device100and/or the underlying processor for a remote socket. However, instead of actually going to a remote socket, the traffic is diverted to interconnect controller114(3) via communication links402(1) and402(3).

In some examples, interconnect controllers114(1)-(4) and124(1)-(4) can replace the spoofed address of the traffic with another address that specifies a local socket when the DFT feature is activated and/or the SLT mode is enabled. For example, interconnect controller114(3) receives the traffic destined for endpoint126(N) via communication links402(1) and402(3). In this example, interconnect controller114(3) then replaces the spoofed address of the traffic with an additional address that specifies socket204(3) inFIG.2as the location of the destination endpoint. Additionally or alternatively, interconnect controller114(3) sends the traffic further toward endpoint126(N) based at least in part on that additional address.

In some examples, communication link402(1) includes and/or represents a SerDes link for interconnect controller114(1), and communication link402(3) includes and/or represents a SerDes link for interconnect controller114(3). In one example, communication links402(1) and402(3) are communicatively coupled to one another by a wire-to-wire connection. In a specific implementation, data path140includes and/or represents communication links402(1) and402(3), and thus the traffic destined for endpoint126(N) during an SLT passes through communication links402(1) and402(3).

In some examples, communication link402(2) includes and/or represents a SerDes link for interconnect controller114(2), and communication link402(4) includes and/or represents a SerDes link for interconnect controller114(4). In one example, communication links402(2) and402(4) are communicatively coupled to one another by a wire-to-wire connection. In a specific implementation, data path140includes and/or represents communication links402(2) and402(4), and thus the traffic destined for endpoint126(N) during the SLT passes through communication links402(2) and402(4).

In some examples, communication link412(1) includes and/or represents a SerDes link for interconnect controller124(1), and communication link412(3) includes and/or represents a SerDes link for interconnect controller124(3). In one example, communication links412(1) and412(3) are communicatively coupled to one another by a wire-to-wire connection. In a specific implementation, a worst-case data path for some traffic includes and/or represents communication links412(1) and412(3), and thus that traffic can traverse from a traffic moderator to an endpoint through communication links412(1) and412(3) during the SLT.

In some examples, communication link412(2) includes and/or represents a SerDes link for interconnect controller124(2), and communication link412(4) includes and/or represents a SerDes link for interconnect controller124(4). In one example, communication links412(2) and412(4) are communicatively coupled to one another by a wire-to-wire connection. In a specific implementation, a worst-case data path for some traffic includes and/or represents communication links412(2) and412(4), and thus that traffic can traverse from a traffic moderator to an endpoint through communication links412(2) and412(4) during the SLT.

FIG.5illustrates an exemplary system500for conducting mission-mode testing on high-speed links and/or data fabric devices. As illustrated inFIG.5, exemplary system500can include and/or represent various interfaces, devices, components, and/or features. In some examples, system500can include and/or represent certain components and/or features that perform and/or provide functionalities that are similar and/or identical to those described above in connection with any ofFIGS.1-4. In one example, system500includes and/or represents a test board502with a processor506, memory devices504, and/or communication links510. In this example, processor506includes and/or incorporates data fabric device100, and all or a portion of processor506constitutes and/or represents a device under test (DUT). Additionally or alternatively, processor506and/or memory devices504are installed and/or inserted into corresponding slots available on test board502.

In some examples, test board502is incorporated into and/or controlled by a mechanical handler and/or gantry for conducting SLT on processor506and/or data fabric device100. In one example, test board502includes and/or provides various peripherals that facilitate and/or support conducting SLT on processor506and/or data fabric device100. Examples of such peripherals include, without limitation, one or more (UART) interfaces and/or connection ports, universal serial bus (USB) interfaces and/or connection ports, joint test action group (JTAG) interfaces and/or connection ports, general purpose input/output (GPIO) signals and/or pins, RJ45 connection ports, serial peripheral interface (SPI) read-only memory (ROM) devices, video graphics array (VGA) interfaces and/or connections ports, server management processors, LAN-on-motherboard (LOM) adapter cards, PCIe cards, system power regulators, power sequencing logic, high-speed connections, portions of one or more of the same, variations or combinations of one or more of the same, and/or any other suitable peripherals and/or components.

In some examples, test board502includes and/or represents a circuit board (e.g., a printed circuit board) that contains a variety of materials. Some of these materials included in test board502can conduct electricity. Other materials included in test board502can insulate the conductive materials from one another.

In some examples, test board502can include and/or incorporate various electrically conductive layers, planes, and/or traces. In one example, each electrically conductive layer, plane, and/or trace can include and/or represent conductive material that is etched during fabrication. Additionally or alternatively, test board502can include and/or incorporate insulating material that facilitates mounting (e.g., mechanical support) and/or interconnection (e.g., electrical coupling) of electrical and/or electronic components.

FIG.6illustrates an exemplary implementation of test board502for conducting mission-mode testing on high-speed links and/or data fabric devices. As illustrated inFIG.6, exemplary test board502can include and/or represent various interfaces, devices, components, and/or features. In some examples, test board502can include and/or represent certain components and/or features that perform and/or provide functionalities that are similar and/or identical to those described above in connection with any ofFIGS.1-5. For example, test board502can include and/or represent processor506, which is the DUT for the SLT, as well as memory devices504.

In some examples, test board502can also include and/or represent one or more connection cards602that serve and/or function as wire-to-wire connections. For example, connection cards602can provide and/or serve as electrical and/or communication couplings between communication links402(1)-(4) and/or communication links412(1)-(4) inFIG.4. In this example connection cards602can communicatively couple interconnect controllers114(1),114(2),124(1), and124(2) to interconnect controllers114(3),114(4),124(3), and124(4), respectively.

In some examples, the various apparatuses, devices, and/or systems described in connection withFIGS.1-6can include and/or represent one or more additional circuits, components, devices, and/or features that are not necessarily illustrated and/or labeled inFIGS.1-6. For example, data fabric device100can also include and/or represent additional analog and/or digital circuitry, onboard logic, transistors, resistors, capacitors, diodes, inductors, switches, registers, flipflops, connections, traces, buses, semiconductor (e.g., silicon) devices and/or structures, processing devices, storage devices, circuit boards, packages, substrates, housings, combinations or variations of one or more of the same, and/or any other suitable components that facilitate and/or support mission-mode training and/or testing. In certain implementations, one or more of these additional circuits, components, devices, and/or features can be inserted and/or applied between any of the existing circuits, components, and/or devices illustrated inFIGS.1-6consistent with the aims and/or objectives provided herein. Accordingly, the communicative and/or electrical couplings described with reference toFIGS.1-6can be direct connections with no intermediate components, devices, and/or nodes or indirect connections with one or more intermediate components, devices, and/or nodes.

In some examples, the phrase “to couple” and/or the term “coupling”, as used herein, can refer to a direct connection and/or an indirect connection. For example, a direct electrical coupling between two components can constitute and/or represent a coupling in which those two components are directly connected to each other by a single node that provides electrical continuity from one of those two components to the other. In other words, the direct coupling can exclude and/or omit any additional components between those two components.

Additionally or alternatively, an indirect electrical coupling between two components can constitute and/or represent a coupling in which those two components are indirectly connected to each other by multiple nodes that fail to provide electrical continuity from one of those two components to the other. In other words, the indirect coupling can include and/or incorporate at least one additional component between those two components.

FIG.7is a flow diagram of an exemplary method700for conducting mission-mode testing on data fabric devices. In one example, the steps shown inFIG.7can be performed and/or executed during mission-mode SLT conducted on a data fabric device. Additionally or alternatively, the steps shown inFIG.7can also incorporate and/or involve various sub-steps and/or variations consistent with the descriptions provided above in connection withFIGS.1-6.

As illustrated inFIG.7, exemplary method700include and/or involve the step of receiving traffic destined for a specific endpoint accessible via a plurality of data paths (710). Step710can be performed in a variety of ways, including any of those described above in connection withFIGS.1-6. For example, a traffic moderator of a data fabric receives traffic destined for a specific endpoint accessible via a plurality of data paths.

Exemplary method700also includes the step of diverting the traffic from a first data path included in the data paths to a second data path included in the data paths (720). Step720can be performed in a variety of ways, including any of those described above in connection withFIGS.1-6. For example, the traffic moderator of the data fabric diverts the traffic from a first data path included in the data paths to a second data path included in the data paths.

Exemplary method700further includes the step of forwarding the traffic to the specific endpoint via a communication link to test a functionality of the first communication link (730). Step730can be performed in a variety of ways, including any of those described above in connection withFIGS.1-6. For example, an interconnect controller of the data fabric forwards the traffic to the specific endpoint via a communication link to test a functionality of the first communication link.

While the foregoing disclosure sets forth various implementations using specific block diagrams, flowcharts, and examples, each block diagram component, flowchart step, operation, and/or component described and/or illustrated herein can be implemented, individually and/or collectively, using a wide range of hardware, software, or firmware (or any combination thereof) configurations. In addition, any disclosure of components contained within other components should be considered exemplary in nature since many other architectures can be implemented to achieve the same functionality. Furthermore, the various steps, events, and/or features performed by such components should be considered exemplary in nature since many alternatives and/or variations can be implemented to achieve the same functionality within the scope of this disclosure.

The process parameters and sequence of the steps described and/or illustrated herein are given by way of example only and can be varied as desired. For example, while the steps illustrated and/or described herein are shown or discussed in a particular order, these steps do not necessarily need to be performed in the order illustrated or discussed. The various exemplary methods described and/or illustrated herein can also omit one or more of the steps described or illustrated herein or include additional steps in addition to those disclosed.

The preceding description has been provided to enable others skilled in the art to best utilize various aspects of the exemplary implementations disclosed herein. This exemplary description is not intended to be exhaustive or to be limited to any precise form disclosed. Many modifications and variations are possible without departing from the spirit and scope of the instant disclosure. The implementations disclosed herein should be considered in all respects illustrative and not restrictive. Reference should be made to the appended claims and their equivalents in determining the scope of the instant disclosure.

Unless otherwise noted, the terms “connected to” and “coupled to” (and their derivatives), as used in the specification and claims, are to be construed as permitting both direct and indirect (i.e., via other elements or components) connection. In addition, the terms “a” or “an,” as used in the specification and claims, are to be construed as meaning “at least one of.” Finally, for ease of use, the terms “including” and “having” (and their derivatives), as used in the specification and claims, are interchangeable with and have the same meaning as the word “comprising.”