Patent ID: 12250485

Corresponding reference characters indicate corresponding components throughout the several views of the drawings. Skilled artisans will appreciate that elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. For example, the dimensions of some of the elements in the figures may be exaggerated relative to other elements to help to improve understanding of various embodiments of the present invention. In addition, common but well-understood elements that are useful or necessary in a commercially feasible embodiment are often not depicted in order to facilitate a less obstructed view of these various embodiments of the present invention.

DETAILED DESCRIPTION

Examples directed to an imaging system including a readout circuit with a current integration ramp generator with a low power ramp settling assist circuit are described herein. In the following description, numerous specific details are set forth to provide a thorough understanding of the examples. One skilled in the relevant art will recognize, however, that the techniques described herein can be practiced without one or more of the specific details, or with other methods, components, materials, etc. In other instances, well-known structures, materials, or operations are not shown or described in detail in order to avoid obscuring certain aspects.

Reference throughout this specification to “one example” or “one embodiment” means that a particular feature, structure, or characteristic described in connection with the example is included in at least one example of the present invention. Thus, the appearances of the phrases “in one example” or “in one embodiment” in various places throughout this specification are not necessarily all referring to the same example. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more examples.

Spatially relative terms, such as “beneath,” “below,” “over,” “under,” “above,” “upper,” “top,” “bottom,” “left,” “right,” “center,” “middle,” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is rotated or turned over, elements described as “below” or “beneath” or “under” other elements or features would then be oriented “above” the other elements or features. Thus, the exemplary terms “below” and “under” can encompass both an orientation of above and below. The device may be otherwise oriented (rotated ninety degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly. In addition, it will also be understood that when an element is referred to as being “between” two other elements, it can be the only element between the two other elements, or one or more intervening elements may also be present.

Throughout this specification, several terms of art are used. These terms are to take on their ordinary meaning in the art from which they come, unless specifically defined herein or the context of their use would clearly suggest otherwise. It should be noted that element names and symbols may be used interchangeably through this document (e.g., Si vs. silicon); however, both have identical meaning.

As will be discussed, various examples of an imaging system including a readout circuit with a current integration ramp generator with a low power ramp settling assist circuit are described. In various examples, the ramp generator is a current integration ramp generator including an operational amplifier configured as an integrator with feedback capacitor coupled between an input and an output of the operational amplifier. An integration current source is also coupled to the input of the operational amplifier. In the examples, a low power ramp settling assist circuit includes an assist current source that is coupled between the output of the current integration ramp generator and ground. In the examples, the low power ramp settling assist circuit provides an assist current from the output of the ramp generator to ground that is switched on during a ramp event or a ramp phase of the output ramp signal of the ramp generator. For purposes of this disclosure, it is appreciated that a ramp event of the output ramp signal is the time during which the ramp signal decreases continuously. In another example, it is appreciated that the ramp event of the output ramp signal could also be considered as the time during which the ramp signal increases continuously. An output capacitor coupled to the output of the ramp generator is discharged by assist current, which therefore reduces a ramp settling time of the ramp signal that is caused by loading of the output of the ramp generator, which therefore improves the maximum frame rate and image sensor performance in accordance with the teachings of the present invention.

To illustrate,FIG.1shows one example of an imaging system100including a readout circuit with a current integration ramp generator with a low power ramp settling assist circuit in accordance with the teachings of the present invention. As shown in the illustrated example, imaging system100includes a pixel array102, a control circuit110, a readout circuit106, and function logic108. In one example, pixel array102is a two-dimensional (2D) array including a plurality of pixel circuits104(e.g., P1, P2, . . . , Pn) that are arranged into rows (e.g., R1 to Ry) and columns (e.g., C1 to Cx) to acquire image data of a person, place, object, etc., which can then be used to render an image of a person, place, object, etc.

In various examples, each pixel circuit104may include one or more photodiodes configured to photogenerate image charge in response to incident light. The image charge generated in each photodiode is transferred to a floating diffusion included in each pixel circuit104, which is converted to an image signal and then read out from each pixel circuit104by readout circuit106through column bitlines112. In the various examples, readout circuit106may read out a row of image data at a time along readout column bitlines112(illustrated) or may read out the image data using a variety of other techniques (not illustrated), such as a serial readout or a full parallel readout of all pixel circuits104simultaneously.

In various examples, readout circuit106may include amplification circuitry, an analog to digital converter (ADC), or otherwise. In the depicted example, ADC118includes a comparator circuit116coupled to receive the image signals from pixel array102through the column bitlines112. In one example, the comparator circuit116may include a plurality of comparators coupled to receive the image signals through the bitlines112. In the example, each of the comparators included in comparator circuit116is also coupled to receive a ramp signal140from a ramp generator114as shown. In the example, each comparator included in comparator circuit116may be used to determine a digital representation of the image signal using a counter based on a comparison of ramp signal140to the image signal voltage level received through bitlines112. As will be discussed in further detail below, in various examples the ramp generator114is a current integration ramp generator. In the various examples, the ramp settling time, or delay, of the ramp signal140that is generated by the ramp generator114and received by the comparator circuit116is reduced with a low power settling assist circuit to increase the maximum frame rate and therefore improve the performance of the imaging system100in accordance with the teachings of the present invention.

In the example, the digital image data values generated by ADC118may then be received by function logic108. Function logic108may simply store the digital image data or even manipulate the digital image data by applying post image effects (e.g., crop, rotate, remove red eye, adjust brightness, adjust contrast, or otherwise).

In one example, control circuit104is coupled to pixel array102to control operation of the plurality of photodiodes in pixel array102. For example, control circuit104may generate a shutter signal for controlling image acquisition. In one example, the shutter signal is a global shutter signal for simultaneously enabling all pixel circuits104within pixel array102to simultaneously capture their respective image data during a single acquisition window. In another example, the shutter signal is a rolling shutter signal such that each row, column, or group of pixels is sequentially enabled during consecutive acquisition windows. In another example, image acquisition is synchronized with lighting effects such as a flash.

In one example, imaging system100may be included in a digital camera, cell phone, laptop computer, or the like. Additionally, imaging system100may be coupled to other pieces of hardware such as a processor (general purpose or otherwise), memory elements, output (USB port, wireless transmitter, HDMI port, etc.), lighting/flash, electrical input (keyboard, touch display, track pad, mouse, microphone, etc.), and/or display. Other pieces of hardware may deliver instructions to imaging system100, extract image data from imaging system100, or manipulate image data supplied by imaging system100.

FIG.2shows a schematic of an example of a current integration ramp generator without a low power ramp settling assist circuit. As shown, the current integration ramp generator includes an operational amplifier224. A first input (e.g., inverting input) of the operational amplifier224is coupled to an integration current source230to receive an integration current IINT232. A second input (e.g., non-inverting input) of the operational amplifier224is coupled to receive a reference voltage VREF234. In the depicted example, a switch and a capacitor236may be coupled to the non-inverting input of operational amplifier224to sample and hold the reference voltage VREF224at the non-inverting input of operational amplifier224. In the depicted example, a feedback capacitor CF226is coupled an output of operational amplifier224and the inverting input of operational amplifier224. A reset switch228is also coupled between the output of operational amplifier224and the inverting input of operational amplifier224. The example depicted inFIG.2shows that an output capacitor COUT238is coupled between the output of operational amplifier224and ground. As will be discussed, the current IC242represents the current that is discharged from the output capacitor COUT238and the current IIN240represents the current that is absorbed by the output of the operational amplifier224due to the discharge of the output capacitor COUT238.

FIG.3is a timing diagram that illustrates signals a non-ideal ramp signal generated by an example current integration ramp generator without a low power ramp settling assist circuit compared to an ideal ramp signal. It is appreciated that the signals illustrated in the timing diagram ofFIG.3may be examples of signals found in the current integration ramp generator depicted inFIG.2, and that similarly named and numbered elements described above are coupled and function similarly below. In particular, the depicted example shows a ramp signal RAMP344, a reset signal RESET328, a ramp voltage signal VRAMP320, an input current IIN340, and a capacitor current IC342.

As shown in the example depicted inFIG.3, the ramp voltage signal VRAMP320is initialized at time T0 before a ramp event to a voltage VCVDN. At time T1, the ramp event begins, which is shown with the ramp signal RAMP344transitioning to a high level (e.g., “1”) and the reset signal RESET328transitioning to a low level (e.g., “0”). In the example, the reset signal RESET328transitioning to the low level (e.g., “0”) turns off the reset switch228shown in the example depicted inFIG.2. As such a ramp event begins in the ramp voltage signal VRAMP320at time T1 with the voltage ramping down as shown. Ideally, the ramp voltage signal VRAMP320should have a sharp corner at time T1 and begin ramping down linearly as indicated with ideal ramp signal384. However, of a current integration ramp generator without a low power ramp settling assist circuit in accordance with the teachings of the present invention has a non-ideal ramp signal386as shown due to discharging of the output capacitor COUT238.

In particular, at time T1 when the ramp event or ramp phase starts in ramp voltage signal VRAMP320, the integration current IINT232goes through the feedback capacitor CF226and the ramp voltage signal VRAMP320starts to ramp down. At this time, the output capacitor COUT238needs to discharge. As a consequence, the output of the operational amplifier224needs to adjust the ramp voltage signal VRAMP320to absorb the input current IIN340, which corresponds to the discharge current IC342of the output capacitor COUT238. In particular, due to the limited bandwidth of the operational amplifier224, the ramp voltage signal VRAMP320and the input current IIN340resettle according to the equations:

VR⁢A⁢M⁢P(t)=VC⁢V⁢D⁢N-IINTtCF+IINT⁢CO⁢U⁢TCF⁢gm⁢(1-egm⁢tCO⁢U⁢T),(1)IN(t)=IC(t)=IINT⁢CO⁢U⁢TCF⁢(1-egm⁢tCO⁢U⁢T),(2)
where gmis the effective transconductance of the operational amplifier224.

FIG.4shows one example of a schematic of a current integration ramp generator with a low power ramp settling assist circuit in accordance with the teachings of the present invention. It is appreciated that the current integration ramp generator with a low power ramp settling assist circuit shown inFIG.4may be an example of the ramp generator114illustrated inFIG.1, and that similarly named and numbered elements described above are coupled and function similarly below.

As shown inFIG.4, the current integration ramp generator includes an operational amplifier424. A first input (e.g., inverting input) of the operational amplifier424is coupled to an integration current source430to receive an integration current IINT432. A second input (e.g., non-inverting input) of the operational amplifier424is coupled to receive a reference voltage VREF434. In the depicted example, a switch and a capacitor436may be coupled to the non-inverting input of operational amplifier424to sample and hold the reference voltage VREF424at the non-inverting input of operational amplifier424. In the depicted example, a feedback capacitor CF426is coupled an output of operational amplifier424and the inverting input of operational amplifier424. A reset switch428is also coupled between the output of operational amplifier424and the inverting input of operational amplifier424. The example depicted inFIG.4shows that an output capacitor COUT438is coupled between the output of operational amplifier424and ground. As shown in the depicted example, an assist current source440is coupled between the output of the operational amplifier424and ground. In the example, a ramp switch444is coupled to the assist current source440such that the ramp switch444and the assist current source440are coupled between the output of the operational amplifier424and ground.

In operation, the assist current source440is configured to conduct an assist current IASSIST446from the output of the operational amplifier424to ground in response to the reset switch428being turned off, which corresponds to a ramp event occurring in the ramp voltage VRAMP420. In the depicted example, the ramp switch444is also turned on during the ramp event occurring in the ramp voltage VRAMP420in order to conduct the assist current IASSIST446from the output of the operational amplifier424to ground during the ramp event. The current IC442represents the current that is discharged from the output capacitor COUT438and the current IIN440represents the current that would be absorbed by the output of the operational amplifier424without the assist current source440due to the discharge of the output capacitor COUT438.

In particular, the assist current IASSIST446is configured to be substantially equal in magnitude to the discharge current IC442of the output capacitor COUT438during the ramp event in the ramp voltage VRAMP420. Therefore, the input current IIN440that would otherwise need to be absorbed by the output of the operational amplifier424remains substantially zero and the operational amplifier424does not need to resettle in accordance with the teachings of the present invention. As such, the ramp voltage VRAMP420is much closer to an ideal ramp signal with substantially no settling time delay and a sharper corner at the beginning of the ramp event in accordance with the teachings of the present invention.

FIG.5is a timing diagram that illustrates signals including a ramp signal generated by an example current integration ramp generator with a low power ramp settling assist circuit in accordance with the teachings of the present invention. It is appreciated that the signals illustrated in the timing diagram ofFIG.5may be examples of signals found in the current integration ramp generator depicted inFIG.4, and that similarly named and numbered elements described above are coupled and function similarly below. In particular, the depicted example shows a ramp signal RAMP544, a reset signal RESET528, a ramp voltage signal VRAMP520, an input current IIN540, a capacitor current IC542, an assist current IASSIST546, and a power line current IAVDD548.

As shown in the example depicted inFIG.5, the ramp voltage signal VRAMP520is initialized at time T0 before a ramp event to a voltage VCVDN. At time T1, the ramp event begins, which is shown with the ramp signal RAMP544transitioning to a high level (e.g., “1”) and the reset signal RESET528transitioning to a low level (e.g., “0”). In the example, the ramp signal RAMP544transitioning to the high level (e.g., “1”) turns on the ramp switch444and the reset signal RESET528transitioning to the low level (e.g., “0”) turns off the reset switch428shown in the example depicted inFIG.4. As such a ramp event begins in the ramp voltage signal VRAMP520at time T1 with the voltage ramping down as shown. As will be discussed, with the assist current IASSIST546being configured to be substantially equal to the capacitor current IC542to discharge the output capacitor COUT438, the ramp voltage signal VRAMP520has a sharp corner at time T1 and begin ramping down linearly with substantially no settling delay as indicated with ideal ramp signal584. It is appreciated that without the assist current source440providing the assist current IASSIST546, a non-ideal ramp signal586would occur due to discharging of the output capacitor COUT438.

In particular, at time T1 when the ramp event or ramp phase starts in ramp voltage signal VRAMP520, the integration current IINT532goes through the feedback capacitor CF526and the ramp voltage signal VRAMP520starts to ramp down. At this time, the output capacitor COUT438needs to discharge with capacitor current IC542. With the assist current source440providing the assist current IASSIST4446, which has a magnitude substantially equal to the capacitor current IC542, the input current IIN540absorbed by the output of the remains substantially zero, which enables the ideal ramp signal584at time T1 as shown. Thus, it is appreciated that the assist current IASSIST546, the input current IIN540, and the ramp voltage signal VRAMP520at time T1 can be represented according to the equations:

IASSIST=IINT⁢CO⁢U⁢TCF,(3)IN(t)=0,(4)VR⁢A⁢M⁢P(t)=VC⁢V⁢D⁢N-IINTtCF.(5)

In operation, it is further appreciated that with the ramp signal RAMP544configured to be off during a non-ramp events (e.g., at time T0) or prior to the ramp event at time T1, extra power consumption due to the assist current546is saved with the ramp switch444being turned off during non-ramp events (e.g., at time T0). Furthermore, as shown inFIG.5, it is also appreciated that the power line current IAVDD548remains substantially constant or unchanged during non-ramp events (e.g., at time T0) and during ramp events (e.g., at time T1) since the assist current source is coupled between the output of the operational amplifier424and ground instead of between the power line (e.g., AVDD) and the output of the operational amplifier424.

The above description of illustrated examples of the invention, including what is described in the Abstract, is not intended to be exhaustive or to limit the invention to the precise forms disclosed. While specific examples of the invention are described herein for illustrative purposes, various modifications are possible within the scope of the invention, as those skilled in the relevant art will recognize.

These modifications can be made to the invention in light of the above detailed description. The terms used in the following claims should not be construed to limit the invention to the specific examples disclosed in the specification. Rather, the scope of the invention is to be determined entirely by the following claims, which are to be construed in accordance with established doctrines of claim interpretation.