Patent ID: 12261136

LIST OF REFERENCE NUMERALS IN THE DRAWINGS

100—Substrate;110—First Source/Drain Region;120—Second Source/Drain Region;200—Gate Conductive Layer;210—Third Conductive Layer;220—Fourth Conductive Layer;230—Fifth Conductive Layer;300—Interlayer Dielectric Layer;310—Shielding Layer;320—Spacer;321—First Spacing Layer;322—Second Spacing Layer;323—Third Spacing Layer;330—Isolation Dielectric Layer;400—Interconnect structure;410—Contact Plug;420—First Contact Pad;500—Second Contact Pad;600—Isolation plug;610—Gap;600a—Trench;700—Conductive Material Layer;700a—Contact Hole;710—First Conductive Layer;720—Second Conductive Layer.

DETAILED DESCRIPTION

As mentioned in the Background section, the fabrication of existing semiconductor structures often suffers from deformation of pattern features for contact pads in interconnects.

In order to overcome this problem, the inventors have found from research that, in practical patterning processes usually employed in the fabrication of interconnects to create pattern features for contact pads, patterning accuracy is often affected by the density of pattern features. When pattern features are arranged too densely, it is often difficult to resolve them from one another and adjacent pattern features tend to be joined together. On the other hand, when pattern features are arranged too sparsely, they tend to be over-resolved, leading to the problems of corrugations or notches. For interconnects, since their contact pads are usually formed alone in big blank areas, during the fabrication of such contact pads, pattern features for them tend to experience deformation, which is detrimental to electrical transmission performance of the resulting interconnects.

In view of this, the present invention proposes semiconductor structures, which less suffer from deformation of pattern features for contact pads of interconnects therein.

Semiconductor structures and methods of fabricating them proposed in the present invention will be described in greater detail below by way of specific embodiments with reference to the accompanying drawings. Advantages and features of the present invention will be more apparent from the following detailed description. Note that the figures are provided in a very simplified form not necessarily drawn to exact scale, and they are only intended to facilitate convenience and clarity in explaining the disclosed embodiments.

FIG.1is a schematic illustration of a semiconductor structure according to an embodiment of the present invention. As illustrated inFIG.1, the semiconductor structure includes:a substrate100, at least one semiconductor device and an interlayer dielectric layer300are formed on the substrate100, the interlayer dielectric layer300covers the semiconductor device;an interconnect structure400, the interconnect structure400including a contact plug410and a first contact pad420, the contact plug410extending through the interlayer dielectric layer300to the semiconductor device and being electrically connected to the semiconductor device, the first contact pad420covering a top of the contact plug410and extending laterally over part of a top surface of the interlayer dielectric layer300; anda second contact pad500formed on the top surface of the interlayer dielectric layer300and spaced laterally apart from the first contact pad420.

In this embodiment, forming the second contact pad500beside the first contact pad420can avoid the first contact pad420from being present in a large bland area, which is favorable to good morphological quality of the resulting first contact pad420. For example, during the formation of the first contact pad420, the second contact pad500beside the first contact pad420can protect the first contact pad420from significant damage from etching processes. As a result, defects in the first contact pad420such as notches or shape irregularities can be avoided.

The first and second contact pads420,500may be fabricated from the same conductive material layers. That is, the first and second contact pads420,500may be made of the same materials. In this embodiment, each of the first and second contact pads420,500may include a first conductive layer710and a second conductive layer720, the second conductive layer720is formed on the first conductive layer710. The first conductive layer710in the first contact pad420may be made of the same material as the first conductive layer710in the second contact pad500, and the second conductive layer720in the first contact pad420may be made of the same material as the second conductive layer720in the second contact pad500. The material of the first conductive layers710may include, for example, titanium nitride, and the material of the second conductive layers720may include, for example, tungsten.

The contact plug410and the first contact pad420in the interconnect structure400may be formed simultaneously of the same materials. That is, in this embodiment, the contact plug410may also include a first conductive layer710and a second conductive layer720, the second conductive layer720is formed on the first conductive layer710. Specifically, the contact plug410may be formed in a contact hole in the interlayer dielectric layer300, with the first conductive layer710in the contact plug410covering an inner surface of the contact hole and the second conductive layer720in the contact plug410filling up the contact hole.

With continued reference toFIG.1, optionally, the first and second contact pads420,500may be spaced from each other by a trench600a, the trench600aextends downward into the interlayer dielectric layer300.

Specifically, in the case of the first and second contact pads420,500being fabricated from the same conductive material layers, in order to ensure that the first and second contact pads420,500are electrically isolated from each other, after the conductive material layers are etched through, a portion of the interlayer dielectric layer300between the first and second contact pads420,500may also be etched away to ensure that the first and second contact pads420,500are separated from each other, resulting in the formation of the trench600a.

In this embodiment, the semiconductor structure may further include an isolation plug600, the isolation plug600fills the trench600aand covers side surfaces of the first and second contact pads420,500exposed in the trench600a.

Additionally, a gap610may be formed in the isolation plug600in the trench600a. In this embodiment, the gap610may extend vertically at the middle of the trench600ain a height-wise direction.

Optionally, a top of the gap610may be located above the top surface of the interlayer dielectric layer300so that a portion of the gap610is situated between the first and second contact pads420,500. That is, the gap610in the isolation plug600may be located between laterally opposing portions of the first and second contact pads420,500. This can reduce the dielectric constant of the dielectric material between the first and second contact pads420,500, thus effectively mitigating parasitic capacitance between the first and second contact pads420,500. In this embodiment, the gap610may vertically extend downward from a top surface of the isolation plug600.

Additionally, the gap610formed in the isolation plug600can relieve internal stress in the isolation plug600, protecting the adjacent contact pads and semiconductor device from possible damage from strong internal stress in the isolation plug600. For example, when a high-temperature process is performed on the semiconductor structure, effective stress relief can be provided by the gap610in the isolation plug600. In this way, the isolation plug600will not squeeze and thus possibly damage other components under strong stress.

In particular, when the isolation plug600is formed right above the semiconductor device, strong internal stress in the isolation plug600may cause damage to the semiconductor device. As shown inFIG.1, in this embodiment, the isolation plug600is formed right above the semiconductor device.

With continued reference toFIG.1, in this embodiment, the semiconductor device may include, for example, at least one transistor. The transistor may include a gate conductive layer200on a top surface of the substrate100and first and second source/drain regions110,120formed in the substrate100, the first and second source/drain regions110,120are formed respectively on opposing sides of the gate conductive layer200.

In this embodiment, the gate conductive layer200may include a third conductive layer210, a fourth conductive layer220and a fifth conductive layer230, which are stacked one on another. The third conductive layer210may be made of a material including, for example, polysilicon. The fourth conductive layer220may be made of a material including, for example, titanium nitride. The fifth conductive layer230may be made of a material including, for example, tungsten.

The interlayer dielectric layer300may include a shielding layer310covering a top surface of the gate conductive layer200. The contact plug410may be located beside the gate conductive layer200and a lower end of the contact plug410may vertically extend downward to the first source/drain region110or second source/drain region120in the substrate100. In this way, electrical connection of the first and second source/drain regions110,120can be accomplished with at least two such contact plugs410. The top of the contact plug410may be higher than that of the gate conductive layer, and the first contact pad420may extend from a side edge of the gate conductive layer200over the shielding layer310. That is, the first contact pad420is located at least partially above the gate conductive layer200.

In this embodiment, the second contact pad500may reside on the shielding layer310and be spaced apart from the first contact pad420. In this embodiment, trench600abetween the first and second contact pads420,500may be formed partially in the shielding layer310, and the isolation plug600may be filled in a corresponding portion of the shielding layer310. That is, there may be an overlap between projections of the isolation plug600and the gate conductive layer200in the height-wise direction.

The distance between the first and second contact pads420,500and the widths of the first and second contact pads420,500may be configured as actually required. Specifically, the distance between the first and second contact pads420,500and the widths of the first and second contact pads420,500may be configured according to the resolution accuracy of the current photolithography and etching processes, as long as the density of pattern features is allowed by the resolution accuracy of the current processes.

For example, the distance between the first and second contact pads420,500may be smaller than a width of the gate conductive layer200. In this way, it can be ensured that the second contact pad500can effectively protect the first contact pad420during the formation of the first contact pad420.

In this embodiment, a width of the first contact pad420over the shielding layer310may be smaller than the width of the second contact pad500. Since the first contact pad420extends from an out edge of the shielding layer310toward a middle of the shielding layer310, and since the second contact pad500is formed above the shielding layer310, the width of the first contact pad420over the shielding layer310smaller than the width of the second contact pad500means that the trench600abetween the first and second contact pads420,500is deviated from the middle of the shielding layer310. In addition, the groove600ais deviated from the middle of the shielding layer310toward the first contact pad420.

With continued reference toFIG.1, the interlayer dielectric layer300may further include a spacer320covering a side surface of the gate conductive layer200. In this embodiment, the spacer320may further cover a side surface of the shielding layer310. Moreover, the contact plug410may be formed on the side of the spacer320away from the gate conductive layer200, and the first contact pad420may extend laterally over the spacer320adjacent to the contact plug410.

Specifically, the spacer320may be, for example, a stacked structure sequentially stacked over the gate conductive layer200. In this embodiment, the spacer320may include a first spacing layer321, a second spacing layer322and a third spacing layer323, which are stacked over the gate conductive layer200sequentially in this order. The first and third spacing layers321,323may be formed of the same material including, for example, silicon oxide, and the second spacing layer322may be formed of a material including, for example, silicon nitride. Therefore, in this case, the spacer320is an ONO structure.

The interlayer dielectric layer300may further include an isolation dielectric layer330external to the gate conductive layer200. In this embodiment, the isolation dielectric layer330may surround the spacer320, and the contact plug410may extend through the isolation dielectric layer330.

In specific embodiments, at least two transistors may be formed on the substrate100. InFIG.1, only two transistors are schematically shown and share the first source/drain region110. In addition, the contact plug410is electrically connected to this shared first source/drain region110and is located between the two transistors. Further, the first contact pad420laterally extends toward both the two transistors and over the gate conductive layers therein.

A method of fabricating a semiconductor structure according to this embodiment will be described in detail below.FIG.2is a flowchart of the method according to an embodiment of the present invention, andFIGS.3ato3fare schematic illustrations of structures formed in the method according to an embodiment of the present invention.

First of all, step S100is performed, in which, with particular reference toFIG.3a, a substrate100is provided, and at least one semiconductor device and an interlayer dielectric layer300covering the semiconductor device are formed on the substrate100.

In this embodiment, the semiconductor device may include a transistor. The transistor may include a gate conductive layer200on a top surface of the substrate100and first and second source/drain regions110,120formed in the substrate100.

The interlayer dielectric layer300may include a shielding layer310covering a top surface of the gate conductive layer200. In this embodiment, the shielding layer310and the gate conductive layer200may be formed in the same photolithography process.

Specifically, the formation of the shielding layer310in the interlayer dielectric layer300and the gate conductive layer200may include the steps of:i) forming a gate material layer and a shielding material layer sequentially over the substrate100;ii) forming the shielding layer310by patterning the shielding material layer using photolithography and etching processes; andiii) forming the gate conductive layer200by etching the gate material layer, with the shielding layer310serving as a mask.

In this embodiment, the gate material layer may consist of a stack of layers, and these layers may be etched through sequentially during the etching process. The resulting gate conductive layer200may be made up of a third conductive layer210, a fourth conductive layer220and a fifth conductive layer230.

Additionally, the formation of the interlayer dielectric layer300may further include forming a spacer320on side surfaces of the gate conductive layer200and the shielding layer310.

With continued reference toFIG.3a, the formation of the interlayer dielectric layer300may further include forming an isolation dielectric layer330external to the gate conductive layer200. In this embodiment, the isolation dielectric layer330may surround the spacer320.

The formation of the isolation dielectric layer330may involve a planarization process. Specifically, after a layer of the isolation dielectric material is deposited, a chemical mechanical polishing process may be performed on the layer, with the shielding layer310serving as a polishing stop layer, so that top surfaces of the resulting isolation dielectric layer330and the shielding layer310are flush with each other.

Step S200is then performed, in which, with particular reference toFIG.3b, a contact hole700ais so formed in the interlayer dielectric layer300as to extend through the interlayer dielectric layer300to the semiconductor device.

In this embodiment, the contact hole700amay extend through the isolation dielectric layer330to the top surface of the substrate100, thus exposing the underlying substrate100.

Step S300is then performed, in which, with particular reference toFIG.3c, a conductive material layer700is formed on the interlayer dielectric layer300so as to fill the contact hole700aand cover the top surface of the interlayer dielectric layer300.

Specifically, the formation of the conductive material layer700may be accomplished by a deposition process and a planarization process. More specifically, the formation of the conductive material layer700may include the steps of:i) depositing a first conductive layer710over the interlayer dielectric layer300, the first conductive layer710covers an inner surface of the contact hole700aand the top surface of the interlayer dielectric layer300with geometric conformity therewith; andii) forming a second conductive layer720on the first conductive layer710, the second conductive layer720fills up the contact hole700aand extends over the top surface of the interlayer dielectric layer300. The second conductive layer720may be planarized, so that the second conductive layer720has a flat top surface.

Step S400is then performed, in which, with particular reference toFIG.3d, an interconnect structure400and a second contact pad500are formed by patterning the conductive material layer700. The interconnect structure400includes a contact plug410in the contact hole and a first contact pad420covering a top of the contact plug410. The second contact pad500is spaced laterally apart from the first contact pad420.

Specifically, the formation of the interconnect structure400and the second contact pad500by patterning the conductive material layer700may include the following steps.

At first, a mask layer (not shown) is formed on the conductive material layer700, the mask layer has a first mask pattern and a second mask pattern. The first mask pattern corresponds to the interconnect structure and the second mask pattern corresponds to the second contact pad. The first mask pattern encompasses the contact hole and an area surrounding the contact hole, and the second mask pattern is located lateral to the first mask pattern and is spaced apart from the first mask pattern by a predetermined distance.

Subsequently, the interconnect structure400corresponding to the first mask pattern and the second contact pad500corresponding to the second mask pattern are formed by etching the conductive material layer700with the mask layer as an etching mask.

In this embodiment, the first contact pad420extends laterally from the contact plug410over the shielding layer310, and the second contact pad500is at least partially formed on the shielding layer310and is spaced from the first contact pad420by the predetermined distance.

Optionally, with particular reference toFIG.3e, subsequent to the etching of the conductive material layer700, the method may further include forming a trench600aby performing an etching process on the interlayer dielectric layer300between the first and second contact pads420,500and stopping the etching process in the interlayer dielectric layer300. In this way, separation of the first and second contact pads420,500from each other can be ensured.

Specifically, the trench600amay be formed by etching the exposed interlayer dielectric layer300with the first and second contact pads420,500serving as etching masks. In this embodiment, the trench600abetween the first and second contact pads420,500may extend downward into the shielding layer310and be located right above the gate conductive layer200. In addition, in this embodiment, another trench may also be formed on the side of the second contact pad500away from the first contact pad420.

With particular reference toFIG.3f, the method may further include filling the trench600awith an isolation plug600. The isolation plug600may cover side surfaces of the first and second contact pads420,500exposed in the trench600a.

In this embodiment, a gap610may be formed in the isolation plug600in order to facilitate stress relief of the isolation plug600. For example, the gap610may extend vertically at the middle of the trench600aalong the height-wise direction.

In summary, in the semiconductor structures according to embodiments of the present invention, the presence of the second contact pad beside the first contact pad in the interconnect structure avoids the first contact pad from being present in a large bland area. In this way, during the fabrication of the interconnect structure, as the first contact pad is not present alone in a large bland area due to the presence of the second contact pad, a pattern feature for the first contact pad will not be over-resolved, increasing formation accuracy of the first contact pad and thus guaranteeing good electrical transmission performance of the resulting interconnect. This can be alternatively interpreted as ensuring good morphological quality of the first contact pad by improving resolution accuracy of the pattern feature for the first contact pad through adjusting a density of pattern features around the area of the first contact pad.

It is to be noted that, while the invention has been described with reference to several preferred embodiments, it is not intended to be limited to these embodiments in any way. In light of the teachings hereinabove, any person of skill in the art may make various possible variations and changes to the disclosed embodiments or modify them into equivalent alternatives, without departing from the scope of the invention. Accordingly, any and all such simple variations, equivalent alternatives and modifications made to the foregoing embodiments without departing from the scope of the invention are intended to fall within the scope thereof.

It is to be noted that, as used herein, the terms “first”, “second” and the like are only meant to distinguish various components, elements, steps, etc. from each other rather than necessarily indicate logical or sequential orderings thereof, unless otherwise indicated or specified.

It is also to be understood that the terminology used herein is used for the purpose of describing particular embodiments only, and is not intended to limit the scope of the present invention. It must be noted that as used herein and in the appended claims, the singular forms “a” and “an” include the plural reference unless the context clearly dictates otherwise. Thus, for example, a reference to “a step” or “a means” is a reference to one or more steps or means and may include sub-steps and subservient means. All conjunctions used are to be understood in the most inclusive sense possible. Thus, the term “or” should be understood as having the definition of a logical “or” rather than that of a logical “exclusive or” unless the context clearly necessitates otherwise. Implementation of the methods and/or device according to the embodiments of the present invention involves performing or completing certain selected tasks or steps manually, automatically, or a combination thereof.