Patent ID: 12199105

DETAIL DESCRIPTION OF EMBODIMENTS

The present disclosure will now be described in detail with reference to the following embodiments. It should be noted that, the following embodiments described herein are only used to illustrate and explain the present disclosure and are not intended to limit the present disclosure.

In order to make the objects, technical solutions and advantages of the embodiments of the present disclosure more apparent, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below with reference to the drawings of the embodiments of the present disclosure. It is to be understood that the described embodiments are only some not all embodiments of the present disclosure. Other embodiments, which can be derived by a person skilled in the art from the described embodiments of the present disclosure without inventive step, are within the scope of protection of the present disclosure.

Unless otherwise defined, technical or scientific terms used in the embodiments of the present disclosure should have the ordinary meaning as understood by one of ordinary skill in the art to which the present disclosure belongs. The use of “first,” “second,” and the like in this disclosure is not intended to indicate any order, quantity, or importance, but rather is used to distinguish one element from another. Similarly, the word “include” or “comprise”, and the like, means that the element or item preceding the word comprises the element or item listed after the word and its equivalent, but does not exclude other elements or items. The terms “connect” or “couple” and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect. “Upper”, “lower”, “left”, “right”, and the like are used only to indicate relative positional relationships, and when the absolute position of the object being described is changed, the relative positional relationships may also be changed accordingly.

With the rapid development of display technologies, Augmented Reality (AR) and Virtual Reality (VR) technologies have attracted wide attention in the market. Liquid crystal display panels may be applied to the AR/VR products. The AR/VR products have high requirements for display panels, such as ultra-high resolution, an ultra-high refresh frequency, and an ultra-fast response. In order to meet the requirement of AR/VR technology for ultra-high resolution of display panels, the support of a high pixel density (i.e., Pixels Per Inch, PPI) technology is required.

The liquid crystal display panel includes a counter substrate and an array substrate which are oppositely arranged, and a liquid crystal layer and spacers between the counter substrate and the array substrate. The spacers support the display panel after the array substrate and the counter substrate are aligned and assembled with each other to form a cell.FIG.1is a schematic plan view of an array substrate and spacers. As shown inFIG.1, the array substrate includes a first base substrate (not shown), and a plurality of gate lines12extending along a first direction and a plurality of data lines13extending along a second direction, which are disposed on the first base substrate. The plurality of gate lines12and the plurality of data lines13intersect with each other to define a plurality of pixel regions a, and each of the pixel regions a is provided with structures such as a thin film transistor6and a pixel electrode. At least a portion of the spacer3is located in the pixel region a. The firsdest direction intersects the second direction, for example, the first direction is perpendicular to the second direction. The counter substrate (not shown) may include a second base substrate and a black matrix disposed on the second base substrate. An orthographic projection of the black matrix on the first base substrate overlaps orthographic projections of the gate line, the data line, the thin film transistor, and the spacer3on the first base substrate. The black matrix may prevent crosstalk from occurring between various pixel regions and prevent the spacers from adversely affecting the display effect.

When the PPI of the display panel is increased, each of the pixel regions a is correspondingly decreased. In order to ensure the supporting effect of the spacer3, an area of the orthographic projection of the spacer3on the array substrate cannot be decreased, so that a ratio of the area of the spacer3and the black matrix corresponding to a pixel region to the area of the pixel region is increased. During the display process of the display panel, the pixel region facing the spacer3is shielded by the black matrix corresponding to the spacer3, so that the brightness of the pixel region is decreased, and the phenomenon of poor display of the display panel occurs.

In order to solve at least one of the above technical problems, an embodiment of the present disclosure provides a display panel including an array substrate, a counter substrate, and spacers located between the array substrate and the counter substrate.FIG.2is a schematic plan view of an array substrate and spacers according to an embodiment of the present disclosure, andFIG.3is a schematic cross-sectional view of a display panel according to an embodiment of the present disclosure. As shown inFIG.2andFIG.3, the array substrate1includes a first base substrate11and a plurality of signal lines4located on the first base substrate11. The plurality of signal lines4includes a plurality of first signal lines41and a plurality of second signal lines42. The plurality of signal lines41are arranged in parallel along a second direction, and the plurality of second signal lines42are arranged in parallel along a first direction. The plurality of first signal lines41and the plurality of second signal lines42intersect with each other to define a plurality of first regions A. The plurality of first regions A include a plurality of first pixel regions A1, at least one second pixel region A2, and at least one redundant region A3. Each of the first pixel region A1and the second pixel region A2is provided with a pixel electrode5and a thin film transistor6, so as to realize display through the driving of a driving signal. No pixel electrode or no thin film transistor is formed in the redundant region A3, therefore the redundant region A3does not have a display function.

Each of the first signal lines41extends along the first direction, and each of the second signal lines42includes a body portion4aextending along the second direction, the first direction intersecting with the second direction, for example, the first direction being perpendicular to the second direction. In addition to the body portion4a, at least one second signal line42includes a bending portion4bconnected to the body portion4a. In some embodiments, some second signal lines42include the body portions4aand the bending portions4b, and the remaining second signal lines42include only the body portions4a.

The first pixel region A1is adjacent to the body portion4aof the at least one second signal line42. The second pixel region A2and the redundant region A3are both adjacent to the bending portion4band located on two sides of the bending portion4balong the first direction, respectively, and the bending portion4bprotrudes toward the redundant region A3. A size of the area of the orthographic projection of the first pixel region A1on the first base substrate11is larger than a size of the area of the orthographic projection of the redundant region A3on the first base substrate11, and a size of the area of the orthographic projection of the second pixel region A2on the first base substrate11is larger than a size of the area of the orthographic projection of the first pixel region A1on the first base substrate11. An orthographic projection of the spacer3on the first base substrate11at least partially overlaps an orthographic projection of the redundant region A3on the first base substrate11.

In addition, as shown inFIG.2, the pixel electrode5may include a connection portion5a, and the pixel electrode5is connected to the thin film transistor6located in the same first region A through the connection portion5a.

Since no pixel electrode5or no thin film transistor6is formed in the redundant region A3, the spacer3disposed in the redundant region A3does not affect the display effect of the display panel. Meanwhile, the area of the second pixel region A2is increased, so that the loss of brightness in the redundant region A3caused by the loss of the pixel structure can be compensated, and the brightness of the display panel is prevented from being reduced.

In some embodiments, the counter substrate2includes a second base substrate21and a black matrix22on a side of the second base substrate21proximal to the array substrate1. An orthographic projection of the black matrix22on the first base substrate11overlaps the orthographic projections of the first signal line41, the second signal line42and the spacer3on the first base substrate11. The spacer3is located on a side of the black matrix22away from the second base substrate21. Since the spacer3is disposed in the redundant region A3, the display effect of the display panel cannot be affected by the spacer3. A portion of the black matrix opposite to the spacer3does not shield the pixel region, so that the display effect of the display panel cannot be affected.

In some embodiments, one of the first signal line41and the second signal line42is a data line, and the other is a gate line. For example, as shown inFIG.2, the first signal line41is a gate line extending in the first direction, and the second signal line42is a data line.

In some embodiments, as shown inFIG.2, a ratio of an area of the orthographic projection of the second pixel region A2on the first base substrate11to an area of the orthographic projection of the first pixel region A1on the first base substrate11ranges from 1.25 to 1.75. For example, a ratio of the area of the orthographic projection of the second pixel region A2on the first base substrate11to the area of the orthographic projection of the first pixel region A1on the first base substrate11is 1.25, or 1.3, or 1.5, or 1.7, or 1.75.

In an example, as shown inFIG.2, the first signal line41is a gate line, the second signal line42is a data line. Three gate lines each extending along the first direction and four data lines are disposed in the region shown inFIG.2. The four data lines include two first data lines and two second data lines. The two first data lines are adjacent to each other, and each of the two first data lines includes a body portion extending along the second direction and a bending portion connected to the body portion. Each of the second data lines extends along the second direction. The three gate lines and the four data lines intersect each other to form nine first regions. A region between the bending portions of the two first data lines is the redundant region A3; a region between the bending portion of the first data line and the second data line is the second pixel region A2; and a region defined by the intersection of a gate line, the body portion of the first data line, another gate line, and the body portion of the second data line is the first pixel region A1. When the area of the second pixel region A2is 1.5 times the area of the first pixel region A1and the second pixel region A2receives the same backlight illumination as the first pixel region A1, the light flux passed through the second pixel region A2is also 1.5 times the light flux passed through the first pixel region A1, and then the sum of the light fluxes for the two second pixel regions A2and the redundant region A3located on one side of the first signal line41is equal to the sum of the light fluxes for the three first pixel regions A1located on the other side of the first signal line41. Therefore, by enlarging the area of the second pixel region A2located at the two sides of the redundant region A3, the loss of brightness in the redundant region A3caused by the pixel missing can be compensated, and the phenomenon of poor display of the display panel can be avoided.

In some embodiments, as shown inFIG.3, the array substrate1includes a plurality of pixel electrodes5and a plurality of thin film transistors6. Each of the first pixel region A1and the second pixel region A2is provided with the pixel electrode5and the thin film transistor6. The thin film transistor6includes a gate electrode61, an active layer62, a first electrode64, and a second electrode63. The active layer62is disposed on a side of the gate electrode61away from the first base substrate11, and a gate insulating layer GI is disposed between the gate electrode61and the active layer62. The first electrode64and the second electrode63are respectively disposed at two ends of the active layer62. In addition, one of the first electrode64and the second electrode63is a source electrode, and the other is a drain electrode. It should be noted that the thin film transistor inFIG.3is a bottom-gate thin film transistor as an example, but the thin film transistor can alternatively be a top-gate thin film transistor.

The pixel electrode5is located on a side of the thin film transistor6away from the first base substrate11and is connected to the first electrode64of the thin film transistor6. One of the gate electrode61and the second electrode63of the thin film transistor6is connected to the first signal line41, and the other of the gate electrode61and the second electrode63of the thin film transistor6is connected to the second signal line42. The orthographic projection of the redundant region A3on the first base substrate11does not overlap the orthographic projection of the pixel electrode5on the first base substrate11, that is, no pixel electrode is disposed in the redundant region A3, so that the redundant region has no display function.

In some embodiments, as shown inFIG.3, the array substrate1further includes a common electrode7. When a voltage difference is generated between the common electrode7and the pixel electrode5, an electric field is generated therebetween, so as to drive liquid crystals in a region (i.e., a first pixel region or a second pixel region) where the pixel electrode is located to deflect, thereby achieving a display effect.

As shown inFIG.3, the common electrode7is located on a side of the pixel electrode5proximal to the thin film transistor6. The common electrode7includes a first hollow portion B1, and the pixel electrode5is connected to the first electrode of the thin film transistor6through the first hollow portion B1of the common electrode7. The pixel electrode5includes a second hollow portion B2, and an orthographic projection of the second hollow portion B2on the first base substrate11overlaps an orthographic projection of the common electrode7on the first base substrate11. When an electric field is generated between the common electrode7and the pixel electrode5, the electric field passes through the second hollow portion B2of the pixel electrode5to drive the liquid crystals to deflect.

The embodiment of the present disclosure does not limit the number and the shape of the second hollow portion B2of the pixel electrode5. For example, the second hollow portion B2may have a rectangular shape, a circular shape, an irregular shape, or the like. For another example, the pixel electrode in each of the first pixel regions A1includes one second hollow portion B2, and the pixel electrode in each of the second pixel regions A2includes two second hollow portions B2.

In an example, the pixel electrode5may not include the hollow portion. An electric field formed between the common electrode7and the pixel electrode5may pass through a spacing region between the pixel electrodes5to drive the liquid crystals to deflect, thereby achieving the display effect.

FIG.4is a schematic cross-sectional view of a display panel according to another embodiment of the present disclosure. In other embodiments, as shown inFIG.4, the array substrate1also includes the common electrode7, the embodiment inFIG.4is different from that inFIG.3in that the common electrode7is located on a side of the pixel electrode5away from the thin film transistor6. The common electrode7includes a third hollow portion B3, and an orthographic projection of each of the pixel electrodes5on the first base substrate11overlaps an orthographic projection of the third hollow portion B3on the first base substrate11. When an electric field is generated between the common electrode7and the pixel electrode5, the electric field passes through the third hollow portion B3of the common electrode7to drive the liquid crystals to deflect, so that the display effect can be realized.

The number and shape of the third hollow portions B3and the correspondence relationship between the pixel electrode and the third hollow portion B3are not limited in the embodiments of the present disclosure. For example, the shape of the third hollow portion B3may have a rectangle shape, a circle shape, an irregular shape, or the like. For example, each of the pixel electrodes is opposite to one third hollow portion B3. For another example, each of the pixel electrodes is opposite to a plurality of third hollow portions B3. For yet another example, multiple pixel electrodes are opposite to a same third hollow portion B3.

As shown inFIG.3andFIG.4, the pixel electrode5and the common electrode7in the array substrate1may be positioned flexibly. That is, the pixel electrode5and the common electrode7is formed in sequence in this order on a side of the thin film transistor6away from the first base substrate11, or the common electrode7and the pixel electrode5is formed in sequence in this order on a side of the thin film transistor6away from the first base substrate11. Alternatively, the common electrode7may be formed on the counter substrate as long as the common electrode7may cooperate with the pixel electrode to drive the liquid crystals to deflect.

In some embodiments, as shown inFIG.3andFIG.4, the thin film transistor6includes a first thin film transistor and a second thin film transistor. The first thin film transistor is located in the first pixel region A1, and the second thin film transistor is located in the second pixel region A2. A width-to-length ratio of a channel of the second thin film transistor is larger than a width-to-length ratio of a channel of the first thin film transistor.

When the pixel region is increased, the area of the pixel electrode5is increased, and a capacitance value of the capacitor formed between the pixel electrode5and the common electrode7is increased, which results in slow charging. In order to make the charging efficiency of the first pixel region A1consistent with the charging efficiency of the second pixel region A2, the width-to-length ratio of the channel of the second thin film transistor in the second pixel region A2is set to be larger, thereby compensating for the reduced charging rate due to the increase of the capacitance value.

In some embodiments, the width-to-length ratio of the channel of the second thin film transistor ranges from 1.8 to 2.2. For example, when the channel of the second thin film transistor has a width of 10 μm and a length of 5 μm, the width-to-length ratio of the channel of the second thin film transistor is 2.

It should be noted that the width-to-length ratio of the channel of the thin film transistor6in the embodiment of the present disclosure refers to a width-to-length ratio of a channel portion located in the active layer62of the thin film transistor6. When a voltage signal applied to the gate electrode61of the thin film transistor6reaches a predetermined value, a carrier path is formed in the channel portion, so that the second electrode63of the thin film transistor6gets through/electrically connected to the first electrode64thereof. The length direction of the channel portion reflects a probability of the carriers being trapped by a gap state in an interface during the migration process. The longer the channel is, the higher the probability of the carriers being captured is. The width direction of the channel portion reflects the probability that the carrier is not captured by the gap state in the interface during the migration process. The wider the channel is, the higher the probability that the carrier is not captured is. Therefore, the higher the width-to-length ratio of the channel is, the easier the carriers drift, and the lower the threshold voltage is.

FIG.5is a simulation circuit diagram according to an embodiment of the present disclosure. In some embodiments, as shown inFIG.5, electrical signals on the first signal line41and the second signal line42are respectively simulated through voltage pulse signals. The first signal line41is a data line and the second signal line42is a gate line, that is, a data signal on the data line and a scan signal on the gate line are simulated. The first voltage terminal V1is connected to the second electrode63of the thin film transistor, and the signal provided by the first voltage terminal V1is equivalent to the data signal on the data line. The signal provided by the second voltage terminal V2is equivalent to the scan signal on the gate line, and the second voltage terminal V2is connected to the gate electrode61of the thin film transistor. The first electrode64of the thin film transistor is connected to the storage capacitor C1, and the storage capacitor C1is equivalent to the capacitor formed by the pixel electrode and the common electrode. When the signal provided by the second voltage terminal V2is at an active voltage level, the thin film transistor6is turned on, and the voltage signal provided by the first voltage terminal V1is transmitted to the pixel electrode5through the thin film transistor, thereby charging the storage capacitor C1. In the present disclosure, the thin film transistor is an N-type thin film transistor for example, and in this case the active voltage level is a high level. Alternatively, the thin film transistor may be a P-type thin film transistor, and in this case the active voltage level is a low level.

FIG.6Ais a timing diagram of a simulation circuit diagram when the width-to-length ratio of the channel of the thin film transistor is 1 and the capacitance value of the storage capacitor is 1 pF. As shown inFIG.6A, when the width of the thin film transistor6is 5 μm, the length of the thin film transistor is 5 μm (i.e. the width-to-length ratio of the channel of the thin film transistor is 1), and the capacitance value of the storage capacitor C1is 1 pF, if the signal from the first voltage terminal V1has a high level, the thin film transistor6is turned on, so that the storage capacitor C1starts to be charged, and the voltage rise time of the storage capacitor C1(i.e., a time required for the voltage across the storage capacitor C1to rise to a fixed value) is approximately 1.5 μs.FIG.6Bis a timing diagram of an emulation circuit diagram when the width-to-length ratio of the channel of the thin film transistor is 2 and the capacitance value of the storage capacitor is 1.5 pF. As shown inFIG.6B, when the width of the thin film transistor6is 10 μm, the length of the thin film transistor6is 5 μm (i.e. the width-to-length ratio of the channel of the thin film transistor is 2), and the capacitance value of the storage capacitor C1is 1.5 pF, if the signal from the first voltage terminal V1has at a high level, the thin film transistor6is turned on, so that the storage capacitor C1starts to be charged, and the voltage rise time of the storage capacitor C1is approximately 1.5 μs.

In some embodiments, the width-to-length ratio of the channel of the first thin film transistor ranges from 0.8 to 1.2, and the ratio of the width-to-length ratio of the channel of the second thin film transistor to the width-to-length ratio of the channel of the first thin film transistor ranges from 1.5 to 2.75, so as to ensure that the luminous brightness of the first pixel area A1is consistent with that of the second pixel area A2.

In an embodiment of the present disclosure, when a ratio of the area of the second pixel region A2to the area of the first pixel region A1is 1.5 (in this case, a ratio of the capacitance value of the storage capacitor in the second pixel region A2to the capacitance value of the storage capacitor in the first pixel region A1is about 1.5), the width-to-length ratio of the channel of the second thin film transistor in the second pixel region A2is set to 1.5, and the width-to-length ratio of the channel of the first thin film transistor in the first pixel region A1is set to 1, so that the voltage rise time used for charging the storage capacitor in the first pixel region A1is consistent with the voltage rise time used for charging the storage capacitor in the second pixel region A2, thereby ensuring the luminance balance between two pixel regions with different sizes, and improving the display uniformity of the display panel.

In some embodiments, the display panel includes a plurality of pairs of bending portions4b. As shown inFIG.2, two bending portions4bin a same pair of bending portions are respectively located in two adjacent second signal lines42. A target redundant region is between the two bending portions4bin the same pair of bending portions, and each of the two bending portions4bin the same pair of bending portions protrudes toward the target redundant region.

It should be noted that a pair of bending portions4brefers to two bending portions4bprotruding along opposite directions and located on two sides of the same redundant region A3, respectively.

FIG.7Ais a schematic plan view of an array substrate and spacers according to another embodiment of the present disclosure. The array substrate and spacers shown inFIG.7Ahave a similar structures to those inFIG.2, that is, the array substrate also have a first pixel region A1, a second pixel region A2and a redundant region A3, and an orthographic projection of the spacer3on the first base substrate11at least partially overlaps an orthographic projection of the redundant region A3on the first base substrate11, the array substrate and spacers shown inFIG.7Aare different from that inFIG.2in that the first signal line41extending along the first direction is the data line; the second signal line42is a gate line and includes a body portion4aextending along the second direction, and at least one gate line further includes a bending portion4bconnected to the body portion4a. The second pixel region A2and the redundant region A3are located at two sides of the bending portion4b, respectively, and the bending portion4bprotrudes toward the redundant region A3.

In some embodiments, as shown inFIG.2andFIG.7A, each of the first pixel regions A1in the display panel is a rectangular region, and a length of a short side of the rectangular region ranges from 4.2 μm to 17 μm.

It should be noted that the structures of the signal line4having the bending portion4band the redundant region A3in the embodiments of the present disclosure are particularly suitable for display panels with a high PPI, wherein the display panels with a high PPI may refer to the display panels having a PPI greater than 500. As shown inFIG.2andFIG.7A, the first pixel region A1is a rectangular region having a long side extending in the row direction and a short side extending in the column direction. In an example, the PPI of the display panel is 500, and in this case, the length l of the short side of the first pixel region A1is about 17 μm. When the PPI of the display panel is 1000, the length l of the short side of the first pixel region A1is about 5.6 μm. When the PPI of the display panel is 2000, the length l of the short side of the first pixel region A1is about 4.2 μm. The length l of the short side of the first pixel region A1in the above example may alternatively have other sizes, which is not limited in the embodiment of the present disclosure.

In the embodiment of the present disclosure, no matter how the PPI of the display panel is set, as long as it is ensured that the orthographic projection of the spacer3on the first base substrate11does not overlap the orthographic projections of each of the first pixel region A1and the second pixel region A2on the first base substrate11, the spacer3may be prevented from affecting the aperture ratio of the display panel, and the positional relationship between the spacer3and the bending portion4bis not particularly limited by the present disclosure. For example, the orthographic projection of the spacer3on the first base substrate11may partially overlap the orthographic projection of the bending portion4bon the first base substrate11, or the orthographic projection of the spacer3on the first base substrate11may not overlap at all the orthographic projection of the bending portion4bon the first base substrate11. In an example, as shown inFIG.2andFIG.7A, the orthographic projection of the spacer3on the first base substrate11at least partially overlaps the orthographic projection of the bending portion4bon the first base substrate11, so that an area of an orthographic projection of the spacer3on the first base substrate11can be increased, and the supporting capability of the spacer3can be further improved.

In some embodiments, the display panel includes a plurality of second pixel regions A2and the plurality of second pixel regions A2have the same area, thereby facilitating calculation of a driving signal for each of the second pixel regions A2according to image information during displaying of an image.

When the display panel includes the plurality of second pixel regions A2, the channels of the plurality of second thin film transistors may have the same width-to-length ratio, and the plurality of second thin film transistors may be in one-to-one correspondence to the plurality of second pixel regions A2.

In some embodiments, as shown inFIG.2andFIG.7A, two bending portions4bin the same pair of bending portions have mirror symmetry about a symmetry axis P extending in the second direction, so as to facilitate manufacturing of the display panel.

In some embodiments, as shown inFIG.2, the first pixel electrode51and the second pixel electrode52have different shapes from each other, and the first pixel electrode51and the second pixel electrode52are the pixel electrodes in the second pixel regions A2adjacent to the two bending portions4bin the same pair of bending portions, respectively.

Specifically, inFIG.2, the second data line42extending along the second direction is on the left side of the first pixel electrode51, and the bending portion4bis on the right side of the first pixel electrode51. The first pixel electrode51has a main body portion and a connection portion connected to the thin film transistor, and the position where the connection portion is connected to the main body portion is in the middle of the main body portion. The bending portion4bis on the left side of the second pixel electrode52, and the second data line42extending in the second direction is on the right side of the second pixel electrode52. The second pixel electrode52has a main body portion and a connection portion connected to the thin film transistor, and the position where the connection portion is connected to the main body portion is proximal to the second data line42on the right side of the second pixel electrode52. That is, the position of the connection portion of the first pixel electrode51is different from the position of the connection portion of the second pixel electrode52, resulting in different shapes of the first pixel electrode51and the second pixel electrode52.

In addition, the shapes of the first pixel electrode51and second pixel electrode52may be different from the shape of the pixel electrode5in the first pixel region A1. For example, the pixel electrode5in the first pixel region A1similarly has a main body portion and a connection portion, but the area of the main body portion of the pixel electrode5in the first pixel region A1may be smaller than the area of the main body portion of the second pixel electrode51and also smaller than the area of the main body portion of the second pixel electrode52.

FIG.7Bis a schematic plan view of an array substrate and spacers according to another embodiment of the present disclosure. In some embodiments, as shown inFIG.7B, the display panel includes a plurality of bending portions4B, each of the bending portions4B is located between two adjacent second signal lines extending along the second direction, and the bending portion4B protrudes toward the redundant region.

That is, one first pixel region A1and one second pixel region A2may be respectively disposed on two sides of the redundant region A3of the display panel, so that the redundant region is located between the first pixel region A1and the second pixel region A2, as shown inFIG.7B. The second pixel region A2in the display panel may be made large enough to compensate for the luminance loss in the redundant region A3due to the missing pixel structure, and to prevent the luminance of the display panel from being reduced.

An embodiment of the present disclosure further provides a display device, which includes the above display panel, and the display panel is a liquid crystal display panel, and the display device further includes a backlight module and a driving circuit.

The display device may display through a field sequential method. Specifically, the backlight module is configured to provide light in a plurality of primary colors, such as red, green and blue, for the display panel during each display period of the display device. The driving circuit is configured to provide driving signals to the display regions according to image information of sub-images in corresponding primary colors of the target image during sub-phases SP1-SP3of the display period DP. In an example, each image to be displayed Im can be regarded as superposition of a red sub-image, a green sub-image and a blue sub-image, and when the image is displayed, firstly image information of the red sub- image, image information of the green sub-image and image information of the blue sub- image are determined according to the image information of the image to be displayed; and then, during the first sub-phase SP1of the display period DP, the backlight module provides red light R, and meanwhile the driving circuit provides driving signals for the pixel regions according to the image information of the red sub-image; during the second sub-phase SP2, the backlight module provides green light G, and meanwhile the driving circuit provides driving signals for the pixel regions according to the image information of the green sub-image; and during the third sub-phase SP3, the backlight module provides blue light B, and the driving circuit provides driving signals for the pixel regions according to the image information of the blue sub-image.

The liquid crystal display panel of the display device in the embodiment of the present disclosure adopts the field sequential method to display. Color display can be realized by using field sequential backlight, so that color film layers are not required to be provided on the counter substrate, thereby improving the light transmissivity of display screen, and reducing the power consumption of field sequential display module assembly, as a result the field sequential display module assembly can better meet the needs of various applications.

In addition, when the display panel of the display device adopts the structure of the array substrate and the spacers shown inFIG.1and the counter substrate2is provided with the color film layers, if the spacers3are formed at the positions corresponding to the blue pixel regions, since the absolute luminance of blue is lower than those of red and green, the effect of the spacers3on the luminance of the blue pixel regions is small. If the structure of the array substrate and the spacers shown inFIG.1is adopted and the field sequential driving mode is adopted, no matter which pixel region the spacers3are formed in, the display effect is negatively affected obviously. However, the display device in the embodiment of the present disclosure adopts the display panel shown inFIGS.2to4andFIG.7AandFIG.7B, which can reduce the phenomenon of poor display regardless of whether the field sequential driving mode is used

FIG.8is a schematic diagram showing a sub-image and a distribution of regions in a display panel in an embodiment of the present disclosure.FIG.9is a schematic view showing a sub-image and a distribution of regions in a display panel in another embodiment of the present disclosure. In some embodiments, as shown inFIG.8andFIG.9, the display panel includes at least one to-be-adjusted region C, each of the to-be-adjusted region C is located between the body portions of the two second signal lines42and includes n second pixel regions A2and m first pixel regions A1, wherein the m first pixel regions A1are located on a side of the n second pixel regions A2along the second direction. The to-be-adjusted region C is defined by the body portions of the two second signal lines42and the two first signal lines41.

For example, if a region formed by two second pixel regions A2adjacent to the same pair of bending portions4band a redundant region between the two second pixel regions A2is referred to as a pixel region set, the to-be-adjusted region C may include one second pixel region set and the smallest region including multiple first pixel regions which are located on a side of the second pixel region set in the second direction and adjacent to the second pixel region set. The display panel may include multiple pairs of bending portions, and correspondingly the display panel may include multiple to-be-adjusted regions.

Each sub-image of the image to be displayed includes a plurality of image pixels, and each first pixel region in the display panel corresponds to a corresponding one of the image pixels, so that when the driving signal is provided for the display panel, the driving signal can be provided to the first pixel region according to the gray scale of the image pixel corresponding to the first pixel region. For the second pixel region, the driving circuit may provide the driving signal to the second pixel region according to the image information of the portion of the sub-image corresponding to the to-be-adjusted region C. Specifically, the following two driving methods will be illustrated.

According to the first method, as shown inFIG.8, a portion of the sub-image Im1corresponding to to-be-adjusted region C displays a picture with uniform gray scales. In this case, the driving signals provided by the driving circuit for each of the first pixel region and the second pixel region in to-be-adjusted region C satisfy that after the first and second pixel regions emit light, the sum of the luminous fluxes of the n second pixel regions A2is substantially equal to the sum of the luminous fluxes of the m first pixel regions A1. The term “substantially equal to” means that the difference between the two values is not more than 5%, 10% or 15%. Alternatively, the two values may be completely equal to each other.

In an example, as shown inFIG.8, the to-be-adjusted region C includes two second pixel regions A2, the redundant region A3between the two second pixel regions A2, and three first pixel regions A1on a side of the two second pixel regions A2in the second direction, wherein a ratio of an area of the second pixel region A2to an area of the first pixel region A1is 1.5. The portion of the sub-image Im1corresponding to the to-be-adjusted region C displays a picture with uniform gray scales and includes image pixels arranged in two rows and three columns. The three image pixels in the first row are in one-to-one correspondence to the three first pixel regions A1in the to-be-adjusted region C. Assuming that the driving signals, determined according to the three image pixels in the first row, for the three first pixel regions A1in the to-be-adjusted region C each are v1and the luminous fluxes of the three first pixel regions A1after being driven each are 200 cd, the driving signals for the two second pixel regions A2in the to-be-adjusted region C may be determined according to the driving signals v1, so that the luminous fluxes of the two second pixel regions A2each are 300 cd. In this case, the sum of the luminous fluxes of the two second pixel regions A2is 600 cd, and the sum of the luminous fluxes of the three first pixel regions A1is 600 cd too, therefore the two second pixel regions A2can compensate for the luminance loss of the redundant region A3located between the two second pixel regions A2, so that no significant shading change occurs in the display panel.

The above-mentioned luminous flux can be calculated according to formula 1:
Φ=gray·S(1)

Where Φ represents luminous flux in cd, gray represents gray-scale luminance in nit, and s represents an area in m2.

It should be noted that the portion of the sub-image Im1corresponding to the to-be-adjusted region C displaying a picture with uniform gray scales means that the image pixels of the sub-pixel Im1corresponding to the to-be-adjusted region C have similar gray scales, for example, the difference between the gray scales is less than 5, 10 or 15.

According to the second method, as shown inFIG.9, the portion of the sub-image Im2corresponding to the to-be-adjusted region C displays a picture with a gray scale jump (gray scales of adjacent pixels changing significantly), and one of the second pixel regions A2is located at a boundary of the abrupt gray scales (i.e., a line between adjacent pixels with gray scales changing significantly). In this case, the driving signals provided by the driving circuit for each of the first pixel region and the second pixel region in the to-be-adjusted region C satisfy that after the first pixel region A1and second pixel region A2emit light, the target luminance of the first target pixel region is the product of the target luminance of the second pixel region located on the boundary and a first ratio, so that the luminous flux of the second pixel region A2located on the boundary is equal to the luminous flux of the first target pixel region, thereby preventing a difference of luminance from occurring between two sides of the boundary. The first target pixel region is one of the first pixel regions A1in the to-be-adjusted region C. The two second signal lines42adjacent to the first target pixel region are the same as the two second signal lines42adjacent to the second pixel region A2on the boundary of the gray scale jump. The first ratio is a ratio of an area of the second pixel region A2to an area of the first pixel region A1.

In an example, as shown inFIG.9, the ratio of the area of the second pixel region A2to the area of the first target pixel region A1is 1.5. The portion of the sub-image Im2corresponding to the to-be-adjusted region C displays a picture with a gray scale jump. It is assumed that the driving signal for the first target pixel region A1is v3, the luminous flux of the first target pixel region A1after being driven is 200 cd, the driving signal for the second pixel region A2is v4, and the luminous flux of the second pixel region A2after being driven is 200 cd, which is equal to the luminous flux of the first target pixel region A1after being driven. According to above equation 1, a ratio of the target luminance of the first pixel region A1to the target luminance of the second pixel region A2is 1.5, which is equal to a ratio of the area of the second pixel region A2to the area of the first pixel region A1. For example, the target luminance for the first pixel region A1is 200 nit, and the target luminance for the second pixel region A2is 133 nit. Although the area of the second pixel region A2is larger than the area of the first pixel region A1, the target luminance of the second pixel region A2is lower than the target luminance of the first pixel region A1, therefore the luminous flux of the second pixel region A2is substantially equal to the luminous flux of the first pixel region A1, and thus no obvious visual defect is caused to the whole display of the display panel.

It should be noted that, the portion of the sub-image Im2corresponding to the to-be-adjusted region C displaying a picture with the gray scale jump means that a boundary exists in the portion of the sub-image Im2corresponding to the to-be-adjusted region C, and the difference between the gray scales of the image pixels on two sides of the boundary is large, for example, larger than 100, 150 or 200. For example, as shown inFIG.9, the to-be-adjusted region C includes image pixels in two rows and three columns. Assuming that the image pixels in the first column on the left have a gray scale of 255 and the image pixels in the remaining two columns have a gray scale of 0, there is a boundary, on which the gray scales changes significantly, between the image pixels in the first column on the left and the image pixels in the middle column, and the second pixel region A2on the left in the to-be-adjusted region is located on the above-mentioned boundary.

It should be noted that, when the display panel employs the structure as shown inFIG.7B, a region including the redundant region and the first pixel region A1and the second pixel region A2respectively located at two sides of the redundant region can be referred to as a pixel region set. The to-be-adjusted region C may include above pixel region set and the smallest region including multiple first pixel regions which are on a side of the pixel region set along the second direction and adjacent to the pixel region set. The display panel may include multiple pairs of bending portions, and correspondingly the display panel may include multiple to-be-adjusted regions. That is, the display panel employing the structure shown inFIG.7Bis also suitable for the above driving method of the driving circuit, so as to provide the driving signal for the second pixel region, thereby reducing the phenomenon of poor display.

An embodiment of the present disclosure further provides a method for manufacturing the array substrate1inFIG.3.FIG.10AtoFIG.10Eare schematic diagrams showing steps of the method for manufacturing the array substrate1. As shown inFIG.3andFIG.10AtoFIG.10E, the method includes steps S11to S15.

At step S11, as shown inFIG.10A, a first base substrate11is provided; and a gate electrode61of the thin film transistor6, a gate insulating layer GI, an active layer62of the thin film transistor6, a second electrode63and a first electrode64of the thin film transistor6, and a passivation layer PVX are sequentially formed on the first base substrate11. The second electrode63and the first electrode64of the thin film transistor6are each connected to the active layer62, and a first via hole c1exposing the first electrode64is formed in the passivation layer PVX.

The material of the gate insulating layer GI includes any one of silicon oxynitride, silicon oxide, silicon nitride, silicon oxycarbide, silicon carbonitride, aluminum oxide, aluminum nitride, tantalum oxide, hafnium oxide, zirconium oxide, titanium oxide, and the like. The material of the gate electrode61includes any one of, metal, metal alloy, metal nitride, conductive metal oxide, transparent conductive material, and the like for example. In addition, each of the gate insulating layer GI and the gate electrode61may be a single layer or a multilayer.

At step S12, as shown inFIG.10B, a planarization layer PLN is formed on the passivation layer PVX, and a second via hole c2exposing the first electrode64is formed in the planarization layer PLN. The planarization layer PLN may be made of an organic insulating material, for example resin materials such as polyimide, epoxy, acryl, polyester, photoresist, polyacrylate, polyamide, and siloxane.

At step S13, as shown inFIG.10C, the common electrode7is formed on the planarization layer PLN, and the common electrode7has a first hollow portion B1exposing the first electrode64.

At step S14, as shown inFIG.10D, an insulating layer8is formed on the common electrode7, and a third via hole c3exposing the first electrode64is formed in the insulating layer8.

At step S15, as shown inFIG.10E, the pixel electrode5is formed on the insulating layer8, and the pixel electrode5is connected to the first electrode64of the thin film transistor6through the via hole (i.e., the combination of the first via hole c1, the second via hole c2, and the third via hole c3) penetrating the insulating layer8, the common electrode7, the planarization layer PLN, and the passivation layer PVX. The pixel electrode5has a second hollow portion B2, and an orthographic projection of the second hollow portion B2on the first base substrate11overlaps an orthographic projection of the common electrode7on the first base substrate11.

It should be noted that all of the orthographic projections of the first via hole c1, the first hollow portion B1, the second via hole c2and the third via hole c3on the first base substrate11are within the orthographic projection of the first hollow portion B1on the first base substrate11, so that the pixel electrode5is prevented from being short-circuited with the common electrode7.

An embodiment of the present disclosure further provides another method for manufacturing the array substrate1inFIG.4.FIG.11AtoFIG.11Eare schematic diagrams showing steps of the method for manufacturing the array substrate1. Referring toFIG.4andFIG.11AtoFIG.11E, the method includes steps S21to S25.

At step S21, as shown inFIG.11A, a first base substrate11is provided, and a gate electrode61of the thin film transistor6, a gate insulating layer GI, an active layer62of the thin film transistor6, a second electrode63and a first electrode64of the thin film transistor6, and a passivation layer PVX are sequentially formed on the first base substrate11. The second electrode63and the first electrode64of the thin film transistor6are each connected to the active layer62, and a first via hole c1exposing the first electrode64is formed in the passivation layer PVX.

At step S22, as shown inFIG.11B, a planarization layer PLN is formed on the passivation layer PVX, and a second via hole c2exposing the first electrode64is formed in the planarization layer PLN.

At step S23, as shown inFIG.11C, the pixel electrode5is formed on the planarization layer PLN, and the pixel electrode5is connected to the first electrode64of the thin film transistor6through the via hole (i.e., the combination of the first via hole c1, the second via hole c2) penetrating the planarization layer PLN and the passivation layer PVX.

At step S24, as shown inFIG.11D, the insulating layer8is formed on the pixel electrode5.

At step S25, as shown inFIG.11E, the common electrode7is formed on the insulating layer8. The common electrode7has a third hollow portion B3, and an orthographic projection of the third hollow portion B3on the base substrate overlaps an orthographic projection of the pixel electrode5on the base substrate. For example, the orthographic projection of each pixel electrode5on the base substrate overlaps the orthographic projections of a plurality of third hollows B3on the base substrate.

An embodiment of the present disclosure provides a virtual reality device, which includes above display device.

In the display device in the embodiment of the present disclosure, the spacer3is disposed in the redundant region A3, and the redundant region A3has no display effect, so that the display effect of the display panel cannot be affected. Meanwhile, by increasing the area of the second pixel region A2, the loss of brightness in the redundant region A3caused by the missing pixel structure can be compensated, and the defects of the display panel can be prevented. Therefore, when the virtual reality device adopting the display device can have high resolution, and ensure the support effect of the spacers3without shielding the effective pixel region.

It will be understood that the above embodiments are merely exemplary embodiments employed to illustrate the principles of the present disclosure, and the present disclosure is not limited thereto. It will be apparent to those skilled in the art that various changes and modifications can be made therein without departing from the spirit and essence of the present disclosure, and these changes and modifications are to be considered within the scope of the present disclosure.