Patent ID: 12237775

DETAILED DESCRIPTION

Descriptions are provided hereinbelow for embodiments based on the drawings. In the respective drawings referenced herein, the same constituents are designated by the same reference numerals and duplicate explanation concerning the same constituents is omitted. All of the drawings are provided to illustrate the respective examples only.

1. Overall Configuration of Image Formation Apparatus

As illustrated inFIG.1, an image formation apparatus5is a color electrophotographic printer, and prints a desired color image on paper of, for example, A3 size or A4 size. Incidentally, in the following description, a right end portion ofFIG.1corresponds to a front side of the image formation apparatus5, and the terms upward and downward directions, leftward and rightward directions, and forward and rearward directions are used from the viewpoint of a person facing the front side.

The image formation apparatus5includes a paper feeder8, an image formation section9(an image formation device), a fixation device10, and a paper discharging part11. The paper feeder8includes a paper cassette12that stores paper, a pickup roller13athat picks up paper stored in the paper cassette12, a separation roller13b, a paper feeding roller13c, and registration rollers14aand14bthat transport fed paper to the image formation section9.

The image formation section9is provided above the paper cassette12in the image formation apparatus5, and includes a transfer belt15, image formation units16(image formation units16K,16Y,16M, and16C), LED heads17(LED heads17K,17Y,17M, and17C), toner cartridges18(toner cartridges18K,18Y,18M, and18C), and transfer rollers19(transfer rollers19K,19Y,19M, and19C).

The transfer belt15is an endless belt that is looped around and supported by rollers whose center axes extend in the leftward/rightward direction, one being disposed on each side in the forward/rearward direction. When the transfer belt15is moved by rotation of the rollers, the transfer belt15transports paper received from the registration rollers14aand14bin the rearward direction with the paper placed on the upper surface of the transfer belt15.

The four image formation units16(image formation units16K,16Y,16M, and16C (hereinafter collectively referred to as an image formation unit16)) are provided above the transfer belt15and arranged sequentially from the front side to the rear side. In other words, the image formation units16having the respective colors are arranged in a so-called tandem manner. The image formation units16K,16Y,16M, and16C correspond to black (K), yellow (Y), magenta (M), and cyan (C), respectively. The image formation units16K,16Y,16M, and16C have the same configuration, except for corresponding toner colors.

The LED heads17K,17Y,17M, and17C (hereinafter collectively referred to as an LED head17) are provided, corresponding to the image formation units16K,16Y,16M, and16C, respectively. The LED head17has a rectangular cuboid shape that is elongated in the leftward/rightward direction. In the LED head17, light emitting diodes (LEDs) are arranged sequentially in the leftward/rightward direction. Each LED is caused to emit light with an emission pattern based on image data supplied from a head controller48(FIG.2). The image formation unit16is located very close to the LED head17, and performs an exposure process using light from the LED head17.

The toner cartridges18K,18Y,18M, and18C (hereinafter collectively referred to as a toner cartridge18) are arranged above and coupled to the image formation units16K,16Y,16M, and16C, respectively. The toner cartridges18are a long, hollow container extending in the leftward/rightward direction, contain toner powders having the respective colors, and have a predetermined built-in stirring mechanism.

The transfer rollers19K,19Y,19M, and19C (hereinafter collectively referred to as a transfer roller19) are provided at four portions directly below the respective image formation units16. Specifically, the transfer belt15is interposed between each image formation unit16and the corresponding transfer roller19with the image formation unit16facing the upper side portion of the transfer belt15. Incidentally, the transfer roller19is configured to be able to be charged.

The image formation unit16includes a charging roller20, a toner supply roller21, a development roller22, and a photosensitive drum23. The charging roller20uniformly charges a surface of the photosensitive drum23to a high voltage. The toner supply roller21supplies toner to the development roller22. The development roller22develops an electrostatic latent image formed on the surface of the photosensitive drum23using toner carried by the development roller22. The photosensitive drum23is a member that carries an electrostatic latent image on a surface (surface layer portion) thereof, and transfers the toner image developed on the surface to paper.

The fixation device10is provided downstream of the image formation section9, and includes a fixation roller24, a heater25, and a temperature detection sensor26. The fixation roller24fixes the toner image to paper. The heater25is provided in the fixation roller24, and is, for example, a halogen lamp or ceramic heater. The temperature detection sensor26is a thermistor that detects the temperature of a surface of the fixation roller24. The paper discharging part11includes a discharging roller27that discharges paper on which fixation has been completed, out of the image formation apparatus5.

2. Control Configuration of Image Formation Apparatus

As illustrated inFIG.2, an image formation apparatus1mainly includes a power supply unit30, a main control block31, and a sub-control block32.

2-1. Configuration of Power Supply Unit

The power supply unit30mainly includes a heater on/off circuit34, a primary rectification and smoothing circuit35, a primary-secondary converter36, a voltage feedback part37, a DC 24-V on/off switch38, a DC-DC converter39, a brown-in/out circuit40, and a bypass circuit41. The power supply unit30is operated using an AC voltage (AC power) output from a commercial power supply2. The commercial power supply2provides an AC voltage of 100 [V] (AC power), which is supplied from, for example, an outlet.

The heater on/off circuit34is provided at an input portion of the power supply unit30, and switches on/off the heater25(FIG.1) in the fixation device10according to a heater on/off signal Sh output from a main controller42. The primary rectification and smoothing circuit35is provided at an input portion of the power supply unit30, and rectifies and smooths an AC voltage supplied from the commercial power supply2.

The primary-secondary converter36transforms the rectified and smoothed voltage, and supplies the resultant DC voltage to the main control block31and the sub-control block32. Incidentally, in the main control block31or the sub-control block32, a DC voltage of 24 V or a DC voltage of 5 V may be decreased, and the decreased DC voltage may be supplied to logic systems in the main control block31and the sub-control block32. The primary-secondary converter36has winding outputs in the secondary, and may generate other DC voltages in addition to a DC voltage of 24 V. The voltage feedback part37detects a voltage output from the primary-secondary converter36, and feeds the result back to the primary-secondary converter36.

The DC 24-V on/off switch38includes a relay or a field effect transistor (FET), and switches on/off a DC voltage of 24 V output from the power supply unit30, according to a sleep signal Ss output from a sub-controller54.

The DC-DC converter39is a circuit that decreases a DC voltage of 24 V output from the primary-secondary converter36to a DC voltage of 5 V, and supplies the DC voltage of 5 V to the sub-control block32. The DC-DC converter39typically includes an integrated circuit (IC). In this embodiment, a combination of such an IC and a peripheral circuit is referred to as a DC-DC converter. In this embodiment, the power supply unit30supplies a DC voltage of 24 V to an actuator system in the main control block31, and a DC voltage of 5 V to logic systems in the main control block31and the sub-control block32. The type of a DC voltage output from the power supply unit30is typically determined by the configuration of the main control block31and the sub-control block32. The power supply unit30typically outputs a DC voltage of 3.3 V in addition to a DC voltage of 24 V and a DC voltage of 5 V.

The brown-in/out circuit40detects an input voltage of the DC-DC converter39, i.e., an output voltage of the primary-secondary converter36, and switches on/off the DC-DC converter39using a function of a DC-DC converter IC with reference to a certain threshold.

The bypass circuit41is provided in parallel with the DC-DC converter39. When the image formation apparatus5is in a sleep mode, then if the bypass circuit41is put into an on state, the bypass circuit41outputs a DC voltage of 5 V output from the primary-secondary converter36without through the DC-DC converter39, i.e., with the DC-DC converter39bypassed. The bypass circuit41is in an off state when the image formation apparatus5is in a normal operation mode. In the normal operation mode, the DC-DC converter39is operated to decrease a DC voltage of 24 V output from the primary-secondary converter36to a DC voltage of 5 V.

2-2. Configuration of Main Control Block

The main control block31includes a main controller42, a read-only memory (ROM)43, a random access memory (RAM)44, a temperature detector45, a sensor on/off circuit46, a high-voltage power supply47, a head controller48, and an actuator driver49.

The main controller42includes a central processing unit (CPU) (not illustrated). The main controller42reads a program from the ROM43, which is a non-volatile storage part storing programs and setting data, and operates according to the program to control the entire image formation apparatus5in a centralized manner. The main controller42, when receiving image data indicating a color image to be printed from a host6that is a higher-level device coupled to the image formation apparatus5, and a command to print the color image, executes a print process of forming a printed image on a surface of paper. The main controller42includes a counter for measuring time, and the like. The RAM44stores data, which is read by the main controller42.

The temperature detector45divides an output of the temperature detection sensor26(FIG.1) in the fixation device10using resistors, and outputs a temperature detection signal to the main controller42. The sensor on/off circuit46, which includes a transistor, basically receives a sensor on/off signal from the main controller42and switches off the supply of power to various sensors50described below, unless the image formation apparatus5is in a warm-up operation during activation or is performing printing according to a command from the host6or the like.

The high-voltage power supply47applies a high voltage to the photosensitive drum23and the rollers of the image formation section9(FIG.1). The head controller48is a controller that controls on/off of the LED head17(FIG.1). The actuator driver49is a dedicated driver that outputs a drive signal to an actuator51described below based on a logic signal output from the main controller42.

Various sensors50are a paper travel path sensor for detecting paper location (not illustrated), a sensor for correcting image density, a sensor for correcting color deviation, and the like, which are provided in the paper feeder8, the image formation section9, the fixation device10, and the paper discharging part11. The actuator51includes a motor, a clutch, a solenoid, and a cooling fan (not illustrated), which are provided in the paper feeder8, the image formation section9, the fixation device10, and the paper discharging part11. The actuator51is driven by the actuator driver49.

2-3. Configuration of Sub-Control Block

The sub-control block32includes a DC 5-V on/off switch53and a sub-controller54. The DC 5-V on/off switch53includes a FET or transistor that is a semiconductor, or a relay. The DC 5-V on/off switch53switches on/off of a DC voltage of 5 V output from the power supply unit30under the control of the sub-controller54. The sub-controller54is a microcomputer for a low consumption mode. The sub-controller54outputs a low consumption mode signal such as the sleep signal Ss. The sub-controller54can transition from a normal operation mode to a sleep mode that is a type of low consumption mode, after a preset time has passed or in association with on/off of a mechanical switch55that is pressed down by a user, and can return from the sleep mode to the normal operation mode in association with on/off of the mechanical switch55that is pressed down by a user.

3. Detailed Configuration of Power Supply Unit

As illustrated in detail inFIG.3, the power supply unit30includes a protection element60, a filter61, a filter62, a heater on/off circuit34, an AC zero-crossing detection circuit63, an inrush prevention circuit64, a primary rectification and smoothing circuit35, a primary-secondary converter36, a secondary rectification and smoothing circuit65, a voltage feedback part37, a DC 24-V protection circuit66, a secondary filter67, a DC 24-V on/off switch38, a DC-DC converter39, a brown-in/out circuit40, a DC 5-V protection circuit68, a filter69, and a bypass circuit41.

The protection element60includes a fuse for protection from overcurrent, a varistor for protection from lightning surge, or the like, and is coupled to the commercial power supply2. The filter61includes a common-mode or normal-mode choke coil and a capacitor, and is coupled to the protection element60. The capacitor, which is a so-called X capacitor, is coupled between LINE and NEUTRAL. In addition, a Y capacitor is also provided between LINE or NEUTRAL and a frame ground (FG).

The heater on/off circuit34includes a TRIAC and a photoTRIAC (not illustrated). The heater on/off circuit34switches on/off the photoTRIAC according to the heater on/off signal Sh output from the main controller42(FIG.2) to switch on/off the TRIAC, so that an electric current passes through the heater25(FIG.1) in the fixation device10. The heater on/off circuit34may include a relay in order to take measures for an anomaly such as TRIAC runaway. A plurality of heater on/off circuits34may be provided, depending on the number of heaters. The filter62is provided downstream of the heater on/off circuit34. The filter62has a configuration similar to that of the filter61.

The AC zero-crossing detection circuit63is provided upstream of the primary rectification and smoothing circuit35, and includes a rectification diode and a photocoupler (not illustrated). The AC zero-crossing detection circuit63outputs an AC zero-crossing signal Sz that goes to a high level at a zero-crossing point, to the main controller42(FIG.2). The configuration of the AC zero-crossing detection circuit63is not particularly limited.

The inrush prevention circuit64, which is provided upstream of the primary rectification and smoothing circuit35, prevents an inrush current during charging of an electrolytic capacitor78of the primary rectification and smoothing circuit35. The inrush prevention circuit64may be configured at low cost using a thermistor, but in that case, cannot prevent an inrush current at high temperature. Therefore, the inrush prevention circuit64may be configured using a circuit that is a combination of a thermistor with a resistor and a switching element such as a TRIAC or a relay.

The primary rectification and smoothing circuit35includes a rectification diode77and an electrolytic capacitor78, and is provided upstream of the primary-secondary converter36. The rectification diode77includes four diodes. As the rectification diode77, an element called a bridge diode with four elements is often used. As the electrolytic capacitor78, an aluminum electrolytic capacitor is typically used.

The primary-secondary converter36incudes a transformer71, a main FET72, a snubber circuit73, a power supply controller74, an auxiliary winding rectification and smoothing circuit75, and a voltage clamp circuit76. The transformer71, in which the primary is insulated from the secondary, transforms a voltage that is input from the commercial power supply2and then rectified and smoothed by the primary rectification and smoothing circuit35. The main FET72is a so-called switching FET that switches on/off the supply of power to the primary winding of the transformer71. The snubber circuit73, which includes a first recovery diode, a resistor, and a capacitor, inhibits a surge voltage from occurring when the main FET72is switched off. As the snubber circuit73, a Zener diode may be used in order to achieve low consumption. The power supply controller74determines the on-duty of the gate voltage of the main FET72mainly based on the result of feedback of a DC output voltage on the secondary. In this embodiment, the power supply controller74is a separately excited IC. Alternatively, the power supply controller74may be a self-excited IC that uses an auxiliary winding output voltage described below. The auxiliary winding rectification and smoothing circuit75, which includes a rectification diode and an electrolytic capacitor, mainly rectifies and smooths an auxiliary winding output voltage that is a power supply voltage for the power supply controller74. The voltage clamp circuit76, which includes a Zener diode, a rectification diode, a transistor, and a resistor, clamps the auxiliary winding output voltage when the auxiliary winding output voltage exceeds the absolute maximum rating of power supply control.

The secondary rectification and smoothing circuit65is coupled downstream of the primary-secondary converter36, and rectifies and smooths the secondary winding output voltage of the transformer71. In the case in which a DC voltage of 24 V and a DC voltage of 5 V are the two winding outputs, a rectification diode and an electrolytic capacitor are provided for each of the DC voltage of 24 V and the DC voltage of 5 V (not illustrated). A DC-DC converter may be coupled to a single output for a DC voltage of 24 V, and may output a DC voltage of 5 V. The DC voltage of 5 V may be used in logic systems in the main control block31and the sub-control block32. Instead of the DC voltage of 5 V, other voltages such as a DC voltage of 3.3 V may be used.

The voltage feedback part37is coupled downstream of the secondary rectification and smoothing circuit65, and receives the sleep signal Ss. The voltage feedback part37includes a shunt regulator80, a photocoupler81, and a set voltage conversion transistor82. The shunt regulator80is an IC that has a reference voltage, and sets a DC output voltage using a peripheral voltage-dividing resistor. The shunt regulator80, when an actual voltage fluctuates from the set voltage, switches on/off the photocoupler81, which is coupled to the shunt regulator80, and feeds the result of the detection back to the power supply controller74, thereby stabilizing the DC voltage of 24 V. The set voltage conversion transistor82is switched on/off according to the sleep signal Ss output from the sub-controller54(FIG.2) to change a peripheral voltage-dividing resistance value of the shunt regulator80, thereby changing the set voltage, and thereby changing the output voltage of the primary-secondary converter36.

The DC 24-V protection circuit66includes an overvoltage detection circuit or an overcurrent detection circuit. The overvoltage detection circuit includes a Zener diode and a photocoupler. When the overvoltage detection circuit detects an overvoltage, the overvoltage detection circuit is latched or the switching of the overvoltage detection circuit is intermittently stopped, by the power supply controller74for the primary. In addition, when an overvoltage is detected, the auxiliary winding output voltage also increases, which can be detected by the power supply controller74for the primary. The overcurrent detection circuit may have various circuit configurations such as current detection, DC output voltage droop, and fuse. The power supply controller74can be used to detect an overcurrent as a primary current. The secondary filter67, which is an LC filter, is used to inhibit a ripple voltage or a ripple noise voltage, but is not necessarily essential.

The DC 24-V on/off switch38, which is a semiconductor, a relay, or the like, is switched on/off according to the sleep signal Ss output from the sub-controller54(FIG.2). The DC 24-V on/off switch38switches on/off the supply of the output voltage of the primary-secondary converter36to the main controller42, according to the sleep signal Ss output from the sub-controller54.

The DC-DC converter39decreases a DC voltage of 24 V voltage output from the secondary rectification and smoothing circuit65(i.e., the primary-secondary converter36) to a DC voltage of 5 V, and outputs the DC voltage of 5 V. The type of the DC-DC converter39is determined between the drop type and the switching type, depending on the load current. In addition, a switching frequency is typically determined. In this embodiment, it is assumed that the DC-DC converter39is of the switching type. The input terminal and output terminal of the DC-DC converter39are referred to as an IN terminal and an OUT terminal, respectively. Furthermore, the DC-DC converter39is often a DC-DC converter IC that has an on/off function at an external terminal thereof. In this embodiment, the external terminal is referred to as an ENABLE terminal.

The brown-in/out circuit40is coupled downstream of the secondary rectification and smoothing circuit65, and mainly includes a brown-in/out Zener diode84, an upstream transistor85, and a downstream transistor86. The collector terminal of the downstream transistor86is coupled to the ENABLE terminal of the DC-DC converter39. The brown-in/out Zener diode84is coupled to an output of the secondary rectification and smoothing circuit65. The brown-in/out Zener diode84switches on/off the upstream transistor85and the downstream transistor86, depending on whether or not a voltage higher than the Zener voltage is applied to the brown-in/out Zener diode84from the secondary rectification and smoothing circuit65, thereby switching a DCDC operating voltage Vdce to a high level or a low level. The Zener voltage of the brown-in/out Zener diode84is any voltage that is determined by the ENABLE function or peripheral constant of the DC-DC converter39.

The DC 5-V protection circuit68is provided downstream of the DC-DC converter39, and has a configuration similar to that of the DC 24-V protection circuit66. In the case in which the DC 5-V protection circuit68is coupled to the power supply controller74, a photocoupler (not illustrated) is required. The DC 24-V protection circuit66and the DC 5-V protection circuit68may share a single common output. The filter69, which is an LC filter, is used to inhibit a ripple voltage or a ripple noise voltage, but is not necessarily essential.

The bypass circuit41mainly includes a bypass circuit FET88, a rectification diode89, and a Zener diode90. The drain and source terminals of the bypass circuit FET88are coupled to the IN and OUT terminals, respectively, of the DC-DC converter39. The gate terminal of the bypass circuit FET88receives the sleep signal Ss. The rectification diode89is coupled between the drain and source terminals of the bypass circuit FET88. In addition, a rectification diode that is, for example, a Schottky barrier diode is coupled between the OUT terminal of the DC-DC converter39and the bypass circuit FET88. The Zener diode90, when the bypass circuit FET88is switched from on to off, clamps a Zener downstream voltage Vt (described below) using a Zener voltage to hold 5 [V] even if a FET output voltage Vfo (described below) increases from 5 [V] toward 24 [V].

4. Operation of Image Formation Apparatus

FIG.4illustrates a time chart of the power supply unit30in the sleep mode and the normal operation mode, which are a representative operation mode of the image formation apparatus5.

4-1. Description of Entire Time Chart

InFIG.4, the vertical axis represents voltages, and the horizontal axis represents elapsed time.FIG.4illustrates eight waveforms of the sleep signal Ss, a DCDC input voltage Vdci, a DCDC operating voltage Vdce, a DCDC output voltage Vdco, a FET output voltage Vfo, a Zener downstream voltage Vt, a DC 5-V output voltage, and a DC 24-V output voltage.

The horizontal axis ofFIG.4also indicates the case in which the image formation apparatus5transitions to the sleep mode and then to the normal operation mode in sequence. The sleep mode is a type of low consumption mode (energy-saving mode). The normal operation mode is a mode that occurs after exit of the sleep mode, including an initial mode, a print mode, a wait mode, and a power-saving mode.

Specifically, at time t1, the image formation apparatus5is in the sleep mode. At time t2, the sleep mode is exited, so that the image formation apparatus5transitions to the initial mode, and starts a warm-up operation, and after a predetermined time has passed, transitions to the print mode.

4-2. Description of Each Signal Waveform

The sleep signal Ss is output from the sub-controller54and is then input to the DC 24-V on/off switch38, the voltage feedback part37, and the bypass circuit41. The sleep signal Ss has positive polarity, and therefore, goes to a low level (OFF) when the operation mode is the normal operation mode. As a result, a DC voltage of 24 V is output. Meanwhile, when the operation mode is the sleep mode, the sleep signal Ss goes to a high level (ON). As a result, the output of a DC voltage of 24 V is stopped. The sleep signal Ss may have negative polarity.

The DCDC input voltage Vdci is input to the IN terminal of the DC-DC converter39, i.e., represents the output voltage of the secondary rectification and smoothing circuit65. The DCDC operating voltage Vdce represents a voltage that is input to the ENABLE terminal of the DC-DC converter39. The DCDC output voltage Vdco represents the output voltage of an output portion (i.e., the OUT terminal) of the DC-DC converter39.

The FET output voltage Vfo represents the output voltage (the voltage of the source terminal) of the bypass circuit FET88of the bypass circuit41. The Zener downstream voltage Vt represents the voltage of an output portion of the Zener diode90.

The DC 5-V output voltage represents an output voltage that is a DC voltage of 5 V output from the power supply unit30to the sub-control block32. The DC 24-V output voltage represents an output voltage that is a DC voltage of 24 V output from the power supply unit30to the main control block31.

4-3. Operation

The image formation apparatus5is in the sleep mode, and at time t1, the sleep signal Ss output from the sub-controller54is at the high level, and therefore, the DC 24-V on/off switch38is off, and the DC 24-V output voltage is 0 [V]. It should be noted that at time t1the primary-secondary converter36is operating. In addition, as the sleep signal Ss is at the high level, the set voltage conversion transistor82is on, and the set voltage has been changed from a DC voltage of 24 V. In this embodiment, the set voltage conversion transistor82has changed the set voltage to, for example, a DC voltage of 5 V. As the set voltage of the voltage feedback part37has been changed from a DC voltage of 24 V to a DC voltage of 5 V, the DCDC input voltage Vdci is maintained at 5 [V].

In the brown-in/out circuit40, as the Zener voltage of the brown-in/out Zener diode84is set higher than a DC voltage of 5 V, the upstream transistor85is off and the downstream transistor86is on, so that the DCDC operating voltage Vdce is at the low level. Therefore, at time t1, the DC-DC converter39is not operating, and the DCDC output voltage Vdco is 0 [V]. In addition, at time t1, the sub-controller54applies the sleep signal Ss with the high level to the gate terminal of the bypass circuit FET88, so that the bypass circuit FET88is on, which allows conduction between the drain terminal and the source terminal. Therefore, the FET output voltage Vfo is 5 [V], which is the output voltage of the secondary rectification and smoothing circuit65in the sleep mode, and the Zener downstream voltage Vt is also 5 [V]. As a result, the DC 5-V output voltage is also 5 [V].

At time t2, when, for example, the user presses down the mechanical switch55, the image formation apparatus5returns from the sleep mode to the normal operation mode, and the sub-controller54outputs the sleep signal Ss with the low level. Therefore, the set voltage conversion transistor82is switched off, and the set voltage is changed from a DC voltage of 5 V to a DC voltage of 24 V. As a result, the DCDC input voltage Vdci starts increasing from 5 [V] toward 24 [V]. When a voltage that is higher than the Zener voltage of the brown-in/out Zener diode84is applied as an inverse voltage to the brown-in/out circuit40by the DCDC input voltage Vdci, the upstream transistor85is switched on, and the downstream transistor86is switched off, so that the DCDC operating voltage Vdce goes to the high level. As a result, at time t2the DC-DC converter39starts operating, so that the DCDC output voltage Vdco starts increasing from 0 [V] toward 5 [V].

When at time t2the output voltage of the secondary rectification and smoothing circuit65in the sleep mode, i.e., 5 [V], is applied to the input side of the DC 24-V on/off switch38, so that the DC 24-V on/off switch38is switched on according to the sleep signal Ss with the low level, the DC 24-V output voltage increases to 5 [V]. Thereafter, the DC 24-V output voltage starts increasing toward 24 [V], which is the output voltage of the secondary rectification and smoothing circuit65in the normal operation mode.

It should be noted that it takes a predetermined time for the DCDC input voltage Vdci to reach a voltage higher than the Zener voltage of the brown-in/out Zener diode84after starting increasing at time t2. Therefore, actually, the DCDC operating voltage Vdce reaches the high level a predetermined time after time t2(not illustrated inFIG.4).

In addition, at time t2, when the sub-controller54applies the sleep signal Ss with the low level to the gate terminal of the bypass circuit FET88, the bypass circuit FET88is switched off, which establishes insulation between the drain and the source. However, the bypass circuit FET88is not immediately switched off, due to the peripheral RC time constant. Therefore, the FET output voltage Vfo is affected by the output voltage of the secondary rectification and smoothing circuit65in the normal operation mode, i.e., 24 [V], and therefore, increases from 5 [V]. It should be noted that as the Zener downstream voltage Vt is clamped by the Zener voltage of the Zener diode90, the Zener downstream voltage Vt is maintained at 5 [V]. As a result, the DC 5-V output voltage is also maintained at 5 [V].

After the DCDC input voltage Vdci reaches 24 [V] at time t3, the DCDC input voltage Vdci is maintained at 24 [V] by the voltage feedback part37. Therefore, the DC 24-V output voltage is also maintained at 24 [V]. At time t3, a voltage that is higher than the Zener voltage of the brown-in/out Zener diode84in the brown-in/out circuit40is applied as an inverse voltage by the DCDC input voltage Vdci, and therefore, the DCDC operating voltage Vdce is maintained at the high level. In addition, at time t3, the DCDC output voltage Vdco is still continuing to increase toward 5 [V]. The bypass circuit FET88is not immediately switched off, due to the peripheral RC time constant, and therefore, the FET output voltage Vfo continues to increase. It should be noted that as the Zener downstream voltage Vt is clamped by the Zener voltage of the Zener diode90, the Zener downstream voltage Vt is maintained at 5 [V]. As a result, the DC 5-V output voltage is also maintained at 5 [V].

At time t4, the bypass circuit FET88is switched off, so that the FET output voltage Vfo starts decreasing. After the DCDC output voltage Vdco reaches 5 [V] at time t5, the DCDC output voltage Vdco is maintained at 5 [V] by the DC-DC converter39. At time t5, the FET output voltage Vfo is still continuing to decrease toward 0 [V].

After the FET output voltage Vfo reaches 0 [V] at time t6, the FET output voltage Vfo is maintained at 0 [V] because the bypass circuit FET88is off. It should be noted that at time t6the DCDC output voltage Vdco is maintained at 5 [V], and therefore, the DC 5-V output voltage is maintained at 5 [V]. At time t6the Zener downstream voltage Vt starts decreasing toward 0 [V], and reaches 0 [V] after a predetermined time.

5. Comparative Example

As illustrated inFIG.1,FIG.5, in which members corresponding to those ofFIG.2are indicated by the same reference characters, andFIG.6, in which members corresponding to those ofFIG.3are indicated by the same reference characters, an image formation apparatus105according to a comparative example has the same configuration as that of the image formation apparatus5, except that a power supply unit130is provided instead of the power supply unit30. The power supply unit130of the comparative example has the same configuration as that of the power supply unit30, except that a voltage feedback part137is provided instead of the voltage feedback part37, and the bypass circuit41is removed. The voltage feedback part137of the comparative example has the same configuration as that of the voltage feedback part37, except that the set voltage conversion transistor82and several resistors are removed, and the sleep signal Ss is not input thereto.

6. Operation of Image Formation Apparatus of Comparative Example

FIG.7, which corresponds toFIG.4, illustrates a time chart of the power supply unit130in a sleep mode and a normal operation mode, which are a representative operation mode of the image formation apparatus105.

6-1. Description of Entire Time Chart

InFIG.7, the vertical axis represents voltages, and the horizontal axis represents elapsed time.FIG.7illustrates six waveforms of the sleep signal Ss, the DCDC input voltage Vdci, the DCDC operating voltage Vdce, the DCDC output voltage Vdco, the DC 5-V output voltage, and the DC 24-V output voltage. The horizontal axis ofFIG.7also indicates the case in which the image formation apparatus105transitions to the sleep mode and then to the normal operation mode in sequence.

Specifically, at time t11, the image formation apparatus105is in the sleep mode. At time t12, the sleep mode is exited, so that the image formation apparatus105transitions to the initial mode, starts a warm-up operation, and after a predetermined time has passed, transitions to the print mode.

6-2. Description of Each Signal Waveform

The sleep signal Ss, the DCDC input voltage Vdci, the DCDC operating voltage Vdce, the DCDC output voltage Vdco, the DC 5-V output voltage, and the DC 24-V output voltage are the signals and voltages at portions similar to those of the power supply unit30.

6-3. Operation

The image formation apparatus105is in the sleep mode, and at time t1, the sleep signal Ss output from the sub-controller54is at the high level, and therefore, the DC 24-V on/off switch38is off, and the DC 24-V output voltage is 0 [V]. It should be noted that at time t11the primary-secondary converter36is operating, and therefore, the DCDC input voltage Vdci is 24 [V]. Therefore, in the brown-in/out circuit40, the upstream transistor85is on, and the downstream transistor86is off, so that the DCDC operating voltage Vdce is at the high level. As a result, at time t11the DC-DC converter39is operating, and therefore, the DCDC output voltage Vdco is 5 [V], and the DC 5-V output voltage is 5 [V].

When at time t12, for example, the user presses down the mechanical switch55, the image formation apparatus105returns from the sleep mode to the normal operation mode, and the sub-controller54outputs the sleep signal Ss with the low level. Therefore, the DC 24-V on/off switch38is switched on, and the DC 24-V output voltage starts increasing from 0 [V] toward 24 [V]. At time t12the primary-secondary converter36is still operating, and therefore, the DCDC input voltage Vdci is 24 [V]. Therefore, in the brown-in/out circuit40, the upstream transistor85is on, and the downstream transistor86is off, so that the DCDC operating voltage Vdce is at the high level. Therefore, at time t12the DC-DC converter39is operating, and therefore, the DCDC output voltage Vdco is 5 [V], and the DC 5-V output voltage is 5 [V].

When the DC 24-V output voltage reaches 24 [V] at time t13, the DC 24-V output voltage is maintained at 24 [V] by the voltage feedback part137.

7. Effects and the Like

As described above, the image formation apparatus5is configured to convert the commercial power supply2using the primary-secondary converter36based on feedback of a set voltage from the voltage feedback part37to the primary-secondary converter36, thereby outputting a DC voltage of 24 V or a DC voltage of 5 V. The image formation apparatus5is also configured to switch on/off the DC-DC converter39that decreases a DC voltage of 24 V output from to the primary-secondary converter36, to a DC voltage of 5 V, under the control of the brown-in/out circuit40. Furthermore, in the image formation apparatus5, the bypass circuit41that outputs a DC voltage of 5 V output from the primary-secondary converter36without through the DC-DC converter39, i.e., with the DC-DC converter39bypassed, is provided in parallel with the DC-DC converter39.

When the image formation apparatus5thus configured is in the normal operation mode, the primary-secondary converter36outputs and supplies a DC voltage of 24 V as a power voltage to an actuator system (power system) in the main control block31, and the DC-DC converter39is switched on, so that the DC voltage of 24 V output from the primary-secondary converter36is decreased to a DC voltage of 5 V by the DC-DC converter39, and is supplied as a control voltage (logic voltage) to logic systems in the main control block31and the sub-control block32.

Meanwhile, when the image formation apparatus5is in the sleep mode, which is a power-saving mode, the primary-secondary converter36outputs a DC voltage of 5 V and the DC 24-V on/off switch38is switched off, so that a voltage is not supplied to an actuator system in the main control block31and the DC-DC converter39is switched off to be inactivated while the bypass circuit41is switched on, so that the DC voltage of 5 V output from the primary-secondary converter36is supplied as a control voltage to logic systems in the main control block31and the sub-control block32, with the DC-DC converter39bypassed using the bypass circuit41.

Therefore, compared to the case in which the primary-secondary converter36outputs a DC voltage of 24 V in the sleep mode as in the comparative example, in the image formation apparatus5the output voltage of the transformer71can be decreased, so that power consumed in the primary-secondary converter36can be reduced, leading to a reduction in overall power consumption in the image formation apparatus5.

In addition, compared to the case in which in the sleep mode the DC-DC converter39is switched on, so that a DC voltage of 24 V output from the primary-secondary converter36is decreased to a DC voltage of 5 V by the DC-DC converter39as in the comparative example, in the image formation apparatus5the DC-DC converter39is switched off to be inactivated, and therefore, power consumed in the DC-DC converter39can be reduced to substantially zero, leading to a reduction in overall power consumption in the image formation apparatus5.

The image formation apparatus5thus configured includes: the primary-secondary converter36that generates, from the commercial power supply2, a DC voltage of 24 V as a first voltage, and a DC voltage of 5 V as a second voltage that is lower than the DC voltage of 24 V; the DC-DC converter39that decreases the DC voltage of 24 V to a DC voltage of 5 V; the bypass circuit41that outputs the DC voltage of 5 V output from the primary-secondary converter36, with the DC-DC converter39bypassed; and the sub-controller54that, in the normal operation mode, causes the primary-secondary converter36to generate and output a DC voltage of 24 V, and causes the DC-DC converter39to operate and decrease the DC voltage of 24 V to a DC voltage of 5 V and output the DC voltage of 5 V, and in the sleep mode, which is a power-saving mode, causes the primary-secondary converter36to generate a DC voltage of 5 V instead of a DC voltage of 24 V, and output the DC voltage of 5 V through the bypass circuit41without causing the DC-DC converter39to operate.

As a result, in the image formation apparatus5, in the sleep mode power consumed in the primary-secondary converter36and the DC-DC converter39can be reduced, leading to a reduction in overall power consumption in the image formation apparatus5in the sleep mode, even in the case in which the image formation apparatus5is a single transformer.

8. Other Embodiments

It should be noted that in the above-described embodiment the case has been described in which, in the image formation apparatus5, the bypass circuit41mainly includes the bypass circuit FET88, which serves as a switch. The invention is not limited to this. In the image formation apparatus5, the bypass circuit41may include, for example, a transistor that is a semiconductor instead of a FET, or various relays. Thus, in the image formation apparatus5, in the sleep mode the bypass circuit that includes various types of switches is switched on, and a DC voltage of 5 V output from the secondary rectification and smoothing circuit65(i.e., the primary-secondary converter36) is output without through the DC-DC converter39, i.e., with the DC-DC converter39bypassed, and in the normal operation mode, the bypass circuit that includes various types of switches is switched off, and a DC voltage of 24 V output from the secondary rectification and smoothing circuit65(i.e., the primary-secondary converter36) is decreased to a DC voltage of 5 V by the DC-DC converter39, and the DC voltage of 5 V is output.

In addition, in the above-described embodiment, in the image formation apparatus5the brown-in/out Zener diode84is coupled to the output of the secondary rectification and smoothing circuit65. When a DC voltage of 24 V, which is higher than the Zener voltage of the brown-in/out Zener diode84, is applied from the secondary rectification and smoothing circuit65, as an inverse voltage of the brown-in/out Zener diode84, in the normal operation mode, the DCDC operating voltage Vdce is caused to go to the high level. Meanwhile, when a DC voltage of 5 V, which is lower than the Zener voltage of the brown-in/out Zener diode84, is applied from the secondary rectification and smoothing circuit65, as an inverse voltage of the brown-in/out Zener diode84, in the sleep mode, the DCDC operating voltage Vdce is caused to go to the low level. Thus, in the image formation apparatus5, the DCDC operating voltage Vdce is switched between the high and low levels, depending on the voltage detection of the DCDC input voltage Vdci by the brown-in/out circuit40.

The invention is not limited to this. In the image formation apparatus5, the sleep signal Ss may be input to the ENABLE terminal of the DC-DC converter39with the polarity of the sleep signal Ss inversed by a transistor and a resistor. When the sleep signal Ss is at the low level, the DCDC operating voltage Vdce may be caused to be at the high level, and when the sleep signal Ss is at the high level, the DCDC operating voltage Vdce may be caused to be at the low level. In other words, in the image formation apparatus5, the DCDC operating voltage Vdce may be switched between the high and low levels, depending on detection of whether the sleep signal Ss is at the low level or the high level.

Furthermore, in the above-described embodiment, in the image formation apparatus5the sleep signal Ss is input to the gate terminal of the bypass circuit FET88, and the gate voltage of the bypass circuit FET88is switched on by the high level of the sleep signal Ss, while the gate voltage of the bypass circuit FET88is switched off by the low level of the sleep signal Ss. Thus, in the image formation apparatus5, the gate voltage of the bypass circuit FET88is switched on or off by the high or low level of the sleep signal Ss.

The invention is not limited to this. In the image formation apparatus5, the output of the downstream transistor86of the brown-in/out circuit40may be coupled to the bypass circuit FET88so that the gate voltage of the bypass circuit FET88is switched on or off. In that case, in the image formation apparatus5, the polarity may be inversed by a transistor and a resistor as appropriate.

Furthermore, in the above-described embodiment, the invention is applied to the image formation apparatus5including four image formation units16. The invention is not limited to this. The invention may be applied to the image formation apparatus5including at most three or at least five image formation units16as appropriate.

Furthermore, in the above-described embodiment, the invention is applied to the image formation apparatus5that is a color printer having a single function. The invention is not limited to this. For example, the invention may be applied to an image formation apparatus having multiple functions such as a multi-function peripheral having a photocopier function and a facsimile device function.

Furthermore, in the above-described embodiment, the invention is applied to the image formation apparatus5. The invention is not limited to this. The invention may be applied to various devices that are operated by AC power supplied from the commercial power supply2.

Furthermore, the invention is not limited to the above-described embodiment or other embodiments described above. Specifically, the scope of the invention encompasses any combination of all or a part of the embodiments. The scope of the invention also encompasses any one of the embodiments a part of which is extracted and replaced or substituted with a part of another one of the embodiments, and any one of the embodiments to which the extracted part is added.

Furthermore, in the above-described embodiment, the primary-secondary converter36serving as a voltage generator, the DC-DC converter39serving as a voltage step-down part, the bypass circuit41serving as a bypass part, and the sub-controller54serving as a controller constitute the power supply unit30and the sub-control block32serving as a power supply device. The invention is not limited to this. A voltage generator, a voltage step-down part, a bypass part, and a controller that have various other configurations may constitute a power supply device.

The invention may be, for example, applicable to an image formation apparatus that is supplied with power from a commercial power supply.