Patent ID: 12198778

DETAILED DESCRIPTION OF THE EMBODIMENTS

Some examples of embodiments of the present disclosure will be described more fully hereinafter with reference to the accompanying drawings. Like reference numerals may refer to like elements throughout the accompanying drawings.

FIG.1is a block diagram illustrating a memory system according to some example embodiments.

Referring toFIG.1, a memory system20may include a memory controller100and a memory module MM. The memory module MM may include a plurality of semiconductor memory devices200a˜200k,200paand200pb. Hereinafter, the plurality of semiconductor memory devices200a˜200k,200paand200pbmay be referred to as a plurality of memory chips. The plurality of memory chips200a˜200k,200paand200pbmay include a plurality of data chips200a˜200k, a first parity chip200pa, and a second parity chip200pb. In example embodiments, k may be 16, but the present disclosure is not limited thereto.

The memory controller100may control an overall operation of the memory system20. The memory controller100may control an overall data exchange between a host (not shown) and the plurality of memory chips200a˜200k,200paand200pb. For example, the memory controller100may write data in the plurality of memory chips200a˜200k,200paand200pband/or read data from the plurality of memory chips200a˜200k,200paand200pbin response to a request from the host. In addition, the memory controller30may issue operation commands to the plurality of memory chips200a˜200k,200paand200pbfor controlling the plurality of memory chips200a˜200k,200paand200pb.

In some example embodiments, each of the plurality of memory chips200a˜200k,200paand200pbincludes volatile memory cells such as a dynamic random access memory (DRAM).

In some example embodiments, each of the data chips200a˜200kmay be referred to as a data memory, and each of the parity chips200paand200pbmay be referred to as an error correction code (ECC) memory, or a redundant memory.

The memory controller100may transmit an address ADDR and a command CMD to the memory module MM and may exchange a codeword set SCW with the memory module MM.

The memory controller100may include a processor110and an error correction circuit130.

The processor110may control overall operation of the memory controller100and may control the error correction circuit130.

The error correction circuit130, in a write operation, may divide a user data set into a plurality of data units, each of which includes a plurality of data bits. The error correction circuit130may identify each of the plurality of data units as one of a plurality of types based on characteristic of the data bits of the each of the plurality of data units. The error correction circuit130may generate data flags indicating the plurality of types, may generate data parities by performing a first error correction code (ECC) encoding on the plurality of data units, may generate flag parities by performing a second ECC encoding on the data flags, may generate an encoded user data set by using at least one null data unit in which all or half of included data bits are zero, from among the plurality of data units. The at least one null data unit may be used as a data duplication space for duplicating a valid data unit in which all or half of included data bits are valid, from among the plurality of data units. The error correction circuit130may generate a codeword set by interleaving the encoded user data set, the data parities, the data flags, the flag parities and a null bit bit-wisely and may transmit the codeword set to the memory module MM.

The decoding circuit440, in a read operation, may generate the encoded user data set, the data parities, the data flags and the flag parities by deinterleaving the user codeword set bit-wisely, read from the memory module MM, may generate decoded data flags by performing a first ECC decoding on the data flags based on the flag parities and may generate a decoded user data set by decoding the encoded user data set based on the data parities and the decoded data flags.

Because the error correction circuit130interleaves the encoded user data set, the data parities, the data flags, the flag parities and the null bit bit-wisely in the write operation, consecutive 18 bits in the codeword set SCW may be stored in each of the plurality of memory chips200a˜200k,200paand200pband an original data bit and a duplicated data bit may be stored in different memory chips, data parities corresponding to two data units may be stored in different memory chips, each half of the data flags may be stored in different memory chips and each half of the flag parities may be stored in different memory chips. Therefore, when errors occur in one memory chip, the original data bit may be recovered by performing OR operation on the original data bit and the duplicated data bit and the original data bit is robust to errors and one error is detected in half of the data flags and in half of the flag parities and the error may be corrected.

FIG.2is block diagram illustrating an example of the memory controller in the memory system ofFIG.1according to some example embodiments.

Referring toFIG.2, the memory controller100may include the processor110, a host interface120, a data register125, the error correction circuit130, a command buffer190and an address buffer195. The error correction circuit130may include an encoding circuit410, a decoding circuit440and a memory180.

The host interface120may receive a request REQ and a user data set SDQ from the host, and may provide the user data set SDQ to the data register125. The data register125may provide the user data set SDQ to the error correction circuit130.

The encoding circuit410may divide the user data set SDQ into a plurality of data units, each of which includes a plurality of data bits, and the encoding circuit410may identify each of the plurality of data units as one of a plurality of types based on characteristic of the data bits of the each of the plurality of data units. The encoding circuit410may generate data flags indicating the plurality of types, may generate data parities by performing a first ECC encoding on the plurality of data units, may generate flag parities by performing a second ECC encoding on the data flags, may generate an encoded user data set by using at least one null data unit in which all or half of included data bits are zero, from among the plurality of data units as a data duplication space for duplicating a valid data unit in which all or half of included data bits are valid, from among the plurality of data units, may generate a first codeword set SCW1by interleaving the encoded user data set, the data parities, the data flags, the flag parities and a null bit bit-wisely and may transmit the first codeword set SCW1to the memory module MM.

The decoding circuit440may receive a second codeword set SCW2from the memory module MM, may generate the encoded user data set, the data parities, the data flags and the flag parities by deinterleaving the second codeword set SCW2bit-wisely, may generate decoded data flags by performing a first ECC decoding on the data flags based on the flag parities, may generate a decoded user data set D_SDQ by decoding (e.g., performing a second ECC decoding) of the encoded user data set based on the data parities and the decoded data flags, and may provide the decoded user data set D_SDQ to the processor110.

The memory180may store a parity generation matrix and a parity check matrix.

The encoding circuit410may perform the first ECC encoding and the second ECC encoding based on the parity generation matrix and the decoding circuit440may perform the first ECC decoding and the second ECC decoding based on the parity check matrix.

The processor110may receive the decoded user data set D_SDQ and may control the error correction circuit130, the command buffer190and the address buffer195. The command buffer190may store the command CMD corresponding to the request REQ and may transmit the command CMD to the memory module MM under control of the processor110. The address buffer195may store the address ADDR and may transmit the address ADDR to the memory module MM under control of the CPU110.

FIG.3illustrates data sets corresponding to a plurality of burst lengths in the memory system ofFIG.1, according to some example embodiments.

Referring toFIG.3, each of the memory chips200a˜200k,200paand200pbmay perform a burst operation. Herein, the burst operation refers to an operation of writing or reading a large amount of data by sequentially increasing or decreasing an initial address provided from the memory controller100. A basic unit of the burst operation may be referred to a burst length BL.

Each of a plurality of data units DQ_BL1˜DQ_BLkm, DQ_BLa, and DQ_BLb corresponding to the plurality of burst lengths are input to/output from each of the each of the memory chips200a˜200k,200paand200pb.

Each of the plurality of data units DQ_BL1˜DQ_BLkm, DQ_BLa, and DQ_BLb may include data segments DQ_BL_SG11˜DQ_BL_SG18corresponding to each burst length of the plurality of burst lengths.

The plurality of data units DQ_BL1˜DQ_BLkm, DQ_BLa, and DQ_BLb, may correspond to the codeword set SCW, and the codeword set SCW may include an encoded user data set E_SDQ, data parities DP, data flags DF, flag parities FP, and null bits NB. The null bits NB may correspond to ‘00’.

The burst length is assumed to be 8 inFIG.3, and it is assumed that the burst operation is performed once. While the burst operation is performed once in each of the memory chips200a˜200k,200paand200pb, data DQ1˜DQ4are input to/output from each of the memory chips200a˜200k,200paand200pb

FIG.4is a block diagram illustrating one of the memory chips in the memory module ofFIG.1according to some example embodiments.

InFIG.4, it is assumed that each of the memory chips200a˜200k,200paand200pbinFIG.1employs a volatile memory device.

Referring toFIG.4, the memory chip200amay include a control logic circuit210, an address register220, a bank control logic circuit230, a row address multiplexer240, a column address latch250, a row decoder260, a column decoder270, a memory cell array310, a sense amplifier unit285, an input/output (I/O) gating circuit290, a refresh counter245and a data input/output (I/O) buffer295.

The memory cell array310may include first through eighth bank arrays310a˜310h.

The row decoder260may include first through eighth bank row decoders260a˜260hcoupled to the first through eighth bank arrays310a˜310h, respectively. The column decoder270may include first through eighth bank column decoders270a˜270hcoupled to the first through eighth bank arrays3107a˜310h, respectively. The sense amplifier unit285may include first through eighth bank sense amplifiers285a˜285hcoupled to the first through eighth bank arrays310a˜310h, respectively.

The first through eighth bank arrays310a˜310h, the first through eighth bank row decoders260a˜260h, the first through eighth bank column decoders270a˜270h, and the first through eighth bank sense amplifiers285a˜285hmay form first through eighth banks. Each of the first through eighth bank arrays may include a plurality of word-lines WL, a plurality of bit-lines BTL, and a plurality of memory cells MC formed at intersections of the word-lines WL and the bit-lines BTL.

Although the memory chip200ais illustrated inFIG.4as including eight banks, the memory chip200amay include any number of banks.

The address register220may receive the address ADDR including a bank address BANK_ADDR, a row address ROW_ADDR, and a column address COL_ADDR from the memory controller100. The address register220may provide the received bank address BANK_ADDR to the bank control logic230, may provide the received row address ROW_ADDR to the row address multiplexer240, and may provide the received column address COL_ADDR to the column address latch250.

The bank control logic230may generate bank control signals in response to the bank address BANK_ADDR. One of the first through eighth bank row decoders260a˜260hcorresponding to the bank address BANK_ADDR may be activated in response to the bank control signals, and one of the first through eighth bank column decoders270a˜270hcorresponding to the bank address BANK_ADDR may be activated in response to the bank control signals.

The row address multiplexer240may receive the row address ROW_ADDR from the address register220, and may receive a refresh row address REF_ADDR from the refresh counter245. The row address multiplexer240may selectively output the row address ROW_ADDR or the refresh row address REF_ADDR as a row address RA. The row address RA that is output from the row address multiplexer240may be applied to the first through eighth bank row decoders260a˜260h.

The activated one of the first through eighth bank row decoders260a˜260hmay decode the row address RA that is output from the row address multiplexer240, and may activate a word-line WL corresponding to the row address RA. For example, the activated bank row decoder may generate a word-line driving voltage and may apply the word-line driving voltage to the word-line WL corresponding to the row address RA.

The column address latch250may receive the column address COL_ADDR from the address register220, and may temporarily store the received column address COL_ADDR. In some example embodiments of the inventive concepts, in a burst mode, the column address latch250may generate column addresses COL_ADDR′ that increments from the received column address COL_ADDR. The column address latch250may apply the temporarily stored or generated column address COL_ADDR′ to the first through eighth bank column decoders270a˜270h.

The activated one of the first through eighth bank column decoders270a˜270hmay decode the column address COL_ADDR that is output from the column address latch250, and may control the I/O gating circuit290to output data corresponding to the column address COL_ADDR.

The I/O gating circuit290may include circuitry for gating input/output data. The I/O gating circuit290may further include read data latches for storing data that is output from the first through eighth bank arrays310a˜310h, and write control devices for writing data to the first through eighth bank arrays310a˜310h.

Data set read from one of the first through eighth bank arrays310a˜310hmay be sensed by a sense amplifier285a˜285hcoupled to the one bank array from which the data set is to be read, and may be stored in the read data latches.

The data set DQ_BL1stored in the read data latches may be provided to the memory controller100through the data set to the data I/O buffer295. Data set DQ_BL1to be written in one of the first through eighth bank arrays310˜380may be provided to the data I/O buffer295from the memory controller100. The data I/O buffer295may provide the data set DQ_BL1to the I/O gating circuit290and the I/O gating circuit290may store the data set DQ_BL1in a sub-page of one bank array.

The control logic circuit210may control operations of the memory chip200a. For example, the control logic circuit210may generate control signals for the memory chip200ato perform the write operation or the read operation. The control logic circuit210may include a command decoder211that decodes the command CMD received from the memory controller100and a mode register212that sets an operation mode of the memory chip200a.

For example, the command decoder211may generate the control signals corresponding to the command CMD by decoding a write enable signal, a row address strobe signal, a column address strobe signal, a chip select signal, etc.

FIG.5illustrates an example of the first bank array in the memory chip ofFIG.4according to some example embodiments.

Referring toFIG.5, the first bank array310amay include a plurality of word-lines WL˜WLm−1 (where m is an even number equal to or greater than two), a plurality of bit-lines BTL0˜BTLn−1 (where n is an even number equal to or greater than two), and a plurality of memory cells MCs arranged at intersections between the word-lines WL0˜WLm−1 and the bit-lines BTL0˜BTLn−1.

The word-lines WL˜WLm−1 may extend in a first direction D1and the bit-lines BTL0˜BTLn−1 may extend in a second direction D2.

Each of the memory cells MCs may include an access (cell) transistor coupled to one of the word-lines WL0˜WLm−1 and one of the bit-lines BTL0˜BTLn−1 and a storage (cell) capacitor coupled to the cell transistor. That is, each of the memory cells MCs has a DRAM cell structure.

In addition, the memory cells MCs may have a different arrangement depending on that the memory cells MCs are coupled to an even word-line (for example, WL0) or an odd word-line (for example, WL1). That is, a bit-line coupled to adjacent memory cells may be different depending on whether a word-line selected by an access address is an even word-line or an odd word-line.

FIG.6is a block diagram illustrating an example of the error correction circuit130inFIG.2according to some example embodiments.

Referring toFIG.6, the error correction circuit130may include an encoding circuit410, a decoding circuit440and a memory180. The memory180may be referred to as an ECC memory180.

The memory180may be connected to the encoding circuit410and the decoding circuit440and may store a parity generation matrix PGM and a parity check matrix PCM.

The error correction circuit130, in a write operation, may divide the user data set SDQ into a plurality of data units, each of which includes a plurality of data bits, may identify each of the plurality of data units as one of a plurality of types based on characteristic of the data bits of the each of the plurality of data units, may generate data flags DF indicating the plurality of types, may generate data parities DP by performing a first ECC encoding on the plurality of data units, may generate flag parities FP by performing a second ECC encoding on the data flags DF, may generate the encoded user data set E_SDQ by using at least one null data unit in which all or half of included data bits are zero, from among the plurality of data units as a data duplication space for duplicating a valid data unit in which all or half of included data bits are valid, from among the plurality of data units, and may generate a codeword set SCW1by interleaving the encoded user data set E_SDQ, the data parities DP, the data flags DF, the flag parities FP and a null bit NB bit-wisely.

The decoding circuit440, in a read operation, may receive a codeword set SCW2including the encoded user data set E_SDQ, the data parities DP, the data flags DF, the flag parities FP and the null bit NB which are interleaved, from the memory module MM, may generate the user data set E_SDQ, the data parities DP, the data flags DF and the flag parities FP by deinterleaving the codeword set SCW2bit-wisely, may generate decoded data flags by performing a first ECC decoding on the data flags DF based on the flag parities FP, may generate the decoded user data set D_SDQ by decoding the encoded user data set ESDQ based on the data parities DP and the decoded data flags.

The encoding circuit410may perform the first ECC encoding and the second ECC encoding based on the parity generation matrix PGM and the decoding circuit440may perform the first ECC decoding and the second ECC decoding based on the parity check matrix PCM.

FIG.7is a block diagram illustrating an example of the encoding circuit410in the error correction circuit ofFIG.6according to example embodiments.

Referring toFIG.7, the encoding circuit410may include a data duplicator415, an ECC encoder420, a flag encoder425and a bitwise interleaver430.

The data duplicator415may generate the encoded user data set E_SDQ by using at least one null data unit in which all or half of included data bits are zero, from among the plurality of data units of the user data set SDQ as a data duplication space. The data duplication space may be used for duplicating a valid data unit in which all or half of included data bits are valid, from among the plurality of data units, and the data duplicator415may provide the encoded user data set E_SDQ to the bitwise interleaver430.

The ECC encoder420may generate the data parities DP by performing a first ECC encoding on the plurality of data units of the user data set SDQ using the parity generation matrix PGM and may provide the data parities DP to the bitwise interleaver430.

The flag encoder425may generate the data flags DF based on the plurality of types of the plurality of data units of the user data set SDQ, may generate the flag parities FP by performing a second ECC encoding on the data flags DF using the parity generation matrix PGM and may provide the bitwise interleaver430with the data flags DF, the flag parities FP and the null bit NB including bits of ‘00’.

The bitwise interleaver430may generate the codeword set SCW1by interleaving the encoded user data set E_SDQ, the data parities DP, the data flags DF, the flag parities FP and the null bit NB bit-wisely.

When the user data set SDQ includes 512 bits, each of the plurality of data units of the user data set SDQ may include 64 bits, and the ECC encoder420may generate the data parities DP of 36 bits by performing the first ECC encoding on two data units of 128 bits to generate data parities of 9 bits. The flag encoder425may generate the data flags DF of 16 bits by generating data flags of 2 bits with respect to each of the plurality of data units, may generate the flag parities FP of 10 bits in total by generating the flag parities of 5 bits by performing the second ECC encoding on each of the data flags of 8 bits from among the data flags DF of 16 bits and adds the null bit NB of 2 bits. Therefore, the codeword set SCW1may include 576 bits.

FIG.8illustrates an example of the user data set inFIG.7according to some example embodiments.

Referring toFIG.8, the user data set SDQ may be divided (e.g., may be arranged) into a plurality of data units DU0, DU1, DU2, DU3, DU4, DU5, DU6and DU7.

As mentioned with reference toFIG.7, when the user data set SDQ includes 512 bits, each of the plurality of data units DU0, DU1, DU2, DU3, DU4, DU5, DU6and DU7includes 64 bits.

Each of the data units DU0, DU2, DU4, DU6, in which all of 64 data bits have a logic low level, may correspond to a zero value (ZV), the data unit DU5may include a first sub data unit SDU51including upper half 32 bits and a second sub data unit SDU52including lower half 32 bits, and a value SV1of the first sub data unit SDU51may be the same as a value SV2of the second sub data unit SDU52.

The data unit DU7may include a third sub data unit SDU71including upper half 32 bits and a fourth sub data unit SDU72including lower half 32 bits. All data bits of the third sub data unit SDU71have a logic low level and the first sub data unit SDU71may be denoted as sub-zero value (SZV). All data bits of the fourth sub data unit SDU72have valid values and the fourth sub data unit SDU72may be denoted as narrow width value (NWV).

Each of the data units DU1and DU3include 64 valid bits and each of the data units DU1and DU3may be denoted as full width value (FWV).

FIG.9is a table illustrating data flags based on characteristics of a plurality of data units.

Referring toFIG.9, in a table TB1, the data units DU0, DU1, DU5and DU7, a type and a data flag DF is shown.

The data unit DU0corresponding to the ZV may be identified to have a first type TY0, and the flag encoder425may assign a data flag DF of ‘01’ to the data unit DU0corresponding to the ZV. The data unit DU7corresponding to the NWV may be identified to have a second type TY1, and the flag encoder425may assign a data flag DF of ‘10’ to the data unit DU7corresponding to the zero value NWV. The data unit DU5corresponding to a same value SV may be identified to have a third type TY2, and the flag encoder425may assign a data flag DF of ‘11’ to the data unit DU5corresponding to the SV. The data unit DU1corresponding to the FWV may be identified to have a fourth type TY3, and the flag encoder425may assign a data flag DF of ‘00’ to the data unit DU1corresponding to the FWV.

The plurality of data units DU0, DU1, DU2, DU3, DU4, DU5, DU6and DU7may have a share in the order of the fourth type TY3, the first type TY0, the second type TY1and the third type TY2. The memory chip200aincludes DRAM cells and the DRAM cells may be divided into a true cell region and an anti cell region. In the true cell region, 0-errors in which a value of ‘1’ is incorrectly read as a value of ‘0’ is more dominant than 1-errors in which a value of ‘0’ is incorrectly read as a value of ‘1’. Therefore, the flag encoder425may reduce error occurrences by assigning the data flag DF of ‘00’ to the data unit having the fourth type TY3.

FIG.10is a flow chart illustrating an example operation of the encoding circuit ofFIG.7according to some example embodiments.

Referring toFIGS.7and10, the data duplicator415, in response to each of a first number of the data unit having the first type TY0and a second number of the data unit having the fourth type TY3being greater than zero, may generate the encoded user data set E_SDQ by duplicating at least a portion of the data units having the fourth type TY3in at least a portion of the data units having the first type TY0.

The encoding circuit410may divide a plurality of data bits of the user data set SDQ into a plurality of data units DU0-DU7(operation S110).

The flag encoder425may identify each of the plurality of data units DU0-DU7as one of first through fourth types TY0, TY1, TY2and TY3based on characteristic of the data bits of the each of the plurality of data units DU0-DU7(operation S120l).

The data duplicator415may determine whether a first number of the data unit having the first type TY0or a second number of the data unit having the fourth type TY3is zero (operation S130).

When the first number of the data unit having the first type TY0or the second number of the data unit having the fourth type TY3is zero (YES in S130), the data duplicator415may end duplication with duplicating nothing (e.g., without duplicating anything) (operation S140).

When each of the first number of the data unit having the first type TY0and the second number of the data unit having the fourth type TY3is not zero (YES in S130), the data duplicator415may determine whether the first number is equal to or greater than the second number (operation S150).

When the first number is equal to or greater than the second number (YES in S150), the data duplicator415may duplicate the data units having the fourth type TY3in the data units having the first type TY0as many as possible (operation S160). That is, data duplicator415may duplicate the data units having the fourth type TY3in a portion or all of the data units having the first type TY0.

When the first number is smaller than the second number (NO in S150), the data duplicator415may duplicate the data unit having the fourth type TY3in the data units having the first type TY0(operation S170). That is, the data duplicator415may duplicate at least one data unit corresponding to the first number, from among the data units having the fourth type, in the data unit having the first type.

FIG.11illustrates an example operation of the encoding circuit ofFIG.7according to some example embodiments.

InFIG.11, assuming that the user data set SDQ includes four data units DU0, DU2, DU4and DU6having the first type TY0, two data units DU1and DU3having the fourth type TY3, a data unit DU5having the third type TY2and a data unit DU7having the second type TY1. The data unit DU5having the third type TY2may include a first sub data unit SDU51and a second sub data unit SDU52and the data unit DU7having the second type TY1includes a third sub data unit SDU71and a fourth sub data unit SDU72.

The data duplicator415may generate a first duplicated data unit DUP_DU1by duplicating the data unit DU1having the fourth type TY3in the data unit DU0having the first type TY0as indicated by a reference numeral416, and may generate a second duplicated data unit DUP_DU3by duplicating the data unit DU3having the fourth type TY3in the data unit DU2having the first type TY0as indicated by a reference numeral417.

The data duplicator415, in response to a third number of the data unit DU7having the second type TY1being greater than zero, may generate a duplicated sub data unit DUP_SDU72by duplicating the fourth sub data unit SDU72of the data unit DU7having the second type TY1in the third sub data unit SDU71of the data unit DU7as indicated by a reference numeral418. Through above-mentioned process, the data duplicator415may generate the encoded user data set D_SDQ by duplicating a portion of the user data set SDQ.

The ECC encoder420, by using the parity generation matrix PGM, may generate a 9-bit data parity DP0by performing a first ECC encoding on the data units DU0and DU1, may generate a 9-bit data parity DP1by performing a first ECC encoding on the data units DU2and DU3, may generate a 9-bit data parity DP2by performing a first ECC encoding on the data units DU4and DU5and may generate a 9-bit data parity DP3by performing a first ECC encoding on the data units DU6and DU7.

The flag encoder425may assign each of 2-bit data flags DF0, DF1, DF2, DF3, DF4, DF5, DF6and DF7to respective one of the data units DU0, DU1, DU2, DU3, DU4, DU5, DU6and DU7, may generate 5-bit parity flag FP0by performing a second ECC encoding on the data flags DF0, DF1, DF2and DF3, may generate 5-bit parity flag FP1by performing a second ECC encoding on the data flags DF4, DF5, DF6and DF7and may add the null bit NB of 2-bit.

The bitwise interleaver430may generate the codeword set SCW1by interleaving the encoded user data set E_SDQ, the data parities DP0, DP1, DP2and DP3, the data flags DF0, DF1, DF2, DF3, DF4, DF5, DF6and DF7, the flag parities FP0and FP1and the null bit NB bit-wisely.

FIG.12is a block diagram illustrating an example of the encoding circuit in the error correction circuit ofFIG.6according to some example embodiments.

Referring toFIG.12, the decoding circuit440may include a bitwise deinterleaver450, a flag encoder455and a data correction circuit460.

The bitwise deinterleaver450may generate the encoded user data set E_SDQ, the data parities DP, the data flags DF and the flag parities FP by deinterleaving the codeword set SCW2bit-wisely, may provide the data flags DF and the flag parities FP to the flag decoder455, and may provide the encoded user data set E_SDQ and the data parities DP to the data correction circuit460.

The flag decoder455may generate decoded data flags D_DF by performing a first ECC decoding on the data flags DF based on the flag parities FP by using the parity check matrix PCM and may provide the decoded data flags D_DF to the data correction circuit460.

The data correction circuit460may generate a decoded user data set D_SDQ by decoding the encoded user data set E_SDQ based on the data parities DP and the decoded data flags D_DF.

The data correction circuit460may include a bitwise OR operator470, a data de-duplicator480and an ECC decoder490.

The bitwise OR operator470may generate an operation data set OP_SDQ by performing OR operation on the encoded user data set E_SDQ bit-wisely based on the decoded data flags D_DF. The data de-duplicator480may generate a recovered data set R_SDQ by eliminate duplications in the operation data set OP_SDQ based on the decoded data flags D_DF.

The ECC decoder490may generate the decoded user data set D_SDQ by performing a second ECC decoding on the recovered user data set R_SDQ based on the data parities DP by using the parity check matrix PCM.

When the codeword set SCW2includes 576 bits, the data flags DF and the flag parities FP include 26 bits, the data parities DP include 36 bits and the decoded data flags D_DF include 16 bits.

FIG.13illustrates example operations of the bitwise OR operator and the data de-duplicator in the decoding circuit ofFIG.12according to some example embodiments.

The bitwise OR operator470may include a plurality of OR gates471,472,473and474.

The OR gate471may generate a first operated data unit ORR OF DU1by performing OR operation on each of data bits of the data unit DU1having the fourth type TY3and respective one of data bits of the first duplicated data unit DUP_DU1, and the data de-duplicator480may recover the data unit DU0having the first type TY0by setting each of the data bits of the first duplicated data unit to a logic low level.

The OR gate472may generate a second operated data unit ORR OF DU3by performing OR operation on each of data bits of the data unit DU3having the fourth type TY3and respective one of data bits of the second duplicated data unit DUP_DU3, and the data de-duplicator480may recover the data unit DU2having the first type TY0by setting each of the data bits of the first duplicated data unit to a logic low level.

The OR gate473may generate a first sub operated data unit ORR OF SDU51and a second sub operated data unit ORR OF SDU52by performing OR operation on each of the upper half bits in the first sub data unit SDU51of the data unit DU5having the third type TY2and respective one of the lower half bits in the second sub data unit SDU51of the data unit DU5having the third type TY2.

The OR gate474may generate an operated sub data unit ORR OF SDU72by performing OR operation on each of lower half bits of the fourth sub data unit SDU72of the data unit having the second type TY1and respective one of data bits of a duplicated sub data unit DUP_SDU72obtained by duplicating the fourth sub data unit SDU72, and the data de-duplicator480may recover the third sub data unit SDU71by setting each of data bits of the duplicated sub data unit DUP_SDU72to a logic low level.

Each of the OR gates471,472,473and474may correct 0-error in which in which a value of ‘1’ is incorrectly read as a value of ‘0’ through bitwise OR operation. The ECC decoder490may correct 0-error which occurs in bits of same locations of an original data bit and a duplicated data bit through the second ECC decoding.

FIG.14illustrates an example operation of the decoding circuit ofFIG.12according to some example embodiments.

Referring toFIG.14, the codeword set SCW2received from the memory module MM may include the encoded user data set E_SDQ, the data parities DP, the data flags DF, the flag parities FP and the null bit NB which are bit-wisely interleaved.

When the flag decoder455performs the first ECC decoding, the decoded data flags D_DF may be generated as indicated by a reference numeral791, when the bitwise OR operator470and the data de-duplicator480, the recovered user data set R_SDQ may be generated as indicated by a reference numeral792, and when the ECC decoder490performs the second ECC decoding on the recovered user data set R_SDQ, the decoded user data set D_SDQ may be generated as indicated by a reference numeral793.

Accordingly, the error correction circuit130in the memory controller100may generate the encoded user data set by using at least one null data unit in which all or half of included data bits are zero, from among the plurality of data units as a data duplication space for duplicating a valid data unit in which all or half of included data bits are valid, from among the plurality of data units. The error correction circuit130may generate a codeword set by interleaving the encoded user data set, the data parities, the data flags, the flag parities and a null bit bit-wisely and may store the codeword set in the plurality of memory chips, and thus may correct errors occurring in one memory chip. In addition, the error correction circuit130may correct 0-error in which in which a value of ‘1’ is incorrectly read as a value of ‘0’ through bitwise OR operation and may correct 0-error which occurs in bits of same locations of an original data bit and a duplicated data bit through the second ECC decoding. Therefore, the error correction circuit130may correct 64-bit errors or 32-bit errors with respect to the duplicated data units without additional storage overhead and thus may enhance reliability of memory chips greatly.

FIG.15is a block diagram illustrating a memory module that may be employed by the memory system according to some example embodiments.

Referring toFIG.15, a memory module500may include a registered clock driver (RCD)590arranged in or mounted on a circuit board501, a plurality of semiconductor memory devices601a˜601e,602a˜602e,603a˜603d, and604a˜604d, a plurality of data buffers541˜545and551˜554, module resistance units560and570, a serial present detect (SPD) chip580, and a power management integrated circuit (PMIC)585.

The RCD590may control the semiconductor memory devices601a˜601e,602a˜602e,603a˜603d, and604a˜604dand the PMIC585under control of the memory controller100. For example, the RCD590may receive an address ADDR, a command CMD, and a clock signal CK from the memory controller100.

The SPD chip580may be a programmable read only memory (e.g., EEPROM). The SPD chip580may include initial information or device information DI of the memory module100. In some example embodiments, the SPD chip580may include the initial information or the device information DI such as a module form, a module configuration, a storage capacity, a module type, an execution environment, or the like of the memory module500.

When a memory system including the memory module500is booted up, the memory controller100may read the device information DI from the SPD chip580and may recognize the memory module500based on the device information DI. The memory controller100may control the memory module500based on the device information DI from the SPD chip580. For example, the memory controller100may recognize a type of the semiconductor memory devices included in the memory module500based on the device information DI from the SPD chip580.

Here, the circuit board501may be a printed circuit board, which may extend in a first direction D1, perpendicular to a second direction D2, between a first edge portion503and a second edge portion505. The first edge portion503and the second edge portion505may extend in the second direction D2.

The RCD590may be provided at a center of the circuit board501. The plurality of semiconductor memory devices601a˜601e,602a˜602e,603a˜603d, and604a˜604dmay be arranged in a plurality of rows between the RCD590and the first edge portion503and between the control device590and the second edge portion505.

In this case, the semiconductor memory devices601a˜601eand602a˜602emay be arranged along a plurality of rows between the RCD590and the first edge portion503. The semiconductor memory devices603a˜603d, and604a˜604dmay be arranged along a plurality of rows between the RCD590and the second edge portion505. The semiconductor memory devices601a˜601d,602a˜602d,603a˜603d, and604a˜604dmay be referred to data chips, and the semiconductor memory devices601eand602emay be referred to as first and second parity chips respectively.

Each of the plurality of semiconductor memory devices601a˜601e,602a˜602e,603a˜603d, and604a˜604dmay be coupled to a corresponding one of the data buffers541˜545and551˜554through a data transmission line for receiving/transmitting data signal DQ and data strobe signal DQS.

The RCD590may provide a command/address signal (e.g., CA) to the semiconductor memory devices601a˜601ethrough a command/address transmission line561and may provide a command/address signal to the semiconductor memory devices602a˜602ethrough a command/address transmission line563.

In addition, the RCD590may provide a command/address signal to the semiconductor memory devices603a˜603dthrough a command/address transmission line571and may provide a command/address signal to the semiconductor memory devices604a˜604dthrough a command/address transmission line573.

The command/address transmission lines561and563may be connected in common to a module resistance unit560(e.g., a first module resistance unit560) adjacent to the first edge portion503, and the command/address transmission lines571and573may be connected in common to a module resistance unit570(e.g., a second module resistance unit570) adjacent to the second edge portion505.

Each of the module resistance units560and570may include a termination resistor Rtt/2 connected to a termination voltage Vtt. In this case, an arrangement of the module resistance units560and570may reduce the number of the module resistance units, thus reducing an area where termination resistors are provided.

In addition, each of the plurality of semiconductor memory devices601a˜601e,602a˜602e,603a˜603d, and604a˜604dmay be a DRAM device.

The SPD chip580may be provided adjacent to the RCD590and the PMIC585may be between the semiconductor memory device603dand the second edge portion505. The PMIC585may generate a power supply voltage VDD based on an input voltage VIN and may provide the power supply voltage VDD to the semiconductor memory devices601a˜601e,602a˜602e,603a˜603d, and604a˜604d.

Although it is illustrated as the PMIC585is adjacent to the second edge portion505inFIG.15, the PMIC585may be provided in a central portion of the circuit board501to be adjacent to the RCD590in some example embodiments, or provided adjacent to the first edge portion503.

FIG.16is a block diagram illustrating a memory system having quad-rank memory modules according to some example embodiments.

Referring toFIG.16, a memory system700may include a memory controller710and at least one or more memory modules720and730.

The memory controller710may control the memory module720and/or the memory module730so as to perform a command supplied from a processor or host. The memory controller710may be implemented in a processor or host, or may be implemented with an application processor or a system-on-a-chip (SoC). The memory controller710may include a transmitter711configured to transmit a signal to the at least one or more memory modules720and730, and a receiver713configured to receive a signal from the at least one or more memory modules720and730. For signal integrity, a source termination may be implemented with a resistor RTT on a bus740of the memory controller710. The resistor RTT may be coupled to a power supply voltage VDDQ. The memory controller710may include an error correction circuit715and the error correction circuit715may employ the error correction circuit130ofFIG.6.

Therefore, the error correction circuit715may include an encoding circuit and a decoding circuit. The encoding circuit may generate an encoded user data set by using at least one null data unit in which all or half of included data bits are zero, from among the plurality of data units as a data duplication space for duplicating a valid data unit in which all or half of included data bits are valid, from among the plurality of data units, may generate a codeword set by interleaving the encoded user data set, the data parities, the data flags, the flag parities and a null bit bit-wisely and may store the codeword set in at least one of the one or memory modules720and730. The decoding circuit may correct errors by performing or operation on original data unit and duplicated data unit of the codeword set read from at least one of the one or memory modules720and730and may correct errors again based on single error correction and double error detection (SECDED) code.

The at least one or more memory modules720and730may be referred to as a first memory module720and a second memory module730. The first memory module720and the second memory module730may be coupled to the memory controller710through the bus740. Each of the first memory module720and the second memory modules730may correspond to the memory module MM inFIG.1. The first memory module720may include at least one or more memory ranks RK1and RK2, and the second memory module730may include one or more memory ranks RK3and RK4.

Each of the first memory module720and the second memory module730may include a plurality of memory chips.

FIG.17is a block diagram illustrating a mobile system including a memory module according to some example embodiments.

Referring toFIG.17, a mobile system800may include an application processor810, a connectivity module820, a memory module MM850, a nonvolatile memory device840, a user interface830, and a power supply870. The application processor810may include a memory controller (MCT)811. The memory controller811may include the system ECC engine130ofFIG.6.

The application processor810may execute applications, such as a web browser, a game application, a video player, or the like. The connectivity module820may perform wired or wireless communication with an external device.

The memory module850may store data processed by the application processor810or operate as a working memory. The memory module850may include a plurality of semiconductor memory devices MD851,852,853, and85r(where r is a positive integer greater than three), and a RCD861.

The semiconductor memory devices851,852,853, and85rmay include a plurality of memory chips. Therefore, the memory controller811may generate an encoded user data set by using at least one null data unit in which all or half of included data bits are zero, from among the plurality of data units as a data duplication space for duplicating a valid data unit in which all or half of included data bits are valid, from among the plurality of data units.

The nonvolatile memory device840may store a boot image for booting the mobile system800. The user interface830may include at least one input device, such as a keypad, a touch screen, etc., and at least one output device, such as a speaker, a display device, etc. The power supply870may supply an operating voltage to the mobile system800.

The mobile system800or components of the mobile system800may be mounted using various types of packages.

FIG.18is a block diagram illustrating a computing system according to some example embodiments.

Referring toFIG.18, a computing system30may include a plurality of hosts900a,900b, . . . ,900gand a memory system1000, and the memory system1000may include a memory controller1100and a memory module1200. Here, g is a natural number greater than two.

The memory module1200may include a plurality of data chips1210a˜1210k, a first parity chip1220and a second parity chip1230. The first parity chip1220and the second parity chip1230may be referred to as an ECC chip.

The memory controller1100may apply a command CMD and an address ADDR to the memory module1200, may exchange a codeword set SCW with the memory module1200.

The memory controller1100may include a processor1110and an error correction circuit1130.

The processor1110may control overall operation of the memory controller1100.

The error correction circuit1130may generate an encoded user data set by using at least one null data unit in which all or half of included data bits are zero, from among the plurality of data units as a data duplication space for duplicating a valid data unit in which all or half of included data bits are valid, from among the plurality of data units, may generate the codeword set SCW by interleaving the encoded user data set and may transmit the codeword set SCW to the memory module1200.

The memory controller1100may be connected to the plurality of hosts900a,900b, . . . ,900gthrough a compute express link (CXL) bus50, may control the plurality of data chips1210a˜1210k, the first parity chip1220and the second parity chip1230, and/or may communicate with the plurality of hosts900a,900b, . . . ,900gthrough the CXL interface.

In some embodiments, the CXL bus50may support a plurality of CXL protocols, and messages and/or data may be transmitted through the plurality of CXL protocols. For example, the plurality of CXL protocols may include a non-coherent protocol (or an I/O protocol CXL.io), a coherent protocol (or a cache protocol CXL.cache), and/or a memory access protocol (or a memory protocol CXL.memory). In some embodiments, the CXL bus50may support protocols such as peripheral component interconnection (PCI), PCI express (PCIe), universal serial bus (USB), and serial advanced technology attachment (SATA). A protocol supported by the CXL bus50may referred to as an interconnect protocol.

The memory controller1100may refer to a device that provides functions to the plurality hosts900a,900b, . . . ,900g. Based on the CXL specification 2.0, the memory controller1100may be an accelerator that supports the CXL specification. For example, at least some of computing operations and I/O operations executed in the plurality hosts900a,900b, . . . ,900gmay be off-loaded to the memory controller1100. In some embodiments, the each of the plurality hosts900a,900b, . . . ,900gmay include any one or any combination of a programmable component (e.g., a graphic processing unit (GPU), a neural processing unit (NPU), a component (e.g., an intellectual property (IP) core) that provides a fixed function, and/or a reconfigurable component (e.g., a field programmable gate array (FPGA)).

FIG.19is a block diagram illustrating one of the plurality hosts in the computing system ofFIG.18according to some example embodiments.

InFIG.19, a configuration of the host900afrom among the plurality hosts900a,900b, . . . ,900gand each configuration of the hosts900b, . . . ,900gmay be substantially the same as the configuration of the host900a.

Referring toFIG.19, the host900amay include a processor910and a host memory940.

The processor910may be a central processing unit (CPU) of the host900a. In some embodiments, the processor910may be a CXL-based processor. As illustrated inFIG.19, the processor910may be connected to the host memory940and may include a physical layer917, a multi-protocol multiplexer916, an interface circuit915, a coherence/cache circuit913, a bus circuit914, at least one core911, and an I/O device912.

The at least one core911may execute an instruction and may be connected to the coherence/cache circuit913. The coherence/cache circuit913may include a cache hierarchy and may be referred to as a coherence/cache logic. As illustrated inFIG.19, the coherence/cache circuit913may communicate with the at least one core911and interface circuit915. For example, the coherence/cache circuit913may enable communicate through at least protocols including a coherent protocol and a memory access protocol. In some embodiments, the coherence/cache circuit913may include a direct memory access (DMA) circuit. The I/O device912may be used to communicate with the bus circuit914. For example, the bus circuit914may be a PCIe logic and the I/O device912may be a PCIe I/O device.

The interface circuit915may enable communication between components (e.g., the coherence/cache circuit913and the bus circuit914) of the processor910and the memory system1000. In some embodiments, the interface circuit915may enable communication between components of the processor910and the memory system1000according to a plurality of protocols (e.g., the non-coherent protocols, the coherent protocols, and/or the memory access protocols discussed above). For example, the interface circuit915may determine one of the plurality of protocols based on messages and data for communication between the components of the processor910and the memory system1000.

The multi-protocol multiplexer916may include at least one protocol queue. The interface circuit915may be connected to the at least one protocol queue and may transmit and receive messages and/or data to and from the memory system1000through the least one protocol queue. In some embodiments, the interface circuit915and the multi-protocol multiplexer916may be integrally formed into one component. In some embodiments, the multi-protocol multiplexer916may include a plurality of protocol queues corresponding respectively to the plurality of protocols supported by the CXL bus50. In some embodiments, the multi-protocol multiplexer916may arbitrate communications of different protocols and provide selected communications the physical layer917.

FIG.20illustrates an example of a multi-protocol for communication in the computing system ofFIG.18.

Referring toFIG.20, the processor910and the memory controller1100may communicate with each other based on a plurality of protocols.

According to the above-mentioned CXL examples, the plurality of protocols may include a memory protocol MEM, a coherent protocol CACHE, and a non-coherent protocol IO. The memory protocol MEM may define a transaction from a master to a subordinate and a transaction from the subordinate to the master. The coherent protocol CACHE may define interactions between the memory controller1100and the processor910. For example, an interface of the coherent protocol CACHE may include three channels including a request, a response, and data. The non-coherent protocol IO may provide a non-coherent load/store for I/O devices.

The memory controller1100may communicate with the memory module1200and the processor910may communicate with the host memory940.

FIG.21is an example of a computing system when a memory system according to some example embodiments corresponds to a Type3memory system defined by a CXL protocol.

Referring toFIG.21, a computing system1300may include a root complex1310, a CXL memory expander1320connected to the root complex1310, and a memory resource1330.

The root complex1310may include a home agent1311and an I/O bridge1313, and the home agent1310may communicate with the CXL memory expander1320based on a coherent protocol CXL.mem. The I/O bridge1313may communicate with the CXL memory expander1320based on a non-coherent protocol, e.g., an I/O protocol CXL.io. In a CXL protocol base, the home agent1310may correspond to an agent on a host side that is arranged to solve the entire consistency of the computing system1300for a given address.

The CXL memory expander1320may include a memory controller1321and the memory controller1321may employ the memory controller1100inFIG.18.

In addition, the CXL memory expander1320may output data to the root complex1310via the I/O bridge1313based on the I/O protocol CXL.io or the PCIe.

The memory resource1330may include a plurality of memory regions MR1, MR2, . . . , MRt, and each of the plurality of memory regions MR1, MR2, . . . , MRt may be implemented as a memory of a various units.

FIG.22is a block diagram illustrating a data center including a computing system according to some example embodiments.

Referring toFIG.22, a data center2000may be a facility that collects various types of data and provides various services, and may be referred to as a data storage center. The data center2000may be a system for operating search engines and databases, and/or may be a computing system used by companies, such as banks, or used by government agencies. The data center2000may include application servers2100_1to2100_U and storage servers2200_1to2200_V. The number of the application servers2100_1to2100_U and the number of the storage servers2200_1to2200_V may be variously selected according to some example embodiments, and the number of the application servers2100_1to2100_U and the number of the storage servers2200_1to2200_V m may be different from each other.

Below, for convenience of description, an example of the storage server2200_1will be described.

The storage server2200_1may include a processor2210_1, a memory2220_1, a switch2230_1, a network interface controller (NIC)2240_1, a storage device2250_1and CXL interface2260_1. The storage server2200_V may include a processor2210_v, a memory2220_v, a switch2230_v, a NIC2240_v, a storage device2250_vand CXL interface2260_v.

The processor2210_1may control overall operation of the storage server2200_1. The memory2220_1may store various instructions or data under control of the processor2210_1. The processor2210_1may be configured to access the memory2220_1to execute various instructions or to process data. In some embodiments, the memory2220_1may include at least one of various kind of memory devices such as double data rate synchronous DRAM (DDR SDRAM), high bandwidth memory (HBM), hybrid memory cube (HMC), dual in-line memory module (DIMM), Optane DIMM, and/or non-volatile DIMM.

In some embodiments, the number of the processors2210_1included in the storage server2200_1and the number of the memories2220_1included in the storage server2200_1may be variously changed or modified. In some embodiments, the processor2210_1and the memory2220_1included in the storage server2200_1may constitute a processor-memory pair and the number of processor-memory pairs included in the storage server2200_1maybe variously changed or modified. In some embodiments, the number of the processors2210_1included in the storage server2200_1and the number of the memories2220_1included in the storage server2200_1may be different. The processor2210_1may include a single core processor and a multi-core processor.

Under control of the processor2210_1, the switch2230_1may selectively connect the processor2210_1and the storage device2250_1or may selectively connect the NIC2240_1, the storage device2250_1and the CXL2260_1.

The NIC2240_1may connect the storage server2200_1with a network NT. The NIC2240_1may include a network interface card, a network adapter, or the like. The NIC2240_1may be connected to the network NT through a wired interface, a wireless interface, a Bluetooth interface, or an optical interface. The NIC2240_1may include an internal memory, a digital signal processor (DSP), a host bus interface, or the like, and may be connected with the processor2210_1or the switch2230_1through the host bus interface. The host bus interface may include at least one of various interface schemes such as an advanced technology attachment (ATA), a serial ATA (SATA) an external SATA (e-SATA), a small computer system interface (SCSI), a serial attached SCSI (SAS), a peripheral component interconnection (PCI), a PCI express (PCIe), an NVMe, a compute express link (CXL), an IEEE 1394, a universal serial bus (USB), a secure digital (SD) card interface, a multi-media card (MMC) interface, an embedded MMC (eMMC) interface, a universal flash storage (UFS) interface, an embedded UFS (eUFS) interface, a compact flash (CF) card interface, or the like. In some embodiments, the NIC2240_1may be integrated with at least one of the processor2210_1, the switch2230_1and the storage device2250_1.

Under control of the processor2210_1, the storage device2250_1may store data or may output the stored data. The storage device2250_1may include a controller CTRL2251_1, a nonvolatile memory NAND2252_1, a DRAM2253_1and an interface I/F2254_1. In some embodiments, the storage device2250_1may further include a secure element SE for security or privacy. The storage device2250_vmay include a controller CTRL2251_v, a nonvolatile memory NAND2252_v, a DRAM2253_vand an interface I/F2254_v. In some embodiments, the storage device2250_vmay further include a secure element SE for security or privacy.

The controller2251_1may control overall operation of the storage device2250_1. The controller2251_1may include an SRAM. In response to signals received through the interface2254_1, the controller2251_1may store data in the nonvolatile memory2252_1or may output data stored in the nonvolatile memory2252_1. The controller2251_1may be configured to control the nonvolatile memory2252_1based on a toggle interface or an ONFI.

The DRAM2253_1may be configured to temporarily store data to be stored in the nonvolatile memory2252_1and/or data read from the nonvolatile memory2252_1. The DRAM2253_1may be configured to store various data (e.g., metadata and mapping data) used in operation of the controller2251_1. The interface2254_1may provide a physical connection between the controller2251_1and the processor2210_1, the switch2230_1, or the NIC2240_1. The interface2254_1may be implemented to support direct-attached storage (DAS) manner that allows the direct connection of the storage device2250_1through a dedicated cable. The interface2254_1may be implemented based on at least one of various above-described interfaces through a host interface bus.

The above components of the storage server2200_1are provided as an example, and the present disclosure is not limited thereto. The above components of the storage server2200_1may be applied to each of the other storage servers or each of the application servers2100_1to2100_U. In each of the application servers2100_1to2100_U, a storage device2150_1may be selectively omitted.

The application server2100_1may include a processor2110_1, a memory2120_1, a switch2130_1, a NIC2140_1, and CXL interface2160_1. The application server2100_U may include a processor2110_u, a memory2120_u, a switch2130_u, a NIC2140_u, and CXL interface2160_u.

The application servers2100_1to2100_U and the storage servers2200_1to2200_V may communicate with each other through the network NT. The network NT may be implemented using a fiber channel (FC) or an Ethernet. The FC may be a medium used for a relatively high-speed data transmission, and an optical switch that provides high performance and/or high availability may be used. The storage servers2200_1to2200_V may be provided as file storages, block storages or object storages according to an access scheme of the network NT.

In some example embodiments, the network NT may be a storage-only network or a network dedicated to a storage such as a storage area network (SAN). For example, the SAN may be an FC-SAN that uses an FC network and is implemented according to an FC protocol (FCP). For another example, the SAN may be an IP-SAN that uses a transmission control protocol/internet protocol (TCP/IP) network and is implemented according to an iSCSI (a SCSI over TCP/IP or an Internet SCSI) protocol. In other example embodiments, the network NT may be a general network such as the TCP/IP network. For example, the network NT may be implemented according to at least one of protocols such as an FC over Ethernet (FCoE), a network attached storage (NAS), a nonvolatile memory express (NVMe) over Fabrics (NVMe-oF), etc.

In some example embodiments, at least one of the plurality of application servers2100_1to2100_U may be configured to access at least one of the remaining application servers or at least one of the storage servers2200_1to2200_V over the network NT.

For example, the application server2100_1may store data requested by s user or a client in at least one of the storage servers2200_1to2200_V over the network NT. Alternatively, the application server2100_1may obtain data requested by a user or a client in at least one of the storage servers2200_1to2200_V over the network NT. In this case, the application server2100_1may be implemented with a web server, a database management system (DBMS), or the like.

The application server2100_1may access a memory2120_1or a storage device2150_1of the application server2100_1or the storage device2250_1of the storage server2200_1over the network NT. As such, the application server2100_1may perform various operations on data stored in the application servers2100_1to2100_U and/or the storage servers2200_1to2200_V. For example, the application server2100_1may execute a command for moving or copying data between the application servers2100_1to2100_U and/or the storage servers2200_1to2200_V. The data may be transferred from the storage devices2250_1to2250_vof the storage servers2200_1to2200_V to the memories2120_1to2120_uof the application servers2100_1to2100_U directly or through the memories2220_1to2220_vof the storage servers2200_1to2200_V. For example, the data transferred through the network NT may be encrypted data for security or privacy.

The storage servers2200_1to2200_V and the application servers2100_1to2100_U may be connected with a memory expander2300through the CXL interfaces2260_1to2260_vand2160_1to2160_u. The memory expander2300may be used as expanded memory of each of the storage servers2200_1to2200_V and the application servers2100_1to2100_U, and/or a virtualized component included therein may communicate with each other through the CXL interfaces2260_1to2260_vand2160_1to2160_uand the memory expander2300.

The present disclosure may be applied to various electronic devices and systems that include memory modules and memory systems. For example, the present disclosure may be applied to systems such as a personal computer (PC), a server computer, a data center, a workstation, a mobile phone, a smart phone, a tablet computer, a laptop computer, a personal digital assistant (PDA), a portable multimedia player (PMP), a digital camera, a portable game console, a music player, a camcorder, a video player, a navigation device, a wearable device, an internet of things (IoT) device, an internet of everything (IoE) device, an e-book reader, a virtual reality (VR) device, an augmented reality (AR) device, a robotic device, a drone, and so on.

While the present disclosure has been particularly shown and described with reference to some examples of embodiments thereof, it will be understood by those of ordinary skill in the art that various changes in form and detail may be made therein without departing from the scope of the present disclosure as defined by the following claims.