Patent ID: 12198747

DETAILED DESCRIPTION

Various embodiments of the present invention will be described below in more detail with reference to the accompanying drawings. The present invention may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present invention to those skilled in the art. Throughout this disclosure, like reference numerals refer to like parts throughout the various figures and embodiments of the present invention.

FIG.2is a block diagram illustrating a memory200in accordance with an embodiment of the present invention.

Referring toFIG.2, the memory200may include a command address receiving circuit201, a data transferring/receiving circuit203, a command decoder210, an address control circuit220, a self-refresh control circuit231, a refresh address generating circuit233, a target row collecting circuit235, a row active signal generating circuit240, an address selecting circuit251, a refresh flag generating circuit253, a cell array260, a row circuit270, and a column circuit280.

The command address receiving circuit201may receive a command/address signal CA. Depending on the type of memory200, a command and an address may be input to the same input terminal, or a command and an address may be input to separate input terminals. In this case, it is described that the command and the address are input to the same input terminal. The command/address signal CA may be of multiple bits.

The data transferring/receiving circuit203may receive data DATA or transfer data DATA. The data transferring/receiving circuit203may receive data DATA to be written into the cell array260during a write operation, and transfer the data DATA that are read from the cell array260during a read operation.

The command decoder210may decode the command/address signal CA to determine the type of an operation directed by a memory controller to the memory200. An active signal ACT may be a signal that is activated when an active operation is directed, and a precharge signal PCG may be a signal that is activated when a precharge operation is directed. A refresh signal REF may be a signal that is activated when an (auto) refresh operation is directed. Also, a write signal WR may be a signal that is activated when a write operation is directed, and a read signal RD may be a signal that is activated when a read operation is directed. A smart refresh signal SMART_REF may be a signal that is activated when a smart refresh operation is directed. A command directing a smart refresh operation may also be referred to as a refresh management (RFM) command.

The address control circuit220may classify the address received from the command decoder210as a row address R_ADD or a column address C_ADD. The address control circuit220may classify an address as a row address R_ADD when an active operation is directed as a result of the decoding by the command decoder210, and may classify the address as a column address C_ADD when a read or write operation is directed.

The self-refresh control circuit231may activate a self-refresh signal SREF periodically in a self-refresh mode. The self-refresh mode may be set by the command decoder210that receives a direction from the memory controller.

The refresh address generating circuit233may generate a refresh address REF_ADD to be used for a refresh operation. Since only a row address is used during a refresh operation, the refresh address REF_ADD may be a row address. The refresh address REF_ADD may be used for an auto-refresh operation and a self-refresh operation. Whenever the auto-refresh operation or the self-refresh operation is performed, that is, whenever the refresh signal REF or the self-refresh signal SREF is activated, the refresh address REF_ADD may be changed so that the rows of the cell array260may be sequentially refreshed.

The target row collecting circuit235may collect information about a row in which data are highly likely to be lost due to row hammering among the rows of the cell array260, which is referred to as a target row, and may provide a target row address TARGET_R_ADD. The target row collecting circuit235may select a row which is adjacent to a row that has been activated excessively many times as a target row. A target row may be selected using a combination of various methods, such as a method of counting the number of times that the rows of the cell array260are activated and a method of randomly sampling the rows that are activated in the cell array260. The target row collecting circuit235may monitor the activation of the rows of the cell array260based on the active signal ACT and the row address R_ADD.

The row active signal generating circuit240may generate a row active signal RACT for controlling active and precharge operations. When the row active signal RACT is activated, a row selected based on the address R_ADD_SEL which is selected by the address selecting circuit251among the rows of the cell array260may be activated, and when the row active signal RACT is deactivated, the activated row may be precharged.

The row active signal generating circuit240may activate the row active signal RACT when the active signal ACT is activated, and deactivates the row active signal RACT when the precharge signal PCG is activated. That is, the selected row of the cell array260may be activated in response to an active command and precharged in response to a precharge command.

Also, the row active signal generating circuit240may activate and deactivate the active row signal RACT in response to the refresh signals REF, SREF, and SMART_REF. When one among the refresh signals REF, SREF, and SMART_REF is activated, the row active signal generating circuit240may activate the row active signal RACT and deactivate it after a predetermined time. For example, the row active signal generating circuit240may activate the row active signal RACT in response to the activation of the self-refresh signal SREF and deactivate the row active signal RACT after a predetermined time passes.

The address selecting circuit251may select one among the row address R_ADD, the refresh address REF_ADD, and the target row address TARGET_R_ADD and transfer the selected address to the row circuit270. The address selecting circuit251may select and output the row address R_ADD during an active operation based on the active signal ACT, that is, when all of the refresh signals REF, SREF, and SMART_REF are deactivated. The address selecting circuit251may select and output the refresh address REF_ADD during an auto-refresh operation and/or a self-refresh operation, that is, when one among the refresh signal REF and the self-refresh signal SREF is activated. Also, the address selecting circuit251may select and output the target row address TARGET_R_ADD during a smart refresh operation, that is, when the smart refresh signal SMART_REF is activated.

The refresh flag generating circuit253may generate a refresh flag REF_FLAG representing that a refresh operation is being performed. The refresh flag generating circuit253may activate the refresh flag signal REF_FLAG when one among the refresh signals REF, SREF, and SMART_REF is activated, and maintains the refresh flag signal REF_FLAG in an activated state during a refresh operation period.

The cell array260may include a plurality of word lines (e.g., row lines) and a plurality of bit lines (e.g., column lines) and a plurality of memory cells provided at intersections between the word lines and the bit lines. Each of the memory cells may include a transistor which is controlled by a corresponding word line, and a capacitor for storing data that are input/output through a corresponding bit line.

The row circuit270may control a row operation of the cell array260. When the row active signal RACT is activated, the row circuit may activate a word line corresponding to the address R_ADD_SEL which is selected by the address selecting circuit251among a plurality of word lines, and when the row active signal RACT is deactivated, the row circuit270may precharge (deactivate) the activated word line.

As described above, when a word line is activated and then precharged (deactivated), that is, when a word line toggles, the data of the memory cells that are coupled to the word lines positioned adjacent to the toggling word line may be deteriorated due to the coupling effect. This phenomenon is called row hammering. As one method for reducing the effect of row hammering, a soft-landing method may be used. Soft landing means reducing the row hammering effect by slowing the precharge when a word line is precharged, or by keeping the word line at an intermediate voltage level for a predetermined time before being discharged from the active voltage level to an inactive voltage level.

A word line may be precharged even when a word line is activated based on an active command and then precharged based on the precharge command, but a word line may also be precharged during a refresh operation. In the former case, since row hammering may become a problem, a soft-landing operation may be essential during the precharging. However, in the latter case, since it is just an operation to reduce the row hammering, the soft-landing operation may not be essential. For example, during a refresh operation, after a third word line is active precharged, a fourth word line may be active precharged, and a fifth word line may be active precharged. However, since the memory cells of the third word line and the fifth word line are refreshed at a moment when the fourth word line toggles, there is no need to worry about row hammering. Considering this point, the row circuit270may be able to control the soft-landing differently in the word line precharge operation that is performed based on the precharge command and the word line precharge operation that is performed during a refresh operation. That is, the row circuit270may be able to make the voltage waveforms of the process of discharging the activated word line to the precharge voltage level to be different when the refresh flag REF_FLAG is deactivated and when the refresh flag REF_FLAG is activated.

The column circuit280may control a column operation of the cell array260. When the read signal RD is activated, the column circuit280may read data from the bit lines corresponding to the column address C_ADD and transfer the read data to the data transferring/receiving circuit203. When the read signal RD is activated, data may be read from the memory cells coupled to the bit lines that are selected based on the column address C_ADD among the memory cells coupled to the word line selected based on the row address R_ADD, and transferred to the data transferring/receiving circuit203. When the write signal WR is activated, the column circuit280may transfer the data transferred from the data transferring/receiving circuit203to the bit lines corresponding to the column address C_ADD so that the data may be written. Namely, when the write signal WR is activated, the data received by the data transferring/receiving circuit203may be written into the memory cells coupled to the bit lines selected based on the column address C_ADD among the memory cells coupled to the word line which is selected based on the row address R_ADD.

FIG.3is a detailed block diagram illustrating the row circuit270shown inFIG.2in accordance with an embodiment of the present invention.

Referring toFIG.3, the row circuit270may include a decoder circuit310and word line drivers320_0to320_511.

The decoder circuit310may use the row active signal RACT and the address R_ADD_SEL which is selected by the address selecting circuit251to generate control signals MWLB<0:63>, FX<0:7>, and FXB<0:7> for enabling a word line corresponding to the selected address R_ADD_SEL among the word lines WL<0:511> to be activated and pre-charged based on the row active signal RACT. It is illustrated that there are 64 main word line signals MWLB<0:63> and 8 first FIAX signals FX<0:7> and 8 second FIAX signals FXB<0:7> among the control signals MWLB<0:63>, FX<0:7>, and FXB<0:7>. With the combinations of 64*8, it may be possible to control the activation and deactivation of the 512 word lines WL<0:511>.

The following Table 1 shows the control signals MWLB<0:63>, FX<0:7>, and FXB<0:7> involving in the activation and deactivation of the word lines WL<0:511>.

TABLE 1WL<0>MWLB<0>FX<0>, FXB<0>WL<1>MWLB<0>FX<1>, FXB<1>WL<2>MWLB<0>FX<2>, FXB<2>WL<3>MWLB<0>FX<3>, FXB<3>WL<4>MWLB<0>FX<4>, FXB<4>WL<5>MWLB<0>FX<5>, FXB<5>WL<6>MWLB<0>FX<6>, FXB<6>WL<7>MWLB<0>FX<7>, FXB<7>WL<8>MWLB<1>FX<0>, FXB<0>WL<9>MWLB<1>FX<1>, FXB<1>WL<10>MWLB<1>FX<2>, FXB<2>WL<11>MWLB<1>FX<3>, FXB<3>WL<12>MWLB<1>FX<4>, FXB<4>WL<13>MWLB<1>FX<5>, FXB<5>WL<14>MWLB<1>FX<6>, FXB<6>WL<15>MWLB<1>FX<7>, FXB<7>WL<16>MWLB<2>FX<0>, FXB<0>WL<17>MWLB<2>FX<1>, FXB<1>. . .. . .. . .WL<510>MWLB<63>FX<6>, FXB<6>WL<511>MWLB<63>FX<7>, FXB<7>

Referring to Table 1, it may be seen that the activation and deactivation of the word line WL<3> may be controlled based on the main word line signal MWLB<0>, the first FIAX signal FX<3>, and the second FIAX signal FXB<3>, and the activation and deactivation of the word line WL<17> may be controlled based on the main word line signal MWLB<2>, the first FIAX signal FX<1> and the second FIAX signal FXB<1>. Herein, it is illustrated that the number of the word lines WL<0:511> is 512, and the number of the main word line signals MWLB<0:63> is 64, and the number of the first FIAX signals FX<0:7> and the number of the second FIAX signals FXB<0:7> are 8. However, it is obvious to those skilled in the art that the number of the word lines and those signals may be different from this example.

The word line drivers320_0to320_511may drive the word lines WL<0:511> in response to the control signals MWLB<0:63>, FX<0:7>, and FXB<0:7>. Table 1 shows the control signals MWLB<0:63>, FX<0:7>, and FXB<0:7> that are used by the word line drivers320_0to320_511. For example, the word line driver320_3may drive the word line WL<3> in response to the main word line signal MWLB<0>, the first FIAX signal FX<3>, and the second FIAX signal FXB<3>.

FIG.4is a detailed block diagram illustrating a word line driver320_kshown inFIG.3in accordance with an embodiment of the present invention.

Referring toFIG.4, the word line driver320_kmay include a PMOS transistor401and NMOS transistors403and405. InFIG.4, i may be an arbitrary integer of 0 to 63, and j may be an arbitrary integer of 0 to 7, and k may be an arbitrary integer of 0 to 511.

The PMOS transistor401may drive a word line WL<k> to the voltage level of the first FIAX signal FX<j> in response to the main word line signal MWLB<i>. The NMOS transistor403may drive the word line WL<k> to the precharge voltage level VBBW in response to the main word line signal MWLB<i>. Also, the NMOS transistor405may drive the word line WL<k> to the precharge voltage level VBBW in response to the second FIAX signal FXB<j>.

Referring toFIGS.5to8, various embodiments in which the word line driver320_kactivates and precharges the word line WL<k> will be described. Hereinafter, the word line WL<k> is selected based on the selected address R_ADD_SEL. In this case, the main word line signal MWLB that does not correspond to the word line WL<k> may maintain a high level, and the first FIAX signal FX that does not correspond to the word line WL<k> may maintain a low level, and the second FIAX signal FXB that does not correspond to the word line WL<k> may maintain a high level. For example, when the word line WL<k> is the word line WL<10>, the main word line signals MWLB<0> and MWLB<2:63> may maintain a high level, and the first FIAX signals FX<0:1> and FX<3:7> may maintain a low level, and the second FIAX signals FXB<0:1> and FXB<3:7> may maintain a high level. Accordingly, the word lines WL<0:9> and WL<11:511> other than the word line WL<10> may maintain the precharged state.

FIG.5is a timing diagram for describing an operation of the word line driver320_kin accordance with a first embodiment of the present invention.

InFIG.5, (a) is a timing diagram for describing an operation of the word line driver320_kwhen the word line driver320_kactivates and precharges the word line WL<k> in response to an active command and a precharge command. That is, (a) ofFIG.5shows the operation of the word line driver320_kwhen the refresh flag REF_FLAG is deactivated.

Referring to (a) ofFIG.5, an active operation may begin at a moment501. At the moment501, the main word line signal MWLB<i> may transition from a high level to a low level, and the first FIAX signal FX<j> may transition from a low level to a high level, and the second FIAX signal FXB<j> may transition from a high level to a low level. Accordingly, the PMOS transistor401of the word line driver320_kmay be turned on, and the PMOS transistor401which is turned on may activate the word line WL<k> to an active voltage level VPP.

A precharge operation may begin at a moment503. At the moment503, the first FIAX signal FX<j> may transition from a high level to a low level. Also, the second FIAX signal FXB<j> may transition from a low level to a high level at the moment503and may be maintained until a moment505. The NMOS transistor405of the word line driver320_kmay be turned on from the moment503to the moment505to pull-down drive the word line WL<k>, and the word line WL<k> may be discharged to an intermediate voltage level VSL. Herein, the intermediate voltage level VSL may be a voltage level which is lower than the active voltage level VPP and higher than the precharge voltage level VBBW. At the moment505, since the second FIAX signal FXB<j> transitions from a high level to a low level, the NMOS transistor405may be turned off, and the voltage level of the word line WL<k> may be maintained at the intermediate voltage level VSL until a moment507. At a moment507, since the main word line signal MWLB<i> transitions to a high level and the second FIAX signal FXB<j> transitions to a high level, the NMOS transistors403and405may be turned on and the word line WL<k> may be discharged to the precharge voltage level VBBW.

InFIG.5, (b) is a timing diagram for describing an operation of the word line driver320_kwhen the word line driver320_kactivates and precharges the word line WL<k> during a refresh operation. That is, (b) ofFIG.5shows the operation of the word line driver320_kwhen the refresh flag REF_FLAG is activated.

Referring to (b) ofFIG.5, an active operation may begin at a moment501. At the moment501, the main word line signal MWLB<i> may transition from a high level to a low level, and the first FIAX signal FX<j> may transition from a low level to a high level, and the second FIAX signal FXB<j> may transition from a high level to a low level. Accordingly, the PMOS transistor401of the word line driver320_kmay be turned on, and the PMOS transistor401which is turned on may activate the word line WL<k> to the active voltage level VPP.

A precharge operation may begin at a moment503. At the moment503, the main word line signal MWLB<i> may transition to a high level, and the first FIAX signal FX<j> may transition to a low level, and the second FIAX signal FXB<j> may transition to a high level. Accordingly, the PMOS transistor401may be turned off, and the NMOS transistors403and405may be turned on so that the word line WL<k> may be precharged to the precharge voltage level VBBW.

Referring to (a) ofFIG.5, it may be seen that during a precharge operation which is performed in response to a precharge command, the word line WL<k> may be discharged from the active voltage level VPP to the intermediate voltage level VSL, maintained at the intermediate voltage level VSL for a predetermined time, and then discharged to the precharge voltage level VBBW. In this case, it may be seen that a soft-landing operation may be performed. However, it may be seen that during the precharge operation which is performed during the refresh operation of (b) ofFIG.5, the word line WL<k> is directly discharged from the active voltage level VPP to the precharge voltage level VBBW. In this case, it may be seen that a soft-landing operation may not be performed.

Referring to (a) and (b) ofFIG.5, it may be seen that the waveform of the process of precharging the word line WL<k> based on the precharge command and the waveform of the process of precharging the word line WL<k> during a refresh operation may be different from each other.

FIG.6is a timing diagram for describing an operation of the word line driver320_kin accordance with a second embodiment of the present invention.

InFIG.6, (a) is a timing diagram for describing an operation of the word line driver320_kwhen the word line driver320_kactivates and precharges the word line WL<k> in response to the active command and the precharge command. That is, (a) ofFIG.6shows the operation of the word line driver320_kwhen the refresh flag REF_FLAG is deactivated.

Referring to (a) ofFIG.6, an active operation may begin at a moment601. At the moment601, the main word line signal MWLB<i> may transition from a high level to a low level, and the first FIAX signal FX<j> may transition from a low level to a high level, and the second FIAX signal FXB<j> may transition from a high level to a low level. Accordingly, the PMOS transistor401of the word line driver320_kmay be turned on, and the PMOS transistor401which is turned on may activate the word line WL<k> to the active voltage level VPP.

A precharge operation may begin at a moment603, and the first FIAX signal FX<j> may transition from a high level to a low level. At the moment603, the second FIAX signal FXB<j> may transition from a low level to a high level and may be maintained until a moment605. The NMOS transistor405of the word line driver320_kmay be turned on from the moment603to the moment605to pull-down drive the word line WL<k>, and the word line WL<k> may be discharged to the intermediate voltage level VSL. Herein, the intermediate voltage level VSL may be a level which is lower than the active voltage level VPP and higher than the precharge voltage level VBBW. At the moment605, since the second FIAX signal FXB<j> transitions from a high level to a low level, the NMOS transistor405may be turned off, and the voltage level of the word line WL<k> may be maintained at the intermediate voltage level VSL until a moment607. At the moment607, since the main word line signal MWLB<1> transitions to a high level and the second FIAX signal FXB<j> transitions to a high level, the NMOS transistors403and405may be turned on and the word line WL<k> may be discharged to the precharge voltage level VBBW.

InFIG.6, (b) is a timing diagram for describing an operation of the word line driver320_kwhen the word line driver320_kactivates and precharges the word line WL<k> during a refresh operation. That is, (b) ofFIG.6shows the operation of the word line driver320_kwhen the refresh flag REF_FLAG is activated.

Referring to (b) ofFIG.6, an active operation may begin at a moment601. At the moment601, the main word line signal MWLB<i> may transition from a high level to a low level, and the first FIAX signal FX<j> may transition from a low level to a high level, and the second FIAX signal FXB<j> may transition from a high level to a low level. Accordingly, the PMOS transistor401of the word line driver320_kmay be turned on, and the PMOS transistor401which is turned on may activate the word line WL<k> to the active voltage level VPP.

A precharge operation may begin at a moment603, and the first FIAX signal FX<j> may transition from a high level to a low level. At the moment603, the second FIAX signal FXB<j> may transition from a low level to a high level and may be maintained until a moment605. The NMOS transistor405of the word line driver320_kmay be turned on from the moment603to the moment605to pull-down drive the word line WL<k>, and the word line WL<k> may be discharged to the intermediate voltage level VSL. At the moment605, since the second FIAX signal FXB<j> transitions from a high level to a low level, the NMOS transistor405may be turned off, and the voltage level of the word line WL<k> may be maintained at the intermediate voltage level VSL until a moment606. At the moment606, since the main word line signal MWLB<i> transitions to a high level and the second FIAX signal FXB<j> transitions to a high level, the NMOS transistors403and405may be turned on and the word line WL<k> may be discharged to the precharge voltage level VBBW.

Referring to (a) ofFIG.6, it may be seen that during a precharge operation which is performed in response to the precharge command, the word line WL<k> may be discharged from the active voltage level VPP to the intermediate voltage level VSL, maintained at the intermediate voltage level VSL for a predetermined time, and then discharged to the precharge voltage level VBBW. Also, it may be seen that during the precharge operation which is performed during the refresh operation of (b) ofFIG.6, the word line WL<k> may be discharged from the active voltage VPP to the intermediate voltage level VSL, maintained at the intermediate voltage level VSL for a predetermined time, and then discharged to the precharge voltage level VBBW.

However, it may be seen from (a) ofFIG.6that the word line WL<k> may maintain the intermediate voltage level VSL from the moment605to the moment607, but it may be seen from (b) ofFIG.6that the word line WL<k> may maintain the intermediate voltage level VSL from the moment605to the moment606(that is, for a shorter time than that of (a) ofFIG.6). In the case of (a) ofFIG.6, the soft-landing operation may be performed more actively than that of (b) ofFIG.6, and it may be seen that the waveforms of the process of precharging the word line WL<k> in the two cases are different from each other.

FIG.7is a timing diagram for describing an operation of the word line driver320_kin accordance with a third embodiment of the present invention.

InFIG.7, (a) is a timing diagram for describing an operation of the word line driver320_kwhen the word line driver320_kactivates and precharges the word line WL<k> in response to the active command and the precharge command. That is, (a) ofFIG.7shows the operation of the word line driver320_kwhen the refresh flag REF_FLAG is deactivated.

Referring to (a) ofFIG.7, an active operation may begin at a moment701. At the moment701, the main word line signal MWLB<i> may transition from a high level to a low level, and the first FIAX signal FX<j> may transition from a low level to a high level, and the second FIAX signal FXB<j> may transition from a high level to a low level. Accordingly, the PMOS transistor401of the word line driver320_kmay be turned on, and the PMOS transistor401which is turned on may activate the word line WL<k> to the active voltage level VPP.

A precharge operation may begin at a moment703, and the first FIAX signal FX<j> may transition from a high level to a low level. Also, the second FIAX signal FXB<j> may transition from a low level to a high level at the moment703and may be maintained until a moment705. The NMOS transistor405of the word line driver320_kmay be turned on from the moment703to the moment705to pull-down drive the word line WL<k>, and the word line WL<k> may be discharged to a first intermediate voltage level VSL1. Herein, the first intermediate voltage level VSL1may be a voltage level which is lower than the level of the active voltage VPP and higher than the precharge voltage level VBBW. At the moment705, since the second FIAX signal FXB<j> transitions from a high level to a low level, the NMOS transistor405may be turned off, and the voltage level of the word line WL<k> may be maintained at the first intermediate voltage level VSL1until a moment707. At the moment707, since the main word line signal MWLB<i> transitions to a high level and the second FIAX signal FXB<j> transitions to a high level, the NMOS transistors403and405may be turned on and the word line WL<k> may be discharged to the precharge voltage level VBBW.

InFIG.7, (b) is a timing diagram for describing an operation of the word line driver320_kwhen the word line driver320_kactivates and precharges the word line WL<k> during a refresh operation. That is, (b) ofFIG.7shows the operation of the word line driver320_kwhen the refresh flag REF_FLAG is activated.

Referring to (b) ofFIG.7, an active operation may begin at a moment701. At the moment701, the main word line signal MWLB<i> may transition from a high level to a low level, and the first FIAX signal FX<j> may transition from a low level to a high level, and the second FIAX signal FXB<j> may transition from a high level to a low level. Accordingly, the PMOS transistor401of the word line driver320_kmay be turned on, and the PMOS transistor401which is turned on may activate the word line WL<k> to the active voltage level VPP.

A precharge operation may begin at a moment703, and the first FIAX signal FX<j> may transition from a high level to a low level. Also, the second FIAX signal FXB<j> may transition from a low level to a high level at the moment703and may be maintained until a moment706. The NMOS transistor405of the word line driver320_kmay be turned on from the moment703to the moment706to pull-down drive the word line WL<k>, and the word line WL<k> may be discharged to a second intermediate voltage level VSL2. Herein, the second intermediate voltage level VSL2may be a voltage level which is lower than the first intermediate voltage level VSL1and higher than the precharge voltage level VBBW. In (b) ofFIG.7, since the period that the NMOS transistor405is turned on is longer than the period in (a) ofFIG.7, the word line WL<k> may be discharged more than the word line WL<k> in (a) ofFIG.7to reach the second intermediate voltage level VSL2. At the moment706, since the second FIAX signal FXB<j> transitions from a high level to a low level, the NMOS transistor405may be turned off, and the voltage level of the word line WL<k> may be maintained at the second intermediate voltage level VSL2until a moment707. At the moment707, since the main word line signal MWLB<i> transitions to a high level and the second FIAX signal FXB<j> transitions to a high level, the NMOS transistors403and405may be turned on and the word line WL<k> may be discharged to the precharge voltage level VBBW.

In both (a) and (b) ofFIG.7, it may be seen that during the precharge operation of the word line WL<k>, the word line WL<k> may not be discharged at once but may be discharged after being maintained at the intermediate voltage level VSL1and VSL2. However, it may be seen from (a) ofFIG.7that the word line WL<k> may be discharged after being maintained at the first intermediate voltage level VSL1, which is a relatively higher voltage, but it may be seen from (b) ofFIG.7that the word line WL<k> may be discharged after being maintained at the second intermediate voltage level VSL2, which is lower than the first intermediate voltage level VSL1. In the case of (a) ofFIG.7, a soft-landing operation may be performed more actively than that of (b) ofFIG.7, and the waveforms of the process of precharging the word line WL<k> in the two cases may be different from each other

FIG.8is a timing diagram for describing an operation of the word line driver320_kin accordance with a fourth embodiment of the present invention.

InFIG.8, (a) is a timing diagram for describing an operation of the word line driver320_kwhen the word line driver320_kactivates and precharges the word line WL<k> in response to the active command and the precharge command. That is, (a) ofFIG.8shows the operation of the word line driver320_kwhen the refresh flag REF_FLAG is deactivated.

Referring to (a) ofFIG.8, an active operation may begin at a moment801. At the moment801, the main word line signal MWLB<i> may transition from a high level to a low level, and the first FIAX signal FX<j> may transition from a low level to a high level, and the second FIAX signal FXB<j> may transition from a high level to a low level. Accordingly, the PMOS transistor401of the word line driver320_kmay be turned on, and the PMOS transistor401which is turned on may activate the word line WL<k> to the active voltage level VPP.

A precharge operation may begin at a moment803, and the first FIAX signal FX<j> may transition from a high level to a low level. Also, at the moment803, the second FIAX signal FXB<j> may transition from a low level to a high level. The NMOS transistor405of the word line driver320_kmay be turned on to pull-down drive the word line WL<k>, and the word line WL<k> may be discharged to the precharge voltage level VBBW. Since only the NMOS transistor405is used to discharge the word line WL<k>, the word line WL<k> may reach the precharge voltage level at a moment805. At a moment807, the main word line signal MWLB<i> may transition to a high level.

InFIG.8, (b) is a timing diagram for describing an operation of the word line driver320_kwhen the word line driver320_kactivates and precharges the word line WL<k> during a refresh operation. That is, (b) ofFIG.8shows the operation of the word line driver320_kwhen the refresh flag REF_FLAG is activated.

Referring to (b) ofFIG.8, an active operation may begin at a moment801. At the moment801, the main word line signal MWLB<i> may transition from a high level to a low level, and the first FIAX signal FX<j> may transition from a low level to a high level, and the second FIAX signal FXB<j> may transition from a high level to a low level. Accordingly, the PMOS transistor401of the word line driver320_kmay be turned on, and the PMOS transistor401which is turned on may activate the word line WL<k> to the active voltage level VPP.

A precharge operation may begin at a moment803. At the moment803, the main word line signal MWLB<i> may transition to a high level, and the first FIAX signal FX<j> may transition to a low level, and the second The FIAX signal FXB<j> may transition to a high level. Accordingly, the NMOS transistors403and405of the word line driver320_kmay be turned on to pull-down drive the word line WL<k>. Since the word line WL<k> is pulled-down driven by the two NMOS transistors403and405, the word line WL<k> may quickly reach the precharge voltage level VBBW.

In (a) ofFIG.8, it may be seen that the word line WL<k> may be precharged relatively slowly, but in (b) ofFIG.8, it may be seen that the word line WL<k> may be precharged relatively quickly. In the case of (a) ofFIG.8, the word line WL<k> may be precharged more softly than in the case of (b) ofFIG.8, and it may be seen that the waveforms of the process of precharging the word line WL<k> in the two cases may be different from each other.

According to the above-described embodiments of the present disclosure, it may be seen that during a precharge operation which is performed in response to the precharge command, a word line may be precharged more softly, and during the precharge operation which is performed during a refresh operation, a word line may be precharged more hardly. When the effect of row hammering needs to be considered, the effect of row hammering may be reduced by softly precharging the word line, and when it is not necessary to consider the effect of row hammering, the burden of power consumption and time caused by softly precharging the word line unnecessarily may be reduced.

According to the embodiment of the present invention, the burden of a precharge operation that is performed during a refresh operation may be reduced.

While the present invention has been described with respect to the specific embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined in the following claims. Furthermore, the embodiments may be combined to form additional embodiments.