Patent ID: 12260838

MODE FOR CARRYING OUT THE INVENTION

Embodiments are described in detail with reference to the drawings. Note that the present invention is not limited to the following description, and it will be readily understood by those skilled in the art that modes and details of the present invention can be modified in various ways without departing from the spirit and scope. Therefore, the present invention should not be interpreted as being limited to the description of embodiments below. Note that in structures of the invention described below, the same portions or portions having similar functions are denoted by the same reference numerals in different drawings, and the description thereof is not repeated in some cases. The same components are denoted by different hatching patterns in different drawings, or the hatching patterns are omitted in some cases.

Even in the case where a single component is illustrated in a circuit diagram, the component may be composed of a plurality of parts as long as there is no functional inconvenience. For example, in some cases, a plurality of transistors that operate as a switch are connected in series or in parallel. In some cases, capacitors are divided and arranged in a plurality of positions.

One conductor has a plurality of functions such as a wiring, an electrode, and a terminal in some cases. In this specification, a plurality of names are used for the same component in some cases. Even in the case where elements are illustrated in a circuit diagram as if they were directly connected to each other, the elements may actually be connected to each other through one conductor or a plurality of conductors. In this specification, even such a configuration is included in direct connection.

Embodiment 1

In this embodiment, a display apparatus of one embodiment of the present invention is described with reference to drawings.

One embodiment of the present invention is a display apparatus including a circuit for boosting a signal voltage output from a gate driver. The signal voltage from the gate driver can be boosted and then supplied to a pixel, which is suitable for driving a display device with a high threshold voltage. Furthermore, power consumption can be reduced by reducing the output of the gate driver with the use of a boosting function. Furthermore, a display apparatus with low power consumption can be provided by combination of the circuit for boosting a signal voltage output from the gate driver and a pixel having a function of boosting image data. In this structure, a general driver can be used for both of a source driver and a gate driver even when the operation of a pixel circuit needs a high voltage; thus, a display apparatus with a low cost can be achieved.

<Display Apparatus>

FIG.1is a diagram illustrating a display apparatus of one embodiment of the present invention. The display apparatus includes a plurality of pixels10, circuits13, a source driver11, and a gate driver12. The source driver11is electrically connected to the pixels10. The gate driver12is electrically connected to the circuits13. The circuits13are electrically connected to the pixels10.

The pixel10includes a transistor101and a circuit21. The circuit21includes a display device. The circuit21can also include a transistor, a capacitor, or the like as appropriate. A gate of the transistor101is electrically connected to a wiring125. A wiring that connects the transistor101and the circuit21is referred to as a node NM. Note that the pixel10may have another structure. The plurality of pixels10are provided to form a pixel array18.

The circuit13can be provided row by row, and can be electrically connected to a pixel10arranged in the same row.FIG.1illustrates the pixels10arranged in the m-th column (a pixel10[n−1,m], a pixel10[n, m], a pixel10[n+1,m] (m and n are each a natural number greater than or equal to 1) and the circuits13each arranged in a corresponding row (a circuit13[n−1], a circuit13[n], and a circuit13[n+1]), in the n-th row and rows in front of and behind the n-th row.

The circuit13is a boosting circuit and has a function of boosting a signal voltage for driving the pixel which is supplied from the gate driver12. The circuit13is electrically connected to the pixel10through the wiring125.

A sequential circuit such as a shift register can be used for the source driver11and the gate driver12. Note that two or more source drivers11and/or two or more gate drivers12may be provided to drive the pixel10. The source driver11is electrically connected to the pixel10through the wiring127.

An output terminal25aof the gate driver12is connected to a wiring124[n−1], an output terminal25bis connected to a wiring124[n], and an output terminal25cis connected to a wiring124[n+1]. The gate driver12includes the output terminal25a, the output terminal25b, and the output terminal25c, and can output a signal voltage in the order of the output terminal25a, the output terminal25b, and the output terminal25c. Note that the output terminal25a, the output terminal25b, and the output terminal25care output terminals whose timing of outputting a signal voltage does not overlap one another. For example, besides three output terminals from which a signal voltage is sequentially output, every other output terminal, every third output terminal, or the like may output a signal voltage.

In addition to the wiring124[n], the wiring124[n−1] and the wiring124[n+1] are electrically connected to the circuit13[n]. Similarly, the circuit13[n−1] and the circuit13[n+1] are electrically connected to the three output terminals from which the gate driver12outputs a signal voltage. Note that the circuit13can be electrically connected to four or more output terminals included in the gate driver12.

<Boosting Circuit>

FIG.2Aillustrates an example of a structure of the circuit13. The circuit13can have a structure including a transistor102, a transistor103, a transistor104, a transistor105, and a capacitor106.FIG.2shows the circuit13[n] electrically connected to the pixel10in the n-th row.

One of a source and a drain of the transistor102is electrically connected to one electrode of the capacitor106. The one electrode of the capacitor106is electrically connected to one of a source and a drain of the transistor104. The other electrode of the capacitor106is electrically connected to one of a source and a drain of the transistor103and one of a source and a drain of the transistor105.

A gate of the transistor102is electrically connected to the wiring124[n−1]. A gate of the transistor103is electrically connected to the wiring124[n]. A gate of the transistor104is electrically connected to the wiring124[n+1]. A gate of the transistor105is electrically connected to the wiring124[n−1]. The other of the source and the drain of the transistor102is electrically connected to a wiring121. The other of the source and the drain of the transistor103is electrically connected to the wiring121. The other of the source and the drain of the transistor104is electrically connected to a wiring122. The other of the source and the drain of the transistor105is electrically connected to the wiring122.

The wirings121and122can each have a function of a power supply line. For example, the wiring121can function as a high potential power supply line, and the wiring122can function as a low potential power supply line.

Here, a wiring to which the one of the source and the drain of the transistor102, the one electrode of the capacitor106, and the one of the source and the drain of the transistor104are connected is referred to as a node A. A wiring to which the other electrode of the capacitor106, the one of the source and the drain of the transistor103, and the one of the source and the drain of the transistor105are connected is referred to as a node B. The node A functions as an output terminal, to which the wiring125[n] is electrically connected. The gate of the transistor102and the gate of the transistor105, to which the wiring124[n−1] is connected, function as first input terminals. The gate of the transistor103to which the wiring124[n] is connected functions as a second input terminal. The gate of the transistor104to which the wiring124[n+1] is connected functions as a third input terminal.

<Description of Boosting Operation>

In the circuit13, first, “V1” (high potential) is input to the first input terminals (the gate of the transistor102and the gate of the transistor105), so that the potential of the node A is set to “V1” (high potential) and the potential of the node B is set to “V0” (low potential). At this time, “V1−V0” is retained in the capacitor106. Next, “V0” is input to the first input terminals, and “V1” is input to the second input terminal (the gate of the transistor103), whereby “V1” is input to the node B with the node A floating.

At this time, when the capacitance value of the capacitor106is C106and the capacitance value of the node A is CA, the potential of the node A becomes “V1+(C106/(C106+CA))×(V1−V0)”. Here, when the value of C106is sufficiently higher than that of CA, C106/(C106+CA) approximates one, and the potential of the node A becomes “2V1−V0”.

At this time, when “V0”=0, the potential of the node A approximates “2V1”. This means that the circuit13can output a potential approximately twice as high as the potential input thereto.

As described above, the circuit13outputs the boosted potential, and a transistor in a pixel can be turned on. Furthermore, the circuit13outputs a potential at which the transistor in the pixel is turned off at next timing. Such a potential can be supplied to the node A from the wiring122through the transistor104by inputting “V1” to the third input terminal (the gate of the transistor104).

Since “V1” is input to the node A or the node B through the transistor, the potential is lower than the potential actually input to the gate by the threshold voltage (Vin) of the transistor. In this embodiment, for simplification of explanation, the absolute value of Vin is assumed sufficiently low (approximately 0 V), and description thereof is omitted.

The node A and the node B function as retention nodes. The transistor connected to the corresponding node is turned on, whereby data can be written to the node. The transistor is turned off, whereby the data can be retained in the node. The use of a transistor with an extremely low off-state current as the transistor enables leakage current to be reduced and the potential of the node to be retained for a long time. As the transistor, a transistor using a metal oxide in a channel formation region (hereinafter referred to as an OS transistor) can be used, for example.

Specifically, OS transistors are preferably used as any or all of the transistors included in the circuit13. An OS transistor may be also used for a component included in the circuit21. In the case of operating within a range where the amount of leakage current is acceptable, a transistor containing Si in a channel formation region (hereinafter, Si transistor) may be used. Alternatively, an OS transistor and a Si transistor may be used together. Examples of the Si transistor include a transistor containing amorphous silicon and a transistor containing crystalline silicon (microcrystalline silicon, low-temperature polysilicon, or single crystal silicon). The above-described structures on the transistors can be applied to other circuits in this embodiment.

As a semiconductor material used for an OS transistor, a metal oxide whose energy gap is greater than or equal to 2 eV, preferably greater than or equal to 2.5 eV, further preferably greater than or equal to 3 eV can be used. A typical example is an oxide semiconductor containing indium, and a CAAC-OS or a CAC-OS described later can be used, for example. A CAAC-OS has a crystal structure including stable atoms and is suitable for a transistor that is required to have high reliability, and the like. A CAC-OS has high mobility and is suitable for a transistor that operates at high speed, and the like.

In the OS transistor, the semiconductor layer has a large energy gap, and thus the OS transistor can have an extremely low off-state current of several yA/μm (current per micrometer of a channel width). An OS transistor has features such that impact ionization, an avalanche breakdown, a short-channel effect, or the like does not occur, which are different from those of a Si transistor. Thus, the use of an OS transistor enables formation of a highly reliable circuit. Moreover, variations in electrical characteristics due to crystallinity unevenness, which are caused in Si transistors, are less likely to occur in OS transistors.

The semiconductor layer included in the OS transistor can be, for example, a film represented by an In-M-Zn-based oxide that contains indium, zinc, and M (a metal such as aluminum, titanium, gallium, germanium, yttrium, zirconium, lanthanum, cerium, tin, neodymium, or hafnium). Besides the above In-M-Zn oxide, an In oxide, an In—Ga oxide, or an In—Zn oxide may be used for the semiconductor layer included in the OS transistor. Note that when a semiconductor layer having high proportion of indium is used, the on-state current, the field-effect mobility, or the like of the OS transistor can be increased. The In-M-Zn-based oxide can be formed by, for example, a sputtering method, an ALD (Atomic layer deposition) method, an MOCVD (Metal organic chemical vapor deposition) method, or the like.

In the case of forming a film of In-M-Zn oxide by a sputtering method, it is preferable that the atomic ratio of metal elements in a sputtering target satisfy In M and Zn≥M. The atomic ratio of metal elements in such a sputtering target is preferably, for example, In:M:Zn=1:1:1, In:M:Zn=1:1:1.2, In:M:Zn=3:1:2, In:M:Zn=4:2:3, In:M:Zn=4:2:4.1, In:M:Zn=5:1:3, In:M:Zn=5:1:6, or In:M:Zn=5:1:7, In:M:Zn=5:1:8, or In:M:Zn=10:1:3. In the case where the oxide semiconductor contained in the semiconductor layer is an In—Zn oxide, it is preferable that the atomic ratio of metal elements in a sputtering target used for forming a film of the In—Zn oxide satisfy In Zn. As the atomic ratio of metal elements in such a sputtering target, In:Zn=1:1, In:Zn=2:1, In:Zn=5:1, In:Zn=5:3, In:Zn=10:1, In:Zn=10:3, and the like are preferable.

An oxide semiconductor with low carrier concentration is used for the semiconductor layer. For example, an oxide semiconductor which has a carrier concentration lower than or equal to 1×1017/cm3, preferably lower than or equal to 1×1015/cm3, further preferably lower than or equal to 1×1013/cm3, still further preferably lower than or equal to 1×1011/cm3, yet further preferably lower than 1×1010/cm3, and higher than or equal to 1×10−9/cm3can be used for the semiconductor layer. Such an oxide semiconductor is referred to as a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor. The oxide semiconductor has a low density of defect states and can thus be regarded as an oxide semiconductor having stable characteristics.

Note that, without limitation to these, a material with an appropriate composition may be used in accordance with required semiconductor characteristics and electrical characteristics (e.g., field-effect mobility and threshold voltage) of the transistor. To obtain the required semiconductor characteristics of the transistor, it is preferable that the carrier concentration, the impurity concentration, the defect density, the atomic ratio between a metal element and oxygen, the interatomic distance, the density, and the like of the semiconductor layer be set to appropriate values.

When the oxide semiconductor in the semiconductor layer contains silicon or carbon, which is an element belonging to Group 14, the amount of oxygen vacancies is increased, and the semiconductor layer becomes n-type. Thus, the concentration of silicon or carbon (the concentration obtained by Secondary Ion Mass Spectrometry) in the semiconductor layer is set to 2×1018atoms/cm3or lower, preferably 2×1017atoms/cm3or lower.

An alkali metal and an alkaline earth metal might generate carriers when bonded to an oxide semiconductor, in which case the off-state current of the transistor might be increased. Therefore, the concentration of alkali metal or alkaline earth metal in the semiconductor layer (measured by secondary ion mass spectrometry) is set to 1×1018atoms/cm3or lower, preferably 2×1016atoms/cm3or lower.

When nitrogen is included in the oxide semiconductor forming the semiconductor layer, electrons serving as carriers are generated and the carrier concentration increases, and the semiconductor layer easily becomes n-type. Thus, a transistor using an oxide semiconductor that contains nitrogen is likely to be normally-on. Hence, the concentration of nitrogen in the semiconductor layer (measured by secondary ion mass spectrometry) is preferably set to 5×1018atoms/cm3or lower.

When hydrogen is contained in an oxide semiconductor included in the semiconductor layer, hydrogen reacts with oxygen bonded to a metal atom to be water, and thus sometimes causes an oxygen vacancy in the oxide semiconductor. If the channel formation region in the oxide semiconductor includes oxygen vacancies, the transistor sometimes has normally-on characteristics. In some cases, a defect that is an oxygen vacancy into which hydrogen enters functions as a donor and generates an electron serving as a carrier. In other cases, bonding of part of hydrogen to oxygen bonded to a metal atom generates electrons serving as carriers. Thus, a transistor including an oxide semiconductor that contains a large amount of hydrogen is likely to have normally-on characteristics.

A defect in which hydrogen has entered an oxygen vacancy can function as a donor of the oxide semiconductor. However, it is difficult to evaluate the defects quantitatively. Thus, the oxide semiconductor is sometimes evaluated by not its donor concentration but its carrier concentration. Therefore, in this specification and the like, the carrier concentration assuming the state where an electric field is not applied is sometimes used, instead of the donor concentration, as the parameter of the oxide semiconductor. That is, “carrier concentration” in this specification and the like can be replaced with “donor concentration” in some cases.

Therefore, hydrogen in the oxide semiconductor is preferably reduced as much as possible. Specifically, the hydrogen concentration of the oxide semiconductor, which is measured by secondary ion mass spectrometry (SIMS), is lower than 1×1020atoms/cm3, preferably lower than 1×1019atoms/cm3, more preferably lower than 5×1018atoms/cm3, still more preferably lower than 1×1018atoms/cm3. When an oxide semiconductor with a sufficiently low concentration of impurities such as hydrogen is used for a channel formation region of a transistor, the transistor can have stable electrical characteristics.

Oxide semiconductors (metal oxides) can be classified into a single crystal oxide semiconductor and a non-single-crystal oxide semiconductor. Examples of the non-single-crystal oxide semiconductors include a CAAC-OS (C-Axis-Aligned Crystalline Oxide Semiconductor), a polycrystalline oxide semiconductor, an nc-OS (nanocrystalline oxide semiconductor), an amorphous-like oxide semiconductor (a-like OS), and an amorphous oxide semiconductor. Among the non-single-crystal structures, an amorphous structure has the highest density of defect states, whereas the CAAC-OS has the lowest density of defect states.

An oxide semiconductor film having an amorphous structure has disordered atomic arrangement and no crystalline component, for example. In another example, an oxide film having an amorphous structure has a completely amorphous structure and no crystal part.

Note that the semiconductor layer may be a mixed film including two or more of the following: a region having an amorphous structure, a region having a microcrystalline structure, a region having a polycrystalline structure, a region of CAAC-OS, and a region having a single crystal structure. The mixed film has, for example, a single-layer structure or a layered structure including two or more of the foregoing regions in some cases.

The composition of a CAC (Cloud-Aligned Composite)-OS, which is one embodiment of a non-single-crystal semiconductor layer, is described below.

The CAC-OS has, for example, a composition in which elements contained in an oxide semiconductor are unevenly distributed. Materials containing unevenly distributed elements each have a size of greater than or equal to 0.5 nm and less than or equal to 10 nm, preferably greater than or equal to 1 nm and less than or equal to 2 nm, or a similar size. Note that in the following description of an oxide semiconductor, a state in which one or more metal elements are unevenly distributed and regions containing the metal element(s) are mixed is referred to as a mosaic pattern or a patch-like pattern. The region has a size greater than or equal to 0.5 nm and less than or equal to 10 nm, preferably greater than or equal to 1 nm and less than or equal to 2 nm, or a similar size.

Note that an oxide semiconductor preferably contains at least indium. In particular, indium and zinc are preferably contained. In addition, one or more of aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, and the like may be contained.

For example, of the CAC-OS, an In—Ga—Zn oxide with the CAC composition (such an In—Ga—Zn oxide may be particularly referred to as CAC-IGZO) has a composition in which materials are separated into indium oxide (InOX1, where X1 is a real number greater than 0) or indium zinc oxide (InX2ZnY2OZ2, where X2, Y2, and Z2 are real numbers greater than 0), and gallium oxide (GaOX3, where X3 is a real number greater than 0) or gallium zinc oxide (GaX4ZnY4OZ4, where X4, Y4, and Z4 are real numbers greater than 0), and a mosaic pattern is formed. Then, InOX1or InX2ZnY2OZ2forming the mosaic pattern is evenly distributed in the film (this composition is also referred to as a cloud-like composition).

That is, the CAC-OS is a composite oxide semiconductor with a composition in which a region containing GaOX3as a main component and a region containing InX2ZnY2OZ2or InOX1as a main component are mixed. Note that in this specification, when the atomic ratio of In to an element M in a first region is greater than the atomic ratio of In to an element Min a second region, for example, the first region is described as having higher In concentration than the second region.

Note that a compound containing In, Ga, Zn, and O is also known as IGZO. Typical examples of IGZO include a crystalline compound represented by InGaO3(ZnO)m1(m1 is a natural number) and a crystalline compound represented by In(1+x0)Ga(1−x0)O3(ZnO)m0(−1≤x0≤1; m0 is a given number).

The above crystalline compounds have a single crystal structure, a polycrystalline structure, or a CAAC structure. Note that the CAAC structure is a crystal structure in which a plurality of IGZO nanocrystals have c-axis alignment and are connected in the a-b plane direction without alignment.

The CAC-OS relates to the material composition of an oxide semiconductor. In a material composition of a CAC-OS containing In, Ga, Zn, and O, nanoparticle regions containing Ga as a main component are observed in part of the CAC-OS and nanoparticle regions containing In as a main component are observed in part thereof. These nanoparticle regions are randomly dispersed to form a mosaic pattern. Thus, the crystal structure is a secondary element for the CAC-OS.

Note that in the CAC-OS, a layered structure including two or more films with different atomic ratios is not included. For example, a two-layer structure of a film containing In as a main component and a film containing Ga as a main component is not included.

A boundary between the region containing GaOX3as a main component and the region containing InX2ZnY2OZ2or InOX1as a main component is not clearly observed in some cases.

Note that in the case where one kind or a plurality of kinds selected from aluminum, yttrium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, and the like are contained instead of gallium, the CAC-OS refers to a composition in which some regions that include the metal element(s) as a main component and are observed as nanoparticles and some regions that include In as a main component and are observed as nanoparticles are randomly dispersed in a mosaic pattern.

The CAC-OS can be formed by a sputtering method under a condition where a substrate is not heated intentionally, for example. In the case where the CAC-OS is formed by a sputtering method, one or more of an inert gas (typically, argon), an oxygen gas, and a nitrogen gas may be used as a deposition gas. The flow rate of the oxygen gas to the total flow rate of the deposition gas in deposition is preferably as low as possible; for example, the flow rate of the oxygen gas is higher than or equal to 0% and lower than 30%, preferably higher than or equal to 0% and lower than or equal to 10%.

The CAC-OS is characterized in that a clear peak is not observed when measurement is conducted using a θ/2θ scan by an out-of-plane method, which is an X-ray diffraction (XRD) measurement method. That is, it is found by the XRD measurement that there are no alignment in the a-b plane direction and no alignment in the c-axis direction in the measured areas.

In an electron diffraction pattern of the CAC-OS that is obtained by irradiation with an electron beam with a probe diameter of 1 nm (also referred to as a nanometer-sized electron beam), a ring-like region (ring region) with high luminance and a plurality of bright spots in the ring region are observed. Thus, it is found from the electron diffraction pattern that the crystal structure of the CAC-OS includes an nc (nano-crystal) structure that does not show alignment in the plane direction and the cross-sectional direction.

For example, energy dispersive X-ray spectroscopy (EDX) is used to obtain EDX mapping, and according to the EDX mapping, the CAC-OS of the In—Ga—Zn oxide has a composition in which the region containing GaOX3as a main component and the region containing InX2ZnY2OZ2or InOX1as a main component are unevenly distributed and mixed.

The CAC-OS has a structure different from that of an IGZO compound in which metal elements are evenly distributed, and has characteristics different from those of the IGZO compound. That is, in the CAC-OS, the region containing GaOX3or the like as a main component and the region containing InX2ZnY2OZ2or InOX1as a main component are separated to form a mosaic pattern.

The conductivity of the region containing InX2ZnY2OZ2or InOX1as a main component is higher than that of the region containing GaOX3or the like as a main component. In other words, when carriers flow through the region containing InX2ZnY2OZ2or InOX1as a main component, the conductivity of an oxide semiconductor is generated. Accordingly, when the regions containing InX2ZnY2OZ2or InOX1as a main component are distributed like a cloud in an oxide semiconductor, high field-effect mobility (μ) can be achieved.

By contrast, the insulating property of the region containing GaOX3or the like as a main component is superior to that of the region containing InX2ZnY2OZ2or InOX1as a main component. In other words, when the regions containing GaOX3or the like as a main component are distributed in an oxide semiconductor, leakage current can be suppressed and a favorable switching operation can be achieved.

Accordingly, when a CAC-OS is used in a semiconductor element, the insulating property derived from GaOX3or the like and the conductivity derived from InX2ZnY2OZ2or InOX1complement each other, whereby high on-state current (Lm) and high field-effect mobility (μ) can be achieved.

A semiconductor element using a CAC-OS has high reliability. Thus, the CAC-OS is suitably used as a material in a variety of semiconductor devices.

Operation Example of Boosting Circuit

An operation example of the circuit13illustrated inFIG.2Ais described using the timing chart inFIG.2B. Note that in the description below or in the timing chart, a low potential is represented by “L”, a potential that is twice as low as the low potential is represented by “2L”, a potential that is three times as low as the low potential is represented by “3L”, a high potential is represented by “H”, a potential that is twice as high as the high potential is represented by “2H”, and a potential that is three times as high as the high potential is represented by “3H”. In addition, the condition is such that the wiring121is supplied with “H”, the wiring122is supplied with “L”, and the wiring124is supplied with “H” or “L”.

Note that in potential distribution, potential coupling, or potential loss, detailed changes due to a circuit structure, operation timing, or the like are not considered. A change in potential due to capacitive coupling using a capacitor depends on the capacitance ratio of the capacitor to a component connected thereto; however, for simplicity of the description, the capacitance value of the component is assumed sufficiently small.

At time T1, when the potential of the wiring124[n−1] becomes “H” (the potential of the wiring124[n] and the potential of the wiring124[n+1] are “L”), the transistor102is turned on and the potential of the node A becomes “H”. Furthermore, the transistor105is turned on and the potential of the node B becomes “L”.

At time T2, when the potential of the wiring124[n−1] becomes “L” (the potential of the wiring124[n] and the potential of the wiring124[n+1] are “L”), the transistor102is turned off and the potential of the node A is retained at “H”. In addition, the transistor105is turned off and the potential of the node B is retained at “L”.

At time T3, when the potential of the wiring124[n] becomes “H” (the potential of the wiring124[n−1] and the potential of the wiring124[n+1] are “L”), the transistor103is turned on, and the potential of the node B changes from “L” to “H”. Accordingly, the amount of change is added to the potential of the node A in accordance with the capacitance ratio of the capacitor106to the node A, whereby the potential of the node A becomes “H+(H−L)”. In other words, when “L”=0, the potential of the node A becomes “2H”.

At time T4, when the potential of the wiring124[n] becomes “L” (the potential of the wiring124[n−1] and the potential of the wiring124[n+1] are “L”), the transistor103is turned off and the potential of the node A is retained at “2H”.

At time T5, when the potential of the wiring124[n+1] becomes “H” (the potential of the wiring124[n−1] and the potential of the wiring124[n] are “L”), the transistor104is turned on and the potential of the node A becomes “L”.

At time T6, when the potential of the wiring124[n+1] becomes “L” (the potential of the wiring124[n−1] and the potential of the wiring124[n] are “L”), the transistor104is turned off and the potential of the node A is retained at “L”.

The writing operation in the pixel10can be performed in a period during which the potential “2A” is supplied to the node A (the wiring125[n]) (at and after time T3 and before time T5). Furthermore, at and after T5, the potential of the node A is retained at “L”; thus, an image signal written to the pixel10can be retained to the next frame (next operation).

Modification Example 1 of Boosting Circuit

FIG.3Aillustrates a modification example of the circuit13. The circuit13illustrated inFIG.3Ais different from the circuit13inFIG.2Ain that a circuit14is included and the other of the source and the drain of the transistor102is electrically connected to a wiring123. The circuit14has a function of increasing the voltage output from the circuit13.

The circuit14can have a structure including a transistor107and a capacitor108. One of a source and a drain of the transistor107is electrically connected to the wiring124[n−1]. The other of the source and the drain of the transistor107is electrically connected to one electrode of the capacitor108and the gate of the transistor102. The other electrode of the capacitor108is electrically connected to the node A. In this structure, the one of the source and the drain of the transistor107serves as the first input terminal.

A gate of the transistor107is electrically connected to the wiring121. The other of the source and the drain of the transistor102is electrically connected to the wiring123. Here, the wiring123is a power supply line for supplying a potential higher than or equal to the potential of the wiring121. Note that the other of the source and the drain of the transistor102may be electrically connected to the wiring121.

The circuit14is incorporated in the circuit13of one embodiment of the present invention, whereby the circuit13can have a bootstrap effect. By the bootstrap effect, a signal voltage higher than a single voltage that is input can be output.

The bootstrap operation is as follows. First, when a potential “H” is input to a node C (a wiring to which the other of the source and the drain of the transistor107, the one electrode of the capacitor108, the gate of the transistor102, and the gate of the transistor105are connected) through the transistor107, current flows through the transistor102until the potential of the node A increases from “L” to “H”. At this time, since the potential of the node C is increased to “H” or higher due to capacitive coupling of the capacitor108, more current flows through the transistor102; thus, the potential of the node A can be increased further.

Note that the potential “H” is supplied to the one of the source and the drain and the gate of the transistor107. When the potential of the other of the source and the drain of the transistor107(the node C) is higher than “H”, current does not flow to the transistor107. That is, the transistor107functions as a diode. The structure in which the circuit14is included can be applied to another circuit in this embodiment.

The circuit13illustrated inFIG.3Acan be operated according to the timing chart inFIG.2B. Note that as described above, at time T1 to time T5, the potential of the node A can be higher than that of the circuit13inFIG.2B.

Modification Example 2 of Boosting Circuit

FIG.3Billustrates another modification example of the circuit13. The circuit13illustrated inFIG.3Bis different from the circuit13illustrated inFIG.2Ain that a circuit15is included. The circuit15is a circuit that controls the supply of a low potential to the wiring125.

The circuit15can include a transistor109, a transistor110, and a capacitor111. One of a source and a drain of the transistor109is electrically connected to the wiring121. The other of the source and the drain of the transistor109is electrically connected to one of a source and a drain of the transistor110, one electrode of the capacitor111, and the gate of the transistor104. The other of the source and the drain of the transistor110is electrically connected to the wiring122. The other electrode of the capacitor111is electrically connected to the wiring122. A gate of the transistor109is electrically connected to the wiring124[n+1]. A gate of the transistor110is electrically connected to the wiring124[n−1]. In this structure, the gates of the transistor102, transistor105, and transistor110serve as the first input terminals, and the gate of the transistor109serves as the third input terminal.

In the circuit13illustrated inFIG.2A, the transistor104is turned off at time T6 in the timing chart illustrated inFIG.2B; thus, the wiring125is brought into a floating state. At this time, if leakage current of the transistor102is relatively high, the potential of the wiring125is increased and thus a malfunction of the pixel10might occur.

The circuit15is a circuit for retaining the potential of a node D (a wiring to which the gate of the transistor104, the one electrode of the capacitor111, the other of the source and the drain of the transistor109, and the one of the source and the drain of the transistor110are connected), and can hold the transistor104in a conduction state or a non-conduction state.

The operation of the circuit15is described as follows. First, when a signal voltage “H” is input to the first input terminals, the transistor110is turned on and a potential “L” is supplied to the node D. At this time, the transistor104is off.

Next, when a signal voltage “L” is input to the first input terminals, the transistor110is turned off and the potential “L” is retained in the node D. Next, also during a period in which a boosting operation is performed using a signal voltage input to the second input terminal, the potential “L” is retained in the node D.

Then, when a signal voltage “H” is input to the third input terminal, the transistor109is turned on, and the potential of the node D becomes “H”. At this time, the transistor104is turned on, and the potential of the node A becomes “L”.

When a signal voltage “L” is input to the third input terminal, the transistor109is turned off and the potential of the node D is retained at “H”. This state is retained to the next frame; during that time, the transistor104is turned on, and the potential “L” of the wiring122is continuously supplied to the node A. Thus, the node A (the wiring125) can be kept at a constant potential “L”.

Note that in the case where an OS transistor is used as the transistor102, owing to its extremely low off-state current, the potential increase in the wiring125is slight because the off-state current is extremely low. The structure including the circuit15can be applied to other circuits in this embodiment.

Operation Example of Modification Example 2

The circuit13illustrated inFIG.3Bcan be operated in accordance with the timing chart illustrated inFIG.2B. Even when the leakage current of the transistor102is relatively high, the potential of the node A can be kept constant also at and after time T6.

Modification Example 3 of Boosting Circuit

FIG.4illustrates another modification example of the circuit13. The above-described circuit13is an example of including three input terminals; however, the circuit13illustrated inFIG.4is an example of including four input terminals. In this structure, the boosting function can be increased more than that in the aforementioned circuit13.

The circuit13illustrated inFIG.4has a structure in which a transistor112, a transistor113, and a capacitor114are added to the circuit13illustrated inFIG.2A.

The one of the source and the drain of the transistor102is electrically connected to the one electrode of the capacitor106. The one electrode of the capacitor106is electrically connected to the one of the source and the drain of the transistor104.

The other electrode of the capacitor106is electrically connected to the one of the source and the drain of the transistor105, one of a source and a drain of the transistor112, and one electrode of the capacitor114. The other electrode of the capacitor114is electrically connected to the one of the source and the drain of the transistor103and one of a source and a drain of the transistor113.

The gate of the transistor102is electrically connected to a wiring124[n−2]. A gate of the transistor112is electrically connected to the wiring124[n−1]. A gate of the transistor113is electrically connected to the wiring124[n−1]. The gate of the transistor103is electrically connected to the wiring124[n]. The gate of the transistor104is electrically connected to the wiring124[n+1]. The other of the source and the drain of the transistor102is electrically connected to the wiring121. The other of the source and the drain of the transistor103is electrically connected to the wiring121. The other of the source and the drain of the transistor104is electrically connected to the wiring122. The other of the source and the drain of the transistor105is electrically connected to the wiring122. The other of the source and the drain of the transistor112is electrically connected to the wiring121. The other of the source and the drain of the transistor113is electrically connected to the wiring122.

Here, a wiring to which the other electrode of the capacitor106, the one of the source and the drain of the transistor112, the one electrode of the capacitor114, and the one of the source and the drain of the transistor105are connected is referred to as a node E. A wiring to which the other electrode of the capacitor114, the one of the source and the drain of the transistor103, and the one of the source and the drain of the transistor113are connected is referred to as a node F.

In the circuit13illustrated inFIG.4, the gate of the transistor102and the gate of the transistor105to which the wiring124[n−2] is connected function as the first input terminals. The gate of the transistor112and the gate of the transistor113to which the wiring124[n−1] is connected function as the second input terminals. The gate of the transistor103to which the wiring124[n] is connected functions as the third input terminal. A gate of the transistor104to which the wiring124[n+1] is connected functions as a fourth input terminal.

Operation Example of Modification Example 3

The basic operation of boosting is the same as that of the circuit13illustrated inFIG.2A. An operation example of the circuit13illustrated inFIG.4is described with reference to the timing chart inFIG.5. Note that the condition is such that the wiring121is supplied with “H”, the wiring122is supplied with “L”, and the wiring124is supplied with “H” or “L”.

At time T1, when the potential of the wiring124[n−2] becomes “H” (the potential of the wiring124[n−1], the potential of the wiring124[n], and the potential of the wiring124[n+1] are “L”), the transistor102is turned on, and the potential of the node A becomes “H”. In addition, the transistor105is turned on, and the potential of the node E becomes “L”.

At time T2, when the potential of the wiring124[n−2] becomes “L” (the potential of the wiring124[n−1], the potential of the wiring124[n], and the potential of the wiring124[n+1] are “L”), the transistor102is turned off and the potential of the node A is retained at “H”. In addition, the transistor105is turned off and the potential of the node E is retained at “L”.

At time T3, when the potential of the wiring124[n−1] becomes “H” (the potential of the wiring124[n−2], the potential of the wiring124[n], and the potential of the wiring124[n+1] are “L”), the transistor112is turned on, and the potential of the node E changes from “L” to “H”. Accordingly, the amount of change is added to the potential of the node A in accordance with the capacitance ratio of the capacitor106to the node A, whereby the potential of the node A becomes “H+(H−L)”. In other words, when “L”=0, the potential of the node A becomes “2H”. The transistor113is turned on, and the potential of the node F becomes “L”.

At time T4, when the potential of the wiring124[n−1] becomes “L” (the potential of the wiring124[n−2], the potential of the wiring124[n], and the potential of the wiring124[n+1] are “L”), the transistor112is turned off and the potential of the node E is retained at “H”. In addition, the transistor113is turned off and the potential of the node F is retained at “L”.

At time T5, when the potential of the wiring124[n] becomes “H” (the potential of the wiring124[n−2], the potential of the wiring124[n−1], and the potential of the wiring124[n+1] are “L”), the transistor103is turned on and the potential of the node F changes from “L” to “H”. The amount of change is added to the potential of the node A in accordance with the capacitance ratio of the capacitor114to the node E and that of the capacitor114to the node A, and the potential of the node A becomes “2H+(H−L)”. In other words, when “L”=0, the potential of the node A becomes “3H”.

At time T6, when the potential of the wiring124[n] becomes “L” (the potential of the wiring124[n−2], the potential of the wiring124[n−1], and the potential of the wiring124[n+1] are “L”), the transistor103is turned off and the potential of the node A is retained at “3H”.

At time T7, when the potential of the wiring124[n+1] becomes “H” (the potential of the wiring124[n−2], the potential of the wiring124[n−1], and the potential of the wiring124[n] are “L”), the transistor104is turned off and the potential of the node A becomes “L”.

At time T8, when the potential of the wiring124[n+1] becomes “L” (the potential of the wiring124[n−2], the potential of the wiring124[n−1], and the potential of the wiring124[n] are “L”), the transistor104is turned off and the potential of the node A is retained at “L”.

The writing operation in the pixel10can be performed in a period during which the potential “3H” is supplied to the node A (the wiring125[n]) (at and after time T5 and before time T7). Since the potential of the node A is retained at “L” at and after T7, an image signal written to the pixel10can be retained to the next frame (next operation).

As described above, the boosting function can be enhanced by addition of the two transistors and one capacitor to the circuit13inFIG.2A. The boosting function can be further enhanced by addition of the above-described structure.

Modification Example 4 of Boosting Circuit

FIG.6Aillustrates another modification example of the circuit13. The circuit13illustrated inFIG.6has a simplified structure, in which the transistor103and the transistor105are omitted from the circuit13illustrated inFIG.2A. In this structure, the wiring124[n] is electrically connected to the other electrode of the capacitor106. In other words, the other electrode of the capacitor106functions as the second input terminal.

Operation Example of Modification Example 4

The basic operation of boosting is the same as that of the circuit13illustrated inFIG.2A. Since the transistor103is omitted, the boosting operation depends on a period during which a signal voltage “H” is input to the second input terminal.

An operation example of the circuit13illustrated inFIG.6Ais described using the timing chart inFIG.6B. In the description below and the timing chart, a low potential is represented by “L”, and a high potential is represented by “H”. In addition, the condition is such that the wiring121is supplied with “H”, the wiring122is supplied with “L”, and the wiring124is supplied with “H” or “L”.

At time T1, when the potential of the wiring124[n−1] becomes “H” (the potential of the wiring124[n] and the potential of the wiring124[n+1] are “L”), the transistor102is turned on, and the potential of the node A becomes “H”. At this time, the other electrode of the capacitor106is supplied with the potential “L”.

At time T2, when the potential of the wiring124[n−1] becomes “L” (the potential of the wiring124[n] and the potential of the wiring124[n+1] are “L”), the transistor102is turned off, and the potential of the node A is retained at “H”. At this time, the other electrode of the capacitor106is supplied with the potential “L”.

At time T3, when the potential of the wiring124[n] becomes “H” (the potential of the wiring124[n−1] and the potential of the wiring124[n+1] are “L”), the potential of the other electrode of the capacitor106changes from “L” to “H”. The amount of change is added to the potential of the node A in accordance with the capacitance ratio of the capacitor106to the node A, whereby the potential of the node A becomes “H+(H−L)”. That is, when “L”=0, the potential of the node A becomes “2H”.

At time T4, when the potential of the wiring124[n] becomes “L” (the potential of the wiring124[n−1] and the potential of the wiring124[n+1] are “L”), the potential of the other electrode of the capacitor106changes from “H” to “L”. The amount of change is added to the potential of the node A in accordance with the capacitance ratio of the capacitor106to the node A, whereby the potential of the node A becomes “2H+(L−H)”. That is, when “L”=0, the potential of the node A becomes “H”. At time T5, when the potential of the wiring124[n+1] becomes “H” (the potential of the wiring124[n−1] and the potential of the wiring124[n] are “L”), the transistor104is turned on, whereby the potential of the node A becomes “L”.

At time T6, when the potential of the wiring124[n+1] becomes “L” (the potential of the wiring124[n−1] and the potential of the wiring124[n] are “L”), the transistor104is turned off and the potential of the node A is retained at “L”.

As described above, although the potential of the node A becomes “2H” at and after time T3, it returns to “H” at time T4. That is, a period during which a high potential can be kept is shorter than that in the circuit13described with reference toFIG.2toFIG.6. The circuit13illustrated inFIG.6Ais preferably used for a display apparatus that can take sufficiently time to perform writing in a pixel even with such an operation.

Note that the same structure can also be applied to the circuit13by which a voltage can be boosted up to a higher level.FIG.7shows a structure in which another input terminal is added to the structure of the circuit13illustrated inFIG.4. The circuit13of this structure can output a potential “4H” at the maximum. A difference from the circuit13illustrated inFIG.4is that a capacitor115is electrically connected to the node F. The capacitor115can be electrically connected to an input terminal in the last stage which performs a boosting operation.

<Another Mode of Boosting Circuit and Another Connection Mode of Boosting Circuit>

Although the structures in each of which the circuit13is connected to an output terminal of the gate driver12are described inFIG.1toFIG.7, the circuit13may be a component of the gate driver12as illustrated inFIG.8A. With this structure, boosting is performed inside the gate driver12. Alternatively, the circuit13may be stacked with a circuit such as a shift register included in the gate driver12. The frame of a display apparatus can be narrowed by stacking these layers.

As illustrated inFIG.8B, a structure in which a selection circuit16is provided in the circuit13may be employed. The selection circuit16can output an output potential that is boosted in the circuit13to a selected wiring125. With such a structure, the number of circuits13provided in a display apparatus can be reduced, and the frame of the display apparatus can be narrowed. Note that a structure may be such that the selection circuit16is provided outside the circuit13and is electrically connected to an output terminal of the circuit13.

As illustrated inFIG.8C, a structure may be employed in which a selection circuit17is provided between the gate driver12and the circuit13. The selection circuit17can select a first path through which a signal voltage output from the gate driver12is output to the circuit13or a second path which bypasses the circuit13and through which a signal voltage is output to the pixel10. With such a structure, a signal voltage which has not been boosted can be supplied to the pixel, allowing the display apparatus to be switched to a power saving operation such as suppressing display luminance.

<Pixel Circuit>

The pixel10may have a structure illustrated inFIG.9Abesides the structure illustrated inFIG.2. The pixel10inFIG.9Ahas a function of boosting input data voltage. The pixel10illustrated inFIG.9Aincludes a transistor116, a transistor117, a capacitor118, and the circuit21; two gate lines (the wiring125and a wiring126) and two source lines (the wiring127and a wiring128) are electrically connected. The wiring125and the wiring126are electrically connected to different circuits13.

A gate of the transistor116is electrically connected to the wiring126, one of a source and a drain of the transistor116is electrically connected to the wiring127, and the other of the source and the drain of the transistor116is electrically connected to one electrode of the capacitor118and the circuit21. A gate of the transistor117is electrically connected to the wiring125, one of a source and a drain of the transistor117is electrically connected to the wiring128, and the other of the source and the drain of the transistor117is electrically connected to the other electrode of the capacitor118.

The transistor116is controlled by a signal supplied to the wiring126, whereas the transistor117is controlled by a signal supplied to the wiring125.

The pixel10illustrated inFIG.9Ais effective in the case where a high voltage is supplied to the display device included in the circuit21. The boosting function of the pixel10is described below. Note that in the pixel10illustrated inFIG.9A, a wiring connecting the other of the source and the drain of the transistor116, the one electrode of the capacitor118, and the circuit21is referred to as a node NM.

First, a potential “D1” of the wiring127is supplied to the node NM through the transistor116and, at overlapping timings, a reference potential “Vref” is supplied from the wiring128to the other electrode of the capacitor118through the transistor117. At this time, “D1−Vref” is retained in the capacitor118. Next, with the node NM floating, the potential of the wiring128, “D2”, is supplied to the other electrode of the capacitor118through the transistor117. Here, the potential “D2” is a potential for addition.

At this time, when the capacitance value of the capacitor118is C118and the capacitance value of the node NM is CNM, the potential of the node NM becomes D1+(C118/(C118+CNM))×(D2−Vref). Here, assuming that the value of C118is sufficiently higher than that of CNM, C118/(C118+CNM) approximates one. Thus, it can be said that the potential of the node NM approximates “D1+(D2−Vref)). When D1=D2 and Vref=0, “D1+(D2−Vref))”=“2D1”.

That is, when the circuit is designed appropriately, a potential approximately twice as high as the potential that can be input from the wiring125or the wiring126can be supplied to the node NM.

By such an action, a high voltage can be supplied to the display device. Thus, even with use of general types of a driver IC, a display device with a high threshold voltage can be operated. Alternatively, power consumption of the driver IC can be reduced.

The pixel10may have the structure illustrated inFIG.9B. The pixel10illustrated inFIG.9Bis different from the pixel10illustrated inFIG.9Ain that the transistor119is included. A gate of the transistor119is electrically connected to the wiring126, one of a source and a drain of the transistor119is electrically connected to the other of the source and the drain of the transistor117and the other electrode of the capacitor118, and the other of the source and the drain of the transistor119is electrically connected to the wiring128. The one of the source and the drain of the transistor117is connected to the wiring127.

As described above, in the pixel10illustrated inFIG.9A, the operation is performed such that the reference potential and the potential for addition are supplied to the other electrode of the capacitor118through the transistor117. In this case, the two wirings125and126are needed and the reference potential and the potential for addition need to be alternately rewritten in the wiring128, leading to a problem in a high-speed operation and power consumption.

Although the transistor119is added to the pixel10illustrated inFIG.9B, the number of wirings is not increased because the gate of the transistor119can be connected to the wiring126. In addition, the wiring128can be a dedicated wiring to which the reference potential is supplied, so that the reference potential and the potential for addition are not alternately rewritten in one wiring. Thus, this structure is suitable for a high-speed operation and low power consumption. As the wiring128, a low-potential line connected to the circuit21, or the like can be used, and thus the number of wirings can be reduced substantially.

Note that inFIG.9AandFIG.9B, an inverted potential of “D1”, “D1B”, may be used as “Vref”. In this case, a potential approximately three times as high as the potential that can be input from the wiring125or the wiring126can be supplied to the node NM. Note that the inverted potential means a potential where the absolute value of the difference from a reference potential is the same as that of the original potential and which is a different from the original potential. When the original potential, the inverted potential, and the reference potential are referred to as “D1”, “D1B”, and Vref, respectively, the relation of Vref=(D1+D1B)/2 is established.

<Circuit21>

FIG.10AtoFIG.10Deach illustrate an example of a structure including a liquid crystal device as the display device, which can be applied to the circuit21.

The structure illustrated inFIG.10Aincludes a capacitor141and a liquid crystal device142. One electrode of the liquid crystal device142is electrically connected to one electrode of the capacitor141. The one electrode of the capacitor141is electrically connected to the node NM.

The other electrode of the capacitor141is electrically connected to a wiring151. The other electrode of the liquid crystal device142is electrically connected to a wiring152. The wirings151and152each have a function of supplying power. For example, the wirings151and152are capable of supplying a reference potential such as GND or 0 V, or a given potential.

Note that a structure in which the capacitor141is omitted may be employed as illustrated inFIG.10B. As described above, an OS transistor can be used as the transistor connected to the node NM. Since an OS transistor has an extremely low leakage current, display can be maintained for a comparatively long time even when the capacitor141functioning as a storage capacitor is omitted. In addition, regardless of the structure of the transistor, omitting the capacitor141is effective also in the case where a display period can be shortened by a high-speed operation, as in field-sequential driving. The aperture ratio can be improved by omitting the capacitor141. Alternatively, the transmittance of the pixel can be improved.

In the structure ofFIG.10AandFIG.10B, the operation of the liquid crystal device142starts when the potential of the node NM becomes higher than or equal to an operation threshold value of the liquid crystal device142. Therefore, there is a case where a display operation starts before the potential of the node NM is determined. However, in the case of a transmissive liquid crystal display apparatus, even when an unnecessary display operation is performed, visual recognition can be inhibited by performing the operation of turning off a backlight until the potential of the node NM is determined.

FIG.10Cillustrates a structure in which a transistor143is added to the structure ofFIG.10A. One of a source and a drain of the transistor143is electrically connected to the one electrode of the capacitor141. The other of the source and the drain of the transistor143is electrically connected to the node NM.

In this structure, the potential of the node NM is applied to the liquid crystal device142when the transistor143is brought into conduction. Thus, the operation of the liquid crystal device142can be started at given timing after the potential of the node NM is determined.

FIG.10Dillustrates a structure in which a transistor144is added to the structure ofFIG.10C. One of a source and a drain of the transistor144is electrically connected to the one electrode of the liquid crystal device142. The other of the source and the drain of the transistor144is electrically connected to a wiring153.

A circuit170electrically connected to the wiring153can have a function of resetting the potential supplied to the capacitor141and the liquid crystal device142.FIG.11AtoFIG.11Deach illustrate an example of a structure including a light-emitting device as the display device, which can be applied to the circuit21.

The structure illustrated inFIG.11Aincludes a transistor145, a capacitor146, and a light-emitting device147. One of a source and a drain of the transistor145is electrically connected to one electrode of the light-emitting device147. The one electrode of the light-emitting device147is electrically connected to one electrode of the capacitor146. The other electrode of the capacitor146is electrically connected to a gate of the transistor145. The gate of the transistor145is electrically connected to the node NM.

The other of the source and the drain of the transistor145is electrically connected to a wiring154. The other electrode of the light-emitting device147is electrically connected to a wiring155. The wirings154and155each have a function of supplying power. For example, the wiring154is capable of supplying a high potential power. The wiring155is capable of supplying a low potential power.

In the structure illustrated inFIG.11A, current flows through the light-emitting device147when the potential of the node NM becomes higher than or equal to the threshold voltage of the transistor145.

Alternatively, as illustrated inFIG.11B, the one electrode of the light-emitting device147may be electrically connected to the wiring154, and the other electrode of the light-emitting device147may be electrically connected to the other of the source and the drain of the transistor145. This structure can also be applied to the other circuits21each including the light-emitting device147.

FIG.11Cillustrates a structure in which a transistor148is added to the structure ofFIG.15A. One of a source and a drain of the transistor148is electrically connected to the one of the source and the drain of the transistor145. The other of the source and the drain of the transistor148is electrically connected to the light-emitting device147.

In this structure, current flows through the light-emitting device147when the potential of the node NM is higher than or equal to the threshold voltage of the transistor145and the transistor148is brought into conduction. Thus, light emission of the light-emitting device147can be started at given timing after the potential of the node NM is determined.

FIG.11Dis a structure in which a transistor149is added to the structure ofFIG.11A. One of a source and a drain of the transistor149is electrically connected to the one of the source and the drain of the transistor145. The other of the source and the drain of the transistor149is electrically connected to a wiring156.

The wiring156can be electrically connected to a supply source of a certain potential such as a reference potential. Supplying a certain potential from the wiring156to the one of the source and the drain of the transistor145enables stable writing of image data. Furthermore, timing of light emission of the light-emitting device147can be controlled.

In addition, the wiring156can be connected to a circuit171and can also have a function of a monitor line. The circuit171can have one or more of a function of the supply source of a certain potential, a function of obtaining electrical characteristics of the transistor145, and a function of generating correction data.

Modification Example of Transistor

As illustrated inFIG.12, a transistor provided with a back gate may be used in a circuit of one embodiment of the present invention.FIG.12shows a structure in which back gates are electrically connected to front gates, which has an effect of increasing on-state current. Alternatively, a structure in which the back gates are electrically connected to wirings capable of supplying a constant potential may be employed. This structure enables control of the threshold voltages of the transistors. The transistors included in the circuit21may also have back gates.

<Simulation Result>

Next, simulation results of pixel operations are described.FIG.13illustrates a structure of the pixel10used in the simulation. In the simulation, the circuit structure illustrated inFIG.6Awas used, and the operation illustrated in the timing chart ofFIG.6Bwas of interest.

Parameters used in the simulation were as follows. The transistor size was L/W=3 μm/1600 μm (transistors Tr1 and Tr2); the capacitance value of a capacitor C1was 149 pF; and the capacitance value and the resistance of a load connected to the node A, on the assumption of about 9-inch diagonal vertical panel, were 149 pF and 1.9 kΩ, respectively. Power supply voltages input to the circuit13were set to GVDD=+11 V and GVSS=−21 V. Furthermore, input voltages from the gate driver (GOUT) were −21 V as “L”, and +11 V as “H”. Note that SPICE was used as circuit simulation software.

FIG.14shows simulation results. The horizontal axis represents time (usec) and the vertical axis represents a voltage (V) of the node A in the pixel10. Note that GOUT[i−1] is a signal voltage input to a gate of the transistor Tr1, GOUT[i] is a signal voltage input to the capacitor C1, and GOUT[i+1] is a signal voltage input to a gate of the transistor Tr2.

As illustrated inFIG.14, it was found that the potential of the node A is increased from the initial state where GVSS is input, −21 V, to approximately 8.4 V by the input of GOUT[i−1], increased to approximately 27.6 V by the input of GOUT[i], and returns to 21 V by the input of GOUT[i+1]. It was also observed that, with reference to the initial state, the output voltage when GOUT[i] is input can be increased approximately 1.65 times as high as the output voltage when GOUT[i−1] is input. A more appropriate design enables boosting characteristics to be improved more.

The above simulation results confirmed the effect of one embodiment of the present invention.

This embodiment can be implemented in combination with any of the structures described in the other embodiments and the like, as appropriate.

Embodiment 2

In this embodiment, a structure example of a display apparatus using a liquid crystal device and a structure example of a display apparatus using a light-emitting device are described. Note that the description of the components, operations, and functions of the display apparatus described in Embodiment 1 is omitted in this embodiment.

The pixel described in Embodiment 1 can be used in the display apparatus described in this embodiment. Note that a scan line driver circuit and a signal line driver circuit which are described below correspond to the gate driver and the source driver, respectively.

FIG.15AtoFIG.15Care diagrams each illustrating a structure of a display apparatus in which one embodiment of the present invention can be used.

InFIG.15A, a sealant4005is provided to surround a display portion215provided over a first substrate4001, and the display portion215is sealed with the sealant4005and a second substrate4006.

InFIG.15A, a scan line driver circuit221a, a signal line driver circuit231a, a signal line driver circuit232a, and a common line driver circuit241aeach include a plurality of integrated circuits4042provided over a printed circuit board4041. The integrated circuits4042are each formed using a single crystal semiconductor or a polycrystalline semiconductor. The common line driver circuit241ahas a function of supplying a prescribed potential to the wirings151,152,154,155, and the like described in Embodiment 1.

Various signals and potentials are supplied to the scan line driver circuit221a, the common line driver circuit241a, the signal line driver circuit231a, and the signal line driver circuit232athrough an FPC (Flexible printed circuit)4018.

The integrated circuits4042included in the scan line driver circuit221aand the common line driver circuit241aeach have a function of supplying a selection signal to the display portion215. The integrated circuits4042included in the signal line driver circuit231aand the signal line driver circuit232aeach have a function of supplying image data to the display portion215. The integrated circuits4042are mounted in a region different from the region surrounded by the sealant4005over the first substrate4001.

Note that the connection method of the integrated circuits4042is not particularly limited; a wire bonding method, a COF (Chip On Film) method, a COG (Chip On Glass) method, a TCP (Tape Carrier Package) method, or the like can be used.

FIG.15Billustrates an example in which the integrated circuits4042included in the signal line driver circuit231aand the signal line driver circuit232aare mounted by a COG method. Some or all of the driver circuits can be integrated over the same substrate as the display portion215, whereby a system-on-panel can be formed.

In the example illustrated inFIG.15B, the scan line driver circuit221aand the common line driver circuit241aare formed over the same substrate as the display portion215. When the driver circuits are formed concurrently with pixel circuits in the display portion215, the number of components can be reduced. Accordingly, the productivity can be increased.

InFIG.15B, the sealant4005is provided to surround the display portion215, the scan line driver circuit221a, and the common line driver circuit241awhich are provided over the first substrate4001. The second substrate4006is provided over the display portion215, the scan line driver circuit221a, and the common line driver circuit241a. Thus, the display portion215, the scan line driver circuit221a, and the common line driver circuit241aare sealed with a display device with the use of the first substrate4001, the sealant4005, and the second substrate4006.

Although the signal line driver circuit231aand the signal line driver circuit232aare separately formed and mounted on the first substrate4001in the example illustrated inFIG.15B, one embodiment of the present invention is not limited to this structure. The scan line driver circuit may be separately formed and then mounted, and part of the signal line driver circuits or part of the scan line driver circuits may be separately formed and then mounted. The signal line driver circuit231aand the signal line driver circuit232amay be formed over the same substrate as the display portion215, as illustrated inFIG.15C.

In some cases, the display apparatus include a panel in which the display device is sealed, and a module in which an IC or the like including a controller is mounted on the panel.

The display portion and the scan line driver circuit provided over the first substrate each include a plurality of transistors. As the transistors, the Si transistor or the OS transistor described in Embodiment 1 can be used.

The structure of the transistors included in the peripheral driver circuit may be the same as or different from the structure of the transistors included in the pixel circuits of the display portion. The transistors included in the peripheral driver circuit may have the same structure, or may have two or more kinds of structures. Similarly, the transistors included in the pixel circuits may have the same structure, or may have two or more kinds of structures.

An input device4200can be provided over the second substrate4006. A structure where the display device illustrated inFIG.15AtoFIG.15Cis provided with the input device4200can function as a touch panel.

There is no particular limitation on a sensor device (also referred to as a sensor element) included in the touch panel of one embodiment of the present invention. A variety of sensors capable of sensing an approach or a contact of a sensing target such as a finger or a stylus can be used as the sensor device.

It is possible to use a sensor of any of a variety of types such as a capacitive type, a resistive type, a surface acoustic wave type, an infrared type, an optical type, and a pressure-sensitive type.

In this embodiment, a touch panel including a capacitive-type sensor device is described as an example.

Examples of the capacitive type include a surface capacitive type and a projected capacitive type. Examples of the projected capacitive type include a self-capacitive type and a mutual capacitive type. The use of a mutual capacitive type is preferred because multiple points can be sensed simultaneously.

The touch panel of one embodiment of the present invention can have any of a variety of structures, including a structure in which a display apparatus and a sensor device that are separately formed are attached to each other and a structure in which an electrode and the like included in a sensor device are provided on one or both of a substrate supporting a display device and a counter substrate.

FIG.16AandFIG.16Billustrate an example of the touch panel.FIG.16Ais a perspective view of a touch panel4210.FIG.16Bis a schematic perspective view of the input device4200. Note that for clarity, only typical components are illustrated.

The touch panel4210has a structure in which a display apparatus and a sensor device that are separately formed are attached to each other.

The touch panel4210includes the input device4200and the display apparatus, which are provided to overlap with each other.

The input device4200includes a substrate4263, an electrode4227, an electrode4228, a plurality of wirings4237, a plurality of wirings4238, and a plurality of wirings4239. For example, the electrode4227can be electrically connected to the wiring4237or the wiring4239. In addition, the electrode4228can be electrically connected to the wiring4239. An FPC4272bis electrically connected to each of the plurality of wirings4237and the wirings4238. An IC4273bcan be provided for the FPC4272b.

Alternatively, a touch sensor may be provided between the first substrate4001and the second substrate4006in the display apparatus. In the case where a touch sensor is provided between the first substrate4001and the second substrate4006, either a capacitive touch sensor or an optical touch sensor including a photoelectric conversion element may be used.

FIG.17AandFIG.17Bare cross-sectional views of a portion indicated by a chain line N1−N2 inFIG.15B. The display apparatus illustrated inFIG.17Aand FIG.17B each include an electrode4015, and the electrode4015is electrically connected to a terminal included in the FPC4018through an anisotropic conductive layer4019. InFIG.17AandFIG.17B, the electrode4015is electrically connected to a wiring4014in an opening formed in an insulating layer4112, an insulating layer4111, and an insulating layer4110.

The electrode4015is formed of the same conductive layer as a first electrode layer4030, and the wiring4014is formed of the same conductive layer as source electrodes and drain electrodes of a transistor4010and a transistor4011.

The display portion215and the scan line driver circuit221aprovided over the first substrate4001each include a plurality of transistors. InFIG.17AandFIG.17B, the transistor4010included in the display portion215and the transistor4011included in the scan line driver circuit221aare illustrated as examples. Note that in the examples illustrated inFIG.17AandFIG.17B, the transistor4010and the transistor4011are bottom-gate transistors but may be top-gate transistors.

InFIG.17AandFIG.17B, the insulating layer4112is provided over the transistor4010and the transistor4011. InFIG.17B, a partition wall4510is formed over the insulating layer4112.

The transistor4010and the transistor4011are provided over an insulating layer4102. The transistor4010and the transistor4011each include an electrode4017formed over the insulating layer4111. The electrode4017can serve as a back gate electrode.

The display apparatuses illustrated inFIG.17AandFIG.17Beach include a capacitor4020. In the example shown here, the capacitor4020includes an electrode4021formed in the same step as a gate electrode of the transistor4010, an insulating layer4103, and an electrode formed in the same step as the source electrode and the drain electrode. The capacitor4020is not limited to having this structure and may be formed using another conductive layer and another insulating layer.

The transistor4010provided in the display portion215is electrically connected to the display device.FIG.17Aillustrates an example of a liquid crystal display apparatus using a liquid crystal device as the display device. InFIG.17A, a liquid crystal device4013serving as the display device includes the first electrode layer4030, a second electrode layer4031, and a liquid crystal layer4008. Note that an insulating layer4032and an insulating layer4033functioning as alignment films are provided so that the liquid crystal layer4008is positioned therebetween. The second electrode layer4031is provided on the second substrate4006side, and the first electrode layer4030and the second electrode layer4031overlap with each other with the liquid crystal layer4008therebetween.

A liquid crystal device having a variety of modes can be used as the liquid crystal device4013. For example, a liquid crystal device using a VA (Vertical Alignment) mode, a TN (Twisted Nematic) mode, an IPS (In-Plane-Switching) mode, an ASM (Axially Symmetric aligned Micro-cell) mode, an OCB (Optically Compensated Bend) mode, an FLC (Ferroelectric Liquid Crystal) mode, an AFLC (AntiFerroelectric Liquid Crystal) mode, an ECB (Electrically Controlled Birefringence) mode, a VA-IPS mode, a guest-host mode, or the like can be used.

As the liquid crystal display apparatus described in this embodiment, a normally black liquid crystal display apparatus such as a transmissive liquid crystal display apparatus employing a vertical alignment (VA) mode may be used. As the vertical alignment mode, an MVA (Multi-Domain Vertical Alignment) mode, a PVA (Patterned Vertical Alignment) mode, an ASV (Advanced Super View) mode, and the like can be used.

Note that the liquid crystal device is a device that controls transmission and non-transmission of light by the optical modulation action of liquid crystal. The optical modulation action of the liquid crystal is controlled by an electric field applied to the liquid crystal (including a horizontal electric field, a vertical electric field, and an oblique electric field). As the liquid crystal used for the liquid crystal device, thermotropic liquid crystal, low-molecular liquid crystal, high-molecular liquid crystal, polymer dispersed liquid crystal (PDLC), ferroelectric liquid crystal, anti-ferroelectric liquid crystal, or the like can be used. Such a liquid crystal material exhibits a cholesteric phase, a smectic phase, a cubic phase, a chiral nematic phase, an isotropic phase, or the like depending on conditions.

Although an example of a liquid crystal display apparatus including a liquid crystal device with a vertical electric field mode is illustrated inFIG.17A, one embodiment of the present invention can be applied to a liquid crystal display apparatus including a liquid crystal device with a horizontal electric field mode. In the case of employing a horizontal electric field mode, liquid crystal exhibiting a blue phase for which an alignment film is not used may be used. The blue phase is one of liquid crystal phases, which appears just before a cholesteric phase changes into an isotropic phase while the temperature of cholesteric liquid crystal is increased. Since the blue phase appears only in a narrow temperature range, a liquid crystal composition in which a chiral material of 5 weight % or more is mixed is used for the liquid crystal layer4008in order to improve the temperature range. The liquid crystal composition that contains liquid crystal exhibiting a blue phase and a chiral material has a short response speed and exhibits optical isotropy. In addition, the liquid crystal composition containing liquid crystal exhibiting a blue phase and a chiral material does not need alignment treatment and has small viewing angle dependence. Since an alignment film does not need to be provided and rubbing treatment is unnecessary, electrostatic breakdown caused by the rubbing treatment can be prevented and defects or damage of the liquid crystal display apparatus in the manufacturing process can be reduced.

A spacer4035is a columnar spacer obtained by selective etching of an insulating layer and is provided in order to control a distance (a cell gap) between the first electrode layer4030and the second electrode layer4031. Note that a spherical spacer may alternatively be used.

A black matrix (a light-blocking layer); a coloring layer (a color filter); an optical member (an optical substrate) such as a polarizing member, a retardation member, or an anti-reflection member; or the like may be provided as appropriate if needed. For example, circular polarization may be employed by using a polarizing substrate and a retardation substrate. In addition, a backlight, a side light, or the like may be used as a light source. A micro LED or the like may be used as the backlight or the side light.

In the display apparatus illustrated inFIG.17A, a light-blocking layer4132, a coloring layer4131, and an insulating layer4133are provided between the second substrate4006and the second electrode layer4031.

Examples of a material that can be used for the light-blocking layer include carbon black, titanium black, a metal, a metal oxide, and a composite oxide containing a solid solution of a plurality of metal oxides. The light-blocking layer may be a film containing a resin material or may be a thin film of an inorganic material such as a metal. Stacked films containing the material for the coloring layer can also be used for the light-blocking layer. For example, a stacked-layer structure of a film containing a material used for a coloring layer which transmits light of a certain color and a film containing a material used for a coloring layer which transmits light of another color can be employed. It is preferable that the coloring layer and the light-blocking layer be formed using the same material because the same apparatus can be used and the process can be simplified.

Examples of a material that can be used for the coloring layer include a metal material, a resin material, and a resin material containing a pigment or a dye. The light-blocking layer and the coloring layer can be formed by, for example, an inkjet method or the like.

The display apparatuses illustrated inFIG.17AandFIG.17Beach include the insulating layer4111and an insulating layer4104. As the insulating layer4111and the insulating layer4104, insulating layers through which an impurity element does not easily pass are used. A semiconductor layer of the transistor is positioned between the insulating layer4111and the insulating layer4104, whereby entry of impurities from the outside can be prevented.

A light-emitting device can be used as the display device included in the display apparatus. As the light-emitting device, for example, an EL device that utilizes electroluminescence can be used. An EL device includes a layer containing a light-emitting compound (also referred to as an “EL layer”) between a pair of electrodes. By generating a potential difference between the pair of electrodes that is greater than the threshold voltage of the EL device, holes are injected to the EL layer from the anode side and electrons are injected to the EL layer from the cathode side. The injected electrons and holes are recombined in the EL layer and a light-emitting compound contained in the EL layer emits light.

As the EL device, an organic EL device or an inorganic EL device can be used, for example. Note that an LED (including a micro LED) that uses a compound semiconductor as a light-emitting material can also be used.

Note that in addition to the light-emitting compound, the EL layer may further include a substance with a high hole-injection property, a substance with a high hole-transport property, a hole-blocking material, a substance with a high electron-transport property, a substance with a high electron-injection property, a substance with a bipolar property (a substance with a high electron- and hole-transport property), and the like.

The EL layer can be formed by a method such as an evaporation method (including a vacuum evaporation method), a transfer method, a printing method, an inkjet method, or a coating method.

The inorganic EL devices are classified according to their element structures into a dispersion-type inorganic EL device and a thin-film inorganic EL device. A dispersion-type inorganic EL device includes a light-emitting layer where particles of a light-emitting material are dispersed in a binder, and its light emission mechanism is donor-acceptor recombination type light emission that utilizes a donor level and an acceptor level. A thin-film inorganic EL device has a structure where a light-emitting layer is positioned between dielectric layers, which are further positioned between electrodes, and its light emission mechanism is localization type light emission that utilizes inner-shell electron transition of metal ions. Note that the description is made here using an organic EL device as the light-emitting device.

In order to extract light emitted from the light-emitting device, at least one of the pair of electrodes needs to be transparent. A transistor and a light-emitting device are formed over a substrate. The light-emitting device can have a top emission structure in which light emission is extracted from the surface on the side opposite to the substrate; a bottom emission structure in which light emission is extracted from the surface on the substrate side; or a dual emission structure in which light emission is extracted from both surfaces. The light-emitting device having any of the emission structures can be used.

FIG.17Billustrates an example of a light-emitting display apparatus using a light-emitting device as a display device (also referred to as an “EL display apparatus”). A light-emitting device4513serving as the display device is electrically connected to the transistor4010provided in the display portion215. Note that the structure of the light-emitting device4513is a stacked-layer structure of the first electrode layer4030, a light-emitting layer4511, and the second electrode layer4031; however, this embodiment is not limited to this structure. The structure of the light-emitting device4513can be changed as appropriate depending on the direction in which light is extracted from the light-emitting device4513, or the like.

The partition wall4510is formed using an organic insulating material or an inorganic insulating material. It is particularly preferable that the partition wall4510be formed using a photosensitive resin material to have an opening portion over the first electrode layer4030such that a side surface of the opening portion slopes with continuous curvature.

The light-emitting layer4511may be formed using a single layer or a plurality of layers stacked.

The emission color of the light-emitting device4513can be white, red, green, blue, cyan, magenta, yellow, or the like depending on the material for the light-emitting layer4511.

As a color display method, there are a method in which the light-emitting device4513that emits white light is combined with a coloring layer and a method in which the light-emitting device4513that emits light of a different emission color is provided in each pixel. The former method is more productive than the latter method. The latter method, which requires separate formation of the light-emitting layer4511pixel by pixel, is less productive than the former method. However, the latter method can provide higher color purity of the emission color than the former method. In the latter method, the color purity can be further increased when the light-emitting device4513has a microcavity structure.

Note that the light-emitting layer4511may contain an inorganic compound such as quantum dots. For example, when used for the light-emitting layer, the quantum dots can function as a light-emitting material.

A protective layer may be formed over the second electrode layer4031and the partition wall4510in order to prevent entry of oxygen, hydrogen, moisture, carbon dioxide, or the like into the light-emitting device4513. For the protective layer, silicon nitride, silicon nitride oxide, aluminum oxide, aluminum nitride, aluminum oxynitride, aluminum nitride oxide, DLC (Diamond Like Carbon), or the like can be used. In a space enclosed by the first substrate4001, the second substrate4006, and the sealant4005, a filler4514is provided for sealing. It is preferable that the light-emitting device be packaged (sealed) with a protective film (such as a laminate film or an ultraviolet curable resin film) or a cover member with high air-tightness and little degasification in this manner so that the light-emitting device is not exposed to the outside air.

As the filler4514, an ultraviolet curable resin or a thermosetting resin can be used as well as an inert gas such as nitrogen or argon; PVC (polyvinyl chloride), an acrylic resin, polyimide, an epoxy-based resin, a silicone-based resin, PVB (polyvinyl butyral), EVA (ethylene vinyl acetate), or the like can be used. A drying agent may be contained in the filler4514.

A glass material such as a glass frit or a resin material such as a curable resin that is curable at room temperature, such as a two-component-mixture-type resin, a light curable resin, or a thermosetting resin can be used for the sealant4005. A drying agent may be contained in the sealant4005.

If necessary, an optical film such as a polarizing plate, a circularly polarizing plate (including an elliptically polarizing plate), a retardation plate (a quarter-wave plate or a half-wave plate), or a color filter may be provided as appropriate on an emission surface of the light-emitting device. Furthermore, the polarizing plate or the circularly polarizing plate may be provided with an anti-reflection film. For example, anti-glare treatment by which reflected light can be diffused by projections and depressions on a surface so as to reduce the glare can be performed.

When the light-emitting device has a microcavity structure, light with high color purity can be extracted. Furthermore, when a microcavity structure and a color filter are combined, the glare can be reduced and visibility of a displayed image can be increased.

The first electrode layer and the second electrode layer (also called a pixel electrode layer, a common electrode layer, a counter electrode layer, or the like) for applying voltage to the display apparatus each have a light-transmitting property or a light-reflecting property, which depends on the direction in which light is extracted, the position where the electrode layer is provided, and the pattern structure of the electrode layer.

Each of the first electrode layer4030and the second electrode layer4031can be formed using a conductive material having a light-transmitting property such as indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide, indium tin oxide containing titanium oxide, indium zinc oxide, or indium tin oxide to which silicon oxide is added.

Each of the first electrode layer4030and the second electrode layer4031can also be formed using one or more kinds selected from a metal such as tungsten (W), molybdenum (Mo), zirconium (Zr), hafnium (Hf), vanadium (V), niobium (Nb), tantalum (Ta), chromium (Cr), cobalt (Co), nickel (Ni), titanium (Ti), platinum (Pt), aluminum (Al), copper (Cu), or silver (Ag); an alloy thereof and a metal nitride thereof.

A conductive composition containing a conductive high molecule (also referred to as conductive polymer) can be used for the first electrode layer4030and the second electrode layer4031. As the conductive high molecule, a so-called π-electron conjugated conductive high molecule can be used. For example, polyaniline or a derivative thereof, polypyrrole or a derivative thereof, polythiophene or a derivative thereof, and a copolymer of two or more of aniline, pyrrole, and thiophene or a derivative thereof can be given.

Since the transistor is easily broken by static electricity or the like, a protective circuit for protecting the driver circuit is preferably provided. The protective circuit is preferably formed using a nonlinear element.

Note that as illustrated inFIG.18, a stacked structure including a region where a transistor and a capacitor overlap with each other in the height direction may be employed. For example, when the transistor4011and a transistor4022included in the driver circuit are provided to overlap with each other, a display apparatus with a narrow frame can be provided. Furthermore, when the transistor4010, a transistor4023, the capacitor4020, and the like included in the pixel circuit are provided to at least partly overlap with each other, the aperture ratio and the resolution can be improved. Although an example in which the stacked structure is employed for the liquid crystal display apparatus illustrated inFIG.17Ais illustrated inFIG.18, the stacked structure may be employed for the EL display apparatus illustrated inFIG.17B.

In addition, a light-transmitting conductive film with high visible-light-transmitting property is used as an electrode or a wiring in the pixel circuit, whereby transmittance of light in the pixel can be increased and the aperture ratio can be substantially improved. Note that in the case where an OS transistor is used, a semiconductor layer also has a light-transmitting property and thus the aperture ratio can be further increased. These are effective even when transistors and the like are not stacked.

The display apparatus may have a structure with a combination of a liquid crystal display apparatus and a light-emitting apparatus.

The light-emitting apparatus is disposed on the side opposite to the display surface or on an end portion of the display surface. The light-emitting apparatus has a function of supplying light to the display device. The light-emitting apparatus can be also referred to as a backlight.

Here, the light-emitting apparatus can include a plate-like or sheet-like light guide portion (also referred to as a light guide plate) and a plurality of light-emitting devices which emit light of different colors. When the light-emitting devices are provided in the vicinity of the side surface of the light guide portion, light can be emitted from the side surface of the light guide portion to the inside. The light guide portion has a mechanism that changes an optical path (also referred to as a light extraction mechanism), and this enables the light-emitting apparatus to emit light uniformly to a pixel portion of a display panel. Alternatively, the light-emitting apparatus may be provided directly under the pixel without providing the light guide portion.

The light-emitting apparatus preferably includes light-emitting devices of three colors, red (R), green (G), and blue (B). In addition, a light-emitting device of white (W) may be included. A light emitting diode (LED) is preferably used as these light-emitting devices.

Furthermore, the light-emitting devices preferably have extremely high color purities; the full width at half maximum (FWHM) of the emission spectrum is less than or equal to 50 nm, preferably less than or equal to 40 nm, further preferably less than or equal to 30 nm, still further preferably less than or equal to 20 nm. Note that the full width at half maximum of the emission spectrum is preferably as small as possible, and can be, for example, greater than or equal to 1 nm. Thus, when a color image is displayed, a vivid image with high color reproducibility can be displayed.

As the red light-emitting device, an element whose wavelength of an emission spectrum peak is in a range from 625 nm to 650 nm is preferably used. As the green light-emitting device, an element whose wavelength of an emission spectrum peak is positioned in a range from 515 nm to 540 nm is preferably used. As the blue light-emitting device, an element whose wavelength of an emission spectrum peak is positioned in a range from 445 nm to 470 nm is preferably used.

The display apparatus can make the light-emitting devices of the three colors blink sequentially, drive the pixels in synchronization with these light-emitting elements, and display a color image on the basis of the successive additive color mixing method. This driving method can also be referred to as a field-sequential driving.

By the field-sequential driving, a clear color image can be displayed. In addition, a smooth moving image can be displayed. When the above-described driving method is used, one pixel does not need to be formed with subpixels of different colors, which can make an effective reflection area (also referred to as an effective display area or an aperture ratio) per pixel large; thus, a bright image can be displayed. Furthermore, the pixels do not need to be provided with color filters, and thus can have improved transmittance and achieve brighter image display. In addition, the manufacturing process can be simplified, and the manufacturing costs can be reduced.

FIG.19AandFIG.19Beach illustrate an example of a schematic cross-sectional view of a display apparatus capable of the field-sequential driving. A backlight unit capable of emitting light of RGB colors is provided on the first substrate4001side of the display apparatus. Note that in the field-sequential driving, the RGB colors are expressed through time division light emission, and thus color filters are not needed.

A backlight unit4340aillustrated inFIG.19Ahas a structure in which a plurality of light-emitting devices4342are provided directly under a pixel with a diffusing plate4352therebetween. The diffusing plate4352have functions of diffusing light emitted from the light-emitting device4342to the first substrate4001side and making the luminance in a display portion uniform. Between the light-emitting device4342and the diffusing plate4352, a polarizing plate may be provided if necessary. The diffusing plate4352is not necessarily provided if not needed. The light-blocking layer4132may be omitted.

The backlight unit4340acan include a large number of light-emitting devices4342, which enables bright image display. Moreover, there are advantages that a light guide plate is not needed and light efficiency of the light-emitting device4342is less likely to be lowered. Note that the light-emitting device4342may be provided with a light diffusion lens4344if necessary.

A backlight unit4340billustrated inFIG.19Bhas a structure in which a light guide plate4341is provided directly under a pixel with the diffusing plate4352therebetween. The plurality of light-emitting devices4342are provided at an end portion of the light guide plate4341. The light guide plate4341has an uneven shape on the side opposite to the diffusing plate4352, and can scatter waveguided light with the uneven shape to emit the light in the direction of the diffusing plate4352.

The light-emitting device4342can be fixed to a printed circuit board4347. Note that inFIG.19B, the light-emitting devices4342of RGB colors overlap with each other; however, the light-emitting devices4342of RGB colors can be arranged to be lined up in the depth direction. A reflective layer4348that reflects visible light may be provided on the side surface of the light guide plate4341which is opposite to the light-emitting device4342.

The backlight unit4340bcan reduce the number of light-emitting devices4342, leading to reductions in cost and thickness.

A light-scattering liquid crystal device may be used as the liquid crystal device. As the light-scattering liquid crystal device, it is preferable to use an element containing a composite material of liquid crystal and a polymer molecule. For example, a polymer dispersed liquid crystal device can be used. Alternatively, a polymer network liquid crystal (PNLC) element may be used.

The light-scattering liquid crystal device has a structure in which a liquid crystal portion is provided in a three-dimensional network structure of a resin portion sandwiched between a pair of electrodes. As a material used in the liquid crystal portion, for example, a nematic liquid crystal can be used. A photocurable resin can be used for the resin portion. As the photocurable resin, it is possible to use a monofunctional monomer, such as acrylate or methacrylate; a polyfunctional monomer, such as diacrylate, triacrylate, dimethacrylate, or trimethacrylate; or a polymerizable compound obtained by mixing these.

The light-scattering liquid crystal device performs display by transmitting or scattering light utilizing the anisotropy of a refractive index of a liquid crystal material. The resin portion may have the anisotropy of a refractive index. When liquid crystal molecules are arranged in a certain direction in accordance with a voltage applied to the light-scattering liquid crystal device, a direction is generated at which a difference in a refractive index between the liquid crystal portion and the resin portion is small. Incident light along the direction passes without being scattered in the liquid crystal portion. Thus, the light-scattering liquid crystal device is perceived in a transparent state from the direction. By contrast, when liquid crystal molecules are arranged randomly in accordance with the applied voltage, a large difference in refractive index between the liquid crystal portion and the resin portion is not generated, and incident light is scattered in the liquid crystal portion. Thus, the light-scattering liquid crystal device is in an opaque state regardless of the viewing direction.

FIG.20Aillustrates a structure in which the liquid crystal device4013of the display apparatus illustrated inFIG.19Ais replaced by a light-scattering liquid crystal device4016. The light-scattering liquid crystal device4016includes a composite layer4009including a liquid crystal portion and a resin portion, the first electrode layer4030, and the second electrode layer4031. Although components relating to the field-sequential driving are the same as those inFIG.19A, when the light-scattering liquid crystal device4016is used, an alignment film and a polarizing plate are not necessary. Note that the spherical spacer4035is illustrated, but the spacer4035may have a columnar shape.

FIG.20Billustrates a structure in which the liquid crystal device4013of the display apparatus inFIG.19Bis replaced by the light-scattering liquid crystal device4016. In the structure ofFIG.19B, operation is preferably performed in a mode where light is transmitted when a voltage is not applied to the light-scattering liquid crystal device4016and light is scattered when a voltage is applied. With such a structure, the display apparatus can be transparent in a normal state (state in which no image is displayed). In that case, a color image can be displayed when a light scattering operation is performed.

FIG.21AtoFIG.21Eillustrate modification examples of the display apparatus illustrated inFIG.20B. Note that inFIG.21AtoFIG.21E, some components in FIG. are used and the other components are not illustrated for simplicity.

FIG.21Aillustrates a structure in which the first substrate4001has a function of a light guide plate. An uneven surface may be provided on an outer surface of the first substrate4001. With this structure, a light guide plate does not need to be provided additionally, leading to a reduction in a manufacturing cost. Furthermore, the attenuation of light caused by the light guide plate also does not occur; accordingly, light emitted from the light-emitting device4342can be efficiently utilized.

FIG.21Billustrates a structure in which light enters from the vicinity of an end portion of the composite layer4009. By utilizing total reflection at the interface between the composite layer4009and the second substrate4006and the interface between the composite layer4009and the first substrate4001, light can be emitted to the outside from the light-scattering liquid crystal device. For the resin portion of the composite layer4009, a material having a refractive index higher than that of the first substrate4001and that of the second substrate4006is used.

Note that the light-emitting device4342may be provided on one side of the display apparatus, or may be provided on each of two sides facing each other as illustrated inFIG.21C. Furthermore, the light-emitting devices4342may be provided on three sides or four sides. When the light-emitting devices4342are provided on a plurality of sides, attenuation of light can be compensated for and application to a large-area display device is possible.

FIG.21Dillustrates a structure in which light emitted from the light-emitting device4342is guided to the display apparatus through a mirror4345. With this structure, light can be guided easily with a certain angle to the display apparatus; thus, total reflection light can be obtained efficiently.

FIG.21Eillustrates a structure including a stack of a layer4003and a layer4004over the composite layer4009. One of the layer4003and the layer4004is a support such as a glass substrate, and the other can be formed of an inorganic film, a coating film of an organic resin, a film, or the like. For the resin portion of the composite layer4009, a material having a refractive index higher than that of the layer4004is used. For the layer4004, a material having a refractive index higher than that of the layer4003is used.

A first interface is formed between the composite layer4009and the layer4004, and a second interface is formed between the layer4004and the layer4003. With this structure, light passing through the first interface without being totally reflected is totally reflected at the second interface and can be returned to the composite layer4009. Accordingly, light emitted from the light-emitting device4342can be efficiently utilized.

Note that the structures inFIG.20BandFIG.21AtoFIG.21Ecan be combined with each other.

This embodiment can be implemented in combination with any of the structures described in the other embodiments and the like, as appropriate.

Embodiment 3

In this embodiment, examples of transistors which can be used as the transistors described in the above embodiments are described with reference to drawings.

The display apparatus of one embodiment of the present invention can be manufactured using a transistor with any of various structures, such as a bottom-gate transistor or a top-gate transistor. Therefore, a material used for a semiconductor layer or the structure of a transistor can be easily changed depending on the existing production line.

[Bottom-Gate Transistor]

FIG.22A1is a cross-sectional view of a channel-protective transistor810, which is a type of bottom-gate transistor, in the channel length direction. In FIG.22A1, the transistor810is formed over a substrate771. The transistor810includes an electrode746over the substrate771with an insulating layer772therebetween. The transistor810also includes a semiconductor layer742over the electrode746with an insulating layer726therebetween. The electrode746can function as a gate electrode. The insulating layer726can function as a gate insulating layer.

The transistor810includes an insulating layer741over a channel formation region in the semiconductor layer742. The transistor810also includes an electrode744aand an electrode744bwhich are over the insulating layer726and partly in contact with the semiconductor layer742. The electrode744acan function as one of a source electrode and a drain electrode. The electrode744bcan function as the other of the source electrode and the drain electrode. Part of the electrode744aand part of the electrode744bare formed over the insulating layer741.

The insulating layer741can function as a channel protective layer. Provision of the insulating layer741over the channel formation region can prevent exposure of the semiconductor layer742which is caused at the time of forming the electrode744aand the electrode744b. Thus, the channel formation region in the semiconductor layer742can be prevented from being etched at the time of forming the electrode744aand the electrode744b. According to one embodiment of the present invention, a transistor with favorable electrical characteristics can be provided.

The transistor810includes an insulating layer728over the electrode744a, the electrode744b, and the insulating layer741and also includes an insulating layer729over the insulating layer728.

In the case where an oxide semiconductor is used for the semiconductor layer742, a material capable of removing oxygen from part of the semiconductor layer742to generate oxygen vacancies is preferably used at least for portions of the electrode744aand the electrode744bwhich are in contact with the semiconductor layer742. The carrier concentration in the regions of the semiconductor layer742where oxygen vacancies are generated is increased, so that the regions become n-type regions (n+ regions). Accordingly, the regions can function as a source region and a drain region. When an oxide semiconductor is used for the semiconductor layer742, examples of the material capable of removing oxygen from the semiconductor layer742to generate oxygen vacancies include tungsten and titanium.

Formation of the source region and the drain region in the semiconductor layer742can reduce contact resistance between the semiconductor layer742and each of the electrode744aand the electrode744b. Accordingly, the electrical characteristics of the transistor, such as the field-effect mobility and the threshold voltage, can be improved.

In the case where a semiconductor such as silicon is used for the semiconductor layer742, a layer that functions as an n-type semiconductor or a p-type semiconductor is preferably provided between the semiconductor layer742and the electrode744aand between the semiconductor layer742and the electrode744b. The layer that functions as an n-type semiconductor or a p-type semiconductor can function as the source region or the drain region of the transistor.

The insulating layer729is preferably formed using a material that has a function of preventing or reducing diffusion of impurities into the transistor from the outside. Note that the insulating layer729can be omitted as necessary.

A transistor811illustrated in FIG.22A2is different from the transistor810in that an electrode723that can function as a back gate electrode is provided over the insulating layer729. The electrode723can be formed using a material and a method similar to those for the electrode746.

In general, a back gate electrode is formed using a conductive layer and positioned so that a channel formation region in a semiconductor layer is positioned between the gate electrode and the back gate electrode. Thus, the back gate electrode can function in a manner similar to that of the gate electrode. The potential of the back gate electrode may be equal to that of the gate electrode, or may be a ground potential (GND potential) or a given potential. When the potential of the back gate electrode is changed independently of the potential of the gate electrode, the threshold voltage of the transistor can be changed.

The electrode746and the electrode723can each function as a gate electrode. Thus, the insulating layer726, the insulating layer728, and the insulating layer729can each function as a gate insulating layer. The electrode723may be provided between the insulating layer728and the insulating layer729.

In the case where one of the electrode746and the electrode723is referred to as a “gate electrode”, the other is referred to as a “back gate electrode”. For example, in the transistor811, in the case where the electrode723is referred to as a “gate electrode”, the electrode746is referred to as a “back gate electrode”. In the case where the electrode723is used as a “gate electrode”, the transistor811can be regarded as a kind of top-gate transistor. One of the electrode746and the electrode723may be referred to as a “first gate electrode”, and the other may be referred to as a “second gate electrode”.

By providing the electrode746and the electrode723with the semiconductor layer742sandwiched therebetween and setting the potentials of the electrode746and the electrode723equal to each other, a region of the semiconductor layer742through which carriers flow is enlarged in the film thickness direction; thus, the number of transferred carriers is increased. As a result, the on-state current of the transistor811is increased and the field-effect mobility is increased.

Therefore, the transistor811is a transistor having high on-state current for its occupation area. That is, the occupation area of the transistor811can be small for required on-state current. According to one embodiment of the present invention, the occupation area of a transistor can be reduced. Therefore, according to one embodiment of the present invention, a semiconductor device having a high degree of integration can be provided.

The gate electrode and the back gate electrode are formed using conductive layers and thus each have a function of preventing an electric field generated outside the transistor from affecting the semiconductor layer in which the channel is formed (in particular, an electric field blocking function against static electricity and the like). When the back gate electrode is formed larger than the semiconductor layer such that the semiconductor layer is covered with the back gate electrode, the electric field blocking function can be enhanced.

When the back gate electrode is formed using a conductive film having a light-blocking property, light can be prevented from entering the semiconductor layer from the back gate electrode side. Therefore, photodegradation of the semiconductor layer can be prevented, and degradation in electrical characteristics of the transistor, such as a shift of the threshold voltage, can be prevented.

According to one embodiment of the present invention, a transistor with favorable reliability can be provided. Moreover, a semiconductor device with favorable reliability can be provided.

FIG.22B1is a cross-sectional view of a channel-protective transistor820, which has a structure different from that in FIG.22A1, in the channel length direction. The transistor820has substantially the same structure as the transistor810but is different from the transistor810in that the insulating layer741covers end portions of the semiconductor layer742. The semiconductor layer742is electrically connected to the electrode744athrough an opening portion formed by selectively removing part of the insulating layer741that overlaps with the semiconductor layer742. The semiconductor layer742is electrically connected to the electrode744bthrough another opening portion formed by selectively removing part of the insulating layer741that overlaps with the semiconductor layer742. A region of the insulating layer741that overlaps with the channel formation region can function as a channel protective layer.

A transistor821illustrated in FIG.22B2is different from the transistor820in that the electrode723that can function as a back gate electrode is provided over the insulating layer729.

Provision of the insulating layer741can prevent exposure of the semiconductor layer742which is caused at the time of forming the electrode744aand the electrode744b. Thus, the semiconductor layer742can be prevented from being reduced in thickness at the time of forming the electrode744aand the electrode744b.

The distance between the electrode744aand the electrode746and the distance between the electrode744band the electrode746are longer in the transistor820and the transistor821than in the transistor810and the transistor811. Thus, the parasitic capacitance generated between the electrode744aand the electrode746can be reduced. Moreover, the parasitic capacitance generated between the electrode744band the electrode746can be reduced. According to one embodiment of the present invention, a transistor with favorable electrical characteristics can be provided.

FIG.22C1is a cross-sectional view of a channel-etched transistor825, which is a type of bottom-gate transistor, in the channel length direction. In the transistor825, the electrode744aand the electrode744bare formed without the insulating layer741. Thus, part of the semiconductor layer742that is exposed at the time of forming the electrode744aand the electrode744bmight be etched. However, since the insulating layer741is not provided, the productivity of the transistor can be increased.

A transistor826illustrated in FIG.22C2is different from the transistor825in that the electrode723that can function as a back gate electrode is provided over the insulating layer729.

FIG.23A1to FIG.23C2are cross-sectional views of the transistors810,811,820,821,825, and826in the channel width direction, respectively.

In each of the structures illustrated in FIG.23B2and FIG.23C2, the gate electrode is connected to the back gate electrode, and the potentials of the gate electrode and the back gate electrode become equal to each other. In addition, the semiconductor layer742is positioned between the gate electrode and the back gate electrode.

The length of each of the gate electrode and the back gate electrode in the channel width direction is longer than the length of the semiconductor layer742in the channel width direction. In the channel width direction, the whole of the semiconductor layer742is covered with the gate electrode and the back gate electrode with the insulating layers726,741,728, and729positioned therebetween.

In this structure, the semiconductor layer742included in the transistor can be electrically surrounded by electric fields of the gate electrode and the back gate electrode.

The transistor device structure in which the semiconductor layer742in which the channel formation region is formed is electrically surrounded by electric fields of the gate electrode and the back gate electrode, as in the transistor821or the transistor826, can be referred to as a Surrounded channel (S-channel) structure.

With the S-channel structure, an electric field for inducing a channel can be effectively applied to the semiconductor layer742by one or both of the gate electrode and the back gate electrode, which improves the current drive capability of the transistor and offers high on-state current characteristics. In addition, the transistor can be miniaturized because the on-state current can be increased. The S-channel structure can also increase the mechanical strength of the transistor.

[Top-Gate Transistor]

A transistor842illustrated in FIG.24A1is a type of top-gate transistor. The electrode744aand the electrode744bare electrically connected to the semiconductor layer742through opening portions formed in the insulating layer728and the insulating layer729.

Part of the insulating layer726that does not overlap with the electrode746is removed, and an impurity is introduced into the semiconductor layer742using the electrode746and the remaining insulating layer726as masks, so that an impurity region can be formed in the semiconductor layer742in a self-aligned manner. The transistor842includes a region where the insulating layer726extends beyond end portions of the electrode746. The semiconductor layer742in a region into which the impurity is introduced through the insulating layer726has a lower impurity concentration than the semiconductor layer742in a region into which the impurity is introduced not through the insulating layer726. Thus, an LDD (Lightly Doped Drain) region is formed in a region of the semiconductor layer742which overlaps with the insulating layer726but does not overlap with the electrode746.

A transistor843illustrated in FIG.24A2is different from the transistor842in that the electrode723is included. The transistor843includes the electrode723that is formed over the substrate771. The electrode723includes a region overlapping with the semiconductor layer742with the insulating layer772therebetween. The electrode723can function as a back gate electrode.

As in a transistor844illustrated in FIG.24B1and a transistor845shown in FIG.24B2, the insulating layer726in a region that does not overlap with the electrode746may be completely removed. Alternatively, as in a transistor846shown in FIG.24C1and a transistor847illustrated in FIG.24C2, the insulating layer726may be left. Also in the transistor842to the transistor847, after the formation of the electrode746, an impurity is introduced into the semiconductor layer742using the electrode746as a mask, so that an impurity region can be formed in the semiconductor layer742in a self-aligned manner. According to one embodiment of the present invention, a transistor with favorable electrical characteristics can be provided. Furthermore, according to one embodiment of the present invention, a semiconductor device having a high degree of integration can be provided.

FIG.25A1to FIG.25C2illustrate cross-sectional views of the transistors842,843,844,845,846, and847in the channel width direction, respectively.

The transistor843, the transistor845, and the transistor847each have the above-described S-channel structure. However, one embodiment of the present invention is not limited to this, and the transistor843, the transistor845, and the transistor847do not necessarily have the S-channel structure.

This embodiment can be implemented in combination with any of the structures described in the other embodiments and the like, as appropriate.

Embodiment 4

Examples of an electronic device that can use the display apparatus of one embodiment of the present invention include display devices, personal computers, image storage devices or image reproducing devices provided with storage media, cellular phones, game machines including portable game machines, portable data terminals, e-book readers, cameras such as video cameras and digital still cameras, goggles-type displays (head mounted displays), navigation systems, audio reproducing devices (e.g., car audio players and digital audio players), copiers, facsimiles, printers, multifunction printers, automated teller machines (ATM), and vending machines.FIG.26illustrates specific examples of such electronic devices.

FIG.26Aillustrates a digital camera, which includes a housing961, a shutter button962, a microphone963, a speaker967, a display portion965, operation keys966, a zoom lever968, a lens969, and the like. With the use of the display apparatus of one embodiment of the present invention for the display portion965, a variety of images can be displayed.

FIG.26Billustrates a portable data terminal, which includes a housing911, a display portion912, speakers913, an operation button914, a camera919, and the like. A touch panel function included in the display portion912enables input and output of information. With the use of the display apparatus of one embodiment of the present invention for the display portion912, a variety of images can be displayed.

FIG.26Cillustrates a cellular phone, which includes a housing951, a display portion952, an operation button953, an external connection port954, a speaker955, a microphone956, a camera957, and the like. The display portion952of the cellular phone includes a touch sensor. Operations such as making a call and inputting text can be performed by touch on the display portion952with a finger, a stylus, or the like. The housing901and the display portion952have flexibility and can be used in a bent state as illustrated in the figure. With the use of the display apparatus of one embodiment of the present invention for the display portion952, a variety of images can be displayed.

FIG.26Dillustrates a video camera, which includes a first housing901, a second housing902, a display portion903, an operation key904, a lens905, a connection portion906, a speaker907, and the like. The operation key904and the lens905are provided on the first housing901, and the display portion903is provided on the second housing902. With the use of the display apparatus of one embodiment of the present invention for the display portion903, a variety of images can be displayed.

FIG.26Eillustrates a television, which includes a housing971, a display portion973, an operation button974, speakers975, a communication connection terminal976, an optical sensor977, and the like. The display portion973includes a touch sensor that enables an input operation. With the use of the display apparatus of one embodiment of the present invention for the display portion973, a variety of images can be displayed.

FIG.26Fillustrates digital signage, which has a large display portion922. The large display portion922in the digital signage is attached to a side surface of a pillar921, for example. With the use of the display apparatus of one embodiment of the present invention for the display portion922, display with high display quality can be performed.

This embodiment can be implemented in combination with any of the structures described in the other embodiments as appropriate.

REFERENCE NUMERALS

10: pixel,11: source driver,12: gate driver,13: circuit,14: circuit,15: circuit,16: selection circuit,17: selection circuit,18: pixel array,21: circuit,25a: output terminal, output terminal,25c: output terminal,101: transistor,102: transistor,103: transistor,104: transistor,105: transistor,106: capacitor,107: transistor,108: capacitor,109: transistor,110: transistor,111: capacitor,112: transistor,113: transistor,114: capacitor,115: capacitor,116: transistor,117: transistor,118: capacitor,119: transistor,121: wiring,122: wiring,123: wiring,124: wiring,125: wiring,126: wiring,127: wiring,128: wiring,141: capacitor,142: liquid crystal device,143: transistor,144: transistor,145: transistor,146: capacitor,147: light-emitting device,148: transistor,149: transistor,151: wiring,152: wiring,153: wiring,154: wiring,155: wiring,156: wiring,170: circuit,171: circuit,215: display portion,221a: scan line driver circuit,231a: signal line driver circuit,232a: signal line driver circuit,241a: common line driver circuit,723: electrode,726: insulating layer,728: insulating layer,729: insulating layer,741: insulating layer,742: semiconductor layer,744a: electrode,744b: electrode,746: electrode,771: substrate,772: insulating layer,810: transistor,811: transistor,820: transistor,821: transistor,825: transistor,826: transistor,842: transistor,843: transistor,844: transistor,845: transistor,846: transistor,847: transistor,901: housing,902: housing,903: display portion,904: operation key,905: lens,906: connection portion,907: speaker,911: housing,912: display portion,913: speaker,914: operation button,919: camera,921: pillar,922: display portion,951: housing,952: display portion,953: operation button,954: external connection port,955: speaker,956: microphone,957: camera,961: housing,962: shutter button,963: microphone,965: display portion,966: operation key,967: speaker,968: zoom lever,969: lens,971: housing,973: display portion,974: operation button,975: speaker,976: communication connection terminal,977: optical sensor,4001: substrate,4003: layer,4004: layer,4005: sealant,4006: substrate,4008: liquid crystal layer,4009: composite layer,4010: transistor,4011: transistor,4013: liquid crystal device,4014: wiring,4015: electrode,4016: light-scattering liquid crystal device,4017: electrode,4018: FPC,4019: anisotropic conductive layer,4020: capacitor,4021: electrode,4022: transistor,4023: transistor,4030: electrode layer,4031: electrode layer,4032: insulating layer,4033: insulating layer,4035: spacer,4041: printed circuit board,4042: integrated circuit,4102: insulating layer,4103: insulating layer,4104: insulating layer,4110: insulating layer,4111: insulating layer,4112: insulating layer,4131: coloring layer,4132: light-blocking layer,4133: insulating layer,4200: input device,4210: touch panel,4227: electrode,4228: electrode,4237: wiring,4238: wiring,4239: wiring,4263: substrate,4272b: FPC,4273b: IC,4340a: backlight unit,4340b: backlight unit,4341: light guide plate,4342: light-emitting device,4344: lens,4345: mirror,4347: printed circuit board,4348: reflective layer,4352: diffusing plate,4510: partition wall,4511: light-emitting layer,4513: light-emitting device,4514: filler