Patent ID: 12205624

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings, in order to enable those skilled in the art to easily implement the present invention. However, the present invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Matters having no concern with the present invention will be omitted, for clarity of explanation. The same or similar elements throughout the specification are designated by the same reference numerals. In the following description, when the detailed description of the relevant known function or configuration is determined to unnecessarily obscure the important point of the present disclosure, the detailed description will be omitted.

Throughout the specification and the claims, the terms “including”, “comprising”, “having” and variations thereof mean “including but not limited to” unless expressly specified otherwise, and, as such, should not be construed to exclude elements other than the elements disclosed herein and should be construed to further include additional elements.

FIG.2is a circuit diagram showing a magnetoresistive random access memory (MRAM) cell according to an exemplary embodiment of the present invention. Referring toFIG.2, the MRAM cell according to the exemplary embodiment of the present invention includes an NMOS transistor (NL)110configured to control a reading or writing operation of the MRAM cell, a storage node120configured to store data of 1 or 0 in a writing mode of the MRAM cell, and a sensing line130configured to sense data stored in the storage node120in a reading mode of the MRAM cell.

The NMOS transistor (NL)110is determined to be opened or closed in accordance with a voltage of a word line (WL)10and, as such, controls a reading or writing operation of a cell corresponding thereto. For this function, the NMOS transistor (NL)110is connected, at a gate thereof, to the word line (WL)10while being connected, at a drain thereof, to a bit line (BL)20and connected, at a source thereof, to the storage node120. That is, the NMOS transistor (NL)110is opened when a voltage higher than a threshold voltage of the NMOS transistor (NL)110is applied to the NMOS transistor (NL)110through the word line (WL)10, the NMOS transistor (NL)110activates a current path from the bit line (BL)20to a bit line bar (BLB)30. In this case, a reading or writing operation of the cell is possible. On the other hand, when a ground voltage GND is supplied to the word line (WL)10, the NMOS transistor (NL)110is closed. In this case, there is no current flowing to the storage node120and, as such, information previously stored in the cell is maintained.

The storage node120stores data in a writing mode of the cell. For this function, the storage node120is configured through inclusion of first and second magnetic tunnel junctions (MTJ1and MTJ2)121and122connected in series between the bit line (BL)20and the bit line bar (BLB)30. In this case, each of the first and second magnetic tunnel junctions (MTJ1and MTJ2)121and122has a state determined by a direction of current determined in accordance with a direction of voltage drop between the bit line (BL)20and the bit line bar (BLB)30. Accordingly, the first and second magnetic tunnel junctions (MTJ1and MTJ2)121and122have different ones of a low resistance state (LRS) (hereinafter, referred to as an “LRS”) and a high resistance state (HRS) (hereinafter, referred to as an “HRS”), respectively. In the example ofFIG.2, the first and second magnetic tunnel junctions (MTJ1and MTJ2)121and122are represented by variable resistors (RS and RD)121and122, respectively. In the following description, the first magnetic tunnel junction (MTJ1)121is simply referred to as an RS121″, and the second magnetic tunnel junction (MTJ2)122is simply referred to as an RD122″.

In order to set the RS121and the RD122such that the RS121and the RD122have different states, that is, opposite magnetic directions, respectively, the RS121and the RD122should have different orders of a free layer and a pinned layer in terms of current direction, respectively. Such structures of the RS121and the RD122are illustrated inFIG.3.

FIG.3is a circuit diagram schematically showing the pair of magnetic tunnel junctions according to an exemplary embodiment of the present invention. Referring toFIG.3, the RS121includes a free layer F formed at the side of the bit line (BL) a pinned layer P formed at the side of the RD122, and an insulating layer formed therebetween, and the RD122includes a free layer F formed at the side of the bit line bar (BLB)30, a pinned layer P formed at the side of the RS121, and an insulating layer formed therebetween.

Accordingly, when current flows in a direction from the bit line (BL)20to the bit line bar (BLB)30, the RS121has an LRS, and the RD122has an HRS. When the flowing direction of current is reversed, the RS121has an HRS, and the RD122has an LRS. The MRAM cell according to the exemplary embodiment of the present invention stores data of 1 or 0 using characteristics as described above. That is, when the RS121has an LRS, and the RD122has an HRS, data of 1 is stored in the storage node120. In the case opposite to the above-described case, data of 0 is stored. Such a data writing operation will be described later with reference toFIG.4.

The sensing line130is activated in a reading mode of the MRAM cell and, as such, creates data reading information based on a voltage between the RS121and the RD122. For this function, the sensing line130is configured through inclusion of an NMOS transistor (ND)131and a load resistor (RL)132connected in series between a power source and the ground.

The NMOS transistor (ND)131is a transistor cell used to sense states of the RS121and the RD122. A voltage VPLbetween the RS121and the RD122is applied to a gate of the NMOS transistor (ND)131. The gate voltage of the NMOS transistor (ND)131is varied in accordance with a relative resistance ratio between the RS121and the RD122. The NMOS transistor (ND)131is opened when the gate voltage of the NMOS transistor (ND)131exceeds a threshold voltage of the NMOS transistor (ND)131. Accordingly, the gate voltage of the NMOS transistor (ND)131may be used as a measure of data stored in the storage node120.

Meanwhile, the NMOS transistor (ND)131is connected, at a source thereof, to the ground while being connected, at a drain thereof, to the load resistor (RL)132. In order to activate the sensing line130only in the reading mode of the MRAM cell, power SL is supplied to the other side of the load resistor (RL)132in the reading mode of the MRAM cell, whereas the other side of the load resistor (RL)132is connected to the ground in a writing mode of the MRAM cell. When the other side of the load resistor (RL)132is connected to the ground in the writing mode of the MRAM cell, unnecessary current flow is prevented and, as such, power saving is achieved.

Meanwhile, the NMOS transistor (ND)131is opened when data of 1 is stored in the storage node120, thereby causing the drain voltage thereof to drop. On the other hand, the NMOS transistor (ND)131is closed when data of 0 is stored in the storage node120, thereby causing the drain voltage thereof to be maintained. Accordingly, an external sensing circuit (for example, an ADC, etc.) may read data stored in the storage node120by sensing a voltage variation as described above. Such a data reading operation will be described later with reference toFIG.5.

FIG.4is a timing diagram of control voltages applied in the writing mode of the MRAM cell according to the exemplary embodiment of the present invention.FIG.4illustrates timings of a word line voltage VWL(a), a bit line voltage VBL(b), a bit line bar voltage VBLB(c), and a sensing line voltage VSL(d). The sensing line voltage VSLis a voltage applied to the sensing line130illustrated inFIG.2. This voltage is generated when predetermined power is supplied to the other side of the load resistor (RL)132.

Referring toFIGS.2to4, first, for the writing operation of the MRAM cell, the word line voltage VWL(a) is maintained at a level higher than the threshold voltage of the NMOS transistor (NL)110in first and second writing periods t1and t2. Accordingly, the NMOS transistor (NL)110is opened, thereby activating a current path from the bit line (BL)20to the bit line bar (BLB)30.

When it is desired to write data of 1 in the storage node120, voltage drop from the bit line (BL)20to the bit line bar (BLB)30is generated in order to generate a flow of current from the free layer F to the pinned layer P in the RS121and a flow of current from the pinned layer P to the free layer F in the RD122. To this end, a predetermined voltage is applied to the bit line (BL)20, and the bit line bar (BLB)30is connected to the ground GND (cf. the first writing period t1). In this case, the RS121and the RD122are set to an LRS and an HRS, respectively, and, as such, data of 1 may be stored in the storage node120.

On the other hand, when it is desired to write data of 0 in the storage node120, voltage drop from the bit line bar (BLB)30to the bit line (BL)20is generated in order to generate a flow of current from the pinned layer P to the free layer F in the RS121and a flow of current from the free layer F to the pinned layer P in the RD122. To this end, the bit line (BL)20is connected to the ground GND, and a predetermined voltage is applied to the bit line bar (BLB)30(cf. the second writing period t2). In this case, the RS121and the RD122are set to an HRS and an LRS, respectively, and, as such, data of 0 may be stored in the storage node120.

The predetermined voltage applied to each of the bit line (BL)20and the bit line bar (BLB)30is a voltage value variable by a corresponding one of the MTJs, and is associated with a process. This voltage may be expressed by a variable Vwrite which is not fixed to a specific value.

Thus, data of 1 may be stored when the RS121and the RD122are in the LRS and the HRS, respectively, because a voltage VPLgenerated at a node PL between the RS121and the RD122is higher than the threshold voltage of the ND131, thereby opening the ND131, and, as such, a voltage drop in the RL132may be sensed. On the other hand, data of 0 may be stored when the RS121and the RD122are in the HRS and the LRS, respectively, because the voltage VPLgenerated at the node PL is lower than the threshold voltage of the ND131, thereby closing the ND131, and, as such, no voltage drop in the RL132will be sensed.

Meanwhile, in the writing mode of the MRAM cell, the sensing line130is connected to the ground GND, thereby causing the voltage VSL(d) to be maintained at a low level, in order to preventing current from flowing through the sensing line130. In addition, after the writing operation, all of the word line voltage VWL(a), the bit line voltage VBL(b), and the bit line bar voltage VBLB(c) are connected to the ground GND in order to avoid writing disturbance and to save energy (cf. a period between the first and second writing periods t1and t2).

FIG.5is a timing diagram of control voltages applied in the reading mode of the MRAM cell according to the exemplary embodiment of the present invention.FIG.5illustrates timings of a word line voltage VWL(a), a bit line voltage VBL(b), a bit line bar voltage VBLB(c), a voltage VPL(d) between the RS121and the RD122illustrated inFIGS.2and3, a sensing line voltage VSL(e), and a drain voltage VO(f) of the NMOS transistor (ND)131illustrated inFIG.2. The sensing line voltage VSLis a voltage applied to the sensing line130illustrated inFIG.2. This voltage is generated when predetermined power is supplied to the other side of the load resistor (RL)132. In addition, the drain voltage VO(f) of the NMOS transistor (ND)131is data reading information. An external sensing circuit (for example, an ADC, etc.) may determine whether data stored in the storage node120is 1 or 0 by sensing a variation in the drain voltage VO(f).

Referring toFIGS.2,3, and5, first, for a reading operation of the MRAM cell, the word line voltage VWL(a) is maintained at a level higher than the threshold voltage of the NMOS transistor (NL)110in first and second writing periods t1and t2. Accordingly, the NMOS transistor (NL)110is opened, thereby activating the current path from the bit line (BL)20to the bit line bar (BLB)30.

In addition, the sensing line voltage VSL(e) is set to a rather high fixed voltage (for example, 0.5 V, 0.8 V, 1 V, etc.), to ensure that the NMOS transistor (ND)131can operate well in a sufficient range for sensing.

In addition, in the reading mode of the MRAM cell, a predetermined voltage (for example, 0.6V) is applied to the bit line (BL)20, and the bit line bar (BLB)30is connected to the ground GND, in order to generate a voltage drop from the bit line (BL)20to the bit line bar (BLB)30, thereby enabling current to flow from the bit line (BL)20to the bit line bar (BLB)30. In this case, the bit line voltage VBL(b) is preferably maintained at a level lower than a voltage in the first writing period t1illustrated inFIG.4, in order to prevent overwriting of the RS121and the RD122.

When the bit line voltage VBL(b) is maintained at a level lower than the voltage in the first writing period t1, a writing operation is not performed because the voltage applied to the RS121and the RD122(that is, a read voltage Vread) is lower than a write voltage Vwrite and, as such, states of the RS121and the RD122are maintained without being varied.

When the MRAM cell operates in the reading mode in accordance with the above-described setting, the RS121and the RD122may be regarded as normal resistor cells. In addition, the gate voltage and the drain voltage of the NMOS transistor (NL)110are fixed, and the total resistance of the RS121and the RD122, which is determined by the voltage drop between the bit line (BL)20and the bit line bar (BLB)30, is also almost fixed. Accordingly, the voltage drop from the source side of the bit line (BL)20to the bit line bar (BLB)30, which is shared by the RS121and the RD122, is almost fixed.

Hereinafter, a reading operation of the MRAM cell under the above-described conditions will be described.

First, in the case in which data of 1 is stored in the MRAM cell, the RS121and the RD122are in the LRS and the HRS, respectively. Accordingly, the RD122shares a voltage in a higher rate than that of the RS121, and the node PL between the RS121and the RD122has a voltage higher than the threshold voltage of the NMOS transistor (ND)131. In this case, the NMOS transistor (ND)131is opened and, as such, current flowing from the drain side to the source side of the NMOS transistor (ND)131is activated. When it is taken into consideration that the drain of the NMOS transistor (ND)131is connected to a path where the load resistor (RL)132is disposed, a voltage drop is generated at the load resistor (RL)132when the current flowing from the drain side to the source side of the NMOS transistor (ND)131is activated. As a result, the drain voltage of the NMOS transistor (ND)131drops in a considerable magnitude (cf. the first reading period t3). Such a voltage variation is used as data reading information for reading of data of 1. That is, the external sensing circuit (for example, an ADC, etc.) senses such a voltage variation and, as such, reads that data of 1 is stored in the storage node120.

On the other hand, in the case in which data of 0 is stored in the MRAM cell, the RS121and the RD122are in the HRS and the LRS, respectively. Accordingly, the RS121shares a voltage in a higher rate than that of the RD122, and the node PL between the RS121and the RD122has a voltage lower than the threshold voltage of the NMOS transistor (ND)131. In this case, the NMOS transistor (ND)131is closed and, as such, current flowing from the drain side to the source side of the NMOS transistor (ND)131is not activated. Although a voltage drop is generated at the load resistor (RL)132in this case, the drain voltage of the NMOS transistor (ND)131is maintained at the same level as that of the sensing line voltage VSL. (cf. a second reading period t4). Such a voltage state is used as data reading information for reading of data of 0. That is, the external sensing circuit (for example, an ADC, etc.) senses such a voltage variation and, as such, reads that data of 0 is stored in the storage node120.

Thus, the NMOS transistor (ND)131included in the sensing line130is turned on when the RS121is in the LRS, and the RD122is in the HRS and, as such, creates data-1 reading information. On the other hand, when the RS121is in the HRS, and the RD122is in the LRS, the NMOS transistor (ND)131is turned off and, as such, creates data-0 reading information.

For correct reading of data of 1 and data of 0 in the reading mode of the MRAM cell, the MRAM cell is required to suitably adjust an applied voltage and a resistance value in the writing mode.

For example, when the MRAM cell stores data of 1, respective voltages of the word line (WL)10, the bit line (BL)20, and the bit line bar (BLB)30may be suitably adjusted such that the voltage VPLof the node PL is higher than the threshold voltage of the NMOS transistor (ND)131. On the other hand, when the MRAM cell stores data of 0, respective voltages of the word line (WL)10, the bit line (BL)20, and the bit line bar (BLB)30may be suitably adjusted such that the voltage VPLof the node PL is lower than the threshold voltage of the NMOS transistor (ND)131. At the same time, the sensing line voltage VSLand the resistance of the load resistor (RL)132are adjusted in accordance with physical characteristics of the NMOS transistor (ND)131. Accordingly, there is no voltage variation when the NMOS transistor (ND)131is closed, and it may be possible to obtain a sufficient voltage drop in the load resistor (RL)132only when the NMOS transistor (ND)131is opened.

That is, the sensing line voltage VSLis set to 0.5 V, and the resistance of the load resistor (RL)132is adjusted to 40 kΩ. Thus, when the MRAM cell stores data of 1, the voltage VPLof the node PL is set to 50 mV larger than the threshold voltage of ND, and, as such, a voltage drop of 30 mV may be obtained in the load resistor (RL)132. Otherwise, when the MRAM cell stores data of 0, the voltage VPLof the node PL is set to 50 mV smaller than the threshold voltage of ND, and, as such, no voltage drop will be obtained in the load resistor (RL)132.

FIG.6is a table representing parameters corresponding to data values stored in the MRAM cell according to the exemplary embodiment of the present invention.FIG.6shows main parameters according to data stored in the storage node120.

Referring toFIGS.2to6, in the case in which data of 1 is stored in the storage node120, there are features in that the RS121and the RD122, which constitute the storage node120, are in the LRS and the HRS, respectively, the voltage VPLat the node PL between the RS121and the RD122is higher than the threshold voltage of the NMOS transistor (ND)131, and the drain voltage VOof the NMOS transistor (ND)131is reduced. On the other hand, in the case in which data of 0 is stored in the storage node120, there are features in that the RS121and the RD122, which constitute the storage node120, are in the HRS and the LRS, respectively, the voltage VPLat the node PL between the RS121and the RD122is lower than the threshold voltage of the NMOS transistor (ND)131, and the drain voltage VOof the NMOS transistor (ND)131is maintained.

FIG.7is a diagram illustrating an example of a memory device including a plurality of MRAM cells disposed in a two-dimensional matrix in accordance with an exemplary embodiment of the present invention. Referring toFIGS.2,4,5, and7, the memory device according to the exemplary embodiment of the present invention includes a plurality of MRAM cells100disposed in an m×n matrix, a word line driver200, and a control voltage generator300.

The configuration and operation of each of the MRAM cells100are identical to those described with reference toFIGS.2to6and, as such, no overlapping description thereof will be given.

The word line driver200generates m word line (WL) voltages for determination of operation modes of corresponding ones of the MRAM cells100, and transmits the word line (WL) voltages to the corresponding MRAM cells100through word lines (WL)10, respectively. In this case, the word line driver200generates a predetermined word line voltage (FIG.4(a)andFIG.5(a)) for control of opening and closing of the NMOS transistor (NL)110in the writing periods t1and t2and the reading periods t3and t4of each MRAM cell100, as illustrated inFIGS.4and5. In this case, a voltage higher than the threshold voltage of the NMOS transistor (NL)110is generated and, as such, current flows between the bit line (BL)20and the bit line bar (BLB)30.

Meanwhile, as illustrated inFIGS.4and5, the word line driver200applies a ground voltage GND in all periods, except for the writing periods t1and t2and the reading periods t3and t4of the MRAM cell100. Accordingly, flow of current between the bit line (BL)20and the bit line bar (BLB)30is prevented and, as such, states of the RS121and the RD122are maintained.

The control voltage generator300generates a control voltage for control of an operation of each of the MRAM cells100and determination of data to be stored in each of the MRAM cells100. The control voltage generator300also generates n bit line (BL) voltages, n bit line bar (BLB) voltages, and n sensing line voltages VSL.

In particular, when each of the MRAM cells100is in a writing mode, the control voltage generator300generates a bit line (BL) voltage (b) and a bit line bar (BLB) voltage (c) while generating a ground voltage as a sensing line voltage VSL(d), as illustrated inFIG.4, in order to generate a voltage drop between the bit line (BL) and the bit line bar (BLB), for writing of data of 1 or data of 0.

On the other hand, when each of the MRAM cell100is in a reading mode, the control voltage generator300generates a predetermined bit line (BL) voltage (b) while connecting the bit line bar (BLB) voltage (c) to the ground, as illustrated inFIG.5, in order to generate a voltage drop in a direction from the bit line (BL) to the bit line bar (BLB). In this case, the control voltage generator300generates a bit line (BL) voltage (b) lower than the bit line (BL) voltage (b) in the first writing period t1illustrated inFIG.4, in order to prevent overwriting of the RS121and the RD122.

In addition, the control voltage generator300may generate a rather high fixed voltage as the sensing line voltage VSL, in order to enable the NMOS transistor (ND)131to operate in a sufficient range for sensing, that is, to enable generation of a sufficient voltage difference when the NMOS transistor (ND)131is opened, as illustrated inFIG.2.

As apparent from the above description, the MRAM cell and the memory device using the same according to the exemplary embodiments of the present invention include a pair of magnetic tunnel junctions (MTJs) having opposite states, and store data based on a relative resistance ratio between the pair of MTJs. Accordingly, it may be possible to enhance the ability to distinguish between two data states ‘1’ and ‘0’, as such, there is an effect of enhancing reliability of data writing or reading.

In addition, in the MRAM cell and the memory device using the same according to the exemplary embodiments of the present invention, states of the pair of MTJs having opposite states are changed to different ones of a low resistance state (LRS) and a high resistance state (HRS), respectively, in accordance with voltage drop directions of a bit line (BL) and a bit line bar (BLB), and data of 0 or 1 is then stored based on information of the changed states. Accordingly, there is an effect of enhancing writing reliability without being influenced by absolute values of a high resistance value (Rap) and a low resistance value (Rp) and, as such, without being influenced by deformation occurring in an MTJ manufacturing procedure.

In addition, in the MRAM cell and the memory device using the same according to the exemplary embodiments of the present invention, data reading information is created based on a voltage between the pair of MTJs respectively having different ones of the LRS and the HRS. Accordingly, there is an effect of rapidly and stably reading previously-stored data and, as such, enhancing data reading reliability.

Although the preferred embodiments of the invention have been disclosed for illustrative purposes, those skilled in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope and spirit of the invention as disclosed in the accompanying claims.