Patent ID: 12230709

Like reference symbols in the various drawings indicate like elements.

DETAILED DESCRIPTION OF THE DISCLOSURE

The making and using of the embodiments of the disclosure are discussed in detail below. It should be appreciated, however, that the embodiments provide many applicable inventive concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative of specific ways to make and use the embodiments, and do not limit the scope of the disclosure. Throughout the various views and illustrative embodiments, like reference numerals are used to designate like elements. Reference will now be made in detail to exemplary embodiments illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts. In the drawings, the shape and thickness may be exaggerated for clarity and convenience. This description will be directed in particular to elements forming part of, or cooperating more directly with, an apparatus in accordance with the present disclosure. It is to be understood that elements not specifically shown or described may take various forms. Reference throughout this specification to “one embodiment” or “an embodiment” means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment. Thus, the appearances of the phrases “in one embodiment” or “in an embodiment” in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. It should be appreciated that the following figures are not drawn to scale; rather, these figures are merely intended for illustration.

Off-state leakage current and on-state resistance are considered figure of merits of a MOS FET. In deep sub-micron CMOS FET devices, the gate induced drain leakage (GIDL) current increases because the gate oxide insulation layer thickness is reduced to as low as 40 angstroms. The GIDL current typically occurs in thin gate oxide MOS devices and is current between the drain and the substrate. The basis of the GIDL current is band-to-band tunneling that occurs on the surface of the gate-to-drain overlap region. For example, an N+ region underneath a gate edge produces a high vertical electrical field that results in hole generation on the surface of an N+ region underneath the gate by band-to-band tunneling in the device. In a MOS FET, Rds(on) is the total resistance between the source and the drain during the on state. It is an important parameter, determining maximum current rating and loss. To reduce Rds(on), the integrity of the chip and trench technique are considered.

Conventional MOS FET fabricated using self-align drain suffers from severe GIDL problem. Although the self-align drain structure offer scaling advantage for the MOS FET, high off-state leakage current leads to low efficiency for power switch applications.

On the other hand, the conventional MOS FET fabricated using drain extended structure or field plate (FP) produce a high Rds(on). Although the leakage current is comparatively low in the drain extended structure or FP scenario, the Rds(on) is high or the on-state current is low. Furthermore, the FP structure limits the scaling capability of the MOS FET. For example, resist protect oxide (RPO) extends from a top of the gate electrode to a top of the heavily doped drain. The width spanning the RPO extension takes at least over 0.4 μm, rendering difficulties in shrinking device pitch.

Present disclosure provides a transistor structure or a high power transistor structure having a low off-state leakage current and a low on-state resistance. At the same time, the transistor structure or the high power transistor structure described herein provides a modulation function to the electric field between the gate edge and heavily doped region (i.e., source or drain) thereby optimizing the breakdown voltage. A method for manufacturing the transistor structure or the high power transistor structure is also described herein.

FIG.1is a cross sectional view showing a transistor structure10, in accordance with some embodiments of the present disclosure. Note the transistor structure10can be a MOS FET in normal power or high power application. Referring toFIG.1, semiconductor substrate100is provided. Semiconductor substrate100may include crystalline silicon or other semiconductor materials such as silicon germanium, silicon carbon, or the like. Optionally, an N+ Buried Layer (NBL) is formed in a portion of the substrate100, wherein NBL is proximate, and below, the top surface of substrate100. NBL may be formed by implanting an n-type dopant into an intermediate region of substrate100. For example, NBL may be formed by implanting phosphorous to a concentration between about 1×1017/cm3and about 1×1019/cm3, or to a higher concentration. Alternatively, other n-type dopants such as arsenic and antimony may be implanted. In some alternative embodiments, NBL is formed by implanting a surface portion of original substrate100, and then epitaxially growing a semiconductor layer over NBL.

The semiconductor substrate100may be selectively implanted using various implantation steps to form a plurality of implantation regions (e.g., well regions, contact regions, etc.). For example, the semiconductor substrate100may be selectively implanted to form a well region101A, a lightly doped region (LDD)103, a source region105, a drain region107, and a contact region (not shown). The plurality of implantation regions may be formed by selectively masking the semiconductor substrate100(e.g., using a photoresist mask) and then introducing high-energy dopants (e.g., p-type dopant species such as boron or n-type dopants such as phosphorous) into exposed areas of the semiconductor substrate100.

A first gate110is disposed over the semiconductor substrate100at a position that is laterally arranged between the source region105and the drain region107. The first gate110includes a gate electrode110A that is separated from the semiconductor substrate100by a gate dielectric layer (not shown). In some embodiments, the gate dielectric layer may include silicon dioxide (SiO2) or a high-k gate dielectric material and the gate electrode110A may include polysilicon or a metal gate material (e.g., aluminum). In some embodiments, the first gate110may also include sidewall spacers110B,110B′ disposed on opposing sides of the gate electrode110A. From a cross sectional perspective, sidewall spacer110B is at a side111of the gate electrode110A in proximity to the source region105, whereas sidewall spacer110B′ is at a side111′ of the gate electrode110A away from the source region105. In various embodiments, the sidewall spacers110B,110B′ may include a nitride based sidewall spacer (e.g., comprising SiN) or an oxide-based sidewall spacer (e.g., SiO2, SiOC, etc.). As shown inFIG.1, the position of the source region105is self-aligned with an edge E1of the sidewall spacer110B, and an LDD103is self-aligned with the side111of the gate electrode110A.

The LDD technique is widely used in high voltage field effect transistor applications to avoid breakdown due to the high electric field intensity at the gate-edge. This technique involves interposing a lightly doped drift region in the drain or source, so as to reduce the electric field intensity to below the breakdown voltage (BV). The length of this LDD region is dependent upon the specific operating range of the transistor. However, in addition to a larger size in the resulting transistor, the drawbacks of an LDD device also include a larger turn-on drain resistance Rds(on), leading to a reduced current drive capability.

A second gate120is disposed over the semiconductor substrate100at a position that is laterally arranged between the source region105and the drain region107. The second gate120includes a gate electrode120A that is separated from the semiconductor substrate100by a gate dielectric layer (not shown). In some embodiments, the gate dielectric layer may include silicon dioxide (SiO2) or a high-k gate dielectric material and the gate electrode120A may include polysilicon or a metal gate material (e.g., aluminum). In some embodiments, the gate electrode110A and the gate electrode120A are composed of the same material. In some embodiments, the second gate120may also include sidewall spacers120B,120B′ disposed on opposing sides of the gate electrode120A. From a cross sectional perspective, sidewall spacer120B is at a side121of the gate electrode120A in proximity to the drain region107, whereas sidewall spacer120B′ is at a side121′ of the gate electrode120A away from the drain region107. In various embodiments, the sidewall spacers120B,120B′ may include a nitride based sidewall spacer (e.g., comprising SiN) or an oxide-based sidewall spacer (e.g., SiO2, SiOC, etc.). As shown inFIG.1, the position of the drain region107is self-aligned with an edge E2of the sidewall spacer120B. Note the LDD is formed asymmetric so as to position only under the sidewall spacer110B of the first gate110, thereby reducing Rds(on).

Referring toFIG.1, the sidewall spacer110B′ of the first gate110and the sidewall spacer120B′ of the second gate120are merged as a continuous sidewall spacer. The merged portion is referring to the portion of the sidewall spacer110B′ and the sidewall spacer120B′ directly in contact with each other. For example, the merged portion inFIG.1possesses a height h, and each of the first gate110and the second gate120possesses a height H. The height H can be measured as a vertical dimension of the gate electrode110A or120A. In some embodiments, the height h is more than one-half of the height H. For example, in a 40 nm transistor technology node, the height H is about 80 nm, and the height h could be designed to be more than 40 nm, for example, about 50 nm.

The determination of the height h could be related to two factors. First, the deposition operation of the sidewall spacer compatible to the corresponding technology node; and second, the implantation energy used in the subsequent self-aligning source and drain region. As a result, in order to prevent the dopant contamination into the channel region underlying the sidewall spacer110B′ and120B′, the height h of the merged portion shall be thick enough to resist the high energy dopant penetration, and at the same time, the gate electrodes110A and120A shall be separated to distinguish itself from the drain extended structure counterpart.

In some embodiments, a gate width W1of the first gate110is longer than a gate width W2of the second gate120, as illustrated inFIG.1. However, this is not a limitation to the present disclosure since the gate width W1of the first gate110and the gate width W2of the second gate120could be substantially identical. In some embodiments, the smaller gate width among two gales110and120could be the critical dimension of the corresponding technology node. For example, in a 40 nm technology node, the gate width W2of the second gate120could be about 40 nm, and the gate width W1of the first gate110could be either 40 nm or greater than 40 nm.

In some embodiments, a separation D between the gate electrode110A and the gate electrode120A could also be equal to or greater than the critical dimension of the corresponding technology node. For example, the separation D illustrated inFIG.1could be 50 nm in the 40 nm technology node. Compared to the conventional FP or drain extended counterpart, where the separation between an edge of the first gate and an edge of the drain is more than about 300 nm, the same separation in the present disclosure can be controlled under 150 nm. A more compact device pitch can thus be obtained, compared to the FP or drain extended counterpart.

Also note inFIG.1, a thickness T1of the sidewall spacer110B at the side111of the first gate110is substantially identical to a thickness T2of the sidewall spacer120B at the side121of the second gate120. The thickness of the sidewall spacer110B and120B is determined by various deposition conditions. Since the sidewall spacer110B,110B′,120B,120B′ are formed in a single blanket deposition operation followed by a planarization operation, the thickness of the sidewall spacer110B and120B could be substantially identical.

FIG.2is a cross sectional view showing a high power transistor structure20, in accordance with some embodiments of the present disclosure. The difference between the high power transistor structure20and the transistor structure10ofFIG.1is that an additional well region101B is formed surrounding the drain region107. The well region101B possesses an opposite conductive type to the well region101A surrounding the source region105. In some embodiments, the well region101B is an N-well region and the well region101A is a P-well region. For example, N-Well region is formed in substrate100, and extends from the top surface of substrate100down to contact NBL. N-region may be formed, for example, by implanting an n-type impurity into substrate100. P-well region is also formed over NBL, and may extend from the top surface of substrate100to NBL. P-well region may have a concentration between about 1015/cm3and about 1017/cm3, although a higher or a lower concentration may be used. The edge of N-well region contacts the edge of p-well region.

The high power MOS FET20illustrated inFIG.2is an n-type power MOSFET. In accordance with alternative embodiments, a p-type power MOSFET may be formed. The p-type power MOSFET may have a structure similar to the structure shown inFIG.2, except that the conductivity types of regions are inverted from the conductivity types of the like components.

Referring toFIG.3,FIG.3is a top view showing a high power transistor structure20, as illustrated inFIG.2. As previously discussed, the well region101A of a first conductivity type is abutting the well region101B of a second conductivity type in the substrate (not shown inFIG.3). A first stripe110A (or the first gate electrode110A) and a second stipe110B (or the first gate electrode110A) are laterally positioned between a source region105and a drain region107. The first stripe110A includes two sidewall spacers110B and110B′ positioned at opposite sides along the longitudinal direction of the first stripe110A. The second stripe120A includes two sidewall spacers120B and120B′ positioned at opposite sides along the longitudinal direction of the second stripe120A. The sidewall spacer110B′ and the sidewall spacer120B′ are merged or directly in contact with each other. As denoted inFIG.3, a dimpled recess130is shown by dotted line to be the local minimum of the merged portion of the sidewall spacer110B′ and the sidewall spacer120B′. In some embodiments, the dimpled recess130is approximately half of the separation D between the first stripe110A and the second stripe120A.

As opposed to the merged sidewall spacers110B′ and120B′,FIG.3shows an un-merged sidewall spacer110B and an un-merged sidewall spacer120B at the opposite sides of the first and second stripes110A,120A, respectively. The un-merged sidewall spacers110B and120B are closer to the source region105and the drain region107, respectively, than the merged sidewall spacers110B′ and120B′. In some embodiments, due the merging nature of the sidewall spacers110B′ and120B′, the separation D between the first stripe110A and the second stripe120A is smaller than 2 times of the thickness T1of the un-merged sidewall spacer110B. In some embodiments, the separation D between the first stripe110A and the second stripe120A is smaller than 2 times of the thickness T2of the un-merged sidewall spacer120B.

The source region105is self-aligned to the un-merged sidewall spacer110B due to the respective edges of the two along the longitudinal direction are aligned. Same configuration applies to the drain region107and the un-merged sidewall spacer120B.

Referring toFIG.4andFIG.5,FIG.4is a cross sectional view showing a high power transistor structure40, in accordance with some embodiments of the present disclosure.FIG.5is a cross sectional view showing a high power transistor structure50, in accordance with some embodiments of the present disclosure. InFIG.4, the remaining components of power MOS FET40are formed. The exemplary components include source/drain silicide regions, contact etch stop layer, contact plugs141and142, Inter-Layer Dielectric (ILD)140, and metal lines143in bottom metal layer M1. It is appreciated that the contact plug141picking up the drain region107and contact plug142picking up the second gate electrode120A are connected or electrically coupled via the bottom metal layer M1. Bottom metal layer M1is the lowest metal layer of a plurality of metal layers, which may be formed in low-k dielectric layers. For example, metal lines143may be formed in low-k dielectric layer. In accordance with embodiments, the second gate electrode120A is formed under bottom metal layer M1. Furthermore, the top surfaces of second gate electrode120A are lower than the top edges of contact plugs141and142. Contact plugs141and142may be tungsten plugs in some exemplary embodiments.

The coupling of the drain region107and the second gate electrode120A provides identical bias, e.g., connected to a same voltage source, in the aforesaid regions. If the second gate electrode120A and the drain region107are applied to the same bias, extra accumulative charge would be generated underneath the second gate electrode120A, and thus providing a greater accumulative current, obtaining lower Rds(on). Biasing the second gate electrode120A by the source voltage provides a high power MOS FET with a low on-state resistance Rds(on) and low dynamic power dissipation (e.g., low Rds(on)*Qgd vs. Breakdown Voltage). The low dynamic power dissipation provides for good performance during high frequency switching applications.

However, the coupling between the drain region107and the second gate electrode120A through the metal lines143of the bottom metal layer M1is not a limitation to the scope of the present disclosure. As shown inFIG.5, other configuration such as the second gate electrode120A not connected to any bias but in a floating position, is also encompassed in the contemplated scope of the present disclosure. In addition, other configuration such as the second gate electrode120A connected to the first gate electrode110A (not shown), is also encompassed in the contemplated scope of the present disclosure. By electrically coupling the second gate electrode120A to the first gate electrode110A, the second gate electrode120A is biased by the first gate voltage. Biasing the second gate electrode120A by the first gate voltage provides high power MOS FET device with a low Rds(on) vs. breakdown voltage.

According to the present disclosure, the breakdown voltage of high power MOS FET40and50is increased. The power MOS FETs including the second gate120have breakdown voltage significantly higher than the breakdown voltages of the power MOS FETs not including the second gate120. For example, simulation results indicated that a power MOS FET including the second gate120has a breakdown voltage equal to about 30 V, and a similar power MOSFET not including the field plate has a breakdown voltage equal to about 15 V.

FIG.6andFIG.7show the measurement results of the device having the transistor structure described herein.FIG.6is a diagram showing drain current with respect to drain voltage, in accordance with some embodiments of the present disclosure. InFIG.6, curve S1represents a conventional device having a drain self-aligned to a first gate between source region and drain region, and curve S2represents a device having a first gate110and a second gate120between the source region105and the drain region107, as described in the present disclosure. At a fixed operating voltage Vd, the conventional device demonstrate a greater leakage current Id around 1E-9A/μm while the device of the present disclosure produce a lower leakage current Id around 1E-12A/μm.

FIG.7is a diagram showing drain current with respect to gate voltage, in accordance with some embodiments of the present disclosure. InFIG.7, curve C1represents a conventional drain extended structure high power MOS FET, and curve C2represents a device having a first gate110and a second gate120between the source region105and the drain region107, as described in the present disclosure. The reciprocals of slops of the two curves C1and C2are correlated to the on-state resistance Rds(on). It is shown that curve C1demonstrate a greater Rds(on) than the curve C1.

FIGS.8-14are cross sectional views showing a method for manufacturing a high power transistor structure, in accordance with some embodiments of the present disclosure. InFIG.8, an N-well101B and a P-well101A are formed, by implantation operations, in a semiconductor substrate100. For example, a masking layer801is selectively patterned to expose portions of the semiconductor substrate100into which high-energy dopants803are subsequently implanted to form N-well101B. It will be appreciated that the implantation regions as shown are one example of possible implantation regions and that the semiconductor substrate100may comprise other configurations of implantation regions.

InFIG.9, a first polysilicon stripe110A (or the first gate electrode previously described) and a second polysilicon stripe120A (or the second gate electrode previously described) are patterned over the semiconductor substrate100. A separation D between the first polysilicon stripe110A and the second polysilicon stripe120A is predetermined according to aforementioned factors. However, materials such as doped polysilicon, a metal, a metal alloy, or the like can replace the polysilicon for the formation of the first stripe and the second stripe. In a metal gate MOS FET, the polysilicon stripes110A and110B are first patterned and then replace by metal materials in subsequent operations.

InFIG.10, an LDD103is formed by implanting high-energy dopants1003in an implantation operation using the first polysilicon stripe110A as a hardmask. A photoresist layer1001is spun over the semiconductor substrate100so as to cover the separation D between the first polysilicon stripe110A and the second polysilicon stripe120A. The LDD103is self-aligned with a side111of the first polysilicon stripe110A.

InFIG.11, sidewall spacers110B,110B′,120B′, and120B are blanket deposited over the first polysilicon stripe110A and the second polysilicon stripe120A, followed by a removal operation exposing a top surface of the first polysilicon stripe110A and a top surface of the second polysilicon stripe120A from the as-deposited sidewall spacer layer. As previously discussed, the sidewall spacers110B′ and120B′ are merged due to the calculation of a suitable separation D. In other words, the sidewall spacers110B′ and120B′ form a continuous body of a homogeneous material. In various embodiments, the sidewall spacers110B,110B′,120B′ and120B may include a nitride based sidewall spacer (e.g., comprising SiN) or an oxide-based sidewall spacer (e.g., SiO2, SiOC, etc.).

InFIG.12, a source region105and a drain region107are formed in a self-align fashion using the first polysilicon stripe110A, the second polysilicon stripe120A, and the sidewall spacers110B,110B′,120B′, and120B as hard mask. Source region105, drain region107, and pickup regions (not shown) may be formed by implanting an n-type dopant1201such as phosphorous to a concentration between about 1×1019/cm3and about 2×1021/cm3, for example. The implantation energy adopted for the n-type dopant1201can be a determining factor of the separation D since the merged portion of the sidewall spacers110B′,120B′ shall be sufficiently thick in order to prevent the high energy dopant from contaminating the channel region underlying sidewall spacers110B′,120B′.

InFIG.13, contact plug141picking up the drain region107and contact plug142picking up the second gate electrode120A are formed in the ILD140. Also note the contact plug143picking up the first gate electrode110A and contact plug144picking up the source region105are formed in the ILD140.

InFIG.14, contact plug141and contact plug142are connected or electrically coupled via the bottom metal layer M1. Bottom metal layer M1is the lowest metal layer of a plurality of metal layers, which may be formed in low-k dielectric layers. For example, metal lines143may be formed in low-k dielectric layer. In accordance with embodiments, the second gate electrode120A is formed under bottom metal layer M1. Furthermore, the top surfaces of second gate electrode120A are lower than the top edges of contact plugs141and142. Contact plugs141and142may be tungsten plugs in some exemplary embodiments. In another embodiment, the second gate electrode120A is floating. In still another embodiment, the second gate electrode120A is electrically coupled to the first gate electrode110A via the bottom metal layer M1, as described previously.

In some embodiments, a transistor structure includes a substrate, a first gate over the substrate, a second gate over the substrate and laterally in contact with the first gate, a first conductive region of a first conductivity type in the substrate, self-aligning to a side of the first gate, and a second conductive region of the first conductivity type in the substrate, self-aligning to a side of the second gate.

In some embodiments, a high power transistor structure includes a substrate, a source region in the substrate, a drain region in the substrate, a first strip between the source region and the drain region, a second stripe between the source region and the drain region, and a merged sidewall spacer stripe between the first strip and the second stripe.

In some embodiments, a method for manufacturing a transistor structure includes patterning a first polysilicon stripe and a second polysilicon stripe separated from the first polysilicon stripe by a predetermined distance on a substrate, forming a sidewall spacer over the first polysilicon stripe and the second polysilicon stripe, wherein the predetermined distance is so determined to render a continuous sidewall spacer between the first polysilicon stripe and the second polysilicon stripe, and forming a source region self-aligning to the first polysilicon stripe and a drain region self-aligning to the second polysilicon stipe by an implantation operation.

Although the present invention and its advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims. For example, many of the processes discussed above cancan be implemented in different methodologies and replaced by other processes, or a combination thereof.

Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the disclosure of the present invention, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed, that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the present invention. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps.