Patent ID: 12235558

Specific embodiments of the present disclosure have been shown by means of the above accompanying drawings, and will be described in more detail below. These accompanying drawings and textual descriptions are not intended to limit the scope of the concept of the present disclosure by any means, but are used to illustrate the concept of the present disclosure to those skilled in the art with reference to the specific embodiments.

DETAILED DESCRIPTION

For clearer descriptions of the objectives, technical solutions, and advantages of the present disclosure, the embodiments of the present disclosure are described in detail hereinafter with reference to the accompanying drawings.

With the development of virtual reality (VR) technologies, there is an increasing demand for display panels with high pixels per inch (PPI) and a large aperture ratio. The aperture ratio may be a ratio of the area of a part that allows light to transmit in a sub-pixel region to the area of the whole sub-pixel. The larger the aperture ratio of the display panel is, the higher the efficiency of light emitted from the interior of the display panel passing through the film layers of the display panel is.

In the related art, a display panel includes a substrate, a liquid crystal layer disposed on the substrate, and a black matrix disposed on the side, distal from the substrate, of the liquid crystal layer. The substrate may include a pixel electrode, a thin film transistor, and an insulating layer disposed between the pixel electrode and the thin film transistor. The thin film transistor includes a source and a drain; and the pixel electrode is connected to the source or the drain of the thin film transistor through a first via hole in the insulating layer, such that the pixel electrode is controlled through the thin film transistor. The pixel electrode may be configured to drive liquid crystals in the liquid crystal layer.

However, due to the relatively large size of the first via hole in the insulating layer, the film layer above the insulating layer is relatively poor in flatness. For example, liquid crystals in the liquid crystal layer above the first via hole cannot deflect normally, resulting in light leakage of the display panel. The liquid crystals that cannot deflect normally can only be shielded by using a black matrix, so as to prevent light leaked out of the liquid crystal layer from exiting the display panel. However, the black matrix with the shielding effect reduces a light-emitting area of the display panel, thereby reducing the aperture ratio of the display panel.

Part and all of the above technical problems can be optimized by the following limited embodiments of the present disclosure.

The substrate according to the embodiments of the present disclosure may be applied to a display region of a display panel.

The substrate according to the embodiments of the present disclosure may be applied to a small-sized mobile device, a notebook computer (NB), a tablet computer, a small and medium-sized monitor (MNT), a large and medium-sized television (TV), a large and medium-sized MNT and other products.

The substrate according to the embodiments of the present disclosure may be applicable to the display field or the chip field. The display field may be technical fields of liquid crystal display (LCD) panels, organic light-emitting diode (OLED) display panels, quantum dot light-emitting diodes (QLED) display panels, micro light-emitting diode (Micro LED) display panels, sensors and others.

FIG.1is a schematic structural diagram of a substrate according to an embodiment of the present disclosure;FIG.2is a schematic diagram of partial film layers of the substrate shown inFIG.1; andFIG.3is a schematic structural diagram of sections of the substrate shown inFIG.1along A1-A2and B1-B2. The substrate10may include a base substrate101and a plurality of sub-pixel structures100. The sub-pixel structures100may be arranged in an array on the base substrate101. The sub-pixel structure100may include a thin film transistor102, an insulating layer103, a pixel electrode104and a filling block105.

FIG.2shows six film layers along the direction distal from the base substrate101in the substrate10. The six film layers include: an active layer1023, a gate line1024, and source and drain (a source1021and a drain1022) of the thin film transistor102, an insulating layer103and a first via hole1031therein, a filling block105, and a pixel electrode104.

The thin film transistor102may be disposed on the base substrate101, and may include a source1021and a drain1022. The source1021and the drain1022may be disposed on the same layer and may be prepared by the same patterning process. It should be noted that, in the embodiments of the present disclosure, the function of the “source” and the function of the “drain” are interchangeable sometimes in the case that a thin film transistor with opposite polarity is used or in the case that the direction of current changes in a circuit. Therefore, in this description, the “source” and the “drain” may be interchangeable, which is not limited in the embodiments of the present disclosure.

The insulating layer103may be disposed on the side of the thin film transistor102distal from the base substrate101, and a first via hole1031may be formed in the insulating layer103. The pixel electrode104may be disposed on the side of the insulating layer103distal from the base substrate101, and may be electrically connected to either the source1021or the drain1022of the thin film transistor102through the first via hole1031. In this way, the on/off state of the pixel electrode104can be controlled through the thin film transistor102. The insulating layer103may be a single-layer structure or a multi-layer structure.

The filling block105may be disposed on the side of the pixel electrode104distal from the base substrate101, and may be disposed at the first via hole1031. The filling block105may be disposed in the first via hole1031to fill up the first via hole1031, such that the film layer on the side of the insulating layer103distal from the base substrate101has good flatness.

For example, the film layer on the side of the insulating layer103distal from the base substrate101includes a liquid crystal layer in the display panel. As the filling block105is disposed at the first via hole1031, the liquid crystal layer has good flatness, thereby avoiding the phenomenon of light leakage caused by the abnormal deflection of liquid crystals in the liquid crystal layer disposed on a side, distal from the base substrate, of the first via hole1031. Therefore, the aperture ratio of the display panel can be increased without arranging a black matrix on the side, distal from the base substrate101, of the liquid crystal layer above the first via hole1031.

In summary, the embodiment of the present disclosure provides a substrate. The thin film transistor in the substrate may be electrically connected to the pixel electrode through the first via hole in the insulating layer. In addition, by arranging the filling block in the first via hole of the insulating layer, the flatness of the film layer above the first via hole of the insulating layer is good, thereby improving the quality of the film layer above the insulating layer.

Optionally,FIG.4is a schematic structural diagram of another substrate according to an embodiment of the present disclosure;FIG.5is a schematic diagram of partial film layers of the substrate shown inFIG.4; andFIG.6is a schematic structural diagram of sections of the substrate shown inFIG.4along C1-C2and D1-D2.

FIG.5shows eight film layers along the direction distal from the base substrate101in the substrate10. The eight film layers include: a light shielding layer107, an active layer1023, a gate line1024and a source and a drain (a source1021and a drain1022) of the thin film transistor102, a connecting line106, an insulating layer103and a via first hole1031therein, a filling block105, and a pixel electrode104.

The thin film transistor102may further include the active layer1023and the gate line1024. The active layer1023may be disposed on the side, proximal to the base substrate101, of the source1021and the drain1022, and the active layer1023is electrically connected to the source1021and the drain1022. The gate line1024is disposed on the side, distal from the base substrate101, of the active layer1023. An orthographic projection of the gate line1024on the base substrate101is overlapped with an orthographic projection of the active layer1023on the base substrate101.

The gate line1024is a gate of the thin film transistor102. The plurality of sub-pixel structures100may include a row of sub-pixel structures100. Gates of the thin film transistors102in one row of sub-pixel structures100may be electrically connected to each other to form the gate line1024.

FIG.7is a schematic structural diagram of a laminated structure of partial film layers in the substrate shown inFIG.5.FIG.7shows the schematic diagram of the laminated structure of the active layer1023, the source1021and the drain of the thin film transistor102(in the schematic diagram of the laminated structure inFIG.7, the connecting line106shields the drain in the direction perpendicular to the base substrate101, so the drain is not marked inFIG.7), the gate line1024, the connecting line106, and the first via hole1031in the active layer103. InFIG.7, the connecting line106is electrically connected to the drain at position106a.

Referring toFIG.7, an orthographic projection of the center of the first via hole1031on the base substrate101may be between orthographic projections of two active layers1023adjacent in the first direction f1on the base substrate101. The first direction f1may be parallel to the extension direction of the gate line1024. Compared with the related art in which the orthographic projection of the first via hole1031on the base substrate101may be between orthographic projections of two active layers1023adjacent in the third direction f3(the third direction f3may be perpendicular to the first direction, and may also be the length direction of the active layer1023) on the base substrate101, in the embodiments of the present disclosure, the orthographic projection of the first via hole1031on the base substrate101is set between the orthographic projections of two active layers1023adjacent in the first direction f1on the base substrate101, which can reduce the distance between active layers adjacent in the third direction f3. Therefore, the density of the active layers1023in the third direction f3can be increased, thereby increasing the density of the thin film transistors102in the third direction f3and the corresponding PPI of the thin film transistors102and increasing the PPI of the display panel including the substrate10according to the embodiments of the present disclosure.

Optionally, the substrate10may further include a connecting line106, and the connecting line106may be disposed on the side, distal from the base substrate101, of the gate line1024. An orthographic projection of one end1061of the connecting line106on the base substrate101may be overlapped with the orthographic projection of the first via hole1031on the base substrate101, and an orthographic projection of the other end1062of the connecting line106on the base substrate101may be overlapped with an orthographic projection of a first electrode on the base substrate101. The first electrode may be the source electrode1021or the drain electrode1022that is electrically connected to the pixel electrode104in the thin film transistor102.

The material of the connecting line106may include a light-transmitting conductive material, such that the light transmittance of the substrate10can be improved, thereby increasing the aperture ratio of the display panel including the substrate10. For example, the light-transmitting conductive material of the connecting line106may include indium tin oxide (ITO).

The material of the pixel electrode104may also include a light-transmitting conductive material, and may also be ITO.

As shown inFIG.7, the extension direction f4of the connecting line106may make an acute angle α with the extension direction f1of the gate line1024, such that one end of the connecting line106may be electrically connected to the pixel electrode104, and the other end of the connecting line106may be electrically connected to the first electrode of the thin film transistor102. One end of the connecting line106may be electrically connected to the pixel electrode104through the first via hole1031.

It should be noted that since the extension direction of the connecting line106intersects the extension directions of positions C1-C2and D1-D2inFIG.6, in the schematic structural diagram of the sections of the substrate at two different positions in the same gazing direction, the connecting line106, the connecting line106shown in the schematic structural diagram of section along C1-C2and the connecting line106shown in the schematic structural diagram of the section along D1-D2are two parts of the same connecting line106, and these two parts of the connecting line106are electrically connected, such that the pixel electrode104is electrically connected to either the source1021or the drain1022of the thin film transistor102through the first via hole1031and the connecting line106.

Optionally, as shown inFIG.6, the substrate may further include a light shielding pattern107which may be disposed on the side, proximal to the base substrate101, of the active layer1023. An orthographic projection of the light shielding pattern107on the base substrate101is overlapped with that the orthographic projection of the active layer1023on the base substrate101. The light shielding pattern107may be configured to block light (such as light emitted from a backlight source on the display panel) from entering the active layer1023, so as to prevent light from affecting the stability of the active layer1023. The light shielding pattern107may be further configured to shield electrical properties of the active layer1023from the adverse influence of the film layer on the side of the light shielding pattern107distal from the active layer1023under the action of an electric field.

The surface of the light shielding pattern107facing the base substrate101is a reflective surface. When external light (e.g., light emitted from the backlight source on the display panel) irradiates the light shielding pattern107, the light shielding pattern107can not only block the external light from irradiating the active layer1023, but also reflect the external light to the substrate10or other film layers of the display panel. The other film layers can reflect the external light again, and at least part of the external light is reflected to the side of the light shielding pattern107distal from the base substrate101. That is, at least part of the external light can be reflected out of the light-emitting surface of the display panel. Therefore, the backlight utilization rate of the display panel can be increased.

Optionally, a fourth insulating layer112may be disposed between the light shielding pattern107and the active layer1023. The fourth insulating layer112may include at least one of an inorganic insulating layer and an organic insulating layer. For example, the fourth insulating layer112may be a composite film layer including an inorganic insulating layer and an organic insulating layer, and the organic insulating layer may be disposed on the side, distal from the base substrate101, of the inorganic insulating layer. In this way, the fourth insulating layer112can protect the light shielding pattern107by means of the inorganic insulating layer so as to prevent the light shielding pattern from being damaged due to the corrosion by external moisture. The fourth insulating layer112may also improve the flatness of the active layer1023on the side of the fourth insulating layer112distal from the base substrate101by means of the organic insulating layer, so as to improve the film quality of the active layer1023.

Optionally,FIG.8is a schematic structural diagram of a light shielding pattern according to an embodiment of the present disclosure, and shows a top view of the light shielding pattern and a schematic diagram of the section along E1-E2. The light shielding pattern107may include a composite film layer. The light shielding pattern107may include a first base1073, and a reflective layer1074disposed on the side, facing the base substrate101, of the first base1073. The material of the first base1073includes at least one of titanium (Ti), tin (Sn) and molybdenum (MO), and the material of the reflective layer1074includes aluminum (Al). By providing the first base1073, the flatness and the film quality of the light shielding pattern107are better; and by providing the reflective layer1074, the reflectivity of the light shielding pattern107is higher, such that the durability of the light shielding pattern107is improved in the case that the reflectivity of the light shielding pattern107is higher.

Or, in an optional implementation, the material of the light shielding pattern107may include an aluminum alloy. Since the aluminum alloy material may have a better light reflecting effect while possessing good film quality, the light shielding pattern107may be of a single-layer structure to simplify the manufacturing process of the light shielding pattern107.

For example, as shown in Table 1 below, Table 1 shows the related data of actually tested transmittance and aperture ratio of the light shielding pattern107made of different materials.

TABLE 1Aperture ratios of light shielding patternSize (μm) of light shielding pattern in the6.29.210.712.213.7first directionSize μm) of light shielding pattern in the2.31.81.83.33.3second directionAperture ratio of light shielding pattern38.80%32.50%26.60%12.90%9.20%Transmittance of light shielding pattern24.20%21.50%18.10%11.00%8.50%made of molybdenumTransmittance of light shielding pattern26.90%24.00%20.40%12.10%9.70%made of laminated aluminum/titaniumTransmittance of light shielding pattern27.60%24.80%21.10%12.70%9.90%made of laminated aluminum/molybdenumPercentage of increase of aperture ratio of10.80%11.40%12.50%10.50%14.40%laminated aluminum/titanium comparedwith molybdenumPercentage of increase of aperture ratio of13.90%15.50%16.50%15.50%16.60%laminated aluminum/molybdenumcompared with molybdenum

As can be seen from Table 1, by providing the light shielding pattern as a laminated structure including the reflective layer, the aperture ratio of the light shielding pattern is better, such that the aperture ratio of the display panel can be increased.

Optionally, as shown inFIG.5andFIG.6, the active layer1023may include a source contact portion10231, a drain contact portion10232, and an intermediate portion10233disposed between the source contact portion10231and the drain contact portion10232. The size of the source contact portion10231in the first direction f1and the size of the drain contact portion10232in the first direction f1are greater than the size of the intermediate portion10233in the first direction f1, and an orthographic projection of the active layer1023on the base substrate101may be in a shape with two wide ends and a narrow middle, such that the source contact portion10231of the active layer1023and the source1021of the thin film transistor102can be electrically connected better, and the drain contact portion10232of the active layer1023and the drain1022of the thin film transistor102can be electrically connected better.

The orthographic projection of the active layer1023on the base substrate101is at least partially overlapped with the orthographic projection of the light shielding pattern107on the base substrate101. Furthermore, the orthographic projection of the active layer1023on the base substrate101is within the orthographic projection of the light shielding pattern107on the base substrate101, such that the stability of the active layer1023is further prevented from being affected by external light, and the light shielding pattern107can further shield electrical properties of the active layer1023from the adverse influence of the film layer on the side of the light shielding pattern107distal from the active layer1023under the action of an electric field.

Optionally, as shown inFIG.8, the light shielding pattern107may include a plurality of light shielding portions1071and a plurality of connecting portions1072, and the light shielding portion1071may be connected to the connecting portion1072. Two adjacent light shielding portions1071may be disposed on two sides of the connecting portion1072, respectively. One ends of the two light shielding portions1071are connected to two sides of the connecting portion1072, respectively. The light shielding portion1071and the connecting portion1072may be disposed on the same layer and may be manufacturing by a single patterning process.

The light shielding portion1071may be extended along the first direction f1, and the plurality of light shielding portions1071may be arranged along the second direction f2. The connecting portions1072are disposed on two sides of the light shielding portion1071in the second direction f2. The connecting portion1072is extended along the second direction f2, and the plurality of connecting portions1072are arranged along the first direction f1. The second direction f2intersects the first direction f1. Since film layers with low light transmittance, such as the active layer1023, the source1201, the drain1022and the gate line1024, are disposed on the side, distal from the base substrate101, of the light shielding portion1071and the connecting portion1072, and are overlapped with the light shielding pattern107, by providing the light shielding portions1072and the connecting portions1071connecting the light shielding portions1072in the light shielding pattern107, the reflective area of the light shielding pattern107can be increased on the premise that the light shielding pattern107does not adversely affect the aperture ratio of the display panel. Therefore, the backlight utilization ratio of the display panel can be increased, thereby increasing the aperture ratio of the display panel.

Optionally,FIG.9is a schematic structural diagram of laminated gate line, active layer and light shielding pattern according to an embodiment of the present disclosure. Referring toFIG.6andFIG.9, edges, in the first direction f1, of an orthographic projection of the connecting portion1072of the light shielding pattern107on the base substrate101are flush with edges, in the first direction f1, of orthographic projections of the source contact portion10231and the drain contact portion10232of the active layer1023on the base substrate101. The light transmittance of the source contact portion10231and the drain contact portion10232of the active layer1023is relatively low. The connecting portion1072of the light shielding pattern107is overlapped with the source contact portion10231and the drain contact portion10232of the active layer1023in the direction perpendicular to the base substrate101and edges of the connecting portion1072in the first direction f1are flush with edges of the source contact portion10231and the drain contact portion10232in the first direction f1, which can prevent the connecting portion1072of the light shielding pattern107from adversely affecting the aperture ratio of the display panel.

Optionally, as shown inFIG.6andFIG.9, an edge, in the second direction f2, of an orthographic projection of the light shielding portion1071of the light shielding pattern107on the base substrate101is flush with an edge, in the second direction f2, of an orthographic projection of the gate line1024on the base substrate101. The light transmittance of the gate line1024is relatively low. The light shielding portion1071of the light shielding pattern107is overlapped with the gate line1024in the direction perpendicular to the base substrate101and the edge of the light shielding portion1071in the first direction f1is flush with the edge of the gate line1024in the first direction f1, which can prevent the light shielding portion1071of the light shielding pattern107from adversely affecting the aperture ratio of the display panel.

FIG.10is a schematic structural diagram of another substrate according to an embodiment of the present disclosure;FIG.11is a schematic diagram of partial film layers of the substrate shown inFIG.10;FIG.12is a schematic structural diagram of sections of the substrate shown inFIG.10along G1-G2and H1-H2; andFIG.13is a schematic structural diagram of a section of the substrate shown inFIG.10along K1-K2. Since many film layers are laminated inFIG.10, the position of K1-K2is marked in the schematic structural diagram of the film layers shown inFIG.11. Referring toFIG.10toFIG.12, the substrate10may further include a data line108. The data line may be disposed on the side, distal from the base substrate101, of the source1021and the drain1022of the thin film transistor102.

The insulating layer103may include a first insulating layer1032and a planarization layer1033which are sequentially laminated in the direction distal from the base substrate101. The first insulating layer1032may be disposed on the side, distal from the base substrate101, of the source1021and the drain1022of the thin film transistor102, and the planarization layer1033is disposed on the side of the data line108distal from the base substrate101. The data line108may be disposed between the first insulating layer1032and the planarization layer1033.

A second via hole10321may be formed in the first insulating layer1032, and the data line108may be electrically connected to either the source1021or the drain1022through the second via hole10321.

Optionally, the insulating layer103may further include a second insulating layer1034disposed between the first insulating layer1032and the planarization layer1033, and the second insulating layer1034may be disposed on the side of the data line108distal from the base substrate101. The second insulating layer1034may be configured to protect the data line108, so as to avoid a short circuit between the data line108and the pixel electrode104.

Optionally, as shown inFIG.11, the extension direction of the data line108may be parallel to the second direction f2, and the orthographic projection of the connecting portion1072of the light shielding pattern107on the base substrate101is within an orthographic projection of the data line108on the base substrate101. The extension direction of the connecting portion1072of the light shielding pattern107may be the same as the extension direction of the data line108. Since the light transmittance of the data line108is relatively low, the data line108covers the connecting portion1072of the light shielding pattern107in the direction perpendicular to the base substrate101, such that the connecting portion1072of the light shielding pattern107is prevented from adversely affecting the light transmittance of the substrate10, thereby preventing the connecting portion1072of the light shielding pattern107from adversely affecting the aperture ratio of the display panel.

Optionally,FIG.14is a schematic structural diagram of still another substrate according to an embodiment of the present disclosure. Referring toFIG.13andFIG.14, the base substrate101may further include a common electrode pattern109, which may be disposed on the side of the pixel electrode104distal from the base substrate101. The pixel electrode104may drive liquid crystals in the liquid crystal layer of the display panel together with the common electrode pattern109. The number of film layers in the substrate10shown inFIG.14is less than the number of film layers in the substrate10shown inFIG.13, such that the processes for manufacturing the substrate10can be simplified.

The common electrode pattern109may include a first electrode portion1091. The material of the first electrode portion1091may include metal. The first electrode portion1091includes a plurality of first strip-shaped electrodes m1. The orthographic projection of the connecting portion of the light shielding pattern107on the base substrate101may be within the orthographic projection of the first electrode portion1091on the base substrate101. Since the sub-pixel structures in the display panel with high PPI have a relatively small size and the distance between adjacent sub-pixel structures is relatively short, light emitted from the sub-pixels is prone to cross color, which adversely affects the display effect of the display panel. The first electrode portion1091can prevent light emitted from a region where a sub-pixel structure100of one color is disposed from being exited from a region where an adjacent sub-pixel structure100of a different color is disposed, such that the cross-color problem of the display panel can be solved.

In addition, the connecting portion1072of the light shielding pattern107is overlapped with the first electrode portion1091in the direction perpendicular to the base substrate101. Furthermore, the orthogonal projection of the connecting portion1072on the base substrate101may be within the orthogonal projection of the first electrode portion1091on the base substrate101. By setting the connecting portion1072and the first electrode portion1091with relatively low light transmittance to be overlapped in the direction perpendicular to the base substrate101, the light-tight area of the substrate10can be reduced, thereby increasing the aperture ratio of the display panel.

Optionally, as shown inFIG.13, the orthographic projections of the data line108and the active layer1023on the base substrate101may be within the orthographic projection of the first electrode portion1091on the base substrate101. Since the extension direction of the data line108, the length direction of the active layer1023and the extension direction of the first electrode portion1091may be parallel to the second direction f2, and the light transmittance of the data line108, the light transmittance of the active layer1023and the light transmittance of the first electrode portion1091is relatively low, the data line108, the active layer1023and the first electrode portion1091with the relatively low light transmittance are overlapped in the direction perpendicular to the base substrate101in the embodiments of the present disclosure, such that the light-tight area of the substrate10is further reduced, thereby increasing the aperture ratio of the display panel.

Optionally,FIG.15is a schematic structural diagram of laminated light shielding pattern, active layer and common electrode pattern according to an embodiment of the present disclosure.FIG.15shows the schematic structural diagram P1of a laminated structure including the common electrode pattern109in the embodiments of the present disclosure, and the schematic structural diagram P2of a laminated structure including a common electrode pattern109A in the related art. The film structures indicated by the arrows inFIG.15are the structures of the film layer of the common electrode pattern109in the embodiments of the present disclosure and the structures of the film layer of the common electrode pattern109A in the related art, respectively.

The common electrode pattern109may further include a transparent electrode layer1092, and the first electrode portion1091may be disposed on the side of the transparent electrode layer1092proximal to the base substrate101. The transparent electrode layer1092may be of a whole layer structure. In the common electrode pattern109, the transparent electrode layer1092of the whole layer structure and the plurality of first strip-shaped electrodes m1of the first electrode portion1091are be laminated, such that the common electrode pattern109is a slit electrode. By arranging slits in different directions and changing the pattern of the slit electrode, the liquid crystals in the display panel may be arranged in multiple directions in the horizontal direction of the pixel region, which can improve the uniformity of the luminance of an image displayed on the display panel, and reduce the color shift of the display panel. That is, the electric field generated by the slit electrodes on the same plane and the electric field generated by the transparent electrode layer1092of the whole layer structure may generate a multi-dimensional electric field, such that the liquid crystals between the slit electrodes and directly above the slit electrodes can rotate, thereby improving the working efficiency of the liquid crystals in the display panel, and increasing the light transmittance of the liquid crystals in the display panel.

Compared with the related art in which a plurality of openings are formed in the common electrode pattern109A to form slit electrodes, the common electrode pattern109according to the embodiments of the present invention can not only form the slit electrodes, but also prevent light emitted from a region where a sub-pixel structure100of one color is disposed from being exited from a region where an adjacent sub-pixel structure100of a different color is disposed, such that the cross-color problem of the display panel can be solved, thereby improving the display effect of the display panel.

Optionally,FIG.16is a schematic structural diagram of still another substrate according to an embodiment of the present disclosure. The common electrode pattern109may further include a transparent electrode layer1092, and the first electrode portion1091is disposed on the side of the transparent electrode layer1092distal from the base substrate101. In this way, the transparent electrode layer1092of the whole layer structure and the plurality of first strip-shaped electrodes m1of the first electrode portion1091may be laminated, such that the common electrode pattern109can be a slit electrode, and meanwhile, the transparent electrode layer1092can protect the first electrode portion1091to prevent the first electrode portion1091from being damaged due to the corrosion by external moisture. The material of the transparent electrode layer1092may include indium tin oxide.

Optionally,FIG.17is a schematic structural diagram of still another substrate according to an embodiment of the present disclosure. The common electrode pattern109may further include a second electrode portion1093. The material of the second electrode portion1093may include a transparent conductive material; and the second electrode portion1093may include a plurality of second strip-shaped electrodes m2, and the first strip-shaped electrodes m1and the second strip-shaped electrodes m2are alternately arranged. By arranging the second strip-shaped electrodes m2and the first strip-shaped electrodes m1alternately, the common electrode pattern109may be a slit electrode. In addition, the second strip-shaped electrodes m2and the first strip-shaped electrodes m1may be disposed on the same layer, such that the size of the substrate10in the direction perpendicular to the base substrate101can be reduced, thereby reducing the thickness of the display panel including the substrate10. The material of the second electrode portion1093may include indium tin oxide.

Optionally, as shown inFIG.12, the substrate10may further include a compensation electrode111, and the insulating layer103may include a first insulating layer1032, a third insulating layer1035, a second insulating layer1034and a planarization layer1033which are sequentially laminated in the direction distal from the base substrate101. The first insulating layer1032may be disposed on the side, distal from the base substrate101, of the source1021and the drain1022. The compensation electrode111may be disposed between the first insulating layer1032and the third insulating layer1035, the data line108may be disposed between the third insulating layer1035and the second insulating layer1034, and the common electrode pattern109may be disposed on the side of the planarization layer1033distal from the base substrate101.

The compensation electrode111is electrically connected to the common electrode pattern109, and an orthogonal projection of the compensation electrode111on the base substrate101is overlapped with the orthogonal projection of the data line108on the base substrate101. Since an input signal of the compensation electrode111is a stable common electrode signal (Vcom), i.e., the charge distribution on the compensation electrode111is relatively stable, but the voltage on the data line108changes, such that shielding capacitance is generated between the compensation electrode111and the data line108. Under the electrostatic shielding effect, the charge distribution on the data line108can be driven such that charges on the data line108is redistributed and stabilized, thereby effectively shielding coupling capacitance and reducing an adverse risk that the data line108interferes with other signal lines or film layers (e.g., the pixel electrode104).

Optionally, as shown inFIG.3, at least one of the plurality of sub-pixel structures100includes a first filling block105protruding from the first via hole1031. The part, protruding from the first via hole1031, of the first filling block105may be in contact with a support column in the liquid crystal layer, to prevent the support column in the liquid crystal layer from being displaced. The liquid crystal layer of the display panel may include an upper substrate, a lower substrate and liquid crystals disposed between the upper substrate and the lower substrate. Since the support column may be arranged between the upper substrate and the lower substrate and the support column may play an isolation role, the gap between the upper substrate and the lower substrate can be kept uniformly. The first filling block105may serve as a barrier structure of the support column, to prevent the liquid crystal layer of the display panel from being damaged due to the displacement of the support column.

Optionally, as shown inFIG.3, the distance L between the surface s1of the side of the first filling block105distal from the base substrate101and the surface s2of the side of the insulating layer103distal from the base substrate101in the thickness direction f0of the substrate (the thickness direction of the substrate may be a direction perpendicular to the base substrate101) is greater than 0 μm and less than 1 μm. In this way, the flatness of the film layer on the side of the insulating layer103distal from the base substrate101is better. In addition, the part, above the insulating layer103, of the first filling block105can block the support column, thereby preventing the display effect from being adversely affected due to damage of the structure of the substrate caused by random sliding of the support column.

Optionally,FIG.18is a schematic structural diagram of a thin film transistor according to an embodiment of the present disclosure. The intermediate portion10233of the active layer1023of the thin film transistor102includes two lightly drain doping (LDD) regions a1and a channel region b1, and the LDD regions a1may be disposed on two sides of the channel region b1. The channel region b1may be an undoped region. The source contact portion10231and the drain contact portion10232may be heavily drain doping (HDD) regions c1, the source1021and the drain1022are electrically connected to the HDD regions c1of the active layer1023, such that the contact resistance can be reduced. Therefore, the source1021and the drain1022may be in good electrical connection to the active layer1023, and thus the thin film transistor has better electrical characteristics.

Here, the ion implantation concentration in the LDD region may range from 1×1013ions/cm2to 9×1013ions/cm2, and the ion implantation concentration in the HDD region may range from 1×1014ions/cm2to 9×1014ions/cm2. Phosphorus ions may be used as doped ions during ion implantation.

Meanwhile, as the semiconductor region of the thin film transistor102becomes shorter and shorter, it's likely to cause a short-channel effect, which results in abnormal characteristics of the thin film transistor102, such as higher cut-off voltage Vth and higher leakage current Ioff. Addition of the LDD region a1between the HDD region c1and the undoped region (channel region b1) is equivalent to connection of a resistor in series between the source1021and the drain1022and the channel region b1. Therefore, the horizontal electric field of the channel is reduced and the leakage current is inhibited, thereby avoiding the above abnormalities of the thin film transistor102.

An orthographic projection of the channel region b1on the base substrate101may be within the orthographic projection of the light shielding portion1071on the base substrate101, and orthographic projections of the source contact portion10231, the drain contact portion10232and the two LDD regions a1on the base substrate101are within the orthographic projection of the connecting portion1072on the base substrate101.

The thin film transistor102may include a single-gate thin film transistor. By arranging two LDD regions a1with high resistance at preset positions on two sides of the channel region b1of the thin film transistor102, the acceleration distance of electrons in the active layer1023under the action of an electric field can be shortened, and thus the leakage current of the thin film transistor can be inhibited. In the embodiments of the present disclosure, the length of the LDD region a1may be controlled the electric field strength of the channel region b1of the substrate10, or based on the characteristic requirements, such as an on-state current or off-state current of the thin film transistor (such as a low-temperature polysilicon thin film transistor), such that the aperture ratio of the display panel can be increased on the premise of meeting the characteristic requirements of the channel region b1of the thin film transistor102.

Optionally, as shown inFIG.12, the intermediate portion10233includes three LDD regions a1and two channel regions b1which are alternately arranged. Orthographic projections of the two channel regions b1and an orthographic projection of the LDD region a1between the two channel regions b1on the base substrate101are within the orthographic projection of the light shielding portion1071on the base substrate101, and an orthographic projection of the source contact portion10231on the base substrate101, an orthographic projection of the drain contact portion10232on the base substrate101and orthographic projections of the LDD regions a1on two sides of the two channel regions b1are within the orthographic projection of the connecting portion1072on the base substrate101. The thin film transistor102may include a dual-gate thin film transistor. By arranging the plurality of LDD regions a1with high resistance at present positions between and on the two sides of the channel regions b1of the thin film transistor102, the acceleration distance of electrons in the active layer1023under the action of the electric field can be shortened, such that the leakage current of the thin film transistor can be inhibited.

One of the LDD regions a1may be disposed in the middle of the active layer1023in the direction parallel to the plate surface of the base substrate101. In this way, when electrons are transmitted in the two undoped regions (channel regions b1) whose orthographic projections on the base substrate101overlap the orthographic projection of the gate line1024on the base substrate101, the electrons inevitably pass through the LDD region a1between the two undoped regions (channel regions b1), which can reduce the transmission speed and kinetic energy of the electrons, thereby inhibiting the leakage current.

In the embodiments of the present disclosure, the length of the LDD region a1can be controlled based on the characteristic requirements, such as the on-state current or off-state current, of the thin film transistor (e.g., a low-temperature polysilicon thin film transistor) of the substrate10, so as to increase the aperture ratio of the display panel on the premise of meeting the characteristic requirements of the channel regions of the thin film transistor102. Since the orthographic projections of the two channel regions b1on the base substrate101and the orthographic projection of the LDD region a1between the two channel regions b1on the base substrate101are within the orthographic projection of the light shielding portion1071on the base substrate101, when the sizes of the two channel regions b1and the size of the LDD region a1between the two channel regions b1are relatively small, the size of the light shielding portion1071can be correspondingly reduced, and thus the aperture ratio of the display panel can be reduced. For example, the channel region b1of the thin film transistor102may have a width less than 1.5 μm and a length less than 2 μm.

Optionally,FIG.19is a schematic structural diagram of still another substrate according to an embodiment of the present disclosure.FIG.19shows a schematic diagram of a laminated structure of the thin film transistor102and the light shielding pattern107and a schematic structural diagram of a section of the laminated structure along the position J1-J2.FIG.19further shows the shape of a light shielding pattern mask107B used for manufacturing the light shielding pattern107of this shape. When the mask is used, it may be by using an opaque pattern template to cover a selected region of a specified film. The selected region may be free of irradiation by exposure light, such that etching or diffusion in subsequent steps may only be performed in regions other than the selected region. The size of the light shielding pattern mask107B may be larger than the size of the light shielding pattern107, and a convex region107B1may be formed at the edge of the light shielding pattern mask107B, such that the acquired light shielding pattern may have the shape of the light shielding pattern107shown inFIG.19.

The intermediate portion10233may include three LDD regions a1and two channel regions b1, and the LDD regions a1and the channel regions b1are alternately arranged.

Orthographic projections of the two channel regions b1on the base substrate101and an orthographic projection of the LDD region a1between the two channel regions b1on the base substrate101are within the orthographic projection of the light shielding portion1071on the base substrate101, and the orthographic projection of the connecting portion1072on the base substrate101is within orthographic projections of the source contact portion10231, the drain contact portion10232and the LDD regions a1on two sides of the two channel regions b1on the base substrate101. The connecting portion1072may only be connected to the light shielding portion1071disposed at one end of the connecting portion1072, to reduce the size of the connecting portion1072. Therefore, on the premise that the active layer1023has a smaller size, the size of the connecting portion1072can be further reduced, thereby further increasing the aperture ratio of the display panel.

Optionally,FIG.20is a schematic structural diagram of another thin film transistor according to an embodiment of the present disclosure. The intermediate portion10233includes four LDD regions a1, two channel regions b1and a HDD region c1. The LDD regions a1and the channel regions b1are alternately arranged, and the HDD region c1is disposed between the two LDD regions a1which are between the two channel regions b1. An orthographic projection of the intermediate portion10233on the base substrate101is within the orthographic projection of the light shielding portion1071on the base substrate101. With this arrangement, the size of the thin film transistor102can be effectively reduced, and thus the aperture ratio of the display panel can be increased. In addition, the overall power consumption can be reduced while the display luminance is improved.

Optionally, the substrate10may further include a gate insulating layer113, a fifth insulating layer114and a sixth insulating layer115. The gate insulating layer113may be disposed between the active layer1023and the gate line1024, the fifth insulating layer114may be disposed between the gate line1024and the connecting line106, and the sixth insulating layer115may be disposed between the filling block105and the common electrode pattern109.

In summary, the embodiment of the present disclosure provides a substrate. The thin film transistor in the substrate can be electrically connected to the pixel electrode through the first via hole in the insulating layer. In addition, by arranging the filling block in the first via hole of the insulating layer, the flatness of the film layer above the first via hole of the insulating layer is good, thereby improving the quality of the film layer above the insulating layer.

FIG.21is a flowchart of a method for manufacturing a substrate according to an embodiment of the present disclosure. The method may be applied to manufacture the substrate described in any of the above embodiments. Referring toFIG.21, the method may include the following steps.

In step201, a base substrate is acquired.

In step202, a plurality of sub-pixel structures are formed on the base substrate, wherein the plurality of sub-pixel structures are arranged in an array on the base substrate.

Here, as shown inFIG.22, step202may include the following four sub-steps.

In sub-step2021, a thin film transistor is formed on the base substrate, wherein the thin film transistor includes a source and a drain.

In sub-step2022, an insulating layer is formed on the base substrate on which the thin film transistor is formed, wherein a first via hole is formed in the insulating layer.

In sub-step2023, a pixel electrode is formed on the base substrate on which the insulating layer is formed.

Here, the pixel electrode is electrically connected to either the source or the drain through the first via hole.

In sub-step2024, a filling block is formed on the base substrate on which the pixel electrode is formed, wherein the filling block is disposed at the first via hole.

In summary, the embodiment of the present disclosure provides a method for manufacturing a substrate. The thin film transistor in the substrate can be electrically connected to the pixel electrode through the first via hole in the insulating layer. In addition, by arranging the filling block in the first via hole of the insulating layer, the flatness of the film layer above the first via hole of the insulating layer is good, thereby improving the quality of the film layer above the insulating layer.

FIG.23is a flowchart of another method for manufacturing a substrate according to an embodiment of the present disclosure. The method may be applied to manufacture the substrates according to the above embodiments, for example, the substrate as shown inFIG.12.FIG.24is a schematic structural diagram of a base substrate in the manufacturing process corresponding toFIG.23. The process for manufacturing the substrate shown inFIG.23may be made reference toFIG.24. The method may include the following steps.

In step301, a light shielding pattern, a fourth insulating layer and an active material pattern are sequentially formed on a base substrate.

The base substrate may be a flexible substrate, which may be made of a flexible material (for example, polyimide (PI)). Or, the base substrate may be a glass substrate. As shown in S11and S12inFIG.24, the light shielding pattern107and the active material pattern t1may be sequentially formed on the base substrate101. The active material pattern t1may be an active material pattern with the shape of an active layer formed by performing preliminary patterning on an active material but without ion doping.

In step302, a fifth insulating layer and a first metal material layer are formed on the base substrate on which the active material pattern is formed.

The first metal material layer may be a gate thin film. The fifth insulating layer114may be configured to insulate the light shielding pattern107from the active material pattern t1.

In step303, the first metal material layer is etched through a dry etching process to acquire a gate line.

By performing the dry etching process, the accuracy of the size of the gate line1024can be well controlled, such that the size of the gate line1024can be relatively small. As shown in S13inFIG.24, the first metal material layer is processed through the dry etching process to acquire the gate line1024.

In step304, ions are implanted into the surface of the side of the active material pattern distal from the base substrate through a first ion implantation process by using the gate line as a mask to form an undoped region and a lightly drain doping region.

The ion implantation process is a process in which ion beams accelerated to be with high energy are implanted into a surface layer of a semiconductor material to change physical and chemical properties of the surface layer. For example, boron, phosphorus or arsenic may be implanted into silicon to change the conductivity of a silicon surface. The depth and concentration of implanted ions can be accurately controlled by the ion implantation process.

As shown in S14inFIG.24, the ions are implanted into the surface of the side of the active material pattern t1distal from the base substrate101through the first ion implantation process to form an active material pattern t2including the undoped region and the lightly drain doping region. Here, the region, overlapped with the gate line1024in the direction perpendicular to the base substrate101, of the active material pattern t2may be the undoped region.

In step305, a first photoresist pattern is formed on the base substrate on which the lightly drain doping region is formed.

The first photoresist pattern may cover part of the active material pattern in the direction perpendicular to the base substrate. As shown in S15inFIG.24, the first photoresist pattern q1covers the partial region in the middle of the active material pattern t2in the direction perpendicular to the base substrate101.

In step306, ions are implanted into the surface of the side of the active material pattern distal from the base substrate through a second ion implantation process by using the first photoresist pattern as a mask to form a heavily drain doping region and a lightly drain doping region.

The ion implantation process may be performed again on the partial region, uncovered by the first photoresist pattern, of the active material pattern, such that the uncovered region forms the heavily drain doping region. As shown in S16inFIG.24, a second ion implantation process may be performed on an edge region of the active material pattern t2that is not covered by the first photoresist pattern q1in the direction perpendicular to the base substrate101. Through the above two ion implantation processes, the active layer1023including two heavily drain doping regions, three lightly drain doping regions and two undoped regions may be formed.

In step307, the first photoresist pattern is removed to form an active layer including two heavily drain doping regions, three lightly drain doping regions and two undoped regions, and a gate insulating layer is formed on the side of the gate line distal from the base substrate.

As shown in S17inFIG.24, after the gate line1024is formed, the gate insulating layer113may be formed on the side of the gate line1024distal from the base substrate101, such that the gate line1024is insulated from the source1021and the drain1022which are later formed. A via hole may be formed in the gate insulating layer113.

In308, a source and a drain are formed on the side of the gate line distal from the base substrate.

As shown in S18inFIG.24, after the gate line1024is formed, a source-drain thin film may be formed on the side of the gate line1024distal from the base substrate101. Here, the material of the source-drain thin film may be a metal material, and may cover the entire base substrate101. After the source-drain thin film is formed, the source-drain thin film may be patterned through a photo-etching process to acquire the source1021and the drain1022. In this implementation, the source1021and the drain1022are formed by the same patterning process.

An orthographic projection of the source1021on the base substrate101is overlapped with an orthographic projection of one heavily drain doping region of the active layer1023on the base substrate101. An orthographic projection of the drain1022on the base substrate101is overlapped with an orthographic projection of the other heavily drain doping region of the active layer1023on the base substrate101. In addition, the source1021and the drain1022may be electrically connected to the active layer1023through the via hole in the gate insulating layer113.

In step309, an insulating layer is formed on the base substrate on which the source and the drain are formed.

The insulating layer may be of a single-layer structure or a multi-layer structure, and a first via hole may be formed in the insulating layer.

In step310, a pixel electrode is formed on the base substrate on which the insulating layer is formed.

The pixel electrode may be electrically connected to either the source or the drain through the first via hole. The material of the pixel electrode may include indium tin oxide.

In step311, a filling block is formed on the base substrate on which the pixel electrode is formed. The filling block is disposed at the first via hole.

The filling block105may be disposed in the first via hole to fill up the first via hole, such that the flatness of the film layer on the side of the insulating layer distal from the base substrate is good.

FIG.25is a flowchart of still another method for manufacturing a substrate according to an embodiment of the present disclosure. The method may be applied to manufacture the substrates according to the above embodiments, for example, the substrate as shown inFIG.12.FIG.26is a schematic structural diagram of the base substrate in the manufacturing process corresponding toFIG.25. The process for manufacturing the substrate shown inFIG.25may be made reference toFIG.26. The method may include the following steps.

In step401, a light shielding pattern, a fourth insulating layer and an active material pattern are formed sequentially on a base substrate.

The base substrate may be a flexible substrate, which may be made of a flexible material (such as polyimide (PI)). Or, the base substrate may be a glass substrate. As shown in S21and S22inFIG.26, the light shielding pattern107and the active material pattern t1may be sequentially formed on the base substrate101. The active material pattern t1may be an active material pattern with the shape of an active layer formed by performing preliminary patterning on an active material but without ion doping.

In step402, a fifth insulating layer and a first metal material layer are formed on the base substrate on which the active material pattern is formed.

The first metal material layer may be a gate thin film. The fifth insulating layer114may be configured to insulate the light shielding pattern107from the active material pattern t1.

In step403, a second photoresist pattern is formed on base substrate on which the first metal material layer is formed, and the first metal material layer is etched through a wet etching process to acquire a gate pattern.

First, the wet etching may be performed on the first metal material layer to acquire a side edge of the gate line. As shown in S23inFIG.26, an orthographic projection of the second photoresist pattern q2on the base substrate101covers a partial region of the active material pattern, and an edge region of the active material pattern is exposed in the direction perpendicular to the base substrate101. Since the first metal material layer is processed by the wet etching process, an orthographic projection of the acquired gate pattern on the base substrate101may be within an orthographic projection of the second photoresist pattern q2on the base substrate101.

In404, ions are implanted into the surface of the side of the active material pattern distal from the base substrate through a first ion implantation process by using the second photoresist pattern as a mask to form an undoped region and a heavily drain doping region.

As shown in S23shown inFIG.26, ions are implanted into the surface of the side of the active material pattern t1distal from the base substrate101through the first ion implantation process to form an active material pattern t3including the heavily drain doping region and the lightly drain doping region. Here, the region, overlapped with the second photoresist pattern q2in the direction perpendicular to the base substrate101, of the active material layer t3may be the undoped region.

In step405, a third photoresist pattern is formed on the base substrate on which the heavily drain doping region is formed, and the gate pattern may be etched through the dry etching process to acquire a gate line.

As shown in S24inFIG.26, since the gate line1024is processed by two different etching processes, the side surface of one side of the acquired gate line1024may be perpendicular to the plate surface of the base substrate101, and a slope angle between the side surface of the other side of the gate line1024and a bottom surface, facing the base substrate101, of the gate line1024may be relatively small, which can improve the flatness of the film layer on the gate line1024.

In step406, the third photoresist pattern is removed, and ions are implanted into the surface of the side of the active material pattern distal from the base substrate through a second ion implantation process by using the gate line as a mask to form a lightly drain doping region and an undoped region.

In this way, an active layer including two heavily drain doping regions, three lightly drain doping regions and two undoped regions may be acquired.

The ion implantation process may be performed on a part region, uncovered by the gate line, of the active material pattern, such that the uncovered region forms the lightly drain doping region. As shown in S25inFIG.26, one iron implantation process may be performed on three regions of the active material pattern t3which are not covered by the gate line1024in the direction perpendicular to the base substrate101. Through the above two ion implantation processes, the active layer1023including two heavily drain doping regions, three lightly drain doping regions and two undoped regions may be formed.

In step407, a gate insulating layer is formed on the side of the gate line distal from the base substrate.

As shown in S26inFIG.26, after the gate line1024is formed, the gate insulating layer113may be formed on the side of the gate line1024distal from the base substrate101, such that the gate line1024is insulated from the source1021and the drain1022later formed. A via hole may be formed in the gate insulating layer113.

In step408, a source and a drain are formed on the side of the gate line distal from the base substrate.

Step408may be made reference to step307in the embodiment shown inFIG.23, and details are not repeated in the embodiment of the present disclosure. For the schematic structural diagram of the formed base substrate after step408, reference may be made to S27inFIG.26.

In step409, an insulating layer is formed on the base substrate on which the source and the drain are formed.

The insulating layer may be of a single-layer structure or a multi-layer structure, and a first via hole may be formed in the insulating layer.

In step410, a pixel electrode is formed on the base substrate on which the insulating layer is formed.

The pixel electrode may be electrically connected to either the source or the drain through the first via hole. The material of the pixel electrode may include indium tin oxide.

In step411, a filling block is formed on the base substrate on which the pixel electrode is formed. The filling block is disposed at the first via hole.

The filling block may be disposed in the first via hole to fill up the first via hole, such that the flatness of the film layer on the side of the insulating layer distal from the base substrate is good.

FIG.27is a flowchart of still another method for manufacturing a substrate according to an embodiment of the present disclosure. The method may be applied to manufacture the substrates according to the above embodiments, for example, the substrate as shown inFIG.20.FIG.28is a schematic structural diagram of the base substrate in the manufacturing process corresponding toFIG.27. The process for manufacturing the substrate shown inFIG.27may be made reference toFIG.28. The method may include the following steps.

In501, a light shielding pattern, a fourth insulating layer and an active material pattern are sequentially formed on the base substrate.

Step501may be made reference to step301in the embodiment shown inFIG.23, and details are not repeated in the embodiment of the present disclosure. For the schematic structural diagram of the formed base substrate after step501, reference may be made to S31and S32inFIG.28.

In step502, a fifth insulating layer and a first metal material layer are formed on the base substrate on which the active material pattern is formed.

The first metal material layer may be a gate thin film. The fifth insulating layer114may be configured to insulate the light shielding pattern107from the active material pattern t1.

In step503, a fourth photoresist pattern is formed on the base substrate on which the first metal material layer is formed, and the first metal material layer is etched through a wet etching process to acquire a gate line.

For the schematic structural diagram of the formed base substrate after step503, reference may be made to S33inFIG.28. The fourth photoresist pattern q4may include two parts of photoresist, and there is a preset distance between the two parts of photoresist so as to form two gate lines1024on the base substrate101.

In504, ions are implanted into the surface of the side of the active material pattern distal from the base substrate through a first ion implantation process by using the fourth photoresist pattern as a mask to form an undoped region and a heavily drain doping region.

As shown in S33inFIG.28, the region, overlapped with the fourth photoresist pattern q4in the direction perpendicular to the base substrate101, of the active material pattern t4is an undoped region.

In step505, the fourth photoresist pattern is removed, and ions are implantation into the surface of the side of the active material pattern distal from the base substrate through a second ion implantation process by using the gate line as a mask to form a lightly drain doping region and an undoped region, so as to acquire an active layer including three heavily drain doping regions, four lightly drain doping regions and two undoped regions.

For the schematic structural diagram of the formed base substrate after step505, reference may be made to S34and S35inFIG.28, and the active layer1023may include three heavily drain doping regions, four lightly drain doping regions and two undoped regions.

In step506, a gate insulating layer is formed on the side of the gate line distal from the base substrate.

As shown in S36inFIG.28, after the gate line1024is formed, the gate insulating layer113may be formed on the side of the gate line1024distal from the base substrate101, such that the gate line1024is insulated from the source1021and the drain1022later formed. A via hole may be formed in the gate insulating layer113.

In step507, a source and a drain are formed on the side of the gate line distal from the base substrate.

Step507may be made reference to step307in the embodiment shown inFIG.23, and details are not repeated in the embodiment of the present disclosure. For the schematic structural diagram of the formed base substrate after step507, reference may be made to S37inFIG.28.

In step508, an insulating layer is formed on the base substrate on which the source and the drain are formed.

The insulating layer may be of a single-layer structure or a multi-layer structure, and a first via hole may be formed in the insulating layer.

In step509, a pixel electrode is formed on the base substrate on which the insulating layer is formed.

The pixel electrode may be electrically connected to either the source or the drain through the first via hole. The material of the pixel electrode may include indium tin oxide.

In step510, a filling block is formed on the base substrate on which the pixel electrode is formed. The filling block is disposed at the first via hole.

The filling block may be disposed in the first via hole to fill up the first via hole, such that the flatness of the film layer on the side of the insulating layer distal from the base substrate is good.

FIG.29is a flowchart of still another method for manufacturing a substrate according to an embodiment of the present disclosure. The method may be applied to manufacture the substrates according to the above embodiments, for example, the substrate as shown inFIG.20.FIG.30is a schematic structural diagram of the base substrate in the manufacturing process corresponding toFIG.29. The process for manufacturing the substrate shown inFIG.29may be made reference toFIG.30. The method may include the following steps.

In step601, a light shielding pattern, a fourth insulating layer and an active material pattern are sequentially formed on a base substrate.

Step601may be made reference to step301in the embodiment shown inFIG.23, and details are not repeated in the embodiment of the present disclosure. For the schematic structural diagram of the formed base substrate after step601, reference may be made to S41and S42inFIG.30.

In step602, a fifth insulating layer and a first metal material layer are formed on the base substrate on which the active material pattern is formed.

The first metal material layer may be a gate thin film. The fifth insulating layer114may be configured to insulate the light shielding pattern107from the active material pattern t1.

In step603, a fifth photoresist pattern is formed on the base substrate on which the first metal material layer is formed, and the first metal material layer is etched through a wet etching process to acquire a gate pattern.

For the schematic structural diagram of the formed base substrate after step603, reference may be made to S43inFIG.30. The fifth photoresist pattern q5may include two parts of photoresist, and there is a preset distance between the two parts of photoresist to form two gate patterns on the base substrate101.

In step604, ions are implant into the surface of the side of the active material pattern distal from the base substrate through a first ion implantation process by using the fifth photoresist pattern as a mask to form an undoped region and a heavily drain doping region.

As shown in S43inFIG.30, the region, overlapped with the fifth photoresist pattern q5in the direction perpendicular to the base substrate101, of the active material pattern t4is an undoped region.

In step605, the fifth photoresist pattern is ashed to form a sixth photoresist pattern, and the gate pattern is etched through a dry etching process to acquire a gate line.

As shown in S45inFIG.30, the formed gate pattern may be modified by the dry etching process, such that the top corner on the side, distal from the base substrate101, of the gate line1024is a rounded corner Z. In this way, the flatness of the film layer above the gate line1024is good.

In step606, the sixth photoresist pattern is removed, and ions are implanted into the surface of the side of the active material pattern distal from the base substrate through a second ion implantation process by using the gate line as a mask to form the lightly drain doping regions and the undoped region, so as to acquire an active layer including three heavily drain doping regions, four lightly drain doping regions and two undoped regions.

For the schematic structural diagram of the formed base substrate after step606, reference may be made to S44inFIG.30, and the active layer1023may include three heavily drain doping regions, four lightly drain doping regions and two undoped regions.

In step607, a gate insulating layer is formed on the side of the gate line distal from the base substrate.

As shown in S46inFIG.30, after the gate line1024is formed, the gate insulating layer113may be formed on the side of the gate line1024distal from the base substrate101, such that the gate line1024is insulated from the source1021and the drain1022later formed. A via hole may be formed in the gate insulating layer113.

In step608, a source and a drain are formed on the side of the gate line distal from the base substrate.

Step608may be made reference to step307in the embodiment shown inFIG.23, and details are not repeated in the embodiment of the present disclosure. For the schematic structural diagram of the formed base substrate after step608, reference may be made to S47inFIG.30.

In step609, an insulating layer is formed on the base substrate on which the source and the drain are formed.

The insulating layer may be of a single-layer structure or a multi-layer structure, and a first via hole may be formed in the insulating layer.

In step610, a pixel electrode is formed on the base substrate on which the insulating layer is formed.

The pixel electrode may be electrically connected to either the source or the drain through the first via hole. The material of the pixel electrode may include indium tin oxide.

In step611, a filling block is formed on the base substrate on which the pixel electrode is formed. The filling block is disposed at the first via hole.

The filling block may be disposed in the first via hole to fill up the first via hole, such that the flatness of the film layer on the side of the insulating layer distal from the base substrate is good.

FIG.31is a flowchart of still another method for manufacturing a substrate according to an embodiment of the present disclosure. The method may be applied to manufacture the substrates according to the above embodiments, for example, the substrate as shown inFIG.12.FIG.32is a schematic structural diagram of the base substrate in the manufacturing process corresponding toFIG.31. The process for manufacturing the substrate shown inFIG.31may be made reference toFIG.32. The method may include the following steps.

In step701, a light shielding pattern and a fourth insulating layer are formed sequentially on a base substrate.

Step701may be made reference to step301in the embodiment shown inFIG.23, and details are not repeated in the embodiment of the present disclosure. For the schematic structural diagram of the formed base substrate after step701, reference may be made to S51and S52inFIG.32.

In step702, an active material pattern and a seventh photoresist pattern are formed on the base substrate, and ions are implanted into the surface of the side of the active material pattern distal from the base substrate through a first ion implantation process by using the seventh photoresist pattern as a mask to form an undoped region and a heavily drain doping region.

As shown in S53inFIG.32, the region, overlapped with the seventh photoresist pattern q7in the direction perpendicular to the base substrate101, of the active material pattern is an undoped region.

In step703, the seventh photoresist pattern is removed, and a fifth insulating layer and a first metal material layer are formed on the base substrate on which the active material pattern is formed.

As shown in S53inFIG.32, the first metal material layer may be a gate thin film. The fifth insulating layer114may be configured to insulate the light shielding pattern107from the active material pattern t3.

In step704, the first metal material layer is etched through a dry etching process to acquire a gate line.

By performing the dry etching process, the accuracy of the size of the gate line1024can be well controlled, such that the size of the gate line1024can be relatively small. As shown in S54inFIG.32, the first metal material layer is processed through the dry etching process to acquire the gate line1024.

In step705, ions are implanted into the surface of the side of the active material pattern distal from the base substrate through a second ion implantation process by using the gate line as a mask to form a lightly drain doping region and an undoped region, so as to acquire an active layer including two heavily drain doping regions, three lightly drain doping regions and two undoped regions.

As shown in S55inFIG.32, ions are implanted into the surface of the side of the active material pattern distal from the base substrate101through the second ion implantation process by using the gate line1024as a mask to form the lightly drain doping regions a1and the undoped region, thereby acquiring the active layer1023including two heavily drain doping regions, three lightly drain doping regions and two undoped regions.

In step706, a gate insulating layer is formed on the side of the gate line distal from the base substrate.

As shown in S56inFIG.30, after the gate line1024is formed, the gate insulating layer113may be formed on the side of the gate line1024distal from the base substrate101, such that the gate line1024is insulated from the source1021and the drain1022later formed. A via hole may be formed in the gate insulating layer113.

In step707, a source and a drain are formed on the side of the gate line distal from the base substrate.

Step707may be made reference to step307in the embodiment shown inFIG.23, and details are not repeated in the embodiment of the present disclosure. For the schematic structural diagram of the formed base substrate after step707, reference may be made to S57inFIG.32.

In step708, an insulating layer, a pixel electrode and a filling block are sequentially formed on the base substrate on which the source and the drain are formed.

The insulating layer may be of a single-layer structure or a multi-layer structure, and a first via hole may be formed in the insulating layer. The pixel electrode may be electrically connected to either the source or the drain through the first via hole. The material of the pixel electrode may include indium tin oxide. The filling block may be disposed in the first via hole to fill up the first via hole, such that the flatness of the film layer on the side of the insulating layer distal from the base substrate is good.

FIG.33is a flowchart of still another method for manufacturing a substrate according to an embodiment of the present disclosure. The method may be applied to manufacture the substrates according to the above embodiments, for example, the substrate as shown inFIG.12.FIG.34is a schematic structural diagram of the base substrate in the manufacturing process corresponding toFIG.32. The process for manufacturing the substrate shown inFIG.33may be made reference toFIG.34. The method may include the following steps.

In step801, a light shielding pattern and a fourth insulating layer are sequentially formed on a base substrate.

Step801may be made reference to step301in the embodiment shown inFIG.23, and details are not repeated in the embodiment of the present disclosure. For the schematic structural diagram of the formed base substrate after step801, reference may be made to S61and S62inFIG.34.

In step802, an active material pattern and an eighth photoresist pattern are formed on the base substrate, and ions are implanted into the surface of the side of the active material pattern distal from the base substrate through a first ion implantation process by using the eighth photoresist pattern as a mask to form an undoped region and a heavily drain doping region.

As shown in S63inFIG.34, the region, overlapped with the eighth photoresist pattern q8in the direction perpendicular to the base substrate101, of the active material pattern is an undoped region. Before the eighth photoresist pattern q8is formed, a fifth insulating layer114may be formed. The fifth insulating layer114may be configured to insulate the light shielding pattern107from the active material pattern t3.

In step803, the eighth photoresist pattern is exposed to acquire a ninth photoresist pattern, and ions are implanted into the surface of the side of the active material pattern distal from the base substrate through a second ion implantation process by using the ninth photoresist pattern as a mask to form a lightly drain doping region and an undoped region, so as to acquire an active layer including two heavily drain doping regions, two lightly drain doping regions and two undoped regions.

As shown in S64inFIG.34, the region, overlapped with the ninth photoresist pattern q9in the direction perpendicular to the base substrate101, of the active material pattern is an undoped region.

In step804, a first metal material layer is formed on the base substrate on which the active layer is formed.

The first metal material layer may be a gate thin film.

In step805, the first metal material layer is etched through a dry etching process to acquire a gate line.

By performing the dry etching process, the accuracy of the size of the gate line1024can be well controlled, such that the size of the gate line1024can be relatively small. As shown in S65inFIG.34, the first metal material layer is processed through the dry etching process to acquire the gate line1024.

In step806, a gate insulating layer is formed on the side of the gate line distal from the base substrate.

As shown in S66inFIG.34, after the gate line1024is formed, the gate insulating layer113may be formed on the side of the gate line1024distal from the base substrate101, such that the gate line1024is insulated from the source1021and the drain1022later formed.

A third via hole1131and a fourth via hole1132are formed in the fifth insulating layer114and the gate insulating layer113, and the third via hole1131and the fourth via hole1132are on the side of the heavily drain doping region distal from the base substrate.

In step807, a source and a drain are formed on the side of the gate insulating layer distal from the base substrate.

A source/drain layer is formed on the base substrate101on which the gate insulating layer113is formed, and the source/drain layer includes a source and a drain. The source1021and the drain1022may be electrically connected to two heavily drain doping regions through the third via hole1131and the fourth via hole1132, respectively. For the schematic structural diagram of the formed base substrate after step807, reference may be mad to S67inFIG.34.

In step808, an insulating layer, a pixel electrode and a filling block are sequentially formed on the base substrate on which the source and the drain are formed.

The insulating layer may be of a single-layer structure or a multi-layer structure, and a first via hole may be formed in the insulating layer. The pixel electrode may be electrically connected to either the source or the drain through the first via hole. The material of the pixel electrode may include indium tin oxide. The filling block may be disposed in the first via hole to fill up the first via hole, such that the flatness of the film layer on the side of the insulating layer distal from the base substrate is good.

In summary, the embodiments of the present disclosure provide a method for manufacturing a substrate. The thin film transistor in the substrate may be electrically connected to the pixel electrode through the first via hole in the insulating layer. In addition, by arranging the filling block in the first via hole of the insulating layer, the flatness of the film layer above the first via hole of the insulating layer is good. Therefore, the quality of the film layer above the insulating layer can be improved.

The embodiments of the present disclosure further provide a display panel. The display panel may include a base substrate, and the above substrate disposed on the base substrate. The substrate may be the substrate provided in the above embodiments.

Optionally, the display panel may be a liquid crystal display device, an organic light-emitting diode (OLED) display device (for example, an active-matrix organic light-emitting diode (AMOLED)), electronic paper, a mobile phone, a tablet computer, a TV, a display, a notebook computer, a digital photo frame, a navigator, or any other product or component having a display function and a fingerprint identification function.

The term “at least one of A and B” in the present disclosure is merely intended to describe an association relationship among associated objects, and may indicate three relationships. For example, “at least one of A and B” may mean that A exists alone, A and B exist concurrently, or B exists alone. Similarly, “at least one of A, B and C” may indicate seven relationships, which may mean that A exists alone, B exists alone, C exists alone, A and B exist concurrently, A and C exist concurrently, C and B exist concurrently, and A, B and C exist concurrently. Similarly, “at least one of A, B, C and D” indicates fifteen relationships which may mean A exists alone, B exists alone, C exists alone, D exists alone, A and B exist concurrently, A and C exist concurrently, A and D exist concurrently, C and B exist concurrently, D and B exist concurrently, C and D exist concurrently, A, B, and C exist concurrently, A, B, and D exist concurrently, A, C, and D exist concurrently, B, C, and D exist concurrently, and A, B, C, and D exist concurrently.

It should be noted that in the accompanying drawings, the dimensions of layers and regions may be exaggerated for the clarity of illustration. Moreover, it is to be understood that when an element or a layer is referred to as “on” another element or layer, the element or layer may be directly arranged on the other element, or there may be an intermediate layer. In addition, it is to be understood that when an element or a layer is referred to as “below” another element or layer, the element or layer may be directly arranged below the other element, or there may be more than one intermediate layer or element. In addition, understandably, when a layer or an element is referred to as “between” two layers or two elements, the layer or element may be the only layer between the two layers or two elements, or there may be more than one intermediate layer or element. Similar reference numerals indicate similar elements throughout.

The terms “first”, “second”, “third” and “fourth” used in the present disclosure are merely used for descriptive purpose, but not denote or imply any relative importance. The term “a plurality of” means two or more, unless otherwise expressly specified.

The above descriptions are merely optional embodiments of the present disclosure, but are not intended to limit the present disclosure. Any modifications, equivalent substitutions, improvements and the like made within the spirit and principle of the present disclosure should be included within the scope of protection of the present disclosure.