Patent ID: 12255181

Embodiments of the present disclosure will be described with reference to the accompanying drawings.

DETAILED DESCRIPTION

Although specific configurations and arrangements are discussed, it should be understood that this is done for illustrative purposes only. A person skilled in the pertinent art will recognize that other configurations and arrangements can be used without departing from the spirit and scope of the present disclosure. It will be apparent to a person skilled in the pertinent art that the present disclosure can also be employed in a variety of other applications.

It is noted that references in the specification to “one embodiment,” “an embodiment,” “an example embodiment,” “some embodiments,” etc., indicate that the embodiment described may include a particular feature, structure, or characteristic, but every embodiment may not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases do not necessarily refer to the same embodiment. Further, when a particular feature, structure or characteristic is described in connection with an embodiment, it would be within the knowledge of a person skilled in the pertinent art to effect such feature, structure or characteristic in connection with other embodiments whether or not explicitly described.

In general, terminology may be understood at least in part from usage in context. For example, the term “one or more” as used herein, depending at least in part upon context, may be used to describe any feature, structure, or characteristic in a singular sense or may be used to describe combinations of features, structures or characteristics in a plural sense. Similarly, terms, such as “a,” “an,” or “the,” again, may be understood to convey a singular usage or to convey a plural usage, depending at least in part upon context. In addition, the term “based on” may be understood as not necessarily intended to convey an exclusive set of factors and may, instead, allow for existence of additional factors not necessarily expressly described, again, depending at least in part on context.

It should be readily understood that the meaning of “on,” “above,” and “over” in the present disclosure should be interpreted in the broadest manner such that “on” not only means “directly on” something but also includes the meaning of “on” something with an intermediate feature or a layer therebetween, and that “above” or “over” not only means the meaning of “above” or “over” something but can also include the meaning it is “above” or “over” something with no intermediate feature or layer therebetween (i.e., directly on something).

Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper,” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

As used herein, the term “substrate” refers to a material onto which subsequent material layers are added. The substrate itself can be patterned. Materials added on top of the substrate can be patterned or can remain unpatterned. Furthermore, the substrate can include a wide array of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate can be made from an electrically non-conductive material, such as a glass, a plastic, or a sapphire wafer.

As used herein, the term “layer” refers to a material portion including a region with a thickness. A layer can extend over the entirety of an underlying or overlying structure or may have an extent less than the extent of an underlying or overlying structure. Further, a layer can be a region of a homogeneous or inhomogeneous continuous structure that has a thickness less than the thickness of the continuous structure. For example, a layer can be located between any pair of horizontal planes between, or at, a top surface and a bottom surface of the continuous structure. A layer can extend horizontally, vertically, and/or along a tapered surface. A substrate can be a layer, can include one or more layers therein, and/or can have one or more layer thereupon, thereabove, and/or therebelow. A layer can include multiple layers. For example, an interconnect layer can include one or more conductor and contact layers (in which interconnect lines and/or vertical interconnect access (via) contacts are formed) and one or more dielectric layers.

As used herein, the term “nominal/nominally” refers to a desired, or target, value of a characteristic or parameter for a component or a process operation, set during the design phase of a product or a process, together with a range of values above and/or below the desired value. The range of values can be due to slight variations in manufacturing processes or tolerances. As used herein, the term “about” indicates the value of a given quantity that can vary based on a particular technology node associated with the subject semiconductor device. Based on the particular technology node, the term “about” can indicate a value of a given quantity that varies within, for example, 10-30% of the value (e.g., ±10%, ±20%, or ±30% of the value).

As used herein, the term “3D memory device” refers to a semiconductor device with vertically oriented strings of memory cell transistors (referred to herein as “memory strings,” such as NAND memory strings) on a laterally-oriented substrate so that the memory strings extend in the vertical direction with respect to the substrate. As used herein, the term “vertical/vertically” means nominally perpendicular to the lateral surface of a substrate.

In some 3D memory devices, such as 3D NAND memory devices, slit structures (e.g., gate line slits (GLSs)) are used for providing electrical connections to the source of the memory array, such as array common source (ACS), from the front side of the devices. The front side source contacts, however, can affect the electrical performance of the 3D memory devices by introducing both leakage current and parasitic capacitance between the word lines and the source contacts, even with the presence of spacers in between. The formation of the spacers also complicates the fabrication process. Besides affecting the electrical performance, the slit structures usually include wall-shaped polysilicon and/or metal fillings, which can introduce local stress to cause wafer bow or warp, thereby reducing the production yield.

Moreover, in some 3D NAND memory devices, semiconductor plugs are selectively grown to surround the sidewalls of channel structures, e.g., known as sidewall selective epitaxial growth (SEG). Compared with another type of semiconductor plugs that are formed at the lower end of the channel structures, e.g., bottom SEG, the formation of sidewall SEG avoids the etching of the memory film and semiconductor channel at the bottom surface of channel holes (also known as “SONO” punch), thereby increasing the process window, in particular when fabricating 3D NAND memory devices with advanced technologies, such as having 96 or more levels with a multi-deck architecture. Sidewall SEGs are usually formed by replacing a sacrificial layer between the substrate and stack structure with the sidewall SEGs, which involves multiple deposition and etching processes through the slit openings. However, as the levels of 3D NAND memory devices continue increasing, the aspect ratio of the slit openings extending through the stack structure becomes larger, making the deposition and etching processes through the slit openings more challenging and undesirable for forming the sidewall SEGs using the known approach due to the increased cost and reduced yield.

Various embodiments in accordance with the present disclosure provide 3D memory devices with backside source contacts. By moving the source contacts from the front side to the backside, the cost per memory cell can be reduced as the effective memory cell array area can be increased, and the spacers formation process can be skipped. The device performance can be improved as well, for example, by avoiding the leakage current and parasitic capacitance between the word lines and the source contacts and by reducing the local stress caused by the front side slit structures (as source contacts). The sidewall SEGs (e.g., semiconductor plugs) can be formed from the backside of the substrate to avoid any deposition or etching process through the openings extending through the stack structure at the front side of the substrate. As a result, the complexity and cost of the fabrication process can be reduced, and the product yield can be increased. Also, as the fabrication process of the sidewall SEGs is no longer affected by the aspect ratio of the openings through the stack structure, i.e., not limited by the levels of the memory stack, the scalability of the 3D memory devices can be improved as well.

In some embodiments, the substrate on which the memory stack is formed is removed from the backside to expose the channel structures prior to the formation of the sidewall SEGs. Thus, the selection of the substrate can be expanded, for example, to dummy wafers to reduce the cost or to silicon on insulator (SOI) wafers to simplify the fabrication process. The removal of the substrate can also avoid the challenging issue of thickness uniformity control in known methods using the backside thinning process.

Various 3D memory device architectures and fabrication methods thereof, for example, with different erase operation mechanisms, are disclosed in the present disclosure to accommodate different requirements and applications. In some embodiments, the sidewall SEGs are parts of an N-type doped semiconductor layer to enable gate-induced-drain-leakage (GIDL) erasing by the 3D memory device. In some embodiments, the sidewall SEGs are parts of a P-type doped semiconductor layer to enable P-well bulk erasing by the 3D memory device.

FIG.1illustrates a side view of a cross-section of an exemplary 3D memory device100, according to some embodiments of the present disclosure. In some embodiments, 3D memory device100is a bonded chip including a first semiconductor structure102and a second semiconductor structure104stacked over first semiconductor structure102. First and second semiconductor structures102and104are jointed at a bonding interface106therebetween, according to some embodiments. As shown inFIG.1, first semiconductor structure102can include a substrate101, which can include silicon (e.g., single crystalline silicon, c-Si), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), SOI, or any other suitable materials.

First semiconductor structure102of 3D memory device100can include peripheral circuits108on substrate101. It is noted that x and y axes are included inFIG.1to further illustrate the spatial relationship of the components in 3D memory device100having substrate101. Substrate101includes two lateral surfaces (e.g., a top surface and a bottom surface) extending laterally in the x-direction (i.e., the lateral direction). As used herein, whether one component (e.g., a layer or a device) is “on,” “above,” or “below” another component (e.g., a layer or a device) of a semiconductor device (e.g., 3D memory device100) is determined relative to the substrate of the semiconductor device (e.g., substrate101) in they-direction (i.e., the vertical direction) when the substrate is positioned in the lowest plane of the semiconductor device in the y-direction. The same notion for describing spatial relationships is applied throughout the present disclosure.

In some embodiments, peripheral circuit108is configured to control and sense 3D memory device100. Peripheral circuit108can be any suitable digital, analog, and/or mixed-signal control and sensing circuits used for facilitating the operation of 3D memory device100including, but not limited to, a page buffer, a decoder (e.g., a row decoder and a column decoder), a sense amplifier, a driver (e.g., a word line driver), a charge pump, a current or voltage reference, or any active or passive components of the circuit (e.g., transistors, diodes, resistors, or capacitors). Peripheral circuits108can include transistors formed “on” substrate101, in which the entirety or part of the transistors are formed in substrate101(e.g., below the top surface of substrate101) and/or directly on substrate101. Isolation regions (e.g., shallow trench isolations (STIs)) and doped regions (e.g., source regions and drain regions of the transistors) can be formed in substrate101as well. The transistors are high-speed with advanced logic processes (e.g., technology nodes of 90 nm, 65 nm, 45 nm, 32 nm, 28 nm, 20 nm, 16 nm, 14 nm, 10 nm, 7 nm, 5 nm, 3 nm, 2 nm, etc.), according to some embodiments. It is understood that in some embodiments, peripheral circuit108may further include any other circuits compatible with the advanced logic processes including logic circuits, such as processors and programmable logic devices (PLDs), or memory circuits, such as static random-access memory (SRAM) and dynamic RAM (DRAM).

In some embodiments, first semiconductor structure102of 3D memory device100further includes an interconnect layer (not shown) above peripheral circuits108to transfer electrical signals to and from peripheral circuits108. The interconnect layer can include a plurality of interconnects (also referred to herein as “contacts”), including lateral interconnect lines and vertical interconnect access (VIA) contacts. As used herein, the term “interconnects” can broadly include any suitable types of interconnects, such as middle-end-of-line (MEOL) interconnects and back-end-of-line (BEOL) interconnects. The interconnect layer can further include one or more interlayer dielectric (ILD) layers (also known as “intermetal dielectric (IMD) layers”) in which the interconnect lines and VIA contacts can form. That is, the interconnect layer can include interconnect lines and VIA contacts in multiple ILD layers. The interconnect lines and VIA contacts in the interconnect layer can include conductive materials including, but not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), silicides, or any combination thereof. The ILD layers in the interconnect layer can include dielectric materials including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, low dielectric constant (low-k) dielectrics, or any combination thereof.

As shown inFIG.1, first semiconductor structure102of 3D memory device100can further include a bonding layer110at bonding interface106and above the interconnect layer and peripheral circuits108. Bonding layer110can include a plurality of bonding contacts111and dielectrics electrically isolating bonding contacts111. Bonding contacts111can include conductive materials including, but not limited to, W, Co, Cu, Al, silicides, or any combination thereof. The remaining area of bonding layer110can be formed with dielectrics including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof. Bonding contacts111and surrounding dielectrics in bonding layer110can be used for hybrid bonding.

Similarly, as shown inFIG.1, second semiconductor structure104of 3D memory device100can also include a bonding layer112at bonding interface106and above bonding layer110of first semiconductor structure102. Bonding layer112can include a plurality of bonding contacts113and dielectrics electrically isolating bonding contacts113. Bonding contacts113can include conductive materials including, but not limited to, W, Co, Cu, Al, silicides, or any combination thereof. The remaining area of bonding layer112can be formed with dielectrics including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof. Bonding contacts113and surrounding dielectrics in bonding layer112can be used for hybrid bonding. Bonding contacts113are in contact with bonding contacts111at bonding interface106, according to some embodiments.

As described below in detail, second semiconductor structure104can be bonded on top of first semiconductor structure102in a face-to-face manner at bonding interface106. In some embodiments, bonding interface106is disposed between bonding layers110and112as a result of hybrid bonding (also known as “metal/dielectric hybrid bonding”), which is a direct bonding technology (e.g., forming bonding between surfaces without using intermediate layers, such as solder or adhesives) and can obtain metal-metal bonding and dielectric-dielectric bonding simultaneously. In some embodiments, bonding interface106is the place at which bonding layers112and110are met and bonded. In practice, bonding interface106can be a layer with a certain thickness that includes the top surface of bonding layer110of first semiconductor structure102and the bottom surface of bonding layer112of second semiconductor structure104.

In some embodiments, second semiconductor structure104of 3D memory device100further includes an interconnect layer (not shown) above bonding layer112to transfer electrical signals. The interconnect layer can include a plurality of interconnects, such as MEOL interconnects and BEOL interconnects. The interconnect layer can further include one or more ILD layers in which the interconnect lines and VIA contacts can form. The interconnect lines and VIA contacts in the interconnect layer can include conductive materials including, but not limited to W, Co, Cu, Al, silicides, or any combination thereof. The ILD layers in the interconnect layer can include dielectric materials including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof.

In some embodiments, 3D memory device100is a NAND Flash memory device in which memory cells are provided in the form of an array of NAND memory strings. As shown inFIG.1, second semiconductor structure104of 3D memory device100can include an array of channel structures124functioning as the array of NAND memory strings. As shown inFIG.1, each channel structure124can extend vertically through a plurality of pairs each including a conductive layer116and a dielectric layer118. The interleaved conductive layers116and dielectric layers118are part of a memory stack114. The number of the pairs of conductive layers116and dielectric layers118in memory stack114(e.g., 32, 64, 96, 128, 160, 192, 224, 256, or more) determines the number of memory cells in 3D memory device100. It is understood that in some embodiments, memory stack114may have a multi-deck architecture (not shown), which includes a plurality of memory decks stacked over one another. The numbers of the pairs of conductive layers116and dielectric layers118in each memory deck can be the same or different.

Memory stack114can include a plurality of interleaved conductive layers116and dielectric layers118. Conductive layers116and dielectric layers118in memory stack114can alternate in the vertical direction. In other words, except the ones at the top or bottom of memory stack114, each conductive layer116can be adjoined by two dielectric layers118on both sides, and each dielectric layer118can be adjoined by two conductive layers116on both sides. Conductive layers116can include conductive materials including, but not limited to, W, Co, Cu, Al, polysilicon, doped silicon, silicides, or any combination thereof. Each conductive layer116can include a gate electrode (gate line) surrounded by an adhesive layer and a gate dielectric layer. The gate electrode of conductive layer116can extend laterally as a word line, ending at one or more staircase structures of memory stack114. Dielectric layers118can include dielectric materials including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof.

As shown inFIG.1, second semiconductor structure104of 3D memory device100can also include an N-type doped semiconductor layer120above memory stack114. N-type doped semiconductor layer120can be an example of the “sidewall SEG” as described above. N-type doped semiconductor layer120can include a semiconductor material, such as silicon. In some embodiments, N-type doped semiconductor layer120includes polysilicon formed by deposition techniques, as described below in detail. In some embodiments, N-type doped semiconductor layer120includes single crystalline silicon, such as the device layer of an SOI wafer, as described below in detail. N-type doped semiconductor layer120can be doped with any suitable N-type dopants, such as phosphorus (P), arsenic (Ar), or antimony (Sb), which contribute free electrons and increase the conductivity of the intrinsic semiconductor. For example, N-type doped semiconductor layer120may be a polysilicon layer doped with N-type dopant(s), such as P, Ar, or Sb. In some embodiments, N-type doped semiconductor layer120is a single polysilicon layer with a uniform doping concentration profile in the vertical direction, as opposed to having multiple polysilicon sub-layers with nonuniform doping concentrations at their interfaces (e.g., a sudden doping concentration change at an interface between two sub-layers). It is understood that the doping concentration of the N-type dopant(s) of N-type doped semiconductor layer120may still gradually change in the vertical direction as long as there are not any sudden doping concentration changes that can distinguish two or more sub-layers by doping concentration variations.

In some embodiments, each channel structure124includes a channel hole filled with a semiconductor layer (e.g., as a semiconductor channel128) and a composite dielectric layer (e.g., as a memory film126). In some embodiments, semiconductor channel128includes silicon, such as amorphous silicon, polysilicon, or single crystalline silicon. In some embodiments, memory film126is a composite layer including a tunneling layer, a storage layer (also known as a “charge trap layer”), and a blocking layer. The remaining space of channel structure124can be partially or fully filled with a capping layer including dielectric materials, such as silicon oxide, and/or an air gap. Channel structure124can have a cylinder shape (e.g., a pillar shape). The capping layer, semiconductor channel128, the tunneling layer, storage layer, and blocking layer of memory film126are arranged radially from the center toward the outer surface of the pillar in this order, according to some embodiments. The tunneling layer can include silicon oxide, silicon oxynitride, or any combination thereof. The storage layer can include silicon nitride, silicon oxynitride, silicon, or any combination thereof. The blocking layer can include silicon oxide, silicon oxynitride, high-k dielectrics, or any combination thereof. In one example, memory film126can include a composite layer of silicon oxide/silicon oxynitride/silicon oxide (ONO).

In some embodiments, channel structure124further includes a channel plug129in the bottom portion (e.g., at the lower end) of channel structure124. As used herein, the “upper end” of a component (e.g., channel structure124) is the end farther away from substrate101in the y-direction, and the “lower end” of the component (e.g., channel structure124) is the end closer to substrate101in the y-direction when substrate101is positioned in the lowest plane of 3D memory device100. Channel plug129can include semiconductor materials (e.g., polysilicon). In some embodiments, channel plug129functions as the drain of the NAND memory string.

As shown inFIG.1, each channel structure124can extend vertically through interleaved conductive layers116and dielectric layers118of memory stack114into N-type doped semiconductor layer120. The upper end of each channel structure124can be flush with or below the top surface of N-type doped semiconductor layer120. That is, channel structure124does not extend beyond the top surface of N-type doped semiconductor layer120, according to some embodiments. In some embodiments, the upper end of memory film126is below the upper end of semiconductor channel128in channel structure124, as shown inFIG.1. In some embodiments, the upper end of memory film126is below the top surface of N-type doped semiconductor layer120, and the upper end of semiconductor channel128is flush with or below the top surface of N-type doped semiconductor layer120. For example, as shown inFIG.1, memory film126may end at the bottom surface of N-type doped semiconductor layer120, while semiconductor channel128may extend above the bottom surface of N-type doped semiconductor layer120, such that N-type doped semiconductor layer120may surround and in contact with a top portion127of semiconductor channel128extending into N-type doped semiconductor layer120. In some embodiments, the doping concentration of top portion127of semiconductor channel128extending into N-type doped semiconductor layer120is different from the doping concentration of the rest of semiconductor channel128. For example, semiconductor channel128may include undoped polysilicon except top portion127, which may include doped polysilicon to increase its conductivity in forming an electrical connection with the surrounding N-type doped semiconductor layer120.

In some embodiments, N-type doped semiconductor layer120includes semiconductor plugs122each surrounding and in contact with top portion127of respective semiconductor channel128of channel structure124extending into N-type doped semiconductor layer120. Semiconductor plug122includes doped polysilicon, for example, N-type doped polysilicon, according to some embodiments. The doping concentration of semiconductor plugs122can be different from the doping concentration of the rest of N-type doped semiconductor layer120since semiconductor plugs122can be formed in a later process after the formation of the rest of N-type doped semiconductor layer120, as described below in detail. In some embodiments, semiconductor plugs122include polysilicon (e.g., N-type doped polysilicon), and the rest of N-type doped semiconductor layer120includes single crystalline silicon (e.g., N-type doped single crystalline silicon). In some embodiments, semiconductor plugs122include polysilicon (e.g., N-type doped polysilicon), and the rest of N-type doped semiconductor layer120includes polysilicon (e.g., N-type doped polysilicon), but with doping centration different from that of semiconductor plugs122.

Each semiconductor plug122can surround and in contact with the sidewall of top portion127of respective semiconductor channel128. As a result, semiconductor plugs122in N-type doped semiconductor layer120can work as a “sidewall SEG (e.g., semiconductor plug)” of channel structure124to replace the “bottom SEG (e.g., semiconductor plug).” Moreover, as described below in detail, the formation of semiconductor plugs122occurs at the opposite side of memory stack114, which can avoid any deposition or etching process through openings extending through memory stack114, thereby reducing the fabrication complexity and cost and increasing the yield and vertical scalability. Depending on the relative position of the upper end of semiconductor channel128of each channel structure124with respect to the top surface of N-type doped semiconductor layer120, semiconductor plug122may be formed above and in contact with the upper end of semiconductor channel128as well, for example, as shown inFIG.1, when the upper end of semiconductor channel128is below the top surface of N-type doped semiconductor layer120. It is understood that in other examples in which the upper end of semiconductor channel128is flush with the top surface of N-type doped semiconductor layer120, semiconductor plug122may be formed surrounding and in contact with the sidewall of top portion127of semiconductor channel128only.

Nevertheless, N-type doped semiconductor layer120surrounding top portion127of semiconductor channels128of channel structures124with semiconductor plugs122(e.g., as sidewall SEGs) can enable GIDL-assisted body biasing for erase operations for 3D memory device100. The GIDL around the source select gate of the NAND memory string can generate hole current into the NAND memory string to raise the body potential for erase operations.

As shown inFIG.1, second semiconductor structure104of 3D memory device100can further include insulating structures130each extending vertically through interleaved conductive layers116and dielectric layers118of memory stack114. Different from channel structure124that extends further into N-type doped semiconductor layer120, insulating structures130stops at the bottom surface of N-type doped semiconductor layer120, i.e., does not extend vertically into N-type doped semiconductor layer120, according to some embodiments. That is, the top surface of insulating structure130can be flush with the bottom surface of N-type doped semiconductor layer120. Each insulating structure130can also extend laterally to separate channel structures124into a plurality of blocks. That is, memory stack114can be divided into a plurality of memory blocks by insulating structures130, such that the array of channel structures124can be separated into each memory block. Different from the slit structures in existing 3D NAND memory devices described above, which include front side ACS contacts, insulating structure130does not include any contact therein (i.e., not functioning as the source contact) and thus, does not introduce parasitic capacitance and leakage current with conductive layers116(including word lines), according to some embodiments. In some embodiments, each insulating structure130includes an opening (e.g., a slit) filled with one or more dielectric materials, including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof. In one example, each insulating structure130may be filled with silicon oxide.

Moreover, as described below in detail, because the opening for forming insulating structure130is not used for forming N-type doped semiconductor layer120and semiconductor plugs122therein (e.g., as sidewall SEGs), the increased aspect ratio of the opening as the number of interleaved conductive layers116and dielectric layers118increases would not affect the formation of N-type doped semiconductor layer120and semiconductor plugs122therein.

Instead of the front side source contacts, 3D memory device100can include a backside source contact132above memory stack114and in contact with N-type doped semiconductor layer120, as shown inFIG.1. Source contact132and memory stack114(and insulating structure130therethrough) can be disposed at opposites sides of N-type doped semiconductor layer120and thus, viewed as a “backside” source contact. In some embodiments, source contact132is electrically connected to semiconductor channel128of channel structure124through semiconductor plug122of N-type doped semiconductor layer120. In some embodiments, source contact132is not laterally aligned with insulating structure130, but approximate to channel structure124to reduce the resistance of the electrical connection therebetween. For example, source contact132may be laterally between insulating structure130and channel structure124(e.g., in the x-direction inFIG.1). Source contacts132can include any suitable types of contacts. In some embodiments, source contacts132include a VIA contact. In some embodiments, source contacts132include a wall-shaped contact extending laterally. Source contact132can include one or more conductive layers, such as a metal layer (e.g., W, Co, Cu, or Al) or a silicide layer surrounded by an adhesive layer (e.g., titanium nitride (TiN)).

As shown inFIG.1, 3D memory device100can further include a BEOL interconnect layer133above and electrically connected to source contact132for pad-out, e.g., transferring electrical signals between 3D memory device100and external circuits. In some embodiments, interconnect layer133includes one or more ILD layers134on N-type doped semiconductor layer120and a redistribution layer136on ILD layers134. The upper end of source contact132is flush with the top surface of ILD layers134, and the bottom surface of redistribution layer136, and source contact132extends vertically through ILD layers134into N-type doped semiconductor layer120, according to some embodiments. ILD layers134in interconnect layer133can include dielectric materials including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof. Redistribution layer136in interconnect layer133can include conductive materials including, but not limited to W, Co, Cu, Al, silicides, or any combination thereof. In one example, redistribution layer136includes Al. In some embodiments, interconnect layer133further includes a passivation layer138as the outmost layer for passivation and protection of 3D memory device100. Part of redistribution layer136can be exposed from passivation layer138as contact pads140. That is, interconnect layer133of 3D memory device100can also include contact pads140for wire bonding and/or bonding with an interposer.

In some embodiments, second semiconductor structure104of 3D memory device100further includes contacts142and144through N-type doped semiconductor layer120. As N-type doped semiconductor layer120can be a thinned substrate, for example, the device layer of an SOI wafer, contacts142and144are through silicon contacts (TSCs), according to some embodiments. In some embodiments, contact142extends through N-type doped semiconductor layer120and ILD layers134to be in contact with redistribution layer136, such that N-type doped semiconductor layer120is electrically connected to contact142through source contact132and redistribution layer136of interconnect layer133. In some embodiments, contact144extends through N-type doped semiconductor layer120and ILD layers134to be in contact with contact pad140. Contacts142and144each can include one or more conductive layers, such as a metal layer (e.g., W, Co, Cu, or Al) or a silicide layer surrounded by an adhesive layer (e.g., TiN). In some embodiments, at least contact144further includes a spacer (e.g., a dielectric layer) to electrically separate contact144from N-type doped semiconductor layer120.

In some embodiments, 3D memory device100further includes peripheral contacts146and148each extending vertically outside of memory stack114. Each peripheral contact146or148can have a depth greater than the depth of memory stack114to extend vertically from bonding layer112to N-type doped semiconductor layer120in a peripheral region that is outside of memory stack114. In some embodiments, peripheral contact146is below and in contact with contact142, such that N-type doped semiconductor layer120is electrically connected to peripheral circuit108in first semiconductor structure102through at least source contact132, interconnect layer133, contact142, and peripheral contact146. In some embodiments, peripheral contact148is below and in contact with contact144, such that peripheral circuit108in first semiconductor structure102is electrically connected to contact pad140for pad-out through at least contact144and peripheral contact148. Peripheral contacts146and148each can include one or more conductive layers, such as a metal layer (e.g., W, Co, Cu, or Al) or a silicide layer surrounded by an adhesive layer (e.g., TiN).

As shown inFIG.1, 3D memory device100also includes a variety of local contacts (also known as “Cl”) as part of the interconnect structure, which are in contact with a structure in memory stack114directly. In some embodiments, the local contacts include channel local contacts150each below and in contact with the lower end of respective channel structure124. Each channel local contact150can be electrically connected to a bit line contact (not shown) for bit line fan-out. In some embodiments, the local contacts further include word line local contacts152each below and in contact with respective conductive layer116(including a word line) at the staircase structure of memory stack114for word line fan-out. Local contacts, such as channel local contacts150and word line local contacts152, can be electrically connected to peripheral circuits108of first semiconductor structure102through at least bonding layers112and110. Local contacts, such as channel local contacts150and word line local contacts152, each can include one or more conductive layers, such as a metal layer (e.g., W, Co, Cu, or Al) or a silicide layer surrounded by an adhesive layer (e.g., TiN).

FIG.2illustrates a side view of a cross-section of another exemplary 3D memory device200, according to some embodiments of the present disclosure. In some embodiments, 3D memory device200is a bonded chip including a first semiconductor structure202and a second semiconductor structure204stacked over first semiconductor structure202. First and second semiconductor structures202and204are jointed at a bonding interface206therebetween, according to some embodiments. As shown inFIG.2, first semiconductor structure202can include a substrate201, which can include silicon (e.g., single crystalline silicon, c-Si), SiGe, GaAs, Ge, SOI, or any other suitable materials.

First semiconductor structure202of 3D memory device200can include peripheral circuits208on substrate201. In some embodiments, peripheral circuit208is configured to control and sense 3D memory device200. Peripheral circuit208can be any suitable digital, analog, and/or mixed-signal control and sensing circuits used for facilitating the operation of 3D memory device200including, but not limited to, a page buffer, a decoder (e.g., a row decoder and a column decoder), a sense amplifier, a driver (e.g., a word line driver), a charge pump, a current or voltage reference, or any active or passive components of the circuit (e.g., transistors, diodes, resistors, or capacitors). Peripheral circuits208can include transistors formed “on” substrate201, in which the entirety or part of the transistors are formed in substrate201(e.g., below the top surface of substrate201) and/or directly on substrate201. Isolation regions (e.g., shallow trench isolations (STIs)) and doped regions (e.g., source regions and drain regions of the transistors) can be formed in substrate201as well. The transistors are high-speed with advanced logic processes (e.g., technology nodes of 90 nm, 65 nm, 45 nm, 32 nm, 28 nm, 20 nm, 16 nm, 14 nm, 10 nm, 7 nm, 5 nm, 3 nm, 2 nm, etc.), according to some embodiments. It is understood that in some embodiments, peripheral circuit208may further include any other circuits compatible with the advanced logic processes including logic circuits, such as processors and PLDs, or memory circuits, such as SRAM and DRAM.

In some embodiments, first semiconductor structure202of 3D memory device200further includes an interconnect layer (not shown) above peripheral circuits208to transfer electrical signals to and from peripheral circuits208. The interconnect layer can include a plurality of interconnects (also referred to herein as “contacts”), including lateral interconnect lines and VIA contacts. As used herein, the term “interconnects” can broadly include any suitable types of interconnects, such as MEOL interconnects and BEOL interconnects. The interconnect layer can further include one or more ILD layers (also known as “(IMD layers”) in which the interconnect lines and VIA contacts can form. That is, the interconnect layer can include interconnect lines and VIA contacts in multiple ILD layers. The interconnect lines and VIA contacts in the interconnect layer can include conductive materials including, but not limited to, W, Co, Cu, Al, silicides, or any combination thereof. The ILD layers in the interconnect layer can include dielectric materials including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof.

As shown inFIG.2, first semiconductor structure202of 3D memory device200can further include a bonding layer210at bonding interface206and above the interconnect layer and peripheral circuits208. Bonding layer210can include a plurality of bonding contacts211and dielectrics electrically isolating bonding contacts211. Bonding contacts211can include conductive materials including, but not limited to, W, Co, Cu, Al, silicides, or any combination thereof. The remaining area of bonding layer210can be formed with dielectrics including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof. Bonding contacts211and surrounding dielectrics in bonding layer210can be used for hybrid bonding.

Similarly, as shown inFIG.2, second semiconductor structure204of 3D memory device200can also include a bonding layer212at bonding interface206and above bonding layer210of first semiconductor structure202. Bonding layer212can include a plurality of bonding contacts213and dielectrics electrically isolating bonding contacts213. Bonding contacts213can include conductive materials including, but not limited to, W, Co, Cu, Al, silicides, or any combination thereof. The remaining area of bonding layer212can be formed with dielectrics including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof. Bonding contacts213and surrounding dielectrics in bonding layer212can be used for hybrid bonding. Bonding contacts213are in contact with bonding contacts211at bonding interface206, according to some embodiments.

As described below in detail, second semiconductor structure204can be bonded on top of first semiconductor structure202in a face-to-face manner at bonding interface206. In some embodiments, bonding interface206is disposed between bonding layers210and212as a result of hybrid bonding (also known as “metal/dielectric hybrid bonding”), which is a direct bonding technology (e.g., forming bonding between surfaces without using intermediate layers, such as solder or adhesives) and can obtain metal-metal bonding and dielectric-dielectric bonding simultaneously. In some embodiments, bonding interface206is the place at which bonding layers212and210are met and bonded. In practice, bonding interface206can be a layer with a certain thickness that includes the top surface of bonding layer210of first semiconductor structure202and the bottom surface of bonding layer212of second semiconductor structure204.

In some embodiments, second semiconductor structure204of 3D memory device200further includes an interconnect layer (not shown) above bonding layer212to transfer electrical signals. The interconnect layer can include a plurality of interconnects, such as MEOL interconnects and BEOL interconnects. The interconnect layer can further include one or more ILD layers in which the interconnect lines and VIA contacts can form. The interconnect lines and VIA contacts in the interconnect layer can include conductive materials including, but not limited to W, Co, Cu, Al, silicides, or any combination thereof. The ILD layers in the interconnect layer can include dielectric materials including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof.

In some embodiments, 3D memory device200is a NAND Flash memory device in which memory cells are provided in the form of an array of NAND memory strings. As shown inFIG.2, second semiconductor structure204of 3D memory device200can include an array of channel structures224functioning as the array of NAND memory strings. As shown inFIG.2, each channel structure224can extend vertically through a plurality of pairs each including a conductive layer216and a dielectric layer218. The interleaved conductive layers216and dielectric layers218are part of a memory stack214. The number of the pairs of conductive layers216and dielectric layers218in memory stack214(e.g., 32, 64, 96, 128, 160, 192, 224, 256, or more) determines the number of memory cells in 3D memory device200. It is understood that in some embodiments, memory stack214may have a multi-deck architecture (not shown), which includes a plurality of memory decks stacked over one another. The numbers of the pairs of conductive layers216and dielectric layers218in each memory deck can be the same or different.

Memory stack214can include a plurality of interleaved conductive layers216and dielectric layers218. Conductive layers216and dielectric layers218in memory stack214can alternate in the vertical direction. In other words, except the ones at the top or bottom of memory stack214, each conductive layer216can be adjoined by two dielectric layers218on both sides, and each dielectric layer218can be adjoined by two conductive layers216on both sides. Conductive layers216can include conductive materials including, but not limited to, W, Co, Cu, Al, polysilicon, doped silicon, silicides, or any combination thereof. Each conductive layer216can include a gate electrode (gate line) surrounded by an adhesive layer and a gate dielectric layer. The gate electrode of conductive layer216can extend laterally as a word line, ending at one or more staircase structures of memory stack214. Dielectric layers218can include dielectric materials including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof.

As shown inFIG.2, second semiconductor structure204of 3D memory device200can also include a P-type doped semiconductor layer220above memory stack114. P-type doped semiconductor layer220can be an example of the “sidewall SEG” as described above. P-type doped semiconductor layer220can include a semiconductor material, such as silicon. In some embodiments, P-type doped semiconductor layer220includes polysilicon formed by deposition techniques, as described below in detail. In some embodiments, P-type doped semiconductor layer220includes single crystalline silicon, such as the device layer of an SOI wafer, as described below in detail. P-type doped semiconductor layer220can be doped with any suitable P-type dopants, such as boron (B), gallium (Ga), or aluminum (Al), to an intrinsic semiconductor creates deficiencies of valence electrons, called “holes.” For example, P-type doped semiconductor layer220may be a polysilicon layer doped with P-type dopant(s), such as P, Ar, or Sb. In some embodiments, P-type doped semiconductor layer220is a single polysilicon layer with a uniform doping concentration profile in the vertical direction, as opposed to having multiple polysilicon sub-layers with nonuniform doping concentrations at their interfaces (e.g., a sudden doping concentration change at an interface between two sub-layers). It is understood that the doping concentration of the P-type dopant(s) of P-type doped semiconductor layer220may still gradually change in the vertical direction as long as there are not any sudden doping concentration changes that can distinguish two or more sub-layers by doping concentration variations.

In some embodiments, second semiconductor structure204of 3D memory device200further includes an N-well221in P-type doped semiconductor layer220. N-well221can be doped with any suitable N-type dopants, such as P, Ar, or Sb, which contribute free electrons and increase the conductivity of the intrinsic semiconductor. In some embodiments, N-well221is doped from the bottom surface of P-type doped semiconductor layer220. It is understood that N-well221may extend vertically in the entire thickness of P-type doped semiconductor layer220, i.e., to the top surface of P-type doped semiconductor layer220, or part of the entire thickness of P-type doped semiconductor layer220.

In some embodiments, each channel structure224includes a channel hole filled with a semiconductor layer (e.g., as a semiconductor channel228) and a composite dielectric layer (e.g., as a memory film226). In some embodiments, semiconductor channel228includes silicon, such as amorphous silicon, polysilicon, or single crystalline silicon. In some embodiments, memory film226is a composite layer including a tunneling layer, a storage layer (also known as a “charge trap layer”), and a blocking layer. The remaining space of channel structure224can be partially or fully filled with a capping layer including dielectric materials, such as silicon oxide, and/or an air gap. Channel structure224can have a cylinder shape (e.g., a pillar shape). The capping layer, semiconductor channel228, the tunneling layer, storage layer, and blocking layer of memory film226are arranged radially from the center toward the outer surface of the pillar in this order, according to some embodiments. The tunneling layer can include silicon oxide, silicon oxynitride, or any combination thereof. The storage layer can include silicon nitride, silicon oxynitride, silicon, or any combination thereof. The blocking layer can include silicon oxide, silicon oxynitride, high-k dielectrics, or any combination thereof. In one example, memory film226can include a composite layer of silicon oxide/silicon oxynitride/silicon oxide (ONO).

In some embodiments, channel structure224further includes a channel plug227in the bottom portion (e.g., at the lower end) of channel structure224. As used herein, the “upper end” of a component (e.g., channel structure224) is the end farther away from substrate201in the y-direction, and the “lower end” of the component (e.g., channel structure224) is the end closer to substrate201in the y-direction when substrate201is positioned in the lowest plane of 3D memory device200. Channel plug227can include semiconductor materials (e.g., polysilicon). In some embodiments, channel plug227functions as the drain of the NAND memory string.

As shown inFIG.2, each channel structure224can extend vertically through interleaved conductive layers216and dielectric layers218of memory stack214into P-type doped semiconductor layer220. The upper end of each channel structure224can be flush with or below the top surface of P-type doped semiconductor layer220. That is, channel structure224does not extend beyond the top surface of P-type doped semiconductor layer220, according to some embodiments. In some embodiments, the upper end of memory film226is below the upper end of semiconductor channel228in channel structure224, as shown inFIG.2. In some embodiments, the upper end of memory film226is below the top surface of P-type doped semiconductor layer220, and the upper end of semiconductor channel228is flush with or below the top surface of P-type doped semiconductor layer220. For example, as shown inFIG.2, memory film226may end at the bottom surface of P-type doped semiconductor layer220, while semiconductor channel228may extend above the bottom surface of P-type doped semiconductor layer220, such that P-type doped semiconductor layer220may surround and in contact with a top portion229of semiconductor channel228extending into P-type doped semiconductor layer220. In some embodiments, the doping concentration of top portion229of semiconductor channel228extending into P-type doped semiconductor layer220is different from the doping concentration of the rest of semiconductor channel228. For example, semiconductor channel228may include undoped polysilicon except top portion229, which may include doped polysilicon to increase its conductivity in forming an electrical connection with surrounding P-type doped semiconductor layer220.

In some embodiments, P-type doped semiconductor layer220includes semiconductor plugs222each surrounding and in contact with top portion229of respective semiconductor channel228of channel structure224extending into P-type doped semiconductor layer220. Semiconductor plug222includes doped polysilicon, for example, P-type doped polysilicon, according to some embodiments. The doping concentration of semiconductor plugs222can be different from the doping concentration of the rest of P-type doped semiconductor layer220since semiconductor plugs222can be formed in a later process after the formation of the rest of P-type doped semiconductor layer220, as described below in detail. In some embodiments, semiconductor plugs222include polysilicon (e.g., P-type doped polysilicon), and the rest of P-type doped semiconductor layer220includes single crystalline silicon (e.g., P-type doped single crystalline silicon). In some embodiments, semiconductor plugs222include polysilicon (e.g., P-type doped polysilicon), and the rest of P-type doped semiconductor layer220includes polysilicon (e.g., P-type doped polysilicon), but with doping centration different from that of semiconductor plugs222.

Each semiconductor plug222can surround and in contact with the sidewall of top portion229of respective semiconductor channel228. As a result, semiconductor plugs222in P-type doped semiconductor layer220can work as a “sidewall SEG (e.g., semiconductor plug)” of channel structure224to replace the “bottom SEG (e.g., semiconductor plug).” Moreover, as described below in detail, the formation of semiconductor plugs222occurs at the opposite side of memory stack214, which can avoid any deposition or etching process through openings extending through memory stack214, thereby reducing the fabrication complexity and cost and increasing the yield and vertical scalability. Depending on the relative position of the upper end of semiconductor channel228of each channel structure224with respect to the top surface of P-type doped semiconductor layer220, semiconductor plug222may be formed above and in contact with the upper end of semiconductor channel228as well, for example, as shown inFIG.2, when the upper end of semiconductor channel228is below the top surface of P-type doped semiconductor layer220. It is understood that in other examples in which the upper end of semiconductor channel228is flush with the top surface of P-type doped semiconductor layer220, semiconductor plug222may be formed surrounding and in contact with the sidewall of top portion229of semiconductor channel228only.

Nevertheless, P-type doped semiconductor layer220surrounding top portion229of semiconductor channels228of channel structures224with semiconductor plugs222(e.g., as sidewall SEGs) can enable P-well bulk erase operations for 3D memory device200. The design of the 3D memory device200disclosed herein can achieve the separation of the hole current path and the electron current path for forming erase operations and read operations, respectively. In some embodiments, 3D memory device200is configured to form an electron current path between the electron source (e.g., N-well221) and semiconductor channel228of channel structure224to provide electrons to the NAND memory string when performing a read operation, according to some embodiments. Conversely, 3D memory device200is configured to form a hole current path between the hole source (e.g., P-type doped semiconductor layer220) and semiconductor channel228of channel structure224to provide holes to the NAND memory string when performing a P-well bulk erase operation, according to some embodiments.

As shown inFIG.2, second semiconductor structure204of 3D memory device200can further include insulating structures230each extending vertically through interleaved conductive layers216and dielectric layers218of memory stack214. Different from channel structure224that extends further into P-type doped semiconductor layer220, insulating structures230stops at the bottom surface of P-type doped semiconductor layer220, i.e., does not extend vertically into P-type doped semiconductor layer220, according to some embodiments. That is, the top surface of insulating structure230can be flush with the bottom surface of P-type doped semiconductor layer220. Each insulating structure230can also extend laterally to separate channel structures224into a plurality of blocks. That is, memory stack214can be divided into a plurality of memory blocks by insulating structures230, such that the array of channel structures224can be separated into each memory block. Different from the slit structures in existing 3D NAND memory devices described above, which include front side ACS contacts, insulating structure230does not include any contact therein (i.e., not functioning as the source contact) and thus, does not introduce parasitic capacitance and leakage current with conductive layers216(including word lines), according to some embodiments. In some embodiments, each insulating structure230includes an opening (e.g., a slit) filled with one or more dielectric materials, including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof. In one example, each insulating structure230may be filled with silicon oxide.

Moreover, as described below in detail, because the opening for forming insulating structure230is not used for forming P-type doped semiconductor layer220and semiconductor plugs222therein (e.g., as sidewall SEGs), the increased aspect ratio of the opening as the number of interleaved conductive layers216and dielectric layers218increases would not affect the formation of P-type doped semiconductor layer220and semiconductor plugs222therein.

Instead of the front side source contacts, 3D memory device100can include backside source contacts231and232above memory stack214and in contact with N-well221and P-type doped semiconductor layer220, respectively, as shown inFIG.1. Source contacts231and232and memory stack214(and insulating structure230therethrough) can be disposed at opposites sides of P-type doped semiconductor layer220and thus, viewed as “backside” source contacts. In some embodiments, source contact232in contact with P-type doped semiconductor layer220is electrically connected to semiconductor channel228of channel structure224through semiconductor plug222of P-type doped semiconductor layer220. In some embodiments, source contact231in contact with N-well221is electrically connected to semiconductor channel228of channel structure224through semiconductor plug222of P-type doped semiconductor layer220. In some embodiments, source contact232is not laterally aligned with insulating structure230and is approximate to channel structure224to reduce the resistance of the electrical connection therebetween. It is understood that although source contact231is laterally aligned with insulating structure230as shown inFIG.2, in some examples, source contact231may not be laterally aligned with insulating structure230, but approximate to channel structure224(e.g., laterally between insulating structure230and channel structure224) to reduce the resistance of the electrical connection therebetween as well. As described above, source contacts231and232can be used to separately control the electron current and hole current during the read operations and erase operations, respectively. Source contacts231and232can include any suitable types of contacts. In some embodiments, source contacts231and232include a VIA contact. In some embodiments, source contacts231and232include a wall-shaped contact extending laterally. Source contacts231and232can include one or more conductive layers, such as a metal layer (e.g., W, Co, Cu, or Al) or a silicide layer surrounded by an adhesive layer (e.g., titanium nitride (TiN)).

As shown inFIG.2, 3D memory device100can further include a BEOL interconnect layer233above and electrically connected to source contacts231and232for pad-out, e.g., transferring electrical signals between 3D memory device200and external circuits. In some embodiments, interconnect layer233includes one or more ILD layers234on P-type doped semiconductor layer220and a redistribution layer236on ILD layers234. The upper end of source contact231or232is flush with the top surface of ILD layers234and the bottom surface of redistribution layer236. Source contacts231and232can be electrically separated by on ILD layers234. In some embodiments, source contact232extends vertically through ILD layers234into P-type doped semiconductor layer220to make an electrical connection with P-type doped semiconductor layer220. In some embodiments, source contact231extends vertically through ILD layers234and P-type doped semiconductor layer220into N-well221to make an electrical connection with N-well. Source contact231can include a spacer (e.g., a dielectric layer) surrounding its sidewall to be electrically separated from P-type doped semiconductor layer220. Redistribution layer236can include two electrically separated interconnects: a first interconnect236-1in contact with source contact232and a second interconnect236-2in contact with source contact231.

ILD layers234in interconnect layer233can include dielectric materials including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof. Redistribution layer236in interconnect layer233can include conductive materials including, but not limited to W, Co, Cu, Al, silicides, or any combination thereof. In one example, redistribution layer236includes Al. In some embodiments, interconnect layer233further includes a passivation layer238as the outmost layer for passivation and protection of 3D memory device200. Part of redistribution layer236can be exposed from passivation layer238as contact pads240. That is, interconnect layer233of 3D memory device200can also include contact pads240for wire bonding and/or bonding with an interposer.

In some embodiments, second semiconductor structure204of 3D memory device200further includes contacts242,243, and244through P-type doped semiconductor layer220. As P-type doped semiconductor layer220can be a thinned substrate, for example, the device layer of a SOI wafer, contacts242,243, and244are TSCs, according to some embodiments. In some embodiments, contact242extends through P-type doped semiconductor layer220and ILD layers234to be in contact with first interconnect236-1of redistribution layer236, such that P-type doped semiconductor layer220is electrically connected to contact242through source contact232and first interconnect236-1of interconnect layer233. In some embodiments, contact243extends through P-type doped semiconductor layer220and ILD layers234to be in contact with second interconnect236-2of redistribution layer236, such that N-well221is electrically connected to contact243through source contact231and second interconnect236-2of interconnect layer233. In some embodiments, contact244extends through P-type doped semiconductor layer220and ILD layers234to be in contact with contact pad240. Contacts242,243, and244each can include one or more conductive layers, such as a metal layer (e.g., W, Co, Cu, or Al) or a silicide layer surrounded by an adhesive layer (e.g., TiN). In some embodiments, at least contacts243and244each further include a spacer (e.g., a dielectric layer) to electrically separate contacts243and244from P-type doped semiconductor layer220.

In some embodiments, 3D memory device200further includes peripheral contacts246,247, and248each extending vertically outside of memory stack214. Each peripheral contact246,247, or248can have a depth greater than the depth of memory stack214to extend vertically from bonding layer212to P-type doped semiconductor layer220in a peripheral region that is outside of memory stack214. In some embodiments, peripheral contact246is below and in contact with contact242, such that P-type doped semiconductor layer220is electrically connected to peripheral circuit208in first semiconductor structure202through at least source contact232, first interconnect236-1of interconnect layer233, contact242, and peripheral contact246. In some embodiments, peripheral contact247is below and in contact with contact243, such that N-well221is electrically connected to peripheral circuit208in first semiconductor structure202through at least source contact231, second interconnect236-2of interconnect layer233, contact243, and peripheral contact247. That is, the electron current and hole current for read operations and erase operations can be separately controlled by peripheral circuits208through different electrical connections. In some embodiments, peripheral contact248is below and in contact with contact244, such that peripheral circuit208in first semiconductor structure202is electrically connected to contact pad240for pad-out through at least contact244and peripheral contact248. Peripheral contacts246,247, and248each can include one or more conductive layers, such as a metal layer (e.g., W, Co, Cu, or Al) or a silicide layer surrounded by an adhesive layer (e.g., TiN).

As shown inFIG.2, 3D memory device200also includes a variety of local contacts (also known as “Cl”) as part of the interconnect structure, which are in contact with a structure in memory stack214directly. In some embodiments, the local contacts include channel local contacts250each below and in contact with the lower end of respective channel structure224. Each channel local contact250can be electrically connected to a bit line contact (not shown) for bit line fan-out. In some embodiments, the local contacts further include word line local contacts252each below and in contact with respective conductive layer216(including a word line) at the staircase structure of memory stack214for word line fan-out. Local contacts, such as channel local contacts250and word line local contacts252, can be electrically connected to peripheral circuits208of first semiconductor structure202through at least bonding layers212and210. Local contacts, such as channel local contacts250and word line local contacts252, each can include one or more conductive layers, such as a metal layer (e.g., W, Co, Cu, or Al) or a silicide layer surrounded by an adhesive layer (e.g., TiN).

FIGS.3A-3Nillustrate a fabrication process for forming an exemplary 3D memory device, according to some embodiments of the present disclosure.FIG.5Aillustrates a flowchart of a method500for forming an exemplary 3D memory device, according to some embodiments of the present disclosure.FIG.5Billustrates a flowchart of another method501for forming an exemplary 3D memory device, according to some embodiments of the present disclosure. Examples of the 3D memory device depicted inFIGS.3A-3N,5A, and5Binclude 3D memory device100depicted inFIG.1.FIGS.3A-3N,5A, and5Bwill be described together. It is understood that the operations shown in methods500and501are not exhaustive and that other operations can be performed as well before, after, or between any of the illustrated operations. Further, some of the operations may be performed simultaneously, or in a different order than shown inFIGS.5A and5B.

Referring toFIG.5A, method500starts at operation502, in which a peripheral circuit is formed on a first substrate. The first substrate can be a silicon substrate. As illustrated inFIG.3G, a plurality of transistors are formed on a silicon substrate350using a plurality of processes including, but not limited to, photolithography, etching, thin film deposition, thermal growth, implantation, chemical mechanical polishing (CMP), and any other suitable processes. In some embodiments, doped regions (not shown) are formed in silicon substrate350by ion implantation and/or thermal diffusion, which function, for example, as source regions and/or drain regions of the transistors. In some embodiments, isolation regions (e.g., STIs) are also formed in silicon substrate350by wet etching and/or dry etching and thin film deposition. The transistors can form peripheral circuits352on silicon substrate350.

As illustrated inFIG.3G, a bonding layer348is formed above peripheral circuits352. Bonding layer348includes bonding contacts electrically connected to peripheral circuits352. To form bonding layer348, an ILD layer is deposited using one or more thin film deposition processes, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof; the bonding contacts through the ILD layer are formed using wet etching and/or dry etching, e.g., reactive ion etching (RIE), followed by one or more thin film deposition processes, such as ALD, CVD, PVD, any other suitable processes, or any combination thereof.

A channel structure extending vertically through a memory stack and an N-type doped semiconductor layer can be formed above a second substrate. Method500proceeds to operation504, as illustrated inFIG.5A, in which a sacrificial layer on the second substrate, the N-type doped semiconductor layer on the sacrificial layer, and a dielectric stack on the N-type doped semiconductor layer are subsequently formed. The second substrate can be a silicon substrate. It is understood that as the second substrate will be removed from the final product, the second substrate may be part of a dummy wafer, for example, a carrier substrate, made of any suitable materials, such as glass, sapphire, plastic, silicon, to name a few, to reduce the cost of the second substrate. In some embodiments, the substrate is a carrier substrate, the sacrificial layer includes a dielectric material, the N-type doped semiconductor layer includes polysilicon, and the dielectric stack includes interleaved stack dielectric layers and stack sacrificial layers. In some embodiments, the stack dielectric layers and stack sacrificial layers are alternatingly deposited on the N-type doped semiconductor layer to form the dielectric stack.

As illustrated inFIG.3A, a sacrificial layer304is formed on a carrier substrate302, and an N-type doped semiconductor layer306is formed on sacrificial layer304. N-type doped semiconductor layer306can include polysilicon doped with N-type dopant(s), such as P, As, or Sb. Sacrificial layer304can include any suitable sacrificial materials that can be later selectively removed and are different from the material of N-type doped semiconductor layer306. In some embodiments, sacrificial layer304includes a dielectric material, such as silicon oxide or silicon nitride. To form sacrificial layer304, silicon oxide or silicon nitride is deposited on carrier substrate302using one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, or any combination thereof, according to some embodiments. In some embodiments, to form N-type doped semiconductor layer306, polysilicon is deposited on sacrificial layer304using one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, or any combination thereof, followed by doping the deposited polysilicon with N-type dopant(s), such as P, As or Sb, using ion implantation and/or thermal diffusion. In some embodiments, to form N-type doped semiconductor layer306, in-situ doping of N-type dopants, such as P, As, or Sb, is performed when depositing polysilicon on sacrificial layer304.

As illustrated inFIG.3B, a dielectric stack308including a plurality pairs of a first dielectric layer (referred to herein as “stack sacrificial layer”312) and a second dielectric layer (referred to herein as “stack dielectric layers”310, together referred to herein as “dielectric layer pairs”) is formed on N-type doped semiconductor layer306. Dielectric stack308includes interleaved stack sacrificial layers312and stack dielectric layers310, according to some embodiments. Stack dielectric layers310and stack sacrificial layers312can be alternatively deposited on N-type doped semiconductor layer306above carrier substrate302to form dielectric stack308. In some embodiments, each stack dielectric layer310includes a layer of silicon oxide, and each stack sacrificial layer312includes a layer of silicon nitride. Dielectric stack308can be formed by one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, or any combination thereof. As illustrated inFIG.3B, a staircase structure can be formed on the edge of dielectric stack308. The staircase structure can be formed by performing a plurality of so-called “trim-etch” cycles to the dielectric layer pairs of dielectric stack308toward carrier substrate302. Due to the repeated trim-etch cycles applied to the dielectric layer pairs of dielectric stack308, dielectric stack308can have one or more tilted edges and a top dielectric layer pair shorter than the bottom one, as shown inFIG.3B.

Method500proceeds to operation506, as illustrated inFIG.5A, in which a channel structure extending vertically through the dielectric stack and the N-type doped semiconductor layer is formed. In some embodiments, to form the channel structure, a channel hole extending vertically through the dielectric stack and the N-type doped semiconductor layer, stopping at the sacrificial layer, is etched, and a memory film and a semiconductor channel are subsequently deposited along a sidewall of the channel hole.

As illustrated inFIG.3B, a channel hole is an opening extending vertically through dielectric stack308and N-type doped semiconductor layer306. In some embodiments, a plurality of openings are formed, such that each opening becomes the location for growing an individual channel structure314in the later process. In some embodiments, fabrication processes for forming the channel hole of channel structure314include wet etching and/or dry etching, such as deep RIE (DRIE). Sacrificial layer304can act as an etch stop layer to control the gouging variation among different channel holes. For example, the etching of channel holes may be stopped by sacrificial layer304without extending further into carrier substrate302. That is, the lower end of each channel hole (and corresponding channel structure314) is between the top surface and bottom surface of sacrificial layer304, according to some embodiments.

As illustrated inFIG.3B, a memory film including a blocking layer317, a storage layer316, and a tunneling layer315, and a semiconductor channel318are subsequently formed in this order along sidewalls and the bottom surface of the channel hole. In some embodiments, blocking layer317, storage layer316, and tunneling layer315are first deposited along the sidewalls and bottom surface of the channel hole in this order using one or more thin film deposition processes, such as ALD, CVD, PVD, any other suitable processes, or any combination thereof, to form the memory film. Semiconductor channel318then can be formed by depositing a semiconductor material, such as polysilicon (e.g., undoped polysilicon), over tunneling layer315using one or more thin film deposition processes, such as ALD, CVD, PVD, any other suitable processes, or any combination thereof. In some embodiments, a first silicon oxide layer, a silicon nitride layer, a second silicon oxide layer, and a polysilicon layer (a “SONO” structure) are subsequently deposited to form blocking layer317, storage layer316, and tunneling layer315of the memory film and semiconductor channel318.

As illustrated inFIG.3B, a capping layer is formed in the channel hole and over semiconductor channel318to completely or partially fill the channel hole (e.g., without or with an air gap). The capping layer can be formed by depositing a dielectric material, such as silicon oxide, using one or more thin film deposition processes, such as ALD, CVD, PVD, any other suitable processes, or any combination thereof. A channel plug then can be formed in the top portion of the channel hole. In some embodiments, parts of the memory film, semiconductor channel318, and the capping layer that are on the top surface of dielectric stack308are removed and planarized by CMP, wet etching, and/or dry etching. A recess then can be formed in the top portion of the channel hole by wet etching and/or drying etching parts of semiconductor channel318and the capping layer in the top portion of the channel hole. The channel plug then can be formed by depositing semiconductor materials, such as polysilicon, into the recess by one or more thin film deposition processes, such as CVD, PVD, ALD, or any combination thereof. Channel structure314is thereby formed through dielectric stack308and N-type doped semiconductor layer306. Depending on the depth at which the etching of each channel hole stops by sacrificial layer304, channel structure314may extend further into sacrificial layer304or stop at the interface between sacrificial layer304and N-type doped semiconductor layer306. Nevertheless, channel structure314may not extend further into carrier substrate302.

Method500proceeds to operation508, as illustrated inFIG.5A, in which the dielectric stack is replaced with a memory stack, for example, using the so-called “gate replacement” process, such that the channel structure extends vertically through the memory stack and the N-type doped semiconductor layer. In some embodiments, to replace the dielectric stack with the memory stack, an opening extending vertically through the dielectric stack, stopping at the N-type doped semiconductor layer, is etched, and the stack sacrificial layers are replaced with stack conductive layers through the opening to form the memory stack including interleaved the stack dielectric layers and the stack conductive layers.

As illustrated inFIG.3C, a slit320is an opening that extends vertically through dielectric stack308and stops at N-type doped semiconductor layer306. In some embodiments, fabrication processes for forming slit320include wet etching and/or dry etching, such as DRIE. A gate replacement then can be performed through slit320to replace dielectric stack308with a memory stack330(shown inFIG.3E).

As illustrated inFIG.3D, lateral recesses322are first formed by removing stack sacrificial layers312(shown inFIG.3C) through slit320. In some embodiments, stack sacrificial layers312are removed by applying etchants through slit320, creating lateral recesses322interleaved between stack dielectric layers310. The etchants can include any suitable etchants that etch stack sacrificial layers312selective to stack dielectric layers310.

As illustrated inFIG.3E, stack conductive layers328(including gate electrodes and adhesive layers) are deposited into lateral recesses322(shown inFIG.3D) through slit320. In some embodiments, a gate dielectric layer332is deposited into lateral recesses322prior to stack conductive layers328, such that stack conductive layers328are deposited on gate dielectric layer332. Stack conductive layers328, such as metal layers, can be deposited using one or more thin film deposition processes, such as ALD, CVD, PVD, any other suitable processes, or any combination thereof. In some embodiments, gate dielectric layer332, such as a high-k dielectric layer, is formed along the sidewall and at the bottom of slit320as well. Memory stack330including interleaved stack conductive layers328and stack dielectric layers310is thereby formed, replacing dielectric stack308(shown inFIG.3D), according to some embodiments.

Method500proceeds to operation510, as illustrated inFIG.5A, in which an insulating structure extending vertically through the memory stack is formed. In some embodiments, to form the insulating structure, after forming the memory stack, one or more dielectric materials are deposited into the opening to fill the opening. As illustrated inFIG.3E, an insulating structure336extending vertically through memory stack330is formed, stopping on the top surface of N-type doped semiconductor layer306. Insulating structure336can be formed by depositing one or more dielectric materials, such as silicon oxide, into slit320to fully or partially fill slit320(with or without an air gap) using one or more thin film deposition processes, such as ALD, CVD, PVD, any other suitable processes, or any combination thereof. In some embodiments, insulating structure336includes gate dielectric layer332(e.g., including high-k dielectrics) and a dielectric capping layer334(e.g., including silicon oxide).

As illustrated inFIG.3F, after the formation of insulating structure336, local contacts, including channel local contacts344and word line local contacts342, and peripheral contacts338and340are formed. A local dielectric layer can be formed on memory stack330by depositing dielectric materials, such as silicon oxide or silicon nitride, using one or more thin film deposition processes, such as CVD, PVD, ALD, or any combination thereof, on top of memory stack330. Channel local contacts344, word line local contacts342, and peripheral contacts338and340can be formed by etching contact openings through the local dielectric layer (and any other ILD layers) using wet etching and/or dry etching, e.g., RIE, followed by filling the contact openings with conductive materials using one or more thin film deposition processes, such as ALD, CVD, PVD, any other suitable processes, or any combination thereof.

As illustrated inFIG.3F, a bonding layer346is formed above channel local contacts344, word line local contacts342, and peripheral contacts338and340. Bonding layer346includes bonding contacts electrically connected to channel local contacts344, word line local contacts342, and peripheral contacts338and340. To form bonding layer346, an ILD layer is deposited using one or more thin film deposition processes, such as CVD, PVD, ALD, or any combination thereof, and the bonding contacts are formed through the ILD layer using wet etching and/or dry etching, e.g., RIE, followed by one or more thin film deposition processes, such as ALD, CVD, PVD, any other suitable processes, or any combination thereof.

Method500proceeds to operation512, as illustrated inFIG.5A, in which the first substrate and the second substrate are bonded in a face-to-face manner, such that the memory stack is above the peripheral circuit. The bonding can include hybrid bonding. As illustrated inFIG.3G, carrier substrate302and components formed thereon (e.g., memory stack330and channel structures314formed therethrough) are flipped upside down. Bonding layer346facing down is bonded with bonding layer348facing up, i.e., in a face-to-face manner, thereby forming a bonding interface354between carrier substrate302and silicon substrate350, according to some embodiments. In some embodiments, a treatment process, e.g., a plasma treatment, a wet treatment, and/or a thermal treatment, is applied to the bonding surfaces prior to the bonding. After the bonding, the bonding contacts in bonding layer346and the bonding contacts in bonding layer348are aligned and in contact with one another, such that memory stack330and channel structures314formed therethrough can be electrically connected to peripheral circuits352and are above peripheral circuits352.

Method500proceeds to operation514, as illustrated inFIG.5A, in which the second substrate and the sacrificial layer are removed to expose an end of the channel structure. The removal can be performed from the backside of the second substrate. As illustrated inFIG.3H, carrier substrate302and sacrificial layer304(shown inFIG.3G) are removed from the backside to expose an upper end of channel structure314. Carrier substrate302can be completely removed using CMP, grinding, dry etching, and/or wet etching. In some embodiments, carrier substrate302is peeled off. The removal of carrier substrate302can be stopped by sacrificial layer304underneath due to the different materials thereof to ensure thickness uniformity. In some embodiments in which carrier substrate302includes silicon and sacrificial layer304includes silicon oxide, carrier substrate302is removed using CMP, which can be automatically stopped at the interface between carrier substrate302and sacrificial layer304.

Sacrificial layer304then can be selectively removed as well using wet etching with suitable etchants, such as hydrofluoric acid, without etching N-type doped semiconductor layer306underneath. As described above, since channel structure314does not extend beyond sacrificial layer304into carrier substrate302, the removal of carrier substrate302does not affect channel structure314. The removal of sacrificial layer304can expose the upper end of channel structure314. In some embodiments in which channel structure314extends into sacrificial layer304, the selective etching of sacrificial layer304including silicon oxide also removes part of blocking layer317including silicon oxide above the top surface of N-type doped semiconductor layer306, but storage layer316including silicon nitride and other layers surrounded by storage layer316(e.g., tunneling layer315) remain intact.

Method500proceeds to operation516, as illustrated inFIG.5A, in which part of the channel structure abutting the N-type doped semiconductor layer is replaced with a semiconductor plug. In some embodiments, to replace the part of the channel structure abutting the N-type doped semiconductor layer with the semiconductor plug, part of the memory film abutting the N-type doped semiconductor layer is removed to form a recess surrounding part of the semiconductor channel, the part of the semiconductor channel is doped, and polysilicon is deposited into the recess to form the semiconductor plug surrounding and in contact with the part of the doped semiconductor channel.

As illustrated inFIG.3I, part of storage layer316(shown inFIG.3H) abutting N-type doped semiconductor layer306is removed. In some embodiments, storage layer316including silicon nitride is selectively removed using wet etching with suitable etchants, such as phosphoric acid, without etching N-type doped semiconductor layer306including polysilicon. The etching of storage layer316can be controlled by controlling the etching time and/or etching rate, such that the etching does not continue to affect the rest of storage layer316surrounded by memory stack330.

As illustrated inFIG.3J, parts of blocking layer317and tunneling layer315abutting N-type doped semiconductor layer306are removed to form a recess357surrounding the top portion of semiconductor channel318abutting N-type doped semiconductor layer306. In some embodiments, blocking layer317and tunneling layer315including silicon oxide are selectively removed using wet etching with suitable etchants, such as hydrofluoric acid, without etching N-type doped semiconductor layer306and semiconductor channel318including polysilicon. The etching of blocking layer317and tunneling layer315can be controlled by controlling the etching time and/or etching rate, such that the etching does not continue to affect the rest of blocking layer317and tunneling layer315surrounded by memory stack330. As a result, the top portion of the memory film (including blocking layer317, storage layer316, and tunneling layer315) of channel structure314abutting N-type doped semiconductor layer306is removed to form recess357, exposing the top portion of semiconductor channel318, according to some embodiments. In some embodiments, the top portion of semiconductor channel318exposed by recess357is doped to increase its conductivity. For example, a tilted ion implantation process may be performed to dope the top portion of semiconductor channel318(e.g., including polysilicon) exposed by recess357with any suitable dopants to a desired doping concentration.

As illustrated inFIG.3K, a semiconductor plug359is formed in recess357(shown inFIG.3J), surrounding and in contact with the doped top portion of semiconductor channel318. As a result, the top portion of channel structure314(shown inFIG.3H) abutting N-type doped semiconductor layer306is thereby replaced with semiconductor plug359, according to some embodiments. In some embodiments, to form semiconductor plug359, polysilicon is deposited into recess357using one or more thin film deposition processes, such as ALD, CVD, PVD, any other suitable processes, or any combination thereof to fill recess357, followed by a CMP process to remove any excess polysilicon above the top surface of N-type doped semiconductor layer306. In some embodiments, in-situ doping of N-type dopants, such as P, As, or Sb, is performed when depositing polysilicon into recess357to dope semiconductor plug359. As semiconductor plug359and N-type doped semiconductor layer306may include the same material, such as polysilicon, and have the same thickness (after the CMP process), semiconductor plug359may be viewed as part of N-type doped semiconductor layer306. Nevertheless, as semiconductor plug359is formed in a later process after the formation of the rest of N-type doped semiconductor layer306(e.g., shown inFIG.3A), regardless whether semiconductor plug359is in-situ doped, the doping concentration of semiconductor plug359is different from the doping concentration of the rest of N-type doped semiconductor layer306, according to some embodiments.

As described above, semiconductor plugs359in N-type doped semiconductor layer306can act as the sidewall SEGs of channel structures314. Different from known methods that form the sidewall SEGs by etching and deposition processes through slit320(e.g., shown inFIG.3D) extending all the way through dielectric stack308with high aspect ratio, semiconductor plugs359can be formed from the opposite side of dielectric stack308/memory stack330once carrier substrate302is removed, which is not affected by the level of dielectric stack308/memory stack330and the aspect ratio of slit320. By avoiding the issues introduced by the high aspect ratio of slit320, the fabrication complexity and cost can be reduced, and the yield can be increased. Moreover, the vertical scalability (e.g., the increasing level of dielectric stack308/memory stack330) can be improved as well.

Method500proceeds to operation518, as illustrated inFIG.5A, in which a source contact is formed above the memory stack and in contact with the N-type doped semiconductor layer. As illustrated inFIG.3L, one or more ILD layers356are formed on N-type doped semiconductor layer306. ILD layers356can be formed by depositing dielectric materials on the top surface of N-type doped semiconductor layer306using one or more thin film deposition processes, such as ALD, CVD, PVD, any other suitable processes, or any combination thereof. A source contact opening358can be formed through ILD layers356into N-type doped semiconductor layer306. In some embodiments, source contact opening358is formed using wet etching and/or dry etching, such as RIE. In some embodiments, source contact opening358extends further into the top portion of N-type doped semiconductor layer306. The etching process through ILD layers356may continue to etch part of N-type doped semiconductor layer306. In some embodiments, a separate etching process is used to etch part of N-type doped semiconductor layer306after etching through ILD layers356.

As illustrated inFIG.3M, a source contact364is formed in source contact opening358(shown inFIG.3L) at the backside of N-type doped semiconductor layer306. Source contact364is above memory stack330and in contact with N-type doped semiconductor layer306, according to some embodiments. In some embodiments, one or more conductive materials are deposited into source contact opening358using one or more thin film deposition processes, such as ALD, CVD, PVD, any other suitable processes, or any combination thereof, to fill source contact opening358with an adhesive layer (e.g., TiN) and a conductor layer (e.g., W). A planarization process, such as CMP, can then be performed to remove the excess conductive materials, such that the top surface of source contact364is flush with the top surface of ILD layers356.

Method500proceeds to operation520, as illustrated inFIG.5A, in which an interconnect layer is formed above and in contact with the source contact. In some embodiments, a contact is formed through the N-type doped semiconductor layer and in contact with the interconnect layer, such that the N-type doped semiconductor layer is electrically connected to the contact through the source contact and the interconnect layer.

As illustrated inFIG.3N, a redistribution layer370is formed above and in contact with source contact364. In some embodiments, redistribution layer370is formed by depositing a conductive material, such as Al, on the top surfaces of ILD layers356and source contact364using one or more thin film deposition processes, such as ALD, CVD, PVD, any other suitable processes, or any combination thereof. A passivation layer372can be formed on redistribution layer370. In some embodiments, passivation layer372is formed by depositing a dielectric material, such as silicon nitride, using one or more thin film deposition processes, such as ALD, CVD, PVD, any other suitable processes, or any combination thereof. An interconnect layer376including ILD layers356, redistribution layer370, and passivation layer372is thereby formed, according to some embodiments.

As illustrated inFIG.3L, contact openings360and361each extending through ILD layers356and N-type doped semiconductor layer306are formed. In some embodiments, contact openings360and361are formed using wet etching and/or dry etching, such as RIE, through ILD layers356and N-type doped semiconductor layer306. In some embodiments, contact openings360and361are patterned using lithography to be aligned with peripheral contacts338and340, respectively. The etching of contact openings360and361can stop at the upper ends of peripheral contacts338and340to expose peripheral contacts338and340. As illustrated inFIG.3L, a spacer362is formed along the sidewalls of contact openings360and361to electrically separate N-type doped semiconductor layer306using one or more thin film deposition processes, such as ALD, CVD, PVD, any other suitable processes, or any combination thereof. In some embodiments, the etching of source contact opening358is performed after the formation of spacer362, such that spacer362is not formed along the sidewall of source contact opening358to increase the contact area between source contact364and N-type doped semiconductor layer306.

As illustrated inFIG.3M, contacts366and368are formed in contact openings360and361, respectively (shown inFIG.3L) at the backside of N-type doped semiconductor layer306. Contacts366and368extend vertically through ILD layers356and N-type doped semiconductor layer306, according to some embodiments. Contacts366and368and source contact364can be formed using the same deposition process to reduce the number of deposition processes. In some embodiments, one or more conductive materials are deposited into contact openings360and361using one or more thin film deposition processes, such as ALD, CVD, PVD, any other suitable processes, or any combination thereof, to fill contact openings360and361with an adhesive layer (e.g., TiN) and a conductor layer (e.g., W). A planarization process, such as ClVIP, can then be performed to remove the excess conductive materials, such that the top surfaces of contacts366and368(and the top surface of source contact364) are flush with the top surface of ILD layers356. In some embodiments, as contact openings360and361are aligned with peripheral contacts338and340, respectively, contacts366and368are above and in contact with peripheral contacts338and340, respectively, as well.

As illustrated inFIG.3N, redistribution layer370is also formed above and in contact with contact366. As a result, N-type doped semiconductor layer306can be electrically connected to peripheral contact338through source contact364, redistribution layer370of interconnect layer376, and contact366. In some embodiments, N-type doped semiconductor layer306is electrically connected to peripheral circuits352through source contact364, interconnect layer376, contact366, peripheral contact338, and bonding layers346and348.

As illustrated inFIG.3N, a contact pad374is formed above and in contact with contact368. In some embodiments, part of passivation layer372covering contact368is removed by wet etching and/or dry etching to expose part of redistribution layer370underneath to form contact pad374. As a result, contact pad374for pad-out can be electrically connected to peripheral circuits352through contact368, peripheral contact340, and bonding layers346and348.

It is understood that the second substrate, sacrificial layer, and N-type doped semiconductor layer described above in method500may be replaced by an SOI wafer, which includes a handling layer, a buried oxide layer (also known as a “BOX” layer), and a device layer as described below with respect to method501. The detail of similar operations between methods500and501may not be repeated for ease of description. Referring toFIG.5B, method501starts at operation502, in which a peripheral circuit is formed on a first substrate. The first substrate can be a silicon substrate.

Method501proceeds to operation503, as illustrated inFIG.5B, in which a device layer of an SOI wafer is doped with an N-type dopant. The SOI wafer can include a handling layer, a buried oxide layer, and a device layer. In some embodiments, the buried oxide layer includes silicon oxide, and the device layer includes single crystalline silicon. As illustrated inFIG.3A, an SOI wafer301includes a handling layer302(corresponding to carrier substrate302above in describing method500), a buried oxide layer304(corresponding to sacrificial layer304), and a device layer306(corresponding to N-type doped semiconductor layer306). Device layer306can be doped with N-type dopant(s), such as P, As, or Sb, using ion implantation and/or thermal diffusion to become an N-type doped device layer306. It is understood that the above descriptions related to carrier substrate302, sacrificial layer304, and N-type doped semiconductor layer306can be similarly applied to handling layer302, buried oxide layer304, and doped device layer306of SOI wafer301, respectively, to better understand method501below and thus, are not repeated for ease of description.

Method501proceeds to operation505, as illustrated inFIG.5B, in which a dielectric stack is formed on the doped device layer of the SOI wafer. The dielectric stack can include interleaved stack dielectric layers and stack sacrificial layers. Method501proceeds to operation507, as illustrated inFIG.5B, in which a channel structure extending vertically through the dielectric stack and the doped device layer is formed. In some embodiments, to form the channel structure, a channel hole extending vertically through the dielectric stack and the doped device layer, stopping at the buried oxide layer, is formed, and a memory film and a semiconductor channel are subsequently deposited along a sidewall of the channel hole. Method501proceeds to operation508, as illustrated inFIG.5B, in which the dielectric stack is replaced with a memory stack, such that the channel structure extends vertically through the memory stack and the doped device layer. In some embodiments, to replace the dielectric stack with the memory stack, an opening extending vertically through the dielectric stack is etched, stopping at the doped device layer, and the stack sacrificial layers are replaced with stack conductive layers through the opening to form the memory stack including interleaved the stack dielectric layers and the stack conductive layers. Method501proceeds to operation510, as illustrated inFIG.5B, in which an insulating structure extending vertically through the memory stack is formed. In some embodiments, to form the insulating structure, after forming the memory stack, one or more dielectric materials are deposited into the opening to fill the opening.

Method501proceeds to operation513, as illustrated inFIG.5B, in which the first substrate and the SOI wafer are bonded in a face-to-face manner, such that the memory stack is above the peripheral circuit. The bonding can include hybrid bonding. Method501proceeds to operation515, as illustrated inFIG.5B, in which the handle layer and the buried oxide layer of the SOI wafer are removed to expose an end of the channel structure. Method501proceeds to operation517, as illustrated inFIG.5B, in which part of the channel structure abutting the doped device layer is replaced with a semiconductor plug. In some embodiments, to replace the part of the channel structure abutting the doped device layer with the semiconductor plug, part of the memory film abutting the doped device layer is etched to form a recess surrounding part of the semiconductor channel, the part of the semiconductor channel is doped, and polysilicon is deposited into the recess to form the semiconductor plug surrounding and in contact with the part of the doped semiconductor channel.

Method501proceeds to operation519, as illustrated inFIG.5B, in which a source contact above the memory stack and in contact with the doped device layer is formed. Method501proceeds to operation520, as illustrated inFIG.5B, in which an interconnect layer above and in contact with the source contact is formed. In some embodiments, a contact is formed through the doped device layer and in contact with the interconnect layer, such that the doped device layer is electrically connected to the contact through the source contact and the interconnect layer.

FIGS.4A-4Oillustrate a fabrication process for forming another exemplary 3D memory device, according to some embodiments of the present disclosure.FIG.6Aillustrates a flowchart of a method600for forming another exemplary 3D memory device, according to some embodiments of the present disclosure.FIG.6Billustrates a flowchart of another method601for forming another exemplary 3D memory device, according to some embodiments of the present disclosure. Examples of the 3D memory device depicted inFIGS.4A-4O,6A, and6Binclude 3D memory device200depicted inFIG.2.FIGS.4A-4O,6A, and6Bwill be described together. It is understood that the operations shown in methods600and601are not exhaustive and that other operations can be performed as well before, after, or between any of the illustrated operations. Further, some of the operations may be performed simultaneously, or in a different order than shown inFIGS.6A and6B.

Referring toFIG.6A, method600starts at operation602, in which a peripheral circuit is formed on a first substrate. The first substrate can be a silicon substrate. As illustrated inFIG.4G, a plurality of transistors are formed on a silicon substrate450using a plurality of processes including, but not limited to, photolithography, etching, thin film deposition, thermal growth, implantation, CMP, and any other suitable processes. In some embodiments, doped regions (not shown) are formed in silicon substrate450by ion implantation and/or thermal diffusion, which function, for example, as source regions and/or drain regions of the transistors. In some embodiments, isolation regions (e.g., STIs) are also formed in silicon substrate450by wet etching and/or dry etching and thin film deposition. The transistors can form peripheral circuits452on silicon substrate450.

As illustrated inFIG.4G, a bonding layer448is formed above peripheral circuits452. Bonding layer448includes bonding contacts electrically connected to peripheral circuits452. To form bonding layer448, an ILD layer is deposited using one or more thin film deposition processes, such as CVD, PVD, ALD, or any combination thereof; the bonding contacts through the ILD layer are formed using wet etching and/or dry etching, e.g., RIE, followed by one or more thin film deposition processes, such as ALD, CVD, PVD, any other suitable processes, or any combination thereof.

A channel structure extending vertically through a memory stack and a P-type doped semiconductor layer having an N-well can be formed above a second substrate. Method600proceeds to operation604, as illustrated inFIG.6A, in which a sacrificial layer on the second substrate, the P-type doped semiconductor layer having the N-well on the sacrificial layer, and a dielectric stack on the P-type doped semiconductor layer are subsequently formed. The second substrate can be a silicon substrate. It is understood that as the second substrate will be removed from the final product, the second substrate may be part of a dummy wafer, for example, a carrier substrate, made of any suitable materials, such as glass, sapphire, plastic, silicon, to name a few, to reduce the cost of the second substrate. In some embodiments, the substrate is a carrier substrate, the sacrificial layer includes a dielectric material, the P-type doped semiconductor layer includes polysilicon, and the dielectric stack includes interleaved stack dielectric layers and stack sacrificial layers. In some embodiments, the stack dielectric layers and stack sacrificial layers are alternatingly deposited on the P-type doped semiconductor layer to form the dielectric stack. In some embodiments, prior to forming the dielectric stack, part of the P-type doped semiconductor layer is doped with an N-type dopant to form the N-well.

As illustrated inFIG.4A, a sacrificial layer404is formed on a carrier substrate402, and a P-type doped semiconductor layer406is formed on sacrificial layer404. P-type doped semiconductor layer406can include polysilicon doped with P-type dopant(s), such as B, Ga, or Al. Sacrificial layer404can include any suitable sacrificial materials that can be later selectively removed and are different from the material of P-type doped semiconductor layer406. In some embodiments, sacrificial layer404includes a dielectric material, such as silicon oxide or silicon nitride. To form sacrificial layer404, silicon oxide or silicon nitride is deposited on carrier substrate402using one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, or any combination thereof, according to some embodiments. In some embodiments, to form P-type doped semiconductor layer406, polysilicon is deposited on sacrificial layer404using one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, or any combination thereof, followed by doping the deposited polysilicon with P-type dopant(s), such as B, Ga, or Al, using ion implantation and/or thermal diffusion. In some embodiments, to form P-type doped semiconductor layer406, in-situ doping of P-type dopants, such as B, Ga, or Al, is performed when depositing polysilicon on sacrificial layer404.

As illustrated inFIG.4A, part of P-type doped semiconductor layer406is doped with N-type dopant(s), such as P, As, or Sb, to form an N-well407in P-type doped semiconductor layer406. In some embodiments, N-well407is formed using ion implantation and/or thermal diffusion. The ion implantation and/or thermal diffusion processes can be controlled to control the thickness of N-well407, either through the entire thickness of P-type doped semiconductor layer406or part thereof.

As illustrated inFIG.4B, a dielectric stack408including a plurality pairs of a first dielectric layer (referred to herein as “stack sacrificial layer”412) and a second dielectric layer (referred to herein as “stack dielectric layers”410, together referred to herein as “dielectric layer pairs”) is formed on P-type doped semiconductor layer406. Dielectric stack408includes interleaved stack sacrificial layers412and stack dielectric layers410, according to some embodiments. Stack dielectric layers410and stack sacrificial layers412can be alternatively deposited on P-type doped semiconductor layer406above carrier substrate402to form dielectric stack408. In some embodiments, each stack dielectric layer410includes a layer of silicon oxide, and each stack sacrificial layer412includes a layer of silicon nitride. Dielectric stack408can be formed by one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, or any combination thereof. As illustrated inFIG.4B, a staircase structure can be formed on the edge of dielectric stack408. The staircase structure can be formed by performing a plurality of so-called “trim-etch” cycles to the dielectric layer pairs of dielectric stack408toward carrier substrate402. Due to the repeated trim-etch cycles applied to the dielectric layer pairs of dielectric stack408, dielectric stack408can have one or more tilted edges and a top dielectric layer pair shorter than the bottom one, as shown inFIG.4B.

Method600proceeds to operation606, as illustrated inFIG.6A, in which a channel structure extending vertically through the dielectric stack and the P-type doped semiconductor layer is formed. In some embodiments, to form the channel structure, a channel hole extending vertically through the dielectric stack and the P-type doped semiconductor layer, stopping at the sacrificial layer, is etched, and a memory film and a semiconductor channel are subsequently deposited along a sidewall of the channel hole.

As illustrated inFIG.4B, a channel hole is an opening extending vertically through dielectric stack408and P-type doped semiconductor layer406. In some embodiments, a plurality of openings are formed, such that each opening becomes the location for growing an individual channel structure414in the later process. In some embodiments, fabrication processes for forming the channel hole of channel structure414include wet etching and/or dry etching, such as DRIE. Sacrificial layer404can act as an etch stop layer to control the gouging variation among different channel holes. For example, the etching of channel holes may be stopped by sacrificial layer404without extending further into carrier substrate402. That is, the lower end of each channel hole (and corresponding channel structure414) is between the top surface and bottom surface of sacrificial layer404, according to some embodiments.

As illustrated inFIG.4B, a memory film including a blocking layer417, a storage layer416, and a tunneling layer415, and a semiconductor channel418are subsequently formed in this order along sidewalls and the bottom surface of the channel hole. In some embodiments, blocking layer417, storage layer416, and tunneling layer415are first deposited along the sidewalls and bottom surface of the channel hole in this order using one or more thin film deposition processes, such as ALD, CVD, PVD, any other suitable processes, or any combination thereof, to form the memory film. Semiconductor channel418then can be formed by depositing a semiconductor material, such as polysilicon (e.g., undoped polysilicon), over tunneling layer415using one or more thin film deposition processes, such as ALD, CVD, PVD, any other suitable processes, or any combination thereof. In some embodiments, a first silicon oxide layer, a silicon nitride layer, a second silicon oxide layer, and a polysilicon layer (a “SONO” structure) are subsequently deposited to form blocking layer417, storage layer416, and tunneling layer415of the memory film and semiconductor channel418.

As illustrated inFIG.4B, a capping layer is formed in the channel hole and over semiconductor channel418to completely or partially fill the channel hole (e.g., without or with an air gap). The capping layer can be formed by depositing a dielectric material, such as silicon oxide, using one or more thin film deposition processes, such as ALD, CVD, PVD, any other suitable processes, or any combination thereof. A channel plug then can be formed in the top portion of the channel hole. In some embodiments, parts of the memory film, semiconductor channel418, and the capping layer that are on the top surface of dielectric stack408are removed and planarized by CMP, wet etching, and/or dry etching. A recess then can be formed in the top portion of the channel hole by wet etching and/or drying etching parts of semiconductor channel418and the capping layer in the top portion of the channel hole. The channel plug then can be formed by depositing semiconductor materials, such as polysilicon, into the recess by one or more thin film deposition processes, such as CVD, PVD, ALD, or any combination thereof. Channel structure414is thereby formed through dielectric stack408and P-type doped semiconductor layer406. Depending on the depth at which the etching of each channel hole stops by sacrificial layer404, channel structure414may extend further into sacrificial layer404or stop at the interface between sacrificial layer404and P-type doped semiconductor layer406. Nevertheless, channel structure414may not extend further into carrier substrate402.

Method600proceeds to operation608, as illustrated inFIG.6A, in which the dielectric stack is replaced with a memory stack, for example, using the so-called “gate replacement” process, such that the channel structure extends vertically through the memory stack and the P-type doped semiconductor layer. In some embodiments, to replace the dielectric stack with the memory stack, an opening extending vertically through the dielectric stack, stopping at the P-type doped semiconductor layer, is etched, and the stack sacrificial layers are replaced with stack conductive layers through the opening to form the memory stack including interleaved the stack dielectric layers and the stack conductive layers.

As illustrated inFIG.4C, a slit420is an opening that extends vertically through dielectric stack408and stops at P-type doped semiconductor layer406. In some embodiments, fabrication processes for forming slit420include wet etching and/or dry etching, such as DRIE. Although slit420is laterally aligned with N-well407as shown inFIG.4C, it is understood that slit420may not be laterally aligned with N-well407in other examples. A gate replacement then can be performed through slit420to replace dielectric stack408with a memory stack430(shown inFIG.4E).

As illustrated inFIG.4D, lateral recesses422are first formed by removing stack sacrificial layers412(shown inFIG.4C) through slit420. In some embodiments, stack sacrificial layers412are removed by applying etchants through slit420, creating lateral recesses422interleaved between stack dielectric layers410. The etchants can include any suitable etchants that etch stack sacrificial layers412selective to stack dielectric layers410.

As illustrated inFIG.4E, stack conductive layers428(including gate electrodes and adhesive layers) are deposited into lateral recesses422(shown inFIG.4D) through slit420. In some embodiments, a gate dielectric layer432is deposited into lateral recesses422prior to stack conductive layers428, such that stack conductive layers428are deposited on gate dielectric layer432. Stack conductive layers428, such as metal layers, can be deposited using one or more thin film deposition processes, such as ALD, CVD, PVD, any other suitable processes, or any combination thereof. In some embodiments, gate dielectric layer432, such as a high-k dielectric layer, is formed along the sidewall and at the bottom of slit420as well. Memory stack430including interleaved stack conductive layers428and stack dielectric layers410is thereby formed, replacing dielectric stack408(shown inFIG.4D), according to some embodiments.

Method600proceeds to operation610, as illustrated inFIG.6A, in which an insulating structure extending vertically through the memory stack is formed. In some embodiments, to form the insulating structure, after forming the memory stack, one or more dielectric materials are deposited into the opening to fill the opening. As illustrated inFIG.4E, an insulating structure436extending vertically through memory stack430is formed, stopping on the top surface of P-type doped semiconductor layer406. Insulating structure436can be formed by depositing one or more dielectric materials, such as silicon oxide, into slit420to fully or partially fill slit420(with or without an air gap) using one or more thin film deposition processes, such as ALD, CVD, PVD, any other suitable processes, or any combination thereof. In some embodiments, insulating structure436includes gate dielectric layer432(e.g., including high-k dielectrics) and a dielectric capping layer434(e.g., including silicon oxide).

As illustrated inFIG.4F, after the formation of insulating structure436, local contacts, including channel local contacts444and word line local contacts442, and peripheral contacts438,439, and440are formed. A local dielectric layer can be formed on memory stack430by depositing dielectric materials, such as silicon oxide or silicon nitride, using one or more thin film deposition processes, such as CVD, PVD, ALD, or any combination thereof, on top of memory stack430. Channel local contacts444, word line local contacts442, and peripheral contacts438,439, and440can be formed by etching contact openings through the local dielectric layer (and any other ILD layers) using wet etching and/or dry etching, e.g., RIE, followed by filling the contact openings with conductive materials using one or more thin film deposition processes, such as ALD, CVD, PVD, any other suitable processes, or any combination thereof.

As illustrated inFIG.4F, a bonding layer446is formed above channel local contacts444, word line local contacts442, and peripheral contacts438,439, and440. Bonding layer446includes bonding contacts electrically connected to channel local contacts444, word line local contacts442, and peripheral contacts438,439, and440. To form bonding layer446, an ILD layer is deposited using one or more thin film deposition processes, such as CVD, PVD, ALD, or any combination thereof, and the bonding contacts are formed through the ILD layer using wet etching and/or dry etching, e.g., RIE, followed by one or more thin film deposition processes, such as ALD, CVD, PVD, any other suitable processes, or any combination thereof.

Method600proceeds to operation612, as illustrated inFIG.6A, in which the first substrate and the second substrate are bonded in a face-to-face manner, such that the memory stack is above the peripheral circuit. The bonding can include hybrid bonding. As illustrated inFIG.4G, carrier substrate402and components formed thereon (e.g., memory stack430and channel structures414formed therethrough) are flipped upside down. Bonding layer446facing down is bonded with bonding layer448facing up, i.e., in a face-to-face manner, thereby forming a bonding interface454between carrier substrate402and silicon substrate450, according to some embodiments. In some embodiments, a treatment process, e.g., a plasma treatment, a wet treatment, and/or a thermal treatment, is applied to the bonding surfaces prior to the bonding. After the bonding, the bonding contacts in bonding layer446and the bonding contacts in bonding layer448are aligned and in contact with one another, such that memory stack430and channel structures414formed therethrough can be electrically connected to peripheral circuits452and are above peripheral circuits452.

Method600proceeds to operation614, as illustrated inFIG.6A, in which the second substrate and the sacrificial layer are removed to expose an end of the channel structure. The removal can be performed from the backside of the second substrate. As illustrated inFIG.4H, carrier substrate402and sacrificial layer404(shown inFIG.4G) are removed from the backside to expose an upper end of channel structure414. Carrier substrate402can be completely removed using CMP, grinding, dry etching, and/or wet etching. In some embodiments, carrier substrate402is peeled off. The removal of carrier substrate402can be stopped by sacrificial layer404underneath due to the different materials thereof to ensure thickness uniformity. In some embodiments in which carrier substrate402includes silicon and sacrificial layer304includes silicon oxide, carrier substrate402is removed using CMP, which can be automatically stopped at the interface between carrier substrate402and sacrificial layer404.

Sacrificial layer404then can be selectively removed as well using wet etching with suitable etchants, such as hydrofluoric acid, without etching P-type doped semiconductor layer406underneath. As described above, since channel structure414does not extend beyond sacrificial layer404into carrier substrate402, the removal of carrier substrate402does not affect channel structure414. The removal of sacrificial layer404can expose the upper end of channel structure414. In some embodiments in which channel structure414extends into sacrificial layer404, the selective etching of sacrificial layer404including silicon oxide also removes part of blocking layer417including silicon oxide above the top surface of P-type doped semiconductor layer406, but storage layer416including silicon nitride and other layers surrounded by storage layer416(e.g., tunneling layer415) remain intact.

Method600proceeds to operation616, as illustrated inFIG.6A, in which part of the channel structure abutting the P-type doped semiconductor layer is replaced with a semiconductor plug. In some embodiments, to replace the part of the channel structure abutting the P-type doped semiconductor layer with the semiconductor plug, part of the memory film abutting the P-type doped semiconductor layer is removed to form a recess surrounding part of the semiconductor channel, the part of the semiconductor channel is doped, and polysilicon is deposited into the recess to form the semiconductor plug surrounding and in contact with the part of the doped semiconductor channel.

As illustrated inFIG.4I, part of storage layer416(shown inFIG.4H) abutting P-type doped semiconductor layer406is removed. In some embodiments, storage layer416including silicon nitride is selectively removed using wet etching with suitable etchants, such as phosphoric acid, without etching P-type doped semiconductor layer406including polysilicon. The etching of storage layer416can be controlled by controlling the etching time and/or etching rate, such that the etching does not continue to affect the rest of storage layer416surrounded by memory stack430.

As illustrated inFIG.4J, parts of blocking layer417and tunneling layer415abutting P-type doped semiconductor layer406are removed to form a recess457surrounding the top portion of semiconductor channel418abutting P-type doped semiconductor layer406. In some embodiments, blocking layer417and tunneling layer415including silicon oxide are selectively removed using wet etching with suitable etchants, such as hydrofluoric acid, without etching P-type doped semiconductor layer406and semiconductor channel418including polysilicon. The etching of blocking layer417and tunneling layer415can be controlled by controlling the etching time and/or etching rate, such that the etching does not continue to affect the rest of blocking layer417and tunneling layer415surrounded by memory stack430. As a result, the top portion of the memory film (including blocking layer417, storage layer416, and tunneling layer415) of channel structure414abutting P-type doped semiconductor layer406is removed to form recess457, exposing the top portion of semiconductor channel418, according to some embodiments. In some embodiments, the top portion of semiconductor channel418exposed by recess457is doped to increase its conductivity. For example, a tilted ion implantation process may be performed to dope the top portion of semiconductor channel418(e.g., including polysilicon) exposed by recess457with any suitable dopants to a desired doping concentration.

As illustrated inFIG.4K, a semiconductor plug459is formed in recess457(shown inFIG.4J), surrounding and in contact with the doped top portion of semiconductor channel418. As a result, the top portion of channel structure414(shown inFIG.4H) abutting P-type doped semiconductor layer406is thereby replaced with semiconductor plug459, according to some embodiments. In some embodiments, to form semiconductor plug459, polysilicon is deposited into recess457using one or more thin film deposition processes, such as ALD, CVD, PVD, any other suitable processes, or any combination thereof to fill recess457, followed by a CMP process to remove excess polysilicon above the top surface of P-type doped semiconductor layer406. In some embodiments, in-situ doping of P-type dopants, such as B, Ga, or Al, is performed when depositing polysilicon into recess457to dope semiconductor plug459. As semiconductor plug459and P-type doped semiconductor layer406may include the same material, such as polysilicon, and have the same thickness (after the CMP process), semiconductor plug459may be viewed as part of P-type doped semiconductor layer406. Nevertheless, as semiconductor plug459is formed in a later process after the formation of the rest of P-type doped semiconductor layer406(e.g., shown inFIG.4A), regardless whether semiconductor plug459is in-situ doped, the doping concentration of semiconductor plug459is different from the doping concentration of the rest of P-type doped semiconductor layer406, according to some embodiments.

As described above, semiconductor plugs459in P-type doped semiconductor layer406can act as the sidewall SEGs of channel structures414. Different from known methods that form the sidewall SEGs by etching and deposition processes through slit420(e.g., shown inFIG.4D) extending all the way through dielectric stack408with high aspect ratio, semiconductor plugs459can be formed from the opposite side of dielectric stack408/memory stack430once carrier substrate402is removed, which is not affected by the level of dielectric stack408/memory stack430and the aspect ratio of slit420. By avoiding the issues introduced by the high aspect ratio of slit420, the fabrication complexity and cost can be reduced, and the yield can be increased. Moreover, the vertical scalability (e.g., the increasing level of dielectric stack408/memory stack430) can be improved as well.

Method600proceeds to operation618, as illustrated inFIG.6A, in which a first source contact is formed above the memory stack and in contact with the P-type doped semiconductor layer, and a second source contact is formed above the memory stack and in contact with the N-well. As illustrated inFIG.4L, one or more ILD layers456are formed on P-type doped semiconductor layer406. ILD layers456can be formed by depositing dielectric materials on the top surface of P-type doped semiconductor layer406using one or more thin film deposition processes, such as ALD, CVD, PVD, any other suitable processes, or any combination thereof.

As illustrated inFIG.4M, a source contact opening458can be formed through ILD layers456into P-type doped semiconductor layer406. In some embodiments, source contact opening458is formed using wet etching and/or dry etching, such as RIE. In some embodiments, source contact opening458extends further into the top portion of P-type doped semiconductor layer406. The etching process through ILD layers456may continue to etch part of P-type doped semiconductor layer406. In some embodiments, a separate etching process is used to etch part of P-type doped semiconductor layer406after etching through ILD layers456.

As illustrated inFIG.4M, a source contact opening465can be formed through ILD layers456into N-well407. In some embodiments, source contact opening465is formed using wet etching and/or dry etching, such as RIE. In some embodiments, source contact opening465extends further into the top portion of N-well407. The etching process through ILD layers456may continue to etch part of N-well407. In some embodiments, a separate etching process is used to etch part of N-well407after etching through ILD layers456. The etching of source contact opening458can be performed after the etching of source contact opening465or vice versa. It is understood that in some examples, source contact openings458and465may be etched by the same etching process to reduce the number of etching processes.

As illustrated inFIG.4N, source contacts464and478are formed in source contact openings458and465, respectively, (shown inFIG.4M) at the backside of P-type doped semiconductor layer406. Source contact464is above memory stack430and in contact with P-type doped semiconductor layer406, according to some embodiments. Source contact478is above memory stack430and in contact with N-well407, according to some embodiments. In some embodiments, one or more conductive materials are deposited into source contact openings458and465using one or more thin film deposition processes, such as ALD, CVD, PVD, any other suitable processes, or any combination thereof, to fill source contact openings458and465with adhesive layers (e.g., TiN) and conductor layers (e.g., W). A planarization process, such as CMP, can then be performed to remove the excess conductive materials, such that the top surfaces of source contacts464and478are flush with one another as well as flush with the top surface of ILD layers456. It is understood that in some examples, source contacts464and478may be formed by the same deposition and CMP processes to reduce the number of fabrication processes.

Method600proceeds to operation620, as illustrated inFIG.6A, in which an interconnect layer is formed above and in contact with the first and second source contacts. In some embodiments, the interconnect layer includes a first interconnect and a second interconnect above and in contact with the first and second source contacts, respectively.

As illustrated inFIG.4O, a redistribution layer470is formed above and in contact with source contacts464and478. In some embodiments, redistribution layer470is formed by depositing a conductive material, such as Al, on the top surfaces of ILD layers456and source contact364using one or more thin film deposition processes, such as ALD, CVD, PVD, any other suitable processes, or any combination thereof. In some embodiments, redistribution layer470is patterned by lithography and etching processes to form a first interconnect470-1above and in contact with source contact464and a second interconnect470-2above and in contact with source contact478. First and second interconnects470-1and470-2can be electrically separated from one another. A passivation layer472can be formed on redistribution layer470. In some embodiments, passivation layer472is formed by depositing a dielectric material, such as silicon nitride, using one or more thin film deposition processes, such as ALD, CVD, PVD, any other suitable processes, or any combination thereof. An interconnect layer476including ILD layers456, redistribution layer470, and passivation layer472is thereby formed, according to some embodiments.

As illustrated inFIG.4L, contact openings460,461, and463each extending through ILD layers456and P-type doped semiconductor layer406are formed. In some embodiments, contact openings460,461, and463are formed using wet etching and/or dry etching, such as RIE, through ILD layers456and P-type doped semiconductor layer406. In some embodiments, contact openings460,461, and463are patterned using lithography to be aligned with peripheral contacts438,440, and439, respectively. The etching of contact openings460,461, and463can stop at the upper ends of peripheral contacts438,439, and440to expose peripheral contacts438,439, and440. The etching of contact openings460,461, and463can be performed by the same etching process to reduce the number of etching processes. It is understood that due to the different etching depths, the etching of contact openings460,461, and463may be performed prior to the etching of source contact opening465, or vice versa, but not at the same time.

As illustrated inFIG.4M, a spacer462is formed along the sidewalls of contact openings460,461, and463as well as source contact opening465to electrically separate P-type doped semiconductor layer406using one or more thin film deposition processes, such as ALD, CVD, PVD, any other suitable processes, or any combination thereof. In some embodiments, spacers462are formed along the sidewalls of contact openings460,461, and463as well as source contact opening465by the same deposition process to reduce the number of fabrication processes. In some embodiments, the etching of source contact opening458is performed after the formation of spacer362, such that spacer362is not formed along the sidewall of source contact opening358to increase the contact area between source contact364and N-type doped semiconductor layer306.

As illustrated inFIG.4N, contacts466,468, and469are formed in contact openings460,461, and463, respectively (shown inFIG.4M) at the backside of P-type doped semiconductor layer406. Contacts466,468, and469extend vertically through ILD layers456and P-type doped semiconductor layer406, according to some embodiments. Contacts466,468, and469as well as source contacts464and478can be formed using the same deposition process to reduce the number of deposition processes. In some embodiments, one or more conductive materials are deposited into contact openings460,461, and463using one or more thin film deposition processes, such as ALD, CVD, PVD, any other suitable processes, or any combination thereof, to fill contact openings460,461, and463with an adhesive layer (e.g., TiN) and a conductor layer (e.g., W). A planarization process, such as CMP, can then be performed to remove the excess conductive materials, such that the top surfaces of contacts466,468, and469(and the top surfaces of source contact464and478) are flush with the top surface of ILD layers456. In some embodiments, as contact openings460,461, and463are aligned with peripheral contacts438,440, and439, respectively, contacts466,468, and469are above and in contact with peripheral contacts438,440, and439, respectively, as well.

As illustrated inFIG.4O, first interconnect470-1of redistribution layer470is formed above and in contact with contact466. As a result, P-type doped semiconductor layer406can be electrically connected to peripheral contact438through source contact464, first interconnect470-1of interconnect layer476, and contact466. In some embodiments, P-type doped semiconductor layer406is electrically connected to peripheral circuits452through source contact464, first interconnect470-1of interconnect layer476, contact466, peripheral contact438, and bonding layers446and448. Similarly, second interconnect470-2of redistribution layer470is formed above and in contact with contact469. As a result, N-well407can be electrically connected to peripheral contact438through source contact478, second interconnect470-2of interconnect layer476, and contact469. In some embodiments, N-well407is electrically connected to peripheral circuits452through source contact478, second interconnect470-2of interconnect layer476, contact469, peripheral contact439, and bonding layers446and448.

As illustrated inFIG.4O, a contact pad474is formed above and in contact with contact468. In some embodiments, part of passivation layer472covering contact468is removed by wet etching and/or dry etching to expose part of redistribution layer470underneath to form contact pad474. As a result, contact pad474for pad-out can be electrically connected to peripheral circuits452through contact468, peripheral contact440, and bonding layers446and448.

It is understood that the second substrate, sacrificial layer, and P-type doped semiconductor layer described above in method600may be replaced by an SOI wafer, which includes a handling layer, a buried oxide layer (also known as a “BOX” layer), and a device layer as described below with respect to method601. The detail of similar operations between methods600and601may not be repeated for ease of description. Referring toFIG.6B, method601starts at operation602, in which a peripheral circuit is formed on a first substrate. The first substrate can be a silicon substrate.

Method601proceeds to operation603, as illustrated inFIG.6B, in which a device layer of an SOI wafer is doped with a P-type dopant. The SOI wafer can include a handling layer, a buried oxide layer, and a device layer. In some embodiments, the buried oxide layer includes silicon oxide, and the device layer includes single crystalline silicon. Method601proceeds to operation605, as illustrated inFIG.6B, in which part of the doped device layer is doped with an N-type dopant to form an N-well in the doped device layer.

As illustrated inFIG.4A, an SOI wafer401includes a handling layer402(corresponding to carrier substrate402above in describing method600), a buried oxide layer404(corresponding to sacrificial layer404), and a device layer406(corresponding to P-type doped semiconductor layer406). Device layer406can be doped with P-type dopant(s), such as P, As, or Sb, using ion implantation and/or thermal diffusion to become a P-type doped device layer406. Part of doped device layer406can be further doped with N-type dopant(s), such as B, Ga, or Al, using ion implantation and/or thermal diffusion to form N-well407. It is understood that the above descriptions related to carrier substrate402, sacrificial layer404, and P-type doped semiconductor layer406can be similarly applied to handling layer402, buried oxide layer404, and doped device layer406of SOI wafer401, respectively, to better understand method601below and thus, are not repeated for ease of description.

Method601proceeds to operation607, as illustrated inFIG.6B, in which a dielectric stack is formed on the doped device layer of the SOI wafer. The dielectric stack can include interleaved stack dielectric layers and stack sacrificial layers. Method601proceeds to operation609, as illustrated inFIG.6B, in which a channel structure extending vertically through the dielectric stack and the doped device layer is formed. In some embodiments, to form the channel structure, a channel hole extending vertically through the dielectric stack and the doped device layer, stopping at the buried oxide layer, is formed, and a memory film and a semiconductor channel are subsequently deposited along a sidewall of the channel hole. Method601proceeds to operation608, as illustrated inFIG.6B, in which the dielectric stack is replaced with a memory stack, such that the channel structure extends vertically through the memory stack and the doped device layer. In some embodiments, to replace the dielectric stack with the memory stack, an opening extending vertically through the dielectric stack is etched, stopping at the doped device layer, and the stack sacrificial layers are replaced with stack conductive layers through the opening to form the memory stack including interleaved the stack dielectric layers and the stack conductive layers. Method601proceeds to operation610, as illustrated inFIG.6B, in which an insulating structure extending vertically through the memory stack is formed. In some embodiments, to form the insulating structure, after forming the memory stack, one or more dielectric materials are deposited into the opening to fill the opening.

Method601proceeds to operation613, as illustrated inFIG.6B, in which the first substrate and the SOI wafer are bonded in a face-to-face manner, such that the memory stack is above the peripheral circuit. The bonding can include hybrid bonding. Method601proceeds to operation615, as illustrated inFIG.6B, in which the handle layer and the buried oxide layer of the SOI wafer are removed to expose an end of the channel structure. Method601proceeds to operation617, as illustrated inFIG.6B, in which part of the channel structure abutting the doped device layer is replaced with a semiconductor plug. In some embodiments, to replace the part of the channel structure abutting the doped device layer with the semiconductor plug, part of the memory film abutting the doped device layer is etched to form a recess surrounding part of the semiconductor channel, the part of the semiconductor channel is doped, and polysilicon is deposited into the recess to form the semiconductor plug surrounding and in contact with the part of the doped semiconductor channel.

Method601proceeds to operation619, as illustrated inFIG.6B, in which a first source contact above the memory stack and in contact with the doped device layer is formed, and a second source contact above the memory stack and in contact with the N-well is formed. Method601proceeds to operation621, as illustrated inFIG.6B, in which an interconnect layer above and in contact with the first and second source contacts is formed. In some embodiments, the interconnect layer includes a first interconnect above and in contact with the first source contact, and a second interconnect above and in contact with the second source contact. In some embodiments, a first contact is formed through the doped device layer and in contact with the first interconnect, such that the doped device layer is electrically connected to the first contact through the first source contact and the first interconnect. In some embodiments, a second contact is formed through the doped device layer and in contact with the second interconnect, such that the N-well is electrically connected to the second contact through the second source contact and the second interconnect.

According to one aspect of the present disclosure, a method for forming a 3D memory device is disclosed. A sacrificial layer on a substrate, an N-type doped semiconductor layer on the sacrificial layer, and a dielectric stack on the N-type doped semiconductor layer are subsequently formed. A channel structure extending vertically through the dielectric stack and the N-type doped semiconductor layer is formed. The dielectric stack is replaced with a memory stack, such that the channel structure extends vertically through the memory stack and the N-type doped semiconductor layer. The substrate and the sacrificial layer are removed to expose an end of the channel structure. Part of the channel structure abutting the N-type doped semiconductor layer is replaced with a semiconductor plug.

In some embodiments, the substrate is a carrier substrate, the sacrificial layer includes a dielectric material, the N-type doped semiconductor layer includes polysilicon, and the dielectric stack includes interleaved stack dielectric layers and stack sacrificial layers.

In some embodiments, to replace the dielectric stack with the memory stack, an opening extending vertically through the dielectric stack is etched, stopping at the N-type doped semiconductor layer, and the stack sacrificial layers are replaced with stack conductive layers through the opening to form the memory stack including interleaved the stack dielectric layers and the stack conductive layers.

In some embodiments, after replacing the dielectric stack with the memory stack, one or more dielectric materials are deposited into the opening to form an insulating structure extending vertically through the memory stack.

In some embodiments, to form the channel structure, a channel hole extending vertically through the dielectric stack and the N-type doped semiconductor layer is etched, stopping at the sacrificial layer, and a memory film and a semiconductor channel are subsequently deposited along a sidewall of the channel hole.

In some embodiments, to replace the part of the channel structure abutting the N-type doped semiconductor layer with the semiconductor plug, part of the memory film abutting the N-type doped semiconductor layer is etched to form a recess surrounding part of the semiconductor channel, the part of the semiconductor channel is doped, and polysilicon is deposited into the recess to form the semiconductor plug surrounding and in contact with the part of the doped semiconductor channel.

In some embodiments, after replacing the part of the channel structure abutting the N-type doped semiconductor layer with the semiconductor plug, a source contact in contact with the N-type doped semiconductor layer is formed.

In some embodiments, an interconnect layer in contact with the source contact is formed.

In some embodiments, a contact through the N-type doped semiconductor layer and in contact with the interconnect layer is formed, such that the N-type doped semiconductor layer is electrically connected to the contact through the source contact and the interconnect layer.

According to another aspect of the present disclosure, a method for forming a 3D memory device is disclosed. A device layer of an SOI wafer including a handle layer, a buried oxide layer, and the device layer is doped with an N-type dopant. A dielectric stack is formed on the doped device layer of the SOI wafer. A channel structure extending vertically through the dielectric stack and the doped device layer is formed. The dielectric stack is replaced with a memory stack, such that the channel structure extends vertically through the memory stack and the doped device layer. The handle layer and the buried oxide layer of the SOI wafer are removed to expose an end of the channel structure. Part of the channel structure abutting the doped device layer is replaced with a semiconductor plug.

In some embodiments, the dielectric stack includes interleaved stack dielectric layers and stack sacrificial layers. In some embodiments, to replace the dielectric stack with the memory stack, an opening extending vertically through the dielectric stack is etched, stopping at the doped device layer, and the stack sacrificial layers are replaced with stack conductive layers through the opening to form the memory stack including interleaved the stack dielectric layers and the stack conductive layers.

In some embodiments, after replacing the dielectric stack with the memory stack, one or more dielectric materials are deposited into the opening to form an insulating structure extending vertically through the memory stack.

In some embodiments, to form the channel structure, a channel hole extending vertically through the dielectric stack and the doped device layer is etched, stopping at the buried oxide layer, and a memory film and a semiconductor channel are subsequently deposited along a sidewall of the channel hole.

In some embodiments, to replace the part of the channel structure abutting the doped device layer with the semiconductor plug, part of the memory film abutting the doped device layer is etched to form a recess surrounding part of the semiconductor channel, the part of the semiconductor channel is doped, and polysilicon is deposited into the recess to form the semiconductor plug surrounding and in contact with the part of the doped semiconductor channel.

In some embodiments, after replacing the part of the channel structure abutting the doped device layer with the semiconductor plug, a source contact in contact with the doped device layer is formed.

In some embodiments, an interconnect layer in contact with the source contact is formed.

In some embodiments, a contact is formed through the doped device layer and in contact with the interconnect layer, such that the doped device layer is electrically connected to the contact through the source contact and the interconnect layer.

According to still another aspect of the present disclosure, a method for forming a 3D memory device is disclosed. A peripheral circuit is formed on a first substrate. A channel structure extending vertically through a memory stack and an N-type doped semiconductor layer is formed above a second substrate. The first substrate and the second substrate are bonded in a face-to-face manner, such that the memory stack is above the peripheral circuit. The second substrate is removed to expose an upper end of the channel structure. Part of the channel structure abutting the N-type doped semiconductor layer is replaced with a semiconductor plug.

In some embodiments, to form the channel structure, a dielectric stack is formed on the N-type doped semiconductor layer, the channel structure extending vertically through the dielectric stack and the N-type doped semiconductor layer is formed, and the dielectric stack is replaced with the memory stack.

In some embodiments, to form the channel structure, a channel hole extending vertically through the dielectric stack and the N-type doped semiconductor layer is etched, and a memory film and a semiconductor channel are subsequently deposited along a sidewall of the channel hole.

In some embodiments, to replace the part of the channel structure abutting the N-type doped semiconductor layer with the semiconductor plug, part of the memory film abutting the N-type doped semiconductor layer is etched to form a recess surrounding part of the semiconductor channel, the part of the semiconductor channel is doped, and polysilicon is deposited into the recess to form the semiconductor plug surrounding and in contact with the part of the doped semiconductor channel.

In some embodiments, prior to bonding the first substrate and the second substrate, an insulating structure extending vertically through the memory stack is formed.

In some embodiments, after replacing the part of the channel structure abutting the N-type doped semiconductor layer with the semiconductor plug, a source contact above the memory stack and in contact with the N-type doped semiconductor layer is formed.

In some embodiments, an interconnect layer above and in contact with the source contact is formed.

In some embodiments, a contact through the N-type doped semiconductor layer and in contact with the interconnect layer is formed, such that the N-type doped semiconductor layer is electrically connected to the contact through the source contact and the interconnect layer.

In some embodiments, the bonding includes hybrid bonding.

The foregoing description of the specific embodiments will so reveal the general nature of the present disclosure that others can, by applying knowledge within the skill of the art, readily modify and/or adapt for various applications such specific embodiments, without undue experimentation, without departing from the general concept of the present disclosure. Therefore, such adaptations and modifications are intended to be within the meaning and range of equivalents of the disclosed embodiments, based on the teaching and guidance presented herein. It is to be understood that the phraseology or terminology herein is for the purpose of description and not of limitation, such that the terminology or phraseology of the present specification is to be interpreted by the skilled artisan in light of the teachings and guidance.

Embodiments of the present disclosure have been described above with the aid of functional building blocks illustrating the implementation of specified functions and relationships thereof. The boundaries of these functional building blocks have been arbitrarily defined herein for the convenience of the description. Alternate boundaries can be defined so long as the specified functions and relationships thereof are appropriately performed.

The Summary and Abstract sections may set forth one or more but not all exemplary embodiments of the present disclosure as contemplated by the inventor(s), and thus, are not intended to limit the present disclosure and the appended claims in any way.

The breadth and scope of the present disclosure should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.