Patent ID: 12255663

DETAILED DESCRIPTION

The detailed description set forth below, in connection with the appended drawings, is intended as a description of various configurations and is not intended to represent the only configurations in which the concepts described herein may be practiced. The detailed description includes specific details for the purpose of providing a thorough understanding of the various concepts. However, it will be apparent to those skilled in the art that these concepts may be practiced without these specific details. In some instances, well-known structures and components are shown in block diagram form in order to avoid obscuring such concepts.

FIG.1shows an example of a PLL110according to certain aspects of the present disclosure. The PLL110may be used to generate a signal having a desired frequency in a wireless communication system, a micro-processing system, a high-speed data system, etc. For example, the PLL110may be used in a wireless communications system to generate a local oscillator signal having a desired frequency.

The PLL110includes a phase detector120(also referred to as a phase frequency detector (PFD)), a phase-to-current circuit130, a capacitor165, a voltage-controlled oscillator (VCO)160, and a frequency divider170. The VCO160has an input162and an output164. The VCO160is configured to generate an output signal at the output164having a frequency that is tuned by a control voltage (labeled “Vtune”) received at the input162, as discussed further below. The output signal of the VCO160provides the output signal of the PLL110.

The output signal of the VCO160is fed back to the phase detector120via a feedback loop including a frequency divider170. The frequency divider170has an input172coupled to the output164of the VCO160and an output174coupled to the phase detector120. The frequency divider170is configured to receive the output signal of the VCO160at the input172, divide the frequency of the output signal to generate a feedback signal (labeled “FB”), and output the feedback signal to the phase detector120via the output174. The feedback signal has a frequency equal to fout/N, where foutis the frequency of the output signal of the VCO160, and N is a divider of the frequency divider170.

The phase detector120has a first input122, a second input124coupled to the output174of the frequency divider170, and an output126coupled to the phase-to-current circuit130. The phase detector120is configured to receive a reference signal (labeled “Ref”) at the first input122and receive the feedback signal at the second input124. The reference signal provides a reference frequency for the PLL110and may include a clock signal from a crystal oscillator or another stable clock source. The phase detector120is configured to detect a phase difference (i.e., a phase error) between the reference signal and the feedback signal, and output a phase signal at the output126indicating the detected phase difference (i.e., phase error).

The phase-to-current circuit130has an input132coupled to the output126of the phase detector120, and an output134coupled to the capacitor165. The phase-to-current circuit130is configured to receive the phase signal from the phase detector120at the input132, generate a current based on the phase signal, and provide the current at the output134. The current may flow in either direction (e.g., depending on whether the reference signal leads or lags the feedback signal). The capacitor165is coupled between the output134of the phase-to-current circuit130and the input162of the VCO160. The capacitor165integrates the current from the phase-to-current circuit130to generate the control voltage (labeled “Vtune”) for the VCO160, which tunes the frequency of the VCO160.

The feedback loop of the PLL110causes the control voltage to tune the frequency of the VCO160in a direction that reduces the phase difference (i.e., phase error) between the feedback signal and the reference signal. When the PLL110is locked, the frequency of the feedback signal is approximately equal to the frequency of the reference signal. Since the frequency of the feedback signal is approximately equal to the frequency of the output signal of the VCO160divided by N, this causes the frequency of the output signal of the VCO160to be approximately equal to N times the frequency of the reference signal. Thus, the PLL110multiplies the frequency of the reference signal by N. The frequency of the output signal of the VCO160(which provides the output signal of the PLL110) may be set to a desired frequency, for example, by setting the value of N accordingly.

FIG.2shows an exemplary implementation of the phase-to-current circuit130according to certain aspects. In this example, the phase-to-current circuit130includes a phase-to-voltage circuit210and a transconductance amplifier230. The transconductance amplifier230may also be referred to as a transconductor, a Gm cell, a transconductance device, or another term.

The phase-to-voltage circuit210has an input212coupled to the output126of the phase detector120, a first output214, and a second output216. The phase-to-voltage circuit210is configured to receive the phase signal from the phase detector120at the input212, and generate a differential voltage including a first voltage (labeled “vp”) and a second voltage (labeled “vm”) based on the phase signal. The phase-to-voltage circuit210outputs the first voltage at the first output214and outputs the second voltage at the second output216. In some implementations, the polarity of the voltage difference between the first voltage and the second voltage (e.g., vp-vm) indicates whether the reference signal leads or lags the feedback signal. However, it is to be appreciated that the present disclosure is not limited to this example. An exemplary implementation of the phase-to-voltage circuit210is discussed further below with reference toFIG.11.

The transconductance amplifier230has a first input232coupled to the first output214of the phase-to-voltage circuit210, a second input234coupled to the second output216of the phase-to-voltage circuit210, and an output236coupled to the capacitor165. The transconductance amplifier230is configured to receive the first voltage at the first input232, receive the second voltage at the second input234, generate a current based on the voltage difference between the first voltage and the second voltage, and provide the current at the output236. The direction of the current may depend on the polarity of the voltage difference between the first voltage and the second voltage, and hence, depend on whether the reference signal leads or lags the feedback signal.

It is to be appreciated that the phase-to-current circuit130is not limited to the exemplary implementation shown inFIG.2. For example, in some implementations, the phase-to-current circuit130may include one or more charge pumps, and/or one or more other components. It is also be appreciated that the PLL110may include one or more additional components between the phase-to-current circuit130and the VCO. For example, in some implementations, the PLL110may further include a resistor and a ripple capacitor coupled in series between the input162of the VCO160and ground.

FIG.3shows an exemplary implementation of the VCO160according to certain aspects. In this example, the VCO160includes an inductor-capacitor (LC) tank330, a first pair of cross-coupled transistors310and315(e.g., p-type field effect transistors (PFETs), and a second pair of cross-coupled transistors320and325(e.g., n-type field effect transistors (NFETs)). In this disclosure, two transistors are cross-coupled when the gate of each of the transistors is coupled to the drain of the other one of the transistors. In the example shown inFIG.3, the first pair of cross-coupled transistors310and315is between the supply rail and the LC tank330, and the second pair of cross-coupled transistors320and325is between the LC tank330and ground.

The LC tank330includes an inductor340, a capacitor bank350, and a voltage-controlled capacitor360. The inductor340, the capacitor bank350, and the voltage-controlled capacitor360may be coupled in parallel, as shown in the example inFIG.3. However, it is to be appreciated that the LC tank330is not limited to this example. The output164of the VCO160is coupled to the LC tank330.

The capacitor bank350may be used to provide coarse tuning of the frequency of the VCO160. In some implementations, the capacitor bank350includes a bank of switchable capacitors (not shown inFIG.3), in which a control circuit370coupled to the capacitor bank350sets the capacitance of the capacitor bank350by controlling which ones of the switchable capacitors are switched on. The capacitance of the capacitor bank350affects the resonance frequency of the LC tank330, which determines the frequency of the VCO160. An exemplary implementation of the capacitor bank350is discussed further below with reference toFIG.4.

The voltage-controlled capacitor360is coupled to the input162of the VCO160. The voltage-controlled capacitor360is configured to receive the control voltage via the input162, and set the capacitance of the voltage-controlled capacitor360based on the control voltage. In this example, the control voltage controls the capacitance of the voltage-controlled capacitor360, which controls the resonance frequency of the LC tank330(and hence the frequency of the VCO160). This allows the feedback loop of the PLL110to tune the frequency of the VCO160by tuning the capacitance of the voltage-controlled capacitor360using the control voltage.

In the example inFIG.3, the voltage-controlled capacitor360include a first varactor364and a second varactor366. The first varactor364and the second varactor366may be coupled in series (e.g., in a back-to-back configuration). In this example, the input162of the VCO160is coupled between the first varactor364and the second varactor366. Each of the varactors364and366may be implemented with a metal-oxide-semiconductor (MOS) varactor, a diode, or another type of varactor. It is to be appreciated that the voltage-controlled capacitor360may include additional varactors in some implementations.

FIG.4shows an exemplary implementation of the capacitor bank350according to certain aspects of the present disclosure. The capacitor bank350includes switchable capacitors410-1to410-ncoupled in parallel. In this example, the control circuit370controls the capacitance of the capacitor bank350by controlling which ones of the switchable capacitors410-1to410-nare switched on, as discussed further below.

In the example inFIG.4, each of the switchable capacitors410-1to410-nincludes respective capacitors420-1to420-nand425-1to425-nand a respective switch430-1to430-ncoupled in series. In this example, the control circuit370switches on a switchable capacitor (i.e., one of the switchable capacitors410-1to410-n) by turning on the respective switch (i.e., respective one of the switches430-1to430-n), and switches off the switchable capacitor by turning off the respective switch. It is to be appreciated that the individual connections between the control circuit370and the switches430-1to430-nare not explicitly shown inFIG.4for ease of illustration. In some implementations, the control circuit370controls the on/off states of the switches430-1to430-nusing codes (e.g., digital codes). For example, each of the codes may include multiple bits, in which each bit corresponds to a respective one of the switchable capacitors410-1to410-n, and the bit value of each bit controls whether the respective one of the switchable capacitors is switched on or off. In this example each of the codes has a respective combination of bit values corresponding to a respective capacitance setting of the capacitor bank350.

It is to be appreciated that the capacitor bank350is not limited to the arrangement of capacitors and switches shown in the example inFIG.4. In general, the capacitor bank350may include switchable capacitors (e.g., switchable capacitors410-1to410-n) coupled in parallel. Each of the switchable capacitors includes one or more capacitors and one or more switches coupled in series, in which the on/off states of the one or more switches are controlled by the control circuit370.

In certain aspects, the control circuit370performs coarse tuning of the frequency of the VCO160(i.e., VCO frequency) during startup of the PLL110to set the frequency of the VCO160close to a target frequency. During the coarse tuning, the input162of the PLL110may be coupled to a voltage equal to Vdd/2 (i.e., half the supply voltage). For example, the input162of the PLL110may be coupled to Vdd/2 through a switch (not shown) that is turned on during the coarse tuning. Thus, in this example, a fixed voltage of Vdd/2 is input to the voltage-controlled capacitor360of the VCO160during the coarse tuning.

The control circuit370performs the coarse tuning of the VCO frequency by tuning the capacitance of the capacitor bank350. For the example where the control circuit370controls the capacitance of the capacitor bank350using codes, the control circuit370may sequentially try different codes where each code corresponds to a respective capacitance setting of the capacitor bank350. While trying the different codes, the control circuit370senses the VCO frequency to determine the code resulting in the VCO frequency that is closest to the target frequency. After determining the code resulting in the VCO frequency that is closest to the target frequency, the control circuit370may set the capacitance of the capacitor bank350based on the determined code.

Thus, the coarse tuning sets the frequency of the VCO160close to the target frequency by determining the coarse setting (e.g., code) resulting in the VCO frequency that is closest to the target frequency. After the coarse tuning, the feedback loop of the PLL110tunes the control voltage (labeled “Vtune”) input to the VCO160to keep the frequency of the VCO160at the target frequency.

Over time, the temperature of the PLL110changes (e.g., due to heating). The change in temperature may cause a change in the inductance of the inductor340, a change in the capacitance of the capacitor bank350, a change in the capacitance of the voltage-controlled capacitor360, and/or a change in one or more other components affecting the frequency of the VCO160. The changes with temperature cause the frequency of the VCO160to drift from the target frequency. In response, the feedback loop of the PLL110adjusts the control voltage to compensate for the change in the temperature to maintain the VCO frequency at the target frequency.

A challenge with temperature compensation is that the practice of performing coarse tuning with the input162of the VCO160coupled to Vdd/2 may significantly reduce the portion of the tunable range of the control voltage that is used for temperature compensation. This is because coupling the input162of the VCO160to Vdd/2 does not take into account the temperature of the PLL110at the time of the coarse tuning. This may be demonstrated by way of the following example.

FIG.5Ashows an example of a frequency versus control voltage curve510of the VCO160for an example of a cold start.FIG.5Aalso shows the tunable range of the control voltage, which has a minimum voltage of Vminand a maximum voltage of Vmax. In this example, coarse tuning is performed when the PLL110is cold. At startup of the PLL110, the control voltage is approximately equal to Vdd/2 since coarse tuning is performed at Vdd/2.

In this example, the temperature of the PLL110gradually increases from the cold start, which causes the frequency versus control voltage curve520to shift down as shown inFIG.5A. As a result, the control voltage needed to maintain the VCO frequency at the target frequency (labeled “Ftarget”) reaches the maximum voltage of Vmax. If the temperature continues to increase further beyond this point, then the control voltage may no longer be able to keep the VCO frequency at the target frequency.

In this example, only about half the tunable range of the control voltage (i.e., Vmax−Vdd/2) is used for temperature compensation. This is because the control voltage starts at approximately the midpoint of the tunable range (i.e., Vdd/2). Since the PLL110starts when the PLL110is cold in this example, the temperature increases from the cold start. As a result, approximately half of the tuning range (i.e., Vdd/2−Vmin) of the control voltage is not utilized for temperature compensation. Thus, for the example of the cold start, the effective tunable range of the control voltage for temperature compensation is reduced by approximately half.

The effective tunable range of the control voltage may also be significantly reduced for the case of a hot start, in which coarse tuning is performed when the PLL110is hot and the temperature of the PLL110decreases from the hot start. An example of a hot start is shown inFIG.5B.FIG.5Bshows an example of the frequency vs control voltage curve530of the VCO160at the startup of the PLL110for a hot start. At startup of the PLL110, the control voltage is approximately equal to Vdd/2 since coarse tuning is performed at Vdd/2.

In this example, the temperature of the PLL110gradually decreases from the hot start, which causes the frequency vs control voltage curve540to shift up as shown inFIG.5B. As a result, the control voltage needed to maintain the VCO frequency at the target frequency (labeled “FTarget”) reaches the minimum voltage of Vmin. If the temperature continues to decrease further beyond this point, then the control voltage may no longer be able to keep the VCO frequency at the target frequency.

In this example, only about half the tunable range of the control voltage (i.e., Vdd/2−Vmin) is used for temperature compensation. This is because the control voltage starts at approximately the midpoint of the tunable range (i.e., Vdd/2). Since the PLL110starts when the PLL110is hot in this example, the temperature decreases from the hot start. As a result, approximately half of the tuning range (i.e., Vmax−Vdd/2) of the control voltage is not utilized for temperature compensation. Thus, for the example of the hot start, the effective tunable range of the control voltage for temperature compensation is reduced by approximately half.

Thus, performing coarse tuning of the VCO160with the input162coupled to a fixed voltage of Vdd/2 regardless of temperature significantly reduces the portion of the tunable range of the control voltage that is used for temperature compensation. For the case of a cold start or the case of a hot start, the portion of the tunable range of the control voltage that is used for temperature compensation is reduced by approximately half.

To address this, aspects of the present disclosure couple the input162of the VCO160to a temperature-dependent voltage during coarse tuning instead of a fixed voltage of Vdd/2. The temperature-dependent voltage increases the portion of the tunable range of the control voltage that is used for temperature compensation, as discussed further below.

FIG.6shows an example of the PLL110further including a temperature circuit610and a switching circuit620according to certain aspects. The temperature circuit610is configured to generate a temperature-dependent voltage (labeled “Vtemp”), and output the temperature-dependent voltage at an output615. The temperature circuit610may include one or more resistors with temperature-dependent resistances (e.g., thermistors), one or more current sources with temperature-dependent currents, and/or one or more other components that are sensitive to temperature. Exemplary implementations of the temperature circuit610are discussed below with reference toFIG.8.

The switching circuit620has a first terminal622, a second terminal624, and a third terminal626. The first terminal622is coupled to the output134of the phase-to-current circuit130. For the example where the phase-to-current circuit130includes the transconductance amplifier230(shown inFIGS.2and3), the first terminal622is coupled to the output236of the transconductance amplifier230. The second terminal624is coupled to the output615of the temperature circuit610. The third terminal626is coupled to the input162of the VCO160(e.g., the voltage-controlled capacitor360).

The switching circuit620is configured to selectively couple the first terminal622to the third terminal626or couple the second terminal624to the third terminal626under the control of the control circuit370. When the switching circuit620couples the first terminal622to the third terminal626, the output134of the phase-to-current circuit130(e.g., the output236of the transconductance amplifier230) is coupled to the input162of the VCO160. When the switching circuit620couples the second terminal624to the third terminal626, the output615of the temperature circuit610is coupled to the input162of the VCO160. Thus, the switching circuit620selectively couples the output134of the phase-to-current circuit130or the output615of the temperature circuit610to the input162of the VCO160under the control of the control circuit370.

In the example inFIG.6, the switching circuit620includes a first switch630between the first terminal622and the third terminal626, and a second switch632between the second terminal624and the third terminal626. In this example, the on/off states of the switches630and632are controlled by the control circuit370. To couple the output134of the phase-to-current circuit130(e.g., the output236of the transconductance amplifier230) to the input162of the VCO160, the control circuit370turns on the first switch630and turns off the second switch632. To couple the output615of the temperature circuit610to the input162of the VCO160, the control circuit370turns off the first switch630and turns on the second switch632. It is to be appreciated that the switching circuit620is not limited to the example shown inFIG.6, and that the switching circuit620may be implemented with various arrangements of switches. Each of the switches630and632may be implemented with a transistor, a transmission gate, or another type of switch.

As discussed above, the control circuit370may perform coarse tuning of the frequency of the VCO160(i.e., VCO frequency) during startup of the PLL110to set the frequency of the VCO160close to the target frequency. During the coarse tuning, the control circuit370causes the switching circuit620to couple the output615of the temperature circuit610to the input162of the VCO160in a first mode. Thus, in this example, the temperature-dependent voltage (labeled “Vtemp”) is input to the voltage-controlled capacitor360(e.g., varactors364and366) instead of a fixed voltage of Vdd/2.

The control circuit370performs the coarse tuning of the VCO frequency in the first mode by tuning the capacitance of the capacitor bank350. For the example where the control circuit370controls the capacitance of the capacitor bank350using codes, the control circuit370may sequentially try different codes where each code corresponds to a respective capacitance setting of the capacitor bank350. While trying the different codes, the control circuit370senses the VCO frequency to determine the code resulting in the VCO frequency that is closest to the target frequency. In this example, the control circuit370may be coupled to the output164of the VCO160to sense the VCO frequency. After determining the code resulting in the VCO frequency that is closest to the target frequency, the control circuit370may set the capacitance of the capacitor bank350based on the code.

Thus, the coarse tuning sets the frequency of the VCO160close to the target frequency by determining the coarse setting (e.g., code) resulting in the VCO frequency that is closest to the target frequency. After the coarse tuning, the control circuit370causes the switching circuit620to couple the output134of the phase-to-current circuit130(e.g., the output236of the transconductance amplifier230) to the input162of the VCO160in a second mode. This allows the feedback loop of the PLL110to tune the control voltage (labeled “Vtune”) input to the VCO160to keep the frequency of the VCO160at the target frequency.

Thus, the control circuit370applies the temperature-dependent voltage (labeled “Vtemp”) to the input162of the VCO160(e.g., the voltage-controlled capacitor360) during coarse tuning instead of a fixed voltage of Vdd/2. Applying the temperature-dependent voltage to the input162of the VCO160during coarse tuning increases the portion of the tunable range of the control voltage that is used for temperature compensation, allowing the PLL110to compensate for temperature over a wider temperature range. This may be demonstrated by way of the following example.

FIG.7Ashows an example of a frequency versus control voltage curve710of the VCO160for an example of a cold start. In this example, coarse tuning is performed when the PLL110is cold. During the coarse tuning, the temperature-dependent voltage from the temperature circuit610(labeled “Vtemp_cold”) is close to the minimum voltage of the control voltage since the PLL110is cold during the coarse tuning. As shown inFIG.7A, the temperature-dependent voltage for the cold start is well below the voltage of Vdd/2, which is used as the starting point for the previous approach regardless of temperature.

In this example, the temperature of the PLL110gradually increases from the cold start, which causes the frequency versus control voltage curve720to shift down as shown inFIG.7A. As a result, the control voltage needed to maintain the VCO frequency at the target frequency (labeled “FTarget”) increases. Because the control voltage starts at a lower voltage (i.e., Vtemp_cold) compared withFIG.5A, the PLL110is able to tune the control voltage over a much wider range (i.e., Vmax−Vtemp_cold) to provide temperature compensation compared withFIG.5A, in which only approximately half the tunable range is used for temperature compensation.

FIG.7Bshows an example of a frequency vs control voltage curve730of the VCO160for an example of a hot start. In this example, coarse tuning is performed when the PLL110is hot. During the coarse tuning, the temperature-dependent voltage from the temperature circuit610(labeled “Vtemp_hot”) is close to the maximum voltage of the control voltage since the PLL110is hot during the coarse tuning. As shown inFIG.7B, the temperature-dependent voltage for the hot start is well above the voltage of Vdd/2, which is used as the starting point for the previous approach regardless of temperature.

In this example, the temperature of the PLL110gradually decreases from the hot start, which causes the frequency vs control voltage curve740to shift up as shown inFIG.7B. As a result, the control voltage needed to maintain the VCO frequency at the target frequency (labeled “FTarget”) decreases. Because the control voltage starts at a higher voltage (i.e., Vtemp_hot) compared withFIG.5B, the PLL110is able to tune the control voltage over a much wider range (i.e., Vtemp_hot−Vmin) to provide temperature compensation compared withFIG.5B, in which only approximately half the tunable range is used for temperature compensation.

In the above examples, the control circuit370couples the temperature circuit610to the input162of the VCO160during coarse tuning, and decouples the temperature circuit610from the input162of the VCO160during operation of the PLL110when the feedback loop tunes the control voltage to maintain the VCO frequency at the target frequency. Because the temperature circuit610is decoupled from the input162of the VCO160during operation of the PLL110, noise on the temperature-dependent voltage does not impact the phase noise performance of the PLL110during operation. As a result, the temperature circuit610does not require a large resistor-capacitor (RC) filter for noise reduction.

Further, in the above examples, the temperature-dependent voltage may be applied to the same varactors364and366that are used for the control voltage without the need for separate temperature varactors for temperature compensation. Not using separate temperature varactors helps avoid difficulties associated with the use of separate temperature varactors such as extensive characterization in a lab to optimize settings for the temperature varactors.

In the example inFIG.6, the capacitor165is coupled between the third terminal626of the switching circuit620and the input162of the VCO160. Placing the capacitor165between the switching circuit620and the VCO160reduces the settling time of the PLL110after the feedback loop of the PLL110is closed. This is because, during coarse tuning, the temperature circuit610charges the capacitor165to the temperature-dependent voltage. As a result, when the feedback loop of the PLL110is closed after coarse tuning, the initial voltage on the capacitor165is approximately equal to the temperature-dependent voltage (e.g., instead of zero volts). After the PLL110is locked, the control voltage Vtune deviates from the initial voltage set by the temperature-dependent voltage by a small amount (e.g., <0.1V), which may depend on the VCO gain and the residual error after coarse tuning. Because of the small difference between the initial voltage set by the temperature-dependent voltage and the control voltage after lock, the settling time of the PLL110is substantially reduced.

The temperature circuit610may be implemented with a proportional to absolute temperature (PTAT) circuit where the temperature-dependent voltage increases with an increase in temperature. Alternatively, the temperature circuit610may be implemented with a conversely proportional to absolute temperature (CTAT) circuit where the temperature-dependent voltage decreases with an increase in temperature.

FIG.8shows an exemplary implementation of the temperature circuit610according to certain aspects. In this example, the temperature circuit610includes a buffer810, a first current source830, a second current source840, a third current source845, and a resistor850. The buffer810may be a unity-gain buffer or another type of buffer. The buffer810has an input812, and an output814coupled to the output615of the temperature circuit610.

The first current source830is coupled between the supply rail and the input812of the buffer810, the second current source840is coupled between the supply rail and the input812of the buffer810, and the third current source845is coupled between the input812of the buffer810and ground. The resistor850is coupled between the input812of the buffer810and ground or some other reference voltage.

In certain aspects, the first current source830is configured to generate a first current (labeled “I_bgu”) that is approximately independent of temperature. The first current source830may be implemented, for example, using a bandgap circuit (not shown) and a resistor (not shown). In this example, the bandgap circuit generates a bandgap voltage that is insensitive to temperature, in which the bandgap voltage is applied across the resistor to generate the first current. However, it is to be appreciated that the present disclosure is not limited to this example.

The second current source840is configured to generate a second current (labeled “I_up”) that is supplied to the resistor850, and the third current source840is configured to generate a third current (labeled “I_dn”) that is drawn away from the resistor850. In this example, the voltage across the resistor850provides the temperate-dependent voltage, which may be given by:

Vtemp=R·I_bgu+R·(I_up-I_dn)(1)
where R is the resistance of the resistor850. The temperature-dependent voltage is applied to the input812of the buffer. For the example where the buffer810is a unity-gain buffer, the buffer810outputs the temperature-dependent voltage at the output814(and hence the output615of the temperature circuit610). In this example, the buffer810helps isolate the resistor850and the current sources830,840, and845at the input812of the buffer810from the loading at the output615of the temperature circuit610.

In this example, the temperature circuit610generates a temperature-dependent voltage that is approximately a linear function of temperature based on equation (1). In some implementations, the first current source830may be used to set the temperature-dependent voltage at a reference temperature (e.g.,25C), and the second current source840and/or the third current source845may be used to set the slope of the temperature-dependent voltage over temperature, as discussed further below.

For example, the second current source840and the third current source845may be configured such that the second current (labeled “I_up) and the third current (labeled “I_dn”) are equal at the reference temperature (e.g., 25 C). As a result, the temperature-dependent voltage at the reference temperature is given by:

Vtemp_ref=R·I_bgu(2)
where Vtemp_ref is the temperature-dependent voltage at the reference temperature (e.g.,25C). Thus, in this example, the voltage-dependent voltage at the reference temperature is a function of the current level of the first current (labeled “I_bgu”) and the resistance of the resistor850. In one example, the current level of the first current source830is controlled by a first digital control signal (labeled “Vnon_ctrl”) from the control circuit370(not shown inFIG.8). In this example, the control circuit370may set the temperature-dependent voltage at the reference temperature by setting the current level of the first current (labeled “I_bgu”) accordingly.

The slope of the temperature-dependent voltage may be positive or negative over temperature. For a positive slope (i.e., upward slope), the second current source840may be implemented with a PTAT current source and the third current source845may be implemented with a constant current source in which the third current (labeled “I_dn”) is approximately constant over temperature. In this example, the second current (labeled “I_up”) from the second current source840increases with an increase in temperature, which causes the temperature-dependent voltage to have a positive slope over temperature. The positive slope is a function of the current level of the second current (labeled “I_up”) over temperature and the resistance of the resistor850. In one example, the current level of the second current source840over temperature is controlled by a second digital control signal (labeled “Slope_ctrl”) from the control circuit370(not shown inFIG.8). In this example, the control circuit370may set the positive slope of the temperature-dependent voltage by setting the current level of the second current (labeled “I_up”) over temperature accordingly.

For a negative slope (i.e., downward slope), the third current source845may be implemented with a PTAT current source and the second current source840may be implemented with constant current source in which the second current (labeled “I_up”) is approximately constant over temperature. In this example, the third current (labeled “I_dn”) from the third current source845increases with an increase in temperature, which causes the temperature-dependent voltage to have a negative slope over temperature since the third current draws current away from the resistor850. The negative slope is a function of the current level of the third current (labeled “I_dn”) over temperature and the resistance of the resistor850. In one example, the current level of the third current source845over temperature is controlled by the second digital control signal (labeled “Slope_ctrl”) from the control circuit370(not shown inFIG.8). In this example, the control circuit370may set the negative slope of the temperature-dependent voltage by setting the current level of the third current (labeled “I_dn”) over temperature accordingly.

The second digital control signal may be input to the second current source840, the third current source845, or both to control the slope of the temperature-dependent voltage.

In the example inFIG.8, the buffer810includes an amplifier860having a first input862, a second input864, and an output866coupled to the output814of the buffer810(and hence the output615of the temperature circuit610). In this example, the output866is coupled to the first input862to provide unity voltage gain. Thus, in this example, the amplifier860acts as a unity-gain buffer. The second input864is coupled to the input812of the buffer810.

FIGS.9A and9Bshow an example in which the PLL110further includes a differential proportional path910according to certain aspects. In this example, the differential proportional path910includes a first signal path912and a second signal path914, in which the first signal path912is between the first output214of the phase-to-voltage circuit210and a second input950of the VCO160, and the second signal path914is between the second output216of the phase-to-voltage circuit210and a third input955of the VCO160.

As shown inFIG.9B, the LC tank330in the VCO160may further include a second voltage-controlled capacitor960coupled to the first signal path912via the second input950, and a third voltage-controlled capacitor970coupled to the second signal path914via the third input955. In the discussion below, the input162may be referred to as the first input and the voltage-controlled capacitor360may be referred to as the first voltage-controlled capacitor360.

In the example shown inFIG.9A, the first signal path912includes a first resistor930and a first capacitor940to provide a low-pass filter (also referred to as an RC network), in which the first resistor930is between the first output214of the phase-to-voltage circuit210and the second input950of the VCO160, and the first capacitor940is between the second input950of the VCO160and ground. The second signal path914includes a second resistor935and a second capacitor945to provide a low-pass filter, in which the second resistor935is between the second output216of the phase-to-voltage circuit210and the third input955of the VCO160, and the second capacitor945is between the third input955of the VCO160and ground.

In this example, the first signal path912receives the first voltage (labeled “vp”) from the phase-to-voltage circuit210, low-pass filters the first voltage, and provides the first voltage after filtering to the second input950of the VCO160. The second signal path914receives the second voltage (labeled “vm”) from the phase-to-voltage circuit210, low-pass filters the second voltage, and provides the second voltage after filtering to the third input955of the VCO160. In this example, the first voltage is input to the second voltage-controlled capacitor960(shown inFIG.9B) after filtering to tune the capacitance of the second voltage-controlled capacitor960, and the second voltage is input to the third voltage-controlled capacitor970(shown inFIG.9B) after filtering to tune the capacitance of the third voltage-controlled capacitor970.

In this example, the path including the capacitor165provides the PLL110with an integral path since the capacitor165integrates the current from the transconductance amplifier230to generate the control voltage (labeled “Vtune”). Thus, in this example, the PLL110is a dual-path PLL including the integral path and the differential proportional path910. The differential proportional path910provides fast phase correction while the integral path provides frequency correction.

In this example, the bandwidth of the PLL110is predominately controlled by the gain of the proportional path910. As a result, the gain of the integral path has little to no impact on the bandwidth of the PLL110. As discussed above, the control voltage on the integral path may vary over a relatively large tunable range to provide temperature compensation. The relatively large tunable range of the control voltage may make it difficult to keep the gain on the integral path linear over the tunable range (and hence temperature). However, since the PLL bandwidth is predominately controlled by the gain of the proportional path910, non-linearity in the gain of the integral path has little to no impact on the PLL bandwidth.

In the example shown inFIG.9B, the second voltage-controlled capacitor960includes a first varactor964and a second varactor966. The first varactor964and the second varactor966may be coupled in series (e.g., in a back-to-back configuration). In this example, the second input950of the VCO160is coupled between the first varactor964and the second varactor966. Each of the varactors964and966may be implemented with a metal-oxide-semiconductor (MOS) varactor, a diode, or another type of varactor. In the example shown inFIG.9B, the varactors964and966are biased by the supply voltage Vdd via bias resistors Rb. The varactors964and966are also AC coupled with the inductor340vias coupling capacitors Cc. It is to be appreciated that the second voltage-controlled capacitor960may include additional varactors in some implementations.

Also, in this example, the third voltage-controlled capacitor970includes a first varactor974and a second varactor976. The first varactor974and the second varactor976may be coupled in series (e.g., in a back-to-back configuration). In this example, the third input955of the VCO160is coupled between the first varactor974and the second varactor976. Each of the varactors974and976may be implemented with a metal-oxide-semiconductor (MOS) varactor, a diode, or another type of varactor. In the example shown inFIG.9B, the varactors974and976have opposite polarity with respect to the varactors964and966since the proportional path910is differential in this example. In this example, the varactors974and976are biased at ground potential via bias resistors Rb. The varactors974and976are also AC coupled with the inductor340vias coupling capacitors Cc. It is to be appreciated that the third voltage-controlled capacitor970may include additional varactors in some implementations.

FIG.10shows an exemplary implementation of the phase detector120according to certain aspects. In this example, the phase detector120includes a first flip-flop1010, a second flip-flop1020, and an AND gate1030. Also, in this example, the output126of the phase detector120includes a first output1022and a second output1024.

The first flip-flop1010has a clock input coupled to the first input122of the phase detector120, an input (labeled “D”) coupled to the supply rail, an output (labeled “Q”) coupled to the first output1022of the phase detector120, and a reset input (labeled “R”). The second flip-flop1020has a clock input coupled to the second input124of the phase detector120, an input (labeled “D”) coupled to the supply rail, an output (labeled “Q”) coupled to the second output1024of the phase detector120, and a reset input (labeled “R”). The AND gate1030has a first input1032coupled to the output of the first flip-flop1010, a second input1034coupled to the output of the second flip-flop1020, and an output1036coupled to the reset input of the first flip-flop1010and the reset input of the second flip-flop1020.

In this example, the phase detector120outputs an up signal (labeled “UP”) at the first output1022and a down signal (labeled “DN”) at the second output1024. The up signal and the down signal indicate whether the reference signal leads or lags the feedback signal, as discussed further below.

When the reference signal leads the feedback signal, the rising edge of the reference signal arrives at the clock input of the first flip-flop1010before the rising edge of the feedback signal arrives at the clock input of the second flip-flop1020. In this case, the output of the first flip-flop1010goes high when the rising edge of the reference signal arrives at the clock input of the first flip-flop1010. When the rising edge of the feedback signal arrives at the clock input of the second flip-flop1020, the output of the second flip-flop1020goes high. When this occurs, both inputs1032and1034of the AND gate1030are high, which causes the output of the AND gate1030to reset the first flip-flop1010and the second flip-flop1020. The reset causes the outputs of both flip-flops1010and1020to return low. Thus, in this example, the first flip-flop1010outputs a positive pulse for the up signal, in which the width of the positive pulse is approximately equal to the time delay between the rising edge of the reference signal and the rising edge of the feedback signal.

When the reference signal lags the feedback signal (i.e., the feedback signal leads the reference signal), the rising edge of the feedback signal arrives at the clock input of the second flip-flop1020before the rising edge of the reference signal arrives at the clock input of the first flip-flop1010. In this case, the output of the second flip-flop1020goes high when the rising edge of the feedback signal arrives at the clock input of the second flip-flop1020. When the rising edge of the reference signal arrives at the clock input of the first flip-flop1010, the output of the first flip-flop1010goes high. When this occurs, both inputs1032and1034of the AND gate1030are high, which causes the output of the AND gate1030to reset the first flip-flop1010and the second flip-flop1020. The reset causes the outputs of both flip-flops1010and1020to return low. Thus, in this example, the second flip-flop1020outputs a positive pulse for the down signal, in which the width of the positive pulse is approximately equal to the time delay between the rising edge of the feedback signal and the rising edge of the reference signal.

FIG.11shows an exemplary implementation of the phase-to-voltage circuit210according to certain aspects. In this example, the phase-to-voltage circuit210includes a first driver1120, a second driver1130, a pre-drive circuit1110, a first sampling switch1160, a second sampling switch1165, a first capacitor1150, and a second capacitor1155.

The first driver1120includes a pull-up transistor1122, a pull-down transistor1124, and a resistor1126between the pull-up transistor1122and the pull-down transistor1124. The pull-up transistor1122(e.g., PFET) has a source coupled to the supply rail and a drain coupled to the resistor1126. The pull-down transistor1124(e.g., NFET) has a drain coupled to the resistor1126, and a source coupled to ground. The first driver1120has an output node1128between the resistor1126and the drain of the pull-down transistor1124. The first capacitor1150is coupled to the output node1128, and the first sampling switch1160is coupled between the output node1128and the first output214of the phase-to-voltage circuit210.

The second driver1130includes a pull-up transistor1132, a pull-down transistor1134, and a resistor1136between the pull-up transistor1132and the pull-down transistor1134. The pull-up transistor1132(e.g., PFET) has a source coupled to the supply rail and a drain coupled to the resistor1136. The pull-down transistor1134(e.g., NFET) has a drain coupled to the resistor1136, and a source coupled to ground. The second driver1130has an output node1138between the resistor1136and the drain of the pull-up transistor1132. The second capacitor1155is coupled to the output node1138, and the second sampling switch1165is coupled between the output node1138and the second output216of the phase-to-voltage circuit210.

The first sampling switch1160and the second sampling switch1165are driven by a sampling clock signal. During each period (i.e., cycle) of the sampling clock signal, the first sampling switch1160and the second sampling switch1165turn on to sample the voltage at the output nodes1128and1138, respectively, and output the sampled voltages at the first and second outputs214and216, respectively, of the phase-to-voltage circuit210. For example, the sampling clock signal may turn on the sampling switches1160and1165when the sampling clock signal is high and turn off the sampling switches1160and1165when the sampling clock signal is low, or vice versa.

In this example, the input212of the phase-to-voltage circuit210includes a first input1102and a second input1104. The first input1102is coupled to the first output1022of the phase detector120to receive the up signal, and the second input1104is coupled to the second output1024of the phase detector120to receive the down signal. The pre-drive circuit1110is configured to receive the up signal and the down signal from the phase detector120, and drive the first driver1120and the second driver1130based on the up signal and the down signal, as discussed further below.

In the example inFIG.11, the pre-drive circuit1110includes a NAND gate1170, an AND gate1180, a first inverter1190, a second inverter1192, a third inverter1194, and a fourth inverter1196. The NAND gate1170has a first input1172, a second input1174, and an output1176. The first input1172is configured to receive an inverse of the reference signal (labeled “Refb”), which may be obtained by inverting the reference signal with an inverter (not shown). The first inverter1190is coupled between the second input1104and the second input1174of the NAND gate1170. As a result, the second input1174of the NAND gate1170receives the inverse of the down signal (labeled “DNb”). The output1176of the NAND gate1170is coupled to the gate of the pull-up transistor1132in the second driver1130. The third inverter1194is coupled between the output1176of the NAND gate1170and the gate of the pull-down transistor1124in the first driver1120.

The AND gate1180has a first input1182, a second input1184, and an output1186. The second inverter1192is coupled between the first input1102and the first input1182of the AND gate1180. As a result, the first input1182of the AND gate1180receives the inverse of the up signal (labeled “UPb”). The second input1184of the AND gate1180is coupled to the second input1104to receive the down signal. The output1186of the AND gate1180is coupled to the gate of the pull-down transistor1134in the second driver1130. The fourth inverter1196is coupled between the output1186of the AND gate1180and the gate of the pull-up transistor1122in the first driver1120.

During each phase (i.e., cycle) of the reference signal, when the reference signal is low and the down signal is low, the NAND gate1170turns on the pull-up transistor1132in the second driver1130, and the NAND gate1170and the third inverter1194turn on the pull-down transistor1124in the first driver1120. This causes the pull-up transistor1132to pull the output node1138of the second driver1130high, and the pull-down transistor1124in the first driver1120to pull the output node1128low.

When the reference signal leads the feedback signal, the inverse up signal goes low, which causes the AND gate1180to leave the pull-down transistor1134in the second driver1130turned off and the pull-up transistor1122in the first driver1120turned off. In this case, the output node1138of the second driver1130stays high (e.g., Vdd) and the output node1128of the first driver1120stays low. As a result, the first sampling switch1160samples the low voltage at the output node1128, which is output at the first output214. The second sampling switch1165samples the high voltage (e.g., Vdd) at the output node1138, which is output at the second output216.

When the reference signal lags the feedback signal (i.e., the feedback signal leads the reference signal), the inverse up signal stays high and the down signal goes high, which causes the AND gate1180to turn on the pull-down transistor1134in the second driver1130and turn on the pull-up transistor1122in the first driver1120. In this case, the voltage at the output node1138of the second driver1130ramps down at a rate based on an RC time constant of the resistor1136and the second capacitor1155. The voltage at the output node1128of the first driver1120ramps up at a rate based on an RC time constant of the resistor1126and the first capacitor1150. The first sampling switch1160then samples the voltage at the output node1128and the second sampling switch1165samples the voltage at the output node1138(e.g., when the sampling clock signal goes high). The sampled voltages at the output nodes1128and1138are output at the first output214and the second output216, respectively, of the phase-to-voltage circuit210.

FIG.12Ashows another exemplary implementation of the phase-to-current circuit130according to certain aspects. In this example, the phase-to-current circuit130includes a first charge pump1210for the integral path, and a second charge pump1220for the proportional path. The first charge pump1210has an input1212coupled to the output126of the phase detector120and an output1214coupled to the first terminal622of the switching circuit620. In this example, the first charge pump1210is configured to receive the phase signal (e.g., up signal and down signal) from the phase detector120and provide a current (labeled “ICPI”) based the phase signal. In certain aspects, the current may flow in either direction depending on whether the reference signal leads or lags the feedback signal. For the example where the phase signal includes the up signal and the down signal, the first charge pump1210may supply current to the capacitor165when the up signal is high and draw current from the capacitor165when the down signal is high. However, it is to be appreciated that the first charge pump1210is not limited to this example.

In this example, the second charge pump1220has an input1222coupled to the output126of the phase detector120, and an output1224coupled to a proportional path1240. The proportional path1240is coupled between the output1224of the second charge pump1220and a second input1250of the VCO160, and may include an RC filter1245including a resistor and a capacitor coupled to a reference voltage. The second charge pump1220is configured to receive the phase signal (e.g., up signal and down signal) from the phase detector120and provide a current (labeled “ICPP”) based the phase signal. In certain aspects, the current may flow in either direction depending on whether the reference signal leads or lags the feedback signal. For the example where the phase signal includes the up signal and the down signal, the second charge pump1220may supply current to the RC filter1245when the up signal is high and draw current from the RC filter1245when the down signal is high.

As shown inFIG.12B, the LC tank330in the VCO160may further include a second voltage-controlled capacitor1260coupled to the proportional path1240via the second input1250. The second voltage-controlled capacitor1260may include a first varactor1264and a second varactor1266. The first varactor1264and the second varactor1266may be coupled in series (e.g., in a back-to-back configuration). In this example, the second input1250of the VCO160is coupled between the first varactor1264and the second varactor1266. Each of the varactors1264and1266may be implemented with a metal-oxide-semiconductor (MOS) varactor, a diode, or another type of varactor.

As discussed above, the PLL110may be used in a wireless communications system. In this regard,FIG.13shows an example of a transmitter1310including the PLL110according to certain aspects. In this example, the transmitter1310includes a mixer1325coupled to a baseband processor1315and the PLL110, and a power amplifier1330coupled between the mixer1325and an antenna1320. The PLL110outputs a local oscillator signal (e.g., from the output164of the VCO160) to the mixer1325.

In operation, the baseband processor1315may receive data and process the data into a baseband signal. Processing performed by the baseband processor1315may include coding, modulation, etc. The mixer1325mixes the baseband signal with the local oscillator signal from the PLL110to frequency unconvert the baseband signal into a radio frequency (RF) signal. The power amplifier1330amplifies the RF signal and outputs the amplified RF signal to the antenna1320for transmission.

It is to be appreciated that the transmitter1310may include one or more additional components (e.g., filter, phase shifter, etc.) not shown inFIG.13.

FIG.14shows an example of a receiver1410including the PLL110according to certain aspects. In this example, the receiver1410includes a mixer1430coupled to a baseband processor1415and the PLL110, and a low-noise amplifier1425coupled between an antenna1420and the mixer1430. The PLL110outputs a local oscillator signal (e.g., from the output164of the VCO160) to the mixer1430.

In operation, the antenna1320receives an RF signal, and the low-noise amplifier1425amplifies the RF signal. The mixer1430mixes the RF signal from the low-noise amplifier1425with the local oscillator signal from the PLL110to frequency downconvert the RF signal into a baseband signal. The baseband processor1415receives the baseband signal and processes the baseband signal. Processing performed by the baseband processor1415may include demodulation, decoding, etc.

It is to be appreciated that the receiver1410may include one or more additional components (e.g., filter, phase shifter, etc.) not shown inFIG.14.

FIG.15is a diagram of an environment1500that includes an electronic device1502and a base station1504. The electronic device1502includes a wireless transceiver1596, which may include the transmitter1310and/or the receiver1410.

In the environment1400, the electronic device1502communicates with the base station1504through a wireless link1506. As shown, the electronic device1502is depicted as a smart phone. However, the electronic device1502may be implemented as any suitable computing or other electronic device, such as a cellular base station, a broadband router, an access point, a cellular or mobile phone, a gaming device, a navigation device, a media device, a laptop computer, a desktop computer, a tablet computer, a server computer, a network-attached storage (NAS) device, a smart appliance, a vehicle-based communication system, an Internet of Things (IoT) device, a sensor or security device, an asset tracker, and so forth.

The base station1504communicates with the electronic device1502via the wireless link1506, which may be implemented as any suitable type of wireless link. Although depicted as a base station tower of a cellular radio network, the base station1504may represent or be implemented as another device, such as a satellite, terrestrial broadcast tower, access point, peer to peer device, mesh network node, fiber optic line, another electronic device generally as described above, and so forth. Hence, the electronic device1502may communicate with the base station1504or another device via a wired connection, a wireless connection, or a combination thereof. The wireless link1506can include a downlink of data or control information communicated from the base station1504to the electronic device1502and an uplink of other data or control information communicated from the electronic device1502to the base station1504. The wireless link1506may be implemented using any suitable communication protocol or standard, such as 3rd Generation Partnership Project Long-Term Evolution (3GPP LTE, 3GPP NR 5G), IEEE 1502.11, IEEE 1502.11, Bluetooth™, and so forth.

The electronic device1502includes a processor1580and a memory1582. The memory1582may be or form a portion of a computer readable storage medium. The processor1580may include any type of processor, such as an application processor or a multi-core processor, that is configured to execute processor-executable instructions (e.g., code) stored by the memory1582. The memory1582may include any suitable type of data storage media, such as volatile memory (e.g., random access memory (RAM)), non-volatile memory (e.g., Flash memory), optical media, magnetic media (e.g., disk or tape), and so forth. In the context of this disclosure, the memory1582is implemented to store instructions1584, data1586, and other information of the electronic device1502.

The electronic device1502may also include input/output (I/O) ports1590. The I/O ports1590enable data exchanges or interaction with other devices, networks, or users or between components of the device.

The electronic device1502may further include a signal processor (SP)1592(e.g., such as a digital signal processor (DSP)). The signal processor1592may function similar to the processor1580and may be capable of executing instructions and/or processing information in conjunction with the memory1582.

For communication purposes, the electronic device1502also includes a modem1594(e.g., baseband processor1315and/or1415), the wireless transceiver1596(e.g., the transmitter1310and/or the receiver1410), and one or more antennas (e.g.,1320and/or1415). The wireless transceiver1596provides connectivity to respective networks and other electronic devices connected therewith using RF wireless signals. The wireless transceiver1596may facilitate communication over any suitable type of wireless network, such as a wireless local area network (LAN) (WLAN), a peer to peer (P2P) network, a mesh network, a cellular network, a wireless wide area network (WWAN), a navigational network (e.g., the Global Positioning System (GPS) of North America or another Global Navigation Satellite System (GNSS)), and/or a wireless personal area network (WPAN).

FIG.16illustrates an example of a method1600for operating a PLL (e.g., PLL110) according to certain aspects of the present disclosure. The PLL includes a voltage-controlled oscillator (e.g., VCO160), the VCO including a voltage-controlled capacitor (e.g., voltage-controlled capacitor360) and a capacitor bank (e.g., the capacitor bank350).

At block1610, in a first mode, a temperature-dependent voltage is coupled to the voltage-controlled capacitor. For example, the control circuit370and the switching circuit620may couple the temperature-dependent voltage to an input of the voltage-controlled capacitor. For example, the temperature-dependent voltage may be generated by the temperature circuit610.

At block1620, in the first mode, a capacitance of the capacitor bank is tuned. For example, the capacitance of the capacitor bank may be tuned by the control circuit370. For example, the capacitor bank may have multiple capacitance settings, and tuning the capacitance of the capacitor bank may include determining one of the multiple capacitance settings resulting in a frequency of the VCO that is closest to a target frequency.

At block1630, in a second mode, the voltage-controlled capacitor is coupled in feedback loop of the PLL. For example, the control circuit370and the switching circuit620may couple the voltage-controlled capacitor in the feedback loop. In certain aspects, the feedback loop includes a phase detector (e.g., phase detector120), a frequency divider (e.g., frequency divider170) coupled between the VCO and the phase detector, and a phase-to-current circuit (e.g., phase-to-current circuit130) coupled to an output of the phase detector. In these aspects, coupling the voltage-controlled capacitor in the feedback loop of the PLL comprises coupling an output of the phase-to-current circuit to the input of the voltage-controlled capacitor. In some implementations, the phase-to-current circuit may include the phase-to-voltage circuit210and the transconductance amplifier230. In other implementations, the phase-to-current circuit may include the first charge pump1210.

In certain aspects, the method1600may include decoupling the temperature-dependent voltage from the input of the voltage-controlled capacitor in the second mode, and decoupling the output of the phase-to-current circuit from the input of the voltage-controlled capacitor in the first mode.

Implementation examples are described in the following numbered clauses:1. A system comprising:a voltage-controlled oscillator (VCO) having a first input and an output;a phase detector having a first input, a second input, and an output, wherein the first input of the phase detector is configured to receive a reference signal;a frequency divider coupled between the output of the VCO and the second input of the phase detector;a phase-to-current circuit having an input and an output, wherein the input of the phase-to-current circuit is coupled to the output of the phase detector;a temperature circuit having an output, wherein the temperature circuit is configured to output a temperature-dependent voltage at the output of the temperature circuit;a switching circuit having a first terminal, a second terminal, and a third terminal, wherein the first terminal is coupled to the output of the phase-to-current circuit, the second terminal is coupled to the output of the temperature circuit, and the third terminal is coupled to the first input of the VCO; anda capacitor coupled to the first input of the VCO.2. The system of clause 1, wherein the capacitor is coupled between the third terminal of the switching circuit and the first input of the VCO.3. The system of clause 1 or 2, wherein the VCO comprises:a voltage-controlled capacitor coupled to the first input of the VCO; anda capacitor bank coupled in parallel with the voltage-controlled capacitor.4. The system of clause 3, wherein the voltage-controlled capacitor comprises a first varactor and a second varactor coupled in series, wherein the first input of the VCO is coupled between the first varactor and the second varactor.5. The system of clause 3 or 4, wherein the capacitor bank comprises switchable capacitors coupled in parallel, and each of the switchable capacitors comprises one or more capacitors and one or more switches coupled in series.6. The system of any one of clauses 3 to 5, wherein the VCO further comprises an inductor coupled in parallel with the voltage-controlled capacitor and the capacitor bank.7. The system of any one of clauses 3 to 6, further comprising a control circuit, wherein the control circuit is configured to:in a first mode, cause the switching circuit to couple the second terminal to the third terminal;in the first mode, tune a capacitance of the capacitor bank; andin a second mode, cause the switching circuit to couple the first terminal to the third terminal.8. The system of clause 7, wherein the capacitor bank has multiple capacitance settings, and the control circuit is configured to sequentially set the capacitor bank to different ones of the capacitance settings to tune the capacitance of the capacitor bank.9. The system of clause 8, wherein the control circuit is configured to determine one of the multiple capacitance settings resulting in a frequency at the output of the VCO that is closest to a target frequency.10. The system of clause 9, wherein each of the multiple capacitance settings is set by a respective one of multiple codes, and the control circuit is configured to determine one of the multiple codes resulting a frequency at the output of the VCO that is closest to a target frequency.11. The system of clause 10, wherein the capacitor bank comprises switchable capacitors coupled in parallel, and each of the multiple codes corresponds to a different combination of the switchable capacitors that are switched on.12. The system of any one of clauses 1 to 11, wherein the phase-to-current circuit comprises:a phase-to-voltage circuit coupled to the output of the phase detector, wherein the phase-to-voltage circuit is configured to generate a first voltage and a second voltage based on a phase signal from the phase detector, output the first voltage at a first output of the phase-to-voltage circuit, and output the second voltage at a second output of the phase-to-voltage circuit; anda transconductance amplifier configured to generate a current based on the first voltage and the second voltage, and provide the current at the output of the phase-to-current circuit.13. The system of clause 12, further comprising:a first path coupled between the first output of the phase-to-voltage circuit and a second input of the VCO; anda second path coupled between the second output of the phase-to-voltage circuit and a third input of the VCO.14. The system of clause 13, wherein the VCO comprises:a first voltage-controlled capacitor coupled to the first input of the VCO;a second voltage-controlled capacitor coupled to the second input of the VCO; anda third voltage-controlled capacitor coupled to the third input of the VCO.15. The system of clause 14, wherein the VCO further comprises an inductor coupled in parallel with the first voltage-controlled capacitor, the second voltage-controlled capacitor, and the third voltage-controlled capacitor.16. The system of any one of clauses 1 to 15, wherein the temperature circuit comprises:a first current source configured to generate a first current that is temperature dependent;a resistor coupled to the first current source; anda buffer having an input and an output, wherein the output of the buffer is coupled to the output of the temperature circuit, and the input of the buffer is coupled between the first current source and the resistor.17. The system of clause 16, wherein the first current is proportional to temperature.18. The system of clause 16 or 17, wherein the first current source is coupled between a supply rail and the input of the buffer, and the resistor is coupled between the input of the buffer and a ground.19. The system of any one of clauses 16 to 18, wherein the temperature circuit further comprises a second current source coupled to the resistor, wherein the second current source is configured to generate a second current that is approximately constant over temperature.20. The system of clause 19, wherein the first current source is coupled between the input of the buffer and a ground, the second current source is coupled between a supply rail and the input of the buffer, and the resistor is coupled between the input of the buffer and the ground.21. The system of any one of clauses 16 to 20, wherein the buffer is a unity-gain buffer.22. The system of any one of clauses 16 to 21, wherein the buffer includes an amplifier having an output, a first input, and a second input, wherein the output of the amplifier is coupled to the first input of the amplifier and the output of the buffer, and the second input of the amplifier is coupled to the input of the buffer.23. The system of any one of clauses 1 to 22, wherein the switching circuit comprises:a first switch coupled between the first terminal and the third terminal; anda second switch coupled between the second terminal and the third terminal.24. The system of any one of clauses 1 to 11 and 16 to 23, wherein the phase-to-current circuit includes a charge pump having input coupled to the output of the phase detector, and an output coupled to the first terminal of the switching circuit.25. A method for operating a phase locked loop (PLL), wherein the PLL includes a voltage-controlled oscillator (VCO), the VCO including a voltage-controlled capacitor and a capacitor bank, the method comprising:in a first mode,coupling a temperature-dependent voltage to the voltage-controlled capacitor; andtuning a capacitance of the capacitor bank; andin a second mode, coupling the voltage-controlled capacitor in a feedback loop of the PLL.26. The method of clause 25, wherein the voltage-controlled capacitor comprises a first varactor and a second varactor coupled in series.27. The method of clause 25 or 26, wherein the capacitor bank has multiple capacitance settings, and tuning the capacitance of the capacitor bank comprises sequentially setting the capacitor bank to different ones of the capacitance settings.28. The method of clause 27, further comprising determining one of the multiple capacitance settings resulting in a frequency of the VCO that is closest to a target frequency.29. The method of clause 28, further comprising:in the second mode, setting the capacitance of the capacitor bank to the determined one of the multiple capacitance settings.30. The method of any one of clauses 25 to 29, wherein:the PLL includes a temperature circuit configured to generate the temperature-dependent voltage; andcoupling the temperature-dependent voltage to the voltage-controlled capacitor comprises coupling an output of the temperature circuit to an input of the voltage-controlled capacitor.31. The method of any one of clauses 25 to 30, wherein:the feedback loop includes a phase detector, a frequency divider coupled between an output of the VCO and an input of the phase detector, and a phase-to-current circuit coupled to an output of the phase detector; andcoupling the voltage-controlled capacitor in the feedback loop of the PLL comprises coupling an output of the phase-to-current circuit to an input of the voltage-controlled capacitor.32. The method of clause 31, wherein the PLL includes a capacitor coupled to the input of the voltage-controlled capacitor.33. An apparatus comprises:a voltage-controlled oscillator (VCO) including a voltage-controlled capacitor and a capacitor bank;means for generating a temperature-dependent voltage;means for inputting the temperature-dependent voltage to the voltage-controlled capacitor in a first mode;means for tuning a capacitance of the capacitor bank in the first mode; and means for coupling the voltage-controlled capacitor in a feedback loop of a phase locked loop (PLL) including the VCO in a second mode.34. A system comprising:a voltage-controlled oscillator (VCO);a phase detector configured to receive a reference signal;a frequency divider coupled between an output of the VCO and the phase detector;a phase-to-voltage circuit coupled to an output of the phase detector;a transconductance device coupled to an output of the phase-to-voltage circuit;a temperature circuit configured to output a temperature-dependent voltage; anda switching circuit configured to selectively couple the transconductance device to an input of the VCO and configured to selectively couple the temperature circuit to the input of the VCO.35. The system of clause 34, further comprising at least one resistor-capacitor network coupled between the output of the phase-to-voltage circuit and the VCO.36. The system of clause 34 or 35, wherein the VCO comprises:a voltage-controlled capacitor coupled to the input of the VCO; anda capacitor bank coupled in parallel with the voltage-controlled capacitor.37. The system of clause 36, wherein the voltage-controlled capacitor comprises a first varactor and a second varactor coupled in series, wherein the input of the VCO is coupled between the first varactor and the second varactor.38. The system of clause 36 or 37, wherein the capacitor bank comprises switchable capacitors coupled in parallel, and each of the switchable capacitors comprises one or more capacitors and one or more switches coupled in series.39. The system of any one of clauses 36 to 38, wherein the VCO further comprises an inductor coupled in parallel with the voltage-controlled capacitor and the capacitor bank.

Within the present disclosure, the word “exemplary” is used to mean “serving as an example, instance, or illustration.” Any implementation or aspect described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other aspects of the disclosure. Likewise, the term “aspects” does not require that all aspects of the disclosure include the discussed feature, advantage or mode of operation. The term “coupled” is used herein to refer to the direct or indirect electrical coupling between two structures.

Any reference to an element herein using a designation such as “first,” “second,” and so forth does not generally limit the quantity or order of those elements. Rather, these designations are used herein as a convenient way of distinguishing between two or more elements or instances of an element. Thus, a reference to first and second elements does not mean that only two elements can be employed, or that the first element must precede the second element.

The previous description of the disclosure is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other variations without departing from the spirit or scope of the disclosure. Thus, the disclosure is not intended to be limited to the examples described herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.