Patent ID: 12230697

DETAILED DESCRIPTION

The advantages and features of the present disclosure and the methods for accomplishing the same will be apparent from the embodiments described hereinafter with reference to the accompanying drawings. However, the embodiments should not be construed as being limited to the embodiments set forth herein. Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art. The terms defined in a generally-used dictionary may not be interpreted ideally or exaggeratedly unless clearly defined. In addition, unless explicitly described to the contrary, the word “comprise”, and variations such as “comprises” or “comprising”, will be understood to imply the inclusion of stated elements but not the exclusion of any other elements.

Further, the singular includes the plural unless mentioned otherwise.

In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Like reference numerals designate like elements throughout the specification.

It will be understood that when an element such as a layer, film, region, or substrate is referred to as being “on” another element, it can be directly on the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly on” another element, there are no intervening elements present.

FIG.1is a view illustrating a cross-section of a semiconductor device10according to an embodiment.FIG.1is a cross-sectional view taken in a direction perpendicular to a direction in which the gate electrode300extends.

For example, a direction in which the gate electrode300extends may be a Z direction, and a direction perpendicular to the Z direction may be an X direction and a Y direction. Hereinafter, in the present specification, the X direction may be referred to as a width direction, the Y direction may be referred to as a height direction, and a direction opposite to the Y direction may be referred to as a depth direction. Also, in this specification, the Y direction may be referred to as an upper direction, and a direction opposite to the Y direction may be referred to as a lower direction.

A semiconductor device10includes an N+ type substrate100, an N− type layer210, a P type region220, a gate electrode300, a source electrode500, and a drain electrode600.

For example, the N+ type substrate100may be an N+ type silicon carbide (SiC) substrate. The N− type layer210is disposed on a first surface of the N+ type substrate100. The N− type layer210may be formed by epitaxial growth or implantation of N− type ions.

The N− type layer210includes a trench240. The trench240is opened toward an opposite side to the side where the N− type layer210faces the N+ type substrate100. In other words, the trench240is opened to the Y direction inFIG.1.

The P type region220is disposed in the N− type layer210and on the side surface of the trench240. For example, the P type region220may be disposed on the upper direction (Y direction) surface of the N− type layer210. The P type region220is a region where P type ions are implanted into the N− type layer210.

Optionally, an N+ type region230may be disposed in the P type region220and on the side surface of the trench240. For example, the N+ type region230may be disposed on the upper direction (Y direction) surface of the P type region220. Accordingly, the N− type layer210, the P type region220, and the N+ type region230may be sequentially disposed in the upper direction (Y direction) on the side surface of the trench240. The ions may be implanted at a higher concentration into the N+ type region230than into the N− type layer210.

A first insulating layer271may be disposed inside the trench240, and on the first insulating layer271, the gate electrode300is disposed. In other words, the first insulating layer271is disposed between the trench240and the gate electrode300.

The gate electrode300may include a first gate electrode region310filling the trench240and a second gate electrode region320protruding outside the trench240.

On the second gate electrode region320protruded outside the trench240, a second insulating layer272is disposed. Optionally, the second insulating layer272may be disposed on the N+ type region230, on the P type region220, or on the N− type layer210.

The gate electrode300may include polysilicon or a metal. The first insulating layer271or the second insulating layer272may include SiO2, Si3N4, or a combination thereof. On the N− type layer210, the source electrode500is disposed. The source electrode500may be disposed on the P type region220, the N+ type region230, and/or the N− type layer210. The source electrode500may be insulated from the gate electrode300by the second insulating layer272. The source electrode500may include Cr, Pt, Pd, Au, Ni, Ag, Cu, Al, Mo, In, Ti, polycrystalline Si, oxides thereof, nitrides thereof, or alloys thereof. In addition, the source electrode500may include a multi-layer electrode structure of stacked different metal layers, for example, Pt/Au, Pt/Al, Pd/Au, Pd/Al, or Pt/Ti/Au and Pd/Ti/Au.

The drain electrode600is disposed on a second surface of the N+ type substrate100. Optionally, the drain electrode600may also be disposed on the N− type layer210. The drain electrode600may include Cr, Pt, Pd, Au, Ni, Ag, Cu, Al, Mo, In, Ti, polycrystalline Si, oxides thereof, nitrides thereof, or alloys thereof. In addition, the drain electrode600may include a multi-layer electrode structure of stacked different metal layers, for example, Ti/Au or Ti/Al.

On the other hand, the N− type layer210includes a P type shield region250disposed under the bottom surface D2of the trench240. The P type shield region250has a structure for protecting the first insulating layer271of the trench240.

The P type shield region250covers the bottom surface D2and edges of the trench240. Herein, the edges of the trench240indicate edges where the bottom surface D2of the trench240meets the sides of the trench. The edges of the trench240are a region where an electric field is most strongly applied, and the P type shield region250may cover the edges of the trench240and thus weaken the electric field at the edges of the trench240.

However, since silicon carbide (SiC) is not well diffused in a horizontal direction during the ion implantation, the P type shield region250covering the edges of the trench240are difficult to form.

FIGS.2and3are views showing cross-sections of conventional methods for manufacturing a semiconductor device10and semiconductor devices manufactured by the methods.

Referring toFIG.2, when the P type shield region250is formed by implanting ions perpendicularly (tilt 0°) to the bottom surface of the trench240, since the ions are not well diffused in the horizontal direction during implantation of the ions, the P type shield region250may not be formed to cover the edges of the trench240(refer to a region A1ofFIG.2). Accordingly, the edges of the trench240are exposed to an epitaxial region and not protected by the P type shield region250.

Referring toFIG.3, when the P type shield region250is formed on the bottom surface of the trench240through tilt ion implantation, the P type shield region250may also be formed in the P type region220and have a problem of blocking a current path (refer to a region A2ofFIG.3). Herein, although a voltage is applied to the gate electrode300, the current path is not formed, not conducting a current.

Accordingly, as the semiconductor device10according to an embodiment is manufactured using inter-ion neutralization (compensation) phenomenon, through a structure including a P type shield region250and an N type current diffusion region260, the above problems may be solved.

The N type current diffusion region260is disposed in the N− type layer210on the side surface of the trench240. The ion concentration of the N type current diffusion region260has an ion concentration (doping concentration) that is equal to or greater than that of the N− type layer210.

When a voltage is applied to the gate electrode300, the N type current diffusion region260serves as a current path through which a current is conducted. Thereby, current reduction does not occur even when the P type shield region250is formed.

Specifically, in the off state, the current path is blocked by the depletion layer formed by the P type region220and the P type shield region250. In this case, the first insulating layer271is protected by the P type shield region250covering the edges of the trench240.

In the on state, a current is conducted through the channel formed by the gate voltage. In this case, the resistance increased due to the interference of the current path of the P type shield region250is offset due to the decrease in resistance caused by the formation of the current path by the N type current diffusion region260.

For reference, the operating conditions of the semiconductor device10are as follows.

Off state: VGS<VTH, VDS≥0 V

On state: VGS≥VTH, VDS>0 V

Herein, VGis a gate voltage, VDis a drain voltage, VSis a source voltage, VTHis threshold voltage of a semiconductor device10, VGS=VG−VS, and VDS=VD−VS.

The N type current diffusion region260may be disposed on the P type shield region250covering the edges of the trench240and the P type shield region250and the N type current diffusion region260may be connected to each other to cover the bottom surface D2and the side surface of the trench240positioned in the N− type layer210. In this case, an effect of forming a current path by the N type current diffusion region260may be increased.

As the semiconductor device10includes the P type shield region250and the N type current diffusion region260, the trench240may include a first trench region241disposed in the P type region220and having a first width W1and a second trench region242disposed in the N− type layer210and having a second width W2.

In this case, the first width W1of the first trench region241may be wider than the second width W2of the second trench region242. The first width W1of the first trench region241may be equal to the width of the P type shield region250, and the second width W2of the second trench region242may be narrower than the width of the P type shield region250. Accordingly, the edge of the bottom surface D2of the second trench region242may be protected by the P type shield region250.

The bottom surface D1of the first trench region241having the first width W1may be disposed in the P type region220, and the bottom surface D1of the first trench region241may not be disposed in the N− type layer210. Accordingly, the entire side surface of the gate electrode300disposed in the N− type layer210is protected by the N type current diffusion region260to increase the resistance reduction effect.

The bottom surface D2of the second trench region242having the second width W2may pass through the N type current diffusion region260and be disposed in the P type shield region250. Accordingly, the edge of the bottom surface D2of the second trench region242may be completely protected by the P type shield region250.

Accordingly, the N type current diffusion region260may be disposed under the bottom surface D1of the first trench region241having the first width W1, on the side surface of the second trench region242having the second width W2, and on an upper portion of the P type shield region250.

In addition, according to the shape of the trench240, the gate electrode300also has a third width in the P type region220, and a fourth width in the N− type layer210, and the third width of the gate electrode300may be wider than the fourth width. Herein, the third width of the gate electrode300is a width excluding the thickness of the first insulating layer271from the first width W1of the trench240, and the fourth width of the gate electrode300is a width excluding the thickness of the first insulating layer271from the second width W2of the trench240.

FIGS.4to14are views sequentially illustrating each step of a method for manufacturing a semiconductor device according to an embodiment. InFIGS.4to14, only the main processes are shown, and the order may be changed depending on process environments and conditions.

Referring toFIG.4, the N− type layer210is formed on the first surface of the N+ type substrate100. For example, after preparing the N+ type substrate100, the N− type layer210is formed on the first surface of the N+ type substrate100through epitaxial growth.

Referring toFIG.5, on the N− type layer210, the P type region220is formed. For example, the P type region220is formed by implanting ions into an upper region of the N− type layer210. Optionally, the N+ type region230may be further formed by implanting ions into a portion of the upper region of the P type region220. Herein, the P type region220and the N+ type region230may be formed not by the ion implantation but by the epitaxial growth.

Next, P type ions are implanted into the N− type layer210and the P type region220with a first width W1to form the P type ion implantation region251.

Referring toFIG.6, a first mask710having an opening having a first width W1is formed on the P type region220. In this case, when the N+ type region230is further included, the first mask710may also be formed on the N+ type region230. The first mask710may be, for example, a hard mask including Si2N3.

Referring toFIG.7, using the first mask710, P type ions are implanted into the N− type layer210and P type region220with a first width W1to form the P type ion implantation region251. In this case, when the N+ type region230is further included, P type ions are also implanted into N+ type region230to form the P type ion implantation region251.

Next, N type ions are implanted with a first width W1to a partial depth of the P type ion implantation region251to form an N type ion implantation region261and a P type shield region250under the N type ion implantation region261.

Referring toFIG.8, N type ions are implanted into the N− type layer210and P type region220with a first width W1using the first mask710. In this case, when the N+ type region230is further included, N type ions may be implanted into the N+ type region230.

The implanted N type ions offset doping of the P type ions implanted to form the P type ion implantation region251.

That is, the method of manufacturing the semiconductor device10according to another embodiment uses such an inter-ion neutralization phenomenon, so that even in the semiconductor device10based on silicon carbide (SiC), the P type shield region250having a shape covering the edges of the trench240may be formed. Herein, when the implantation dose of the N type ions and the implantation dose of the P type ions are equal, and the amount of ions (ion implantation concentration, or doping concentration) that is activated by heat treatment to determine the semiconductor type becomes zero (0), it is called inter-ion neutralization (compensation).

In order to form the N type ion implantation region261using the inter-ion neutralization (compensation) phenomenon, N type ions are implanted with an implantation amount of N type ions equal to or greater than the implantation amount of P type ions. At this time, the ion implantation concentration of the P type ion implantation region251is greater than the ion implantation concentration of the N− type layer210. A difference between the implantation amount of N type ions and the implantation amount of P type ions may be greater than the ion implantation concentration of the N− type layer210, and in this case, the ion implantation concentration of the N− type layer210may be greater than zero. Herein, the implantation amount of P type ions is an amount of P type ions implanted to form the P type ion implantation region251, and the implantation amount of N type ions is an amount of N type ions implanted to form the N type ion implantation region261.

Referring toFIG.9, the N type ion implantation region261is etched to a partial depth using the first mask710to form a first trench region241having a first width W1. That is, P type ions implantation, N type ion implantation, and the first trench region241may be formed using one first mask710.

In this case, in the etching of the N type ion implantation region261, the bottom surface D1of the first trench region241having the first width W1may be disposed in the P type region220, and the may not be disposed in the N− type layer210. Accordingly, the entire side surface of the gate electrode300disposed in the N− type layer210is protected by the N type current diffusion region260to increase the resistance reduction effect.

Referring toFIG.10, a second mask720having an opening having a second width W2is formed on a side surface of the first trench region241. The second mask720may be, for example, a hard mask including Si2N3.

Referring toFIG.11, the P type shield region250is etched to a partial depth through the N type ion implantation region261using the second mask720to form a second trench region242having have a second width W2.

Referring toFIGS.12and13, after the first mask710and the second mask720are removed, a first insulating layer271is formed in the trench240.

Referring toFIG.14, the gate electrode300is formed in the trench240in which the first insulating layer271is formed. In this case, the first gate electrode region310may be formed by filling the inside of the trench240, and a second gate electrode region320protruding outside the trench240may be further formed.

Thereafter, a second insulating layer272is formed on the second gate electrode region320protruding to the outside of the trench240, and a source electrode500is formed on the P type region220, the N+ type region230, and/or the N− type epitaxial layer. The source electrode500is insulated from the gate electrode300by the second insulating layer272.

Finally, the semiconductor device10shown inFIG.1is manufactured by forming the drain electrode600on the second surface of the N+ type substrate100.

The method of manufacturing the semiconductor device according to another embodiment may effectively provide the P type shield region250covering the edge portion of the trench240in an SiC-based semiconductor device10in which horizontal diffusion of ions does not occur well, and may not require a development of a new process technology because a conventional ion implantation process and an epitaxial process are used.

Hereinafter, specific examples of the present disclosure are presented. However, the examples described below are only for specifically illustrating or explaining the present disclosure, and the scope of the present disclosure is not limited thereto.

As shown inFIG.1, the semiconductor device of Example 1 includes a P type shield region covering the bottom surface and edges of the trench, and an N type current diffusion region disposed on the side surface of the trench.

The semiconductor device of Comparative Example 1 has a general trench structure that does not include both the P type shield region and the N type current diffusion region and as shown inFIG.2, the semiconductor device of Comparative Example 2 includes a P type shield region on the bottom surface of the trench, but the P type shield region does not cover the edge of the bottom surface of the trench.

FIG.15is a graph showing the on-state current density measurement results of the semiconductor devices prepared in Comparative Example 1, Comparative Example 2, and Example 1, andFIG.16is a graph illustrating an off-state breakdown voltage measurement result of the semiconductor devices manufactured in Comparative Example 1, Comparative Example 2, and Example 1. In addition, the measurement results ofFIGS.15and16are summarized in Table 1.

TABLE 1ComparativeComparativeExample 1Example 2Example 1Current density723.139208.64390.599[A/cm2](@VDS= 2.5 V)Breakdown voltage152515361510[V]

In addition,FIGS.17and18are views showing current distribution and electric field distribution measurement results of the semiconductor device manufactured in Comparative Example 1;FIGS.19and20are views showing current distribution and electric field distribution measurement results of the semiconductor device manufactured in Comparative Example 2, andFIGS.21and22are views showing current distribution and electric field distribution measurement results of the semiconductor device manufactured in Example 1. Measurements were performed with a Sentaurus TCAD from Synopsys.

Referring toFIGS.15to22and Table 1, the semiconductor device of Example 1 exhibited an increased current density compared to the semiconductor devices of Comparative Examples 1 and 2 at the equivalent breakdown voltage. Specifically, the on-state current density of the semiconductor device of Example 1 is increased by 698% compared to the semiconductor device of Comparative Example 1 at the equivalent breakdown voltage, and the on-state current density of the semiconductor device of Example 1 is increased by 246% compared to the semiconductor device of Comparative Example 2 at the same breakdown voltage.

Accordingly, the semiconductor device according to Example 1 protects an oxide film at the edge portion of the trench gate, and thus may prevent the oxide film from being destroyed and a breakdown voltage from being reduced due to a concentration of an electric field on the oxide film at the edge portion of the trench gate, and may prevent a current being reduced due to ion implantation to protect the edge portion of the trench gate, in particular, in a SiC-based semiconductor device. In addition, the semiconductor device of Example 1 may reduce a device cost by improving the number and yield of devices per unit wafer when designing an equivalent current area.

While the present disclosure has been described in connection with what is presently considered to be practical example embodiments, it is to be understood that the present disclosure is not limited to the disclosed embodiments. On the contrary, it is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.