Patent ID: 12204248

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

A typical lithography development process performed in a semiconductor fabrication facility as part of an integrated circuit (IC) manufacturing process includes depositing a photoresist to a photoresist on the wafer, exposing the photoresist to light using a mask to control the light exposure, and developing the photoresist. The development step includes applying a developer fluid to the photoresist to dissolve resist in areas exposed to the light (in the case of positive photoresist) or to dissolve resist in areas not exposed to the light (in the case of negative photoresist). The developer can be applied to the semiconductor wafer by immersion, spray, puddle, wet spin, or another technique. For deep ultraviolet (DUV) or extreme ultraviolet (EUV) lithography to achieve small feature size additional steps may be performed, such as a post-exposure bake (PEB) to provide chemical amplification, and performing a deionized water (DI) pre-rinse to the semiconductor wafer prior to applying the developer. In the case of DUV or EUV lithography using a chemically amplified (CA) photoresist, photo-acids are produced during the exposure step by a photo-acid generator component of the CA resist. A hard bake may be performed after the development to improve structural stability of the developed photoresist pattern.

However, in experiments reported herein, it has been observed that in some IC manufacturing processes, the device yield is lower than desired. Forensic inspection performed at different stages of the development process found that some failure modes that can occur during the development process relate to lithographic pattern failure during the development step. In lithographic pattern failure, pattern melting occurs. This can lead to bridge defects, arcing defects, and/or the like. The forensic inspection disclosed herein also found that pattern failure tended to occur mostly at the center of the wafer.

As further disclosed herein, and without being limited to any particular theory of operation, it is believed that at least some of the observed lithographic pattern failure events relate to static electric charge buildup in the central region of the semiconductor wafer. Lithographic pattern failures such as bridge and arcing defects are induced by charging of nonmetallic pipes used to deliver process fluids. For example, due to friction, static electric charge is generated and accumulated in non-CO2deionized water (DI) piping, developer (e.g., tetramethylammonium hydroxide, i.e. TMAH) piping, and/or other piping used in the development process. During operation, the fluid from these nonmetallic pipes are believed to deposit electrons at the wafer surface. This causes static electricity accumulation on the wafer surface. The static electric charge buildup at the center region of the wafer (which is where the fluid is delivered in the case of spray delivery) has been observed to occur after a non-CO2DI pre-rinse which is performed prior to delivery of the developer fluid. Due to this static electric charge buildup in the central region of the wafer, the developer cannot neutralize the photo-acids of the photoresist, and therefore lithographic pattern failure (e.g., pattern melting) occurs at the center region of the wafer.

While particularly observed in the case of DI pre-rinse, such static electric charge buildup is also believed to potentially occur during other steps of the development of a CA photoresist, such as during delivery of the developer fluid itself, or during delivery of a photoresist thinner.

In view of these insights disclosed herein, various embodiments disclosed herein provide approaches for suppressing static electric charge delivery from process fluid piping to the wafer surface. Notably, the pipes providing such fluids to the developer system are electrically grounded to reduce or eliminate static charge generation in the pipes. The electrical grounding of a pipe can be implemented in various ways. In one approach, aluminum foil (Al foil) or another a metal foil is disposed over at least a portion of the pipe, and the metal foil is connected to electrical ground. If the chamber or housing within which the development process is performed is an electrically grounded chamber or housing, then the metal foil may be grounded by way of a grounding strap connecting the metal foil to the chamber or housing. Alternatively, the metal foil can directly contact the grounded chamber at the point where the pipe connects into the chamber or housing to provide the electrical grounding.

In another embodiment, the pipe is electrically grounded by way of an electrically conductive coating disposed on the pipe. In this case, a grounding strap is typically suitably employed to ground the electrically conductive coating to the grounded process chamber or housing or other electrical ground point.

With reference toFIG.1, an apparatus for performing a lithography development process is diagrammatically shown. Semiconductor lithography process equipment10for performing this process, also referred to herein as a developer system10, includes a chamber or housing12that is configured to contain a semiconductor wafer14on which is disposed photoresist16. The illustrative chamber or housing12is an electrically grounded chamber or housing. An electrical ground18of the chamber or housing12is diagrammatically shown, and can for example be physically implemented by any type of electrical equipment grounding arrangement meeting applicable electrical safety regulations and providing a sufficient electrical ground for performing the development process. The illustrative electrically grounded chamber or housing12is configured to contain the semiconductor wafer14, which is secured in the chamber or housing12by a suitable wafer mount20that holds the semiconductor wafer14using a vacuum chuck, electrostatic chuck, or the like. The wafer mount20optionally includes an electric heater22for heating the wafer14mounted on the wafer mount20in order to perform a post-exposure bake (PEB), a hard bake, and/or other thermal processing of the semiconductor wafer14as may be appropriate depending on the type of the photoresist16and the development process being implemented. In some embodiments, the wafer mount20includes a rotatable driveshaft24that is connected to a motor (not shown) to enable the semiconductor wafer14to be spun during some or all processing steps, for example to perform a spin-on coating operation or to uniformly apply a process fluid or the like.

As the illustrative example of semiconductor lithography development process equipment10is used to develop the photoresist16on the semiconductor wafer14, the photoresist16is assumed to have already undergone a prior light exposure step in which the photoresist16was exposed to light through a photomask to from a latent image in the photoresist16. The exposure is typically performed in a different apparatus (not shown), such as an EUV or DUV lithography system (not shown). In one nonlimiting illustrative embodiment, the EUV lithography system employs 13 nm EUV light and a reflective mask for the light exposure. In another nonlimiting illustrative example, the exposure may be done using a DUV lithography system, for example using a DUV immersion lithography system employing 193 nm ultraviolet light. The purpose of the development process is then to develop the latent image in the photoresist16to remove portions of the photoresist in those areas that were exposed to the light (in the case of positive photoresist), or in those areas that were not exposed to the light (in the case of negative photoresist) and thereby produce a patterned photoresist on the semiconductor wafer14. In some nonlimiting illustrative embodiments, the photoresist16is a chemically amplified (CA) photoresist. As previously noted, a CA photoresist is particularly sensitive to static electrical charge on the surface of the wafer14, as the static electric charge can interfere with the ability of the developer to neutralize the photo-acids of the CA photoresist16thereby leading to lithographic pattern failure.

The illustrative developer system10further includes or is connected with a deionized water (DI) source30by way of a first pipe32, and is further connected with a developer source34by way of a second pipe36. The first pipe32is connected to deliver DI (or, in other embodiments, another process fluid other than the developer fluid) to the developer system10, and more particularly to the chamber or housing12configured to contain the semiconductor wafer14. The second pipe36is connected to deliver developer fluid to the developer system10(and more particularly to the chamber or housing12configured to contain the semiconductor wafer14). One or both pipes32,36are typically nonmetallic pipes. The use of nonmetallic pipes32,36instead of metal pipes is advantageous because DI, developer fluid, or other process fluids flowing through metal pipes can pick up metallic or other contaminants that can be deposited onto the surface of the semiconductor wafer14and thereby adversely impact the development process. In some embodiments, the nonmetallic pipe or pipes32,36may be fluoropolymer (PFA) pipes. In other embodiments, the nonmetallic pipes may be made of another type of nonmetallic material such as polytetrafluoroethylene (PTFE). By “nonmetallic” it is meant that the pipe or pipes32,36are not a stainless steel pipe, copper or copper alloy pipe, or other metal pipe. In some embodiments, the electrical conductivity of the nonmetallic pipe or pipes32,36is about the same as the electrical conductivity of PFA. It should also be appreciated that while two process fluid sources30,34for DI and developer fluids, respectively, are illustrated, it is contemplated for the developer system10to include or be connected with additional or other process fluids, such a photoresist thinner source or so forth.

The illustrative developer system10is automated by way of inclusion of an electronic process controller40that controls valves42for controlling which fluid source30,34is delivered to a nozzle44at any given time. The illustrative nozzle44is a spray nozzle for spraying the process fluid onto the surface of the wafer14, or for performing a wet spin application in conjunction with rotation of the wafer14by the driveshaft24. In variant embodiments, the chamber or housing12may be designed to apply process fluids by another application process such as immersion or puddle application (variants not shown). The electronic process controller40is also electrically connected to control operation of the optional heater22and the motor (not shown) driving the optional driveshaft24. The electronic process controller40suitably comprises a microprocessor- or microcontroller-based process controller (for example, a computer or a dedicated microprocessor-based programmable electronic controller) that is programmable to control at least the valves42, the optional heater22, and the optional driveshaft motor to perform a development process recipe tailored for a particular type of the photoresist16and a particular IC manufacturing process lithography patterning step being performed. The electronic process controller40may be programmed by way of a suitable non-transitory storage medium (e.g. a flash memory, CMOS memory, magnetic disk, or the like) which stores instructions that are readable and executable by the microprocessor or microcontroller of the electronic process controller40to perform the desired development process recipe.

With continuing reference toFIG.1, as disclosed herein an electrically conductive material50is disposed on the outside of the first pipe32, and similarly an electrically conductive material52is disposed on the outside of the second pipe36. The electrically conductive material50disposed on the outside of the first pipe32is grounded by a connection to the electrically grounded chamber or housing12using a grounding strap54. The electrically conductive material52disposed on the outside of the second pipe36is grounded to the electrically grounded chamber or housing12by way of a direct galvanic connection56of the electrically conductive material52to the electrically grounded chamber or housing12. As diagrammatically indicated inFIG.1by dashed arrows indicating flow of electrons (e−) for the electrically conductive material50, the electrically conductive material50disposed on the outside of the first pipe32along with the grounding strap54serves as an electrical discharge path for static electric charge that might otherwise accumulate in the DI (or other process fluid) flowing through the first pipe32. Notably, while the nonmetallic pipe32is much less electrically conductive than a metal pipe, the nonmetallic pipe32suitably comprises PFA-NE tubing (e.g., TOMBO® No. 9003-NE NAFLON PFA-NE tubing, available from Sunrise Valve Ltd., Taiwan) or another type of fluoropolymer (PFA) based tubing or other somewhat electrically conductive nonmetallic tubing which has sufficient electrical conductivity to permit accumulated electrons to gradually discharge through the nonmetallic pipe32to the electrically conductive material50and grounding strap54. In this way, the static electric charge is diverted away and does not deposit onto the surface of the wafer14. Similarly (although not diagrammatically indicated inFIG.1), the electrically conductive material52disposed on the outside of the second pipe36along with the direct galvanic connection56to the electrically grounded chamber or housing12serves as an electrical discharge path for static electric charge that might otherwise accumulate in the developer fluid flowing through the second pipe36. In this way, that static electric charge is diverted away and does not deposit onto the surface of the wafer14.

With further reference toFIG.1, Inset A, in a variant embodiment the first pipe32includes a first pipe portion32-1that connects with the chamber or housing12, and a second pipe portion32-2that connects with the DI water source30. The first pipe portion32-1and the second pipe portion32-2are connected in series by a valve or other pipe connector58to form the first pipe32. In this embodiment, the first pipe portion32-1that connects with the chamber or housing12comprises PFA-NE or another nonmetallic pipe having sufficient electrical conductivity to transfer electrons from the fluid within the pipe to the electrically conductive material50disposed on the outside of the first pipe32. The second pipe portion32-2that is distal from the chamber or housing12is more electrically insulating than the first pipe portion32-1. Thus, the second pipe portion32-2can comprise a more electrically insulating material such as high purity PFA-HG tubing (e.g., TOMBO® No. 9003-PFA-HG NAFLON PFA-HG tubing, available from Sunrise Valve Ltd., Taiwan), and optionally can be electrically nonconductive. While Inset A illustrates the electrically conductive material50wrapped around and contacting both the first pipe portion32-1and the second pipe portion32-2, in other embodiments it may wrap around or otherwise contact only the more electrically conductive first pipe portion32-1. Furthermore, while Inset A diagrammatically depicts the variant embodiment for the first pipe32, it will be appreciated that this arrangement can additionally or alternatively be employed for the second pipe36.

The electrically conductive material50disposed on the outside of the first pipe32and the electrically conductive material52disposed on the outside of the second pipe36can be variously embodied. In one embodiment, the electrically conductive material50,52comprise metal foils, such as aluminum foil, that are wrapped around the respective nonmetallic pipes32,36. The metal foil should be packed around the pipe to provide good electrical contact between the metal foil and the nonmetallic pipe. In this embodiment, the galvanic connection56of the metal foil52wrapped around the second pipe36to the electrically grounded chamber or housing12is suitably achieved by pressing the metal foil52located adjacent to the connection of the second pipe36to the chamber or housing12against a flange or valve box12aof the chamber or housing12to which the second pipe36is connected. If the chamber or housing12is not electrically grounded, then the metal foils50,52can be grounded to another suitable electrical ground point, such as a grounded housing of the DI water source30and/or developer source34, or a ground line of a nearby electrical cord, or so forth.

In another embodiment, the electrically conductive material50disposed on the outside of the first pipe32and the electrically conductive material52disposed on the outside of the second pipe36can comprise electrically conductive coatings applied to the respective first and second pipes32,36. For example, the electrically conductive coatings can be metal coatings. In this case, the illustrative direct connection56of the electrically conductive coating52disposed on the outside of the second pipe36is suitably replaced by a grounding strap analogous to the grounding strap54used to ground the electrically conductive material50disposed on the outside of the first pipe32.

It should be noted that the electrically conductive material50does not necessarily cover the entire length of the first pipe32; and likewise, the electrically conductive material52does not necessarily cover the entire length of the first pipe36. If the entire length of the pipe is not covered, then the electrically conductive material should cover the portion of the pipe that connects to the chamber or housing12, as illustrated inFIG.1. This ensures that the desired discharge of static electricity (e−) occurs (at least) at the end of the pipe32,36where it connects with the chamber or housing12. As illustrated inFIG.1, the end of the first pipe32connecting to the DI water source30is optionally left uncovered; and likewise, the end of the second pipe36connecting to the developer source34is optionally left uncovered. This is because any static electrical charge developing in the DI or other process fluid flowing through the end of the first pipe32connected to the DI source30flows toward the chamber or housing12and thus passes through the portion of the first pipe32that is covered by the electrically conductive material50, so that static electrical charge is discharged through the electrically conductive material50and grounding strap54. Likewise, any static electrical charge developing in the developer flowing through the end of the second pipe36connected to the developer fluid source34flows toward the chamber or housing12and thus passes through the portion of the second pipe36that is covered by the electrically conductive material52, so that static electrical charge is discharged through the electrically conductive material52and its direct galvanic connection56to the grounded chamber or housing12.

With continuing reference toFIG.1and with further reference toFIG.2, a typical development process is illustrated.FIG.2illustrates a development process as a function of time (vertical axis). It should be noted that the time direction is not necessarily to scale, that is, the vertical dimension of blocks60,62,64,66representing the various process steps does not necessarily represent the actual time entailed in performing those respective process steps. It is also emphasized that the development process depicted inFIG.2is merely a nonlimiting illustrative example. Moreover, prior to the illustrative development process ofFIG.2, the photoresist16on the wafer14is assumed to have already undergone a prior light exposure step to form a latent image in the photoresist16, and the development process ofFIG.2operates to develop the latent image formed by the light exposure by removing portions of the photoresist in those areas that were exposed to the light (in the case of positive photoresist), or in those areas that were not exposed to the light (in the case of negative photoresist). As previously noted, in some embodiments the photoresist16is a chemically amplified (CA) photoresist. Depending on the type of photoresist and other factors, a post-exposure bake (PEB)60may optionally be performed. This can be done in a dedicated PEB oven (not shown) before placing the wafer14into the development system chamber or housing12, or can be done after placing the wafer14into the development system chamber or housing12using the illustrative optional integral heater22, optionally under automated control of the electronic process controller40. In the case of some types of CA photoresists, the optional PEB60may operate to continue the photoacid catalysis that was initiated by the light exposure.

In an operation62, a DI pre-rinse is performed prior to delivery of the developer fluid. The DI rinse62is performed by opening a valve of the valving42under control of the electronic process controller40(or, alternatively, by manually opening the valve in the case of a manual development system) to flow DI from the DI water source30, through the first pipe32into the chamber or housing12and then out of the nozzle44onto the surface of the wafer14. In a typical approach, the nozzle44directs the DI onto the central region of the wafer14, which is being spun via the driveshaft24during the DI rinse step62to cause the DI to flow from the center of the wafer14radially outward to provide laminar flow of DI across the surface of the wafer14, thereby rinsing any particulates or contaminants outward and off the surface of the wafer14. In some embodiments, the DI water source30supplies non-CO2DI water (that is, DI water with a dissolved carbon dioxide level below a specified threshold level) to avoid contaminating the surface of the wafer14with hydrocarbons.

In an operation64, the developer is applied to the surface of the semiconductor wafer14. To this end, the electronic process controller40controls the valving42to close the valve for the DI water and open the valve to flow developer fluid from the developer source34, through the second pipe36into the chamber or housing12and then out of the nozzle44onto the surface of the wafer14. In a typical approach, the nozzle44directs the developer fluid onto the central region of the wafer14, which is being spun via the driveshaft24during the developer application step62to cause the developer fluid to flow from the center of the wafer14radially outward to provide laminar flow of developer fluid across the surface of the wafer14, thereby uniformly developing the latent image in the photoresist16. The developer fluid and its time of application is suitably chosen based on the type of photoresist16that has been coated onto the wafer14and the particular photolithographic patterning being performed. By way of nonlimiting illustrative example, some embodiments in which the photoresist is a CA photoresist, the developer fluid is comprises tetramethylammonium hydroxide (TMAH) and is intended to operate, in part, by neutralizing the photo-acids of the CA photoresist16thereby stabilizing the developed photoresist pattern.

In an optional operation66, a hard bake may be performed after the developer has been applied. The hard bake66, if performed at all, can be done in a dedicated hard bake oven after removal of the wafer14from the development system chamber or housing12and placement into the oven; or the hard back66can be done while the wafer14with the developed photoresist is still in the development system chamber or housing12using the illustrative optional integral heater22, optionally under automated control of the electronic process controller40. The optional hard bake66may operate to increase stability of the developed photoresist pattern. The choice of whether to perform the optional hard bake66is determined based on the type of the photoresist16.

The illustrative development process ofFIG.2is merely a nonlimiting example. A given development process may omit one or more of the PEB60, the DI pre-rinse62, or the hard bake66; and/or may include addition process operations not shown, such as an additional process step or steps to assist in stabilizing the developed photoresist pattern.

Some photoresist development processes were actually-performed without electrically conductive material disposed on the process fluid pipes. That is, the actually-performed development processes were performed without the electrically conductive material50disposed on the outside of the first pipe32, and similarly without the electrically conductive material52is disposed on the outside of the second pipe36. The actually-performed development process included the DI pre-rinse step62and the developer application step64described with reference toFIG.2, with the nozzle44depositing the DI and then the developer at the center of the wafer14with the wafer spinning. The DI fluid applied in the pre-rinse62was non-CO2DI, and the developer fluid applied in the step64was TMAH. In subsequent forensic examination of the developed photoresist pattern, scanning electron microscopy (SEM) imaging of the developed photoresist revealed lithographic pattern failure occurred during the development step. The lithographic pattern failure was observed in the SEM imaging of the wafer performed after the development process as pattern melting as defects and defective regions such as bridge defects, arcing defects, and/or the like. The SEM imaging also found that pattern failure tended to occur mostly in the central region of the wafer.

It was determined that the observed lithographic pattern failure events relate to static electric charge buildup in the central region of the semiconductor wafer. Due to such static electric charge buildup in the central region of the wafer, the developer cannot neutralize the photo-acids of the photoresist (which was a chemically amplified photoresist in the actually-performed development processes), and therefore lithographic pattern failure occurred at the center region of the wafer.

With reference toFIGS.3and4, to establish that surface charge deposition in the central region of the wafer14occurred during the DI rinse step62, surface charge mapping was used to verify the presence of the charge buildup after the DI rinse step62of the development process ofFIG.2.FIG.3presents a charge map70and corresponding charge histogram72of the semiconductor wafer before the DI rinse62. As can be seen, the static charge map exhibits substantial uniformity across the surface of the wafer, with only a small amount of excess static charge in the central region74of the wafer. The substantial uniformity of the charge over the surface of the wafer is also seen in the narrow peak of the charge histogram72. By comparison,FIG.4presents a charge map80and corresponding charge histogram82of the semiconductor wafer after the DI rinse62. As can be seen, the charge map80does exhibit substantial static charge buildup in a central region84of the wafer, and the static charge is nonuniform across the surface of the wafer as exhibited by the broad peak of the charge histogram82.

With reference back toFIG.2and with further reference toFIG.5, and without being limited to any particular theory of operation, the accumulation of static charge during the pre-rinse when performed without the electrically conductive material50disposed on the outside of the first pipe32, and its effect leading to lithographic pattern failure, is diagrammatically shown inFIG.5, and its effects are indicated in column (a) ofFIG.2. The illustrative example shows the semiconductor wafer14comprising a silicon substrate90on which is disposed a bottom layer92and a middle layer94, with the photoresist16disposed on top of the middle layer94. Such a structure is commonly used in some types of lithographically controlled processes, for example to enable formation of openings using etches that cannot be masked by the photoresist16alone. For example, after patterning the photoresist by exposure and the development process ofFIG.2, a first etchant may be used to extend the openings in the patterned photoresist16through the middle layer94, and this patterned middle layer then serves as a mask for a different etch used to extend the openings through the bottom layer92. This again is merely one nonlimiting illustrative example.

The left diagram ofFIG.5diagrammatically depicts the DI pre-rinse step62of the process ofFIG.2. This operation flows DI water96over the surface of the wafer14to rinse the photoresist16prior to development. However, as indicated by explanation98inFIG.2, in the absence of the use of the electrically conductive material50disposed on the outside of the first pipe32, during the DI rinse62electric charge generated by friction along first pipe32is transferred to the wafer14producing static charge102in a central region of the wafer14. Thus, the DI rinse62deposits static electric charge100onto the surface of the wafer14, and more particularly on or in the photoresist16. Notably, the static electric charge100is deposited in the central region of the wafer14and in regions102of the latent image formed in the photoresist16that are to be removed by the subsequent development step64. During the subsequent development application step64(right diagram ofFIG.5), the static charge102blocks the developer fluid from neutralizing the photo-acids of the photoresist16(which again is considered to be a CA photoresist in this example), and therefore lithographic pattern failure occurs in these regions102, as also described in the explanation104inFIG.2. That is, the static charge102in the central region of wafer14leads to photoresist pattern failure.

By contrast, as indicated by explanations106and108in column (b) ofFIG.2, when the DI rinse62is performed with the electrically conductive material50disposed on the outside of the first pipe32, electric charge is again generated by friction along first pipe—but the electric charge is released by grounding via the electrically conductive material50disposed on first pipe32(see explanation106). Hence, in the subsequent developer application step64, static charge is not on wafer14, so photoresist pattern failure does not occur (see explanation108).

The results ofFIGS.3and4relate to charge buildup in the central area of the surface of the wafer14during the DI rinse step62. However, it is anticipated that such charge buildup could also occur during the developer application step64, due to charge frictionally generated in the second pipe36due to flow of the developer fluid being deposited onto the surface of the semiconductor wafer14. To combat this, the electrically conductive material52disposed on the second pipe36carrying the developer fluid operates analogously to the electrically conductive material50disposed on the first pipe32, to discharge the electrical charge produced in the developer fluid to electrical ground via the electrically conductive material52and (in the example ofFIG.1) its direct connection56to the electrically grounded chamber or housing12.

Even more generally, the approach is expected to be useful in semiconductor lithography process equipment (of which the developer system10is an example) in which at least one nonmetallic pipe connected with the semiconductor lithography equipment (of which first and second pipes32,36are examples). In this generalized case, an electrically conductive material is suitably disposed on an outside of the at least one nonmetallic pipe (corresponding to electrically conductive materials50,52ofFIG.1), and is connected to release charge from the at least one nonmetallic pipe to an electrical ground (e.g., via the grounding strap54and the direct connection56in the example ofFIG.1).

In the following, some further embodiments are described.

In a nonlimiting illustrative embodiment, a semiconductor manufacturing method operating on a semiconductor wafer is disclosed. The method comprises performing a deionized (DI) water rinse of the semiconductor wafer by flowing DI water through a nonmetallic pipe and onto the semiconductor wafer and, during the DI water rinse, discharging static electric charge from the DI water flowing through the nonmetallic pipe via an electrically conductive material disposed on an outside of the nonmetallic pipe. The electrically conductive material disposed on the outside of the nonmetallic pipe is electrically grounded. In some embodiments, the nonmetallic pipe comprises fluoropolymer (PFA) based tubing.

In a nonlimiting illustrative embodiment, a semiconductor manufacturing method operating on a semiconductor wafer is disclosed. The method comprises: applying a process fluid to the semiconductor wafer; during the applying of the process fluid, supplying the process fluid that is applied via a nonmetallic pipe; and during the applying of the process fluid, discharging static electricity from the nonmetallic pipe via an electrically grounded electrically conductive material disposed on the outside of the nonmetallic pipe. In some embodiments, the process fluid comprises deionized water (DI).

In a nonlimiting illustrative embodiment, a semiconductor manufacturing method comprises flowing a process fluid through a nonmetallic pipe onto a semiconductor wafer disposed in a chamber or housing, and releasing charge from the process fluid in the nonmetallic pipe to the chamber or housing via an electrically conductive material disposed on an outside of the nonmetallic pipe and in electrical contact with the chamber or housing. In some embodiments, the nonmetallic pipe comprises a PFA-NE pipe connected with the chamber or housing, a second pipe connected with the PFA-NE pipe, and a pipe connector connecting the PFA NE pipe and the second pipe in series, wherein the second pipe is more electrically insulating than the PFA-NE pipe.

In a nonlimiting illustrative embodiment, an apparatus comprises: a developer system configured to develop photoresist disposed on a semiconductor wafer; a developer fluid delivery pipe connected to deliver a developer fluid to the developer system; a fluoropolymer (PFA) pipe connected to deliver a process fluid other than the developer fluid to the developer system; and an electrically conductive material disposed on an outside of the PFA pipe. The developer system is configured to apply developer fluid from the developer fluid delivery pipe to the semiconductor wafer and to apply process fluid from the PFA pipe to the semiconductor wafer. The electrically conductive material disposed on the outside of the PFA pipe is electrically grounded. In some embodiments, the PFA pipe is connected to deliver the process fluid comprising deionized water (DI) to the developer system. In some such embodiments, the developer system is configured to develop the photoresist disposed on the semiconductor wafer by process operations including spraying DI from the PFA pipe onto the wafer, and after the spraying of the DI, spraying developer fluid from the developer fluid delivery pipe onto the wafer.

In a nonlimiting illustrative embodiment, a method of developing photoresist disposed on a semiconductor wafer, is disclosed. The method comprises: performing a deionized (DI) water rinse of the photoresist disposed on the semiconductor wafer by flowing DI water through a nonmetallic pipe and onto the photoresist; during the DI water rinse, discharging static electric charge from the DI water flowing through the nonmetallic pipe via an electrically conductive material disposed on an outside of the nonmetallic pipe; and after the DI water rinse, developing the photoresist by flowing a developer fluid through a second pipe and onto the photoresist. The electrically conductive material disposed on the outside of the nonmetallic pipe is electrically grounded.

In a nonlimiting illustrative embodiment, a method of developing photoresist disposed on a semiconductor wafer includes applying a process fluid to the semiconductor wafer. During the applying of the process fluid, the process fluid that is applied is supplied via a nonmetallic pipe. Also during the applying of the process fluid, static electricity from the nonmetallic pipe is discharged via an electrically grounded electrically conductive material disposed on the outside of the nonmetallic pipe. After the applying of the process fluid, a developer fluid is applied to the semiconductor wafer. In some embodiments, the process fluid comprises deionized water (DI).

In a nonlimiting illustrative embodiment, a method of developing photoresist disposed on a semiconductor wafer includes applying a process fluid to the semiconductor wafer. During the applying of the process fluid, the process fluid that is applied is supplied via a nonmetallic pipe. Also during the applying of the process fluid, static electricity from the nonmetallic pipe is discharged via an electrically grounded electrically conductive material disposed on the outside of the nonmetallic pipe. After the applying of the process fluid, a developer fluid is applied to the semiconductor wafer. During the applying of the developer fluid, the developer fluid that is applied is supplied via a second nonmetallic pipe. Also during the applying of the developer fluid, static electricity from the second nonmetallic pipe is discharged via a second electrically grounded electrically conductive material which is disposed on the outside of the second nonmetallic pipe.

In a nonlimiting illustrative embodiment, an apparatus comprises: semiconductor lithography process equipment; at least one nonmetallic pipe connected with the semiconductor lithography equipment; and an electrically conductive material disposed on an outside of the at least one nonmetallic pipe and connected to release charge from the at least one nonmetallic pipe to an electrical ground.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.