Patent ID: 12197783

The figures are not exhaustive and do not limit the present disclosure to the precise form disclosed.

DETAILED DESCRIPTION

Data IN (DIN) and data OUT (DOUT) speeds for write and read operations for memory devices (e.g., a NAND flash device) continue to increase. Similar performance gains, however, have not been achievable with respect to command and addressing sequencing. As such, the command and addressing sequencing time remains a bottleneck for overall system timing. While the command/addressing speed can be increased to some degree, the extent of the increase that can be achieved is limited. Moreover, this approach is not scalable.

Embodiments of the disclosed technology relate to systems, devices, circuits, methods, computer-readable media, and techniques for performing a command/address sequence associated with a data operation (such as a read operation, write operation, erase operation, etc.) for a memory device that does not require an input/output (I/O) bus, and thus, can be performed in the background and in parallel with DIN/DOUT operations. According to example embodiments of the disclosed technology, the command/address sequence utilizes an existing interface, previously used only for testing of the memory system during manufacturing and prior to shipping to consumers, in a novel way that obviates the need to utilize the I/O bus. Traditionally, the test interface was not utilized for consumer or user DIN/DOUT operations or command/address sequencing. Instead, the test interface, which is include in memory devices (e.g., a NAND flash device), was left unconnected and unused after manufacturing and chip verification. As such, a command/address sequence according to embodiments of the disclosed technology can be performed in parallel with the DIN/DOUT operations, thereby removing the performance bottleneck that would otherwise be caused by the command and address sequencing and providing a technical solution to a technical problem associated with existing command and address sequencing.

In an example embodiment of the disclosed technology, a controller generates a first enable signal for triggering command and address sequencing techniques and generates a first data signal encoded with a second enable signal followed data that includes a command code or an address code. The generated signals are provided to a memory array over a I/O data bus of a second memory interface, where the I/O data bus of the second memory interface is a separate an I/O data bus of a first memory interface used for DIN/DOUT operations. The second enable signal notifies the memory array that the data encoded in the first data signal is a command code or an address code. For instance, the second enable signal may be a command latch enable (CLE) signal or an address latch enable (ALE) signal. In example embodiments, the second interface is a test interface, conventionally used only for testing memory array chip performance during manufacture and before shipment for sale to consumers. Thus, the test interface (e.g., an X1 interface or by 1 interface) uses an I/O data bus comprising a 1- or 2-bit I/O signal lines, whereas the I/O data bus of the first memory interface used for DIN/DOUT operations uses 8-bit I/O signal lines. Embodiments herein are not limited to 1- or 2-bit I/O signal lines, but may include an I/O data bus having fewer I/O signal lines than the I/O data bus used for the DIN/DOUT operations. While the signal lines and associated pins have been generally used only for testing prior to public sale, memory devices are shipped with the test interface and electrical connections (e.g., pins) present within the devices but unused for consumer data.

However, in contrast to these existing memory device, as introduced above, the embodiments herein leverage the existing test interface and electrical connections for command and address sequencing as outlined above. Embodiments herein provide commands and address sequencing for read/write operations using the I/O data bus (referred to herein as a test data bus) of the second memory interface, separate from the data bus used for a DIN/DOUT operation for read/write operations. Using separate bus and data signal frees up the I/O data bus of the first memory interface for additional DIN/DOUT operations. Thus, command/address sequencing can be performed in the background, parallel, and simultaneously with DIN/DOUT operations, which reduces overall data processing overhead by hiding command/address sequencing processing overhead in the background.

Accordingly, embodiments herein provide a technical solution to a technical problem associated with existing command and address sequencing by performing command/address sequence in parallel with DIN/DOUT operations, thereby reducing (and even removing) performance bottleneck due to process time overhead. Thus, read/write operation performance can be improved by hiding (e.g., executing in the background) command/address overhead, which enables embodiments disclosed herein to be constrained more by DIN/DOUT operation speeds and less so by command/address sequencing processing.

FIGS.1to4Gdepict an example memory system that can be used to implement the technology disclosed herein.FIG.1is a schematic block diagram illustrating a memory system100. The memory system100includes a memory device200(also referred to herein as a storage device), a host device106, at least one host device112, and a computer network114.

The host device106may be a computing device (e.g., laptop, desktop, smartphone, tablet, digital camera, wearable smart device, and so on) that includes one or more processors and readable storage devices (such as, but not limited to, RAM, ROM, flash memory, hard disk drive, solid state memory) that store processor readable code (also referred to herein as instructions or software) for programming storage controller102to perform the methods described herein. The host device106may also include additional system memory, one or more input/output interfaces, and/or one or more input/output devices in communication with the one or more processors, as well as other components well known in the art.

The memory system100includes at least one memory device200, comprising the storage controller102and a plurality of memory dies104. “Storage controller” refers to any hardware, device, component, element, or circuit configured to manage data operations on non-volatile memory media, and may comprise one or more processors, programmable processors (e.g., FPGAs), ASICs, micro-controllers, or the like. In some embodiments, the storage controller is configured to store data on and/or read data from non-volatile memory media, to transfer data to/from the non-volatile memory device(s), and so on.

In some embodiments, the memory system100may include two or more memory devices. Each memory device200may include a plurality of memory dies104, such as flash memory, nano random access memory (“nano RAM or NRAM”), magneto-resistive RAM (“MRAM”), dynamic RAM (“DRAM”), phase change RAM (“PRAM”), etc. The data memory device200may also include other types of non-volatile and/or volatile data storage, such as dynamic RAM (“DRAM”), static RAM (“SRAM”), magnetic data storage, optical data storage, and/or other data storage technologies.

The memory device200may be a component within a host device106as depicted inFIG.1, and may be connected using a system bus, such as a peripheral component interconnect express (“PCI-e”) bus, a Serial Advanced Technology Attachment (“serial ATA”) bus, or the like. In another embodiment, the memory device200may be external to the host device106and is connected via a wired connection, such as, but not limited to, a universal serial bus (“USB”) connection, an Institute of Electrical and Electronics Engineers (“IEEE”) 1394 bus (“FireWire”), or the like. In other embodiments, the memory device200may be connected to the host device106using a peripheral component interconnect (“PCI”) express bus using external electrical or optical bus extension or bus networking solution such as Infiniband or PCI Express Advanced Switching (“PCIe-AS”), or the like.

In various embodiments, the memory device200may be in the form of a dual-inline memory die (“DIMM”), a daughter card, or a micro-module. In another embodiment, the memory device200may be a component within a rack-mounted blade. In another embodiment, the memory device200may be contained within a package that is integrated directly onto a higher level assembly (e.g., mother-board, laptop, graphics processor, etc.). In another embodiment, individual components comprising the memory device200may be integrated directly onto a higher level assembly without intermediate packaging.

In some embodiments, instead of directly connected to the host device106via a wired connection, the data memory device200may be connected to the host device106over a wireless connection. For example, the data memory device200may include a storage area network (“SAN”) storage device, a network attached storage (“NAS”) device, a network share, or the like. In some embodiments, the memory system100may be connected to the host via a data network, such as the Internet, a wide area network (“WAN”), a metropolitan area network (“MAN”), a local area network (“LAN”), a token ring, a wireless network, a fiber channel network, a SAN, a NAS, ESCON, or the like, or any combination of networks. A data network may also include a network from the IEEE 802 family of network technologies, such Ethernet, token ring, Wi-Fi, Wi-Max, and the like. A data network may include servers, switches, routers, cabling, radios, and other equipment used to facilitate networking between the host device106and the data memory device200.

The memory system100includes at least one host device106connected to the memory device200. Multiple host devices may be used and may comprise a host, a server, a storage controller of a storage area network (“SAN”), a workstation, a personal computer, a laptop computer, a handheld computer, a supercomputer, a computer cluster, a network switch, router, or appliance, a database or storage appliance, a data acquisition or data capture system, a diagnostic system, a test system, a robot, a portable electronic device, a wireless device, or the like. “Computer” refers to any computing device. Examples of a computer include, but are not limited to, a personal computer, a laptop, a tablet, a desktop, a server, a main frame, a supercomputer, a computing node, a virtual computer, a hand held device, a smart phone, a cell phone, a system on a chip, a single chip computer, and the like. In another embodiment, a host device106may be a client and the memory device200may operate autonomously to service data requests sent from the host device106. In this embodiment, the host device106and memory device200may be connected using a computer network, system bus, DAS or other communication means suitable for connection between a computer and an autonomous memory device200.

The illustrative example shown inFIG.1, the memory system100includes a user application108in communication with a storage client110as part of the host device106. “Application” refers to any software that is executed on a device above a level of the operating system. An application will typically be loaded by the operating system for execution and will make function calls to the operating system for lower-level services. An application often has a user interface, but this is not always the case. Therefore, the term ‘application’ includes background processes that execute at a higher level than the operating system.

“Operating system” refers to logic, typically software, that supports a device's basic functions, such as scheduling tasks, managing files, executing applications, and interacting with peripheral devices. In normal parlance, an application is said to execute “above” the operating system, meaning that the operating system is necessary in order to load and execute the application and the application relies on modules of the operating system in most cases, not vice-versa. The operating system also typically intermediates between applications and drivers. Drivers are said to execute “below” the operating system because they intermediate between the operating system and hardware components or peripheral devices.

In various embodiments, the user application108may be a software application operating on or in conjunction with the storage client110. The storage client110manages files and data and utilizes the functions and features of the storage controller102and associated memory dies104. “File” refers to a unitary data structure for storing, retrieving, and communicating data and/or instructions. A file is distinguished from other types of packaging by having associated management metadata utilized by the operating system to identify, characterize, and access the file. Representative examples of storage clients include, but are not limited to, a server, a file system, an operating system, a database management system (“DBMS”), a volume manager, and the like. The storage client110may be in communication with the storage controller102within the memory device200.

In various embodiments, the memory system100may include one or more clients connected to one or more host device112through one or more computer networks114. A host device112may be a host, a server, a storage controller of a SAN, a workstation, a personal computer, a laptop computer, a handheld computer, a supercomputer, a computer cluster, a network switch, router, or appliance, a database or storage appliance, a data acquisition or data capture system, a diagnostic system, a test system, a robot, a portable electronic device, a wireless device, or the like. The computer network114may include the Internet, a wide area network (“WAN”), a metropolitan area network (“MAN”), a local area network (“LAN”), a token ring, a wireless network, a fiber channel network, a SAN, network attached storage (“NAS”), ESCON, or the like, or any combination of networks. The computer network114may also include a network from the IEEE 802 family of network technologies, such Ethernet, token ring, WiFi, WiMax, and the like.

The computer network114may include servers, switches, routers, cabling, radios, and other equipment used to facilitate networking the host device106or host devices and host devices112or clients. In some embodiments, the memory system100may include one or more host devices112and host device106that communicate as peers over a computer network114. In other embodiments, the memory system100may include multiple memory devices200that communicate as peers over a computer network114. One of skill in the art will recognize other computer networks comprising one or more computer networks and related equipment with single or redundant connection(s) between one or more clients or other computer with one or more memory devices200or one or more memory devices200connected to one or more host devices. In one embodiment, the memory system100may include two or more memory devices200connected through the computer network114to a host device112without a host device106.

In some embodiments, the storage client110communicates with the storage controller102through a host device interface comprising an Input/Output (I/O) interface. “Interface” refers to a protocol and associated circuits, circuitry, components, devices, systems, sub-systems, and the like that enable one device, component, or apparatus to interact and/or communicate with another device, component, or apparatus. For example, the memory device200may support the ATA interface standard, the ATA Packet Interface (“ATAPI”) standard, the small computer system interface (“SCSI”) standard, and/or the Fibre Channel standard which are maintained by the InterNational Committee for Information Technology Standards (“INCITS”).

In certain embodiments, the storage media of a memory device is divided into volumes or partitions. Each volume or partition may include a plurality of sectors. A sector of data is typically 512 bytes, corresponding to the size of a sector in magnetic disk drives.

In various embodiments number of sectors form a block (or data block), anywhere from 8 sectors, which is 4 KB, for example, up to 32, 64, 128 or more sectors. Different sized blocks and sectors can also be used. In certain storage systems, such as those interfacing with the Windows® operating systems, the data blocks may be referred to as clusters. In other storage systems, such as those interfacing with UNIX, Linux, or similar operating systems, the data blocks may be referred to simply as blocks. A block or data block or cluster represents a smallest physical amount of storage space on the storage media that is managed by a storage manager, such as a storage controller, storage system, storage unit, storage device, or the like.

In some embodiments, the storage controller102may be configured to store data on one or more asymmetric, write-once storage media, such as solid-state storage memory cells within the memory die(s)104. As used herein, a “write once” storage media refers to storage media that is reinitialized (e.g., erased) each time new data is written or programmed thereon. As used herein, an “asymmetric” storage media refers to a storage media having different latencies for different storage operations. Many types of solid-state storage media (e.g., memory die) are asymmetric; for example, a read operation may be much faster than a write/program operation, and a write/program operation may be much faster than an erase operation (e.g., reading the storage media may be hundreds of times faster than erasing, and tens of times faster than programming the storage media).

Management of a data block by a storage manager may include specifically addressing a particular data block for a read operation, write operation, or maintenance operation. A block storage device may associate n blocks available for user data storage across the storage media with a logical address, numbered from 0 to n. In certain block storage devices, the logical addresses may range from 0 to n per volume or partition. In conventional block storage devices, a logical address, also referred to as a logical block address (LBA), maps directly to a particular data block on physical storage media. In conventional block storage devices, each data block maps to a particular set of physical sectors on the physical storage media.

However, certain storage devices need not directly or necessarily associate logical addresses with particular physical data blocks. These storage devices may emulate a conventional block storage interface to maintain compatibility with a block storage client110.

In some embodiments, the storage controller102may provide a block I/O emulation layer, which serves as a block device interface, or API. In these embodiments, the storage client110communicates with the storage device through this block device interface. The block I/O emulation layer may receive commands and logical addresses from the storage client110in accordance with this block device interface. As a result, the block I/O emulation layer may provide the storage device compatibility with a block storage client110.

In some embodiments, a storage client110communicates with the storage controller102through a host device interface comprising a direct interface. In these embodiments, the memory device200directly exchanges information specific to non-volatile storage devices. Memory device200using direct interface may store data in the memory die(s)104using a variety of organizational constructs including, but not limited to, blocks, sectors, pages, logical blocks, logical pages, erase blocks, logical erase blocks, ECC codewords, logical ECC codewords, or in any other format or structure advantageous to the technical characteristics of the memory die(s)104.

The storage controller102may receive a logical address and a command from the storage client110and perform the corresponding operation in relation to the memory die(s)104. The storage controller102may support block I/O emulation, a direct interface, or both.

FIG.2Ais a functional block diagram of an example memory device200. The components depicted inFIG.2Aare electrical circuits.

The memory device200may include a storage controller102and a memory array202comprised of a number of memory dies104a-n, the storage controller102and memory dies104a-nbeing effectively as described with regard toFIG.1. Each memory die104a-ncan be a complete memory die or a partial memory die and may include a die controller204, at least one memory structure206, and read/write circuits208. The following description will be made with reference to memory die104aas an example of memory dies104a-n, where each memory die may include same or similar components and function in the same or similar way. Thus, while reference herein is made to memory die104a, the same description may be applied equally to memory dies104b-n.

In this context, “memory array” refers to a set of memory cells (also referred to as storage cells) organized into an array structure having rows and columns. A memory array is addressable using a row identifier and a column identifier, each represented as part of an address, such as a command address. A non-volatile memory array is a memory array having memory cells configured such that a characteristic (e.g., threshold voltage level, resistance level, conductivity, etc.) of the memory cell used to represent stored data remains a property of the memory cell without a requirement for using a power source to maintain the characteristic.

Those of skill in the art recognize that a memory array may comprise the set of memory cells within a plane, the set of memory cells within a memory die, the set of memory cells within a set of planes, the set of memory cells within a set of memory die, the set of memory cells within a memory package, the set of memory cells within a set of memory packages, or with other known memory cell set architectures and configurations.

A memory array may include a set of memory cells at a number of levels of organization within a storage or memory system. In one embodiment, memory cells within a plane may be organized into a memory array. In one embodiment, memory cells within a plurality of planes of a memory die may be organized into a memory array. In one embodiment, memory cells within a plurality of memory dies of a memory device may be organized into a memory array. In one embodiment, memory cells within a plurality of memory devices of a storage system may be organized into a memory array.

In the context ofFIG.2A, memory structure206may be addressable by wordlines via a row decoder210and by bitlines via a column decoder212. The read/write circuits208include multiple sense blocks232including SB1, SB2, . . . , SBp (sensing circuitry) and allow a pages of memory cells to be read or programmed in parallel. Also, many strings of memory cells can be erased in parallel.

“Circuitry”, as used herein, refers to electrical circuitry having at least one discrete electrical circuit, electrical circuitry having at least one integrated circuit, electrical circuitry having at least one application specific integrated circuit, circuitry forming a general purpose computing device configured by a computer program (e.g., a general purpose computer configured by a computer program which at least partially carries out processes or devices described herein, or a microprocessor configured by a computer program which at least partially carries out processes or devices described herein), circuitry forming a memory device (e.g., forms of random access memory), or circuitry forming a communications device (e.g., a modem, communications switch, or optical-electrical equipment).

A physical page may include memory cells along a row of the memory array for a single plane or for a single memory die. In some embodiments, each memory die104a-nincludes a memory array made up of two equal sized planes. A plane is a division of the memory array that permits certain storage operations to be performed on both places using certain physical row addresses and certain physical column addresses. In one embodiment, a physical page of one plane of a memory die includes four data blocks (e.g., 16 KB). In one embodiment, a physical page (also called a “die page”) of a memory die includes two planes each having four data blocks (e.g., 32 KB).

The memory structure206can be two-dimensional (2D—laid out in a single fabrication plane) or three-dimensional (3D—laid out in multiple fabrication planes). The non-volatile memory array206may comprise one or more arrays of memory cells including a 3D array. In one embodiment, the non-volatile memory array206may comprise a monolithic three-dimensional memory structure (3D array) in which multiple memory levels are formed above (and not in) a single substrate, such as a wafer, with no intervening substrates. The non-volatile memory array206may comprise any type of non-volatile memory that is monolithically formed in one or more physical levels of arrays of memory cells having an active area disposed above a silicon substrate. The non-volatile memory array206may be in a non-volatile solid state drive having circuitry associated with the operation of the memory cells, whether the associated circuitry is above or within the substrate. Word lines may comprise sections of the layers containing memory cells, disposed in layers above the substrate. Multiple word lines may be formed on single layer by means of trenches or other non-conductive isolating features.

The die controller204(also referred to as a die control circuitry) cooperates with the read/write circuits208to perform memory operations on memory cells of the non-volatile memory array206and includes a control circuit214(also referred to as a state machine) and a decoder circuit216that may incorporate an address decoder218. The control circuit214provides chip-level control of memory operations on the memory die104a. The die controller204may also include power control circuit215that controls the power and voltages supplied to the wordlines, bitlines, and select lines during memory operations. The power control circuit204may include voltage circuitry, in one embodiment. Power control circuit204may include charge pumps for creating voltages. The sense blocks232include bitline drivers. The power control circuit215executes under control of the control circuit214, in various embodiments.

“Die controller” refers to a set of circuits, circuitry, logic, or components configured to manage the operation of a die. In one embodiment, the die controller is an integrated circuit. In another embodiment, the die controller is a combination of discrete components. In another embodiment, the die controller is a combination of one or more integrated circuits and one or more discrete components. In one example, the die controller may include buffers such as registers, read-only memory (ROM) fuses and other storage devices for storing default values such as base voltages and other parameters.

“Control circuit” refers to a device, component, element, module, system, sub-system, circuitry, logic, hardware, or circuit configured and/or operational to manage one or more other circuits. For example, a controller programmed by firmware to perform the functions described herein is one example of a control circuit. A control circuit can include a processor, a PGA (Programmable Gate Array), an FPGA (Field Programmable Gate Array), an ASIC (Application Specific Integrated Circuit), or another type of integrated circuit or circuit more generally. In certain embodiments, a control circuit is responsible to ensure that primary features and functionality of a larger circuit, die, or chip, that includes the control circuit, perform properly. The address decoder218provides an address interface between that used by the host or a storage controller102to the hardware address used by the row decoder210and column decoder212.

Commands and data are transferred between the host device and storage controller102via a data bus220, and between the storage controller102and an input/output (IO) circuit222on each of the memory dies104a-nvia a memory interface224. The memory interface224may be a type of communication bus, comprising a control bus226and a data bus228(also referred to herein as I/O data bus), over which fixed length command sequences230may be transmitted. “Memory interface” refers to an interface between a memory die and a storage controller. Examples of memory interface that may be used in connection with the disclosed solution include Toggle Mode (“TM”), Toggle NAND2.0, Open NAND Flash Interface (ONFI) NAND, a vendor specific interface, a proprietary interface, and the like. In the depicted embodiment, the memory interface224is a proprietary interface configured to transfer fixed length command sequences230.

“Communication bus” refers to hardware, software, firmware, logic, control line(s), and one or more associated communication protocols, that are configured to enable a sender to send data to a receiver. A communication bus may include a data bus and/or a control bus.

“Firmware” refers to logic embodied as processor-executable instructions stored on volatile memory media and/or non-volatile memory media.

“Data bus” refers to a communication bus used to exchange one or more of data bits between two electronic circuits, components, chips, die, and/or systems. A data bus may include one or more signal/control lines. A sender, such as a controller, may send data signals over one or more control lines of the data bus in parallel (operating as a parallel bus) or in series (operating as a serial bus). A data bus may include the hardware, control line(s), software, firmware, logic, and/or the communication protocol used to operate the data bus.

Examples data buses may include 8-bit buses having 8 control lines, 16-bit buses having 16 control lines, 32-bit buses having 32 control lines, 64-bit buses having 64 control lines, and the like. Control lines may carry exclusively communication data, exclusively address data, exclusively control data, or any combination of these types of data.

In various embodiments, a single data bus may be shared by a plurality of components, such as memory die. When multiple chips or memory dies share a data bus, that data may be accessed or transferred by a single memory die or by all the memory dies in parallel based on signals on a chip enable control line.

A data bus may operate, and be configured, according to an industry standard or based on a proprietary protocol and design. Multiple control line of a data bus may be used in parallel and may latch data into latches of a destination component according to a clocking signal, data strobe signal (“DOS”), or clock, such as strobe signal. In certain embodiments, a control bus and a data bus together may form a communication bus between a sender and a receiver.

“Control bus” refers to a communication bus used to exchange one or more of data, address information, control signals, clock signals, and the like, between two electronic circuits, components, chips, die, and/or systems. A control bus may comprise 1 or more control lines, be configured to operate as a parallel bus or a serial bus, and may include the hardware, control line(s), software, firmware, logic, and/or the communication protocol used to operate the control bus. Typically, a control bus sends control signals to one or more memory die to manage operations on the memory die.

In certain embodiments, the control bus sends control signals such as, for example, one or more of, a write enable (“WE”), chip enable (“CEn”), read enable (“RE”), a clock signal, strobe signal (“DOS”), command latch enable (“CLE”), address latch enable (“ALE”), and the like.

In certain embodiments, the control bus may not transfer data relating to a storage operation, such as write data or read data. Instead, write data and read data may be transferred over a data bus. In certain embodiments, a control bus and a data bus together may form a communication bus between a sender and a receiver.

The address decoder218of the die controller204may be coupled to the memory structure206in order to identify a location within the memory structure206for a storage command. In particular, the address decoder218determines a row identifier and a column identifier which together identifies the location within the memory structure206that applies to a storage command associated with a command address. The storage command and command address are received in a fixed length command sequence.

The input/output (IO) circuit222may be coupled, through the memory interface224and to the memory interface circuit234of the storage controller102, to a data bus220in order to receive a fixed length command sequence230. The decoder circuit216of the die controller204may be coupled through the input/output (IO) circuit222to a control bus226to receive fixed length command sequences230over the data bus220via memory interface circuit234. In one embodiment, the data bus220may comprise eight control lines, each configured to transfer one bit in parallel across the data bus220.

The decoder circuit216may decode a command address and a storage command from a fixed length command sequence. The control circuit214of the die controller204may be coupled to the input/output (IO) circuit222and decoder circuit216and may generate control signals231to execute storage commands decoded by the decoder circuit216. “Control signal” refers to an electrical signal (wired or wireless) sent from one device, component, manager, or controller to another device, component, manager, or controller configured to act in response to the control signal.

The read/write circuits208may be coupled to the non-volatile memory array206and the control circuit214in order to transfer data between the non-volatile memory array206and the input/output (IO) circuit222in response to the storage commands.

In some implementations, some of the components can be combined. In various designs, one or more of the components (alone or in combination), other than memory structure206, can be thought of as at least one control circuit or storage controller which is configured to perform the techniques described herein. For example, a control circuit may include any one of, or a combination of, storage controller102, die controller204, read/write circuits208, column decoder212, control circuit214, decoder circuit216, address decoder218, sense blocks SB1, SB2, . . . , SBp, and so forth.

Associated circuitry may be required for operation of the memory cells and for communication with the memory cells. As non-limiting examples, memory devices may have circuitry used for controlling and driving memory cells to accomplish functions such as programming and reading. This associated circuitry may be on the same substrate as the memory cells and/or on a separate substrate. For example, a storage controller for memory read-write operations may be located on a separate storage controller chip and/or on the same substrate as the memory cells.

In various embodiments, memory structure206comprises a three-dimensional (3D) memory array of non-volatile memory cells in which multiple memory levels are formed above a single substrate, such as a wafer. The memory structure may comprise any type of non-volatile memory monolithically formed in one or more physical levels of arrays of memory cells having an active area disposed above a silicon (or other type of) substrate. In one example, the non-volatile memory cells comprise vertical NAND strings with charge-trapping material. In another embodiment, memory structure206comprises a two-dimensional (2D) memory array of non-volatile memory cells. In one example, the non-volatile memory cells are NAND flash memory cells utilizing floating gates. Other types of memory cells (e.g., NOR-type flash memory) can also be used.

The exact type of memory array architecture or memory cell included in memory structure206is not limited to the examples above. Many different types of memory array architectures or memory technologies can be used to form memory structure206. No particular non-volatile memory technology is required for purposes of the new claimed embodiments proposed herein. Other examples of suitable technologies for memory cells of the memory structure206include resistive random access memory (ReRAM) memories, magnetoresistive RAM (MRAM) memory (e.g., MRAM, Spin Transfer Torque MRAM, Spin Orbit Torque MRAM), phase change memory (PCM), and the like. Examples of suitable technologies for memory cell architectures of the memory structure206include 2D arrays, 3D arrays, cross-point arrays, stacked 2D arrays, vertical bitline arrays, and the like.

Cross point memory—one example of a ReRAM or PCM RAM—includes reversible resistance-switching elements arranged in cross point arrays accessed by X lines and Y lines (e.g., wordlines and bitlines). In another embodiment, the memory cells may include conductive bridge memory elements. A conductive bridge memory element may also be referred to as a programmable metallization cell. A conductive bridge memory element may be used as a state change element based on the physical relocation of ions within a solid electrolyte. In some cases, a conductive bridge memory element may include two solid metal electrodes, one that is relatively inert (e.g., tungsten) and the other of which is electrochemically active (e.g., silver or copper), with a thin film of the solid electrolyte between the two electrodes. As temperature increases, the mobility of the ions also increases causing the programming threshold for the conductive bridge memory cell to decrease. Thus, the conductive bridge memory element may have a wide range of programming thresholds over temperature.

MRAM stores data within magnetic storage elements. The magnetic storage elements are formed from two ferromagnetic plates, each of which can hold a magnetization, separated by a thin insulating layer. One of the two plates is a permanent magnet set to a particular polarity; the other plate's magnetization can be changed to match that of an external field to store memory. A memory device can be built from a grid of such memory cells. In one embodiment for programming, each memory cell lies between a pair of write lines arranged at right angles to each other, parallel to the cell, one above and one below the cell. When current is passed through them, an induced magnetic field is created.

PCM exploits the unique behavior of chalcogenide glass. One embodiment uses a GeTe—Sb2Te3 super lattice to achieve non-thermal phase changes by simply changing the co-ordination state of the Germanium atoms with a laser pulse (or light pulse from another source). As such, the programming doses are laser pulses. The memory cells can be inhibited by blocking the memory cells from receiving the light. Note that the use of “pulse” in this document does not require a square pulse, but also includes a continuous (or non-continuous) vibration or burst of sound, current, voltage light, or other wave.

A person of ordinary skill in the art will recognize that the technology described herein is not limited to a single specific memory structure, but covers many relevant memory structures within the spirit and scope of the technology as described herein and as understood by one of ordinary skill in the art.

FIG.2Bis a block diagram of example memory device200that depicts more details of one embodiment of controller102. While the storage controller102in the embodiment ofFIG.2Bis a flash memory controller, it should be appreciated that memory device200is not limited to flash memory. Thus, the storage controller102is not limited to the particular example of a flash memory controller. As used herein, a flash memory controller is a device that manages data stored on flash memory and communicates with a host, such as a computer or electronic device. A flash memory controller can have various functionality in addition to the specific functionality described herein. For example, the flash memory controller can format the flash memory to ensure the memory is operating properly, map out bad flash memory cells, and allocate spare memory cells to be substituted for future failed cells. Some part of the spare cells can be used to hold firmware to operate the flash memory controller and implement other features. In an example operation, when a host needs to read data from or write data to the flash memory, it will communicate with the flash memory controller. If the host provides a logical address to which data is to be read/written, the flash memory controller can convert the logical address received from the host to a physical address in the flash memory. Alternatively, the host itself can provide the physical address. The flash memory controller can also perform various memory management functions including, but not limited to, wear leveling (distributing writes to avoid wearing out specific blocks of memory that would otherwise be repeatedly written to) and garbage collection (after a block is full, moving only the valid pages of data to a new block, so that the full block can be erased and reused).

The interface between storage controller102and memory dies104may be any suitable flash interface, such as Toggle Mode200,400, or800. In one embodiment, memory device200may be a card-based system, such as a secure digital (SD) or a micro secure digital (micro-SD) card. In an alternate embodiment, memory system100may be part of an embedded memory system. For example, the flash memory may be embedded within the host. In other examples, memory device200can be a solid state drive (SSD).

In some embodiments, memory device200includes a single channel between storage controller102and memory die108. However, the subject matter described herein is not limited to having a single memory channel. For example, in some memory system architectures, 2, 4, 8 or more channels may exist between the controller and the memory die, depending on controller capabilities. In any of the embodiments described herein, more than a single channel may exist between the controller and the memory die, even if only a single channel is shown in the drawings.

As depicted inFIG.2B, storage controller102includes a front-end module236that interfaces with a host, a back-end module238that interfaces with the memory die108, and various other modules that perform functions which will now be described in detail. The components of storage controller102depicted inFIG.2Bmay take various forms including, without limitation, a packaged functional hardware unit (e.g., an electrical circuit) designed for use with other components, a portion of a program code (e.g., software or firmware) executable by a (micro) processor or processing circuitry that usually performs a particular function of related functions, a self-contained hardware or software component that interfaces with a larger system, or the like. For example, each module may include an ASIC, an FPGA, a circuit, a digital logic circuit, an analog circuit, a combination of discrete circuits, gates, or any other type of hardware or combination thereof. Alternatively or additionally, each module may include software stored in a processor readable device (e.g., memory) to program a processor to enable storage controller102to perform the functions described herein.

Referring again to modules of the storage controller102, a buffer manager/bus control240manages buffers in RAM242and controls the internal bus arbitration of storage controller102. ROM244stores system boot code. Although illustrated inFIG.2Bas located separately from the storage controller102, in other embodiments, one or both of RAM242and ROM244may be located within the storage controller102. In yet other embodiments, portions of RAM242and ROM244may be located within the storage controller102, while other portions may be located outside the controller. Further, in some implementations, the storage controller102, RAM242, and ROM244may be located on separate semiconductor dies.

Front-end module236includes a host interface246and a physical layer interface (PHY)248that provide the electrical host interface220with the host or next level storage controller. The choice of the type of host interface220can depend on the type of memory being used. Examples of host interfaces220include, but are not limited to, SATA, SATA Express, SAS, Fibre Channel, USB, PCIe, and NVMe. The host interface220typically facilitates transfer for data, control signals, and timing signals.

Back-end module238includes an error correction code (ECC) engine250that encodes the data bytes received from the host, and decodes and error corrects the data bytes read from the memory dies104. A command sequencer252generates command sequences, such as program and erase command sequences, to be transmitted to memory dies104. A RAID (Redundant Array of Independent Dies) module254manages generation of RAID parity and recovery of failed data. The RAID parity may be used as an additional level of integrity protection for the data being written into the memory device200. In some cases, the RAID module254may be a part of the ECC engine250. Note that the RAID parity may be added as one or more extra dies, or may be added within the existing die, e.g., as an extra plane, an extra block, or extra WLs within a block. As described above in connection withFIG.2A, the memory interface circuit234provides command sequences230to memory die104and receives status information from memory die104, via memory interface224. A flash control layer256controls the overall operation of back-end module238.

Additional components of memory device200illustrated inFIG.2Binclude media management layer (MML)258, which performs wear leveling of memory cells of memory dies104, as well as, other discrete components260, such as external electrical interfaces, external RAM, resistors, capacitors, or other components that may interface with storage controller102. In alternative embodiments, one or more of the physical layer interface248, RAID module254, MML258, or buffer management/bus controller240are optional components.

MML258(e.g., Flash Translation Layer (FTL)) may be integrated as part of the flash management for handling flash errors and interfacing with the host. In particular, MML258may be a module in flash management and may be responsible for the internals of NAND management. In particular, MML258may include an algorithm in the memory device firmware which translates writes from the host into writes to the memory structure205of each memory die104. MML258may be needed because: 1) the memory structure206may have limited endurance; 2) the memory structure206may only be written in multiples of pages; and/or 3) the memory structure206may not be written unless it is erased as a block (or a tier within a block in some embodiments). MML258understands these potential limitations of the memory structure206which may not be visible to the host. Accordingly, MML258attempts to translate the writes from host into writes into the memory structure206.

Storage controller102may interface with one or more memory dies104. In one embodiment, storage controller102and multiple memory dies (together comprising non-volatile storage system100) implement an SSD, which can emulate, replace, or be used in place of a hard disk drive inside a host, as a network access storage (NAS) device, in a laptop, in a tablet, in a server, etc. Additionally, the SSD need not be made to work as a hard drive.

Some embodiments of the memory device200may include one memory dies104connected to one storage controller102. Other embodiments may include multiple memory dies104in communication with one or more controllers102. In one example, the multiple memory dies104can be grouped into a set of memory packages. Each memory package may include one or more memory dies104in communication with storage controller102. In one embodiment, a memory package includes a printed circuit board (or similar structure) with one or more memory dies104mounted thereon. In some embodiments, a memory package can include molding material to encase the memory dies104of the memory package. In some embodiments, storage controller102is physically separate from any of the memory packages.

FIG.3is a perspective view of a portion of a monolithic 3D memory array that includes a plurality of non-volatile memory cells, and that can comprise memory structure206in one embodiment.FIG.3illustrates, for example, a portion of one block of memory. The structure depicted includes a set of bitlines (BLs) positioned above a stack of alternating dielectric layers and conductive layers. For example purposes, one of the dielectric layers is marked as D and one of the conductive layers (also called wordline layers) is marked as W. The number of alternating dielectric and conductive layers can vary based on specific implementation requirements. In some embodiments, the 3D memory array includes between 108-300 alternating dielectric and conductive layers. One example embodiment includes 96 data wordline layers, 8 select layers, 6 dummy wordline layers, and 110 dielectric layers. More or less than 108-300 layers can also be used. Data wordline layers include data memory cells. Dummy wordline layers include dummy memory cells. As will be explained below, the alternating dielectric and conductive layers are divided into four “fingers” by local interconnects LI.FIG.3shows two fingers and two local interconnects LI. Below the alternating dielectric layers and wordline layers is a source line layer SL. Memory holes are formed in the stack of alternating dielectric layers and conductive layers. For example, one of the memory holes is marked as MH. Note that inFIG.3, the dielectric layers are depicted as see-through so that the reader can see the memory holes positioned in the stack of alternating dielectric layers and conductive layers. In one embodiment, NAND strings are formed by filling the memory hole with materials including a charge-trapping material to create a vertical column of memory cells. Each memory cell can store one or more bits of data. More details of the 3D monolithic memory array that may comprise memory structure206is provided below with respect toFIGS.4A-4G.

One of the local interconnects LI separates the block into two horizontal sub-blocks HSB0, HSB1. The block comprises multiple vertical sub-blocks VSB0, VSB1, VSB2. The vertical sub-blocks VSB0, VSB1, VSB2can also be referred to as “tiers.” Each vertical sub-block extends across the block, in one embodiment. Each horizontal sub-block HSB0, HSB1in the block is a part of vertical sub-block VSB0. Likewise, each horizontal sub-block HSB0, HSB1in the block is a part of vertical sub-block VSB1. Likewise, each horizontal sub-block HSB0, HSB1in the block is a part of vertical sub-block VSB2. For ease of explanation, vertical sub-block VSB0will be referred to as a lower vertical sub-block, vertical sub-block VSB1will be referred to as a middle vertical sub-block, and VSB2will be referred to as an upper vertical sub-block. In one embodiment, there are two vertical sub-blocks in a block. In other embodiments, there could be four or more vertical sub-blocks in a block.

A memory operation for a vertical sub-block may be performed on memory cells in one or more horizontal sub-blocks. For example, a programming operation of memory cells in vertical sub-block VSB0may include: programming memory cells in horizontal sub-block HSB0but not horizontal sub-block HSB1; programming memory cells in horizontal sub-block HSB1but not horizontal sub-block HSB0; or programming memory cells in both horizontal sub-block HSB0and horizontal sub-block HSB1.

The different vertical sub-blocks VSB0, VSB1, VSB2are treated as separate units for erase/program purposes, in one embodiment. For example, the memory cells in one vertical sub-block can be erased while leaving valid data in the other vertical sub-blocks. Then, memory cells in the erased vertical sub-block can be programmed while valid data remains in the other vertical sub-blocks. In some cases, memory cells in the middle vertical sub-block VSB1are programmed while there is valid data in the lower vertical sub-block VSB0and/or the upper vertical sub-block VSB2. Programming the memory cells in middle vertical sub-block VSB1may present challenges due to the valid data in the other vertical sub-blocks VSB0, VSB2.

FIG.4Ais a block diagram depicting one example organization of memory structure206, which is divided into two planes302and304. Each plane is then divided into M blocks. In one example, each plane has about 2000 blocks. However, different numbers of blocks and planes can also be used. In one embodiment, a block of memory cells constitutes a single unit for an erase operation. That is, in one embodiment, all memory cells of a block are erased together. In other embodiments, memory cells can be grouped into blocks for other reasons, such as to organize the memory structure206to enable the signaling and selection circuits. In some embodiments, a block represents a groups of connected memory cells that share a common set of wordlines.

FIGS.4B-4Fdepict an example 3D NAND structure that corresponds to the structure ofFIG.3and that can be used to implement memory structure206ofFIGS.2A and2B. Although the example memory system ofFIGS.3-4His a 3D memory structure that includes vertical NAND strings with charge-trapping material, it should be appreciated that other (2D and 3D) memory structures can also be used with the technology described herein.FIG.4Bis a block diagram depicting a top view of a portion of one block from memory structure206. The portion of the block depicted inFIG.4Bcorresponds to portion306in block2ofFIG.4A. As can be seen fromFIG.4B, the block depicted inFIG.4Bextends in the direction of332. While in some embodiments, the memory array may have many layers,FIG.4Billustrates only the top layer.

FIG.4Bdepicts a plurality of circles that represent the vertical columns. Each of the vertical columns include multiple select transistors (also referred to as a select gate or selection gate) and multiple memory cells. In one embodiment, each vertical column implements a NAND string. For example,FIG.4Bdepicts vertical columns422,432,442and452. Vertical column422implements NAND string482. Vertical column432implements NAND string484. Vertical column442implements NAND string486. Vertical column452implements NAND string488. More details of the vertical columns are provided below. Since the block depicted inFIG.4Bextends in the direction of arrow332, the block includes more vertical columns than depicted inFIG.4B.

FIG.4Balso depicts a set of bitlines415, including bitlines411,412,413,414, . . .419.FIG.4Bshows twenty-four bitlines because only a portion of the block is depicted. It is contemplated that more than twenty-four bitlines connected to vertical columns of the block. Each of the circles representing vertical columns has an “x” to indicate its connection to one bitline. For example, bitline414is connected to vertical columns422,432,442and452.

The block depicted inFIG.4Bincludes a set of local interconnects402,404,406,408and410that connect the various layers to a source line below the vertical columns. Local interconnects402,404,406,408and410also serve to divide each layer of the block into four regions; for example, the top layer depicted inFIG.4Bis divided into regions420,430,440and450, which are referred to as fingers. In the layers of the block that implement memory cells, the four regions are referred to as wordline fingers that are separated by the local interconnects. In one embodiment, the wordline fingers on a common level of a block connect together to form a single wordline. In another embodiment, the wordline fingers on the same level are not connected together. In one example implementation, a bitline only connects to one vertical column in each of regions420,430,440and450. In that implementation, each block has sixteen rows of active columns and each bitline connects to four rows in each block. In one embodiment, all of the four rows connected to a common bitline are connected to the same wordline (via different wordline fingers on the same level that are connected together), in which case, the system uses the source side selection lines and the drain side selection lines to choose one (or another subset) of the four to be subjected to a memory operation (program, verify, read, and/or erase).

AlthoughFIG.4Bshows four regions and sixteen rows of vertical columns in a block, with each region having four rows of vertical columns, those exact numbers are an example implementation. Other embodiments may include more or less regions per block, more or less rows of vertical columns per region, and/or more or less rows of vertical columns per block.FIG.4Balso shows the vertical columns being staggered. In other embodiments, different patterns of staggering can be used. In some embodiments, the vertical columns may not be staggered.

FIG.4Cdepicts an embodiment of a stack435showing a cross-sectional view along line AA ofFIG.4B. Two SGD layers (SGD0, SDG1), two SGS layers (SGS0, SGS1) and six dummy wordline layers DWLD0, DWLD1, DWLM1, DWLM0, DWLS0and DWLS1are provided, in addition to the data wordline layers WLL0-WLL95. Each NAND string has a drain side select transistor at the SGD0layer and a drain side select transistor at the SGD1layer. In operation, the same voltage may be applied to each layer (SGD0, SGD1), such that the control terminal of each transistor receives the same voltage. Each NAND string has a source side select transistor at the SGS0layer and a drain side select transistor at the SGS1layer. In operation, the same voltage may be applied to each layer (SGS0, SGS1), such that the control terminal of each transistor receives the same voltage. Also depicted are dielectric layers DL0-DL106.

Columns432,434of memory cells are depicted in the multi-layer stack. The stack includes a substrate301, an insulating film250on the substrate, and a portion of a source line SL. A portion of the bitline414is also depicted. Note that NAND string484is connected to the bitline414. NAND string484has a source-end439at a bottom of the stack and a drain-end438at a top of the stack. The source-end439is connected to the source line SL. A conductive via441connects the drain-end438of NAND string484to the bitline414. The metal-filled slits404and406fromFIG.4Bare also depicted.

The stack435is divided into three vertical sub-blocks (VSB0, VSB1, VSB2). Vertical sub-block VSB0includes WLL0-WLL31. Layers SGS0, SGS1, DWLS0, DWLS1could also be considered to be a part of vertical sub-block VSB0. Vertical sub-block VSB1includes WLL32-WLL63. Layers SGD0, SGD1, DWLD0, DWLD1could also be considered to be a part of vertical sub-block VSB2. Vertical sub-block VSB2includes WLL64-WLL95. Each NAND string has a set of data memory cells in each of the vertical sub-blocks. Dummy wordline layer DMLM0is between vertical sub-block VSB0and vertical sub-block VSB1. Dummy wordline layer DMLM1is between vertical sub-block VSB1and vertical sub-block VSB2. The dummy wordline layers have dummy memory cell transistors that may be used to electrically isolate a first set of memory cell transistors within the memory string (e.g., corresponding to vertical sub-block VSB0wordlines WLL0-WLL31) from a second set of memory cell transistors within the memory string (e.g., corresponding to the vertical sub-block VSB1wordlines WLL32-WLL63) during a memory operation (e.g., an erase operation or a programming operation).

In another embodiment, one or more middle junction transistor layers are used to divide the stack435into vertical sub-blocks. A middle junction transistor layer contains junction transistors, which do not necessarily contain a charge storage region. Hence, a junction transistor is typically not considered to be a dummy memory cell. Both a junction transistor and a dummy memory cell may be referred to herein as a “non-data transistor.” A non-data transistor, as the term is used herein, is a transistor on a NAND string, where the transistor is either configured to not store user or system data or operated in such a way that the transistor is not used to store user data or system data. A wordline that is connected to non-data transistors is referred to herein as a non-data wordline. Examples of non-data wordlines include, but are not limited to, dummy wordlines, a select line in a middle junction transistor layer, or the like.

The stack435may have more than three vertical sub-blocks. For example, the stack435may be divided into four, five, or more vertical sub-blocks. Each of the vertical sub-blocks may contain at least one data memory cell. In some embodiments, additional layers similar to the middle dummy wordline layers DWLM may be provided to divide the stack435into the additional vertical sub-blocks. In one embodiment, the stack has two vertical sub-blocks.

FIG.4Ddepicts an alternative view of the SG layers and wordline layers of the stack435ofFIG.4C. Each of SGD layers SGD0and SGD0(the drain side SG layers) includes parallel rows of SG lines associated with the drain side of a set of NAND strings. For example, SGD0includes drain side SG regions420,430,440and450, consistent withFIG.4B. Below the SGD layers are the drain side dummy wordline layers. In one implementation, each dummy wordline layer represents a wordline that is connected to a set of dummy memory cells at a given height in the stack. For example, DWLD0includes wordline layer regions451,453,455and457. A dummy memory cell, also referred to herein as a non-data memory cell, does not store data and is ineligible to store data, while a data memory cell is eligible to store data. Moreover, the threshold voltage Vth of a dummy memory cell is generally fixed at the time of manufacture or may be periodically adjusted, while the Vth of the data memory cells changes more frequently, e.g., during erase and programming operations of the data memory cells.

Below the dummy wordline layers are the data wordline layers. For example, WLL95comprises wordline layer regions471,472,473and474. Below the data wordline layers are the source side dummy wordline layers. Below the source side dummy wordline layers are the SGS layers. Each of the SGS layers SGS0and SGS1(the source side SG layers) includes parallel rows of SG lines associated with the source side of a set of NAND strings. For example, SGS0includes source side SG lines475,476,477and478. In some embodiments, each SG line is independently controlled, while in other embodiments, the SG lines are connected and commonly controlled.

FIG.4Edepicts a view of the region445ofFIG.4C. Data memory cell transistors520and521are above dummy memory cell transistor522. Below dummy memory cell transistor522are data memory cell transistors523and524. A number of layers can be deposited along the sidewall (SW) of the memory hole444and/or within each wordline layer, e.g., using atomic layer deposition. For example, each column (e.g., the pillar which is formed by the materials within a memory hole) can include a blocking oxide/block high-k material470, charge-trapping layer or film463such as SiN or other nitride, a tunneling layer464, a polysilicon body or channel465, and a dielectric core466. A wordline layer can include a conductive metal462such as tungsten as a control gate. For example, control gates490,491,492,493and494are provided. In this example, all of the layers except the metal are provided in the memory hole. In other approaches, some of the layers may be in the control gate layer. Additional pillars can be similarly formed in the different memory holes. A pillar can form a columnar active area (AA) of a NAND string.

When a data memory cell transistor is programmed, electrons are stored in a portion of the charge-trapping layer which is associated with the data memory cell transistor. These electrons are drawn into the charge-trapping layer from the channel, and through the tunneling layer. The Vth of a data memory cell transistor is increased in proportion to the amount of stored charge. During an erase operation, the electrons return to the channel.

Non-data transistors (e.g., select transistors, dummy memory cell transistors) may also include the charge trapping layer463. For example, inFIG.4E, dummy memory cell transistor522includes the charge trapping layer463. Thus, the Vth of at least some non-data transistors may also be adjusted by storing or removing electrons from the charge trapping layer463. However, it is not required that all non-data transistors have an adjustable Vth. For example, the charge trapping layer463is not required to be present in every select transistor.

Each of the memory holes can be filled with a plurality of annular layers comprising a blocking oxide layer, a charge trapping layer, a tunneling layer, and a channel layer. A core region of each of the memory holes is filled with a body material, and the plurality of annular layers are between the core region and the WLLs in each of the memory holes. In some cases, the tunneling layer464can comprise multiple layers such as in an oxide-nitride-oxide configuration.

FIG.4Fis a schematic diagram of a portion of the memory depicted inFIGS.3-4E.FIG.4Fshows physical wordlines WLL0-WLL95running across the entire block. The structure ofFIG.4Fcorresponds to portion306in Block2ofFIGS.4A-E, including bitlines411,412,413,414, . . .419. Within the block, each bitline is connected to four NAND strings. Drain side selection lines SGD0, SGD1, SGD2and SGD3are used to determine which of the four NAND strings connect to the associated bitline(s). Source side selection lines SGS0, SGS1, SGS2and SGS3are used to determine which of the four NAND strings connect to the common source line. The block can also be thought of as divided into four horizontal sub-blocks HSB0, HSB1, HSB2and HSB3. Horizontal sub-block HSB0corresponds to those vertical NAND strings controlled by SGD0and SGS0, horizontal sub-block HSB1corresponds to those vertical NAND strings controlled by SGD1and SGS1, horizontal sub-block HSB2corresponds to those vertical NAND strings controlled by SGD2and SGS2, and horizontal sub-block HSB3corresponds to those vertical NAND strings controlled by SGD3and SGS3.

FIG.4Gis a schematic of horizontal sub-block HSB0. Horizontal sub-blocks HSB1, HSB2and HSB3may have similar structures.FIG.4Gshows physical wordlines WL0-WL95running across the entire sub-block HSB0. All of the NAND strings of sub-block HSB0are connected to SGD0and SGS0. For ease of depiction,FIG.4Gonly depicts six NAND strings501,502,503,504,505, and506; however, horizontal sub-block HSB0may have thousands of NAND strings (e.g., 15,000 or more).

FIG.4Gis being used to explain the concept of a selected memory cell. A memory operation is an operation designed to use the memory for its purpose and includes one or more of reading data, writing/programming data, erasing memory cells, refreshing data in memory cells, and the like. During any given memory operation, a subset of the memory cells will be identified to be subjected to one or more parts of the memory operation. These memory cells identified to be subjected to the memory operation are referred to as selected memory cells. Memory cells that have not been identified to be subjected to the memory operation are referred to as unselected memory cells. Depending on the memory architecture, the memory type, and the memory operation, unselected memory cells may be actively or passively excluded from being subjected to the memory operation.

As an example of selected memory cells and unselected memory cells, during a programming process, the set of memory cells intended to take on a new electrical characteristic (or other characteristic) to reflect a changed programming state are referred to as the selected memory cells, while the memory cells that are not intended to take on a new electrical characteristic (or other characteristic) to reflect a changed programming state are referred to as the unselected memory cells. In certain situations, unselected memory cells may be connected to the same wordline as selected memory cells. Unselected memory cells may also be connected to different wordlines than selected memory cells. Similarly, during a reading process, the set of memory cells to be read are referred to as the selected memory cells, while the memory cells that are not intended to be read are referred to as the unselected memory cells.

To better understand the concept of selected memory cells and unselected memory cells, assume a programming operation is to be performed and, for example purposes only, that wordline WL94and horizontal sub-block HSB0are selected for programming (seeFIG.4G). That means that all of the memory cells connected to WL94that are in horizontal sub-blocks HSB1, HSB2and HSB3(the other horizontal sub-blocks) are unselected memory cells. Some of the memory cells connected to WL94in horizontal sub-block HSB0are selected memory cells and some of the memory cells connected to WL94in horizontal sub-block HSB0are unselected memory cells depending on how the programming operation is performed and the data pattern being programmed. For example, those memory cells that are to remain in the erased state (e.g., state S0) will be unselected memory cells because their programming state will not change in order to store the desired data pattern, while those memory cells that are intended to take on a new electrical characteristic (or other characteristic) to reflect a changed programming state (e.g., programmed to states S1-S7) are selected memory cells. Looking atFIG.4G, assume for example purposes, that memory cells511and514(which are connected to wordline WL94) are to remain in the erased state; therefore, memory cells511and514are unselected memory cells (labeled unset inFIG.4G). Additionally, assume, for example purposes, that memory cells510,512,513and515(which are connected to wordline WL94) are each to be programmed to a respective one of data states S1-S7; therefore, memory cells510,512,513and515are selected memory cells (labeled sel inFIG.4G).

FIG.5is a block diagram of an example configuration of a sense block500, which may be representative of one of the sense blocks232(FIG.1). The sense block500may include a plurality of sense circuits504and a plurality of sets of latching circuits506. For example, there can be 16 k sets of sense circuits504and latching circuits506. In other example embodiments, there can be a set of sense circuits504and a respective latching circuit506for each memory cell in a memory array, for example. In some embodiments, each sense circuit504(which may also include sense amplifier circuitry) may be associated with a respective one of the latching circuits506. That is, each sense circuit504may be configured to communicate with and/or perform a sense operation using data and/or storing data into its associated latching circuit506.

Additionally, the sense block500may include a sense circuit controller508that is configured to control operation of the sense circuits504(and/or the sets of latches506) of the sense block500. As described in further detail below, the sense circuit controller508may control operation of the sense circuits504and the latches506by outputting control signals to terminals of the sense circuits504and the latches506. The sense circuit controller508may be implemented in hardware, firmware, software, or combinations thereof. For example, the sense circuit controller508may include a processor that executes computer instructions stored in a memory to perform at least some of its functions. Controller508can be configured with various modules to perform one or more functions. Each module may include one or more instructions for execution of logic of one or more circuits described herein. For example, instructions may include instructions for generating one or more signals or sensing one or more voltage levels. Instructions may further include instructions for executing any of the steps of any of the methods disclosed herein. The controller508may send messages and receive data, including program code, through one or more communication interface(s). The received code may be executed by a processor of the controller508as it is received, and/or stored in a storage device, or other non-volatile storage for later execution.

Sense circuits504described herein can be coupled to bitlines and/or wordlines. Bitline connection circuit502is depicted inFIG.5as part of sense block500. It should be appreciated, however, that the bitline connection circuit502may be, more generally, part of read/write circuit128. Bitline connection circuit502may be configured to electrically connect and disconnect the ith bitline BL(i) from the sensing circuit504(and the latching circuit506). In the case of a 3D NAND architecture, the ith bitline BL(i) may be connected to a respective memory hole from each NAND string of each NAND block of the 3D structure. In the case of a 2D NAND architecture, the ith bitline BL(i) may be connected to an associated NAND string. The ith bitline BL(i) may be one of a plurality bitlines and the NAND string may be one of a plurality of NAND strings included in a memory cell structure of a memory die. The NAND string can include one or more memory cells. For a read operation, a target memory cell can be a memory cell from which data is to be read, and thus, for which a sense operation is performed. For a verification operation, a target memory cell can be a memory cell being programmed in an associated program-verify operation.

When the bitline connection circuitry502connects the ith bitline BL(i) to the sensing circuit504(e.g., for a sense operation), current may flow from the sense circuit504to the ith bitline BL(i). Alternatively, when the bitline connection circuitry502disconnects the ith bitline BL(i) from the sense circuit504, current may be prevented from flowing from the sensing circuit504to the ith bitline BL(i). Bitline connection circuit502may include a bitline biasing circuit configured to bias the ith bitline BL(i) by generating a bitline bias voltage at a bitline bias node. The amount of the bitline bias voltage may depend on whether the ith bitline BL(i) is a selected bitline or an unselected bitline. In particular, when the ith bitline BL(i) is a selected bitline, the bitline biasing may allow the bitline bias voltage at the high supply voltage level or a level corresponding to the high supply voltage, and when the ith bitline BL(i) is an unselected bitline, the bitline biasing circuit may generate the bitline bias voltage at the cell source voltage level or a level corresponding to the cell source voltage.

Sensing circuits504described herein can include a pre-charge circuit path configured to pre-charge one or more sense node(s) with a voltage at a pre-charge level during a sense operation. A latching circuit506, in response to receiving a control signal at a high voltage level at a first transistor of the latch circuit506, can enable a pre-charge circuit path to pre-charge the sense node with the voltage at the pre-charge level.

FIG.6is a block diagram of example memory system600that depicts more details of one embodiment of memory die104a. With reference toFIG.2Babove, the memory die104ais connected to the storage controller102via a memory interface224and operates based on commands from the storage controller102. For example, the memory die104atransmits and receives, for example, 8-bit signals DQ0to DQn (hereinafter simply referred to as signals DQ or signals DQ [n:0], where n is an integer of the number of lines) to and from the storage controller102. In various embodiments, the number of DQ signals may be 7, thus DQ [n:0] may be DQ[7:0]. The signals DQ [n:0] may include, for example, data, address codes, and command codes. The memory die104areceives, for example, a chip enable signal (CEn), a command latch enable signal (CLE), an address latch enable signal (ALE), a write enable signal (WEn), and a read enable signal (REn) from the storage controller102. Then, the memory die104atransmits a ready/busy signal (R/Bn) to the storage controller102.

The chip enable signal CEn is a signal for enabling the memory die104aand is asserted, for example, at a logic LOW level. The CLE signal is a signal indicating that the DQ signal is encoded with a command code (also referred to as CMD) and is asserted, for example, at a logic HIGH level. The ALE signal is a signal indicating that the signal DQ is encoded with an address code (also referred to as ADDR) and is asserted, for example, at the logic HIGH level. The WEn signal is a clock signal for sampling a received signal in the memory die104a. For example, a received signal is sampled and latched at each rising or falling edge of the WEn signal to obtain a bit pattern encoded into the received signal. Accordingly, a signal DQ is received in the memory die104awhen the WEn signal is toggled. The REn signal is a signal used for the storage controller102to read data from the memory die104a. For example, data is read out of the memory die104aat each rising or falling edge of the REn signal. Accordingly, the memory die104aoutputs the signal DQ to the storage controller102based on the toggled REn signal. The R/Bn signal is a signal indicating whether the memory die104ais in a busy state or a ready state (in a state in which a command is not receivable or receivable from the storage controller102) and is considered to be at the logic LOW level, for example, when the memory die104ais in the busy state.

The storage controller102issues a read command, a write command, an erasing command, or the like to the memory die104ain response to a command from a host device (e.g., host device106and/or112). The storage controller102manages a memory space of the Memory die104a.

As described above, the memory interface circuit234connects to the input/output circuit222via a plurality of pins (also referred to as electrical contact pads) the memory interface224. For example, the storage controller102includes a plurality of pins680a-nthat are connected to a plurality of pins682a-nof the memory die104a. The memory interface circuit234transmits the CEn signal, CLE signal, ALE signal, and WEn signal to the memory die104avia control bus226of the memory interface and transmits DQ [n:0] signals via the data bus228of the memory interface234. The input/output circuit222transmits the R/Bn signal to the storage controller102via the control bus226and the DQ [n:0] signals via the data bus228.

As illustrated inFIG.6, the memory die104aincludes an input and output circuit662, a logic control circuit664, a status register666, an address register668, a command register670, a sequencer672, a ready/busy circuit674, a voltage generation circuit676, and a data register678. The various components662-678may be included comprised as part of the die controller204, for example, as part of the control circuit214and/or decoder circuit216.FIG.6also illustrates the memory structure206, row decoder210, a sense blocks232, and column decoder212, as described above in connection withFIG.2B.

The input and output circuit662controls input and output of the signal DQ to and from the storage controller102. For example, the input and output circuit662transmits data received from the storage controller102as DIN to data register678, transmits an address code to the address register668, and transmits a command code to the command register670. The input and output circuit662also transmits status information STS received from the status register666, data received from the data register678to be transmitted to the storage controller102as DOUT, and an address code received from the address register668to the storage controller102. STS, DOUT, and the address are transmitted as signals DQ encoded with a bit pattern for the STS, DOUT, or address. The input and output circuit662and the data register678are connected via a data bus. For example, the data bus includes eight I/O data lines IO0to IO7corresponding to the 8-bit signals DQ0to DQ7. The number of I/O data lines is not limited to eight, but may be set to 16, 32, or any number of data lines.

The logic control circuit664receives, for example, the CEn signal, the CLE signal, the ALE signal, the WEn signal, and the REn signal from the storage controller102via control bus226. Then, logic control circuit664controls the input and output circuit662and the sequencer672in accordance with a received signal.

The status register666temporarily stores status information STS, for example, in a write operation, a read operation, and an erasing operation for data and notifies the storage controller102whether the operation normally ends.

The address register668temporarily stores the address code received from the storage controller102via the input and output circuit662. For example, the input and output circuit662may detect a signal DQ and sample the signal according to the WEn signal to obtain a bit pattern encoded thereon. The input and output circuit662may then decode the bit pattern to obtain the data, which in this case may be an address code. The address code is then temporarily stored in the address register668. Then, the address register668transmits a row address (row addr) to the row decoder210and transmits a column address (col addr) to the column decoder212. In various embodiments, the address code may include row and column, as well as a wordline selection, memory block selection, memory string selection, plane selection and die selection. Each of which are transmitted by the address register668to the row decoder210and/or the column decoder212.

The command register670temporarily stores the command code received from the storage controller102via the input and output circuit662and transmits the command CODE to the sequencer672. For example, the input and output circuit662may detect a signal DQ and sample the signal according to the WEn signal to obtain a bit pattern encoded thereon. The input and output circuit662may then decode the bit pattern to obtain the data, which in this case may be a command code. The command code is then temporarily stored in the command register670.

The sequencer672controls operation of the memory die104a. For example, the sequencer672controls the status register666, the ready/busy circuit674, the voltage generation circuit676, the row decoder210, the sense blocks232, the data register678, the column decoder212, and the like according to a command code stored in the command register670to execute the write operation, the read operation, and the erasing operation according to the code.

The ready/busy circuit674transmits the R/Bn signal to the storage controller102according to an operation state of the sequencer672. For example, the R/Bn signal is transmitted to the storage controller102via the control bus626of the memory interface624.

The voltage generation circuit676generates a voltage necessary for an operation (e.g., a write operation, a read operation, or an erasing operation) according to control of the sequencer672. The voltage generation circuit676supplies the generated voltage, for example, to the memory structure206, the row decoder210, and the sense blocks232. The row decoder210and the sense blocks232apply a voltage supplied from the voltage generation circuit676to memory cells in the memory structure206. Details of the memory structure206are provided in connection withFIGS.3-4Gabove.

The data register678includes a plurality of latch circuits. The latch circuit stores the write data WD and the read data RD. For example, in a write operation, the data register678temporarily stores the write data WD received from the input and output circuit662and transmits the write data WD to the sense blocks232. For example, in a read operation, the data register678temporarily stores the read data RD received from the sense blocks232and transmits the read data RD to the input and output circuit662.

Furthermore, a test interface684(also referred to as a by 1 or X1 interface) may be used to execute die (or chip) level performance testing tasks, according to a testing protocol (as described in connection withFIG.7below) during manufacture, prior to packaging and shipment for sale to consumers. For example, an X1 interface was conventionally used in wafer sort testing. More particularly, the X1 interface may be used to test any properties of the memory die (e.g., wafer) needed at wafer sort, such as, but not limited to, trimming operations of all the voltage generators in the memory device; data latch testing; wordline, string, block, and plane memory array testing with each erase/program/read mode in order to decide whether there are bad wordlines or memory blocks; or column related testing in order to enable column redundancy settings. In conventional implementations, wafer sort testing requires probe cards and testers that only access the X1 protocol on the X1 interface. This is required so that the tester, probe cards will not touch down on pins designated for user data, such as IO[n:0], ALE, CLE, etc. Thus, the X1 interface make it much cheaper for manufacturing testing.

The memory die104aincludes a designated test control circuit686that is connected to the storage controller102via the test interface684. The test control circuit686is separate and distinct from the logic control circuit664and contains the probe cards and testers for performing the test protocol on the test interface684. While the memory interface224includes multiple buses for different data (e.g., a control bus for command/address sequencing, a data bus for DIN/DOUT data operations, etc.), the test interface684comprises a single bus (referred to herein as a test data bus) on which all data is exchanged. For example, command/address sequencing, along with all data operations are performed on the single test data bus. While the signal lines and associated pins have been generally used only for testing prior to public sale, the memory die104ais shipped with the interface and pins present but unused for consumer data.

The storage controller102may transmit and receive signals according to the testing protocol over the test data bus of the test interface684. For example, the storage controller102may transmit a monitoring voltage (VMON) signal for enabling or otherwise triggering the testing protocol on the memory die104aand is asserted, for example, at a logic HIGH level. The storage controller102transmits the VMON signal to the memory die104avia the control bus226of the test interface684. For command/address sequencing and DIN/DOUT operations between the memory die104aand the storage controller102, a single data line X1DQ is used to provide a 1-bit X1DQ signal for all data exchanges between the storage controller102and the test control circuit686of the memory die104a. Under the testing protocol, the eight data lines IO0to IOn are not utilized. The X1DQ signal (also referred to herein as a 1-bit I/O data signal) may include, for example, DIN/DOUT, addresses, and commands. For example, the X1DQ signal may be encoded to indicate the CEn signal, CLE signal, ALE signal, RE signal, data signals, command signals, and address signals, each signal serially provided in a 1-bit sequence, over the X1DQ signal. The test control circuit686then applies the test protocol to the received signal in order to decipher what data is coming in and/or out, for example, whether the data is a command, an address, DIN/DOUT, etc. Then, the test control circuit686controls input and output of data and the sequencer672in accordance with a received signal. The storage controller102also transmits a 1-bit SKn signal, which is a clock signal for sampling a received signal in (e.g., write into the memory die104a) and reading data from the memory die104a. The SKn signal is asserted, for example, at the logic LOW level when a command, an address, data, or the like is received from the storage controller102.

The test interface684may be a portion of the memory interface234corresponding to a subset of pins682and680, as shown inFIG.6. For example, memory die104aincludes pins682c,682d, and682eof the test control circuit686for connecting to pins680c,680d, and680eof the storage controller102. Thus, the memory interface circuit234transmits the VMON signal, SKn signal, X1DQ signals via the test data bus of the test interface284to the test control circuit686.

FIG.7illustrates example timing diagrams710and720of signals associated performance testing of the memory device200. Timing diagram710illustrates an example test write operation performed on a memory die104aand timing diagram720illustrates an example test read operation performed on memory die104a. Timing diagrams710and720include a plurality of signals for performing the respective operations exchanged over a test interface (e.g., test interface684ofFIG.6), which include a VMON signal702, an SKn signal704, X1DQ data signal712, and X1DQ data signal722. The X1DQ data signal712and X1DQ data signal722may be representative of signals on the same test bus or lines, one in the case of the write operation of diagram710and one in the case of the read operation of diagram720. The timing diagram710is divided into a mode select protocol portion714and a data input protocol portion716. The timing diagram720is similarly divided into a mode select protocol portion724, which is the same as mode select protocol portion714, and data output protocol portion726.

The testing protocol starts with the storage controller102asserting VMON at the logic HIGH level, to trigger the testing protocol and notify the memory die104athat performance testing is to be performed over the test interface. As illustrated inFIG.7, once triggered and during the mode select protocol portion714, the storage controller transmits a mode select signal encoded with a first bit pattern as a 1-bit data sequence on the X1DQ signal712. The first bit pattern includes a bit for asserting each of a plurality of control signals, asserted as logic HIGH or logic LOW levels, to notify the memory die104aof a selected mode and inform the memory die104athat a bit pattern in the input/output protocol portion716is encoded with a control signal for the selected mode. The memory die104adetects the mode select signal and samples the mode select signal according to the SKn signal704to obtain the first bit pattern. The memory die104athen decodes the first bit pattern as a control signal of the selected mode. Example, modes include, but are not limited to, CEn, CLE, ALE, RE, to name a few. For example, to indicate a command cycle, an example first bit pattern encoded into the X1DQ signal712is 0100, where for the first bit at logic LOW level for the CEn mode; the second bit at logic HIGH level for the CLE; and the bits at logic LOW level for ALE, and RE. Other bits may be set to indicate other modes as desired for testing the memory die104a.

After the mode select protocol portion714, the storage controller then generates a data signal on the X1DQ signal712encoded with a second bit pattern of data for the selected mode. For example, The memory die104adetects the data signal and samples the data signal according to the SKn signal704to obtain the second bit pattern. The memory die104athen decodes the second bit pattern as the data for the selected mode.

Which portion714(or724) or716(726) of the testing protocol is indicated by the SKn signal704. For example, the two consecutive bits of on the SKn signal704may be utilized to indicate change between portion714and portion716(or portions724and726). In the case of the mode select protocol portion714(or724), two consecutive bits at logic HIGH level may indicate to the test control circuit686that data on the X1DQ signal712(or722) is encoded with the first bit pattern for mode selection. Then consecutive bits at logic LOW level on the SKn signal702may indicate the mode selection protocol is complete. In the case of input/output protocol portion716or726, a first bit on the SKn signal702at logic HIGH level followed by a consecutive bit at logic LOW level may indicate to the test control circuit686that data on the X1DQ signal712(or722) is encoded with the second bit pattern of data for the selected mode.

An example CLE mode will be provided here. For example, during the mode select protocol portion714, the storage controller generates a mode select signal encoded with a first bit pattern to instruct the memory die104ato enter a CLE mode. In this case, the first bit pattern may assert a second bit as logic HIGH level, while asserting the other bits as logic LOW level. The mode select signal is transmitted from the storage controller102to the memory die104avia the test data bus of the test interface684. The memory die104adetects the X1DQ signal and, at each rising or falling edge of the SKn signal704, samples and latches a bit value in the mode select signal to obtain the first bit pattern. The memory die104a(e.g., at the control circuit214) decodes the first bit pattern to identify that CLE mode is selected. During the input/output protocol portion716, the storage controller generates a data signal encoded with a second bit pattern that is a command code. For example, the storage controller102may encode bits D0-D7of the data signal as 00000000 for command code 00 h, 00110000 for command code 30 h, and 10101010 for command code 55 h, to name a few examples. As introduced above and shown inFIGS.7A and7B, there are is a two cycle header (e.g., used to indicate which portion of the test protocol is currently implemented) and a dummy cycle, which total 11 cycles of the SKn signal702. The data signal is transmitted from the storage controller102to the memory die104avia the test data bus of the test interface684. The memory die104adetects the X1DQ signal and, at each rising or falling edge of the SKn signal704, samples and latches a bit value in the data signal to obtain the second bit pattern. The memory die104a(e.g., at the control circuit214) decodes the second bit pattern to retrieve the command code. The command code is then processed as set forth above in connection withFIG.6, for example, by storing the command code in the command register670.

An example ALE mode will now be provided. For example, during the mode select protocol portion714, the storage controller generates a mode select signal encoded with a first bit pattern to instruct the memory die104ato enter an ALE mode. In this case, the first bit pattern may assert a third bit as logic HIGH level, while asserting the other bits as logic LOW level. The mode select signal is transmitted from the storage controller102to the memory die104avia the test data bus of the test interface684. The memory die104adetects the X1DQ signal and, at each rising or falling edge of the SKn signal704, samples and latches a bit value in the mode select signal to obtain the first bit pattern. The memory die104a(e.g., at the test control circuit686) decodes the first bit pattern to identify that ALE mode is selected. During the input/output protocol portion716, the storage controller generates a data signal encoded with a second bit pattern that is an address code. For example, the storage controller102may encode bits D0-D7of the data signal as 00100000 for the first bit pattern, as an address code to select a wordline1of string0. The data signal is transmitted from the storage controller102to the memory die104avia the test data bus of the test interface684. The memory die104adetects the X1DQ signal and, at each rising or falling edge of the SKn signal704, samples and latches a bit value in the data signal to obtain the second bit pattern. The memory die104a(e.g., at the control circuit214) decodes the second bit pattern to retrieve the address code. The address code is then processed as set forth above in connection withFIG.6, for example, by storing the address code in the address register668.

Conventionally, the testing protocol, using the test interface and associated pins, is implemented only during manufacture for chip and memory system verifications, prior to packaging for shipment for sale and consumer use. Traditionally, these pins and related test interface is not used for data operations related to consumer user data or control signals for effectuating these data operation. Instead, the control signals and data are transmitted and received using the CEn, CLE, ALE, WEn, REn, and DQ signals.

FIGS.8and8Billustrate an example timing diagram800of signals associated with a read command from a memory device. Timing diagram800depicts an example DOUT operation (e.g., read operation) performed on a memory device (e.g., memory device200) based on one or more signals exchanged between a controller (e.g., storage controller102) and a memory die (e.g., memory die104a) via a memory interface (e.g., memory interface230). Timing diagram800includes a plurality of signals for performing the DOUT operation, which includes an active-low chip enable (CEn) signal802, an active-high command latch enable (CLE) signal804, an active-high address latch enable (ALE) signal806, an active-low write enable (WE) signal808, an active-low read enable (REn) signal810, an active-high read enable (RE) signal812, an active-high data strobe (DQS) signal814, an active-low data strobe (DQS) signal816, an I/O data signal818, and a ready/busy (R/Bn) signal820.

In the illustrative example ofFIGS.8A and8B, the memory die executes a read operation822based on a command received from the storage controller. The read operation822comprises a cell read operation824during which data is read from a memory cell of the memory die and a register (or cache) read operation826during which data is read from a register.

First, as illustrated inFIGS.8A and8B, the storage controller102transmits a cell read command in the form of a bit pattern clocked with respect to the WEn signal808, which the memory die104adecodes to a command code and an address code (e.g., an address of the cell from which data is to be read). The period of the WEn signal808is “tWC”. For example, the storage controller asserts the CLE signal804to the logic HIGH level to notify the memory die that a command code is being transmitted. The storage controller transmits a page control command code, such as command code “01 h/02 h/03 h”, where 01 h is a lower page, 02 h is a middle page, and 03 h is an upper page. The storage controller then transmits a bit pattern on the I/O signal818encoded with a command code, which the memory die104adetects and samples according to the WEn signal808to obtain command code “00 h” to notify the memory die to execute the cell read command. The command code is latched into a command register (e.g., command register670ofFIG.6).

The storage controller also asserts the ALE signal806to the logic HIGH level (and asserts the CLE signal804to logic LOW level) and transmits the address of the memory cell on the I/O signal818as a bit pattern encoded with an address code. The memory die detects the signal, samples the signal according to the WEn signal808to obtain the bit pattern, and decodes the bit pattern to obtain the address code. The address code is latched into an address register (e.g., address register668ofFIG.6). In the example ofFIGS.8A and8B, the row address (Row addr) is transmitted by three cycles after the column address (Col addr) is transmitted by two cycles. However, any number of cycles may be used for providing the column address and the row address.

Subsequently, the storage controller asserts the CLE signal804to the logic HIGH level and the transmits a cell read command “30 h” encoded into a bit pattern. The command code “30 h” instructs the memory die to execute the cell read operation using the address code stored on the address register. At this time, the R/Bn signal820set to the logic LOW level (e.g., busy state). A sense circuit of the sense block (e.g., a sense block232) reads the data from the memory cell corresponding to the address code from the address register. The sense circuit subsequently transmits the read data to a data register (e.g., data register678ofFIG.6). The period in which the sense circuit starts the reading of the data from the memory cell and ends the transmission of the read data to the data register is shown a “tR”. The R/Bn signal820is set at the logic LOW level during the period tR.

When the storage controller confirms that the R/Bn signal820returns to the logic high level (e.g., ready state), the storage controller transmits a register read command to the memory die. For example, the storage controller asserts the CLE signal804to the logic HIGH level and transmits a command code “05 h”, on the I/O signal818, to the memory die to notify the memory die to execute the register read operation. The storage controller asserts the ALE signal806to the logic HIGH level and transmits the address code on the I/O signal818. In the example ofFIGS.8A and8B, the row address (Row addr) is transmitted by three cycles after the column address (Col addr) is transmitted by two cycles. However, any number of cycles may be used for providing the column address and the row address. Subsequently, the storage controller asserts the CLE signal804to the logic HIGH level and transmits a register read command “E0 h” to instruct the memory die to execute the register read operation.

The memory die starts the register read operation according to the register read command code “E0 h”. For example, the storage controller transmits the REn signal810with the logic LOW level after a waiting period tWHR1elapses from rising edge of the WEn signal808(e.g., from logic LOW level to logic HIGH level) corresponding to the command “E0 h”. The memory die then starts reading of the data from the register and, after a waiting period tWHR2elapses, starts transmitting the read data as DOUT, on the I/O signal818, to the storage controller clocked according to the DQS signal814. Waiting period tWHR2is a period of time that the memory die104a(e.g., input and output circuit662) takes to decode command code “E0 h” and for the memory die104ato fetch data from a cache buffer (e.g., data register678) over pipeline states due to such cache buffers being some distance from the pins (e.g., pins682a-682bfor the DQ signal ofFIG.6). For example, internal logic needs to be enabled, initial column address needs to be decoded and deciphered whether column redundancy replacement had occurred on specific column, and then moving data from the requested plane, column through the pipeline. Then when the RE signal toggles, data will be available immediately from last stage of pipeline to pins of the DQ signals. The embodiments herein utilize the X1 interface and protocol as described herein, which provides a benefit to hide this type of overhead while DQ signal is used for DIN/DOUT operations.

The total register read time is amount of time to perform register (or cache) read operation826plus the amount of time to transmit DOUT to the storage controller. That is, the total register read time is the sum of the period from the falling edge of the WEn signal808corresponding to the command code “05 h” to the rising edge of the WEn signal808corresponding to the command code “E0 h”, the waiting period tWHR2, and the time period to transmit DOUT to the storage controller “tDOUT” (also referred to herein as data toggle out time). The period from the falling edge of the WEn signal808corresponding to the command code “05 h” to the rising edge of the WEn signal808corresponding to the command code “E0 h” may correspond to the period of the WEn signal808tWCmultiplied by a multiplier, which is an integer equal to the number of cycles of the WEn signal808required to complete the register read operation826. That is, with reference to the example inFIGS.8A and8B, the register read time of timing diagram800is tWC×7+tWHR2+tDOUT, where seven cycles of the WEn signal808are required to complete the register read operation826.

As an illustrative example, tWCmay be 10 ns and the waiting period tWHR2may be 300 ns. The example values for tWCand tWHR2are merely used as examples of the current state of the art. Other values would be equally applicable. In this example case, the total register read time is 370 ns plus the data toggle out time tDOUT. The data toggle out time tDOUTis based on the size of the data and the data I/O speed corresponding to a Toggle Mode. Table 1 below illustrates example data toggle out times tDOUTin ns for three data sizes and three Toggle Modes, where the number following TM indicates the number of megabytes per second for processing DIN/DOUT operations.

TM1600TM3200TM48004K byte2867143495616K byte114685734382364K byte458732293615291

The total register read time is a critical performance indicator of the memory device. Performance and speed considerations of data read operations are generally gauged based on the register read time, opposed to the entire read operation time (e.g., entire time for read operation820). That is, the time from command code “05 h” to code “E0 h” is generally used to gauge the performance of the read operation. This is because, read out from the memory cell to the register during time tris significantly longer and will dominate the time period. Read out from the memory cell is an operation internal to the memory die (e.g., from memory structure to command and/or address register), which is not dispositive of the speed of at the memory interface (e.g., the I/O signals and/or control signals). I/O speeds continue to increase, but similar increases have not occurred on the command/address sequencing. Thus, evaluating the register read time as set forth above is representative of the performance of the command/address sequencing of the memory device.

Additionally, once command code “30 h” is issued and the memory die is busy, the DQ signal818can be used to issue command/address codes to other dies, while the current memory die104ais sensing from memory array. This not possible during between the command codes “05 h” and “E0 h.” The codes “05 h” to “E0 h” to data streaming out requires atomic sequence control. Thus, the storage controller cannot issue 05 h-address-E0 h and perform other sequence to another memory die or same memory die for a different operation, and then come back to stream out data. In this case, the overhead of command/address sequencing and tWHR2is visible and gates the data bus usage for memory device.

FIGS.8A and8Bdepict command and address sequencing that require use of I/O signals818(e.g., over the data bus228of memory interface224) to provide command/address information to a memory device. As such, when command or address information is received on the data bus, DIN/DOUT operations cannot be performed on the data bus. Thus, even as DIN/DOUT speeds increase, the command and address sequences depicted inFIGS.8A and8Bremain a bottleneck for system performance because they utilize the same data bus to send command and address information to a memory device as DIN/DOUT operations use to provide data to and/or receive data from the memory device.

Accordingly, embodiments herein separate the command/address sequencing from the data bus, I/O signals, and related data I/O pins. Embodiments herein provide commands and address sequencing for read/write operations using a test data bus that is separate from the data bus used for a DIN/DOUT operation for read/write operations. Furthermore, using separate bus and data signal frees up the data bus for DIN/DOUT operations. Thus, command/address sequencing can be performed in the background, parallel, and simultaneously with DIN/DOUT operations, which reduces overall data processing overhead by hiding command/address sequencing processing overhead in the background. For example, referring to the above example, the 370 ns of overhead for performing the register read operation826plus other overhead for the rest of operation822may be hidden during a multi-die data operation (examples of which are described below in connectionFIGS.9-12). That is, the command/address sequencing for a first read/write operation and its corresponding overhead may be performed on a first memory die, while a DIN/DOUT operation for a second read/write operation is be performed on a second memory die. Subsequently, the first memory die can perform a DIN/DOUT operation corresponding to the first read/write operation. Further, the second memory die may perform command/address sequencing for a third read/write operation, while the first memory die is performing the DIN/DOUT operation for the first read/write operation. Thus, embodiments of the disclosed technology may perform command/address sequencing corresponding to a next read/write operation for a first memory die in parallel with performing a DIN/DOUT operation corresponding to a current read/write operation for a second memory die.

FIG.9is a block diagram of example memory system900for multi-memory die data operations, in accordance with embodiments of the disclosed technology. The memory system900, which is substantially similar to memory system100ofFIG.1, includes a storage controller930, a first memory array902, and a second array904. The storage controller930is substantially similar to storage controller102ofFIG.1except as provided below. The first and second memory arrays902and904may be substantially similar to the memory array202ofFIG.2B. Thus, each memory array902and904comprises a plurality of memory dies910and920, respectively. The following description is made with reference to each memory die in the singular; however, the disclosure herein applies equally to each memory die of a respective memory array. Thus, as used herein, memory die910may refer to any one of the memory dies of the memory array902and memory die920may refer to any one of the memory dies of the memory array904. Each memory die910and920is substantially similar to the memory die104adescribed in connection withFIGS.2A-8B, except as provided below.

Referring to memory die910, a I/O circuit911of the memory die910is connected to a memory interface circuit940(e.g., memory interface circuit234ofFIG.2B) of the storage controller930via a memory interface919(e.g., memory interface224ofFIGS.2A and2B) and operates based on commands from the storage controller930. For example, the memory die910transmits and receives, for example, 8-bit signals DQ [7:0] to and from the storage controller930, for example, similar to the I/O circuit222ofFIG.2A. In various embodiments, the signals DQ [7:0] include DIN/DOUT. The memory die910transmits and receives, for example, a 1-bit signal X1DQ to and from the storage controller, for example, similar to the test control circuit686ofFIG.6. In various embodiments, the signal X1DQ includes command and address used for command/address sequencing. Additionally, the memory die910receives, for example, an active-low command/address enable signal (SKENn), a command/address clock signal (SKn) (e.g., such as the SKn signal on the test control circuit686), an active-low DIN/DOUT enable signal (DQENn), active-high and -low data strobe signals (QBS/BDQS), and active-high and -low read enable signals (REn/BREn) from the storage controller930(such as those on the I/O circuit222). Then, the memory die910may transmit and receive one or more additional signals to and from the storage controller930as set forth above, for example, in connection withFIG.6.

The SKENn signal is a signal for enabling command/address sequencing on the memory die910and is asserted, for example, at a logic LOW level to enable the command/address sequencing. In memory system900, the X1DQ signal is a signal for receiving control signals and exchanging of data related to command/address sequencing, for example, according to the testing protocol as described above in connection toFIG.7. For example, the X1DQ signal may include a 1-bit pattern that comprises one or more of a first bit encoded at logic HIGH level indicating to select a CLE mode and that that information encoded in signal X1DQ is a command code and a second bit asserted at logic HIGH level to select ALE mode and indicating that information encoded in the signal X1DQ is an address code. In some embodiments, additional bits of the X1DQ signal may by asserted at logic HIGH or LOW levels to select other modes, such as described above in connection withFIG.7. The SKn signal is a clock signal for sampling a received signal in the memory die910(e.g., such as described above in connection withFIG.7). Accordingly, a signal X1DQ is received in the memory die910when the SKn signal is toggled.

The DQENn signal is a signal for enabling DIN/DOUT on the memory die910and is asserted, for example, at a logic LOW level. The DQS/BDQS signal is a clock signal for sampling a received signal in the memory die910(e.g., latching bit values detected at each rising or falling edge of the DQS/BDQS signal to obtain an encoded bit patter). Accordingly, a signal DQ [n:0] is received in the memory die910when the DQS/BDQS signal is toggled. The REn/BREn signal is a signal used for the storage controller102to read data from the memory die910. The REn signal is asserted, for example, at the logic LOW level. Accordingly, the memory die910outputs the signal DQ [n:0] to the storage controller930based on the toggled REn/BREn signal.

FIG.9depicts various pins included as part of the I/O circuit911and the memory interface circuit940. A first subset of pins is used to perform the command and address sequence and a second subset of pins are used to perform DIN/DOUT operations. It should be appreciated that the character ‘x’ in each block element following a given acronym indicates that the block element is a pin for the signal identified in the block element. For example, block element SKnx912represents SKnx pin912for receiving the SKn signal on the memory die910and block element SKnx934arepresents SKnx pin934afor transmitting the SKn signal from the storage controller930. Accordingly, the memory die910comprises a first subset of pins including, but not limited to, SKnx pin912, X1IOx pin913for transmitting and receiving control and data signals for command/address sequencing, and SKENnx pin918for receiving the SKENn signal. The storage controller930includes corresponding pins, such as SKNx pin934a, X1IOx pin936a, and SKENnx pin938a. The memory die910also comprises a second subset of pins including, but not limited to, DQENnx pin914for receiving the DQENn signal, DQS/BDQS pin915for receiving the DQS/BDQS signal, REn/BREnx pin916for receiving the REn/BREn signal, and I/O[n:0]x for transmitting and receiving the DQ [n:0] signal. The storage controller includes corresponding pins, such as DQENnx pin940a, DQS/BDQS pin942a, REn/BREnx pin944a, and I/O[n:0]x pin946a. As described above, the memory interface circuit940connects to the I/O circuit911over the memory interface919via the plurality of pins. The first sub-set of bins (e.g., pins912,913,918,934a,935a, and938a) connects the memory interface circuit940connects to the I/O circuit911over the test interface (e.g., test interface684ofFIG.6).

With reference toFIG.6, the memory die910also includes status register666, address register668, command register670, sequencer672, ready/busy circuit674, voltage generation circuit676, and data register678. The I/O circuit911(e.g., implemented in a manner similar to input and output circuit662) inputs the DQ [0:n] signa as DIN received from the storage controller930to data register678. The I/O circuit911also receives address code and command code over the X1DQ signal and transmits the address to the address register668and the command code to the command register670. The I/O circuit911also transmits DOUT received from the data register678to storage controller930over the DQ [n:0] signal and transmits an address code received from the address register668to the storage controller102over the X1DQ signal.

The I/O circuit911(e.g., implemented in a manner similar to logic control circuit664) receives, for example, the SKENn signal and the SKn signal from the storage controller930via the test data bus of a test interface (e.g., test interface684). The I/O circuit911receives, for example, the DQENnx signal, the DQS/BDQS signal, and the REn/BREn signal from the storage controller930via a control bus (e.g., control bus226) of the memory interface919. The internal functions of the memory die910proceeds in a manner substantially similar to memory die104aas set forth in connection withFIG.6. For example, I/O circuit911controls the input and output circuit662and the sequencer672in accordance with a received signal as described in connection withFIG.6.

The memory die920of memory array904may function in a manner similar to memory die910. Memory die920includes I/O circuit921(which may be substantially similar to I/O circuit911) connected to a memory interface circuit940via a memory interface929(e.g., memory interface224ofFIGS.2A and2B) and operates based on commands from the storage controller930. For example, the memory die920comprises a first subset of pins including, but not limited to, SKnx pin922for transmitting an SKn signal from the storage controller930, X1IOx pin923for transmitting and receiving control and data signals to storage controller930for command/address sequencing, and SKENnx pin928for receiving an SKENn signal from the storage controller930. The storage controller930includes corresponding pins, such as SKNx pin934b, X1IOx pin936b, and SKENnx pin938b. The memory die920also comprises a second subset of pins including, but not limited to, DQENnx pin924for receiving the DQENn signal from the storage controller930, DQS/BDQS pin925for receiving the DQS/BDQS signal from the storage controller, REn/BREnx pin926for receiving the REn/BREn signal from the storage controller930, and I/O[n:0]x for transmitting and receiving the DQ [n:0] signals to and from the storage controller930. The storage controller930includes corresponding pins, such as DQENnx pin940b, DQS/BDQS pin942b, REn/BREnx pin944b, and I/O[n:0]x pin946b. As described above, the memory interface circuit940connects to the I/O circuit921over the memory interface928via the plurality of pins. The first sub-set of bins (e.g., pins912,913,918,934a,935a, and938a) connects the memory interface circuit940connects to the I/O circuit911over the test interface (e.g., test interface684ofFIG.6).

FIG.9depicts memory system900having multiple memory arrays902and904. The term “G1” and “G2” following the acronyms SKENn and DQENn represent a “Group 1” and “Group 2” and indicates a given signal is associated with a respective group of memory dies or memory array. That is, the term “G1” indicates that the SKENn_G1and DQENn_G1signals are received by the memory array902(e.g., a first group of one or more memory dies), and the term “G2” indicates that the SKENn_G2and DQENn_G2signals are received by the memory array904(e.g., a second group of one or more memory dies). As used herein, a group of memory dies or a memory array may refer to one or more memory dies. The group of memory dies may be arranged in a memory die stack or otherwise. Furthermore, a single memory array (e.g., memory array202ofFIG.2A) may comprises a plurality of memory dies that are grouped into the first group and the second group. That is, the first group of memory dies may comprise one or more memory dies of a memory array and the second group of memory dies may comprise one or more memory dies of the same memory array, where the memory dies of contained in each group are separate and distinct memory dies. Thus, embodiments herein of multi-die operations may apply either inter-memory array (e.g., between memory dies of separate memory array) or intra-memory array (e.g., between memory dies of the same memory array).

Furthermore, embodiments herein are not limited to only two memory arrays as shown inFIG.9but may apply to any number of memory arrays for multi-die data operations. For example, embodiments herein may include three, four, five, or any number of groups of memory dies. Two groups are provided merely as an illustrative example to facilitate understanding.

FIGS.10and11schematically depict an example timing diagrams of signals for overlapping a DIN/DOUT operations with command/address sequencing, in accordance with embodiments of the disclosed technology.FIG.10illustrates example timing diagram1000for overlapping a DIN operation with command/address sequencing.FIG.11illustrates example timing diagram1100for overlapping a DOUT operation with command/address sequencing.

Timing diagram1000and1100depict example operation performed on memory system900based on one or more signals exchanged between storage controller930and memory array902(also referred to as a first group of memory dies including memory die910) via memory interface919one or more signal exchanged between memory array904(also referred to as a second group of memory dies including memory die920) via a memory interface929. The timing diagrams1000and1100illustrate examples of overlapping multi-die data operations, whereby memory array902executes a DIN/DOUT operation that is overlapped, in time, with command/address sequencing on memory array904. Reference herein will be made with respect to a single memory die on each memory array (e.g., memory dies910and920).

The command/address sequence depicted inFIGS.10and11utilize various signals that are also used in connection with the existing command/address sequences depicted inFIGS.7-8B, but employs them in a novel way that allows for the command/address sequence to be performed without requiring use of an I/O data bus (e.g., data bus228of memory interface224) and/or the DQ[n:0] signals. For example, the command/address sequence encodes bit information on the X1DQ signal of the test interface (e.g., test interface684), where the bit information can be decoded to obtain a control signals (e.g., CLE signal, ALE signal, etc.), command codes, and address codes, and thus, does not require the DQ[n:0] signals or I/O data bus to provide the command and address information, nor enable the functionality. In contrast, the command/address sequence ofFIGS.10and11utilize the X1DQ signal over the test data bus to both enable command/address sequencing and provide the command and address information. As such, the command/address sequence ofFIGS.10and11can be performed in parallel with DIN/DOUT operations, thereby eliminating the bottleneck that the command/address sequence would otherwise have caused, and providing a technical improvement over the existing command/address sequences ofFIGS.8A and8B, in the form of improved memory system performance.

Referring first toFIG.10, timing diagram1000includes a plurality of signals for performing DIN overlapped with command/address sequencing. For example, but not limited to, timing diagram1000includes an active-low command/address enable (SKEn_G1) signal1002the first group of memory dies, an active-low command/address enable (SKEn_G2) signal1004for the second group of memory dies, an active-low DIN/DOUT enable (DQENn_G1) signal1006for the first group, an active-low DIN/DOUT enable (DQENn_G1) signal1008for the second group, a command/address clock signal (SKn) signal1010, a data strobe (DQS) signal1012, I/O data (DQ [n:0]) signals1014, and a 1-bit I/O data (X1DQ) signal1016.

In the illustrative example ofFIG.10, the storage controller asserts the SKENn_G1signal1002to logic HIGH level, to notify the memory die910that command/address sequencing is disabled. The storage controller also asserts the DQENn_G1signal to logic LOW level, thereby notifying the memory die910of incoming data over the DQ [n:0] signal1014for the DIN operation and enabling the DIN operation. The DQS signal1012is a clock signal for sampling the DQ [n:0] signal in the memory die910at each rising or falling edge of the DQS signal1012. Accordingly, a signal DQ [n:0] is received in the memory die910when the DQS signal1012is toggled. The memory die910detects the DQ[n:0] signals and, for each rising or falling edge of the DQS signal1012, latches bit values encoded into the DQ[n:0] signals to obtain a DIN bit pattern. The memory die910then decodes the DIN bit pattern to obtain DIN and stores DIN in a data register (e.g., data register678).

Concurrent with memory die910executing the DIN operation, the storage controller asserts SKENn_G2signal1004to logic LOW level, to notify the memory die920that command/address sequencing is enabled. The storage controller also asserts the DQENn_G2signal to logic HIGH level, thereby notifying the memory die920that data operations on the DQ [n:0] signal are disabled. The storage controller transmits command and address data for sequencing over the X1DQ signal1016, for example, as set forth in connection withFIGS.7and9.

In the illustrative example shown inFIG.10, during a mode select protocol portion1040, the storage controller generates a mode select signal encoded with a first bit pattern to instruct the memory die910to enter a one of CLE or ALE mode. For example, a first bit pattern may assert a bit corresponding to the CLE or ALE mode as logic HIGH level, while asserting the other bits as logic LOW level, to select CLE or ALE. In the illustrative example ofFIG.10, the first and second bits are at logic HIGH level indicating mode selection protocol is initiated, which is followed by a first bit set to logic LOW level (e.g., a CEn bit set to 0) and a second bit set to logic HIGH level (e.g., a CLE bit set to 1), the rest of the bits are set to logic low in this example. Thus, the first bit pattern indicates CLE is selected. Alternatively, if the second bit was set to logic LOW level and the third bit was set to logic HIGH level (e.g., a ALE bit set to 1), the first bit pattern was indicate ALE is selected. The mode select signal is transmitted from the storage controller930to the memory die910on the X1DQ signal1016via the test data bus of the test interface (e.g., test interface684). The memory die910detects the X1DQ signal1016and, at each rising or falling edge of the SKn signal1010, samples and latches a bit value in the mode select signal to obtain the first bit pattern. The memory die910decodes the first bit pattern to identify the selected mode as one of CLE or ALE.

During the input protocol portion1050, following a first bit at logic HIGH level and a second bit at logic LOW level indicating data of the selected mode is forthcoming, the storage controller930generates a command or address data signal encoded with a second bit pattern that is one of a command code and an address code. In the case of a command code as indicated by mode select protocol portion1040in this example, the storage controller930may encode bits D0-D7of the data signal with a command code, such as, any one of 00000000 for command code 00 h, 00110000 for command code 30 h, 10101010 for command code 55 h, etc. In the case of an address code, the storage controller930may encode first bit pattern as bits D0-D7as, for example, 00100000, which may be decoded to an address code to select a wordline1of string0. The command or address data signal is transmitted from the storage controller930to the memory die920via the test data bus of the test interface. The memory die920detects the X1DQ signal1016and, at each rising or falling edge of the SKn signal1010, samples and latches a bit value in the command or address data signal to obtain the second bit pattern. The memory die920decodes the second bit pattern to retrieve the one of the command code and address code. The command code or address code is then processed as set forth above in connection withFIG.6, for example, by storing the command code in the command register670or address register668, respectively.

Once the input protocol portion1050, a subsequent mode select protocol portion1060can be performed, for example, by setting two consecutive bits to logic HIGH level. For example, in a case where mode select protocol portion1040includes a CLE command and a command code is transmitted to the memory die910over the X1DQ signal1016(e.g., the X1DQ signal1016includes a CLE signal), the storage controller930generates a second mode select signal encoded with a third bit pattern to instruct the memory die910to enter an ALE mode (e.g., the X1DQ signal1016includes an ALE signal). The memory die910detects the X1DQ signal1016and, at each rising or falling edge of the SKn signal1010, samples and latches a bit value in the mode select signal to obtain the third bit pattern. The memory die910decodes the third bit pattern to identify the selected mode ALE.

After the portion1060, for example during a subsequent input protocol portion (not shown), the storage controller930generates an address data signal encoded with a fourth bit pattern that is an address code. The address data signal is transmitted from the storage controller930to the memory die920via the test data bus of the test interface. The memory die920detects the X1DQ signal1016and, at each rising or falling edge of the SKn signal1010, samples and latches a bit value in the command or address data signal to obtain the fourth bit pattern. The memory die920decodes the fourth bit pattern to retrieve the address code.

Turning now toFIG.11, timing diagram1100includes a plurality of signals for performing DOUT overlapped with command/address sequencing. For example, similar to timing diagram1000, the plurality of signals includes, but is not limited to, timing diagram1100includes an active-low command/address enable (SKEn_G1) signal1102the first group of memory dies, an active-low command/address enable (SKEn_G2) signal1104for the second group of memory dies, an active-low DIN/DOUT enable (DQENn_G1) signal1106for the first group, an active-low DIN/DOUT enable (DQENn_G1) signal1108for the second group, a command/address signal (SKn) signal1110, a data strobe (DQS) signal1112, IO data (DQ [n:0]) signals1114, and a 1-bit I/O data (X1DQ) signal1116. The timing diagram1100also includes an active-low read enable (REn) signal1118.

In the illustrative example ofFIG.11, the storage controller asserts the SKENn_G1signal1102to logic HIGH level, to notify the memory die910that command/address sequencing is disabled. The storage controller also asserts the DQENn_G1signal to logic LOW level, thereby enabling transmission of data over the DQ [n:0] signal1114for the DOUT operation. After the waiting period waiting period tWHR1elapses (as described above in connection withFIG.8), the storage controller930transmits the REn signal1118and the memory die910starts reading out data from the data register and, after waiting period tWHR2elapses, starts transmitting DOUT on the DQ [n:0] signal1114to the storage controller930clocked according to the DQS signal1112.

Concurrent with the memory die910executing the DOUT operation, the storage controller asserts SKENn_G2signal1104to logic LOW level, to notify the memory die920that command/address sequencing is enabled. The storage controller also asserts the DQENn_G2signal to logic HIGH level, thereby notifying the memory die920that data operations on the DQ [n:0] signal1114are disabled. The storage controller transmits command and address data for sequencing over the X1DQ signal1116, for example, as set forth in connection withFIGS.7and9.

In the illustrative example shown inFIG.11, during a mode select protocol portion1140, the storage controller generates a mode select signal encoded with a first bit pattern to instruct the memory die910to enter a one of CLE or ALE mode, for example, as described above in connection with mode select protocol portion1040. The mode select signal is transmitted from the storage controller930to the memory die910on the X1DQ signal1116via the test data bus of the test interface (e.g., test interface684). The memory die910detects the X1DQ signal1116and obtains the first bit pattern. The memory die910decodes the first bit pattern to identify the selected mode as one of CLE or ALE.

During the input protocol portion1150, the storage controller930generates a command or address data signal encoded with a second bit pattern that is one of a command code and an address code, for example, as described above in connection with input/output protocol portion1050. The command or address data signal is transmitted from the storage controller930to the memory die920via the test data bus of the test interface. The memory die920detects the X1DQ signal1116and obtains the second bit pattern. The memory die920decodes the second bit pattern to retrieve the one of the command code and address code. The command code or address code is then processed as set forth above in connection withFIG.6, for example, by storing the command code in the command register670or address register668, respectively.

Once the input protocol portion1150, a subsequent mode select protocol portion1160can be performed, for example, as described above in connection with mode select protocol portion1060.

FIG.12schematically depicts an example timing diagram1200of signals illustrating how command/address sequencing overhead is hidden in the background, in accordance with embodiments of the disclosed technology. Timing diagram1200depicts an example multi-die read operation performed on memory system900based on one or more signals exchanged between storage controller930and memory array902(also referred to as a first group of memory dies including memory die910) via memory interface919one or more signal exchanged between memory array904(also referred to as a second group of memory dies including memory die920) via a memory interface929. The timing diagram900illustrates an example of multi-die data operations, whereby DOUT operations are overlapped with command/address sequencing. As such, the command/address sequencing is performed in the background, and the processing time overhead associated therewith is essentially hidden from data operations (e.g., DIN and DOUT operations). Thus, data operations can be performed in parallel with command/address sequencing, which improves overall data processing time due to parallelizing the processes.

FIG.12illustrates a series command/address sequence are depicted encoded in a data signal on X1DQ signal1216, a first command/address sequence1226in a first time portion1220and a second1236in second time portion1230. In addition, a series of DIN/DOUT operations are depicted encoded in data signal on DQ[n:0] signal1214, a first DIN/DOUT operation1228in first time portion1220and a second1238in time portion1230. Each command/address sequence may be performed in parallel with a DIN/DOUT operation. More specifically, in example embodiments of the disclosed technology, while a DIN/DOUT operation corresponding to a current read/write operation is being performed by a first memory die910on the I/O bus via DQ[n:0] single1214, a command/address sequence corresponding to a read/write operation may be performed in parallel by a second memory die920on the test data bus via X1DQ signal1216. The command/address sequence may correspond to a read/write operation that will be performed after the DIN/DOUT operation1228, for example, during the second time portion1230.

Timing diagram1200includes a first time portion1220and a second time portion1230. In the first time portion1220, one memory die in a first group (G1) of memory dies (e.g., memory die910of memory array902) executes a DIN/DOUT operation1228(e.g., DOUT operation in this example) that is overlapped, in time, with command/address sequencing1226performed on a second group (G2) of memory dies (e.g., memory array904). In this example, the first group G1of memory dies may include at least memory die X1and memory die Y1and the second group G2of memory dies may include at least memory die X2and memory die Y2. The example command/address sequencing1226includes different operations for different dies (e.g., operation1222for memory die X2and operation1224for memory die Y2); however, operations may be for the same die. In the second time portion1230, a memory die (Y2) of a second group (e.g., memory die920) executes a DIN/DOUT operation1238(e.g., a DOUT operation in this example) that is overlapped, in time, with command/address sequencing1236performed on the memory die of the first group (e.g., memory die910). The example command/address sequencing1236includes different operations for different dies (e.g., operation1232for memory die X1and operation1234for memory die Y1); however, operations may be for the same die.

Accordingly, the command/address sequence1226may be performed in parallel with the DIN/DOUT operation1228. The DIN/DOUT operation1228may correspond to a prior command/address sequence that was performed by memory die910. More specifically, the prior command/address sequence and the current DIN/DOUT operation1226may both correspond to a same current read/write operation. The command/address sequence1224, on the other hand, may be associated with a next read/write operation to be performed by the memory die Y2, but may be performed in parallel with the DIN/DOUT operation1228associated with the current read/write operation on the memory die910. The command/address sequence depicted inFIGS.10and11according to example embodiments of the disclosed technology enables the parallelism depicted inFIG.12between the command/address sequencing and the DIN/DOUT operations.

Timing diagram1200includes a plurality of signals for performing DOUT operations overlapped with command/address sequencing. For example, timing diagram1200includes an active-low command/address enable (SKEn_G1) signal1202the first group G1of memory dies, an active-low command/address enable (SKEn_G2) signal1204for the second group G2of memory dies, an active-low DIN/DOUT enable (DQENn_G1) signal1206for the first group G1, an active-low DIN/DOUT enable (DQENn_G1) signal1208for the second group G2, a command/address clock signal (SKn)1210, a data strobe (DQS) signal1212, IO data (DQ [n:0]) signals1214, a IO data (X1DQ) signal1216, and an active-low read enable (REn) signal1218.

In operation, during time portion1220, the storage controller asserts the SKENn_G1signal1202to logic HIGH level, to notify the memory die910that command/address sequencing is disabled. The storage controller also asserts the DQENn_G1signal to logic LOW level, thereby enabling transmission of data over the DQ [n:0] signal1214for the DOUT operation1228. After the waiting period waiting period tWHR1elapses (as described above in connection withFIG.8), the storage controller930transmits the REn signal1218and the memory die910starts reading out data from the data register and, after waiting period tWHR2elapses, starts transmitting DOUT on the DQ [n:0] signal1214to the storage controller930clocked according to the DQS signal1212.

Concurrent with the DOUT operation1228performed by memory die910, the storage controller asserts SKENn_G2signal1204to logic LOW level, to notify the memory dies of the second group G2that command/address sequencing is enabled. The storage controller also asserts the DQENn_G2signal to logic HIGH level, thereby notifying the second group G2that data operations on the DQ [n:0] signal1214are disabled. The storage controller transmits command and address data for sequencing over the X1DQ signal1216, for example, as set forth in connection withFIGS.7and9. For example, the memory die X2performs a first read operation1222for cell read command and address sequencing based on an “ooh” to “30 h” commands (and column and address data) decoded from a first bit pattern encoded onto the X1DQ signal1216sampled based on SKn signal1210. As explained above, the “ooh” command notifies the memory die X2to execute the cell read command at the address provided, and the “30 h” command instructs the memory die X2to store the data in data register.

After the period tRelapses, the memory die Y2performs a second read operation1224for register read command and address sequencing based on an “05 h” to “E0 h” commands (and column and address data) decoded from a second bit pattern encoded onto the X1DQ signal1216sampled based on SKn signal1210. As explained above, the “05 h” command notifies the memory die Y2to execute the register read command at the address provided, and the “E0 h” command instructs the memory die Y2to transmit the data to the storage controller.

Then, during the waiting period tWHR2, the memory die Y2starts prefetching processes and packages for the DOUT operation1238. Also, during the waiting period tWHR2, the storage controller toggles the SKENn_G2to logic HIGH level to disable the command/address sequencing over the test interface and toggles DQENn_G2to logic LOW level to instruct the memory die Y2to perform DOUT on the DQ [n:0] signal1214, for example, during time portion1230. For example, after waiting period tWHR2elapses, the memory die Y2starts transmitting DOUT on the DQ [n:0] signal1214to the storage controller930clocked according to the DQS signal1212. As an illustrative example, the DQENn_G2signal1208may be toggled to logic LOW level when the storage controller930is ready to receive data from the second group G2of memory dies through DQ[n:0] signal1214. The DQENn_G2signal1208and the DQENn_G1signal1206may use a common bus, for example, the bus from the first group G1to the storage controller930may be common with the bus from the second group G2and the storage controller930. During time portion1220the storage controller930may be still busy receiving data from first group G1. When the data transfer from the first group G1is done, then the first group G1disables DQENn_G1signal1206and the second group G2enables DQENn_G2signal1208to enable the data bus for DQ[n:0] signal1214from the second group G2. QENn_G2signal1208and QENn_G1signal1206can both be disabled, but cannot both be enabled at the same time otherwise contention may occur on the data bus. Similarly, for SKENn_G1signal1202and SKENn_G2signal1204, both signals cannot be enabled at the same time.

Concurrent with the DOUT operation1238during time portion1230, in the illustrative example, the first group G1may be instructed to perform command/address sequencing1236on the test interface, for example, responsive to a command from a host device to perform another data operation. For example, in parallel with the DOUT operation1238, the storage controller asserts SKENn_G1signal1204to logic LOW level, to notify the first group G1of memory dies that command/address sequencing is enabled. The storage controller also asserts the DQENn_G1signal to logic HIGH level, thereby notifying the first group G1of memory dies that data operations on the DQ [n:0] signal1214are disabled. The storage controller transmits command and address data for sequencing over the X1DQ signal1216, for example, as set forth in connection withFIGS.7and9. For example, the memory die X1performs a first operation1232for cell read command and address sequencing based on an “ooh” to “30 h” commands (and column and address data) decoded from a third bit pattern encoded onto the X1DQ signal1216sampled based on SKn signal1210. After the period tRelapses, the memory die Y1performs a second operation1234for register read command and address sequencing based on an “05 h” to “E0 h” commands (and column and address data) decoded from a fourth bit pattern encoded onto the on the X1DQ signal1216sampled based on SKn signal1210.

Then, during the waiting period tWHR2, the memory die Y1starts prefetching processes and packages a subsequent DIN/DOUT operation to be performed by the memory die Y1. Also, during the waiting period tWHR2, the storage controller may toggle the SKENn_G1to logic HIGH level to disable the command/address sequencing over the test interface and toggles DQENn_G1to logic LOW level to instruct the memory die Y1to perform DOUT on the DQ [n:0] signal1214(not shown). For example, after waiting period tWHR2elapses, the memory die Y1starts transmitting DOUT on the DQ [n:0] signal1214to the storage controller930clocked according to the DQS signal1212.

The amount of time to perform command/address sequencing for embodiments disclosed herein may be based on the number cycles required to execute the command/address sequencing over the test interface (e.g., in a 1-bit sequence on the X1DQ signal). The number of cycles refers to the period of the SKn signal used to sample the X1DQ signal. The current state of art of memory systems provides for an SKn signal having a cycle time or period of 10 ns, while some implementations use 50 ns cycle time. The cycle time of the SKn signal is continuing to improve to shorter periods. The embodiments herein are not limited to 10 ns or 50 ns, but use these cycle times as illustrative examples only. In the testing protocol described above in connection withFIG.7, the number of cycles to complete each command is 22 cycles (e.g.,22periods of the SKn signal704ofFIG.7). Similarly, an address requires 22 cycles to complete. Turning to the example operations ofFIG.12, the operation1224and1234each require 154 cycles to complete using the test interface protocol ofFIG.7, while the combined operation1222and1224and combined operation1232and1234each require 176 cycles. Table 2 below provides examples times for tWC×7+tWHR2based on the cycle times and number of cycles provided above.

TABLE 2# of cyclesCycle time = 50 nsCycle time = 10 nsEach command221100 ns220 nsEach address221100 ns220 ns01 h-00 h-addr*5-30 h1768800 ns1760 ns05 h-addr*5-E01547700 ns1540 ns

Thus, as shown above, the value for tWC×7+tWHR2according to the embodiments disclosed herein may be longer than example of 370 ns provided in connection withFIG.8. This is because the command/address sequencing ofFIGS.8A and8Bwas performed using an I/O data bus having 8-bit signals DQ [0:7] as eight data lines, whereas the embodiments herein utilize a test data bus having a 1-bit signal X1DQ as a single data line. Thus, while the total time for the command/address sequencing may be longer, the total time to complete a read/write operation is reduced due to performing the command/address sequencing in the background and in parallel with DIN/DOUT operations. For example, as illustrated above in connection withFIG.12, the time needed for the command/address sequencing is performed in parallel with DIN/DOUT operations, thereby hiding the processing time overhead associated with command/address sequencing. As such, the execution of command/address sequencing on a 1-bit signal X1DQ in parallel with DIN/DOUT operations on 8-bit signals DQ [n:0] reduces overall processing time to complete host commands. Additionally, the SKn cycle time can be reduced to 2 ns, which will then closely follow original overhead of 370 ns as in the above example, along with being hidden due to parallel operation with DIN/DOUT operations. Thus, even more command/address sequencing is possible allowed within a smaller window of time and hidden within DIN/DOUT operations.

Accordingly embodiments herein provide a technical solution to a technical problem associated with existing command and address sequencing by performing command/address sequence in parallel with DIN/DOUT operations, thereby reducing (and even removing) performance bottleneck due to process time overhead for executing the command/address sequencing on the DQ lines. Thus, memory system data operation performance can be improved by reducing command/address overhead, which enables memory systems to be constrained more by DIN/DOUT speeds and less so by command/address sequencing.

FIG.12also illustrates a dotted lines1240and1242. Dotted line1240corresponds with toggling DQENn_G2signal1208to logic LOW level and dotted line1242corresponds with toggling DQENn_G1signal1206to logic HIGH level. The timing gap1244between line1242and1240is a period of time from the one memory die in a first group of memory dies (e.g., memory die910of memory array902) disabling the data bus between the one memory die and the storage controller to the one memory die of a second group of memory dies (e.g., memory die920) enabling its data bus with the storage controller. In various embodiments, the timing gap1244may be needed to avoid contention at the storage controller over the data bus.

FIGS.13A and13Billustrate example timing diagrams for command/address sequencing, in accordance with embodiments of the disclosed technology.FIG.13Aillustrates a timing diagram1310andFIG.13Billustrates timing diagram1320, both of which provide alternative embodiments for command/address processing that provide increased command/address processing speeds. For example, as described above, the test interface protocol ofFIG.7includes 22 cycles to complete a command or address sequencing. Timing diagrams1310and1320provide for a reduced number of cycles to complete each command or address.

For example, timing diagram1310is similar to timing diagram710in that timing diagram1300includes the SKn signal1304and the X1DQ signal1306. Timing diagram1310also includes the SKENn signal1302as described above in connection withFIGS.9-12. Thus, timing diagram1310is substantially the same as the preceding embodiments described in connection withFIGS.9-12. However, while the preceding embodiments operated using the same protocol as the test interface, the timing diagram1310illustrates a command/address sequencing specific implementation that modifies the test interface protocol. For example, during the mode select protocol portion1314of the test interface protocol (e.g., portion714ofFIG.7) bits were set for certain modes and settings that may be unnecessary for command/address sequencing. Specifically, for example, the CEn bit, MVM bit, PARAMs bit, and WPn bit shown inFIG.7are not necessary and are unrelated to command and address sequencing. Thus, as shown inFIG.13A, the mode selection protocol portion ofFIG.7can be reduced to a single bit1318in the mode selection protocol portion1314ofFIG.13A, which is followed by the input/output protocol portion1316.

For example, the storage controller may toggle the SKENn signal1302to logic LOW level to notify the memory die that command/address sequencing is enabled. The storage controller can then assert a first bit1318aon the X1DQ signal1306to logic HIGH level in the mode select protocol portion1318a, for example, to notify the memory die that the next bits are command bits. During the input/output protocol portion1316a, the storage controller then transmits bits at logic HIGH or LOW levels for D0to D7according to a command for the memory die. Then the SKENn signal1302can be toggled at1315to logic HIGH level to rest the bit counter and toggled back to logic LOW level to notify the memory die that command/address sequencing is enabled. The storage controller can then assert a first bit1318bon the X1DQ signal1306to logic LOW level in the mode select protocol portion1314b, for example, to notify the memory die that the next bits are address bits. During the input/output protocol portion1316b, the storage controller then transmits bits at logic HIGH or LOW levels for D0to D7according to a command for the memory die. While logic HIGH and LOW levels for command and address, respectively, are described above, this setting is purely for illustrative purpose. For example, the command may be indicated by logic LOW level and the address by logic HIGH level.

Using the protocol shown inFIG.13A, the number of cycles for each command and address can be reduced to 9 cycles, compared to 22 cycles of the test interface protocol. Thus, the processing time overhead of the command/address sequencing is reduced according. For example, where cycle time is 10 ns, the tWC×7+tWHR2of a command according to timing diagram1210is 90 ns as compared to 220 ns of Table 2.

Timing diagram1320provides even further reduction in processing time overhead of the command/address sequencing according to embodiments herein. For example, a data line may be added to the interface thereby providing 2-bit signals X2DQ[0:1]1322. Thus, for each sampling of the X2DQ signal1322, two states may be indicated thereby reducing the number of cycles required to complete a command or process. For example, in the mode select protocol portion1324a, the SKENn signal1302is toggled to logic LOW level and a first bit1328ais asserted on the X2DQ signal1322, to notify the memory die that the next bits are command bits. In this example, a command can be asserted by setting both bits to logic HIGH level (e.g., “11”); however, the command may be asserted by setting both bits to logic LOW level (e.g., “00”). Then in the input/output protocol portion1326a, the storage controller then transmits bits at logic HIGH or LOW levels for D0to D7according to a command for the memory die. Then the SKENn signal1302can be toggled at1315to logic HIGH level to rest the bit counter and toggled back to logic LOW level to notify the memory die that command/address sequencing is enabled. In the mode select protocol portion1324b, the storage controller asserts an address by setting the first two bits1328bon the X2DQ signal1306to logic LOW level, for example. While both bits are set to logic LOW level to assert an address in this example, an address may be asserted by setting both bits to logic HIGH level. In the input/output protocol portion1326b, the storage controller then transmits bits at logic HIGH or LOW levels for D0to D7according to a command for the memory die.

Using the protocol shown inFIG.13B, the number of cycles for each command and address can be reduced to 5 cycles, compared to 22 cycles of the test interface protocol. Thus, the processing time overhead of the command/address sequencing is reduced according. For example, where cycle time is 10 ns, the tWC×7+tWHR2of a command according to timing diagram1200is 40 ns as compared to 220 ns of Table 2.

In another example, more than two data lines may be used. For example, the command/address sequencing may be performed on a data bus having m data lines (also referred to herein as a m-bit signal data bus), where m is an integer that is less than a number n of data lines in data bus used for the DQ[n:0] signal (e.g., data bus228)

FIGS.14and15are flowcharts of illustrative methods1400and1500for performing a command/address sequence according to example embodiments of the disclosed technology. The method1400and/or the method1500may be performed by a controller such as storage controller102(FIG.1) and/or storage controller930(FIG.9). More generally, the methods1400and/or1500may be performed by any volatile or non-volatile memory system configured to interface with a memory device such as a NAND device (or that is embedded therein) including, without limitation, a separately provided DRAM, an embedded microcontroller, or the like. In some embodiments, the instructions for performing the method1400and/or the instructions for performing the method1500may be hardwired or fused into the memory core.

Referring now toFIG.14, at block1402, a first enable signal is detected. In example embodiments, the first enable signal may be a SKENn signal to instruct a memory die (e.g., memory die104aofFIG.1and/or memory die910or920ofFIG.9) to activate the test interface for command/address sequencing. The memory die may detect the SKENn signal from the storage controller and enable command/address sequencing via the test interface.

At block1404, a first data signal is detected, for example, by the memory die. In example embodiments, the first data signal is detected on a test data bus of the test interface. The test data bus may comprise a 1-bit I/O data signal via a single data line (e.g., as described in connection withFIGS.9-12). In another example, the test data bus has an m-bit I/O data signal, where m is an integer less than the number of bit I/O data signals used for DIN/DOUT operations (e.g., as described in connection withFIG.13B). The storage controller may encode a first bit pattern. In example embodiments, the storage controller generates the first data signal by encoding a CLE or an ALE signal into an X1DQ signal on the test data bus.

At block1406, responsive to detecting the first enable signal at block1402, a bit value encoded in the first data signal to obtain a first bit pattern is latched at each of a first one or more rising or falling edges of a clock signal. For example, the clock signal may be the SKn signal generated by the storage controller and provided via the test data bus to the memory die for sampling the first data signal. At block1408, a bit value encoded in the first data signal to obtain a second bit pattern is latched at each of a second one or more rising or falling edges of the clock signal. In example embodiments, the first bit pattern is encoded in the first data signal as bits the precede the second bit pattern. For example, the first bit pattern may correspond to a mode select protocol portion (e.g., portions1040,1060,1140,1160,1314, and1324) and the second bit pattern may correspond an input/output protocol portion (e.g., portions1050,1150,1316, and1326).

At block1408, a second enable signal is decoded from the first bit pattern. In example embodiments, the memory die decodes the first bit pattern as one of a CLE command and an ALE command. At block1410, one of a command code and an address code is decoded from the second bit pattern.

Referring now toFIG.15, at block1502, a first enable signal is detected on a control bus of a first memory interface. In example embodiments, the first memory interface may be memory interface224ofFIGS.2A and2Band/or memory interface919or929ofFIG.9. The first memory interface may be between a first memory array and a storage controller and comprises an 8-bit signal data bus and the control bus. The first enable signal may be, for example, an SKENn signal and/or a DQENn signal as described above in connection withFIGS.9-12. At block1504, responsive to the first enable signal detected at block1502, a first data signal is detected over the 8-bit signal data bus. The first data signal is encoded with data for one of a data in (DIN) and data out (DOUT) operation on the first memory array.

At block1506, a second enable signal is detected a second memory interface. In example embodiments, the second memory interface may be memory interface224ofFIGS.2A and2Band/or memory interface919or929ofFIG.9, and more specifically, a test interface thereof (e.g., as described inFIGS.7and9). The second memory interface connects a second memory array and the storage controller. In an example embodiment, the second memory interface comprises at least one 1-bit signal data bus. In another example, the second memory interface comprises m-bit signal data bus, where m is an integer less than eight. In example embodiments, the second enable signal may be a SKENn signal that triggers command/address sequencing on the second memory interface.

Responsive to detecting the second enable signal at block1506, at block1508a second data signal is detected on the second memory interface. The second data signal is encoded with a first bit pattern representative of a third enable signal and a second bit pattern representative of at least one of a command code and an address code. In example embodiments, the third enable signal may be one of a CLE and an ALE.

Aspects of the present disclosure may be embodied as an apparatus, system, method, or computer program product. Accordingly, aspects of the present disclosure may take the form of an entirely hardware embodiment, an entirely software embodiment (including firmware, resident software, micro-code, or the like) or an embodiment combining software and hardware aspects that may all generally be referred to herein as a “circuit,” “module,” “apparatus,” or “system.” Furthermore, aspects of the present disclosure may take the form of a computer program product embodied in one or more non-transitory computer readable storage media storing computer readable and/or executable program code.

Many of the functional units described in this specification have been labeled as modules, in order to more particularly emphasize their implementation independence. For example, a module may be implemented as a hardware circuit comprising custom VLSI circuits or gate arrays, off-the-shelf semiconductors such as logic chips, transistors, or other discrete components. A module may also be implemented in programmable hardware devices such as field programmable gate arrays, programmable array logic, programmable logic devices, or the like.

Modules may also be implemented at least partially in software for execution by various types of processors. An identified module of executable code may, for instance, comprise one or more physical or logical blocks of computer instructions which may, for instance, be organized as an object, procedure, or function. Nevertheless, the executables of an identified module need not be physically located together, but may comprise disparate instructions stored in different locations which, when joined logically together, comprise the module and achieve the stated purpose for the module.

Indeed, a module of executable code may include a single instruction, or many instructions, and may even be distributed over several different code segments, among different programs, across several memory devices, or the like. Where a module or portions of a module are implemented in software, the software portions may be stored on one or more computer readable and/or executable storage media. Any combination of one or more computer readable storage media may be utilized. A computer readable storage medium may include, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing, but would not include propagating signals. In the context of this document, a computer readable and/or executable storage medium may be any tangible and/or non-transitory medium that may contain or store a program for use by or in connection with an instruction execution system, apparatus, processor, or device.

Computer program code for carrying out operations for aspects of the present disclosure may be written in any combination of one or more programming languages, including an object oriented programming language such as Python, Java, Smalltalk, C++, C #, Objective C, or the like, conventional procedural programming languages, such as the “C” programming language, scripting programming languages, and/or other similar programming languages. The program code may execute partly or entirely on one or more of a user's computer and/or on a remote computer or server over a data network or the like.

A component, as used herein, comprises a tangible, physical, non-transitory device. For example, a component may be implemented as a hardware logic circuit comprising custom VLSI circuits, gate arrays, or other integrated circuits; off-the-shelf semiconductors such as logic chips, transistors, or other discrete devices; and/or other mechanical or electrical devices. A component may also be implemented in programmable hardware devices such as field programmable gate arrays, programmable array logic, programmable logic devices, or the like. A component may comprise one or more silicon integrated circuit devices (e.g., chips, die, die planes, packages) or other discrete electrical devices, in electrical communication with one or more other components through electrical lines of a printed circuit board (PCB) or the like. Each of the modules described herein, in certain embodiments, may alternatively be embodied by or implemented as a component.

A circuit, as used herein, comprises a set of one or more electrical and/or electronic components providing one or more pathways for electrical current. In certain embodiments, a circuit may include a return pathway for electrical current, so that the circuit is a closed loop. In another embodiment, however, a set of components that does not include a return pathway for electrical current may be referred to as a circuit (e.g., an open loop). For example, an integrated circuit may be referred to as a circuit regardless of whether the integrated circuit is coupled to ground (as a return pathway for electrical current) or not. In various embodiments, a circuit may include a portion of an integrated circuit, an integrated circuit, a set of integrated circuits, a set of non-integrated electrical and/or electrical components with or without integrated circuit devices, or the like. In an embodiment, a circuit may include custom VLSI circuits, gate arrays, logic circuits, or other integrated circuits; off-the-shelf semiconductors such as logic chips, transistors, or other discrete devices; and/or other mechanical or electrical devices. A circuit may also be implemented as a synthesized circuit in a programmable hardware device such as field programmable gate array, programmable array logic, programmable logic device, or the like (e.g., as firmware, a netlist, or the like). A circuit may comprise one or more silicon integrated circuit devices (e.g., chips, die, die planes, packages) or other discrete electrical devices, in electrical communication with one or more other components through electrical lines of a printed circuit board (PCB) or the like. Each of the modules described herein, in certain embodiments, may be embodied by or implemented as a circuit.

Reference throughout this specification to “one embodiment,” “an embodiment,” or similar language means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present disclosure. Thus, appearances of the phrases “in an embodiment,” “in an embodiment,” and similar language throughout this specification may, but do not necessarily, all refer to the same embodiment, but mean “one or more but not all embodiments” unless expressly specified otherwise. The terms “including,” “comprising,” “having,” and variations thereof mean “including but not limited to” unless expressly specified otherwise. An enumerated listing of items does not imply that any or all of the items are mutually exclusive and/or mutually inclusive, unless expressly specified otherwise. The terms “a,” “an,” and “the” also refer to “one or more” unless expressly specified otherwise.

Aspects of the present disclosure are described below with reference to schematic flowchart diagrams and/or schematic block diagrams of methods, apparatuses, systems, and computer program products according to embodiments of the disclosure. It will be understood that each block of the schematic flowchart diagrams and/or schematic block diagrams, and combinations of blocks in the schematic flowchart diagrams and/or schematic block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a computer or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor or other programmable data processing apparatus, create means for implementing the functions and/or acts specified in the schematic flowchart diagrams and/or schematic block diagrams block or blocks.

It should also be noted that, in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. Other steps and methods may be conceived that are equivalent in function, logic, or effect to one or more blocks, or portions thereof, of the illustrated figures. Although various arrow types and line types may be employed in the flowchart and/or block diagrams, they are understood not to limit the scope of the corresponding embodiments. For instance, an arrow may indicate a waiting or monitoring period of unspecified duration between enumerated steps of the depicted embodiment.

In the following detailed description, reference is made to the accompanying drawings, which form a part thereof. The foregoing summary is illustrative only and is not intended to be in any way limiting. In addition to the illustrative aspects, embodiments, and features described above, further aspects, embodiments, and features will become apparent by reference to the drawings and the following detailed description. The description of elements in each figure may refer to elements of proceeding figures. Like numbers may refer to like elements in the figures, including alternate embodiments of like elements.