Patent ID: 12223915

DETAILED DESCRIPTION

The disclosure may have various modifications and various embodiments, and specific embodiments are illustrated in the drawings and are described in detail in the detailed description. Effects and features of the disclosure and methods of achieving the same will become apparent with reference to embodiments described in detail with reference to the drawings. However, the disclosure is not limited to the embodiments described below, and may be implemented in various forms.

In the following embodiments, the terms “first”, “second”, etc. are not used in a limited sense and are used to distinguish one element from another element.

In the following embodiments, an expression used in the singular encompasses the expression of the plural, unless it has a clearly different meaning in the context.

In the following embodiments, it will be further understood that the terms “comprise” and/or “comprising” used herein specify the presence of stated features or elements, but do not preclude the presence or addition of one or more other features or elements.

It will be understood that when a layer, region, or element is referred to as being “formed on” another layer, area, or element, it can be directly or indirectly formed on the other layer, region, or element. That is, for example, intervening layers, regions, or elements may be present.

In the drawings, for convenience of description, sizes of elements may be exaggerated or reduced. In other words, because sizes and thicknesses of elements in the drawings are arbitrarily illustrated for convenience of explanation, the disclosure is not necessarily limited thereto.

As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items. Throughout the disclosure, the expression “at least one of a, b, and c” indicates only a, only b, only c, both a and b, both a and c, both b and c, all of a, b, and c, or variations thereof.

According to embodiments, a case where X and Y are connected to each other may include a case where X and Y are electrically connected to each other, a case where X and Y are functionally connected to each other, and a case where X and Y are physically connected to each other, with or without intervening elements (for example, direct or indirect connection). Here, X and Y may be objects (for example, apparatuses, devices, circuits, wires, electrodes, terminals, conductive layers, or layers). Accordingly, such a connection is not limited to a certain connection relationship, for example, a connection relationship indicated in drawings or detailed description, and may include connection relationships other than that indicated in the drawings or detailed description.

A case where X and Y are electrically connected to each other may include, for example, a case where X and Y are directly connected to each other, and a case where at least one device (for example, a switch, a transistor, a capacitor, an inductor, a resistor, or a diode) enabling an electric connection between X and Y is connected between X and Y.

According to embodiments, the term “on” used in association with a device state may refer to an activated state of a device, and the term “off” may refer to a deactivated state of the device. The term “on” used in association with a signal received by a device may refer to a signal activating the device, and the term “off” may refer to a signal deactivating the device. A device may be activated by a voltage of a high level or a low level. For example, a P-channel transistor (P-type transistor) may be activated by a low-level voltage, and an N-channel transistor (N-type transistor) may be activated by a high-level voltage. Accordingly, it should be understood that “on” voltages for the P-type transistor and the N-type transistor are opposite voltage levels (low versus high).

According to embodiments, an x direction, a y direction, and a z direction are not limited to directions in three axes on an orthogonal coordinate system, but may be interpreted in a broad sense including the three axes. For example, the x direction, the y direction, and the z direction may be perpendicular to one another, or may represent different directions that are not perpendicular to one another.

A display device according to embodiments of the disclosure is an apparatus for displaying a moving image or a still image, and may be used as a display screen of not only portable electronic devices, such as a mobile phone, a smart phone, a tablet personal computer (“PC”), a mobile communication terminal, an electronic notebook, an electronic book, a portable multimedia player (“PMP”), a navigation device, and an ultra-mobile PC (“UMPC”), but also various products, such as a television, a laptop computer, a monitor, a billboard, and Internet of things (“IoT”). Also, a display device according to an embodiment may be used for a wearable device, such as a smart watch, a watch phone, a glasses-type display, or a head mounted display (“HMD”). In addition, a display device according to an embodiment may be used as a panel of a vehicle, a center information display (“CID”) arranged on a center fascia or dashboard of a vehicle, a room mirror display replacing a side mirror of a vehicle, or a display arranged on a rear surface of a front seat, as entertainment for a back seat of a vehicle. Also, a display device may be a flexible device.

FIGS.1A and1Bare views schematically showing a display device1according to embodiments.FIG.2is a diagram schematically showing the display device1according to an embodiment.

Referring toFIGS.1A and1B, the display device1may include a display area DA where an image is displayed, and a peripheral area PA outside the display area DA. The display area DA may be entirely surrounded by the peripheral area PA.

When the display area DA is viewed in a plane, the display area DA may have a rectangular shape. According to another embodiment, the display area DA may have a polygonal shape, such as a triangle, a pentagon, or a hexagon, or may have a circular shape, an oval shape, or an atypical shape. The display area DA may have a round shape at a corner of an edge. According to an embodiment, the display device1may include the display area DA in which a length in an x direction is longer than a length in a y direction, as shown inFIG.1A. According to another embodiment, the display device1may include the display area DA in which the length in the y direction is longer than the length in the x direction, as shown inFIG.1B.

The display device1may include a display panel10, and a cover window (not shown) protecting the display panel10may be further disposed on the display panel10.

Various elements included in the display panel10may be arranged on a substrate100. The substrate100may include the display area DA and the peripheral area PA surrounding the display area DA.

A plurality of pixels PX may be arranged in the display area DA. A plurality of gate lines GL, a plurality of data lines DL, and the plurality of pixels PX connected thereto may be arranged in the display area DA. The plurality of pixels PX may realize an image by being arranged in various forms, such as a stripe arrangement, a pentile arrangement, a diamond arrangement, and a mosaic arrangement. Each pixel PX may include an organic light-emitting diode OLED as a display element (light-emitting device), and the organic light-emitting diode OLED may be connected to a pixel circuit. The pixel circuit may include a plurality of transistors and at least one capacitor. The pixel PX may be configured to emit, for example, red, green, blue, or white light through the organic light-emitting diode OLED. Each pixel PX may be connected to a corresponding gate line GL from among the plurality of gate lines GL, and a corresponding data line DL from among the plurality of data lines DL.

The gate lines GL may each extend in the x direction (a row direction) and be connected to the pixels PX located in the same row. The gate lines GL may each be configured to transmit a gate signal to the pixels PX in the same row. The data lines DL may each extend in the y direction (a column direction) and be connected to the pixels PX located in the same column. The data lines DL may each be configured to transmit a data signal to each of the pixels PX in the same column, in synchronization with the gate signal. Each pixel PX may be connected to a driving voltage line PL to receive a driving voltage ELVDD. The driving voltage lines PL may each extend in the y direction (column direction) to be connected to the pixels PX located in the same column.

InFIG.2, the pixel PX is connected to one gate line GL, but an embodiment of the disclosure is not limited thereto. The pixel PX may be connected to one or more gate lines GL in another embodiment.

Each of the pixel circuits configured to drive the pixels PX may be connected (e.g., electrically connected) to outer circuits arranged in the peripheral area PA. A first gate driving circuit DRV1, a second gate driving circuit DRV2, a terminal portion PAD, a driving voltage supply line11, and a common voltage supply line13may be arranged in the peripheral area PA.

According to an embodiment, the peripheral area PA may be a non-display area where the pixels PX are not arranged. According to another embodiment, a portion of the peripheral area PA may be embodied as the display area DA. For example, the plurality of pixels PX may be arranged by overlapping the outer circuit, in at least one corner of the peripheral area PA. Accordingly, a dead area may be reduced and the display area DA may be expanded.

The first gate driving circuit DRV1may be connected to the plurality of gate lines GL and configured to apply a gate signal to each of the pixel circuits configured to drive the pixels PX, through the gate lines GL. The second gate driving circuit DRV2may be located on an opposite side of the first gate driving circuit DRV1, with respect to the display area DA, and may be approximately parallel to the first gate driving circuit DRV1. According to an embodiment, the pixel circuits of the pixels PX of the display area DA may be connected (e.g., electrically connected) to the first gate driving circuit DRV1and the second gate driving circuit DRV2. According to another embodiment, some of the pixel circuits of the pixels PX of the display area DA may be connected (e.g., electrically connected) to the first gate driving circuit DRV1, and the remaining pixel circuits may be electrically connected to the second gate driving circuit DRV2. The second gate driving circuit DRV2may be omitted.

The terminal portion PAD may be arranged at one side of the substrate100. The terminal portion PAD may not be covered by an insulating layer, but may be exposed and connected to a display circuit board30. A display driving unit32may be arranged in the display circuit board30.

The display driving unit32includes a data driving circuit, wherein the data driving circuit may be connected to the plurality of data lines DL and configured to generate the data signal, and the generated data signal may be transmitted to the pixel circuits of the pixels PX through fanout lines FW and the data lines DL connected to the fanout lines FW.

The display driving unit32includes a power supply circuit, wherein the power supply circuit may be configured to supply the driving voltage ELVDD to the driving voltage supply line11and supply a common voltage ELVSS to the common voltage supply line13. The driving voltage ELVDD may be applied to the pixel circuits of the pixels PX through the driving voltage line PL connected to the driving voltage supply line11, and the common voltage ELVSS may be applied to an opposing electrode of the display element through the common voltage supply line13.

The display driving unit32includes a controller, wherein the controller may be configured to generate a control signal transmitted to the first gate driving circuit DRV1, the second gate driving circuit DRV2, the data driving circuit, and the power supply circuit.

The driving voltage supply line11may be connected to the terminal portion PAD and may extend in the x direction from below the display area DA. The common voltage supply line13may be connected to the terminal portion PAD and may partially surround the display area DA by having a loop shape in which one side is opened.

A portion or all of the first gate driving circuit DRV1and second gate driving circuit DRV2may be directly formed in the peripheral area PA of the substrate100during a process of configuring the pixel circuit in the display area DA of the substrate100. The display driving unit32may be formed in the form of an integrated circuit chip and disposed on the display circuit board30that is connected (e.g., electrically connected) to the terminal portion PAD arranged on one side of the substrate100. The display circuit board30may be a flexible printed circuit board (“FPCB”). According to another embodiment, the display driving unit32may be directly disposed on the substrate100in a chip-on-glass (“COG”) or chip-on-plastic (“COP”) manner.

According to an embodiment, the plurality of transistors included in the pixel circuits of the display area DA, and a plurality of transistors included in the outer circuits, for example, the first gate driving circuit DRV1and the second gate driving circuit DRV2, of the peripheral area PA may be N-type oxide thin-film transistors. The plurality of transistors included in the outer circuits of the peripheral area PA and the plurality of transistors included in the pixel circuits of the display area DA may be simultaneously formed through the same process. According to another embodiment, the plurality of transistors included in the pixel circuits of the display area DA may be N-type oxide thin-film transistors, and the plurality of transistors included in the outer circuits of the peripheral area PA may be a P-type silicon thin-film transistors.

A semiconductor layer of an oxide thin-film transistor may include an oxide. An oxide semiconductor may include, as a Zn oxide-based material, a Zn oxide, an In—Zn oxide, or a Ga—In—Zn oxide. According to some embodiments, the oxide semiconductor may be an In—Ga—Zn—O (“IGZO”) semiconductor, in which metals, such as indium (In) and gallium (Ga), are contained in ZnO. According to an embodiment, the oxide thin-film transistor may be a low temperature polycrystalline oxide (“LTPO”) thin-film transistor. A silicon thin-film transistor may be a low temperature poly-silicon (“LTPS”) thin-film transistor, in which a semiconductor layer includes amorphous silicon or polysilicon).

FIG.3is an equivalent circuit diagram of the pixel PX according to an embodiment.FIG.4is a diagram showing signals for describing an operation of the pixel PX ofFIG.3.

Referring toFIG.3, the pixel PX may include a pixel circuit PC and the organic light-emitting diode OLED, as a display element, connected to the pixel circuit PC.

The pixel PX may be connected to a first gate line GWL configured to transmit a first gate signal GW, a second gate line GIL configured to transmit a second gate signal GI, a third gate line GRL configured to transmit a third gate signal GR, a fourth gate line EML configured to transmit a fourth gate signal EM, a fifth gate line EMBL configured to transmit a fifth gate signal EMB, and the data line DL configured to transmit a data signal. Light emission of the pixel PX is controlled by the fourth gate signal EM and the fifth gate signal EMB, and thus the fourth gate signal EM and the fifth gate signal EMB may be referred to as emission control signals, and the fourth gate line EML and the fifth gate line EMBL may be referred to as emission control lines. Also, the pixel PX may be connected to the driving voltage line PL configured to transmit the driving voltage ELVDD, a reference voltage line VRL configured to transmit a reference voltage Vref, and an initialization voltage line VL configured to transmit an initialization voltage Vint.

According to an embodiment, the plurality of transistors included in the pixel circuit PC may be an N-type oxide thin-film transistor. An oxide thin-film transistor may be an LTPO thin-film transistor, in which a semiconductor layer includes an oxide. However, this is only an example, and the N-type transistors are not limited thereto. For another example, the semiconductor layer included in the N-type transistor may include an inorganic semiconductor (for example, amorphous silicon or polysilicon) or an organic semiconductor.

The pixel circuit PC may include first to sixth transistors T1to T6, and first and second capacitors C1and C2. The first transistor T1may be a driving transistor configured to output a driving current corresponding to the data signal, and the second to sixth transistors T2to T6may be switching transistors configured to transmit signals. A first terminal (first electrode) and a second terminal (second electrode) of each of the first to sixth transistors T1to T6may be a source or a drain, according to voltages of the first terminal and the second terminal. For example, according to the voltages of the first terminal and the second terminal, the first terminal may be a drain and the second terminal may be a source, or the first terminal may be a source and the second terminal may be a drain. A node to which a first gate of the first transistor T1is connected may be defined as a first node N1, and a node to which the second terminal of the first transistor T1is connected may be defined as a second node N2.

The first transistor T1may be connected between the driving voltage line PL and the second node N2. The first transistor T1may include a gate, the first terminal, and the second terminal connected to the second node N2. The first transistor T1may include the first gate connected to the first node N1. The first transistor T1may further include a second gate connected to its second terminal. The first gate and the second gate may be arranged on different layers while facing each other. For example, the first gate and second gate of the first transistor T1may face each other with a semiconductor layer therebetween.

The first gate of the first transistor T1may be connected to the second terminal of the second transistor T2, the first terminal of the third transistor T3, and the first capacitor C1. The second gate of the first transistor T1may be connected to the first terminal of the sixth transistor T6, the first capacitor C1, and the second capacitor C2. The first terminal of the first transistor T1may be connected to the driving voltage line PL via the fifth transistor T5, and the second terminal thereof may be connected to the organic light-emitting diode OLED via the sixth transistor T6. The first terminal of the first transistor T1may be connected to the second terminal of the fifth transistor T5. The second terminal of the first transistor T1may be connected to the first terminal of the sixth transistor T6, the first capacitor C1, and the second capacitor C2. The first transistor T1may be configured to control a current amount of the driving current flowing through the organic light-emitting diode OLED by receiving a data signal DATA according to a switching operation of the second transistor T2.

The second transistor T2(a write transistor) may be connected between the data line DL and the first gate of the first transistor T1. The second transistor T2may include a gate connected to the first gate line GWL, the first terminal connected to the data line DL, and the second terminal connected to the first node N1. The second terminal of the second transistor T2may be connected to the first gate of the first transistor T1, the first terminal of the third transistor T3, and the first capacitor C1. The second transistor T2is turned on by the first gate signal GW transmitted to the first gate line GWL to connect (e.g., electrically connect) the data line DL and the first node N1to each other, and may be configured to transmit the data signal DATA transmitted to the data line DL to the first node N1.

The third transistor T3(a first initialization transistor) may be connected between the first gate of the first transistor T1and the reference voltage line VRL (In other words, the reference voltage line VRL may be referred to as a “first voltage line”.). The third transistor T3may include a gate connected to the third gate line GRL, the first terminal connected to the first node N1, and the second terminal connected to the reference voltage line VRL. The first terminal of the third transistor T3may be connected to the first gate of the first transistor T1, the second terminal of the second transistor T2, and the first capacitor C1. The third transistor T3may be turned on by the third gate signal GR transmitted to the third gate line GRL to transmit the reference voltage Vref transmitted to the reference voltage line VRL to the first node N1.

The fourth transistor T4(a second initialization transistor or a reset transistor) may be connected between the sixth transistor T6and the initialization voltage line VL (In other words, the initialization voltage line VL may be referred to as a “second voltage line”.). The fourth transistor T4may be connected between the organic light-emitting diode OLED and the initialization voltage line VL. The fourth transistor T4may include a gate connected to the second gate line GIL, the first terminal connected to a third node N3, and the second terminal connected to the initialization voltage line VL. The first terminal of the fourth transistor T4may be connected to the second terminal of the sixth transistor T6and the organic light-emitting diode OLED. The fourth transistor T4may be turned on by the second gate signal GI transmitted to the second gate line GIL to transmit the initialization voltage Vint transmitted to the initialization voltage line VL to the third node N3.

The fifth transistor T5(a first emission control transistor) may be connected between the driving voltage line PL (In other words, the driving voltage line PL may be referred to as a “third voltage line”.) and the first transistor T1. The fifth transistor T5may include a gate connected to the fourth gate line EML, a first terminal connected to the driving voltage line PL, and a second terminal connected to the first terminal of the first transistor T1. The fifth transistor T5may be turned on or off according to the fourth gate signal EM transmitted to the fourth gate line EML.

The sixth transistor T6(a second emission control transistor) may be connected between the first transistor T1and the organic light-emitting diode OLED. The sixth transistor T6may be connected between the second node N2and the third node N3. The sixth transistor T6may include a gate connected to the fifth gate line EMBL, the first terminal connected to the second node N2, and the second terminal connected to the third node N3. The first terminal of the sixth transistor T6may be connected to the second terminal of the first transistor T1, the first capacitor C1, and the second capacitor C2. The second terminal of the sixth transistor T6may be connected to the first terminal of the fourth transistor T4and a pixel electrode of the organic light-emitting diode OLED. The sixth transistor T6may be turned on or off according to the fifth gate signal EMB transmitted to the fifth gate line EMBL.

The first capacitor C1may be connected between the first gate of the first transistor T1and the second terminal of the first transistor T1. A first electrode of the first capacitor C1may be connected to the first node N1and a second electrode thereof may be connected to the second node N2. The first electrode of the first capacitor C1may be connected to the first gate of the first transistor T1, the second terminal of the second transistor T2, and the first terminal of the third transistor T3. The second electrode of the first capacitor C1may be connected to the second terminal and second gate of the first transistor T1, the second electrode of the second capacitor C2, and the first terminal of the sixth transistor T6. The first capacitor C1may be configured to store a voltage corresponding to the data signal DATA and a threshold voltage of the first transistor T1, as a storage capacitor.

The second capacitor C2may be connected between the driving voltage line PL and the second node N2. A first electrode of the second capacitor C2may be connected to the driving voltage line PL. A second electrode of the second capacitor C2may be connected to the second terminal and second gate of the first transistor T1, the second electrode of the first capacitor C1, and the first terminal of the sixth transistor T6. Capacitance of the first capacitor C1may be greater than capacitance of the second capacitor C2.

The organic light-emitting diode OLED may be connected to the first transistor T1through the sixth transistor T6. The organic light-emitting diode OLED may include the pixel electrode (anode) connected to the third node N3and the opposing electrode (cathode) facing the pixel electrode, and the opposing electrode may receive the common voltage ELVSS. The opposing electrode may be a common electrode for the plurality of pixels PX.

The pixel PX may display an image in units of frames. Referring toFIG.4, one frame may include a non-emitting period NEP during which the pixel PX does not emit light, and an emitting period EP during which the pixel PX emits light. The non-emitting period NEP may include a first period P1, a second period P2, a third period P3, and a fourth period P4.

Each of the first gate signal GW, the second gate signal GI, the third gate signal GR, the fourth gate signal EM, and the fifth gate signal EMB may have a high-level voltage (first level voltage) for some periods and a low-level voltage (second level voltage) for some periods. Here, a high-level voltage may be a gate-on voltage for turning a transistor on, and a low-level voltage may be a gate-off voltage for turning a transistor off.

The first period P1may be a first initialization period where the first node N1connected to the first gate of the first transistor T1and the third node N3connected to the pixel electrode of the organic light-emitting diode OLED are initialized. During the first period P1, the second gate signal GI of a gate-on voltage may be supplied (applied) to the second gate line GIL, the third gate signal GR of a gate-on voltage may be supplied to the third gate line GRL, and the fifth gate signal EMB of a gate-on voltage may be supplied to the fifth gate line EMBL. During the first period P1, the first gate signal GW and the fourth gate signal EM may be supplied in gate-off voltages.

The sixth transistor T6may be turned on by the fifth gate signal EMB, the fourth transistor T4may be turned on by the second gate signal GI, and the third transistor T3may be turned on by the third gate signal GR. The first gate of the first transistor T1, i.e., the first node N1, may be initialized to the reference voltage Vref by the turned-on third transistor T3. The second terminal of the first transistor T1and the pixel electrode of the organic light-emitting diode OLED may be initialized to the initialization voltage Vint by the turned-on sixth transistor T6and turned-on fourth transistor T4. The pixel electrode of the organic light-emitting diode OLED is reset to the initialization voltage Vint during the first period P1, and thus the first period P1may be referred to as a reset period.

The second period P2may be a compensation period where the threshold voltage of the first transistor T1is compensated for. During the second period P2, the third gate signal GR of a gate-on voltage may be supplied to the third gate line GRL, and the fourth gate signal EM of a gate-on voltage may be supplied to the fourth gate line EML. The first gate signal GW, the second gate signal GI, and the fifth gate signal EMB may be supplied in gate-off voltages.

The third transistor T3may be turned on by the third gate signal GR, and the fifth transistor T5may be turned on by the fourth gate signal EM. Accordingly, the first transistor T1may be turned on as the reference voltage Vref is supplied to the first node N1and the driving voltage ELVDD is supplied to the first terminal of the first transistor T1. The first transistor T1may be turned off when a voltage of the second terminal of the first transistor T1reaches a difference (Vref-Vth) between the reference voltage Vref and a threshold voltage Vth of the first transistor T1. The threshold voltage Vth of the first transistor T1may be compensated for, as a voltage corresponding to the threshold voltage Vth of the first transistor T1is stored in the first capacitor C1.

The third period P3may be a write period where a data signal is supplied to the pixel PX. During the third period P3, the first gate signal GW of a gate-on voltage may be supplied to the first gate line GWL. The second gate signal GI, the third gate signal GR, the fourth gate signal EM, and the fifth gate signal EMB may be supplied in gate-off voltages.

The second transistor T2may be turned on by the first gate signal GW, and the turned-on second transistor T2may be configured to transmit the data signal DATA from the data line DL to the first node N1, i.e., the first gate of the first transistor T1. Accordingly, a voltage of the first node N1may be changed from the reference voltage Vref to a voltage corresponding to the data signal DATA. Here, a voltage of the second node N2may also change in response to a voltage change amount of the first node N1. A voltage of the second node N2may be a voltage (Vref−Vth+α×(DATA−Vref)) changed according to a capacity ratio (α=C1/(C1+C2)) of the first capacitor C1and the second capacitor C2. Accordingly, the threshold voltage Vth of the first transistor T1and the voltage corresponding to the data signal DATA may be charged in the first capacitor C1.

The fourth period P4may be a second initialization period where the second node N2connected to the second terminal of the first transistor T1and the third node N3connected to the pixel electrode of the organic light-emitting diode OLED are initialized before the emitting period EP after data write. The second gate signal GI of a gate-on voltage may be supplied to the second gate line GIL, and the fifth gate signal EMB of a gate-on voltage may be supplied to the fifth gate line EMBL. Also, the first gate signal GW, the third gate signal GR, and the fourth gate signal EM may be supplied in gate-off voltages.

The fourth transistor T4may be turned on by the second gate signal GI, and the sixth transistor T6may be turned on by the fifth gate signal EMB. The initialization voltage Vint may be transmitted to the pixel electrode of the organic light-emitting diode OLED by the turned-on fourth transistor T4, and the second node N2and the third node N3may share an electric charge by the turned-on sixth transistor T6.

The emitting period EP may be a period during which the organic light-emitting diode OLED emits light. During the emitting period EP, the fourth gate signal EM of a gate-on voltage may be supplied to the fourth gate line EML and the fifth gate signal EMB of a gate-on voltage may be supplied to the fifth gate line EMBL. The first gate signal GW, the second gate signal GI, and the third gate signal GR may be supplied in gate-off voltages.

The fifth transistor T5may be turned on by the fourth gate signal EM, and the driving voltage ELVDD may be supplied to the first terminal of the first transistor T1by the turned-on fifth transistor T5. The first transistor T1may output a voltage corresponding to the data signal DATA, which was stored in the first capacitor C1, i.e., a driving current (Id(Vgs-Vth)2) having magnitude corresponding to a voltage (Vgs-Vth) obtained by subtracting the threshold voltage Vth of the first transistor T1from a gate-source voltage Vgs of the first transistor T1, the driving current may flow through the organic light-emitting diode OLED through the sixth transistor T6turned on by the fifth gate signal EMB, and the organic light-emitting diode OLED may emit light of luminance corresponding to the magnitude of the driving current.

FIG.5is a diagram schematically showing the display device1according to an embodiment.FIG.6is a diagram schematically showing a portion of a gate driving circuit130ofFIG.5.FIG.7is a diagram showing gate signals output by the gate driving circuit130ofFIG.5.FIG.7illustrates examples of gate signals supplied to an n-th row and an (n+1)th row. Hereinafter, for convenience of description, the pixel PX arranged in an arbitrary row and gate signals supplied to an arbitrary row will be described as examples.

As shown inFIG.5, the display device1may include a pixel unit110, the gate driving circuit130, a data driving circuit150, a power supply circuit170, and a controller190.

The pixel unit110may be provided in the display area DA. Various conductive lines configured to transmit an electric signal to be applied to the display area DA, outer circuits connected (e.g., electrically connected) to pixel circuits, and pads to which a printed circuit board or a driver IC chip is attached may be located in the peripheral area PA. For example, the gate driving circuit130, the data driving circuit150, the power supply circuit170, and the controller190may be provided in the peripheral area PA.

A plurality of gate lines are spaced apart from each other in the y direction (for example, the column direction) at regular intervals, in the pixel unit110. The gate lines may each extend in the x direction (for example, the row direction) and be connected to the pixels PX located in the same row (row line). In an embodiment, for example, the gate lines may include the first gate lines GWL, the second gate lines GIL, the third gate lines GRL, the fourth gate lines EML, and the fifth gate lines EMBL, and the first gate lines GWL, the second gate lines GIL, the third gate lines GRL, the fourth gate lines EML, and the fifth gate lines EMBL may be arranged in each row.

A plurality of data lines may be spaced apart from each other in the x direction at regular intervals, in the pixel unit110. The data lines may each extend in the y direction and be connected to the pixels PX located in the same column (a column line).

The gate driving circuit130may be connected to the gate lines and configured to apply gate signals sequentially to the gate lines. The gate line may be connected to a gate of a transistor included in the pixel PX. The gate signal may be a gate control signal controlling on or off of the transistor. The gate signal may be a square wave signal including a gate-on voltage for turning the transistor on, and a gate-off voltage for turning the transistor off. According to an embodiment, a gate-on voltage may be a low-level voltage (first level voltage) or a high-level voltage (second level voltage).

The gate driving circuit130may include a first gate driving circuit130L arranged at a left side of the pixel unit110and a second gate driving circuit130R arranged at a right side of the pixel unit110. The first gate driving circuit130L and the second gate driving circuit130R may each include a first driving circuit131, a second driving circuit133, a third driving circuit135, a fourth driving circuit137, and a fifth driving circuit139.

The first driving circuit131may be connected to the plurality of first gate lines GWL, and configured to supply the first gate signal GW sequentially to the first gate lines GWL according to a first control signal GCS1. The second driving circuit133may be connected to the plurality of fourth gate lines EML, and configured to supply the fourth gate signal EM sequentially to the fourth gate lines EML according to a second control signal GCS2. The third driving circuit135may be connected to the plurality of third gate lines GRL, and configured to supply the third gate signal GR sequentially to the third gate lines GRL according to a third control signal GCS3. The fourth driving circuit137may be connected to the plurality of second gate lines GIL, and configured to supply the second gate signal GI sequentially to the second gate lines GIL according to a fourth control signal GCS4. The fifth driving circuit139may be connected to the plurality of fifth gate lines EMBL, and configured to supply the fifth gate signal EMB sequentially to the fifth gate lines EMBL according to a fifth control signal GCS5.

The data driving circuit150may be connected to the plurality of data lines DL, and configured to apply the data signal DATA indicating a grayscale to the data lines DL according to a sixth control signal DCS. The data driving circuit150may be configured to convert input image data having a grayscale input from the controller190into the data signal DATA in the form of a voltage or current.

The power supply circuit170may be configured to generate voltages to drive the pixel PX, according to a seventh control signal PCS. In an embodiment, for example, the power supply circuit170may be configured to generate the driving voltage ELVDD and the common voltage ELVSS, and supply the same to the pixels PX. The driving voltage ELVDD may be a high-level voltage provided to one end of a driving transistor connected to a first electrode (a pixel electrode or anode) of a display element included in the pixel PX. The common voltage ELVSS may be a low-level voltage provided to a second electrode (an opposing electrode or cathode) of the display element included in the pixel PX. The power supply circuit170may be configured to generate the reference voltage Vref and the initialization voltage Vint, and supply the same to the pixels PX. A voltage level of the driving voltage ELVDD may be greater than a voltage level of the common voltage ELVSS. A voltage level of the reference voltage Vref may be lower than the voltage level of the driving voltage ELVDD. A voltage level of the initialization voltage Vint may be lower than the voltage level of the common voltage ELVSS.

The power supply circuit170may be configured to generate a first voltage VGH and a second voltage VGL, which are to drive the gate driving circuit130, and transmit the same to the gate driving circuit130. A voltage level of the first voltage VGH may be greater than a voltage level of the second voltage VGL.

Referring toFIG.6, the first driving circuit131, the second driving circuit133, the third driving circuit135, the fourth driving circuit137, and the fifth driving circuit139may each include a plurality of stages, and each stage may be configured to receive at least one clock signal and at least one voltage signal, and generate a corresponding gate signal.

The first driving circuit131may include a plurality of stages WST1, WST2, WST3, WST4, and so on, which are sequentially connected to each other, and the plurality of stages WST1, WST2, WST3, WST4, and so on may correspond to rows of the pixel unit110, respectively. Each of the plurality of stages WST1, WST2, WST3, WST4, and so on may be configured to generate the first gate signal GW and output the same to the first gate line GWL of a corresponding row. The first gate signals GW output by the plurality of stages WST1, WST2, WST3, WST4, and so on may be sequentially shifted. In an embodiment, for example, the first gate signals GW may be sequentially output while being shifted at intervals of 1 horizontal period (“H”). Here, 1H may be 1/(driving frequency×vertical resolution). The number of stages of the first driving circuit131may be the same as the number of rows or the number of first gate lines GWL.

The second driving circuit133may include a plurality of stages EST1, EST2, and so on, which are sequentially connected to each other, and the plurality of stages EST1, EST2, and so on may each correspond to two rows (a pair of rows) of the pixel unit110. Each of the plurality of stages EST1, EST2, and so on may be configured to generate the fourth gate signal EM and transmit the same to the fourth gate lines EML of the corresponding two rows. For example, the fourth gate signal EM may be simultaneously supplied to the two fourth gate lines EML arranged in the two rows, respectively. According to an embodiment, each of the plurality of stages EST1, EST2, and so on includes two output terminals, i.e., a first output terminal and a second output terminal, wherein one of two fourth gate lines EML may be connected to the first output terminal and the other one of the two fourth gate lines EML may be connected to the second output terminal. According to another embodiment, each of the plurality of stages EST1, EST2, and so on includes one output terminal, and the two fourth gate lines EML may be connected to the output terminal. The fourth gate signals EM output by the plurality of stages EST1, EST2, and so on may be sequentially shifted. For example, the fourth gate signals EM may be sequentially output while being shifted at intervals of 2H (2 horizontal periods). The number of stages of the second driving circuit133may be ½ of the number of rows or the number or ½ of the number of fourth gate lines EML.

The third driving circuit135may include a plurality of stages RST1, RST2, and so on, which are sequentially connected to each other, and the plurality of stages RST1, RST2, and so on may each correspond to two rows (a pair of rows) of the pixel unit110. Each of the plurality of stages RST1, RST2, and so on may be configured to generate the third gate signal GR and transmit the same to the third gate lines GRL of the corresponding two rows. For example, the third gate signal GR may be simultaneously supplied to the two third gate lines GRL arranged in the two rows, respectively. According to an embodiment, each of the plurality of stages RST1, RST2, and so on includes two output terminals, i.e., a first output terminal and a second output terminal, wherein one of two third gate lines GRL may be connected to the first output terminal and the other one of the two third gate lines GRL may be connected to the second output terminal. According to another embodiment, each of the plurality of stages RST1, RST2, and so on includes one output terminal, and the two third gate lines GRL may be connected to the output terminal. The third gate signals GR output by the plurality of stages RST1, RST2, and so on may be sequentially shifted. For example, the third gate signals GR may be sequentially output while being shifted at intervals of 2H (2 horizontal periods). The number of stages of the third driving circuit135may be ½ of the number of rows or the number or ½ of the number of third gate lines GRL.

The fourth driving circuit137may include a plurality of stages IST1, IST2, and so on, which are sequentially connected to each other, and the plurality of stages IST1, IST2, and so on may each correspond to two rows (a pair of rows) of the pixel unit110. Each of the plurality of stages IST1, IST2, and so on may be configured to generate the second gate signal GI and transmit the same to the second gate lines GIL of the corresponding two rows. For example, the second gate signal GI may be simultaneously supplied to the two second gate lines GIL arranged in the two rows, respectively. According to an embodiment, each of the plurality of stages IST1, IST2, and so on includes two output terminals, i.e., a first output terminal and a second output terminal, wherein one of two second gate lines GIL may be connected to the first output terminal and the other one of the two second gate lines GIL may be connected to the second output terminal. According to another embodiment, each of the plurality of stages IST1, IST2, and so on includes one output terminal, and the two second gate lines GIL may be connected to the output terminal. The second gate signals GI output by the plurality of stages IST1, IST2, and so on may be sequentially shifted. For example, the second gate signals GI may be sequentially output while being shifted at intervals of 2H (2 horizontal periods). The number of stages of the fourth driving circuit137may be ½ of the number of rows or the number or ½ of the number of second gate lines GIL.

The fifth driving circuit139may include a plurality of stages BST1, BST2, and so on, which are sequentially connected to each other, and the plurality of stages BST1, BST2, and so on may each correspond to two rows (a pair of rows) of the pixel unit110. Each of the plurality of stages BST1, BST2, and so on may be configured to generate the fifth gate signal EMB and transmit the same to the fifth gate lines EMBL of the corresponding two rows. For example, the fifth gate signal EMB may be simultaneously supplied to the two fifth gate lines EMBL arranged in the two rows, respectively. According to an embodiment, each of the plurality of stages BST1, BST2, and so on includes two output terminals, i.e., a first output terminal and a second output terminal, wherein one of two fifth gate lines EMBL may be connected to the first output terminal and the other one of the two fifth gate lines EMBL may be connected to the second output terminal. According to another embodiment, each of the plurality of stages BST1, BST2, and so on includes one output terminal, and the two fifth gate lines EMBL may be connected to the output terminal. The fifth gate signals EMB output by the plurality of stages BST1, BST2, and so on may be sequentially shifted. For example, the fifth gate signals EMB may be sequentially output while being shifted at intervals of 2H (2 horizontal periods). The number of stages of the fifth driving circuit139may be ½ of the number of rows or the number or ½ of the number of fifth gate lines EMBL.

As shown inFIG.6, the first stage WST1of the first driving circuit131may be configured to output a first first-gate signal GW1to a first gate line GWL1connected to a first pixel PX1arranged in a first row, and the second stage WST2may be configured to output a second first-gate signal GW2to a first gate line GWL2connected to a second pixel PX2arranged in a second row.

The fourth gate signal EM output by the first stage EST1of the second driving circuit133may be simultaneously supplied as a first fourth-gate signal EM1to a fourth gate line EML1connected to the first pixel PX1, and as a second fourth-gate signal EM2to a fourth gate line EML2connected to the second pixel PX2. The fourth gate signal EM output by the second stage EST2of the second driving circuit133may be simultaneously supplied as a third-fourth gate signal EM3to a fourth gate line EML3to a third pixel PX3arranged in a third row, and as a fourth fourth-gate signal EM4to a fourth gate line EML4connected to a fourth pixel PX4arranged in a fourth row.

The third gate signal GR output by the first stage RST1of the third driving circuit135may be simultaneously supplied as a first third-gate signal GR1to a third gate line GRL1connected to the first pixel PX1, and as a second third-gate signal GR2to a third gate line GRL2connected to the second pixel PX2. The third gate signal GR output by the second stage RST2of the third driving circuit135may be simultaneously supplied as a third third-gate signal GR3to a third gate line GRL3connected to the third pixel PX3, and as a fourth third-gate signal GR4to a third gate line GRL4connected to the fourth pixel PX4.

The second gate signal GI output by the first stage IST1of the fourth driving circuit137may be simultaneously supplied as a first second-gate signal G11to a second gate line GIL1connected to the first pixel PX1, and as a second second-gate signal G12to a second gate line GIL2connected to the second pixel PX2. The second gate signal GI output by the second stage IST2of the fourth driving circuit137may be simultaneously supplied as a third second-gate signal G13to a second gate line GIL3connected to the third pixel PX3, and as a fourth second-gate signal G14to a second gate line GIL4connected to the fourth pixel PX4.

The fifth gate signal EMB output by the first stage BST1of the fifth driving circuit139may be simultaneously supplied as a first fifth-gate signal EMB1to a fifth gate line EMBL1connected to the first pixel PX1, and as a second fifth-gate signal EMB2to a fifth gate line EMBL2connected to the second pixel PX2. The fifth gate signal EMB output by the second stage BST2of the fifth driving circuit139may be simultaneously supplied as a third-fifth gate signal EMB3to a fifth gate line EMBL3connected to the third pixel PX3, and as a fourth fifth-gate signal EMB4to a fifth gate line EMBL4connected to the fourth pixel PX4.

In the same way, as shown inFIG.7, the second gate signal GI, the third gate signal GR, the fourth gate signal EM, and the fifth gate signal EMB may be applied to an n-th pixel arranged in an n-th row and an (n+1)th pixel arranged in an (n+1)th row, and a first gate signal GW[n] and a first gate signal GW[n+1] may be sequentially applied to the n-th pixel and the (n+1)th pixel.

Locations of the first driving circuit131, second driving circuit133, third driving circuit135, fourth driving circuit137, and fifth driving circuit139are not limited to those shown inFIGS.5and6. Various embodiments may be realized, for example, locations of some driving circuits may be changed by changing some gate signals supplied to the pixel PX, and one of bisymmetric driving circuits may be omitted.

FIG.8is a diagram schematically showing a display device1aaccording to an embodiment.FIG.9is a diagram schematically showing a portion of a gate driving circuit130aofFIG.8.FIGS.10A to10Care diagrams schematically showing some stages, for describing an operation of a pixel ofFIG.8.FIG.11is a diagram showing a pixel PXn arranged in an n-th row in the pixel unit110ofFIG.8.FIG.12is a diagram showing gate signals output by the gate driving circuit130aofFIG.8. InFIGS.8to12, like reference numerals are used for elements, periods, and signals described with reference toFIGS.3to7, and redundant descriptions thereof will be omitted.

Referring toFIG.8, the gate driving circuit130aof the display device1amay include a first gate driving circuit130La and a second gate driving circuit130Ra. The first gate driving circuit130La and the second gate driving circuit130Ra may each include a first driving circuit131a, a second driving circuit133a, and a third driving circuit135a.

Referring toFIG.9, the first driving circuit131amay include a plurality of stages WST1to WST2m, which are sequentially connected to each other, and each of the plurality of stages WST1to WST2mmay correspond to each of rows of the pixel unit110. The first driving circuit131amay be substantially the same as or similar to the first driving circuit131ofFIG.5.

The second driving circuit133amay include a plurality of stages EST1to ESTm, which are sequentially connected to each other. The plurality of stages EST1to ESTm may each correspond to two rows (a pair of rows) of the pixel unit110. Each of the plurality of stages EST1to ESTm may be configured to generate the fourth gate signal EM and supply the same simultaneously to the two fourth gate lines EML arranged in the two rows, respectively. The second driving circuit133amay further include a plurality of dummy stages DEST1, DEST2, and so on, which are sequentially connected to the last stage ESTm.

Some of the plurality of stages EST1to ESTm and the plurality of dummy stages DEST1, DEST2, and so on of the second driving circuit133amay each be configured to supply, as the fifth gate signal EMB, the fourth gate signal EM to the fifth gate lines EMBL of two rows other than the corresponding two rows. According to an embodiment, some of the plurality of stages EST1to ESTm may be configured to output, as the fifth gate signal EMB, the fourth gate signal EM to a pair of the fifth gate lines EMBL arranged in a pair of rows forward the corresponding pair of rows. Each of the plurality of dummy stages DEST1, DEST2, and so on may be configured to output, as the fifth gate signal EMB, the fourth gate signal EM to a pair of fifth gate lines EMBL arranged in a pair of rows from among rows from an (2m)th row that is the last row to certain rows.

The third driving circuit135amay include a plurality of stages RST1to RSTm, which are sequentially connected to each other. The plurality of stages RST1to RSTm may each correspond to two rows (a pair of rows) of the pixel unit110. Each of the plurality of stages RST1to RSTm may be configured to generate the third gate signal GR and supply the same simultaneously to the two third gate lines GRL arranged in the two rows, respectively. The third driving circuit135amay further include a plurality of dummy stages DRST1, DRST2, and so on, which are sequentially connected to the first stage RST1.

Some of the plurality of stages RST1to RSTm and the plurality of dummy stages DRST1, DRST2, and so on of the third driving circuit135amay each be configured to supply, as the second gate signal GI, the third gate signal GR to the second gate lines GIL of two rows other than the corresponding two rows. According to an embodiment, some of the plurality of stages RST1to RSTm may be configured to output, as the second gate signal GI, the third gate signal GR to a pair of the second gate lines GIL arranged in a pair of rows backward the corresponding pair of rows. Each of the plurality of dummy stages DRST1, DRST2, and so on may be configured to output, as the second gate signal GI, the third gate signal GR to a pair of second gate lines GIL arranged in a pair of rows from among rows from the first row to certain rows.

Referring toFIGS.10A to10Ctogether, the first driving circuit131amay be connected to the plurality of first gate lines GWL, and configured to supply the first gate signal GW sequentially to the first gate lines GWL according to the first control signal GCS1.

The second driving circuit133amay be connected to the plurality of fourth gate lines EML, and configured to supply the fourth gate signal EM sequentially to the fourth gate lines EML according to the second control signal GCS2. Also, the second driving circuit133amay be connected to the plurality of fifth gate lines EMBL, and configured to supply the fifth gate signal EMB sequentially to the fifth gate lines EMBL according to the second control signal GCS2. The pixel PX may be configured to receive, as the fifth gate signal EMB, the fourth gate signal EM shifted from the fourth gate signal EM by a certain period, from the fifth gate line EMBL.

The third driving circuit135amay be connected to the plurality of third gate lines GRL, and configured to supply the third gate signal GR sequentially to the third gate lines GRL according to the third control signal GCS3. Also, the third driving circuit135amay be connected to the plurality of second gate lines GIL, and configured to supply the second gate signal GI sequentially to the second gate lines GIL according to the third control signal GCS3. The pixel PX may be configured to receive, as the second gate signal GI, the third gate signal GR shifted from the third gate signal GR by a certain period, from the second gate line GIL.

Referring toFIG.10A, the first pixel PX1arranged in the first row may be configured to receive the first first-gate signal GW1through the first first-gate line GWL1from the first stage WST1of the first driving circuit131a, and the second pixel PX2arranged in the second row may be configured to receive the second first-gate signal GW2through the second first-gate line GWL2from the second stage WST2of the first driving circuit131a.

The fourth gate signal EM output by the first stage EST1of the second driving circuit133aand the third gate signal GR output by the first stage RST1of the third driving circuit135amay be simultaneously supplied to the first pixel PX1and the second pixel PX2.

The first pixel PX1may be configured to receive the first fourth-gate signal EM1through the first fourth-gate line EML1from the first stage EST1of the second driving circuit133a, and receive the first third-gate signal GR1through the first third-gate line GRL1from the first stage RST1of the third driving circuit135a. The second pixel PX2may be configured to receive the second fourth-gate signal EM2through the second fourth-gate line EML2from the first stage EST1of the second driving circuit133a, and receive the second third-gate signal GR2through the second third-gate line GRL2from the first stage RST1of the third driving circuit135a.

Each of the first pixel PX1and the second pixel PX2may be configured to receive the fourth gate signal EM output to the fourth gate line EML of a corresponding row by a next stage after a certain number from the first stage EST1of the second driving circuit133a, as the first fifth-gate signal EMB1through the first fifth-gate line EMBL1and as the second fifth-gate signal EMB2through the second fifth-gate line EMBL2.

Each of the first pixel PX1and the second pixel PX2may be configured to receive a signal DGR1output by a first dummy stage DRST1of the third driving circuit135a, as the first second-gate signal G11through the first second-gate line GIL1and as the second second-gate signal G12through the second second-gate line GIL2.

The third gate signal GR output by each of the first stage RST1and second stage RST2of the third driving circuit135amay be supplied to the second gate line GIL of each row corresponding to the next stage after the certain number.

Referring toFIG.10B, the n-th pixel PXn arranged in the n-th row may be configured to receive an n-th first gate signal GWn through an n-th first gate line GWLn from an n-th stage WSTn of the first driving circuit131a, and an (n+1)th pixel PXn+1 arranged in an (n+1)th row may be configured to receive an (n+1)th first gate signal GWn+1 through an (n+1)th first gate line GWLn+1 from an (n+1)th stage WSTn+1 of the first driving circuit131a.

The fourth gate signal EM output by a k-th stage ESTk (k=(n+1)/2) of the second driving circuit133aand the third gate signal GR output by a k-th stage RSTk of the third driving circuit135amay be simultaneously supplied to the n-th pixel PXn and the (n+1)th pixel PXn+1.

The n-th pixel PXn may be configured to receive an n-th fourth gate signal EMn through an n-th fourth gate line EMLn from the k-th stage ESTk of the second driving circuit133a, and receive an n-th third gate signal GRn through an n-th third gate line GRLn from the k-th stage RSTk of the third driving circuit135a. The (n+1)th pixel PXn+1 may be configured to receive an (n+1)th fourth gate signal EMn+1 through an (n+1)th fourth gate line EMLn+1 from the k-th stage ESTk of the second driving circuit133a, and receive an (n+1)th third gate signal GRn+1 through an (n+1)th third gate line GRLn+1 from the k-th stage RSTk of the third driving circuit135a.

The fourth gate signal EM output by a q-th stage ESTq (q=(j+1)/2, where q is a natural number greater than k and j is a natural number greater than n) of the second driving circuit133amay be supplied as a j-th fourth gate signal EMj through a j-th fourth gate line EMLj to a j-th pixel PXj arranged in a j-th row and supplied as a (j+1)th fourth gate signal EMj+1 through a (j+1)th fourth gate line EMLj+1 to a (j+1)th pixel PXj+1 arranged in a (j+1)th row. Also, the fourth gate signal EM output by the q-th stage ESTq of the second driving circuit133amay be supplied to the n-th pixel PXn as an n-th fifth gate signal EMBn through an n-th fifth gate line EMBLn, and supplied as an (n+1)th fifth gate signal EMBn+1 through an (n+1)th fifth gate line EMBLn+1. Accordingly, the n-th fifth gate signal EMBn of the n-th pixel PXn and the (n+1)th fifth gate signal EMBn+1 of the (n+1)th pixel PXn+1 may be the same as the j-th fourth gate signal EMj and the (j+1)th fourth gate signal EMj+1.

The third gate signal GR output by a p-th stage RSTp (p=(i+1)/2, wherein p is a natural number lower than k and i is a natural number lower than n) of the third driving circuit135amay be supplied as an i-th third gate signal GRi through an i-th third gate line GRLi to an i-th pixel PXi arranged in an i-th row, and supplied as an (i+1)th third gate signal GRi+1 through an (i+1)th third gate line GRLi+1 to an (i+1)th pixel PXi+1 arranged in an (i+1)th row. Also, the third gate signal GR output by the p-th stage RSTp of the third driving circuit135amay be supplied to the n-th pixel PXn as an n-th second gate signal Gin through an n-th second gate line GILn, and to the (n+1)th pixel PXn+1 as an (n+1)th second gate signal GIn+1 through an (n+1)th second gate line GILn+1. Accordingly, the n-th second gate signal Gin of the n-th pixel PXn and the (n+1)th second gate signal GIn+1 of the (n+1)th pixel PXn+1 may be the same as the i-th third gate signal GRi and the (i+1)th third gate signal GRi+1.

The fourth gate signal EM output by each of a p-th stage ESTp and the k-th stage ESTk of the second driving circuit133amay be supplied to the fifth gate line EMBL of each row corresponding to a previous stage before a certain number.

The third gate signal GR output by each of the k-th stage RSTk and a q-th stage RSTq of the third driving circuit135amay be supplied to the second gate line GIL of each row corresponding to the next stage after the certain number.

Referring toFIG.10C, a (2m-1)th pixel PX2m-1arranged in an (2m-1)th row may be configured to receive a (2m-1)th first gate signal GW2m-1through a (2m-1)th first gate line GWL2m-1from a (2m-1)th stage WST2m-1of the first driving circuit131a, and a (2m)th pixel PX2marranged in a (2m)th row may be configured to receive a (2m)th first gate signal GW2mthrough a (2m)th first gate line GWL2mfrom a (2m)th stage WST2mof the first driving circuit131a.

The fourth gate signal EM output by the m-th stage ESTm of the second driving circuit133aand the third gate signal GR output by an m-th stage RSTm of the third driving circuit135amay be simultaneously supplied to the (2m-1)th pixel PX2m-1and the (2m)th pixel PX2m.

The (2m-1)th pixel PX2m-1may be configured to receive a (2m-1)th fourth gate signal EM2m-1 through a (2m-1)th fourth gate line EML2m-1from the m-th stage ESTm of the second driving circuit133a, and receive a (2m-1)th third gate signal GR2m-1through a (2m-1)th third gate line GRL2m-1from the m-th stage RSTm of the third driving circuit135a. The (2m)th pixel PX2mmay be configured to receive a (2m)th fourth gate signal EM2mthrough a (2m)th fourth gate line EML2mfrom the m-th stage ESTm of the second driving circuit133a, and receive a (2m)th third gate signal GR2mthrough a (2m)th third gate line GRL2mfrom the m-th stage RSTm of the third driving circuit135a.

Each of the (2m-1)th pixel PX2m-1and the (2m)th pixel PX2mmay be configured to receive a signal DEM1output by the first dummy stage DEST1of the second driving circuit133aas a (2m-1)th fifth gate signal EMB2m-1through a (2m-1)th fifth gate line EMBL2m-1, and as a (2m)th fifth gate signal EMB2mthrough a (2m)th fifth gate line EMBL2m.

The fourth gate signal EM output by each of the m-th stage ESTm and an (m-1)th stage ESTm-1of the second driving circuit133amay be supplied to the fifth gate line EMBL of each row corresponding to the previous stage before the certain number.

According to an embodiment, the i-th row is a row spaced apart from the n-th row by 30 rows forward, and the j-th row may be a row spaced apart from the n-th row by 28 rows backward. In this case, the third driving circuit135amay include 15 dummy stages DRST1to DRST15, and the second driving circuit133amay include 14 dummy stages DEST1to DEST14. Some stages RST1to RSTm-15from among the plurality of stages RST1to RSTm and the dummy stages DRST1to DRST15may each be configured to supply the third gate signal GR as the second gate signal GI to a pair of second gate lines GIL corresponding to a stage RST spaced apart by 15 stages backward. Some stages EST15to ESTm from among the plurality of stages EST1to ESTm and the dummy stages DEST1to DEST14may each be configured to supply the fourth gate signal EM as the fifth gate signal EMB to a pair of fifth gate lines EMBL corresponding to a stage EST spaced apart by 14 stages forward. When the third gate signals GR and the fourth gate signals EM output by neighboring stages are shifted by 2H (2 horizontal periods), the n-th third gate signal GRn may be output by being shifted by t1(e.g., 30H: 30 horizontal periods) from the i-th third gate signal GRi, and the j-th fourth gate signal EMj may be output by being shifted by t2(e.g., 28H: 28 horizontal periods) from the n-th fourth gate signal EMn, as shown inFIG.12.

Referring toFIG.11, the pixel PX included in the pixel unit110of the display device1adiffers from the pixel PX shown inFIG.3in that the fourth transistor T4is configured to receive the third gate signal GR as the second gate signal GI and the sixth transistor T6is configured to receive the fourth gate signal EM as the fifth gate signal EMB.

Referring toFIG.12, the fourth period P4from among the first to fourth periods P1to P4ofFIG.7may be omitted. Hereinafter, the n-th pixel PXn will be described as an example.

During the first period P1, the i-th third gate signal GRi of a gate-on voltage may be supplied (applied) as the n-th second gate signal GIn to the n-th second gate line GILn, the j-th fourth gate signal EMj of a gate-on voltage may be supplied as the n-th fifth gate signal EMBn to the n-th fifth gate line EMBLn, and the n-th third gate signal GRn of a gate-on voltage may be supplied to the n-th third gate line GRLn. The first gate of the first transistor T1may be initialized to the reference voltage Vref by the turned-on third transistor T3. The second terminal of the first transistor T1and the pixel electrode of the organic light-emitting diode OLED may be initialized to the initialization voltage Vint by the turned-on sixth transistor T6and turned-on fourth transistor T4.

During the second period P2, the n-th third gate signal GRn of a gate-on voltage may be supplied to the n-th third gate line GRLn, and the n-th fourth gate signal EMn of a gate-on voltage may be supplied to the n-th fourth gate line EMLn. The threshold voltage Vth of the first transistor T1may be compensated for by the turned-on third transistor T3and fifth transistor T5.

During the emitting period EP, the n-th fourth gate signal EMn and the j-th fourth gate signal EMj shifted from the n-th fourth gate signal EMn by t2may be sequentially supplied in gate-on voltages. The organic light-emitting diode OLED may emit light by the turned-on fifth transistor T5and sixth transistor T6.

During the emitting period EP, when the fifth transistor T5and the sixth transistor T6are simultaneously turned on while a certain voltage is applied to each of the second node N2and third node N3of the pixel PX, i.e., to each of the first terminal and second terminal of the sixth transistor T6, a voltage of the third node N3may be changed by a voltage difference between the first terminal and second terminal of the sixth transistor T6. According to an embodiment of the disclosure, during the emitting period EP, the gate-on voltage of the fifth gate signal EMB may be delayed by the certain time t2than a gate-on voltage applying timing of the fourth gate signal EM. For example, the voltage difference between the first terminal and second terminal of the sixth transistor T6may be reduced before the sixth transistor T6is turned on, by using the j-th fourth gate signal EMj shifted from the n-th fourth gate signal EMn by t2as the n-th fifth gate signal EMBn of the n-th pixel PXn. Accordingly, voltage fluctuation of the third node N3may be reduced, thereby reducing occurrence of a flicker phenomenon.

In the present embodiment, the third gate signal GR output by the third driving circuit135aand the fourth gate signal EM output by the second driving circuit133amay be used as the second gate signal GI and the fifth gate signal EMB, and thus the fourth driving circuit137and the fifth driving circuit139ofFIG.5may be omitted, thereby reducing a non-display area. According to another embodiment, a fourth driving circuit configured to output the second gate signal GI may be further provided such that the fourth transistor T4may be configured to receive the second gate signal GI from the fourth driving circuit and use the fourth gate signal EM output by the second driving circuit133aas the fifth gate signal EMB. In this case, only the fifth driving circuit139may be omitted.

FIG.13is a diagram schematically showing a display device1baccording to an embodiment.FIG.14is a diagram schematically showing a portion of a gate driving circuit130bofFIG.13.FIGS.15A to15Care diagrams schematically showing some stages, for describing an operation of a pixel ofFIG.13.FIG.16is a diagram showing the n-th pixel PXn arranged in the n-th row in the pixel unit110ofFIG.13.FIG.17is a diagram showing gate signals output by the gate driving circuit130bofFIG.13. InFIGS.13to17, like reference numerals are used for elements, periods, and signals described with reference toFIGS.3to12, and redundant descriptions thereof will be omitted.

Referring toFIG.13, the gate driving circuit130bof the display device1bmay include a first gate driving circuit130Lb and a second gate driving circuit130Rb. The first gate driving circuit130Lb may include a first driving circuit131b, a second driving circuit133b, and a third driving circuit135b. The second gate driving circuit130Rb may include the first driving circuit131b, the third driving circuit135b, and a fourth driving circuit137b.

The first driving circuit131bmay be connected to the plurality of first gate lines GWL, and configured to supply the first gate signal GW sequentially to the first gate lines GWL according to the first control signal GCS1. As shown inFIG.14, the first driving circuit131bmay include the plurality of stages WST1to WST2m, which are sequentially connected to each other. The first driving circuit131bmay be substantially the same as or similar to the first driving circuit131aofFIG.9.

The second driving circuit133bmay be connected to the plurality of fourth gate lines EML, and configured to supply the fourth gate signal EM sequentially to the fourth gate lines EML according to the second control signal GCS2. As shown inFIG.14, the second driving circuit133bmay include the plurality of stages EST1to ESTm, which are sequentially connected to each other, and the plurality of dummy stages DEST1, DEST2, and so on, which are sequentially connected to the last m-th stage ESTm. The second driving circuit133bmay be substantially the same as or similar to the second driving circuit133bofFIG.9.

The third driving circuit135bmay be connected to the plurality of third gate lines GRL, and configured to supply the third gate signal GR sequentially to the third gate lines GRL according to the third control signal GCS3. As shown inFIG.14, the third driving circuit135bmay include the plurality of stages RST1to RSTm, which are sequentially connected to each other. The third driving circuit135bmay be substantially the same as or similar to the third driving circuit135ofFIG.5.

The fourth driving circuit137bmay be connected to the plurality of second gate lines GIL, and configured to supply the second gate signal GI sequentially to the second gate lines GIL according to the fourth control signal GCS4. As shown inFIG.14, the fourth driving circuit137bmay include the plurality of stages IST1to ISTm, which are sequentially connected to each other. The fourth driving circuit137bmay be substantially the same as or similar to the fourth driving circuit137ofFIG.5.

Referring toFIG.15A, the first pixel PX1may be configured to receive the first first-gate signal GW1through the first first-gate line GWL1from the first stage WST1of the first driving circuit131b, and the second pixel PX2may be configured to receive the second first-gate signal GW2through the second first-gate line GWL2from the second stage WST2of the first driving circuit131b.

The fourth gate signal EM output by the first stage EST1of the second driving circuit133b, the third gate signal GR output by the first stage RST1of the third driving circuit135b, and the second gate signal GI output by the first stage IST1of the fourth driving circuit137bmay be simultaneously supplied to the first pixel PX1and the second pixel PX2.

The first pixel PX1may be configured to receive the first fourth-gate signal EM1through the first fourth-gate line EML1from the first stage EST1of the second driving circuit133b, receive the first third-gate signal GR1through the first third-gate line GRL1from the first stage RST1of the third driving circuit135b, and receive the first second-gate signal G11through the first second-gate line GIL1from the first stage IST1of the fourth driving circuit137b.

The second pixel PX2may be configured to receive the second fourth-gate signal EM2through the second fourth-gate line EML2from the first stage EST1of the second driving circuit133b, receive the second third-gate signal GR2through the second third-gate line GRL2from the first stage RST1of the third driving circuit135b, and receive the second second-gate signal G12through the second second-gate line GIL2from the first stage IST1of the fourth driving circuit137b.

Each of the first pixel PX1and the second pixel PX2may be configured to receive the fourth gate signal EM output to the fourth gate line EML of a corresponding row by a next stage EST after a certain number from the first stage EST1of the second driving circuit133b, as the first fifth-gate signal EMB1through the first fifth-gate line EMBL1and as the second fifth-gate signal EMB2through the second fifth-gate line EMBL2.

Referring toFIG.15B, the n-th pixel PXn may be configured to receive the n-th first gate signal GWn through the n-th first gate line GWLn from the n-th stage WSTn of the first driving circuit131b, and the (n+1)th pixel PXn+1 may be configured to receive the (n+1)th first gate signal GWn+1 through the (n+1)th first gate line GWLn+1 from the (n+1)th stage WSTn+1 of the first driving circuit131b.

The fourth gate signal EM output by the k-th stage ESTk of the second driving circuit133b, the third gate signal GR output by the k-th stage RSTk of the third driving circuit135b, and the second gate signal GI output by a k-th stage ISTk of the fourth driving circuit137bmay be simultaneously supplied to the n-th pixel PXn and the (n+1)th pixel PXn+1.

The n-th pixel PXn may be configured to receive the n-th fourth gate signal EMn through the n-th fourth gate line EMLn from the k-th stage ESTk of the second driving circuit133b, receive the n-th third gate signal GRn through the n-th third gate line GRLn from the k-th stage RSTk of the third driving circuit135b, and receive the n-th second gate signal Gin through the n-th second gate line GILn from the k-th stage ISTk of the fourth driving circuit137b.

The (n+1)th pixel PXn+1 may be configured to receive the (n+1)th fourth gate signal EMn+1 through the (n+1)th fourth gate line EMLn+1 from the k-th stage ESTk of the second driving circuit133b, receive the (n+1)th third gate signal GRn+1 through the (n+1)th third gate line GRLn+1 from the k-th stage RSTk of the third driving circuit135b, and receive the (n+1)th second gate signal GIn+1 through the (n+1)th second gate line GILn+1 from the k-th stage ISTk of the fourth driving circuit137b.

The fourth gate signal EM output by the q-th stage ESTq of the second driving circuit133bmay be simultaneously supplied as the j-th fourth gate signal EMj through the j-th fourth gate line EMLj to the j-th pixel PXj, and as the (j+1)th fourth gate signal EMj+1 through the (j+1)th fourth gate line EMLj+1 to the (j+1)th pixel PXj+1. Also, the fourth gate signal EM output by the q-th stage ESTq of the second driving circuit133bmay be supplied to the n-th pixel PXn as the n-th fifth gate signal EMBn through the n-th fifth gate line EMBLn, and supplied to the (n+1)th pixel PXn+1 as the (n+1)th fifth gate signal EMBn+1 through the (n+1)th fifth gate line EMBLn+1. Accordingly, the n-th fifth gate signal EMBn of the n-th pixel PXn and the (n+1)th fifth gate signal EMBn+1 of the (n+1)th pixel PXn+1 may be the same as the j-th fourth gate signal EMj and the (j+1)th fourth gate signal EMj+1.

The fourth gate signal EM output by the k-th stage ESTk of the second driving circuit133bmay be supplied to the fifth gate lines EMBL of each row corresponding to previous stage before a certain number.

Referring toFIG.15C, the (2m-1)th pixel PX2m-1may be configured to receive the (2m-1)th first gate signal GW2m-1through the (2m-1)th first gate line GWL2m-1from the (2m-1)th stage WST2m-1of the first driving circuit131b, and the (2m)th pixel PX2mmay be configured to receive the (2m)th first gate signal GW2mthrough the (2m)th first gate line GWL2mfrom the (2m)th stage WST2mof the first driving circuit131b.

The fourth gate signal EM output by the m-th stage ESTm of the second driving circuit133b, the third gate signal GR output by the m-th stage RSTm of the third driving circuit135b, and the second gate signal GI output by an m-th stage ISTm of the fourth driving circuit137bmay be simultaneously supplied to the (2m-1)th pixel PX2m-1and the (2m)th pixel PX2m.

The (2m-1)th pixel PX2m-1may be configured to receive the (2m-1)th fourth gate signal EM2m-1 through the (2m-1)th fourth gate line EML2m-1from the m-th stage ESTm of the second driving circuit133b, receive the (2m-1)th third gate signal GR2m-1through the (2m-1)th third gate line GRL2m-1from the m-th stage RSTm of the third driving circuit135b, and receive an (2m-1)th second gate signal G12m-1through a (2m-1)th second gate line GIL2m-1from the m-th stage ISTm of the fourth driving circuit137b.

The (2m)th pixel PX2mmay be configured to receive the (2m)th fourth gate signal EM2mthrough the (2m)th fourth gate line EML2mfrom the m-th stage ESTm of the second driving circuit133b, receive the (2m)th third gate signal GR2mthrough the (2m)th third gate line GRL2mfrom the m-th stage RSTm of the third driving circuit135b, and receive a (2m)th second gate signal G12mthrough a (2m)th second gate line GIL2mfrom the m-th stage ISTm of the fourth driving circuit137b.

Each of the (2m-1)th pixel PX2m-1and the (2m)th pixel PX2mmay be configured to receive the signal DEM1output by the first dummy stage DEST1of the second driving circuit133bas the (2m-1)th fifth gate signal EMB2m-1through the (2m-1)th fifth gate line EMBL2m-1, and as the (2m)th fifth gate signal EMB2mthrough the (2m)th fifth gate line EMBL2m.

The fourth gate signal EM output by each of the (m-1)th stage ESTm-1and the m-th stage ESTm of the second driving circuit133bmay be supplied to the fifth gate line EMBL of each row corresponding to the previous stage before the certain number.

According to an embodiment, when the j-th row is a row spaced apart from the n-th row by 6 rows backward, the second driving circuit133bmay include three dummy stages DEST1to DEST3. Some stages EST4to ESTm from among the plurality of stages EST1to ESTm and the dummy stages DEST1to DEST3may each be configured to supply the fourth gate signal EM as the fifth gate signal EMB to a pair of fifth gate lines EMBL corresponding to a stage EST spaced apart by 3 stages forward. When the fourth gate signals EM output by the neighboring stages EST are shifted by 2H (2 horizontal periods), the j-th fourth gate signal EMj may be shifted from the n-th fourth gate signal EMn by t3(e.g., 6H: 6 horizontal periods) inFIG.17.

Referring toFIG.16, the pixel PX included in the pixel unit110of the display device1bdiffers from the pixel PX ofFIG.3in that the pixel PX ofFIG.16further includes a seventh transistor T7and the sixth transistor T6is configured to receive the fourth gate signal EM as the fifth gate signal EMB.

The seventh transistor T7may be connected to the fifth transistor T5in parallel. The seventh transistor T7may be connected between the driving voltage line PL and the first terminal of the first transistor T1. A gate of the seventh transistor T7may be configured to receive the third gate signal GR by being connected to the third gate line GRL.

Referring toFIG.17, the fourth period P4may be omitted from among the first to fourth periods P1to P4shown inFIG.7, and signals supplied during the first period P1and second period P2differ from signals supplied during the first period P1and second period P2ofFIG.7. Hereinafter, the n-th pixel PXn will be described as an example.

During the first period P1, the n-th second gate signal GIn may be supplied (applied) to the n-th second gate line GILn, and the j-th fourth gate signal EMj of a gate-on voltage may be supplied as the n-th fifth gate signal EMBn to the n-th fifth gate line EMBLn. The second terminal of the first transistor T1and the pixel electrode of the organic light-emitting diode OLED may be initialized to the initialization voltage Vint by the turned-on sixth transistor T6and turned-on fourth transistor T4.

During the second period P2, the n-th third gate signal GRn of a gate-on voltage may be supplied to the n-th third gate line GRLn. The threshold voltage Vth of the first transistor T1may be compensated for by the turned-on third transistor T3and seventh transistor T7.

During the third period P3, the n-th first gate signal GWn of a gate-on voltage and the (n+1)th first gate signal GWn+1 of a gate-on voltage are sequentially supplied to the n-th first gate line GWLn and the (n+1)th first gate line GWLn+1, respectively, and thus the data signal DATA may be supplied to each of the n-th pixel PXn and (n+1)th pixel PXn+1.

During the emitting period EP, the n-th fourth gate signal EMn and the j-th fourth gate signal EMj shifted from the n-th fourth gate signal EMn by t3may be sequentially supplied in gate-on voltages. The organic light-emitting diode OLED may emit light by the turned-on fifth transistor T5and sixth transistor T6.

In the present embodiment, the fourth gate signal EM output by the second driving circuit133bmay be used as the fifth gate signal EMB, and thus the fifth driving circuit139ofFIG.5may be omitted, thereby reducing a non-display area.

FIG.18is a diagram schematically showing a display device1caccording to an embodiment.FIG.19is a diagram schematically showing a portion of a gate driving circuit130cofFIG.18.FIG.20is a diagram showing the n-th pixel PXn arranged in the n-th row in the pixel unit110ofFIG.18.FIG.21is a diagram showing gate signals output by the gate driving circuit130cofFIG.18. InFIGS.18to21, like reference numerals are used for elements, periods, and signals described with reference toFIGS.3to17, and redundant descriptions thereof will be omitted.

Referring toFIG.18, the gate driving circuit130cof the display device1cmay include a first gate driving circuit130Lc and a second gate driving circuit130Rc. The first gate driving circuit130Lc and the second gate driving circuit130Rc may each include a first driving circuit131c, a second driving circuit133c, and a third driving circuit135c.

The first driving circuit131c, the second driving circuit133c, and the third driving circuit135cmay be substantially the same as or similar to the first driving circuit131a, the second driving circuit133a, and the third driving circuit135aofFIG.9, respectively. Gate signals output from the first driving circuit131c, the second driving circuit133c, and the third driving circuit135care similar to gate signals output from the first driving circuit131a, the second driving circuit133a, and the third driving circuit135aofFIGS.10A to10C, respectively, and thus descriptions thereof are not provided below.

According to an embodiment, the i-th row is a row spaced apart from the n-th row by 28 rows forward, and the j-th row may be a row spaced apart from the n-th row by 6 rows backward. In this case, the third driving circuit135cmay include 14 dummy stages DRST1to DRST14, and the second driving circuit133cmay include 3 dummy stages DEST1to DEST3. Some stages RST1to RSTm-14from among the plurality of stages RST1to RSTm and the dummy stages DRST1to DRST14may each be configured to supply the third gate signal GR as the second gate signal GI to a pair of second gate lines GIL corresponding to a stage RST spaced apart by 14 stages backward. Some stages EST4to ESTm from among the plurality of stages EST1to ESTm and the dummy stages DEST1to DEST3may each be configured to supply the fourth gate signal EM as the fifth gate signal EMB to a pair of fifth gate lines EMBL corresponding to a stage EST spaced apart by 3 stages forward. When the third gate signals GR output by the neighboring stages RST are shifted by 2H (2 horizontal periods), and the fourth gate signals EM output by the neighboring stages EST are shifted by 2H (2 horizontal periods), the n-th third gate signal GRn may be output by being shifted by t4(e.g., 28H: 28 horizontal periods) from the i-th third gate signal GRi and the j-th fourth gate signal EMj may be output by being shifted by t5(e.g., 6H: 6 horizontal periods) from the n-th fourth gate signal EMn, inFIG.21.

Referring toFIG.20, the pixel PX included in the pixel unit110of the display device1cdiffers from the pixel PX ofFIG.16in that the fourth transistor T4is configured to receive the third gate signal GR as the second gate signal GI.

FIG.21differs fromFIG.17with respect to a gate signal supplied during the first period P1from among the first to third periods P1to P3, and gate signals supplied during other periods may be the same or similar. Hereinafter, differences will be described with reference to the n-th pixel PXn as an example.

During the first period P1, the i-th third gate signal GRi of a gate-on voltage may be supplied to the n-th second gate line GILn, and the j-th fourth gate signal EMj of a gate-on voltage may be supplied to the n-th fifth gate line EMBLn. The second terminal of the first transistor T1and the pixel electrode of the organic light-emitting diode OLED may be initialized to the initialization voltage Vint by the turned-on sixth transistor T6and turned-on fourth transistor T4.

In the present embodiment, the third gate signal GR output by the third driving circuit135cand the fourth gate signal EM output by the second driving circuit133cmay be used as the second gate signal GI and the fifth gate signal EMB, and thus the fourth driving circuit137and the fifth driving circuit139ofFIG.5may be omitted, thereby reducing a non-display area.

FIG.22is a diagram schematically showing a display device1daccording to an embodiment.FIG.23is a diagram schematically showing a portion of a gate driving circuit130dofFIG.22.FIGS.24A to24Care diagrams schematically showing some stages, for describing an operation of a pixel ofFIG.22.FIG.25is a diagram showing the n-th pixel PXn arranged in the n-th row in the pixel unit110ofFIG.22.FIG.26is a diagram showing gate signals output by the gate driving circuit130dofFIG.22. InFIGS.22to26, like reference numerals are used for elements, periods, and signals described with reference toFIGS.3to21, and redundant descriptions thereof will be omitted.

Referring toFIG.22, the gate driving circuit130dof the display device1dmay include a first gate driving circuit130Ld and a second gate driving circuit130Rd. The first gate driving circuit130Ld and the second gate driving circuit130Rd may each include a first driving circuit131d, a second driving circuit133d, and a third driving circuit135d.

As shown inFIG.23, the first driving circuit131dmay include the plurality of stages WST1to WST2m, which are sequentially connected to each other. The plurality of stages WST1to WST2mmay be configured to sequentially output the first gate signal GW, and supply the first gate signal GW to the first gate lines GWL. The first driving circuit131dmay further include a plurality of dummy stages DWST1, DWST2, and so on, which are sequentially connected to the first stage WST1.

Some of the plurality of stages WST1to WST2mand the plurality of dummy stages DWST1, DWST2, and so on of the first driving circuit131dmay each be configured to output the first gate signal GW as the second gate signal GI to the second gate line GIL of another row. According to an embodiment, the some of the plurality of stages WST1to WST2mand the plurality of dummy stages DWST1, DWST2, and so on may each be configured to output the first gate signal GW as the second gate signal GI to the second gate line GIL arranged in the other row spaced apart from a corresponding row by certain rows backward.

The second driving circuit133dmay include the plurality of stages EST1to ESTm, which are sequentially connected to each other. The second driving circuit133dmay further include the plurality of dummy stages DEST1, DEST2, and so on, which are sequentially connected to the last stage ESTm. The second driving circuit133dmay be substantially the same as or similar to the second driving circuit133cofFIG.19.

The third driving circuit135dmay include a plurality of stages RST1to RSTm, which are sequentially connected to each other. The third driving circuit135dmay be substantially the same as or similar to the third driving circuit135dofFIG.9.

Referring toFIG.24A, the first pixel PX1may be configured to receive the first first-gate signal GW1through the first first-gate line GWL1from the first stage WST1of the first driving circuit131d, and the second pixel PX2may be configured to receive the second first-gate signal GW2through the second first-gate line GWL2from the second stage WST2of the first driving circuit131d. The first pixel PX1may be configured to receive a signal DGW1output by the first dummy stage DWST1of the first driving circuit131d, as the first second-gate signal G11through the first second-gate line GIL1. The second pixel PX2may be configured to receive a signal DGW2output by the second dummy stage DWST2of the first driving circuit131d, as the second second-gate signal G12through the second second-gate line GIL2.

The first first-gate signal GW1output by the first stage WST1may be supplied to the second gate line GIL arranged in a corresponding row of a next stage WST after a certain number. Similarly, the second first-gate signal GW2output by the second stage WST2may be supplied to the second gate line GIL arranged in a corresponding row of a next stage WST after a certain number.

The fourth gate signal EM output by the first stage EST1of the second driving circuit133dmay be supplied as the first fourth-gate signal EM1through the first fourth-gate line EML1of the first pixel PX1, and as the second fourth-gate signal EM2through the second fourth-gate line EML2of the second pixel PX2.

The third gate signal GR output by the first stage RST1of the third driving circuit135dmay be supplied as the first third-gate signal GR1through the first third-gate line GRL1of the first pixel PX1, and as the second third-gate signal GR2through the second third-gate line GRL2of the second pixel PX2.

Each of the first pixel PX1and the second pixel PX2may be configured to receive the fourth gate signal EM output to the fourth gate line EML of a corresponding row by a next stage EST after a certain number from the first stage EST1of the second driving circuit133d, as the first fifth-gate signal EMB1through the first fifth-gate line EMBL1and as the second fifth-gate signal EMB2through the second fifth-gate line EMBL2.

Referring toFIG.24B, the n-th pixel PXn may be configured to receive the n-th first gate signal GWn through the n-th first gate line GWLn from the n-th stage WSTn of the first driving circuit131d, and receive the first gate signal GW output by an i-th stage WSTi as the n-th second gate signal Gin through the n-th second gate line GILn. The n-th pixel PXn may be configured to receive the n-th fourth gate signal EMn through the n-th fourth gate line EMLn from the k-th stage ESTk of the second driving circuit133d, and receive the n-th third gate signal GRn through the n-th third gate line GRLn from the k-th stage RSTk of the third driving circuit135d. The n-th pixel PXn may be configured to receive the fourth gate signal EM output by the q-th stage ESTq as the n-th fifth gate signal EMBn through the n-th fifth gate line EMBLn.

Similarly, the (n+1)th pixel PXn+1 may be configured to receive the (n+1)th first gate signal GWn+1 through the (n+1)th first gate line GWLn+1 from the (n+1)th stage WSTn+1 of the first driving circuit131d, and receive the first gate signal GW output by an (i+1)th stage WSTi+1 as the (n+1)th second gate signal GIn+1 through the (n+1)th second gate line GILn+1. The (n+1)th pixel PXn+1 may be configured to receive the (n+1)th fourth gate signal EMn+1 through the (n+1)th fourth gate line EMLn+1 from the k-th stage ESTk of the second driving circuit133d, and receive the (n+1)th third gate signal GRn+1 through the (n+1)th third gate line GRLn+1 from the k-th stage RSTk of the third driving circuit135d. The (n+1)th pixel PXn+1 may be configured to receive the fourth gate signal EM output by the q-th stage ESTq as the (n+1)th fifth gate signal EMBn+1 through the (n+1)th fifth gate line EMBLn+1.

The first gate signal GW output by each of the n-th stage WSTn, the (n+1)th stage WSTn+1, a j-th stage WSTj, and a (j+1)th stage WSTj+1 of the first driving circuit131dmay be supplied to the second gate line GIL of each row corresponding to a next stage after a certain number.

The fourth gate signal EM output by each of the p-th stage ESTp and the k-th stage ESTk of the second driving circuit133dmay be supplied to the fifth gate line EMBL of each row corresponding to a previous stage before a certain number.

Referring toFIG.24C, the (2m-1)th pixel PX2m-1may be configured to receive the (2m-1)th first gate signal GW2m-1through the (2m-1)th first gate line GWL2m-1from the (2m-1)th stage WST2m-1of the first driving circuit131d, and the first gate signal GW output by a stage WST before a certain number from the (2m-1)th stage WST2m-1, as the (2m-1)th second gate signal G12m-1through the (2m-1)th second gate line GIL2m-1. The (2m-1)th pixel PX2m-1may be configured to receive the (2m-1)th fourth gate signal EM2m-1 through the (2m-1)th fourth gate line EML2m-1from the m-th stage ESTm of the second driving circuit133d, and receive the (2m-1)th third gate signal GR2m-1through the (2m-1)th third gate line GRL2m-1from the m-th stage RSTm of the third driving circuit135d. The (2m-1)th pixel PX2m-1may be configured to receive the signal DEM1output by the first dummy stage DEST1of the second driving circuit133d, as the (2m-1)th fifth gate signal EMB2m-1through the (2m-1)th fifth gate line EMBL2m-1.

Similarly, the (2m)th pixel PX2mmay be configured to receive the (2m)th first gate signal GW2mthrough the (2m)th first gate line GWL2mfrom the (2m)th stage WST2mof the first driving circuit131d, and receive the first gate signal GW output by a stage WST before a certain number from the (2m-1)th stage WST2m-1, as the (2m)th second gate signal G12mthrough the (2m)th second gate line GIL2m. The (2m)th pixel PX2mmay be configured to receive the (2m)th fourth gate signal EM2mthrough the (2m)th fourth gate line EML2mfrom the m-th stage ESTm of the second driving circuit133d, and receive the (2m)th third gate signal GR2mthrough the (2m)th third gate line GRL2mfrom the m-th stage RSTm of the third driving circuit135d. The (2m)th pixel PX2mmay be configured to receive the signal DEM1output by the first dummy stage DEST1of the second driving circuit133d, as the (2m)th fifth gate signal EMB2mthrough the (2m)th fifth gate line EMBL2m.

The fourth gate signal EM output by each of the m-th stage ESTm and an (m-1)th stage ESTm-1of the second driving circuit133dmay be supplied to the fifth gate line EMBL of each row corresponding to a previous stage before a certain number.

According to an embodiment, the i-th row is a row spaced apart from the n-th row by 30 rows forward, and the j-th row may be a row spaced apart from the n-th row by 6 rows backward. In this case, the first driving circuit131dmay include 30 dummy stages DWST1to DWST30, and the second driving circuit133dmay include 3 dummy stages DEST1to DEST3. Some stages WST1to WST2m-30from among the plurality of stages WST1to WST2mand the dummy stages DWST1to DWST30may each be configured to output the first gate signal GW as the second gate signal GI to the second gate line GIL corresponding to a stage WST spaced apart by 30 stages backward. Some stages EST4to ESTm from among the plurality of stages EST1to ESTm and the dummy stages DEST1to DEST3may each be configured to output the fourth gate signal EM as the fifth gate signal EMB to a pair of fifth gate lines EMBL corresponding to a stage EST spaced apart by 3 stages forward. When the first gate signals GW output by the neighboring stages WST are shifted by 1H (1 horizontal period), and the fourth gate signals EM output by the neighboring stages EST are shifted by 2H (2 horizontal periods), the n-th first gate signal GWn may be output by being shifted by t6(e.g., 30H: 30 horizontal periods) from an i-th first gate signal GWi and the j-th fourth gate signal EMj may be output by being shifted by t7(e.g., 6H: 6 horizontal periods) from the n-th fourth gate signal EMn, inFIG.26.

The pixel PX included in the pixel unit110of the display device1dofFIG.25differs from the pixel PX ofFIG.20with respect to a gate signal supplied to the gate of the fourth transistor T4, and configurations and operations thereof are the same.

FIG.26differs fromFIG.21with respect to a gate signal supplied during the first period P1from among the first to third periods P1to P3, and gate signals supplied during other periods may be the same or similar. Hereinafter, differences will be described with reference to the n-th pixel PXn as an example.

During the first period P1, the n-th pixel PXn may be configured to receive the i-th first gate signal GWi of a gate-on voltage through the n-th second gate line GILn, and receive the j-th fourth gate signal EMj of a gate-on voltage through the n-th fifth gate line EMBLn. The second terminal of the first transistor T1and the pixel electrode of the organic light-emitting diode OLED may be initialized to the initialization voltage Vint by the turned-on sixth transistor T6and turned-on fourth transistor T4.

In the present embodiment, the first gate signal GW output by the first driving circuit131dand the fourth gate signal EM output by the second driving circuit133dmay be used as the second gate signal GI and the fifth gate signal EMB, and thus the fourth driving circuit137and the fifth driving circuit139ofFIG.5may be omitted, thereby reducing a non-display area.

FIG.27is a diagram schematically showing a display device1eaccording to an embodiment.FIG.28is a diagram schematically showing a portion of a gate driving circuit130eofFIG.27.FIG.29is a diagram showing the n-th pixel PXn arranged in the n-th row in the pixel unit110ofFIG.27.FIG.30is a diagram schematically showing some stages, for describing an operation of a pixel ofFIG.27.FIG.31is a diagram showing gate signals output by the gate driving circuit130eofFIG.27. InFIGS.27to31, like reference numerals are used for elements, periods, and signals described with reference toFIGS.3to26, and redundant descriptions thereof will be omitted.

Referring toFIG.27, the gate driving circuit130eof the display device1emay include a first gate driving circuit130Le and a second gate driving circuit130Re. The first gate driving circuit130Le may include a first driving circuit131e, a second driving circuit133e, and a third driving circuit135e. The second gate driving circuit130Re may include the first driving circuit131e, the third driving circuit135e, and a fourth driving circuit137e.

As shown inFIG.28, the first driving circuit131e, the second driving circuit133e, the third driving circuit135e, and the fourth driving circuit137emay be substantially the same as or similar to the first driving circuit131, the second driving circuit133, the third driving circuit135, and the fourth driving circuit137ofFIG.6, respectively.

Referring toFIG.29, the pixel PX included in the pixel unit110of the display device1ediffers from the pixel PX ofFIG.3in that the pixel PX ofFIG.29further includes the seventh transistor T7and an eighth transistor T8, the sixth transistor T6is configured to receive the fourth gate signal EM as the fifth gate signal EMB, and an initialization voltage transmitted by the fourth transistor T4is a second initialization voltage Vaint.

The seventh transistor T7may be connected to the fifth transistor T5in parallel. The seventh transistor T7may be connected between the driving voltage line PL and the first terminal of the first transistor T1. The gate of the seventh transistor T7may be configured to receive the third gate signal GR by being connected to the third gate line GRL.

The eighth transistor T8may be connected between the second node N2and a second initialization voltage line VL2configured to supply the initialization voltage Vint, and the gate may be configured to receive the second gate signal GI by being connected to the second gate line GIL (In other words, the second initialization voltage line VL2may be referred to as a “fourth voltage line”.).

The fourth transistor T4may be connected between the third node N3and a first initialization voltage line VL1configured to supply the second initialization voltage Vaint, and the gate may be configured to receive the second gate signal GI by being connected to the second gate line GIL. The second initialization voltage Vaint may be a voltage different from the initialization voltage Vint. According to an embodiment, the second initialization voltage Vaint may have a voltage level greater than the initialization voltage Vint.

FIG.31differs fromFIG.7in that signals supplied during the second period P2from among the first to fourth periods P1to P4are different from the signals supplied during the second period P2ofFIG.7. Hereinafter, the n-th pixel PXn will be described as an example.

Referring toFIGS.29to31together, the n-th pixel PXn may be configured to receive the n-th first gate signal GWn through the n-th first gate line GWLn from the n-th stage WSTn of the first driving circuit131e, receive the n-th fourth gate signal EMn through the n-th fourth gate line EMLn from the k-th stage ESTk of the second driving circuit133e, receive the n-th third gate signal GRn through the n-th third gate line GRLn from the k-th stage RSTk of the third driving circuit135e, and receive the n-th second gate signal GIn through the n-th second gate line GILn from the k-th stage ISTk of the fourth driving circuit137e. The n-th pixel PXn may be configured to receive the fourth gate signal EM output by the k-th stage ESTk as the n-th fifth gate signal EMBn through the n-th fifth gate line EMBLn. In other words, the n-th fourth gate signal EMn and the n-th fifth gate signal EMBn may be the same.

Similarly, the (n+1)th pixel PXn+1 may be configured to receive the (n+1)th first gate signal GWn+1 through the (n+1)th first gate line GWLn+1 from the (n+1)th stage WSTn+1 of the first driving circuit131e, receive the (n+1)th fourth gate signal EMn+1 through the (n+1)th fourth gate line EMLn+1 from the k-th stage ESTk of the second driving circuit133e, receive the (n+1)th third gate signal GRn+1 through the (n+1)th third gate line GRLn+1 from the k-th stage RSTk of the third driving circuit135e, and receive the (n+1)th second gate signal GIn+1 through the (n+1)th second gate line GILn+1 from the k-th stage ISTk of the fourth driving circuit137e. The (n+1)th pixel PXn+1 may be configured to receive the fourth gate signal EM output by the k-th stage ESTk as the (n+1)th fifth gate signal EMBn+1. In other words, the (n+1)th fourth gate signal EMn+1 and the (n+1)th fifth gate signal EMBn+1 may be the same.

During the first period P1, the n-th second gate signal Gin of a gate-on voltage may be supplied to the n-th second gate line GILn, and the n-th third gate signal GRn of a gate-on voltage may be supplied to the n-th third gate line GRLn. The pixel electrode of the organic light-emitting diode OLED may be initialized to the second initialization voltage Vaint, the second terminal of the first transistor T1may be initialized to the initialization voltage Vint, and the first gate of the first transistor T1may be initialized to the reference voltage Vref, by the turned-on fourth transistor T4, turned-on eighth transistor T8, and turned-on third transistor T3.

During the second period P2, the n-th third gate signal GRn of a gate-on voltage may be supplied to the n-th third gate line GRLn. The threshold voltage Vth of the first transistor T1may be compensated for by the turned-on third transistor T3and seventh transistor T7.

During the third period P3, the n-th first gate signal GWn of a gate-on voltage and the (n+1)th first gate signal GWn+1 of a gate-on voltage are sequentially supplied to the n-th first gate line GWLn and the (n+1)th first gate line GWLn+1, respectively, and thus the data signal DATA may be supplied to each of the n-th pixel PXn and (n+1)th pixel PXn+1.

During the emitting period EP, the n-th fourth gate signal EMn may be supplied in a gate-on voltage, and the organic light-emitting diode OLED may be configured to emit light by the turned-on fifth transistor T5and sixth transistor T6.

FIG.32is a diagram schematically showing a portion of the gate driving circuit130eofFIG.27.FIG.33is a diagram showing the n-th pixel PXn arranged in the n-th row in the pixel unit110ofFIG.27.FIG.34is a diagram showing the gate signals output by the gate driving circuit130eofFIG.27.

Embodiments shown inFIGS.28to31use the n-th fourth gate signal EMn as the n-th fifth gate signal EMBn, but an embodiment of the disclosure is not limited thereto. According to another embodiment, as shown inFIG.32, the second driving circuit133e′ may include the plurality of stages EST1to ESTm, which are sequentially connected to each other, and the plurality of dummy stages DEST1, DEST2, and so on, which are sequentially connected to the last m-th stage ESTm. Accordingly, as shown inFIGS.33and34, the j-th fourth gate signal EMj output from a stage spaced apart from the n-th row by certain rows backward may be used as the n-th fifth gate signal EMBn.

In the above-described embodiments, a stage of a first driving circuit or third driving circuit in an arbitrary row is configured to supply the first gate signal GW or third gate signal GR to a succeeding row, and a stage of a second driving circuit is configured to supply the fourth gate signal EM to a preceding row, but this is only an example. According to another embodiment, at least one of a first driving circuit, a second driving circuit, a third driving circuit, and a fourth driving circuit may be configured to supply a gate signal to a preceding row or a succeeding row, according to a change in a pixel and operation.

In the above-described embodiments, the emitting period EP starts at a timing when the fourth gate signal EM is applied in a gate-on voltage, but it may be understood that the emitting period EP may start from a time point when the fourth gate signal EM and the fifth gate signal EMB are both in a gate-on voltage.

FIG.35illustrates an example of an arbitrary stage WST of a first driving circuit, according to an embodiment.

Referring toFIG.35, a plurality of transistors included in the stage WST of the first driving circuit may be N-type thin-film transistors. The n-type thin-film transistors may be oxide thin-film transistors. The stage WST may include an input circuit121, a first control circuit122, a second control circuit123, a reset circuit124, a stabilization circuit125, a first output circuit126, and a second output circuit127.

The input circuit121may be configured to transmit a start signal (e.g., an initial signal FLM or carry signal) applied to an input terminal IN to a first control node GW_Q according to a first carry clock signal CR_CLK1. The input circuit121may include a first transistor M1.

The first transistor M1may include a (1-1)th transistor M1-1and a (1-2)th transistor M1-2, which are connected to each other in series between the input terminal IN and the first control node GW_Q. Gates of the (1-1)th transistor M1-1and (1-2)th transistor M1-2may be connected to a first carry clock terminal to which the first carry clock signal CR_CLK1is input. When the first carry clock signal CR_CLK1of a first level (high level) is applied, the first transistor M1is turned on and the first control node GW_Q may be set (charged) to a voltage of the start signal.

The reset circuit124may include a second transistor M2. The second transistor M2may include a (2-1)th transistor M2-1and a (2-2)th transistor M2-2, which are connected to each other in series between the first control node GW_Q and a second voltage terminal to which a second voltage VGL_GW of a second level (low level) is input. Gates of the (2-1)th transistor M2-1and (2-2)th transistor M2-2may be connected to a reset terminal to which a reset voltage SESR_GW is input. The second transistor M2may be turned on by the reset voltage SESR_GW of the first level while a gate driving circuit is not driven, and configured to reset a voltage of a first control node GW_Q to the first level. The reset voltage SESR_GW may be supplied in the second level while the gate driving circuit is driven.

The stabilization circuit125may include a third transistor M3. The third transistor M3may include a (3-1)th transistor M3-1and a (3-2)th transistor M3-2, which are connected to each other in series between a node GW_A and a first voltage terminal to which a first voltage VGH_GW of the first level is input. Gates of the (3-1)th transistor M3-1and (3-2)th transistor M3-2may be connected to the first control node GW_Q. The third transistor M3may be turned on when a voltage of the first control node GW_Q is in the first level, and configured to maintain voltages of intermediate nodes of the (2-1)th transistor M2-1and (2-2)th transistor M2-2, and intermediate nodes of the (1-1)th transistor M1-1and (1-2)th transistor M1-2, which are connected to the node GW_A, to the first level, thereby preventing a voltage drop caused by a current leakage of the first control node GW_Q when the first control node GW_Q is in a floating state.

The first output circuit126may be configured to output the first gate signal GW to the first gate signal GW of a corresponding row and/or the second gate line GIL of another row. The first output circuit126may include a tenth transistor M10, an eleventh transistor M11, and a twelfth transistor M12, which are connected between the second voltage terminal and a scan clock terminal to which a scan clock signal CLK is input.

The tenth transistor M10(pull-up transistor) may be connected between the scan clock terminal and a first output terminal OUT1, and a gate thereof may be connected to the first control node GW_Q. The tenth transistor M10may be turned on when a voltage of the first control node GW_Q is in the first level, and configured to output the scan clock signal CLK of the first level as the first gate signal GW through the first output terminal OUT1.

The eleventh transistor M11(pull-down transistor) may be connected between the first output terminal OUT1and the second voltage terminal, and a gate thereof may be connected to a (2-1)th control node GW_QB1. The eleventh transistor M11may be turned on when a voltage of the (2-1)th control node GW_QB1is in the first level, and configured to output the second voltage VGL_GW of the second level as the first gate signal GW through the first output terminal OUT1.

The twelfth transistor M12(pull-down transistor) may be connected between the first output terminal OUT1and the second voltage terminal, and a gate thereof may be connected to a (2-2)th control node GW_QB2. The twelfth transistor M12may be turned on when a voltage of the (2-2)th control node GW_QB2is in the first level, and configured to output the second voltage VGL_GW of the second level as the first gate signal GW through the first output terminal OUT1.

The second output circuit127may be configured to output a carry signal GW_CR to the input terminal IN of a next stage. The second output circuit127may include a seventh transistor M7, an eighth transistor M8, and a ninth transistor M9, which are connected between a second carry clock terminal to which a second carry clock signal CR_CLK2is input and a third voltage terminal to which a third voltage VGL2_GW of the second level is input. The second output circuit127may further include the first capacitor C1. A voltage level of the third voltage VGL2_GW may be lower than a voltage level of the second voltage VGL_GW.

The seventh transistor M7(pull-up transistor) may be connected between the second carry clock terminal and a second output terminal OUT2, and a gate thereof may be connected to the first control node GW_Q. The first capacitor C1may be connected between the first control node GW_Q and the second output terminal OUT2. The seventh transistor M7may be turned on when a voltage of the first control node GW_Q is in the first level, and configured to output the second carry clock signal CR_CLK2of the first level as the carry signal GW_CR through the second output terminal OUT2.

The eighth transistor M8(pull-down transistor) may be connected between the second output terminal OUT2and the third voltage terminal, and a gate thereof may be connected to the (2-1)th control node GW_QB1. The eighth transistor M8may be turned on when a voltage of the (2-1)th control node GW_QB1is in the first level, and configured to output the third voltage VGL2_GW of the second level as the carry signal GW_CR through the second output terminal OUT2.

The ninth transistor M9(pull-down transistor) may be connected between the second output terminal OUT2and the third voltage terminal, and a gate thereof may be connected to the (2-2)th control node GW_QB2. The ninth transistor M9may be turned on when a voltage of the (2-2)th control node GW_QB2is in the first level, and configured to output the third voltage VGL2_GW of the second level as the carry signal GW_CR through the second output terminal OUT2.

The first control circuit122may control a voltage of the first control node GW_Q according to the second carry clock signal CR_CLK2and a voltage of a second control node GW_QB. The second control node GW_QB may include the (2-1)th control node GW_QB1and the (2-2)th control node GW_QB2. The first control circuit122may include a fourth transistor M4, a fifth transistor M5, and a sixth transistor M6.

The fourth transistor M4may be connected between the first control node GW_Q and a node GW_H, and a gate thereof may be connected to the second carry clock terminal. The fifth transistor M5may be connected between the node GW_H and the second output terminal OUT2, and a gate thereof may be connected to the (2-1)th control node GW_QB1. The sixth transistor M6may be connected between the node GW_H and the second output terminal OUT2, and a gate thereof may be connected to the (2-2)th control node GW_QB2.

When the second carry clock signal CR_CLK2is in the first level and the (2-1)th control node GW_QB1is in the first level, the fourth transistor M4and the fifth transistor M5may be turned on, and the eighth transistor M8of the second output circuit127may be turned on. Accordingly, while the (2-1)th control node GW_QB1is in the first level, the voltage of the first control node GW_Q may stably maintain the second level of the third voltage VGL2_GW.

When the second carry clock signal CR_CLK2is in the first level and the (2-2)th control node GW_QB2is in the first level, the fourth transistor M4and the sixth transistor M6may be turned on, and the ninth transistor M9of the second output circuit127may be turned on. Accordingly, while the (2-2)th control node GW_QB2is in the first level, the voltage of the first control node GW_Q may stably maintain the second level of the third voltage VGL2_GW.

The second control circuit123may reverse the voltage level of the first control node GW_Q according to the second voltage VGL_GW, the third voltage VGL2_GW, a fourth voltage GW_GB11, and a fifth voltage GW GB12and supply the same to the second control node GW_QB, thereby controlling the voltage of the second control node GW_QB.

The second control circuit123may include a thirteenth transistor M13, a fourteenth transistor M14, a fifteenth transistor M15, a sixteenth transistor M16, a seventeenth transistor M17, an eighteenth transistor M18, a nineteenth transistor M19, a twentieth transistor M20, the second capacitor C2, and a third capacitor C3.

The thirteenth transistor M13may include a (13-1)th transistor M13-1and a (13-2)th transistor M13-2, which are connected to each other in series between a node GW_C and a fourth voltage terminal to which the fourth voltage GW_GB11is input. Gates of the (13-1)th transistor M13-1and (13-2)th transistor M13-2may be connected to the fourth voltage terminal. The fourteenth transistor M14may be connected between the (2-1)th control node GW_QB1and the fourth voltage terminal, and a gate thereof may be connected to the node GW_C. The fifteenth transistor M15may be connected between the node GW_C and the second voltage terminal, and a gate thereof may be connected to the first control node GW_Q. The sixteenth transistor M16may be connected between the (2-1)th control node GW_QB1and the third voltage terminal, and a gate thereof may be connected to the first control node GW_Q.

The seventeenth transistor M17may include a (17-1)th transistor M17-1and a (17-2)th transistor M17-2, which are connected to each other in series between a node GW_E and a fifth voltage terminal to which the fifth voltage GW_GB12is input. Gates of the (17-1)th transistor M17-1and (17-2)th transistor M17-2may be connected to the fifth voltage terminal. The eighteenth transistor M18may be connected between the (2-2)th control node GW_QB2and the fifth voltage terminal, and a gate thereof may be connected to the node GW_E. The nineteenth transistor M19may be connected between the node GW_E and the second voltage terminal, and a gate thereof may be connected to the first control node GW_Q. The twentieth transistor M20may be connected between the (2-2)th control node GW_QB2and the third voltage terminal, and a gate thereof may be connected to the first control node GW_Q.

The second capacitor C2may be connected between the (2-1)th control node GW_QB1and the node GW_C. The third capacitor C3may be connected between the (2-2)th control node GW_QB2and the node GW_E. When the voltages of the (2-1)th control node GW_QB1 and (2-2)th control node GW_QB2are switched from the first level to the second level by the second capacitor C2and third capacitor C3, the fourteenth transistor M14and the eighteenth transistor M18may be quickly turned off.

The fourth voltage GW GB11and the fifth voltage GW_GB12may be supplied in voltages of the first level or the second level by alternating in frame units. When the fourth voltage GW GB11is in the first level and the fifth voltage GW_GB12is in the second level, the voltage of the (2-1)th control node GW_QB1may be in the first level and the voltage of the (2-2)th control node GW_QB2may be in the second level. When the fifth voltage GW_GB12is in the first level and the fourth voltage GW_GB11is in the second level, the voltage of the (2-2)th control node GW_QB2may be in the first level and the voltage of the (2-1)th control node GW_QB1may be in the second level.

The eleventh transistor M11and the twelfth transistor M12, and the eighth transistor M8and the ninth transistor M9may be turned on while alternating in frame units according to the fourth voltage GW_GB11and the fifth voltage GW_GB12. Accordingly, changes in threshold voltages of the eleventh transistor M11and the twelfth transistor M12, and the eighth transistor M8and the ninth transistor M9may be reduced or prevented.

FIG.36illustrates an example of an arbitrary stage EST of a second driving circuit, according to an embodiment.

Referring toFIG.36, a plurality of transistors included in the stage EST of the second driving circuit may be N-type thin-film transistors. The n-type thin-film transistors may be oxide thin-film transistors. The stage EST may include an input circuit141, a first control circuit142, a second control circuit143, a reset circuit144, a stabilization circuit145, a first output circuit146, and a second output circuit147.

The input circuit141may be configured to transmit the start signal (e.g., the initial signal FLM or carry signal) applied to the input terminal IN to a first control node EM_Q according to a first clock signal EM_CLK1. The input circuit141may include the first transistor M1and the third transistor M3. The first control node EM_Q may include a (1-1)th control node EM_Q1and a (1-2)th control node EM_Q2.

The first transistor M1may include the (1-1)th transistor M1-1and the (1-2)th transistor M1-2, which are connected to each other in series between the input terminal IN and the (1-1)th control node EM_Q1. The gates of the (1-1)th transistor M1-1and (1-2)th transistor M1-2may be connected to a first clock terminal to which the first clock signal EM_CLK1is input. When the first clock signal EM_CLK1of the first level (high level) is applied, the first transistor M1is turned on and the (1-1)th control node EM_Q1may be set (charged) to the voltage of the start signal.

The third transistor M3may be connected between the (1-1)th control node EM_Q1and the (1-2)th control node EM_Q2, and the gate thereof may be connected to the first voltage terminal to which a first voltage VGH_EMB of the first level is input. The third transistor M3may conduct the (1-1)th control node EM_Q1and the (1-2)th control node EM_Q2to control the voltage level of the (1-2)th control node EM_Q2to be the voltage level of the (1-1)th control node EM_Q1. The third transistor M3may be always turned on by the first voltage VGH_EMB to prevent a line voltage drop between the (1-1)th control node EM_Q1and the (1-2)th control node EM_Q2.

The reset circuit144may include the sixteenth transistor M16. The sixteenth transistor M16may include a (16-1)th transistor M16-1and a (16-2)th transistor M16-2, which are connected to each other in series between the (1-1)th control node EM_Q1and the second voltage terminal to which a second voltage VGL_EMB of the second level (low level) is input. Gates of the (16-1)th transistor M16-1and (16-2)th transistor M16-2may be connected to the reset terminal to which a reset voltage ESR is input. The sixteenth transistor M16may be turned on by the reset voltage ESR of the first level while the gate driving circuit is not driven, and configured to reset a voltage of the (1-1)th control node EM_Q1to the first level. The reset voltage ESR may be supplied in the second level while the gate driving circuit is driven.

The stabilization circuit145may include the fifteenth transistor M15. The fifteenth transistor M15may include a (15-1)th transistor M15-1and a (15-2)th transistor M15-2, which are connected to each other in series between the first voltage terminal and a node EM_A. Gates of the (15-1)th transistor M15-1and (15-2)th transistor M15-2may be connected to the (1-1)th control node EM_Q1. The fifteenth transistor M15may be turned on when the voltage of the (1-1)th control node EM_Q1is in the first level to maintain voltages of intermediate nodes of the (2-1)th transistor M2-1and (2-2)th transistor M2-2, intermediate nodes of the (1-1)th transistor M1-1and (1-2)th transistor M1-2, and intermediate nodes of the (16-1)th transistor M16-1and (16-2)th transistor M16-2, which are connected to the node EM_A, to the first level, thereby preventing a voltage drop caused by a current leakage of the (1-1)th control node EM_Q1when the (1-1)th control node EM_Q1is in a floating state.

The first output circuit146may be configured to output the fourth gate signal EM to the fourth gate line EML of a corresponding row and/or the fifth gate line EMBL of the same row or another row. The first output circuit146may include the twelfth transistor M12and the fourteenth transistor M14, which are connected between the first voltage terminal and the second voltage terminal. The first output circuit146may further include a fourth capacitor C4and a fifth capacitor C5.

The twelfth transistor M12(pull-up transistor) may be connected between the first voltage terminal and the first output terminal OUT1, and the gate thereof may be connected to the (1-2)th control node EM_Q2. The twelfth transistor M12may be turned on when the voltage of the (1-2)th control node EM_Q2is in the first level, and configured to output the first voltage VGH_EMB as the fourth gate signal EM through the first output terminal OUT1.

The fourteenth transistor M14(pull-down transistor) may be connected between the first output terminal OUT1and the second voltage terminal, and the gate thereof may be connected to a second control node EM_QB. The fourteenth transistor M14may be turned on when a voltage of the second control node EM_QB is in the first level, and configured to output the second voltage VGL_EMB as the fourth gate signal EM through the first output terminal OUT1.

The second output circuit147may be configured to output a carry signal EM_CR to the input terminal IN of the next stage. The second output circuit147may include the sixth transistor M6and the thirteenth transistor M13, which are connected between the first voltage terminal and the third voltage terminal to which a third voltage VGL2_EMB of the second level is input. A voltage level of the third voltage VGL2_EMB may be lower than a voltage level of the second voltage VGL_EMB.

The sixth transistor M6(pull-up transistor) may be connected between the first voltage terminal and the first output terminal OUT1, and the gate thereof may be connected to the (1-2)th control node EM_Q2. The sixth transistor M6may be turned on when the voltage of the (1-2)th control node EM_Q2is in the first level, and configured to output the first voltage VGH_EMB as the carry signal EM_CR through the second output terminal OUT2.

The thirteenth transistor M13(pull-down transistor) may be connected between the first output terminal OUT1and the third voltage terminal, and the gate thereof may be connected to the second control node EM_QB. The thirteenth transistor M13may be turned on when the voltage of the second control node EM_QB is in the first level, and configured to output the third voltage VGL2_EMB as the carry signal EM_CR through the second output terminal OUT2.

The first control circuit142may control a voltage of the first control node EM_Q according to a second clock signal EM_CLK2and a voltage of the second control node EM_QB. The first control circuit142may include the second transistor M2, the fifth transistor M5, and the first capacitor C1.

The second transistor M2may include the (2-1)th transistor M2-1and the (2-2)th transistor M2-2, which are connected between the (1-1)th control node EM_Q1and the third voltage terminal. The gates of the (2-1)th transistor M2-1and (2-2)th transistor M2-2may be connected to the second control node EM_QB. The (2-1)th transistor M2-1and (2-2)th transistor M2-2may be turned on when the second control node EM_QB is in the first level to maintain the voltage of the (1-1)th control node EM_Q1to the second level.

The fifth transistor M5may be connected between the (1-2)th control node EM_Q2and a second clock terminal to which the second clock signal EM_CLK2is input, and the gate thereof may be connected to the (1-2)th control node EM_Q2. The first capacitor C1may be connected between the (1-2)th control node EM_Q2and a node EM_B. The fifth transistor M5may be turned on when the (1-2)th control node EM_Q2is in the first level and configured to transmit the second clock signal EM_CLK2to one end of the first capacitor C1. When the second clock signal EM_CLK2is in the first level, the voltage of the (1-2)th control node EM_Q2may be boosted to be greater than the first voltage VGH_EMB by the first capacitor C1and the turned-on fifth transistor M5.

The second control circuit143may be configured to reverse the voltage level of the (1-1)th control node EM_Q1according to the first voltage VGH_EMB, the second voltage VGL_EMB, the third voltage VGL2_EMB, the first clock signal EM_CLK1, and the second clock signal EM_CLK2and supply the same to the second control node EM_QB, thereby controlling the voltage of the second control node EM_QB. The second control circuit143may include the fourth transistor M4, the seventh transistor M7, the eighth transistor M8, the ninth transistor M9, the tenth transistor M10, the eleventh transistor M11, and the third capacitor C3.

The fourth transistor M4may be connected between the second control node EM_QB and the third voltage terminal, and the gate thereof may be connected to the (1-1)th control node EM_Q1. The fourth transistor M4is turned on when the voltage of the (1-1)th control node EM_Q1is in the first level to maintain the voltage of the second control node EM_QB to the second level.

The seventh transistor M7may be connected between the first voltage terminal and a node SR_QB, and the gate thereof may be connected to the first clock terminal. The eighth transistor M8may include an (8-1)th transistor M8-1and an (8-2)th transistor M8-2, which are connected to each other in series between the first clock terminal and the node SR_QB, and gates of the (8-1)th transistor M8-1and (8-2)th transistor M8-2may be connected to the (1-1)th control node EM_Q1. The ninth transistor M9may be connected between the node SR_QB and a node SR_QBF, and the gate thereof may be connected to the first voltage terminal. The tenth transistor M10may be connected between the second clock terminal and a node EM_E, and the gate thereof may be connected to the node SR_QBF. The eleventh transistor M11may be connected between the first voltage terminal and the second control node EM_QB, and the gate thereof may be connected to the node EM_E.

The third capacitor C3may be connected between the node SR_QBF and the node EM_E. When the second clock signal EM_CLK2is in the first level, a voltage of the node SR_QBF may be boosted to be greater than the first voltage VGH_EMB by the third capacitor C3and the turned-on tenth transistor M10.

When the voltage of the (1-1)th control node EM_Q1is in the first level, the first clock signal EM_CLK1is in the first level, and the second clock signal EM_CLK2is in the second level, the eighth transistor M8and seventh transistor M7may be turned on, voltages of the node SR_QB and node SR_QBF, which are conducted by the turned-on ninth transistor M9, may become the first level by the first voltage VGH_EMB, and a voltage of the node EM_E may become the second level by the second clock signal EM_CLK2through the turned-on tenth transistor M10. Accordingly, the eleventh transistor M11may be turned off and the second control node EM_QB may maintain the second level.

When the voltage of the (1-1)th control node EM_Q1is in the second level, the first clock signal EM_CLK1is in the second level, and the second clock signal EM_CLK2is in the first level, the eighth transistor M8and seventh transistor M7may be turned off, the voltages of the node SR_QB and node SR_QBF, which are conducted by the turned-on ninth transistor M9, may maintain the first level, and the voltage of the node EM_E may become the first level by the second clock signal EM_CLK2through the turned-on tenth transistor M10. Accordingly, the eleventh transistor M11may be turned on and the second control node EM_QB may maintain the first level.

FIG.37illustrates an example of an arbitrary stage RST of a third driving circuit, according to an embodiment.

Referring toFIG.37, a plurality of transistors included in the stage RST of the third driving circuit may be N-type thin-film transistors. The n-type thin-film transistors may be oxide thin-film transistors. The stage RST may include an input circuit161, a first control circuit162, a second control circuit163, a reset circuit164, a stabilization circuit165, a first output circuit166, and a second output circuit167.

The input circuit161may be configured to transmit the start signal (e.g., the initial signal FLM or carry signal) applied to the input terminal IN to a first control node GR_Q according to a first clock signal GR_CLK1. The first control node GR_Q may include a (1-1)th control node GR_Q1and a (1-2)th control node GR_Q2. The input circuit161may include the first transistor M1and the fourth transistor M4.

The first transistor M1may include the (1-1)th transistor M1-1and the (1-2)th transistor M1-2, which are connected to each other in series between the input terminal IN and the (1-1)th control node GR_Q1. The gates of the (1-1)th transistor M1-1and (1-2)th transistor M1-2may be connected to the first clock terminal to which the first clock signal GR_CLK1is input. When the first clock signal GR_CLK1of the first level (high level) is applied, the first transistor M1is turned on and the (1-1)th control node GR_Q1may be set (charged) to the voltage of the start signal.

The fourth transistor M4may be connected between the (1-1)th control node GR_Q1and the (1-2)th control node GR_Q2, and the gate thereof may be connected to the first voltage terminal. The fourth transistor M4may conduct the (1-1)th control node GR_Q1and the (1-2)th control node GR_Q2to control the voltage level of the (1-2)th control node GR_Q2to be the voltage level of the (1-1)th control node GR_Q1. The fourth transistor M4may be always turned on by a first voltage VGH_GR to prevent a line voltage drop between the (1-1)th control node GR_Q1and the (1-2)th control node GR_Q2.

The reset circuit164may include a23rdtransistor M23. The23rdtransistor M23may include a (23-1)th transistor M23-1and a (23-2)th transistor M23-2, which are connected to each other in series between the (1-1)th control node GR_Q1and the second voltage terminal to which a second voltage VGL_GR of the second level (low level) is input. Gates of the (23-1)th transistor M23-1and (23-2)th transistor M23-2may be connected to the reset terminal to which a reset voltage SESR_GR is input. The23rdtransistor M23may be turned on by the reset voltage SESR_GR of the first level while the gate driving circuit is not driven, and configured to reset a voltage of the (1-1)th control node GR_Q1to the first level. The reset voltage SESR_GR may be supplied in the second level while the gate driving circuit is driven.

The stabilization circuit165may include a22ndtransistor M22. The22ndtransistor M22may include a (22-1)th transistor M22-1and a (22-2)th transistor M22-2, which are connected to each other in series between a node GR_A and the first voltage terminal to which the first voltage VGH_GR of the first level is input. Gates of the (22-1)th transistor M22-1and (22-2)th transistor M22-2may be connected to the (1-1)th control node GR_Q1. The22ndtransistor M22may be turned on when the voltage of the (1-1)th control node GR_Q1is in the first level to maintain voltages of intermediate nodes of the (2-1)th transistor M2-1and (2-2)th transistor M2-2, intermediate nodes of the (3-1)th transistor M3-1and (3-2)th transistor M3-2, and intermediate nodes of the (1-1)th transistor M1-1and (1-2)th transistor M1-2, which are connected to the node GR_A, to the first level, thereby preventing a voltage drop caused by a current leakage of the first control node GR_Q when the first control node GR_Q is in a floating state.

The first output circuit166may be configured to output the third gate signal GR to the third gate line GRL of a corresponding row and/or the second gate line GIL of another row. The first output circuit166may include the ninth transistor M9, the tenth transistor M10, and the eleventh transistor M11, which are connected between the first voltage terminal and the second voltage terminal. The first output circuit166may further include the second capacitor C2. A second control node GR_QB may include a (2-1)th control node GR_QB1and the (2-2)th control node GR_QB2.

The ninth transistor M9(pull-up transistor) may be connected between the first voltage terminal and the first output terminal OUT1, and the gate thereof may be connected to the (1-2)th control node GR_Q2. The second capacitor C2may be connected between the (1-2)th control node GR_Q2and the first output terminal OUT1.

The ninth transistor M9may be turned on when the voltage of the (1-2)th control node GR_Q2is in the first level, and configured to output the first voltage VGH_GR as the third gate signal GR through the first output terminal OUT1.

The tenth transistor M10(pull-down transistor) may be connected between the first output terminal OUT1and the second voltage terminal, and the gate thereof may be connected to the (2-1)th control node GR_QB1. The tenth transistor M10may be turned on when the voltage of the (2-1)th control node GR_QB1is in the first level, and configured to output the second voltage VGL_GR as the third gate signal GR through the first output terminal OUT1.

The eleventh transistor M11(pull-down transistor) may be connected between the first output terminal OUT1and the second voltage terminal, and the gate thereof may be connected to the (2-2)th control node GR_QB2. The eleventh transistor M11may be turned on when the voltage of the (2-2)th control node GR_QB2is in the first level, and configured to output the second voltage VGL_GR as the third gate signal GR through the first output terminal OUT1.

The second output circuit167may be configured to output a carry signal GR_CR to the input terminal IN of the next stage. The second output circuit167may include the sixth transistor M6, the seventh transistor M7, and the eighth transistor M8, which are connected between the first voltage terminal and the third voltage terminal.

The sixth transistor M6(pull-up transistor) may be connected between the first voltage terminal and the second output terminal OUT2, and the gate thereof may be connected to the (1-2)th control node GR_Q2. The sixth transistor M6may be turned on when the voltage of the (1-2)th control node GR_Q2is in the first level, and configured to output the first voltage VGH_GR as the carry signal GR_CR through the second output terminal OUT2.

The seventh transistor M7(pull-down transistor) may be connected between the second output terminal OUT2and the second voltage terminal, and the gate thereof may be connected to the (2-1)th control node GR_QB1. The seventh transistor M7may be turned on when a voltage of the (2-1)th control node GR_QB1is in the first level, and configured to output a third voltage VGL3_GR as the carry signal GR_CR through the second output terminal OUT2.

The eighth transistor M8(pull-down transistor) may be connected between the second output terminal OUT2and the third voltage terminal, and the gate thereof may be connected to the (2-2)th control node GR_QB2. The eighth transistor M8may be turned on when a voltage of the (2-2)th control node GR_QB2is in the first level, and configured to output a third voltage VGL2_GR as the carry signal GR_CR through the second output terminal OUT2.

The first control circuit162may control a voltage of the first control node GR_Q according to a second clock signal GR_CLK2and a voltage of the second control node GR_QB. The first control circuit162may include the second transistor M2, the third transistor M3, the fifth transistor M5, and the first capacitor C1.

The second transistor M2may include the (2-1)th transistor M2-1and the (2-2)th transistor M2-2, which are connected between the (1-1)th control node GR_Q1and the third voltage terminal. The gates of the (2-1)th transistor M2-1and (2-2)th transistor M2-2may be connected to the (2-2)th control node GR_QB2. The (2-1)th transistor M2-1and (2-2)th transistor M2-2may be turned on when the (2-2)th control node GR_QB2is in the first level to maintain the voltage of the (1-1)th control node GR_Q1to the second level.

The third transistor M3may include the (3-1)th transistor M3-1and the (3-2)th transistor M3-2, which are connected between the (1-1)th control node GR_Q1and the third voltage terminal. The gates of the (3-1)th transistor M3-1and (3-2)th transistor M3-2may be connected to the (2-1)th control node GR_QB1. The (3-1)th transistor M3-1and (3-2)th transistor M3-2may be turned on when the (2-1)th control node GR_QB1is in the first level to maintain the voltage of the (1-1)th control node GR_Q1to the second level.

The fifth transistor M5may be connected between the (1-2)th control node GR_Q2and the second clock terminal to which the second clock signal GR_CLK2is input, and the gate thereof may be connected to the (1-2)th control node GR_Q2. The first capacitor C1may be connected between the (1-2)th control node GR_Q2and a node GR_I. The fifth transistor M5may be turned on when the (1-2)th control node GR_Q2is in the first level and configured to transmit the second clock signal GR_CLK2to one end of the first capacitor C1. When the second clock signal GR_CLK2is in the first level, the voltage of the (1-2)th control node GR_Q2may be boosted to be greater than the first voltage VGH_GR by the first capacitor C1and the turned-on fifth transistor M5.

The second control circuit163may reverse the voltage level of the first control node GR_Q according to the second voltage VGL_GR, the third voltage VGL2_GR, a fourth voltage GR_GB11, and a fifth voltage GR_GB12, and supply the same to the second control node GR_QB, thereby controlling the voltage of the second control node GR_QB.

The second control circuit163may include the twelfth transistor M12, the thirteenth transistor M13, the fourteenth transistor M14, the fifteenth transistor M15, the sixteenth transistor M16, the seventeenth transistor M17, the eighteenth transistor M18, the nineteenth transistor M19, the twentieth transistor M20, the21sttransistor M21, the third capacitor C3, and the fourth capacitor C4.

The twelfth transistor M12may include a (12-1)th transistor M12-1and a (12-2)th transistor M12-2, which are connected to each other in series between a node GR_C and the fourth voltage terminal to which the fourth voltage GR_GB11is input. Gates of the (12-1)th transistor M12-1and (12-2)th transistor M12-2may be connected to the fourth voltage terminal. The thirteenth transistor M13may be connected between the fourth voltage terminal and a node GR_G, and the gate thereof may be connected to the node GR_C. The fourteenth transistor M14may be connected between the node GR_G and the (2-1)th control node GR_QB1, and the gate thereof may be connected to the second clock terminal. The fifteenth transistor M15may be connected between the node GR_C and the second voltage terminal, and the gate thereof may be connected to the (1-1)th control node GR_Q1. The sixteenth transistor M16may be connected between the (2-1)th control node GR_QB1and the third voltage terminal, and the gate thereof may be connected to the (1-1)th control node GR_Q1.

The seventeenth transistor M17may include the (17-1)th transistor M17-1and the (17-2)th transistor M17-2, which are connected to each other in series between a node GR_E and the fifth voltage terminal to which the fifth voltage GR_GB12is input. The gates of the (17-1)th transistor M17-1and (17-2)th transistor M17-2may be connected to the fifth voltage terminal. The eighteenth transistor M18may be connected between the fifth voltage terminal and a node GR_H, and the gate thereof may be connected to the node GR_E. The nineteenth transistor M19may be connected between the node GR_H and the (2-2)th control node GR_QB2, and the gate thereof may be connected to the second clock terminal. The twentieth transistor M20may be connected between the node GR_E and the second voltage terminal, and the gate thereof may be connected to the (1-1)th control node GR_Q1. The21sttransistor M21may be connected between the (2-2)th control node GR_QB2and the third voltage terminal, and the gate thereof may be connected to the (1-1)th control node GR_Q1.

The third capacitor C3may be connected between the (2-1)th control node GR_QB1and the node GR_C. The fourth capacitor C4may be connected between the (2-2)th control node GR_QB2and the node GR_E. When the voltages of the (2-1)th control node GR_QB1and (2-2)th control node GR_QB2are switched from the first level to the second level by the third capacitor C3and fourth capacitor C4, the thirteenth transistor M13and the eighteenth transistor M18may be quickly turned off.

The fourth voltage GR_GB11and the fifth voltage GR_GB12may be supplied in voltages of the first level or the second level by alternating in frame units. When the fourth voltage GR_GB11is in the first level and the fifth voltage GR_GB12is in the second level, the voltage of the (2-1)th control node GR_QB1may be in the first level and the voltage of the (2-2)th control node GR_QB2may be in the second level. When the fifth voltage GR_GB12is in the first level and the fourth voltage GR_GB11is in the second level, the voltage of the (2-2)th control node GR_QB2may be in the first level and the voltage of the (2-1)th control node GR_QB1may be in the second level.

The tenth transistor M10and the eleventh transistor M11, and the seventh transistor M7and the eighth transistor M8may be turned on while alternating in frame units according to the fourth voltage GR_GB11and the fifth voltage GR_GB12. Accordingly, changes in threshold voltages of the tenth transistor M10and the eleventh transistor M11, and the seventh transistor M7and the eighth transistor M8may be reduced or prevented.

InFIGS.35to37, gates of some transistors of each stage may be a dual-gate transistor including a pair of a first gate and a second gate. According to an embodiment, the first gate may be a top gate provided on a semiconductor and the second gate may be a bottom gate provided below the semiconductor. The dual-gate transistor may be turned on or off according to a voltage level of a signal input to the first gate. Among the dual-gate transistors, some transistors may receive a voltage of the same polarity for the first gate and the second gate, and some transistors may receive voltages of different polarities for the first gate and the second gate. In an embodiment, for example, the first gate and second gate of some transistors may be connected to the same node (or terminal), and the first gate and second gate of some transistors may be connected to different nodes (or terminals).

FIG.38is a cross-sectional view of a structure of a display element, according to an embodiment.FIGS.39A to41are cross-sectional views of a structure of a display element, according to embodiments.

Referring toFIG.38, the organic light-emitting diode OLED, as the display element according to an embodiment, may include a pixel electrode211, an opposing electrode215, and an intermediate layer213between the pixel electrode211(first electrode or anode) and the opposing electrode215(second electrode or cathode).

In an embodiment, the pixel electrode211may include a transparent conducting oxide, such as indium tin oxide (“ITO”), indium zinc oxide (“IZO”), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (“IGO”), or aluminum zinc oxide (“AZO”). The pixel electrode211may include a reflective layer including silver (Ag), magnesium (Mg), aluminum (AI), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), or a compound thereof. In an embodiment, for example, the pixel electrode211may have a three-layer structure of ITO/Ag/ITO.

The opposing electrode215may be disposed on the intermediate layer213. The opposing electrode215may include a metal having a low work function, an alloy, an electric conductive compound, or an arbitrary combination thereof. In an embodiment, for example, the opposing electrode215may include lithium (Li), Ag, Mg, Al, Al—Li, calcium (Ca), Mg—In, Mg—Ag, ytterbium (Yb), Ag—Yb, ITO, IZO, or an arbitrary combination thereof. The opposing electrode215may be a transparent electrode, a semi-transparent electrode, or a reflective electrode.

The intermediate layer213may include a high-molecular weight organic material or low-molecular weight organic material, which emit light of a certain color. The intermediate layer213may further include, in addition to various organic materials, a metal-containing compound, such as an organic metal compound, and an inorganic material, such as a quantum dot.

According to an embodiment, the intermediate layer213may include one emission layer, and a first functional layer and a second functional layer below and on the emission layer, respectively. The first functional layer may include, for example, a hole transport layer (“HTL”) or may include an HTL and a hole injection layer (“HIL”). The second functional layer may include an electron transport layer (“ETL”) and/or an electron injection layer (“EIL”). The first functional layer or the second functional layer may be omitted. The first functional layer and second functional layer may be integrally formed to correspond to the plurality of organic light-emitting diodes OLED included in the display area DA.

According to an embodiment, the intermediate layer213may include two or more emitting units sequentially stacked between the pixel electrode211and the opposing electrode215, and a charge generation layer provided between the two emitting units. When the intermediate layer213includes the emitting unit and the charge generation layer, the organic light-emitting diode OLED may be a tandem light-emitting element. The organic light-emitting diode OLED may have a stack structure of a plurality of emitting units, and thus have improved color purity and light-emitting efficiency.

One emitting unit may include the emission layer, and the first functional layer and the second functional layer below and on the emission layer, respectively. The charge generation layer may include a negative charge generation layer and a positive charge generation layer. The light-emitting efficiency of the organic light-emitting diode OLED that is the tandem light-emitting element including the plurality of emission layers may be further increased by the negative charge generation layer and the positive charge generation layer.

The negative charge generation layer may be an n-type charge generation layer. The negative charge generation layer may supply electrons. The negative charge generation layer may include a host and a dopant. The host may include an organic material. The dopant may include a metal material. The positive charge generation layer may be a p-type charge generation layer. The positive charge generation layer may supply holes. The positive charge generation layer may include a host and a dopant. The host may include an organic material. The dopant may include a metal material.

According to an embodiment, as shown inFIG.39A, the organic light-emitting diode OLED may include a first emitting unit EU1including a first emission layer EL1and a second emitting unit EU2including a second emission layer EL2, which are sequentially stacked. A charge generation layer CGL may be provided between the first emitting unit EU1and the second emitting unit EU2. In an embodiment, for example, the organic light-emitting diode OLED may include the pixel electrode211, the first emission layer EL1, the charge generation layer CGL, the second emission layer EL2, and the opposing electrode215, which are sequentially stacked in the stated order. The first functional layer and the second functional layer may be provided below and on the first emission layer EL1, respectively. The first functional layer and the second functional layer may be provided below and on the second emission layer EL2, respectively. The first emission layer EL1may be a blue emission layer and the second emission layer EL2may be a yellow emission layer.

According to an embodiment, as shown inFIG.39B, the organic light-emitting diode OLED may include the first emitting unit EU1and a third emitting unit EU3, which include the first emission layer EL1, and the second emitting unit EU2including the second emission layer EL2. A first charge generation layer CGL1may be provided between the first emitting unit EU1and the second emitting unit EU2, and a second charge generation layer CGL2may be provided between the second emitting unit EU2and the third emitting unit EU3. In an embodiment, for example, the organic light-emitting diode OLED may include the pixel electrode211, the first emission layer EL1, the first charge generation layer CGL1, the second emission layer EL2, the second charge generation layer CGL2, the first emission layer EL1, and the opposing electrode215, which are stacked in the stated order. The first functional layer and the second functional layer may be provided below and on the first emission layer EL1, respectively. The first functional layer and the second functional layer may be provided below and on the second emission layer EL2, respectively. The first emission layer EL1may be a blue emission layer and the second emission layer EL2may be a yellow emission layer.

According to an embodiment, in the organic light-emitting diode OLED, the second emitting unit EU2may further include, in addition to the second emission layer EL2, a third emission layer EL3and/or a fourth emission layer EL4, which is in direct contact with a bottom and/or a top of the second emission layer EL2. Here, the direct contact may indicate that another layer is not arranged between the second emission layer EL2and the third emission layer EL3and/or between the second emission layer EL2and the fourth emission layer EL4. The third emission layer EL3may be a red emission layer and the fourth emission layer EL4may be a green emission layer.

In an embodiment, for example, as shown inFIG.39C, the organic light-emitting diode OLED may include the pixel electrode211, the first emission layer EL1, the first charge generation layer CGL1, the third emission layer EL3, the second emission layer EL2, the second charge generation layer CGL2, the first emission layer EL1, and the opposing electrode215, which are sequentially stacked in the stated order. Alternatively, as shown inFIG.39D, the organic light-emitting diode OLED may include the pixel electrode211, the first emission layer EL1, the first charge generation layer CGL1, the third emission layer EL3, the second emission layer EL2, the fourth emission layer EL4, the second charge generation layer CGL2, the first emission layer EL1, and the opposing electrode215, which are sequentially stacked in the stated order.

FIG.40Ais a cross-sectional view showing an example of the organic light-emitting diode OLED ofFIG.39C, andFIG.40Bis a cross-sectional view showing an example of the organic light-emitting diode OLED ofFIG.39D.

Referring toFIG.40A, the organic light-emitting diode OLED may include the first emitting unit EU1, the second emitting unit EU2, and the third emitting unit EU3, which are sequentially stacked in the stated order. The first charge generation layer CGL1may be provided between the first emitting unit EU1and the second emitting unit EU2, and the second charge generation layer CGL2may be provided between the second emitting unit EU2and the third emitting unit EU3. The first charge generation layer CGL1and the second charge generation layer CGL2may each include a negative charge generation layer nCGL and a positive charge generation layer pCGL.

The first emitting unit EU1may include a blue emission layer BML. The first emitting unit EU1may further include a hole injection layer HIL and a hole transport layer HTL between the pixel electrode211and the blue emission layer BML. According to an embodiment, a p-doping layer further included between the hole injection layer HIL and the hole transport layer HTL. The p-doping layer may be formed by doping the hole injection layer HIL with a p-type doping material. According to an embodiment, at least one of a blue light auxiliary layer, an electron blocking layer, and a buffer layer may be further provided between the blue emission layer BML and the hole transport layer HTL. The blue light auxiliary layer may enhance light-emitting efficiency of the blue emission layer BML. The blue light auxiliary layer may enhance the light-emitting efficiency of the blue emission layer BML by adjusting a hole charge balance. The electron blocking layer may prevent electron injection to the hole transport layer HTL. The buffer layer may compensate for a resonance distance according to a wavelength of light emitted from an emission layer.

The second emitting unit EU2may include a yellow emission layer YML and a red emission layer RML in direct contact with the yellow emission layer YML below the yellow emission layer YML. The second emitting unit EU2may further include the hole transport layer HTL between the positive charge generation layer pCGL of the first charge generation layer CGL1and the red emission layer RML, and an electron transport layer ETL between the yellow emission layer YML and the negative charge generation layer nCGL of the second charge generation layer CGL2.

The third emitting unit EU3may include the blue emission layer BML. The third emitting unit EU3may further include the hole transport layer HTL between the positive charge generation layer pCGL of the second charge generation layer CGL2and the blue emission layer BML. The third emitting unit EU3may further include the electron transport layer ETL and an electron injection layer EIL between the blue emission layer BML and the opposing electrode215. The electron transport layer ETL may be a single layer or a multilayer. According to an embodiment, at least one of the blue light auxiliary layer, the electron blocking layer, and the buffer layer may be further provided between the blue emission layer BML and the hole transport layer HTL. At least one of a hole blocking layer and the buffer layer may be further provided between the blue emission layer BML and the electron transport layer ETL. The hole blocking layer may prevent hole injection to the electron transport layer ETL.

The organic light-emitting diode OLED shown inFIG.40Bhas the same configuration as the organic light-emitting diode OLED shown inFIG.40A, except for a stack structure of the second emitting unit EU2. Referring toFIG.40B, the second emitting unit EU2may include the yellow emission layer YML, the red emission layer RML in direct contact with the yellow emission layer YML below the yellow emission layer YML, and a green emission layer GML in direct contact with the yellow emission layer YML on the yellow emission layer YEML. The second emitting unit EU2may further include the hole transport layer HTL between the positive charge generation layer pCGL of the first charge generation layer CGL1and the red emission layer RML, and the electron transport layer ETL between the green emission layer GML and the negative charge generation layer nCGL of the second charge generation layer CGL2.

FIG.41is a cross-sectional view of a structure of a pixel of a display device, according to an embodiment.

Referring toFIG.41, the display device may include a plurality of pixels. The plurality of pixels may include the first pixel PX1, the second pixel PX2, and the third pixel PX3. The first pixel PX1, the second pixel PX2, and the third pixel PX3may each include the pixel electrode211, the opposing electrode215, and the intermediate layer213. According to an embodiment, the first pixel PX1may be a red pixel, the second pixel PX2may be a green pixel, and the third pixel PX3may be a blue pixel. Here, the pixel may include the organic light-emitting diode OLED as a display element, and the organic light-emitting diode OLED of each pixel may be connected (e.g., electrically connected) to a pixel circuit.

The pixel electrode211may be provided independently to each of the first pixel PX1, the second pixel PX2, and the third pixel PX3.

The intermediate layer213of the organic light-emitting diode OLED of each of the first pixel PX1, the second pixel PX2, and the third pixel PX3may include the first emitting unit EU1and the second emitting unit EU2, which are sequentially stacked, and the charge generation layer CGL between the first emitting unit EU1and the second emitting unit EU2. The charge generation layer CGL may include the negative charge generation layer nCGL and the positive charge generation layer pCGL. The charge generation layer CGL may be a common layer formed consecutively on the first pixel PX1, the second pixel PX2, and the third pixel PX3.

The first emitting unit EU1of the first pixel PX1may include the hole injection layer HIL, the hole transport layer HTL, the red emission layer RML, and the electron transport layer ETL, which are sequentially stacked in the stated order, on the pixel electrode211.

The first emitting unit EU1of the second pixel PX2may include the hole injection layer HIL, the hole transport layer HTL, the green emission layer GML, and the electron transport layer ETL, which are sequentially stacked in the stated order, on the pixel electrode211. The first emitting unit EU1of the third pixel PX3may include the hole injection layer HIL, the hole transport layer HTL, the blue emission layer BML, and the electron transport layer ETL, which are sequentially stacked in the stated order, on the pixel electrode211. Each of the hole injection layers HIL, the hole transport layers HTL, and the electron transport layers ETL of the first emitting units EU1may be a common layer consecutively formed on the first pixel PX1, the second pixel PX2, and the third pixel PX3.

The second emitting unit EU2of the first pixel PX1may include the hole transport layer HTL, an auxiliary layer AXL, the red emission layer RML, and the electron transport layer ETL, which are sequentially stacked in the stated order, on the charge generation layer CGL. The second emitting unit EU2of the second pixel PX2may include the hole transport layer HTL, the green emission layer GML, and the electron transport layer ETL, which are sequentially stacked in the stated order, on the charge generation layer CGL. The second emitting unit EU2of the third pixel PX3may include the hole transport layer HTL, the blue emission layer BML, and the electron transport layer ETL, which are sequentially stacked in the stated order, on the charge generation layer CGL. Each of the hole transport layers HTL and the electron transport layers ETL of the second emitting units EU2may be a common layer consecutively formed on the first pixel PX1, the second pixel PX2, and the third pixel PX3. According to an embodiment, at least one of the hole blocking layer and the buffer layer may be further provided between an emission layer and the electron transport layer ETL, in the second emitting units EU2of the first pixel PX1, the second pixel PX2, and the third pixel PX3.

A thickness H1of the red emission layer RML, a thickness H2of the green emission layer GML, and a thickness H3of the blue emission layer BEML may be determined according to a resonance distance. The auxiliary layer AXL is a layer added to adjust the resonance distance, and may include a resonance auxiliary material. In an embodiment, for example, the auxiliary layer AXL may include the same material as the hole transport layer HTL.

InFIG.41, the auxiliary layer AXL is provided only in the first pixel PX1, but an embodiment of the disclosure is not limited thereto. For another example, the auxiliary layer AXL may be provided in at least one of the first pixel PX1, the second pixel PX2, and the third pixel PX3, so as to adjust the resonance distance of each of the first pixel PX1, the second pixel PX2, and the third pixel PX3.

The display device may further include a capping layer217provided outside the opposing electrode215. The capping layer217may enhance light-emitting efficiency according to the principle of constructive interference. Accordingly, light-extracting efficiency of the organic light-emitting diode OLED may be increased, and thus light-emitting efficiency of the organic light-emitting diode OLED may be enhanced.

One or more embodiments of the disclosure may provide a display device, in which a dead space is minimized and power consumption is reduced. Effects of the disclosure are not limited to the above, and may be variously expanded to the extent that they do not deviate from the scope of the disclosure.

It should be understood that embodiments described herein should be considered in a descriptive sense only and not for purposes of limitation. Descriptions of features or aspects within each embodiment should typically be considered as available for other similar features or aspects in other embodiments. While one or more embodiments have been described with reference to the figures, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope as defined by the following claims.