Patent ID: 12191266

DETALLED DESCRIPTION

According to one embodiment, a semiconductor device includes a silicon substrate, a first layer, a second layer, a barrier metal, and a gate pad. The first layer is formed of an oxide film provided on an upper surface of the silicon substrate. The second layer is a layer at least selectively having a projecting and recessed part on an upper surface of the first layer, the projecting and recessed part having a projection and recess deeper than a projection and recess occurring when the layer is formed in a planar shape. The barrier metal is formed on an upper surface of the second layer according to a shape of the projecting and recessed part. The gate pad is in close contact with the silicon substrate via the barrier metal.

Hereinafter, embodiments will be explained referring to the drawings. It should be noted that this disclosure explains the formation of a gate pad, and therefore the illustration and explanation of a semiconductor to be formed in a silicon substrate are omitted. Further, the ratio in size between elements, the aspect ratio or angle, and the like are changed for easy understanding of the structure in the drawings, but the contents of the embodiments are not limited to the ratios, and the elements are constituted in appropriate sizes. Further, a portion illustrated as having an angular shape may have a shape rounded at its angle depending on the specification of process such as etching or design configuration. Besides, the expression of an upper surface is used, and this indicates a surface on the upper side in the vertical direction in a general semiconductor process. Further, a projecting and recessed part is explained, and the number of grooves of the projecting and recessed part in each drawing is illustrated as a not-limited example and can be arbitrarily changed.

First Embodiment

FIG.1is a sectional view schematically illustrating a part of a semiconductor device according to a first embodiment.

A semiconductor device1is, for example, an IGBT (Insulated Gate Bipolar Transistor). The semiconductor device1includes a silicon substrate (semiconductor substrate)10, an oxide film12, an interlayer film14, polysilicon16, barrier metal18, and a gate pad20. The semiconductor device1operates as a power device by applying voltage via the gate pad20to a semiconductor layer formed in the silicon substrate10.

The silicon substrate10is a substrate for forming various semiconductor layers, and, for example, a drift layer and a collector layer are formed therein. In the case where the semiconductor device1is an n-channel IGBT as a not-limited example, a channel is formed in a p-type semiconductor layer formed in an upper part of an n-type drift layer by applying voltage from the gate pad20via the oxide film12. A collector current flows from a collector to an emitter electrode formed on the silicon substrate10via the p-type semiconductor layer, the n-type drift layer, and the channel. As a matter of course, in the case where the semiconductor device1is a p-channel IGBT, a collector current is appropriately output based on the voltage applied to the gate pad20.

The oxide film12is a gate insulating film formed as a first layer on the silicon substrate10and is formed, for example, of a thermal oxide film (SiO2) obtained by thermally oxidizing Si. Besides, as another example, the thermal oxide film may be replaced by a thermal nitride film (SiON) obtained by thermally nitriding Si.

The interlayer film14is an interlayer insulating film formed on the oxide film12and separates wiring placed on the silicon substrate10. The interlayer film14is, for example, an insulating film obtained by doping fluorine or the like into the SiO2film.

The polysilicon16is selectively formed in the interlayer film14on the oxide film12of the silicon substrate10in a manner to be in contact with the barrier metal18. In a process of manufacturing the semiconductor device1, a silicide composed of the polysilicon16and the material of the barrier metal18is formed. The formation of the silicide improves the adhesiveness between the silicon substrate10and the barrier metal18(and the gate pad20). In this embodiment, the interlayer film14and the polysilicon16form a second layer2.

The barrier metal18is a metal film formed between the polysilicon16(a predetermined region of the second layer2) and the gate pad20. The barrier metal18is a metal film formed for preventing the diffusion or preventing the cross reaction of metal materials used for the gate pad20. For the barrier metal18, for example, a material which forms the silicide with the polysilicon16and is excellent in adhesiveness with the gate pad20is used.

The gate pad20operates as a gate electrode and controls a current flowing through the semiconductor device1by a voltage input into the gate pad20. For the gate pad20, for example, Al, AlSi, AlCu, AlSiCu, Cu, Au, W, WSi, Ti, TiSi or the like may be used.

Depending on the material of the gate pad20, the material of the barrier metal18is appropriately selected. For the barrier metal18, for example, Ti or TIN may be used when the gate pad20is Al or AlSi, or Ta or TaN may be used when the gate pad20is Cu. Further, the material of the gate pad20is not limited to these materials, but only needs to be suitably formed of a material having following characteristics. In the following, as an example, the gate pad20is explained as AlSi and the barrier metal18is explained as Ti or TIN.

In this embodiment, the polysilicon16and the barrier metal18are in contact with each other not at a flat surface as an interface but have a projecting and recessed part (first projection and recess)100selectively formed in a cross-section. A height (or depth) h of the projecting and recessed part100is sufficiently deeper or lower than a projection and recess (up to about 150 nm) occurring when a first surface16aof the polysilicon16is formed as the flat surface. For example, h may be about 300 to 600 nm, and is made sufficiently30deeper or lower than the projection and recess occurring when the polysilicon16is formed. In other words, a recces of the projecting and recessed part100formed on the polysilicon16has a sufficiently larger depth than the depth of the projection and recess which may occur when the polysilicon16is formed flat.

The recess of the projecting and recessed part (first projection and recess)100may be deeper or lower than a first surface surrounding the first projection and recess100. The first surface16ais a plain surface, however, the first surface16ahas the tiny projection and recess unintentionally produced in the semiconductor manufacturing process. In this case, a height of the projection and recess of the first surface16acorresponds to a height of the projection and recess occurring when the first surface16aof the polysilicon is formed as the flat surface.

Note that on the barrier metal18, a meal film of W or the like may be formed, to an extent not to fill up the projection and recess, in a region of a side wall of the projecting and recessed part formed on the barrier metal18.

According to this shape, the gate pad20is also formed having a projection and recess. The gate pad20formed in this manner can suppress bonding peeling between the silicon substrate10and the gate pad20by the anchoring effect. Further, the formation of the silicide at the interface can further suppress the bonding peeling. Besides, when the metal film of W or the like is formed at the contact surface between the gate pad20and the barrier metal18, this metal film can further improve the adhesiveness. These characteristics are the same in the following embodiments.

The manufacturing process of the semiconductor device1according to this embodiment will be explained usingFIG.2toFIG.11.

First, as illustrated inFIG.2, the semiconductor layer is formed in the silicon substrate10by various processes so as to suitably operate, and the oxide film12is formed on the upper surface of the silicon substrate10. Then, the polysilicon16is formed on the upper surface of the oxide film12. This process is executed by a general process.

Next, as illustrated inFIG.3, a mask30is selectively formed on the upper surface of the polysilicon16. The mask30is formed according to a region where the gate electrode is arranged on the silicon substrate10such that the polysilicon16is formed on the region. In the case of photolithography, the mask30is photoresist.

Next, as illustrated inFIG.4, the polysilicon16is etched. This etching may be executed by RIE (Reactive Ion Etching) or CDE (Chemical Dry Etching).

Next, as illustrated inFIG.5, the mask30formed in the process ofFIG.3is removed once, and a new mask32is formed. The mask32is selectively formed in a manner that the projecting and recessed part is suitably generated on the polysilicon16.

Next, as illustrated inFIG.6, second etching (for example, CDE) of the polysilicon16is executed. This etching process is executed not to remove the polysilicon16down to the interface surface with the oxide film12by etching but executed to form a dent in a recess shape having an appropriate depth. More specifically, the material to be etched in an opening portion of the mask is not completely removed unlike the general CDE process, but the process is finished where the material is removed down to the middle. Through this process, the projecting and recessed part100illustrated inFIG.1is formed.

Next, as illustrated inFIG.7, the mask32is removed, and then the interlayer film14is formed on upper surfaces of the oxide film12and the polysilicon16.

Next, as illustrated inFIG.8, a mask34is formed based on a region where the gate pad is to be formed. The mask34is formed so as to secure a contact region in the interlayer film14where the polysilicon16and the gate pad are electrically connected.

Next, as illustrated inFIG.9, the interlayer film14is selectively removed by the RIE treatment to form the contact region.

Next, as illustrated inFIG.10, the mask34is removed, and then the barrier metal18is film-formed on the upper surfaces of the interlayer film14and the polysilicon16.

Next, as illustrated inFIG.11, a conductor forming the gate pad20is film-formed on the upper surface of the barrier metal18. Excessive portions of the conductor and the barrier metal are removed in a manner to remain in a suitable region, whereby the semiconductor device1illustrated inFIG.1is manufactured.

As an example, the process may be executed so that the polysilicon16is 1000 nm inFIG.2, the width of the opening portion of the mask32is 450 nm inFIG.5, and the depth and the width of a recessed part (recess) of the polysilicon16are 300 nm and 500 nm respectively inFIG.6, but they are not limited to these sizes.

Second Embodiment

FIG.12is a sectional view schematically illustrating a part of a semiconductor device according to a second embodiment.

The semiconductor device1has a plug22in the projecting and recessed part100. Further, the semiconductor device1may include a metal film24between the barrier metal18and the gate pad20at a side wall of a contact region of the gate pad20.

The plug22is a plug formed of, for example, W and is formed to fill the projecting and recessed part100. In other words, W is formed so as to flatten a projection and recess region caused by the projecting and recessed part100formed on the barrier metal18.

The gate pad20is formed on the upper surface flattened by the plug22. Since the lower surface is flat, the upper surface in the contact region of the gate pad20is also formed flat after the film-formation of the gate pad20.

The width and the depth of the projecting and recessed part100may be made to be, for example, 500 nm and 300 nm respectively as in the first embodiment, and the depth may be changed in a range of 300 to 600 nm or the like.

To form the plug22, the projecting and recessed part100of the polysilicon16may be formed not to change in width as compared with the first embodiment.

In order for the formation, for example, the process inFIG.6is executed by RIE in this embodiment. After the RIE treatment, the barrier metal18is film-formed and then the plug22and the metal film24are formed using, for example, W. Thereafter, patterning is performed so as to appropriately form the plug22and the metal film24, and the entire surface is etched back again by RIE. The etch back of the entire surface in the contact region after the film-formation of metal such as W forms the plug22, and the etch back process similarly forms the metal film24on the side wall of the contact region. The metal film24may be removed as needed, but the metal film24causes no problem even if it exists.

According to this embodiment, the bonding peeling can be suppressed by the anchoring effect as in the first embodiment. Further, filling up the recessed part of the polysilicon with the plug flattens the upper surface of the gate pad20formed thereon. The flattening the upper surface of the gate pad20can improve the adhesiveness of the wire in bonding.

Note that the width of the plug22is, but not limited to, 500 nm as an example, and only needs to be a width with which the plug can be appropriately formed.

Third Embodiment

FIG.13is a sectional view schematically illustrating a part of a semiconductor device according to a third embodiment.

The projecting and recessed part100may be configured to include a plug22along its side wall. More specifically, unlike the second embodiment, the recessed part of the barrier metal18along the projecting and recessed part100is not filled but the plug22may be provided along the side wall of the recessed part. To this end, the width of the projecting and recessed part100may be made larger than that in the second embodiment. The width of the projecting and recessed part100can be made to be, but not limited to, for example, 5 μm, and can be made to be a width with which the recessed part of the barrier metal18is not filled up with metal (for example, W).

The process of the semiconductor device1is almost the same as that in the second embodiment other than that the width of the projecting and recessed part100is made larger. However, metal is formed to an extent not to fill up the recessed part of the barrier metal18in the process of film-forming the plug22.

The formation of the projection and recess on the surface of the polysilicon in contact with the barrier metal can suppress the bonding peeling by the anchoring effect.

Fourth Embodiment

FIG.14is a sectional view schematically illustrating a part of a semiconductor device according to a fourth embodiment.

The projecting and recessed part100formed in the polysilicon16may have a form in contact with the oxide film12at least at its lowermost surface. Also in the semiconductor device1of this embodiment, the metal film24may be formed on the side wall of the recessed part of the barrier metal18and a side wall region of the contact region of the gate pad20in the barrier metal18. The width of the projecting and recessed part100can be made to be, but not limited to, for example, 5 μm.

The process of the semiconductor device1is implemented by suitably increasing the pattern width of the mask in the process inFIG.5and etching the polysilicon16by its height by CDE in the process inFIG.6. The subsequent process is the same as that in the first embodiment.

The projection and recess is thus formed on the surface of the polysilicon16in contact with the barrier metal18, thereby suppressing the bonding peeling by the anchoring effect.

Fifth Embodiment

FIG.15is a sectional view schematically illustrating a part of a semiconductor device according to a fifth embodiment.

In the semiconductor device1, the projecting and recessed part100is formed by the interlayer film14on the upper surface of the polysilicon16in the second layer2. The projecting and recessed part100formed by the interlayer film14is formed such that the polysilicon16and the barrier metal18are in contact with each other, at its lower surface. The width of the recessed part (recess) is, for example, 500 nm.

Then, at the recessed part caused by the projecting and recessed part100in the barrier metal18, the plug22is formed such that the recessed part is filled.

The process of the semiconductor device1will be explained. The processes inFIG.2toFIG.4are the same as those in the first embodiment. Thereafter, the processes inFIG.5andFIG.6are not performed but the formation process of the interlayer film14inFIG.7is executed. As an example, the interlayer film14may be formed up to a height of 1000 nm.

FIG.16andFIG.17are sectional views schematically illustrating subsequent processes.

After the formation of the interlayer film14, a mask34is formed based on the pattern for forming the projecting and recessed part using the interlayer film14as illustrated inFIG.16.

Next, as illustrated inFIG.17, the interlayer film14is etched by RIE. In the above example, the interlayer film14is etched by 1000 nm, thereby enabling the formation of the projecting and recessed part using the interlayer film14so that the barrier metal18can come into contact with the polysilicon16at the lower surface of the recessed part.

The subsequent process is the same as that in the second embodiment.

As above, the formation of the projection and recess on the surface of the second layer2in contact with the barrier metal18can suppress the bonding peeling by the anchoring effect. Further, in this embodiment, filling the recessed part of the interlayer film14with the plug22, thereby flattening the upper surface of the gate pad20formed thereon. The flattening the upper surface of the gate pad20can improve the adhesiveness of the wire in bonding. A void width of the recessed part of the interlayer film is, but not limited to, for example, 500 nm, and may take an arbitrary value as long as it is a value with which the plug22is formed.

Sixth Embodiment

FIG.18is a sectional view schematically illustrating a part of a semiconductor device according to a sixth embodiment.

In the semiconductor device1, the projecting and recessed part100is formed using the interlayer film14in the second layer2as in the fifth embodiment. The metal film24is formed on the side wall of the recessed part by the projecting and recessed part100on the upper surface of the barrier metal18.

The process of this semiconductor device1is the one made by combining those of the above-explained fifth embodiment and third embodiment. More specifically, in the etching of the interlayer film14in the fifth embodiment, the pattern of the mask34is changed, and the mask34is arranged so that the void width of the recessed part of the second layer2is, for example, 5 μm in etching of the interlayer film14in the fifth embodiment. Thereafter, the interlayer film14is etched as in the fifth embodiment. Subsequent to the etching, the process of forming the metal film24on the side wall of the recessed part of the barrier metal18is executed as in the third embodiment.

The formation of the projection and recess on the surface of the second layer2in contact with the barrier metal18can suppress the bonding peeling by the anchoring effect.

Seventh Embodiment

FIG.19is a sectional view schematically illustrating a part of a semiconductor device according to a seventh embodiment.

In the semiconductor device1, the projecting and recessed part100is formed using the interlayer film14in the second layer2as in the fifth embodiment. Then, the plug22is formed on the upper surface of the barrier metal18in at least one projecting and recessed part100in the interlayer film14, and the metal film24is formed on the side wall of the barrier metal18in the projecting and recessed part100where the plug22is not formed. The lower surface of the recessed part of the barrier metal18is in contact with the polysilicon16.

The void widths of the recessed parts are, but not limited to, 500 nm and 5 μm as examples in the projecting and recessed parts100of the interlayer film14. In the recessed part having the void width of 500 nm, the recessed part formed in the barrier metal18has the plug22. In the recessed part having the void width of 5 μm, the metal film24is formed on the side wall of the barrier metal18.

The process of this semiconductor device1can be implemented by the process similar to that in the fifth embodiment by changing the pattern of the mask for forming the projecting and recessed part100.

The formation of the projection and recess on the surface of the interlayer film14in contact with the barrier metal18as above can suppress the bonding peeling by the anchoring effect. The case where the widths of the recessed parts of the interlayer film are 500 nm and 5 μm is explained in this embodiment, and the widths can take arbitrary values as long as they are a values with which the plug22can be formed and a value with which the metal film24is formed without forming the plug22, respectively.

Eighth Embodiment

FIG.20is a sectional view schematically illustrating a part of a semiconductor device according to an eighth embodiment.

This semiconductor device1is constituted such that the second layer2includes the interlayer film14and the polysilicon16. The projecting and recessed part100is formed at two stages. More specifically, the projecting and recessed part100is formed of the recessed part formed in the polysilicon16and the projecting part formed using the interlayer film14on the upper surface of the polysilicon16.

In the projecting and recessed part100, the plug22is formed via the barrier metal18. The gate pad20is formed in contact with the upper surfaces of the plug22and the barrier metal18.

The process of the semiconductor device1can be implemented by performing isotropic etching such as RIE inFIG.5toFIG.6and patterning the mask so as to form the projection and recess by the interlayer film14inFIG.8toFIG.9.

As an example where the numerical values are not limited, the void width and the height of the recessed part of the interlayer film14is 500 nm or less and about 1400 nm, respectively. Note that the lower surface of the projecting and recessed part100may be formed in a manner to be in contact with the oxide film12.

The formation of the projection and recess on the surface of the polysilicon and the interlayer film in contact with the barrier metal as above, thereby enabling the suppression of the bonding peeling by the anchoring effect. Further, the filling the recessed parts of the polysilicon16and the interlayer film14with the plug22flattens the surface of the gate pad20formed thereon. The flattening the surface of the gate pad20can improve the adhesiveness of the wire in bonding. The case where the void widths of the recessed parts of the polysilicon16and the interlayer film14are, for example, 500 nm is illustrated, and the void widths may take appropriate values as long as they are values with which the plug22is formed.

Ninth Embodiment

FIG.21is a sectional view schematically illustrating a part of a semiconductor device according to a ninth embodiment.

The semiconductor device1is configured such that the second layer2includes the interlayer film14and the polysilicon16as in the eighth embodiment. The projecting and recessed part100is formed at two stages. More specifically, the projecting and recessed part100is formed of the recessed part formed in the polysilicon16and the projecting part formed using the interlayer film14on the upper surface of the polysilicon16.

As an example where the numerical values are not limited, the void width of the recessed part of the polysilicon16is 500 nm or less, and the recessed part of the polysilicon16is filled up with the plug22. Further, the recessed part (recces) of the polysilicon16has a height of about 300 to 600 nm, and has a shape deeper than the projection and recess (about 150 nm) on the surface after the film-formation of the polysilicon16.

Further, the void width of the recessed part of the interlayer film14is 5 μm, and the metal film24is formed on the side wall of the recessed part of the interlayer film14.

The process of the semiconductor device1is similar to that in the eighth embodiment. The appropriate control of the width of patterning of the mask inFIG.8in the process explained in the eighth embodiment can manufacture the semiconductor device1according to this embodiment.

As an example where the numerical values are not limited, the polysilicon16is film-formed into 1000 nm on the upper surface of the oxide film12. Then, a void pattern having a width of 500 nm is formed on the polysilicon16by an appropriate etching process, and etching is performed to have a width of 500 nm. As a result of this, a recessed part having a height of 300 nm and a width of 500 nm is formed on the surface of the polysilicon16.

Next, the interlayer film14is formed into 1000 nm, then a void pattern having a width of 5 μm is formed above the recessed part of the polysilicon16, and the interlayer film14is etched. As a result of this, a recessed part having a width of 5 μm is formed on the surface of the interlayer film14.

Thereafter, the barrier metal18, the plug22, the metal film24, and the gate pad20are formed, whereby the semiconductor device1according to this embodiment can be manufactured. Note that the lower surface of the projecting and recessed part100may be formed to come into contact with the oxide film12as in the eighth embodiment.

The projection and recess is formed on the surfaces of the polysilicon16and the interlayer film14in contact with the barrier metal18as above, thereby enabling the suppression of the bonding peeling by the anchoring effect. The case where the void width of the recessed part of the polysilicon is 500 nm is explained, and the void width can take an arbitrary value as long as it is a value with which the plug22is formed. Further, the case where the void width of the recessed part of the interlayer film14is 5 μm is explained, and the void width can take an arbitrary value as long as it is a value with which the plug22is not formed.

Tenth Embodiment

In each of the above embodiments, the section of the projecting and recessed part100is explained. Various forms of the projecting and recessed part100in a plan view will be explained in this embodiment. In each of the drawings, the shape of the projecting and recessed part100formed in the second layer2is illustrated in a plan view.FIG.22toFIG.27are views illustrating several not-limited examples in a plan view of the shape of the projecting and recessed part100formed in the second layer2.

As illustrated inFIG.22, the projecting and recessed parts100may be formed in a stripe shape in the second layer2.

As illustrated inFIG.23, each of the projecting and recessed parts100may be formed in a quadrangular shape having a width in the second layer2.

As illustrated inFIG.24, the projecting and recessed part100may be formed in a swirl shape having a width in the second layer2. Note that the swirl shape is composed of a quadrangular shape but may be composed of another polygonal shape, or may be a circular swirl shape having no corner (for example, a spiral shape having a width).

As illustrated inFIG.25, the projecting and recessed parts100may be formed in a shape of a check pattern in the second layer2.

As illustrated inFIG.26, the projecting and recessed parts100may be formed in a honeycomb shape in the second layer2.

As illustrated inFIG.27, the projecting and recessed parts100may be formed in an octagonal shape in the second layer2.

In any of the examples, a projection and recess pattern of the polysilicon16and the interlayer film14can be arranged efficiently using the anchoring effect in consideration of the bonding direction.

While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions. Indeed, the novel embodiments described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the embodiments described herein may be made without departing from the spirit of the inventions. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the inventions.

For example, the above embodiments are each explained as an IGBT, but may be a MOSFET. Further, the embodiments are not limited to these examples. The embodiments in this disclosure can be applied to the formation of an electrode in any of a planar type and a trench type in a semiconductor device having an insulating film and an electrode which applies voltage via the insulating film as several not-limited examples.

For example, the semiconductor device may be a diode. When the semiconductor device is the diode, the pad20may be an anode pad or a cathode pad. The manufacturing process of the pad20(at least one of, the anode pad or the cathode pad) may be same as some above-mentioned embodiments.

As another example, the semiconductor device1may have a source pad produced as same semiconductor manufacturing process as the gate pad20described in some embodiments.