Patent ID: 12200875

DETAILED DESCRIPTION

Reference will now be made in detail to various embodiments, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals will be used throughout the drawings to refer to the same or like parts. One embodiment of components used in the methods of the present disclosure is shown inFIG.1, and is designated generally throughout by the reference numeral100. The components generally include a glass substrate including a plurality of vias having an aspect ratio greater than or equal to 5:1, wherein the aspect ratio is equal to the average thickness t of the glass substrate to the average diameter of the vias, that are filled with an electrically conductive material such that the electrically conductive material has a void volume fraction of less than or equal to 5%.

Unless otherwise expressly stated, it is in no way intended that any method set forth herein be construed as requiring that its steps be performed in a specific order, nor that with any apparatus specific orientations be required. Accordingly, where a method claim does not actually recite an order to be followed by its steps, or that any apparatus claim does not actually recite an order or orientation to individual components, or it is not otherwise specifically stated in the claims or description that the steps are to be limited to a specific order, or that a specific order or orientation to components of an apparatus is not recited, it is in no way intended that an order or orientation be inferred, in any respect. This holds for any possible non-express basis for interpretation, including: matters of logic with respect to arrangement of steps, operational flow, order of components, or orientation of components; plain meaning derived from grammatical organization or punctuation, and; the number or type of embodiments described in the specification.

As used herein, the singular forms “a,” “an” and “the” include plural referents unless the context clearly dictates otherwise. Thus, for example, reference to “a” component includes aspects having two or more such components, unless the context clearly indicates otherwise. Also, the word “or” when used without a preceding “either” (or other similar language indicating that “or” is unequivocally meant to be exclusive—e.g., only one of x or y, etc.) shall be interpreted to be inclusive (e.g., “x or y” means one or both x or y).

The term “and/or” shall also be interpreted to be inclusive (e.g., “x and/or y” means one or both x or y). In situations where “and/or” or “or” are used as a conjunction for a group of three or more items, the group should be interpreted to include one item alone, all the items together, or any combination or number of the items. Moreover, terms used in the specification and claims such as have, having, include, and including should be construed to be synonymous with the terms comprise and comprising.

Unless otherwise indicated, all numbers or expressions, such as those expressing dimensions, physical characteristics, and the like, used in the specification (other than the claims) are understood to be modified in all instances by the term “approximately.” At the very least, and not as an attempt to limit the application of the doctrine of equivalents to the claims, each numerical parameter recited in the specification or claims which is modified by the term “approximately” should be construed in light of the number of recited significant digits and by applying ordinary rounding techniques.

All disclosed ranges are to be understood to encompass and provide support for claims that recite any and all subranges or any and all individual values subsumed by each range. For example, a stated range of 1 to 10 should be considered to include and provide support for claims that recite any and all subranges or individual values that are between and/or inclusive of the minimum value of 1 and the maximum value of 10; that is, all subranges beginning with a minimum value of 1 or more and ending with a maximum value of 10 or less (e.g., 5.5 to 10, 2.34 to 3.56, and so forth) or any values from 1 to 10 (e.g., 3, 5.8, 9.9994, and so forth).

All disclosed numerical values are to be understood as being variable from 0-100% in either direction and thus provide support for claims that recite such values or any and all ranges or subranges that can be formed by such values. For example, a stated numerical value of 8 should be understood to vary from 0 to 16 (100% in either direction) and provide support for claims that recite the range itself (e.g., 0 to 16), any subrange within the range (e.g., 2 to 12.5) or any individual value within that range (e.g., 15.2).

The drawings shall be interpreted as illustrating one or more embodiments that are drawn to scale and/or one or more embodiments that are not drawn to scale. This means the drawings can be interpreted, for example, as showing: (a) everything drawn to scale, (b) nothing drawn to scale, or (c) one or more features drawn to scale and one or more features not drawn to scale. Accordingly, the drawings can serve to provide support to recite the sizes, proportions, and/or other dimensions of any of the illustrated features either alone or relative to each other. Furthermore, all such sizes, proportions, and/or other dimensions are to be understood as being variable from 0-100% in either direction and thus provide support for claims that recite such values or any and all ranges or subranges that can be formed by such values.

The terms recited in the claims should be given their ordinary and customary meaning as determined by reference to relevant entries in widely used general dictionaries and/or relevant technical dictionaries, commonly understood meanings by those in the art, etc., with the understanding that the broadest meaning imparted by any one or combination of these sources should be given to the claim terms (e.g., two or more relevant dictionary entries should be combined to provide the broadest meaning of the combination of entries, etc.) subject only to the following exceptions: (a) if a term is used in a manner that is more expansive than its ordinary and customary meaning, the term should be given its ordinary and customary meaning plus the additional expansive meaning, or (b) if a term has been explicitly defined to have a different meaning by reciting the term followed by the phrase “as used in this document shall mean” or similar language (e.g., “this term means,” “this term is defined as,” “for the purposes of this disclosure this term shall mean,” etc.). References to specific examples, use of “i.e.,” use of the word “invention,” etc., are not meant to invoke exception (b) or otherwise restrict the scope of the recited claim terms. Other than situations where exception (b) applies, nothing contained in this document should be considered a disclaimer or disavowal of claim scope.

In the three-dimensional integrated circuit (3D-IC) industry, stacking devices is a technique being used to increase device performance in a limited space. The performance of the integrated circuit may be further enhanced through the use of thinner substrates and smaller vias, which leads to higher aspect ratios (e.g., aspect ratios the average thickness of the glass substrate to the average diameter of the via of greater than or equal to 4:1), thereby reducing packaging size and stress effects. However, the higher the aspect ratio, the more difficult it is to metallize the sidewalls of the vias, particularly when the vias have small (e.g., less than or equal to 50 μm) diameters, which may lead to voids within the electrically conductive material within the vias after filling.

The methods of the present disclosure enable through-glass vias to be filled with an electrically conductive material, such as copper or another metal, despite the challenges associated with the glass substrate having an aspect ratio of greater than 5:1. As used herein, the term “aspect ratio” refers to the ratio of the average thickness t of the glass substrate to the average diameter of the plurality of vias. For example, by utilizing a method that includes a wet electroless plating step in conjunction with a wet electroplating step, the challenges associated with metallizing vias with a high aspect ratio in a thin glass substrate may be mitigated.

In the embodiment shown inFIG.1, the glass article is in the form of a glass substrate102that includes a plurality of vias104, or precision holes, defined by one or more sidewalls105. For example, in the embodiments described herein, the vias104are circular in cross section and, as such, the vias104have a single sidewall105. However, it should be understood that vias with other cross-sectional geometries are contemplated include, for example vias which have more than one sidewall. The glass substrate102may be used, for example, as an interposer to provide vertical electrical connections within a three-dimensional integrated circuit. The glass substrate102comprises a first face110and a second face112opposite the first face110. The first face110of the glass substrate102is separated from the second face112of the glass substrate102by a thickness t of the glass substrate.

The composition of the glass substrate102is not particularly limited, and may be selected based on the desired end use of the glass substrate102. In some embodiments, the glass substrate102may be a flexible glass substrate. The glass substrate102may be formed from glasses suitable for electronics applications including, for example, WILLOW® glass, Eagle XG™ glass, or Code2318glass, manufactured by Corning, Inc. However, it should be understood that other glasses are contemplated and possible. For example, other types of ion-exchangeable glasses or fused silica may be used to form the glass substrate102. Additionally, the glass substrate102may be in the shape of a wafer having a 10 cm, 15 cm, 20 cm, or 30 cm diameter, for example. However, it should be understood that glass substrates102of other dimensions are contemplated and possible. The thickness of the glass substrate102may also vary depending on its end use, although in various embodiments, the average thickness t of the glass substrate is greater than or equal to 50 μm and less than or equal to 150 μm. For example, the glass substrate102may have a thickness of from greater than or equal to 90 μm and less than or equal to 110 μm. In various embodiments, the glass substrate102has a thickness of less than or equal to about 100 μm. In some embodiments, the glass substrate102has a thickness of less than 100 μm. However, it should be understood that glass substrates of any suitable thickness may be utilized. In embodiments, the thickness of the glass substrate may be measured through interferometric methods at locations within the area of the substrate. Additionally or alternatively, mechanical means (e.g., calipers) may be used to measure the thickness of the glass substrate. Unless otherwise specified, thickness of the glass substrate is measured by interferometric methods.

The plurality of vias104can be formed in the glass substrate102by any suitable method. For example, in embodiments, the plurality of vias104may be drilled in the glass substrate102using a pulsed laser. The laser may be any laser having suitable optical properties for drilling through the glass substrate102as well as a sacrificial cover layer positioned on a surface of the glass substrate102. Suitable lasers include, without limitation, ultra-violet (UV) lasers, such as frequency tripled neodymium doped yttrium orthovanadate (Nd:YVO4) lasers, which emit a beam of coherent light having a wavelength of about 355 nm. The beam of the laser may be directed onto a predetermined location on the surface of the glass substrate and pulsed to form each of the plurality of vias104in the glass substrate102. Alternatively, the plurality of vias may be mechanically machined.

In some embodiments, a diameter of an opening of a via in face110of the glass substrate102and a diameter of an opening of the via in face112of the glass substrate102may be the same such that the via is cylindrical. Alternatively, a diameter of an opening of a via in face110of the glass substrate102and a diameter of an opening of the via in face112of the glass substrate102may differ by 2 μm or less, such that the via is substantially cylindrical. In other embodiments, a diameter of the vias may decrease from one face of the glass substrate102to the other face of the glass substrate102such that the vias have a cone shape. In various embodiments, each of the plurality of vias has an average diameter of greater than or equal to 8 μm and less than or equal to 20 μm, or greater than or equal to 8 μm and less than or equal to 12 μm. For example, each of the plurality of vias may have an average diameter of about 20 μm, about 15 μm, about 12 μm, or about 10 μm. As used herein, the term “average diameter” refers to the diameter of the via normal to the axis of the via through the thickness of the glass, averaged along the axis of the via. In embodiments, the average diameter is measured using an SEM cross-section or visual metrology from the top/bottom side (e.g., averaging the top, waist (or some location within the via within the thickness of the glass), and the bottom). Unless otherwise specified, the average diameter is measured using an SEM cross-section.

According to various embodiments, the aspect ratio is greater than or equal to 3:1, or greater than or equal to 5:1. For example, the aspect ratio may be greater than or equal to 3:1 and less than or equal to 16:1, greater than or equal to 5:1 and less than or equal to 12:1, or greater than or equal to 5:1 and less than or equal to 10:1.

In the embodiments described herein, the plurality of vias104are filled with an electrically conductive material500(shown inFIG.5). The electrically conductive material may be, by way of example and not limitation, copper, silver, aluminum, nickel, alloys thereof, and combinations thereof. In some embodiments, the plurality of vias104are filled with a copper-containing material, such as a copper alloy. In various embodiments, the electrically conductive material in each of the plurality of filled vias has a void volume fraction of less than or equal to 5%, less than or equal to 4%, less than or equal to 3%, or even less than or equal to 1% by volume. In some embodiments, the electrically conductive material in each of the plurality of filled vias has a void volume fraction of less than or equal to 1%. In some embodiments, the electrically conductive material in each of the plurality of filled vias is free of voids (i.e., the electrically conductive material in each of the plurality of filled vias has a void volume fraction of 0%). In embodiments herein, the void volume is measured based on analysis of a scanning electron microscope (SEM) cross-section image or an X-ray CT scan. Unless otherwise specified, the void volume fraction is measured based on analysis of an SEM cross-section. Accordingly, “free of voids” means that there are no voids visible according to the resolution of the imaging equipment.

FIG.2depicts one embodiment of a method200for filling, or metallizing, the vias with the electrically conductive material. In particular, as shown inFIG.2, the method generally includes functionalizing a surface of the glass substrate (step202), applying an electroless plating solution to deposit a seed layer on the functionalized surface (step204), wetting the glass substrate including the seed layer (step206) and employing an electroplating process to reduce a conductive material within the vias on the seed layer (step208). In embodiments, the method200is performed as a wet process that enables the electrically conductive material to be substantially void-free manner without the use of a temporary carrier, thereby enabling the method200to be employed in roll-to-roll manufacturing processes. As used herein, the term “substantially void-free” means that the electrically conductive material has a void volume fraction of less than or equal to 5%, less than or equal to 1%, less than or equal to 0.5%, less than or equal to 0.1%, less than or equal to 0.05%, or even 0%.

In some embodiments, prior to functionalizing the surface of the glass substrate, the glass substrate may be optionally cleaned (optional step201). Cleaning may be performed according to any conventional cleaning process known and used in the art to remove organic residues and enrich hydroxyl groups on the surface of the glass substrate. For example, the glass substrate may be cleaned by a process such as O2plasma, UV-ozone, or RCA cleaning to remove organics and other impurities (metals, for example) that would interfere with the silane reacting with the surface silanol groups. Washes based on other chemistries may also be used, for example, HF or H2SO4wash chemistries. In some embodiments, the glass substrate may be cleaned with a detergent in an ultrasonic bath and rinsed with deionized water. In various embodiments, the glass substrate has a water contact angle of less than or equal to 7 degrees, less than or equal to 6 degrees, less than or equal to 5 degrees after cleaning, less than or equal to 4 degrees, or less than or equal to 2 degrees as measured using an goniometer, such as DSA100 available from Kruss GmbH (Germany).

At step202, the surface of the glass substrate102is functionalized with a silane. In embodiments, the surface of the glass substrate102that is functionalized includes one or more of the sidewall(s)105of the plurality of vias104, the first surface110of the glass substrate102, and the second surface112of the glass substrate102. Silanes are chosen so as to produce a suitable surface energy on the functionalized surfaces, and so as to have sufficient thermal stability upon exposure to elevated temperatures experienced by the glass substrate102in downstream processing. Suitable silanes may include, by way of example and not limitation, cationic silanes or polymers, such as 3-(2-amino ethylamino)propyldimethoxy-methylsilane. Moreover, in various embodiments, silane modification of the surface of the glass substrate modifies the glass surface to have a positive charge and enables binding of the palladium (Pd) used in the electroless plating to the surface of the glass substrate, as will be described in greater detail below.

In embodiments, the surface functionalization is performed by diluting a silane in isopropanol to form a silane solution and submerging the glass substrate in the silane solution. Optionally, ultrasonic energy is applied to the silane solution with the submerged glass substrate and the glass substrate to enhance wetting and bubble removal. In embodiments, the glass substrate is soaked in the silane solution for a predetermined period of time. For example, the glass substrate may be submerged in the silane solution for a period of time of greater than or equal to 15 minutes, greater than or equal to 20 minutes, or greater than or equal to 30 minutes. After soaking in the silane solution, the glass substrate may be dried, for example, in an oven. While one example of a functionalization process is described herein, it should be understood that other functionalization processes are contemplated, provided that such processes are effective to adsorb the silane to the surface of the glass substrate. In embodiments, the glass substrate may be heated to control the surface hydroxyl concentration prior to functionalization, and/or may be heated after silane application to complete silane condensation with the hydroxyl groups on the surface of the glass substrate.

After functionalization, in step204, electroless plating is used to deposit a seed layer300of a conductive material (e.g., a copper seed layer) on the surface of the glass substrate, as depicted inFIG.3. In the embodiments described herein, the deposition of the seed layer renders the surfaces of the glass substrate electrically conductive, enabling an electroplating technique to be used to fill the vias with electrically conductive material. In particular, the seed layer300is deposited on the silane-modified surface305of the glass substrate102. In embodiments, commercially available kits and/or electroless plating solutions may be employed to deposit the seed layer300. For example, in some embodiments, the glass substrate may be dipped into a catalyst mixture, such as a Pd/Sn colloid, and then rinsed. A coating of the catalyst mixture remains on the surfaces of the glass substrate after the rinsing. The catalyst on the surfaces of the glass substrate may then be activated, such as through removal of the Sn shell from the Pd. The activation may include, for example, dipping the glass substrate into an activation solution including fluoroboric acid and boric acid. Commercially available activation solutions include those available from Uyremura. After the catalyst is activated, the glass substrate may be dipped into an electroless plating bath to form the seed layer on the surface of the glass substrate. In embodiments, the seed layer300is formed on at least the sidewalls105of each of the plurality of vias104, although it is contemplated that the seed layer300may be additionally be formed on the first surface110, the second surface112of the glass substrate102, as shown inFIG.3.

In embodiments, the glass substrate may be thermally annealed (not shown inFIG.2) after the seed layer is deposited thereon to relieve stresses in the glass substrate and thereby reduce the impact of any downstream thermal processing steps which may otherwise effect the dimensional stability of the glass substrate materials, such as electrically conductive materials, deposited on the glass substrate. In embodiments, the glass substrate may be heated to a temperature of greater than or equal to 400° C. for a time period sufficient to relieve the stresses in the glass substrate.

Returning toFIG.2, the glass substrate is wetted (step206) following deposition of the seed layer. In embodiments, the glass substrate is wetted by submerging the glass substrate including the seed layer in water to ensure that each of the vias is wetted. For example, the glass substrate may be dipped into deionized water for a period of greater than or equal to 2 minutes. In embodiments, ultrasonic energy may be applied to the glass substrate while the glass substrate is submerged in the water to enhance wetting and bubble removal. Without being bound by theory, it is believed that wetting the glass substrate prior to electroplating ensures that the vias are pre-wetted thereby preventing bubbles from being trapped within the vias, which bubbles may create voids in the conductive material subsequently filled within the vias.

After the glass substrate is wetted at step206, electroplating (step208) is carried out. In particular, an electrolyte is disposed within the plurality of vias. For example, the glass substrate may be submerged in an electrolyte solution such that the electrolyte enters the vias. The electrolyte includes ions of the electrically conductive material, for example, copper ions, to be deposited on the seed layer.

In embodiments, the electrolyte comprises ions of the electrically conductive material (e.g., copper ions) in addition to chloride ions and an additive. The chloride ions combine with the organic species in the solution to form a complex that slows down the plating rate. The chloride ions may be present in a concentration of greater than or equal to 20 ppm and less than or equal to 140 ppm in the electrolyte or greater than or equal to 20 ppm and less than or equal to 120 ppm. For example, the chloride ions may be present in a concentration of 20 ppm, 80 ppm, 100 ppm, 120 ppm, or even 140 ppm.

In embodiments, the additive is a leveler, such as nitrotetrazolium blue chloride (NTB). The leveler may enhance current density in the center of the via and help control surface morphology of the deposited electrically conductive material. In addition, the leveler may possess several physiochemical characteristics, such as a potential-dependent electrochemical desorption or breakdown and a mass-transfer controlled electrochemical adsorption. The mass-transfer controlled electrochemical adsorption may create a concentration gradient of the leveler from the opening to the center of the via during plating. Without being bound by theory, it is believed that the physiochemical characteristics of the leveler, and in particular, the NTB, enable the leveler to adsorb to the via sidewalls and suppress deposition of the electrically conductive material near the opening of the vias at a greater rate than near the center of the vias.

The additive may be present in a concentration of greater than or equal to 20 ppm and less than or equal to 60 ppm in the electrolyte. For example, the additive may be present in a concentration of 20 ppm, 40 ppm, or even 60 ppm. The electrolyte may have a ratio of chloride ions to additive of greater than or equal to 0.5 and less than or equal to 7. In some embodiments, the electrolyte is free of accelerators which form electroactive species responsible for enhanced plating rate, suppressors which combine with chloride ions to inhibit plating on areas where a reduced plating rate is desired, and additional levelers that are conventionally found in electrolyte solutions for electroplating. Such single-additive electrolytes may reduce the number of degrees of freedom and simplify optimization of the electroplating process. In other words, the use of single-additive electrolytes may result in fewer variables within the electroplating process to be modified for optimization, thereby simplifying the optimization of the electroplating process.

In some particular embodiments, the electrolyte is an electrolyte bath consisting of CuSO4, H2SO4, chloride ions, and NTB. In such embodiments, the CuSO4provides a source of copper ions, while the H2SO4makes the bath conductive and acts as a charge carrier.

Electroplating is carried out by positioning one or more electrodes within the electrolyte. In various embodiments, two electrodes, three electrodes, or more can be positioned within the electrolyte. For example, in some embodiments, three electrodes are employed. In these embodiments, the glass substrate including the seed layer is the working electrode, or cathode, and the other two electrodes are anodes. In such embodiments, the anodes may be positioned on opposite sides of the glass substrate such that plating of the electrically conductive material may be conducted symmetrically from both sides of the glass substrate. The anodes may be, by way of example and not limitation, copper plates. While a specific configuration of the electrodes is described herein, it should be understood that other configurations are contemplated and possible.

Thereafter, a current is supplied through the electrodes, the electrolyte, and the glass substrate, thereby reducing the electrically conductive ions in the electrolyte into electrically conductive material within the plurality of vias. For example, in embodiments in which the electrolyte includes copper ions, the copper ions are reduced into copper within the plurality of vias such that each of the plurality of vias is filled with copper. In embodiments, the current is applied at a current density of greater than or equal to 0.05 amps/dm2and less than or equal to 2 amps/dm2. The current density is a measure of the total current passed over a time period divided by the total surface area over which the deposition took place. In various embodiments, the total surface are is a summation of the first and second surfaces of the glass substrate and the interior surface areas of the vias. The current density, in various embodiments, is constant. However, the current density may be varied during the electroplating process. For example, in embodiments, the current may be changed in a step-wise fashion during the electroplating process.

In embodiments, the current is applied at a first current density for a first period of time and then at a second current density for a second period of time. In embodiments, the second current density is greater than the first current density. For example, the current may be applied at a current density of about 0.05 amps/dm2(ampere per square decimeter or “ASD”) for a time sufficient to generate a “butterfly” merged shape within the vias, as shown inFIG.4. In particular, as shown inFIG.4, when vias are being filled with copper, the copper tends to begin to deposit on the walls at the center of the via where it plugs at the center forming a “butterfly” or two vias. The two vias fill to complete the deposition of the through-glass vias. Without being bound by theory, the initial use of a low current density results in greater copper particle diffusion distance, enabling the copper particles to deposit and build up along the center of the via sidewall as opposed to along the entrance to the via, which can seal up the via and result in voids within the copper material, particularly when coupled with the effects of the leveler in the electrolyte, which suppresses copper deposition near the entrance to the via, as described above.

After formation of the plug, or butterfly400, the current may be applied at a second density for a second period of time to continue filling the conductive material toward the open ends of the vias. In particular, the current density may be increased following the formation of the butterfly400to fill the vias to improve throughput efficiency, since the diffusion limitation has decreased significantly. For example, the current may be applied at a current density of about 0.1 amps/dm2to about 1.6 amps/dm2for a time sufficient to fill the vias with the conductive material500, as shown inFIG.5. In some particular embodiments, the current may be applied at a current density of 0.1 amps/dm2for a period of about 5 minutes, and then at a current density of 1.6 amps/dm2until the vias are filled. It is contemplated that the current may be applied at any number of current densities to fill the vias.

In embodiments, the electroplated glass substrate may be thermally annealed (not shown inFIG.2) after the electrically conductive material is deposited thereon to relieve the stress in the glass substrate and reduce the impact of any downstream thermal processing steps. For example, the glass substrate may be heated to a temperature of greater than or equal to 400° C. for a time period sufficient to release the stresses. In various embodiments, after being filled with the electrically conductive material, the electrically conductive material in each of the plurality of vias has a void volume fraction of less than or equal to 5% or less than or equal to 1%. In particular embodiments, the electrically conductive material in each of the plurality of vias is free of voids after being filled with the electrically conductive material.

EXAMPLES

The following examples illustrate one or more features of the embodiments described herein.

Glass substrates (WILLOW™ glass available from Corning, Incorporated) having an average thickness t of 100 μm and including 20 μm or 10 μm diameter vias were cleaned using a standard cleaning process. In particular, the substrates were cleaned with 2.5 vol % of PK-LCG225X-1 detergent at 70° C. for 8 minutes in an ultrasonic bath. The substrates were then rinsed with deionized water to remove organic residues and enrich hydroxyl groups on the substrate surfaces. After cleaning, the glass substrates showed good wettability with a water contact angle of less than 5° as measured using a DSA100 from Kruss GmbH (Germany).

Next, 1 vol % of 3-(2-aminoethylamino)propyldimethoxy-methylsilane (AEA-PDMMS) diluted in ispopropanol was used to functionalize the glass surfaces. In particular, the cleaned glass substrates were submerged into the AEA-PDMMS solution with applied ultra sonic energy at 23° C. for 30 minutes. The glass substrates were then dried in an oven at 120° C. for 1 hour.

The AEA-PDMMS-modified glass substrates were then processed using a copper electroless plating kit available from Uyemura, Taiwan. Specifically, the glass substrates were dipped into a Pd/Sn colloid at room temperature for 8 minutes, then gently rinsed with deionized water. Next, the glass substrates were dipped into an activation solution at room temperature for 3 minutes to remove the Sn shell from the Pd catalyst. Finally, the glass substrates were dipped into an electroless plating bath at 35° C. for 5 minutes to form a uniform copper layer having a thickness of greater than or equal to 130 nm and less than or equal to 200 nm on the surface of the glass substrates and on the via sidewalls. The glass substrates including the seed layer were annealed by rapid thermal process (RTA) at 400° C. for 8 minutes with a 10° C./s ramping rate to release the stress.

FIG.6is a scanning electron microscope (SEM) image showing the uniform and continuous copper seed layer deposited on the sidewall of a via in the glass substrate having an aspect ratio of 10 (e.g., via diameter of 10 μm).

The glass substrates were then pre-wetted by dipping the glass substrate into DI water in an ultrasonic bath for 2 minutes. Next, the wetted glass substrates were plated in a 2 L electrolyte bath including 0.88 M CuSO4.5H2O and 0.54 M H2SO4. The electrolyte bath included 20 ppm of chloride ions and 40 ppm of nitrotetrazolium blue chloride. The glass substrates were positioned between two copper plates (anodes), and a constant current density of 0.05 amps/dm2was applied using an Auto-Lab PGSTAT 302N to plug the vias, forming the butterfly shape within the vias, as shown inFIGS.7A and7B.

FIG.7Ais an SEM image showing the plug in the shape of a butterfly within the 10 μm vias.FIG.7Bis a CT scan image further evidencing the formation of the plug within the 10 μm vias.FIG.7Cis an SEM image showing the plug in the shape of a butterfly within the 20 μm vias.FIG.7Dis a CT scan image further evidencing the formation of the plug within the 20 μm vias

Following formation of the plug within the through-glass vias, the current density was increased to 0.1 amps/dm2for 5 minutes, and then increased to 1.6 amps/dm2to completely fill the vias with the copper.FIG.8Ais an SEM image showing the complete and void-free filling of the 10 μm vias with the copper.FIG.8Bis a CT scan image further evidencing the complete and void-free filling of the 10 μm vias.FIG.8Cis an SEM image showing the complete and void-free filling of the 20 μm vias with the copper.

As a comparative example, a glass substrate (WILLOW™ glass available from Corning, Incorporated) having an average thickness t of 100 μm and including 10 μm diameter vias was cleaned, processed using the copper electroless plating kit, and pre-wetted as described for the samples above. However, following pre-wetting, the wetted glass substrate was plated at a constant current density of 0.16 amps/dm2was applied using an Auto-Lab PGSTAT 302N. The electrolyte solution was the same as described for the samples above.FIG.9A-9Cshow the results. In particular,FIG.9Ais an SEM image showing voids created within the vias as a result of the electroplating at the current density of 0.16 amps/dm2through the entirety of the process.FIGS.9B and9Care additional SEM images further evidencing the voids within the vias.

Accordingly,FIGS.6-8Bdemonstrate that the methods described herein may be used to produce a thin (<150 μm thick) glass substrate including vias at an aspect ratio of greater than 5:1 that are filled with copper such that the electrically conductive material in the filled vias have a void volume fraction of less than 5%. Specifically, the examples show that the methods may be used to produce a 100 μm thick glass substrate including vias at an aspect ratio of 12:1 that are filled with copper such that the electrically conductive material in the vias is free of voids.

It should now be understood that embodiments of the present disclosure enable through-glass vias to be formed in a thin glass substrate at an aspect ratio of greater than or equal to 5:1 and metallized such that the electrically conductive material in the filled vias has a void volume fraction of less than or equal to 5%. In particular, various embodiments enable a glass substrate including through-glass vias to be metallized without the use of a carrier. Accordingly, such processes may be used in roll-to-roll processes to fill through holes in thin, flexible glass substrates without the creation of voids.

It will be apparent to those skilled in the art that various modifications and variations can be made to the embodiments described herein without departing from the spirit and scope of the claimed subject matter. Thus it is intended that the specification cover the modifications and variations of the various embodiments described herein provided such modification and variations come within the scope of the appended claims and their equivalents.