Patent ID: 12228952

DETAILED DESCRIPTION

Electronic device10ofFIG.1may be a computing device such as a laptop computer, a desktop computer, a computer monitor containing an embedded computer, a tablet computer, a cellular telephone, a media player, or other handheld or portable electronic device, a smaller device such as a wristwatch device, a pendant device, a headphone or earpiece device, a device embedded in eyeglasses or other equipment worn on a user's head, or other wearable or miniature device, a television, a computer display that does not contain an embedded computer, a gaming device, a navigation device, an embedded system such as a system in which electronic equipment with a display is mounted in a kiosk or automobile, a wireless internet-connected voice-controlled speaker, a home entertainment device, a remote control device, a gaming controller, a peripheral user input device, a wireless base station or access point, equipment that implements the functionality of two or more of these devices, or other electronic equipment.

As shown in the functional block diagram ofFIG.1, device10may include components located on or within an electronic device housing such as housing12. Housing12, which may sometimes be referred to as a case, may be formed from plastic, glass, ceramics, fiber composites, metal (e.g., stainless steel, aluminum, metal alloys, etc.), other suitable materials, or a combination of these materials. In some embodiments, parts or all of housing12may be formed from dielectric or other low-conductivity material (e.g., glass, ceramic, plastic, sapphire, etc.). In other embodiments, housing12or at least some of the structures that make up housing12may be formed from metal elements.

Device10may include control circuitry14. Control circuitry14may include storage such as storage circuitry16. Storage circuitry16may include hard disk drive storage, nonvolatile memory (e.g., flash memory or other electrically-programmable-read-only memory configured to form a solid-state drive), volatile memory (e.g., static or dynamic random-access-memory), etc. Storage circuitry16may include storage that is integrated within device10and/or removable storage media.

Control circuitry14may include processing circuitry such as processing circuitry18. Processing circuitry18may be used to control the operation of device10. Processing circuitry18may include on one or more microprocessors, microcontrollers, digital signal processors, host processors, baseband processor integrated circuits, application specific integrated circuits, central processing units (CPUs), etc. Control circuitry14may be configured to perform operations in device10using hardware (e.g., dedicated hardware or circuitry), firmware, and/or software. Software code for performing operations in device10may be stored on storage circuitry16(e.g., storage circuitry16may include non-transitory (tangible) computer readable storage media that stores the software code). The software code may sometimes be referred to as program instructions, software, data, instructions, or code. Software code stored on storage circuitry16may be executed by processing circuitry18.

Control circuitry14may be used to run software on device10such as satellite navigation applications, internet browsing applications, voice-over-internet-protocol (VOIP) telephone call applications, email applications, media playback applications, operating system functions, etc. To support interactions with external equipment, control circuitry14may be used in implementing communications protocols. Communications protocols that may be implemented using control circuitry14include internet protocols, wireless local area network (WLAN) protocols (e.g., IEEE 802.11 protocols—sometimes referred to as Wi-Fi®), protocols for other short-range wireless communications links such as the Bluetooth® protocol or other wireless personal area network (WPAN) protocols, IEEE 802.11ad protocols (e.g., ultra-wideband protocols), cellular telephone protocols (e.g., 3G protocols, 4G (LTE) protocols, 5G protocols, etc.), antenna diversity protocols, satellite navigation system protocols (e.g., global positioning system (GPS) protocols, global navigation satellite system (GLONASS) protocols, etc.), antenna-based spatial ranging protocols (e.g., radio detection and ranging (RADAR) protocols or other desired range detection protocols for signals conveyed at millimeter and centimeter wave frequencies), or any other desired communications protocols. Each communications protocol may be associated with a corresponding radio access technology (RAT) that specifies the physical connection methodology used in implementing the protocol.

Device10may include input-output circuitry20. Input-output circuitry20may include input-output devices22. Input-output devices22may be used to allow data to be supplied to device10and to allow data to be provided from device10to external devices. Input-output devices22may include user interface devices, data port devices, and other input-output components. For example, input-output devices22may include touch sensors, displays (e.g., touch-sensitive and/or force-sensitive displays), light-emitting components such as displays without touch sensor capabilities, buttons (mechanical, capacitive, optical, etc.), scrolling wheels, touch pads, key pads, keyboards, microphones, cameras, buttons, speakers, status indicators, audio jacks and other audio port components, digital data port devices, motion sensors (accelerometers, gyroscopes, and/or compasses that detect motion), capacitance sensors, proximity sensors, magnetic sensors, force sensors (e.g., force sensors coupled to a display to detect pressure applied to the display), etc. In some configurations, keyboards, headphones, displays, pointing devices such as trackpads, mice, and joysticks, and other input-output devices may be coupled to device10using wired or wireless connections (e.g., some of input-output devices22may be peripherals that are coupled to a main processing unit or other portion of device10via a wired or wireless link).

Input-output circuitry20may include wireless circuitry24to support wireless communications. Wireless circuitry24(sometimes referred to herein as wireless communications circuitry24) may include one or more antennas. Wireless circuitry24may also include baseband processor circuitry, transceiver circuitry, amplifier circuitry, filter circuitry, switching circuitry, radio-frequency transmission lines, and/or any other circuitry for transmitting and/or receiving radio-frequency signals using the antenna(s).

Wireless circuitry24may transmit and/or receive radio-frequency signals within a corresponding frequency band at radio frequencies (sometimes referred to herein as a communications band or simply as a “band”). The frequency bands handled by wireless circuitry24may include wireless local area network (WLAN) frequency bands (e.g., Wi-Fi® (IEEE 802.11) or other WLAN communications bands) such as a 2.4 GHz WLAN band (e.g., from 2400 to 2480 MHz), a 5 GHz WLAN band (e.g., from 5180 to 5825 MHz), a Wi-Fi® 6E band (e.g., from 5925-7125 MHz), and/or other Wi-Fi® bands (e.g., from 1875-5160 MHz), wireless personal area network (WPAN) frequency bands such as the 2.4 GHz Bluetooth® band or other WPAN communications bands, cellular telephone frequency bands (e.g., bands from about 600 MHz to about 5 GHz, 3G bands, 4G LTE bands, 5G New Radio Frequency Range 1 (FR1) bands below 10 GHz, 5G New Radio Frequency Range 2 (FR2) bands between 20 and 60 GHz, etc.), other centimeter or millimeter wave frequency bands between 10-300 GHz, near-field communications frequency bands (e.g., at 13.56 MHz), satellite navigation frequency bands (e.g., a GPS band from 1565 to 1610 MHz, a Global Navigation Satellite System (GLONASS) band, a BeiDou Navigation Satellite System (BDS) band, etc.), ultra-wideband (UWB) frequency bands that operate under the IEEE 802.15.4 protocol and/or other ultra-wideband communications protocols, communications bands under the family of 3GPP wireless communications standards, communications bands under the IEEE 802. XX family of standards, and/or any other desired frequency bands of interest.

Wireless circuitry24may include transmit circuitry for transmitting or radiating signals to external devices using the antenna(s).FIG.2is a circuit diagram of illustrative transmit circuitry (sometimes referred to as a transmit path) within wireless circuitry24in accordance with an embodiment. As shown inFIG.2, the transmit circuitry may include a processor such as processor50, data converting circuits such as digital-to-analog converters (DACs)52I and54Q, filtering circuits such as filters54I and54Q, current buffering circuits such as current buffers56, mixing circuits such as mixers58I-1,58I-2,58Q-1, and58Q-2, an amplifying circuit such as amplifier60, and one or more antennas62.

Processor50may be a baseband processor, an application processor, a digital signal processor, a microcontroller, a microprocessor, a central processing unit (CPU), a programmable device, a combination of these circuits, and/or one or more processors within circuitry18. Processor50may be configured to generated digital (transmit) signals. The digital signals generated by processor50may include in-phase (I) digital signals and quadrature-phase (Q) digital signals. The in-phase signals may be fed through a first group of circuits sometimes referred to collectively as the in-phase (I) channel, whereas the quadrature-phase signals may be fed through a second group of circuits sometimes referred to as the quadrature-phase (Q) channel. The in-phase channel may include the in-phase DAC circuit52I, the in-phase filter54I, the in-phase current buffer56, and in-phase mixers58I-1and58I-2. The quadrature-phase channel may include the quadrature-phase DAC circuit52Q, the quadrature-phase filter54Q, the quadrature-phase current buffer56, and quadrature-phase mixers58Q-1and58Q-2.

Data converter52I may be configured to convert the in-phase (I) signals output from processor50from the digital domain to the analog domain to generate corresponding in-phase analog signals. Filter54I may be a low-pass filter, bandpass filter, or high-pass filter configured to pass through only a portion of the in-phase analog signals (e.g., to pass through signals in a given range(s) of frequencies while rejecting or at least partially attenuating signals outside of the given frequency range) to generate corresponding in-phase filtered signals. In-phase current buffer56may be used to provide proper output impedance termination for filter54I. In accordance with some embodiments, providing a proper termination resistance for filter54I enables filter54I to be implemented as an LC filter since LC filters typically have more stringent termination requirements. An LC filter is defined as a filter circuit having inductor (L) and capacitor (C) components. An LC filter coupled between data converter52I and current buffer56can help provide enhanced bandwidth (e.g., a bandwidth of 1 GHz or more), which enables DAC oversampling rates as low as four, eight or less, 12 or less, 16 or less, 2-4, 2-8, or other suitable ranges. If desired, filter54I may alternatively be implemented as an RC filter (i.e., a filter having resistor and capacitor components). In general, filter54I can be implemented using any combination of passive and/or active components. Device configurations in which filter54I is an LC-type filter may sometimes be described herein as an example.

In the example ofFIG.2, the circuits in the IQ channels are differential circuits (e.g., circuits having differential input ports and/or differential output ports). The in-phase current buffer56may have a first differential output port coupled to mixer58I-1and a second differential output port coupled to mixer58I-2. Mixers58I-1and58I-2may also receive local oscillator signals LOI+ and LOI− and may be configured to upconvert (modulate) the in-phase signals to radio frequencies or intermediate frequencies for later upconversion to radio frequencies. These frequencies may be 5G NR FR1 or FR2 frequencies, for example. Local oscillator signals LOI+ and LOI− may be 180 degrees phased shifted (as an example) or offset by some other phase value with respect to each other.

Similarly, data converter52Q may be configured to convert the quadrature-phase (Q) signals output from processor50from the digital domain to the analog domain to generate corresponding quadrature-phase analog signals. Filter54Q may be a low-pass filter, bandpass filter, or high-pass filter configured to pass through only a portion of the quadrature-phase analog signals to generate corresponding quadrature-phase filtered signals. Quadrature-phase current buffer56may be used to provide proper output impedance termination for filter54Q. As described above with respect to the in-phase channel, providing a proper termination resistance for filter54Q enables filter54Q to be implemented as an LC filter since LC filters typically have more stringent termination requirements. An LC filter coupled between data converter52Q and quadrature-phase current buffer56can help minimize amplitude modulation to phase modulation (AMPM) distortion while providing enhanced bandwidth (e.g., a bandwidth of 1 GHz or more), which enables DAC oversampling rates as low as four, eight or less, 12 or less, 16 or less, 2-4, 2-8, or other suitable ranges. If desired, filter54Q may alternatively be implemented as an RC filter or using any combination of passive and/or active components. Device configurations in which filter54Q is an LC-type filter may sometimes be described herein as an example.

The quadrature-phase current buffer56may have a first differential output port coupled to mixer58Q-1and a second differential output port coupled to mixer58Q-2. Mixers58Q-1and58Q-2may also receive local oscillator signals LOI+ and LOI− and may be configured to upconvert (modulate) the quadrature-phase signals to radio frequencies or intermediate frequencies for later up-conversion to radio frequencies (e.g., 5G NR FR1 or FR2 frequencies). Local oscillator signals LOI+ and LOI− may be 180 degrees phased shifted (as an example) or offset by some other phase value with respect to each other.

The mixers of the IQ channels may output the upconverted signals to amplifier60. Amplifier60(sometimes referred to as a power amplifier, radio-frequency power amplifier, or transmit amplifier) may be configured to amplify the upconverted signals for transmission by one or more corresponding antennas62in the transmit path without changing the signal shape, format, or modulation. Amplifier60may, for example, be used to provide 10 dB of gain, 20 dB of gain, 10-20 dB of gain, less than 20 dB of gain, more than 20 dB of gain, or other suitable amounts of gain. If desired, additional circuit components (e.g., additional filters, multiplexing circuitry, switching circuitry, coupling circuitry, impedance matching circuitry, tuning circuitry, etc.) may be disposed between the mixers and amplifier60and/or between amplifier60and antenna62.

Antenna62may be formed using any desired antenna structures. For example, antenna62may include antennas with resonating elements that are formed from loop antenna structures, patch antenna structures, inverted-F antenna structures, slot antenna structures, planar inverted-F antenna structures, helical antenna structures, monopole antennas, dipoles, hybrids of these designs, etc. Filter circuitry, switching circuitry, impedance matching circuitry, and/or other antenna tuning components may be adjusted to adjust the frequency response and wireless performance of the antennas over time.

The radio-frequency signals handled by antennas62may be used to convey wireless communications data between device10and external wireless communications equipment (e.g., one or more other devices such as device10). Wireless communications data may be conveyed by wireless circuitry24bidirectionally or unidirectionally. The wireless communications data may, for example, include data that has been encoded into corresponding data packets such as wireless data associated with a telephone call, streaming media content, internet browsing, wireless data associated with software applications running on device10, email messages, etc.

FIG.3is a circuit diagram of an illustrative filter circuit54in accordance with some embodiments. Filter54may represent one suitable implementation of the in-phase filter circuit54I and the quadrature-phase filter circuit54Q ofFIG.2. As shown inFIG.3, filter54may be a differential LC filter circuit. Differential LC filter54may include inductors L1and L2and capacitors C1, C2, C3, and C4. Inductor L1has a first (dotted) terminal coupled to a first differential input port of filter54and has a second terminal coupled to a first differential output port of filter54. Inductor L2has a first terminal coupled to a second differential input port of filter54and has a second (dotted) terminal coupled to a second differential output port of filter54.

Capacitor C1may be coupled across the two differential input ports of filter54and may sometimes be referred to as an input capacitor. The differential input ports of filter54may be configured to receive analog signals from a DAC circuit (e.g., DAC52I or52Q). Capacitor C2may be coupled across the two differential output ports of filter54and may be defined as an output capacitor. The differential output ports of filter54may be coupled to a corresponding current buffer circuit (e.g., current buffer56). Capacitor C3has a first terminal coupled to the first differential input port of filter54and has a second terminal coupled to the first differential output port of filter54(e.g., capacitor C3may be coupled in parallel with inductor L1).

Capacitor C4has a first terminal coupled to the second differential input port of filter54and has a second terminal coupled to the second differential output port of filter54(e.g., capacitor C4may be coupled in parallel with inductor L2). In some embodiments, capacitors C1, C2, C3, and/or C4may have adjustable capacitance. If desired, filter54may include additional passive (e.g., inductive, capacitive, resistive) and/or active components (e.g., transistors).

As described above in connection withFIG.2, current buffer56can help provide proper impedance termination for LC filter54. In accordance with an embodiment, current buffer56may be implemented as a current mirror circuit (sometimes referred to as a current mirror). An ideal current mirror should exhibit perfect nonlinearity cancellation as the non-linear current of the output current branch would be canceled out by the non-linear current associated with the input current branch. In such scenario, the input resistance of the current mirror can be arbitrarily non-linear while the ratio of the output current to the input current remains perfectly linear.

In practice, however, this cancellation is disrupted if the current mirror sees a finite impedance at its input. In the example ofFIG.2, current buffer56(e.g., a current mirror circuit) may see a finite impedance Zs looking towards the LC filter and the digital-to-analog converter.FIG.4is a diagram plotting impedance Zs as a function of frequency. Curve70represents the magnitude of Zs. As shown inFIG.4, curve70can have a zero at frequency ωz(which causes the impedance to rise) and a pole at frequency ωp(which causes impedance to fall), where ωzis less than ωp. If care is not taken, the zero at ωzcan result in a noise overshoot and linearity degradation for current buffer56in or near the frequency band of interest. To mitigate this effect, it may be desirable to linearize the input resistance Rin of current buffer56.

FIG.5is a circuit diagram of an illustrative current buffer56implemented using differential current mirror circuits. The current buffer56ofFIG.5may represent current buffer56that is part of the in-phase channel and/or the quadrature-phase channel inFIG.2. As shown inFIG.5, current buffer56may include a first current mirror circuit80-1and a second current mirror circuit80-2. Current buffer56having multiple current mirrors is therefore sometimes referred to as current mirror circuitry. Current mirror80-1may include n-type transistors N1and N2(e.g., n-channel metal-oxide-semiconductor or NMOS switches) and p-type transistors P1and P2(e.g., p-channel metal-oxide-semiconductor or PMOS switches).

Transistor N1may have a source terminal coupled to a ground power supply line84, a gate terminal, and a drain terminal that is shorted to its gate terminal and that is coupled to a first differential input port of current buffer56. The first differential input port of current buffer56may be coupled to an LC filter (e.g., coupled to an output of filter54shown inFIG.3). Ground power supply line84is sometimes referred to as a ground line or ground. The terms “source” and “drain” are sometimes used interchangeably when referring to current-conducting terminals of a metal-oxide-semiconductor transistor. The source and drain terminals are therefore sometimes referred to as “source-drain” terminals (e.g., a transistor has a gate terminal, a first source-drain terminal, and a second source-drain terminal). A transistor having its drain and gate terminals shorted is sometimes referred to as a diode-connected transistor. Transistor N1is therefore a diode-connected n-type transistor within current mirror80-1.

Transistor N2may have a source terminal coupled to ground power supply line84, a gate terminal coupled to the gate terminal of transistor N1, and a drain terminal coupled to a first differential output port of current buffer56. The first differential output port of current buffer56may be coupled to a mixer (e.g., coupled to an input of one the mixers shown inFIG.2). Transistor P2may have a drain terminal coupled to the first differential output port of current buffer56, a gate terminal, and a source terminal coupled to a high voltage line82(e.g., a voltage line on which a regulated voltage Vreg can be provided). Voltage line82may sometimes be referred to as the supply voltage line for current buffer56. Transistor P1may have a source terminal coupled to high voltage line82, a gate terminal coupled to the gate terminal of transistor P2, and a drain terminal that is shorted to its gate terminal and that is coupled to the first different input port of current buffer56. Transistor P1is therefore a diode-connected p-type transistor within current mirror80-1. Transistor P2may be sized M times larger than transistor P1. Similarly, transistor N2may be sized M times larger than transistor N1. Configured in this way, the current flowing through transistors P2and N2(sometimes referred to as the output current branch) may be M times larger than the current flowing through transistor P1and N1(sometimes referred to as the input current branch). The value M may be equal to 1, 2, 3, 4, 5, 1-10, 10-20, more than 20, or any suitable integer or number greater than one.

Similarly, current mirror80-2may also include n-type transistors N1and N2(e.g., re-channel metal-oxide-semiconductor or NMOS switches) and p-type transistors P1and P2(e.g., p-channel metal-oxide-semiconductor or PMOS switches). Transistor N1in current mirror80-2may have a source terminal coupled to ground power supply line84, a gate terminal, and a drain terminal that is shorted to its gate terminal and that is coupled to a second differential input port of current buffer56. The second differential input port of current buffer56may be coupled to an LC filter (e.g., coupled to an output of filter54shown inFIG.3). Transistor N1is therefore a diode-connected n-type transistor within current mirror80-2.

Transistor N2in current mirror80-2may have a source terminal coupled to ground power supply line84, a gate terminal coupled to the gate terminal of transistor N1, and a drain terminal coupled to a second differential output port of current buffer56. The second differential output port of current buffer56may be coupled to a mixer (e.g., coupled to an input of another one the mixers shown inFIG.2). Transistor P2in current mirror80-2may have a drain terminal coupled to the second differential output port of current buffer56, a gate terminal, and a source terminal coupled to voltage line82. Transistor P1in current mirror80-2may have a source terminal coupled to high voltage line82, a gate terminal coupled to the gate terminal of transistor P2in current mirror80-2, and a drain terminal that is shorted to its gate terminal and that is coupled to the second different input port of current buffer56. Transistor P1is therefore a diode-connected p-type transistor within current mirror80-2. Within current mirror80-2, transistor P2may be sized M times larger than transistor P1. Similarly, transistor N2may be sized M times larger than transistor N1within current mirror80-2. Configured in this way, the current mirrored onto the output current branch can be M times that of the current in the input current branch.

Forming current mirrors using both diode-connected n-type and diode-connected p-type transistors in this way at the input of current buffer56can provide a mild push-pull behavior (e.g., to mimic a class AB amplifier behavior), which can help provide a more linear input resistance Rin and a more linear output current for buffer56. A current mirror circuit having both diode-connected n-type transistor N1and diode-connected p-type transistor P1is sometimes referred to herein as a complementary current mirror. Any additional parasitic capacitance due to the complementary diode connection at the differential input port of current buffer56can be absorbed into the LC filter without adversely affecting the overall performance of the transmit path.

A capacitor86may be coupled to voltage line82. Capacitor86may have a first terminal coupled to voltage line82and a second terminal coupled to ground line84. A regulated voltage Vreg may be provided on voltage line82using, for example, a voltage regulating circuit such as voltage regulator88. This is merely illustrative. If desired, a positive power supply voltage (e.g., voltage Vdd) greater than or less than the regulated voltage Vreg may be provided on high voltage line82.

FIG.6is a circuit diagram of an illustrative voltage regulator88. As shown inFIG.6, voltage regulator88may include an operational amplifier94, a resistor98, capacitors96and100, current sources102and104, and transistors92, N3, and P3. Transistor92(e.g., an n-type transistor) may have a drain terminal coupled to a positive power supply line (e.g., a power supply line on which a positive power supply voltage Vdd is provided), a gate terminal, and a source terminal on which voltage Vreg is provided. Operational amplifier94may have an output terminal coupled to the gate of transistor92, a first (positive) input terminal, and a second (negative) input terminal that is coupled to the source terminal of transistor92. Capacitor96may have a first terminal coupled to the first (+) terminal of operational amplifier94and a second terminal coupled to ground line84. Resistor98may have a first terminal coupled to the first (+) terminal of operational amplifier94and a second terminal. Capacitor100may have a first terminal coupled to the second terminal of resistor98and a second terminal coupled to the ground line.

Current source102may be coupled between positive power supply line90and the second terminal of resistor98. Transistor P3(e.g., a p-type transistor) may have a source terminal coupled to the second terminal of resistor98, a gate terminal, and a drain terminal that is shorted to its gate terminal to form a diode-connected p-type transistor. Transistor N3(e.g., an n-type transistor) may have a drain terminal coupled to the drain terminal of transistor P3, a source terminal coupled to ground line84, and a gate terminal that is shorted to its gate terminal to form a diode-connected n-type transistor. Current source104may be coupled between positive power supply line90and the node disposed between transistors P3and N3. Similar to transistors N1and P1in the current mirrors of buffer56, transistors P3and N3within regulator88are also both in the diode-connected configuration and may therefore sometimes be referred to as “replica” biasing circuit. In one embodiment, transistors P3and N3may be smaller than transistors P1and N1(e.g., transistor P3and N3may be scaled down versions of transistors P1and N1). In another embodiment, transistors P3and N3may be the same size as transistors P1and N1. In yet another embodiment, transistors P3and N3may be larger than transistors P1and1(e.g., transistor P3and N3may be sized up versions of transistors P1and N1).

Configured in this way, voltage regulator88can exhibit a low impedance at its output, where a stable voltage Vreg can be provided. Current sources102and104can be proportional-to-absolute-temperature (PTAT) current sources, complementary-to-absolute-temperature (CTAT) current sources, or a combination of PTAT and CTAT current sources, which can be used within voltage regulator88to ensure that voltage Vreg is insensitive to temperature changes. PTAT and CTAT current sources are sometimes referred to herein as temperature-dependent current sources. Voltage regulator88of the type shown inFIG.6is sometimes referred to as a low dropout (LDO) voltage regulator. This is merely illustrative. If desired, other types of voltage regulators or supply regulating circuit can be coupled to current buffer56. The use of voltage regulator88ofFIG.6can help ensure that current buffer input resistance Rin is kept constant across process, voltage, temperature, and frequency (PVTF) variations and for a wide range of the full scale current of the corresponding DAC (e.g., DAC52I or52Q).

Current buffer56of the type shown inFIG.5may have a certain input common voltage Vcm_in. In practice, the associated DAC circuit coupled to the input port of current buffer56via the LC filter can only tolerate a certain range of the current buffer input common mode voltage Vcm_in. The input common mode voltage Vcm_in of current buffer56ofFIG.5may be equal to the gate-to-source voltage across transistor N1. The gate-to-source voltage across transistor N1is set by the input resistance Rin and the linearity of current buffer56. Such relationship between the input common mode voltage Vcm_in and the input resistance Rin of current buffer56can make it difficult to design the DAC, filter, and/or the current buffer in the transmit path.

FIG.7illustrates another example of a current mirror80′ that can be used within current buffer56. For example, current mirrors80-1and80-2ofFIG.5can be implemented using current mirror80′ of the type shown inFIG.7. As shown inFIG.7, current mirror80′ may include n-type transistors N1and N2, p-type transistors P1and P2, a current source Ib, a resistor Rb, and a capacitor Cx. Transistor N1may have a source terminal coupled to ground power supply line84, a gate terminal, and a drain terminal that is coupled to its gate terminal via resistor Rb and that is coupled to a differential input port of current buffer56. Transistor N2may have a source terminal coupled to ground power supply line84, a gate terminal coupled to the gate terminal of transistor N1, and a drain terminal coupled to a differential output port of current buffer56. Transistor P2may have a drain terminal coupled to the differential output port of current buffer56, a gate terminal, and a source terminal coupled to high voltage line82(sometimes referred to as a regulated voltage line). Transistor P1may have a source terminal coupled to voltage line82, a gate terminal coupled to the gate terminal of transistor P2, and a drain terminal that is coupled to its gate terminal via capacitor Cx and that is coupled to the different input port of current buffer56. As an example, transistor P2may be sized M times larger than transistor P1. Similarly, transistor N2may be sized M times larger than transistor N1. The value M may be equal to 1, 2, 3, 4, 5, 1-10, 10-20, more than 20, or any suitable integer or number greater than one. Current source Ib may be coupled between voltage line82and the gate terminals of transistors P1and P2so that current Ib flows down through resistor Rb as indicated by current path110.

The use of resistor Rb disposed between the drain and gate terminals of transistor N1can decouple input common mode voltage Vcm_in from the gate-to-source voltage Vgsn of transistor N1. Configured as such, the current mirror input common mode voltage Vcm_in will be equal to the difference between transistor N1's gate-to-source voltage Vgsn and the voltage drop across resistor Rb (i.e., Vcm_in=Vgsn−Ib*Rb). Decoupling Vcm_in from Vgsn in this way can help make it easier to design the DAC, filter, and/or the current buffer in the transmit path. The addition of resistor Rb might lead to an inductive behavior in the input impedance of current mirror80′. The use of capacitor Cx, which is coupled in parallel with resistor Rb, can help mitigate or cancel out this inductive behavior. Canceling out this inductive component can help ensure that there is minimal lag between the drain and gate terminals of transistor N1. Capacitor Cx should be sized much larger than the parasitic capacitance associated with resistor Rb (e.g., capacitor Cx may be at least 10 times, 10-100 times, more than 100 times, or more than 1000 times larger than the parasitic capacitance of resistor Rb).

The linearity of current buffer56can be adversely affected by intermodulation distortion terms that are sometimes present on voltage line82. Intermodulation distortion arises when at least two signals of different frequencies are applied to a non-linear circuit and when the amplitude modulation or mixing (multiplication) of the two signals when their sum is raised to a power greater than one generates intermodulation products that are not just at harmonic frequencies (integer multiples) of either input signal but also at the sum and differences of the input signal frequencies and also at sums and differences of multiples of those frequencies.

The embodiment ofFIG.8illustrates using an envelope detector and a frequency-dependent current mirror to inject a second order intermodulation (IM2) term onto voltage line82to cancel or mitigate any unwanted 2nd order intermodulation distortion (IMD2), which can also help reduce any third order intermodulation distortion (IMD3). As shown inFIG.8, current buffer56may include current mirror80-1, current mirror80-2, envelope detector120, and frequency-dependent current mirror122. The structure and operation of current mirrors80-1and80-2shown inFIG.8are identical to that already described above in connection withFIG.5and need not be reiterated in detail in order to avoid obscuring the current embodiment. If desired, current mirrors80-1and80-2may alternatively be implemented using current mirror80′ ofFIG.7.

Envelope detector may include transistors124and126(e.g., n-type transistors). Transistor124may have a source terminal coupled to ground line84, a gate terminal shorted to the gate terminal of transistor N1in current mirror80-1, and a drain terminal. Transistor126may have a source terminal coupled to ground line84, a gate terminal shorted to the gate terminal of transistor N1in current mirror80-2, and a drain terminal coupled to the drain terminal of transistor124. Configured in this way, envelope detector120can be used to sense the input common mode voltage of the two current mirrors and can generate an IM2 signal (sometimes referred to as an IM2 term or IM2 component).

Current mirror122may include a first p-type transistor128, a second p-type transistor130, a resistor132, capacitors134and136, and a current sink140. Transistor128may have a drain terminal coupled to the drain terminals of transistors124and126, a source terminal coupled to a bias voltage line138(e.g., a voltage line on which bias voltage Vbias is provided), and a gate terminal. Voltage Vbias can be less than Vreg, equal to Vreg, greater than Vreg, or equal to positive power supply voltage Vdd. Resistor132may be coupled across the gate and drain terminals of transistor128. Capacitor134may be coupled across the gate and source terminals of transistor128. Transistor130may have a source terminal coupled to bias voltage line138, a gate terminal coupled to the drain terminal of transistor128, and a drain terminal coupled to current sink140. Capacitor136may be coupled across the gate and source terminals of transistor130. The drain terminal of transistor130may also be coupled to high voltage line82via path131.

The current flowing through transistor128down into the drain terminals of transistor124and126(sometimes referred to collectively as the tail node) is labeled input current Iin. The current flowing through transistor130is labeled as output current Iout. The input current Iin may be mirrored to the output current Iout by some predetermined mirroring factor.FIG.9is a diagram showing the current frequency response of current mirror122ofFIG.8. As shown inFIG.9, line150plots the magnitude of the ratio of Iout to Iin as a function of frequency. Line150may be at a first magnitude A for frequencies less than ω1, ramp up from magnitude A to a second greater magnitude B from frequency ω1to ω2, and then start ramping down for frequencies greater than ω3. Current mirror122having this type of frequency response with an elevated magnitude B for a given frequency range of interest (e.g., from ω2to ω3) can help increase the gain of the IM2 signal generated by envelope detector120and is therefore sometimes referred to as a frequency-dependent current mirror. Configured and operated in this way, an amplified IM2 signal may be generated on path131to cancel unwanted IM2 terms on voltage line82. Envelope detector120and frequency-dependent current mirror122may therefore sometimes be referred to collectively as a second order intermodulation (IM2) injection circuit, IM2 cancellation circuit, or 2nd order intermodulation distortion (IMD2) reduction circuit.

The embodiments of the current buffer shown inFIGS.5and8having current mirrors with complementary (n-type and p-type) diode-connected input transistors are merely illustrative.FIG.10is a circuit diagram of illustrative current buffer56″ that employs resistors to set the differential input resistance of the current buffer. As shown inFIG.10, current buffer56″ may include inverters160-1,160-2,162-1, and162-2and resistors R1and R2. For example, each of these inverters may include a p-type transistor connected in series with an n-type transistor, where the gate terminals of the p-type and n-type transistors are shorted together. If desired, other types of inverters or inverting circuits may be used. Resistors R1and R2may be poly resistors (e.g., resistors formed from doped polysilicon or some other gate material), diffusion resistors (e.g., resistors formed from n-type or p-type diffusion regions in a semiconductor substrate), well resistors (e.g., resistors formed from n-wells or p-wells in a semiconductor substrate), metal resistors, transistors with high resistivity, or other types of resistive components.

Inverter160-1may have an input that is coupled to a first differential input port of current buffer56″ and an output. Inverter162-1may have an input coupled to the input of inverter160-1and an output that is coupled to a first differential output port of current buffer56″. Inverter160-2may have an input that is coupled to a second differential input port of current buffer56″ and an output. Inverter162-2may have an input coupled to the input of inverter160-2and an output that is coupled to a second differential output port of current buffer56″. The first and second differential input ports of current buffer56″ may be coupled to an LC filter (e.g., coupled to an output of filter54shown inFIG.3). The first and second differential output ports of current buffer56″ may be coupled to a mixer (e.g., coupled to an input of one the mixers shown inFIG.2).

Resistor R1has a first terminal coupled to the input of inverter160-1and a second terminal coupled to the output of inverter160-1. Resistor R2has a first terminal coupled to the input of inverter160-2and a second terminal coupled to the output of inverter160-2. Configured as such, resistors R1and R2set the differential input resistance of current buffer56″. The differential input resistance of the current buffer provided in this way can be sufficiently linear. Inverters160-1and160-2set the biasing point of these inverters and the common-mode resistance seen by the LC filter. Since the outputs of inverters160-1and160-2are shorted together, the noise of the two inverters160-1and160-2is common mode and would thus canceled out with each other. Inverters160-1and160-2may have the same size. Inverters162-1and162-2may also have identical sizes. Inverters160-1and160-2can be sized relatively small to minimize power consumption, whereas inverters162-1and162-2can be sized relatively large to provide greater current drive-ability for current buffer56″ (e.g., inverters162-1and162-2can be larger than inverters160-1and160-2).

Referring back toFIG.2, any mismatch in the input resistance Rin of the current buffers56in I and Q channels can result in IQ mismatch (IQMM), which degrades the error vector magnitude (EVM) of wireless circuitry24. To help alleviate the effect of the Rin mismatch or any other differences between the I and Q channels (broadly referred to as IQ mismatch), components within filters54I and54Q can be intentionally adjusted to different values to mitigate any undesired IQMM.

FIG.11Ais a circuit diagram of a differential LC filter54I associated with the in-phase (I) channel. As shown inFIG.11A, filter54I may include inductors L1and L2and adjustable capacitors C1, C2-I, C3, and C4. Inductor L1has a first (dotted) terminal coupled to a first differential input port of filter54I and has a second terminal coupled to a first differential output port of filter54I. Inductor L2has a first terminal coupled to a second differential input port of filter54I and has a second (dotted) terminal coupled to a second differential output port of filter54I. Inductors L1and L2may have the same inductance value (as an example). Capacitor C3may be coupled in parallel with inductor L1within filter54I. Capacitor C4may be coupled in parallel with inductor L2within filter54I. Capacitor C1may be coupled across the two differential input ports of filter54I. Capacitor C2-I may be coupled across the two differential output ports of filter54I. The differential output ports of filter54I may see an I-channel input resistance Rini looking towards the corresponding current buffer.

FIG.11Bis a circuit diagram of a differential LC filter54Q associated with the quadrature-phase (Q) channel. As shown inFIG.11B, filter54Q may include inductors L1and L2and adjustable capacitors C1, C2-Q, C3, and C4. Inductor L1has a first (dotted) terminal coupled to a first differential input port of filter54Q and has a second terminal coupled to a first differential output port of filter54Q. Inductor L2has a first terminal coupled to a second differential input port of filter54Q and has a second (dotted) terminal coupled to a second differential output port of filter54Q. Capacitor C3may be coupled in parallel with inductor L1within filter54Q. Capacitor C4may be coupled in parallel with inductor L2within filter54Q. Capacitor C1may be coupled across the two differential input ports of filter54Q. Capacitor C2-Q may be coupled across the two differential output ports of filter54Q. The differential output ports of filter54Q may see a Q-channel input resistance Rin_Q looking towards the corresponding current buffer.

In accordance with an embodiment, capacitor C2-I in filter54I and capacitor C2-Q in filter54Q can be deliberately set (adjusted) to different capacitance values to reduce or mitigate the IQMM, which can improve the EVM of the overall wireless circuitry. The capacitance of C2-I and C2-Q could be different or could be the same. The IQMM may be a frequency dependent metric (e.g., a value that varies as a function of frequency). The difference in capacitance values of the filter output capacitors can be expressed as follows:

Δ⁢C2(%)=-Δ⁢R⁡(%)1+Δ⁢R⁡(%)⁢(1-C1C2*1ω02⁢L1,2⁢C1-1)(1)
where ΔC2represents the percentage capacitance difference between C2-I and C2-Q, where ΔR represents the percentage resistance difference between Rin_I and Rin_Q, and where ω0represents a notch frequency in the frequency dependent IQMM(f).

FIG.12is a diagram plotting the image rejection ratio (IMRR) as a function of frequency for an LC filter of the type shown inFIGS.11A and11B. Curve170may represent a first IMRR profile for an uncompensated filter scenario (e.g., ΔC2=0), curve172may represent a second IMRR profile for a compensated filter scenario where ΔC2has a first non-zero value, and curve174may represent a third IMRR profile for another compensated filter scenario where ΔC2has a second non-zero value that is different than the first non-zero value. As shown inFIG.12, curve172may have a notch at frequency ω1, whereas curve174has a notch at another frequency ω2. This shows how the value of ΔC2can be adjusted to shift the notch frequency in IQMM(f) across a given frequency band of interest (i.e., the notch frequency ω0can be tailored to provide the best overall frequency dependent IQMM). If desired, the IMRR can be measured for different ΔC2values in the factory or in the field, and the desired capacitance difference ΔC2can be chosen to optimize the image rejection. The example ofFIGS.11and12where different capacitance values within the LC filters are used to mitigate Rin mismatch between the I and Q channels is merely illustrative. In general, different C1values, different C2values, different C3values, different C4values, different L1values, different L2values, and/or some combination of these may be used to compensate for any undesirable mismatch between the I and Q channels.

The methods and operations described above in connection withFIGS.1-12may be performed by the components of device10using software, firmware, and/or hardware (e.g., dedicated circuitry or hardware). Software code for performing these operations may be stored on non-transitory computer readable storage media (e.g., tangible computer readable storage media) stored on one or more of the components of device10(e.g., storage circuitry16ofFIG.1). The software code may sometimes be referred to as software, data, instructions, program instructions, or code. The non-transitory computer readable storage media may include drives, non-volatile memory such as non-volatile random-access memory (NVRAM), removable flash drives or other removable media, other types of random-access memory, etc. Software stored on the non-transitory computer readable storage media may be executed by processing circuitry on one or more of the components of device10(e.g., processing circuitry18ofFIG.1, etc.). The processing circuitry may include microprocessors, central processing units (CPUs), application-specific integrated circuits with processing circuitry, or other processing circuitry.

The foregoing is merely illustrative and various modifications can be made to the described embodiments. The foregoing embodiments may be implemented individually or in any combination.