Patent ID: 12230701

DETAILED DESCRIPTION

Embodiments of the present inventive concepts are described more fully hereinafter with reference to the accompanying drawings, in which embodiments of the invention are shown. This inventive concepts may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the inventive concepts to those skilled in the art. Like numbers refer to like elements throughout.

Embodiments of the inventive concepts provide multi-cell transistor devices with large effective gate widths. By feeding the gate signal to the gate fingers at multiple locations along the width of the gate finger, the high frequency gain performance of the transistor may be improved, and electromigration concerns that are normally associated with wide gate fingers can be reduced. According to some embodiments, a larger gate width of a multi-cell transistor device can be accommodated by adding a second layer of metal over the source regions of a unit cell to act as a gate jumper. The gate jumper is connected to the gate finger at various locations along the gate finger, effectively dividing the gate finger into multiple segments. The gate jumper may be provided by a second layer of metal that extends over and above the source contact that connects the gate pad to the gate segments. In some embodiments, the gate jumper could extend over and above the drain contact or the gate finger instead of over and above the source contact.

By effectively dividing the gate finger into segments and distributing the gate signal to each of the gate finger segments by means of a gate jumper, the gain performance of the transistor may be improved and electromigration concerns can be alleviated.

Thus, embodiments of the inventive concepts provide transistor layouts that define multiple unit cells in series for each gate finger. Individually, each of the unit cells has a shorter effective gate width. However, when connected in series, the unit cells can increase the effective length of a single gate finger. The gate fingers of the series-connected unit cells are connected to a gate bus by means of a second metal bridge that runs over the source contacts of the unit cells. The metal bridge is connected between the source contacts to connecting bars that run along the surface of the substrate between the source contacts and connect to the gate finger.

A transistor having a layout as described herein may have higher frequency performance and higher output power while at the same time having a reduced current density, which can improve device reliability.

Pursuant to further embodiments of the present invention, multi-cell transistors with large effective gate widths are provided in which a plurality of series gate resistors (which are also referred to as “gate resistors” herein) are distributed throughout the device. For example, the transistors may have segmented gate fingers, and a series gate resistor may be provided for each gate finger segment or for pairs of gate finger segments. This approach breaks up long feedback loops within the gate fingers and drains of the transistor structure by making the feedback loops lossy enough to avoid high levels of instability. The distributed series gate resistors may be positioned, for example, in the gap regions that are provided between the gate finger segments of the gate fingers.

Thus, in some embodiments, transistors are provided that include a drain contact extending along a first axis, a source contact extending along a second axis that is parallel to the first axis, and a gate finger extending between the source contact and the drain contact. The gate finger may comprise a plurality of physically discontinuous, collinear gate finger segments that are electrically connected to each other by one or more other structures (e.g., a gate jumper). The transistor further includes a plurality of spaced-apart gate resistors that are electrically connected to the gate finger. At least one of the gate resistors is disposed in a portion of the region between the first axis and the second axis that is between a first end and a second end of the gate finger when the transistor is viewed from above. In some embodiments, a gate jumper may be electrically connected to the gate finger, and the gate jumper may be electrically connected to a gate bus. The gate jumper may be interposed along an electrical path between a first of the gate finger segments and the gate bus, and a first of the gate resistors may be interposed along an electrical path between the gate jumper and the first of the gate finger segments.

In other embodiments, transistors are provided that include a source contact extending in a first direction, a gate jumper extending in the first direction, and a gate finger that comprises a plurality of discontinuous gate finger segments that extend in the first direction. The transistor further includes a plurality of spaced-apart gate resistors, each of which is electrically connected to the gate jumper. A first of the gate finger segments is connected to the gate jumper through a first of the gate resistors.

Pursuant to still further embodiments of the present invention, multi-cell transistors with large effective gate widths are provided in which a plurality of odd mode resistors are distributed throughout the device. In an example embodiment, odd mode resistors may be provided in the gap regions that are formed between the “gate splits,” where a gate split refers to the regions where a plurality of gate finger segments extend in parallel to each other. The odd mode resistors may be distributed throughout these gap regions to further improve the stability of the transistor. The above described gate resistors may also be located in these gap regions.

Thus, in additional embodiments, transistors are provided that include a plurality of gate fingers that extend in a first direction and that are spaced apart from each other in a second direction that is perpendicular to the first direction, each of the gate fingers comprising at least spaced-apart and generally collinear first and second gate finger segments that are electrically connected to each other, where the first gate finger segments are separated from the second gate finger segments in the first direction by a gap region that extends in the second direction. At least one resistor is disposed in the gap region. The at least one resistor may be an odd mode resistor and/or a series gate resistor.

The transistors according to embodiments of the inventive concepts may have large effective gate widths, support increased power density levels and exhibit improved frequency response as compared to conventional transistors. Additionally, the gate series resistors and odd mode resistors, if provided, may help prevent feedback loops that may generate unwanted signals at frequencies that are low enough to be close to or within the operating frequency range of the transistor. Accordingly, the transistors may also exhibit increased stability and hence may have improved production yields and/or better reliability.

It will be appreciated that the above-described embodiments may be combined in any fashion. For example, transistors may be provided that include both distributed gate resistors and distributed odd mode resistors. Likewise, transistors having non-segmented gate fingers may include either or both distributed gate resistors and distributed odd mode resistors.

Embodiments of the present invention will now be described in greater detail with reference toFIGS.2-15.

FIG.2is a plan view of a metal layout of a transistor100in accordance with some embodiments. The transistor is formed on a semiconductor structure120that includes one or more device epitaxial layers which are described in greater detail below. The layout ofFIG.2is simplified for ease of understanding and includes a gate pad112that is connected to a gate bus114and a drain pad132that is connected to a drain bus134. The source pad and source bus are omitted fromFIG.2for clarity of illustration, but are illustrated inFIGS.5and6.

A plurality of gate fingers116are connected to the gate bus114and extend in the y-direction. Likewise, a plurality of drain contacts136are connected to the drain bus134and extend in parallel with and adjacent to respective ones of the gate fingers116. Although only four gate fingers116and three drain contacts136are illustrated inFIG.2, it will be appreciated that the transistor100may have many more gate fingers116and drain contacts136so that the transistor has a large number of unit cells.

Source contacts162are also provided and extend in the y-direction in parallel with adjacent ones of the gate fingers116. The source contacts162are divided in the y-direction into respective source contact segments162a,162band162c. The source contact segments may be connected by means of source contact bars128(FIG.6) that extend laterally across the device structure (in the x-direction). The source contact segments162a,162b,162cmay be connected by other means. For example source contact plugs may be provided that electrically connect each source contact segment162a,162b,162cto a common conductive layer located, for example, in a lower level of the device.

Adjacent ones of the source contact segments162a-162care separated by gaps162g. AlthoughFIG.2illustrates three source contact segments162a-162cfor each source contact162, the inventive concepts are not limited to such a configuration, and it will be appreciated that the source contact162may include two or more source contact segments162a-162c.

The gate fingers116may extend in parallel with the source contacts162for the entire length of the source contacts162. However, because the source contacts162are divided into source contact segments162a-162c, the source contact segments162a,162band162cdefine a plurality of series unit cells40a,40b,40cfor each of the gate fingers116. That is, each gate finger116acts as a gate contact for a plurality of unit cells40a,40b,40cthat are laid out in the direction (y-direction) along which the gate fingers116extend and that defines the width of the gate fingers116. Thus, the total width contributed to the gate periphery of the overall device by each gate finger116is equal to the distance by which the gate finger116overlaps the adjacent source contact segments162a,162band162cin the y-direction.

The transistor100further includes a plurality of gate jumpers172that extend along the y-direction in parallel with the gate fingers116. The gate jumpers172may be formed over the source contacts162, and may be insulated from the source contacts162by, for example, a dielectric layer and/or an air gap. The gate jumpers172are electrically connected to the gate bus114, and connect each gate finger116to the gate bus114at multiple locations along the gate finger116.

In particular, the gate jumpers172connect to the gate fingers116through gate signal distribution bars174that are provided at multiple locations along the width of the device and that extend laterally (in the x-direction) within the gaps162gbetween adjacent ones of the source contact segments162a,162band162c. The gate signal distribution bars174contact the gate fingers116at respective gate signal distribution points176. Thus, an electrical signal applied to the gate pad112(a “gate signal”) is carried to the gate bus114, and then to the gate jumpers172, which distribute the gate signal to the gate fingers116at multiple locations (the gate signal distribution points176) along the width of the gate fingers116. Thus, in the embodiment ofFIG.2, rather than having the gate fingers116carry the gate signal for the entire width of the device, the gate signal is carried by the gate jumpers172over a large part of the width of the device and then distributed to the gate fingers116at various locations along the width of the device.

The gate jumpers172may have larger cross sectional areas than the gate fingers116, and thus may be better able to handle higher current densities than the gate fingers116without the problems normally associated with increased gate widths, such as electromigration and reduction of high frequency gain performance.

FIG.3is a partial isometric view of the metal layout of transistor100, andFIG.4is a partial cross section taken along line A-A′ ofFIG.2. As can be seen inFIGS.3and4, the gate jumpers172are formed at a metal level higher than the metal level of the source contact segments162a,162b,162c, the gate fingers116, the gate bus114and the gate signal distribution bars174. The gate jumpers172are connected to the gate bus114and the gate signal distribution bars174by vertical contact plugs178.

The gate jumpers172, gate bus114, vertical contact plugs178and gate signal distribution bars174may be formed of a conductive material, such as copper or aluminum, having a very low resistance.

FIG.5is a plan view of a larger version of transistor100, andFIG.6is a detail plan view of a small portion150of the metal layout ofFIG.5(namely the portion within the dotted box inFIG.5). The transistor100includes a plurality of unit cells40that extend vertically (in the y-direction). Each of the unit cells40includes one gate finger116that extends over the entire width of the device, and is subdivided into series unit cells40a,40b,40cthat are arranged in the vertical direction (y-direction) as described above. In the embodiment illustrated inFIGS.5and6, each of the unit cells40has an overall width of 1120 microns, with the series unit cells40a,40b, and40chaving widths of 370 microns, 380 microns and 370 microns, respectively, although the inventive concepts are not limited to these particular dimensions. In this manner, the effective gate width of the device may be increased.

Referring toFIG.6, a gate pad112and gate bus114are provided at the one end of the structure, while a drain pad132and drain bus134are provided at the other end of the structure. Source pads122are provided on the side of the structure and are connected to a source bus124. The source bus124is connected to a plurality of source contact bars128that extend in the lateral direction (x-direction) to contact the source contact segments162a,162b,162c. As noted above, the source contact segments162a,162b,162cmay be electrically connected in other ways such as through the use of source contact plugs that electrically connect each source contact segment162a,162b,162cto a common conductive layer.

The detail view of the portion150of the device layout of the transistor100inFIG.6also illustrates the gate fingers116, the gate jumpers172, gate signal distribution bars174and the gate signal distribution points176where the gate signal distribution bars174contact the gate fingers116.

FIG.7is a cross-section of a unit cell40of a transistor device100taken along line B-B′ ofFIG.2. The transistor structure100includes a semiconductor structure120including a substrate200, which may, for example, include 4H—SiC or 6H—SiC. A channel layer210is formed on the substrate200, and a barrier layer220is formed on the channel layer210. The channel layer210and the barrier layer220may include Group III-nitride based materials, with the material of the barrier layer220having a higher bandgap than the material of the channel layer210. For example, the channel layer210may comprise GaN, while the barrier layer220may comprise AlGaN.

Due to the difference in bandgap between the barrier layer220and the channel layer210and piezoelectric effects at the interface between the barrier layer220and the channel layer210, a two dimensional electron gas (2DEG) is induced in the channel layer210at a junction between the channel layer210and the barrier layer220. The 2DEG acts as a highly conductive layer that allows conduction between the source and drain regions of the device that are beneath a source contact segment162band a drain contact136, respectively. The source contact segment162band the drain contact136are formed on the barrier layer220. A gate finger116is formed on the barrier layer220between the drain contact136and the source contact segment162b. A gate jumper172is provided over the source contact segment162b, and is connected to the gate finger116through a vertical contact plug178and a gate signal distribution bar174. The vertical contact plug178and the gate signal distribution bar174are provided in gaps162gbetween adjacent ones of the source contact segments162a-162cand do not physically contact the source contact segments162a-162c. Note that the source contact segment162bis not actually in the cross-section ofFIG.7as it is offset in the y-direction from the cut along line B-B′ (seeFIG.2), but is illustrated inFIG.7to facilitate the above explanation.

A first interlayer insulating layer232is formed over the drain contact136, the gate finger116, the source contact segment162band the gate signal distribution bar174. The interlayer insulating layer232may include a dielectric material, such as SiN, SiO2, etc. The vertical contact plug178penetrates the first interlayer insulating layer232. The gate jumper172is formed on the first interlayer insulating layer232, which insulates the gate jumper172from the source contact segment162b. A second interlayer insulating layer234may be formed on the first interlayer insulating layer232and the gate jumper172. The second interlayer insulating layer234may include a dielectric material, such as SiN, SiO2, etc.

The material of the gate finger116may be chosen based on the composition of the barrier layer220. However, in certain embodiments, conventional materials capable of making a Schottky contact to a nitride based semiconductor material may be used, such as Ni, Pt, NiSix, Cu, Pd, Cr, W and/or WSiN. The drain contacts136and source contact segments162may include a metal, such as TiAlN, that can form an ohmic contact to GaN.

Series gate resistors and odd mode resistors may be included in the high power transistors according to embodiments of the present invention in order to stabilize the feedback loops within the gate fingers and drains of the device. In high power devices, the gates may have long gate widths in order to increase the gate periphery of the device, which results in long feedback loops. Because these high power transistors have large transconductance values, the feedback loops may be prone to instability. In particular, the feedback loops may generate an unwanted signal which may be in or out of the frequency band of operation of the transistor. In either case, the generation of such a signal may be problematic, and may render the transistor unusable. The instability of the feedback loops tends to increase with the length of the feedback loop.

Pursuant to further embodiments of the present invention, high power transistors are provided that include multiple series gate resistors and/or odd mode resistors that are distributed throughout the device and, in particular, along the long gate fingers. The distributed series gate resistors and/or odd mode resistors may be particularly advantageous in transistors that have segmented gate fingers as such devices may include gap regions between the “gate splits” that are natural locations for locating the series gate resistors and/or odd mode resistors along the width of the gate fingers. Herein, the term “gate splits” refers to the shorter arrays of gate finger segments that are produced when long gate fingers are segmented into multiple gate finger segments as discussed above with reference toFIGS.2-7. The gap regions that are present between adjacent gate splits may be a convenient location for implementing the distributed series gate resistors and odd mode resistors, as will be discussed in greater detail below.

It has been found that by distributing the series gate resistors and/or odd mode resistors along the extended width of the gate fingers, the feedback loops may become sufficiently lossy such that the potential instability is overcome. Accordingly, by distributing the series gate resistors and/or odd mode resistors along the extended width of the gate fingers it may be possible to increase device yield and/or reduce the failure rate of devices in the field. Moreover, when the series gate resistors and/or odd mode resistors are distributed along and between gate finger segments of a segmented gate fingers, relatively small resistance levels may be used. For example, if a transistor has three gate splits, the resistance levels may be about one third the size of the resistance levels that would be used if the gate fingers were not segmented. Moreover, in practice it has been found that the reduction in the resistance values is even greater. For example, when three gate splits are used, the series resistors included along each gate segment may have resistance values that are one fourth to one fifth of the resistance value of a series gate resistor that is implemented at the gate pad. The use of resistors having lower resistance values reduces losses and therefore results in a transistor having a higher gain, while also exhibiting increased stability.

FIG.8is a plan (top) view of a metal layout of a transistor300in accordance with further embodiments that implements both the series gate resistors and the odd mode resistors in a distributed fashion, as discussed above. The transistor300is formed on a semiconductor structure320that includes one or more device epitaxial layers. The semiconductor structure320may be the same as the semiconductor structure120discussed above with reference toFIG.7. As with the preceding figures, the layout ofFIG.8is simplified for ease of understanding and includes a pair of gate pads312that are connected to a respective pair of gate buses314, as well as a drain pad332that is connected to a drain bus334. A source pad322and source bus are also included in the transistor300, but are omitted fromFIG.8for clarity of illustration. The source pad322is shown inFIG.10.

A plurality of gate fingers316are connected to each gate bus314and extend in the y-direction. Each gate finger316is divided in the y-direction into three gate finger segments316a,316band316c. As described below, the gate finger segments316a,316b,316cof each gate finger316may be electrically connected to each other via gate jumpers372, gate signal distribution bars374and vertical contact plugs378(FIG.9A). A plurality of drain contacts336are connected to the drain bus334and extend in parallel with and adjacent respective ones of the gate fingers316. The gate signal distribution bars374may be formed at a different vertical level in the device than the gate distribution bars174of transistor100to allow the gate signal distribution bars374to pass over the drain contacts336, as will be described below. Source contacts362are also provided and extend in the y-direction in parallel with adjacent ones of the gate fingers316. The source contacts362are also divided in the y-direction into respective source contact segments362a,362band362c. The source contact segments362a,362b,362cmay be electrically connected to each other via source contact plugs364. Each source contact plug364may electrically connect a respective source contact segment362a,362b,362cto a common conductive layer that acts as a source bus. This source bus may be located, for example, in a lower level of the device. More than one source contact plug364may be provided per source contact segment362a,362b,362cin some embodiments. Two representative source contact plugs364are illustrated on one source contact segment362cinFIG.8. The source contact plugs364for the other source contact segments362a,362b,362chave been omitted fromFIG.8(as well as fromFIGS.9A-9B and12-13) to simplify the drawings.FIGS.10and11illustrate how, for example, a pair of source contact plugs364may be provided for each source contact segment362a,362b,362c. The source contact segments362a,362b,362cmay also be electrically connected by other means such as, for example, source contact bars. InFIG.8, a total of sixteen segmented gate fingers316, eight segmented source contacts362and eight drain contacts336are shown. It will be appreciated, however, that the transistor300may have many more gate fingers316, source contacts362and drain contacts336so that the transistor300has a large number of unit cells. Fewer gate fingers316, source contacts362and drain contacts336may be provided in other embodiments.

Adjacent ones of the gate finger segments316a-316care separated by gaps316g, and adjacent ones of the source contact segments362a-362care separated by gaps362g. AlthoughFIG.8illustrates three gate finger segments316a-316cand three source contact segments362a-362cfor each respective gate finger316and source contact362, the inventive concepts are not limited to such a configuration. Thus, it will be appreciated that a gate finger316may include two or more gate finger segments and that a source contact362may include two or more source contact segments.

The gate fingers316may extend in parallel with the source contacts362for the entire length of the source contacts362. Because the gate fingers316and source contacts362are segmented, a plurality of unit cells340a,340b,340care defined along each gate finger316. That is, each gate finger segment316a-316cacts as a gate contact for a respective unit cell340a,340b,340cthat are laid out in the direction (y-direction) along which the gate fingers316extend. The sum of the width of the gate finger segments316a-316cdefines the total width of each gate finger316. Thus, the total width contributed to the gate periphery of the overall device by each gate finger316is equal to the sum of the widths of the gate finger segments316a-316cin the y-direction.

The transistor300further includes a plurality of gate jumpers372that extend along the y-direction in parallel with the gate fingers316. The gate jumpers372may be formed at a metal level higher than the metal level of the source contact segments362, the gate fingers316and the gate buses314. The gate jumpers372may be formed over the source contacts362, and may be insulated from the source contacts362by, for example, a dielectric layer and/or an air gap. The gate jumpers372need not extend over the source contact segments362cthat are farthest from the gate buses314. The gate jumpers372are electrically connected to the gate buses314. The gate jumpers372may electrically connect some or all of the gate finger segments316a-316cof each gate finger316to one of the gate buses314. In the embodiment depicted inFIG.8, each gate jumper372electrically connects gate finger segments316band316cto a gate bus314, while gate finger segments316aare connected to the gate buses314via more direct connections. Gate finger segments316amay be connected to the gate buses314through the gate jumper372in other embodiments. In some embodiments, the gate jumpers372may be positioned over the drain contacts336or the gate fingers316instead of over the source contacts362.

FIG.9Ais a partial cross section taken along line A-A′ ofFIG.8.FIG.9Bis a partial cross section taken along line B-B′ ofFIG.8. As can be seen inFIGS.8and9A, a plurality of gate jumpers372, gate signal distribution bars374and vertical contact plugs378are provided. The gate jumpers372are connected to a gate bus314and the gate signal distribution bars374by the vertical contact plugs378. The gate jumpers372, gate signal distribution bars374and vertical contact plugs378are used to connect each gate finger segment316b-316cto one of the gate buses314. The gate signal distribution bars374may be formed at a higher metal layer in the device than the gate fingers316. For example, the gate signal distribution bars374may be formed in the same metal layer of the device as the gate jumpers372, as shown inFIG.9A. Vertical contact plugs378may connect the gate jumpers372to the gate buses314. Additional vertical contact plugs378(not visible in the cross-section ofFIG.9A, but located at the points where each gate signal distribution bar passes over a gate resistor380in the plan view ofFIG.8) may physically and electrically connect the gate signal distribution bars374to the gate resistors and the gate finger segments316a-316cconnected thereto. As noted above, the gate jumpers372may extend over and above the source contacts362. As can be seen inFIG.8, a gate jumper372is provided over every other source contact362, in contrast to the transistor100ofFIGS.2-7which included a gate jumper172extending over every source contact162. Each gate jumper372in the transistor300ofFIGS.8-9Bthus feeds four gate fingers316instead of two gate fingers116as in the case of transistor100. The gate signal distribution bars374are formed at a higher metal layer in the device than the gate distribution bars174of transistor100to allow each gate signal distribution bar374to pass over two drain contacts336to connect to the outer ones of the four gate finger segments316a-316c.

The gate jumpers372, gate buses314, vertical contact plugs378and gate signal distribution bars374may be formed of a conductive material, such as copper or aluminum, having a very low resistance.

Still referring toFIGS.8and9A, the gate signal distribution bars374extend laterally (in the x-direction) in the gaps362gbetween adjacent ones of the source contact segments362a,362band362c. The gate signal distribution bars374that are coupled to the first gate finger segments316amay be coupled to two of the gate finger segments316a. Each of the gate signal distribution bars374that are coupled to the second or third gate finger segments316b,316cmay be coupled to four of the gate finger segments316bor316c. As can be seen inFIG.8, each gate signal distribution bar374that is coupled to the first gate finger segments316amay connect to one of the gate buses314through a gate resistor380. The gate signal distribution bars374that connect to the gate finger segments316amay be part of the same metal layer as the gate fingers316or part of the same metal layer as the gate jumpers372, since these gate signal distribution bars374need not cross the drain contacts336. Each gate signal distribution bar374that is coupled to either second gate finger segments316bor third gate finger segments316cmay connect to one of the gate buses314through one of the gate jumpers372, and may connect to the gate finger segments316b,316cthrough respective vertical contact plugs378, as can be seen inFIGS.8and9A. A series gate resistor380is provided on the electrical path between each gate finger segment316b,316cand its associated gate signal distribution bar374.

Referring still toFIGS.8and9A, the distribution of an electrical signal that is applied to the gate pad312on the left-hand side ofFIG.8to the leftmost gate finger segments316a,316b,316cinFIG.8will now be discussed. When the gate signal is applied to the gate pad312, it is carried to the left gate bus314. The gate signal travels from the left gate bus314through a first gate signal distribution bar374and a first series gate resistor380to the first gate finger segment316a. The gate signal also travels from the left gate bus314through a first vertical contact plug378that connects the gate bus314to a gate jumper372, through the gate jumper372to a second gate signal distribution bar374, and through the second gate signal distribution bar374to a second vertical contact plug378that connects to the leftmost second gate finger segment316bthrough a second series gate resistor380. Similarly, the gate signal travels from the left gate bus314through the first vertical contact plug378to the gate jumper372, through the gate jumper372to a third gate signal distribution bar374, and through the third gate signal distribution bar374to a third vertical contact plug378that connects to the leftmost third gate finger segment316cthrough a third series gate resistor380.

Thus, as shown inFIGS.8and9A, the gate signal does not travel the full length of any gate finger316, but instead travels only along the length of a gate finger segment (for example, gate finger segments316a) or along the length of a gate finger segment and part of the gate jumper372(for example, gate finger segments316b) or along the length of a gate finger segment and the full length of the gate jumper372(for example, gate finger segments316c). The gate jumpers372may have larger cross sectional areas than the gate fingers316, and thus may be better able to handle higher current densities than the gate fingers316without the problems normally associated with increased gate widths, such as electromigration and reduction of high frequency gain performance. The gate signals also travel along a portion of a gate signal distribution bar374and vertical contact plugs378. However, it should be noted thatFIG.8is not drawn to scale and that the distance that a gate signal travels along any gate signal distribution bar374may be very small compared to the length of a gate finger segment in the y-direction (e.g., less than 5%), as can be seen inFIGS.10-11. The distances travelled along the vertical contact plugs378are also very small. Accordingly, the distance that the gate signals travel along narrow conductive traces may be reduced.

As discussed above, the transistor300includes a plurality of series gate resistors380that are distributed throughout the device. In particular, a series gate resistor380is provided at or near one end of each gate finger segment316a,316b,316c. As shown inFIG.8, the gate fingers316are divided into three “gate splits,” namely a first gate split382athat includes the gate finger segments316a, a second gate split382bthat includes the gate finger segments316b, and a third gate split382cthat includes the gate finger segments316c. A first gap region384ais provided between the gate buses314and the first gate split382a, a second gap region384bis provided between gate splits382aand382b, and a third gap region384cis provided between gate splits382band382c.

As shown inFIG.8, the series gate resistors380may be formed in the above-described gap regions384a-384c. The series gate resistors380may be formed, for example, by depositing a higher resistivity conductive material, as compared to the conductive material used to form the gate fingers316, drain contacts336, source contacts362, etc. The series gate resistors380may be provided in any appropriate vertical level of the transistor300. In an example embodiment, the series gate resistors380may be formed at the same metallization level as the source contacts362, the drain contacts336and the gate fingers316, as can be seen or inferred fromFIGS.8and9A. It will also be appreciated that the gate resistors380(or the odd mode resistors390discussed below) may be replaced with other lossy elements that may act as the functional equivalent to a resistor, such as, for example, a series inductor-capacitor circuit.

As will be discussed below with reference toFIG.12, a single series gate resistor80may provided between each gate pad312and its associated gate bus314instead of the distributed series gate resistors380included in transistors according to certain embodiments of the present invention. When the series gate resistors are implemented as a single series gate resistor80between each gate pad312and its corresponding gate bus314, each series gate resistor80may need to have a relatively high resistance value in order to reduce or prevent instabilities in the device. In the transistor300, a plurality of series gate resistors380are positioned between the gate splits382of the device. Each of the gate resistors380may have a much smaller resistance value as compared to the gate resistors80that would be required if gate resistors80were only located between the gate pads312and the gate buses314.

A series gate resistor380may be provided for each gate finger segment316a,316b,316cin some embodiments, while in other embodiments some gate finger segments may share a series gate resistor380. In the particular embodiment depicted inFIG.8, all of the gate finger segments316b,316chave their own associated series gate resistor380, while pairs of gate finger segments316ashare a single series gate resistor380. It will also be appreciated that in other embodiments, some of the gate finger segments316a-316may not have an associated gate resistor380.

By distributing the series gate resistance in two or more locations along the gate fingers316, the feedback loops within the gate fingers and drains of the transistor may be made sufficiently lossy so that instability may be reduced or eliminated. This may improve device yields and/or reduce the occurrence rate of device failures in the field. Moreover, as described above and as can be seen inFIG.8, the current path along any particular gate finger segment316a,316b,316cmay only traverse a single series gate resistor380. As the series gate resistors380may have relatively small resistance values, power losses are reduced and the transistor300may thus support higher gain levels for a given size device.

As can be seen inFIG.8, the transistor300includes a drain contact336that extends in the y-direction along a first axis, a source contact362that extends in the y-direction along a second axis that is parallel to the first axis, and a gate finger316that extends between the source contact362and the drain contact336. The gate finger316comprises a plurality of discontinuous and collinear gate finger segments316a,316b,316cthat are electrically connected to each other. The transistor300further includes a plurality of spaced-apart gate resistors380that are electrically connected to the gate finger316. Each gate resistor380may be coupled between a respective one of the gate finger segments316a,316b,316cand a respective one of the gate signal distribution bars374. At least one of the gate resistors380is disposed between the first axis and the second axis. A gate jumper372is interposed along an electrical path between a gate bus314and the gate finger316. The gate jumper372is interposed along respective electrical paths between gate finger segments316band316cand the gate bus314, and respective gate resistors380are interposed along respective electrical paths between the gate jumper372and the gate finger segments316b,316c.

As can also be seen inFIG.8, the transistor300includes a source contact362that extends in the y-direction, a gate jumper372that extends in the y-direction, and a gate finger316that comprises a plurality of discontinuous and electrically-connected gate finger segments316a,316b,316c. The transistor300further includes a plurality of spaced-apart gate resistors380. Gate finger segments316band316care connected to the gate jumper372through respective first and second gate resistors380. Pairs of the gate finger segments316aare connected to the gate buses314through respective gate resistors380.

As is further shown inFIG.8, odd mode resistors390are also included in the transistor300. The odd mode resistors390are provided to break up the long odd mode instability feedback loops in the device. In particular, as the number of gate fingers316fed by a gate jumper372increases, instabilities may arise. For example, a transistor may be stable when a gate jumper372feeds four gate fingers316, but may start to show instability if the gate jumper372is used to feed eight gate fingers316. When instabilities arise may be a function of the gate finger width and the frequency of operation of the device. The odd mode resistors390may be interposed between adjacent gate signal distribution bars374. When the transistor300operates normally, the voltage on each side of each odd mode resistor390should be the same, and thus no current should flow between adjacent gate signal distribution bars374.

Odd mode resistors390may be provided in the gap regions384that are between adjacent gate splits382. As shown inFIGS.8and9B, odd mode resistors390may be implemented at, for example, the same metallization level as the gate signal distribution bars374and source contacts362, and may be directly connected between two adjacent gate distribution bars374. Odd mode resistors390may also be interposed between adjacent gate buses314.

Thus, the transistor300may include a plurality of gate fingers316that extend in the y-direction and that are spaced apart from each other in the x-direction. Each of the gate fingers316may include a plurality of spaced-apart and generally collinear gate finger segments316a,316b,316cthat are electrically connected to each other, where the gate finger segments316a,316b,316care arranged in respective gate splits382a,382b,382cthat are separated by gap regions384b,384c. Odd mode resistors390are disposed in the gap regions384b,384c. In example embodiments, the odd mode resistors390may be interposed between adjacent gate signal distribution bars374.

It will also be appreciated that the source contact362need not be segmented in some embodiments. In particular, the gate resistors380and the odd mode resistors may both be implemented in the same metal layer as the gate signal distribution bars374and the gate jumpers372. In such an implementation, the source contacts362need not be segmented. Thus, it will be appreciated that in other embodiments the resistors380,390may be implemented directly above, or above and to the side of, the source contacts362in other embodiments, and that each source contact362may be a single, continuous (i.e., non-segmented) source contact362.

WhileFIG.8depicts a transistor300that includes segmented gate fingers316and segmented source contacts362, it will be appreciated that embodiments of the present invention are not limited thereto. For example, in other embodiments, the drain contacts336may be segmented in a similar fashion so that each drain contact includes, for example, three separate segments. When the drain contacts336are segmented, they may be electrically connected to each other via, for example, drain contact plugs and another metallization layer in the device. In embodiments, where the drain contacts are segmented, the source contacts362may or may not be segmented. Additionally, the gate fingers316may be segmented as shown inFIG.8or may not be segmented as shown inFIG.2(as well as inFIGS.14-15). Segmenting the drain contacts may provide additional room in the regions between the gate splits for gate resistors380and/or odd mode resistors390. As one simplt example of such an embodiment having segmented drain contacts336, the transistor300ofFIG.8could be modified so that reference numerals332,334and336were a source pad, a source bus and source contacts, respectively, and reference numerals362362a/362b/362cand364were a drain contact, drain contact segments and drain contact plugs, respectively. In other words,FIG.8may also be viewed as an embodiment having segmented gate fingers316and segmented drain contacts362simply by reversing the source and drain features.

FIG.10is a plan view of a larger version of the transistor300ofFIG.8.FIG.11is a detail plan view of a small portion302of the transistor300ofFIG.10.

Referring toFIGS.10and11, the transistor300includes a plurality of unit cells that extend vertically (in the y-direction). Each of the unit cells includes a gate finger316that extends over the entire width of the device, and is subdivided into series unit cells340a,340b,340cthat are arranged in the vertical direction (y-direction) as described above. In the embodiment illustrated inFIGS.10-11, each of the unit cells340has an overall width of 1120 microns, with the series unit cells340a,340b, and340chaving widths of 370 microns, 380 microns and 370 microns, respectively, although the inventive concepts are not limited to these particular dimensions.

A plurality of gate buses314are provided at the one end of the structure, while a drain bus334is provided at the other end of the structure. Source pads322are provided on the side of the structure and are connected to a source bus that is located, for example, on a lower metallized layer of the device (not shown). The source contact segments362a,362b,362care connected to the source bus via contact plugs364.

The detail view of the portion302of the device layout of the transistor300inFIG.11also illustrates the gate fingers316, the gate jumpers372, the gate signal distribution bars374, the series gate resistors380and the odd mode resistors390.

The transistors according to embodiments of the inventive concepts may include a semiconductor structure that is a multiple layer structure. For example, as discussed above with reference toFIG.7, the semiconductor structure120of transistor100may include a substrate200(e.g., 4H—SiC or 6H—SiC) that has at least a channel layer210and a barrier layer220formed thereon. The same is true with respect to the other transistors according to embodiments of the inventive concepts that are depicted herein. Thus, while it will be appreciated that the discussion of the semiconductor structure120inFIG.7applies equally to the semiconductor structures of each of the other embodiments described herein, although the metallization and other aspects of the device will vary based on the differences between the various embodiments depicted in the figures. Thus, for example, it will be appreciated that all of the transistors described herein may include silicon carbide substrates and Group III-nitride based channel and barrier layers, and that the semiconductor structures of these transistors may operate in the manner described with reference toFIG.7.

FIG.12is a plan view of a metal layout of a transistor400in accordance with further embodiments of the inventive concepts. The transistor400is similar to the transistor300discussed above with reference toFIGS.8-11, except that the transistor400uses a series gate resistors80that are connected between each gate pad312and a respective gate bus314instead of the distributed series gate resistors380that are included in the transistor300. Since aside from this change the two transistors300,400may otherwise be essentially identical, further discussion of the transistor400will be omitted.

FIG.13is a plan view of a metal layout of a transistor500in accordance with still further embodiments of the inventive concepts. The transistor500is also similar to the transistor300discussed above with reference toFIGS.8-11, except that the transistor500uses a single odd mode resistor90between each pair of adjacent gate buses314and does not include the distributed odd mode resistors390that are provided in the gap regions384b,384cin transistor300ofFIG.8. Since aside from this change the two transistors300,500may otherwise be essentially identical, further discussion of the transistor500will be omitted.

It will be appreciated that features of the above-described embodiments may be combined in any way to create a plurality of additional embodiments. For example,FIG.14is a plan view of a metal layout of a transistor100′ that is identical to the transistor100described above, except that it has been modified to include series gate resistors180that may be identical to the series gate resistors380ofFIG.8. As another example,FIG.15is a plan view of a metal layout of a transistor300′ that is similar to the transistor300described above, except that the gate fingers316are no longer segmented, and the location of the series gate resistors380are modified accordingly. It will be appreciated thatFIGS.14and15are provided to illustrate a few of the possible combinations of the different embodiments that result in additional embodiments.

Embodiments of the inventive concepts may be particularly well suited for use in connection with Group III-nitride based high electron mobility transistor (HEMT) devices. As used herein, the term “Group III nitride” refers to those semiconducting compounds formed between nitrogen and the elements in Group III of the periodic table, usually aluminum (Al), gallium (Ga), and/or indium (In). The term also refers to ternary and quaternary compounds such as AlGaN and AlInGaN. These compounds all have empirical formulas in which one mole of nitrogen is combined with a total of one mole of the Group III elements.

Suitable structures for GaN-based HEMTs that may utilize embodiments of the present invention are described, for example, in commonly assigned U.S. Publication No. 2002/0066908A1 published Jun. 6, 2002, for “Aluminum Gallium Nitride/Gallium Nitride High Electron Mobility Transistors Having A Gate Contact On A Gallium Nitride Based Cap Segment And Methods Of Fabricating Same,” U.S. Publication No. 2002/0167023A1 for “Group-III Nitride Based High Electron Mobility Transistor (HEMT) With Barrier/Spacer Layer,” published Nov. 14, 2002, U.S. Publication No. 2004/0061129 for “Nitride-Based Transistors And Methods Of Fabrication Thereof Using Non-Etched Contact Recesses,” published on Apr. 1, 2004, U.S. Pat. No. 7,906,799 for “Nitride-Based Transistors With A Protective Layer And A Low-Damage Recess” issued Mar. 15, 2011, and U.S. Pat. No. 6,316,793 entitled “Nitride Based Transistors On Semi-Insulating Silicon Carbide Substrates,” issued Nov. 13, 2001, the disclosures of which are hereby incorporated herein by reference in their entirety.

In particular embodiments of the present invention, the substrate200may be a semi-insulating silicon carbide (SiC) substrate that may be, for example, 4H polytype of silicon carbide. Other silicon carbide candidate polytypes include the 3C, 6H, and 15R polytypes.

Optional buffer, nucleation and/or transition layers (not shown) may be provided on the substrate200beneath the channel layer210. For example, an AlN buffer layer may be included to provide an appropriate crystal structure transition between the silicon carbide substrate and the remainder of the device. Additionally, strain balancing transition layer(s) may also be provided as described, for example, in commonly assigned U.S. Publication 2003/0102482A1, published Jun. 5, 2003, and entitled “Strain Balanced Nitride Hetrojunction Transistors And Methods Of Fabricating Strain Balanced Nitride Heterojunction Transistors,” the disclosure of which is incorporated herein by reference as if set forth fully herein. Moreover, one or more capping layers, such as SiN capping layers, may be provided on the barrier layer220.

Silicon carbide has a much closer crystal lattice match to Group III nitrides than does sapphire (Al2O3), which is a very common substrate material for Group III nitride devices. The closer lattice match of SiC may result in Group III nitride films of higher quality than those generally available on sapphire. Silicon carbide also has a very high thermal conductivity so that the total output power of Group III nitride devices on silicon carbide is, typically, not as limited by thermal dissipation of the substrate as in the case of the same devices formed on sapphire. Also, the availability of semi-insulating silicon carbide substrates may provide for device isolation and reduced parasitic capacitance. Appropriate SiC substrates are manufactured by, for example, Cree, Inc., of Durham, N.C., the assignee of the present invention.

Although silicon carbide may be used as a substrate material, embodiments of the present invention may utilize any suitable substrate, such as sapphire, aluminum nitride, aluminum gallium nitride, gallium nitride, silicon, GaAs, LGO, ZnO, LAO, InP and the like. In some embodiments, an appropriate buffer layer also may be formed.

In some embodiments of the present invention, the channel layer210is a Group III-nitride, such as AlxGa1−xN where 0≤x<1, provided that the energy of the conduction band edge of the channel layer210is less than the energy of the conduction band edge of the barrier layer220at the interface between the channel and barrier layers. In certain embodiments of the present invention, x=0, indicating that the channel layer210is GaN. The channel layer210may also be other Group III-nitrides such as InGaN, AlInGaN or the like. The channel layer210may be undoped or unintentionally doped and may be grown to a thickness of greater than about 20 Å. The channel layer210may also be a multi-layer structure, such as a superlattice or combinations of GaN, AlGaN or the like.

The channel layer210may have a bandgap that is less than the bandgap of the barrier layer220, and the channel layer210may also have a larger electron affinity than the barrier layer220. In certain embodiments of the inventive concepts, the barrier layer220is AlN, AlInN, AlGaN or AlInGaN with a thickness of between about 0.1 nm and about 10 nm. In particular embodiments of the inventive concepts, the barrier layer22is thick enough and has a high enough Al composition and doping to induce a significant carrier concentration at the interface between the channel layer210and the barrier layer220.

The barrier layer220may be a Group III-nitride and has a bandgap larger than that of the channel layer210and a smaller electron affinity than the channel layer210. Accordingly, in certain embodiments of the present invention, the barrier layer220may include AlGaN, AlInGaN and/or AlN or combinations of layers thereof. The barrier layer220may, for example, be from about 0.1 nm to about 30 nm thick. In certain embodiments of the present invention, the barrier layer220is undoped or doped with an n-type dopant to a concentration less than about 1019cm−3. In some embodiments of the present invention, the barrier layer220is AlxGa1−xN where 0<x<1. In particular embodiments, the aluminum concentration is about 25%. However, in other embodiments of the present invention, the barrier layer220comprises AlGaN with an aluminum concentration of between about 5% and about 100%. In specific embodiments of the present invention, the aluminum concentration is greater than about 10%.

While embodiments of the present invention are illustrated with reference to a GaN High Electron Mobility Transistor (HEMT) structure, the present inventive concepts are not limited to such devices. Thus, embodiments of the present invention may include other transistor devices having a plurality of unit cells and a controlling electrode. Embodiments of the present invention may be suitable for use in any semiconductor device where a wider controlling electrode is desired and multiple unit cells of the device are present. Thus, for example, embodiments of the present invention may be suitable for use in various types of devices, such as, MESFETs, MMICs, SITs, LDMOS, BJTs, pHEMTs, etc., fabricated using SiC, GaN, GaAs, silicon, etc.

It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present invention. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms “a,” “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” “comprising,” “includes” and/or “including” when used herein, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms used herein should be interpreted as having a meaning that is consistent with their meaning in the context of this specification and the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

It will be understood that when an element such as a layer, region or substrate is referred to as being “on” or extending “onto” another element, it can be directly on or extend directly onto the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly on” or extending “directly onto” another element, there are no intervening elements present. It will also be understood that when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements present.

Relative terms such as “below” or “above” or “upper” or “lower” or “horizontal” or “lateral” or “vertical” may be used herein to describe a relationship of one element, layer or region to another element, layer or region as illustrated in the figures. It will be understood that these terms are intended to encompass different orientations of the device in addition to the orientation depicted in the figures.

Embodiments of the invention are described herein with reference to cross-section illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the invention. The thickness of layers and regions in the drawings may be exaggerated for clarity. Additionally, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments of the invention should not be construed as limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing.

In the drawings and specification, there have been disclosed typical embodiments of the invention and, although specific terms are employed, they are used in a generic and descriptive sense only and not for purposes of limitation, the scope of the invention being set forth in the following claims.