Patent ID: 12193271

DETAILED DESCRIPTION

Examples of embodiments are described with reference to the accompanying drawings. In the drawings, like reference numerals may refer to like elements. Practical embodiments may have different forms and should not be construed as being limited to the described embodiments.

Although the terms “first.” “second,” etc. may be used to describe various components/elements, these components/elements should not be limited by these terms. These terms may be used to distinguish one component/element from another. A first element may be termed a second element without departing from teachings of one or more embodiments. The description of an element as a “first” element may not require or imply the presence of a second element or other elements. The terms “first,” “second,” etc. may be used to differentiate different categories or sets of elements. For conciseness, the terms “first,” “second,” etc. may represent “first-category (or first-set),” “second-category (or second-set),” etc., respectively.

The singular forms “a,” “an,” and “the” may indicate the plural forms as well, unless the context clearly indicates otherwise.

The terms “includes”, “comprises”, “has”, “including”, “comprising”, and/or “having” may specify the presence of stated features or elements, but may not preclude the presence or addition of one or more other features or elements.

When a first element is referred to as being “on” component second element, the first element can be directly or indirectly on the second element. Zero, one, or more intervening elements may be present between the first element and the second element.

Dimensions in the drawings may be exaggerated for convenience of explanation and may not limit embodiments.

The term “connect” may mean “directly connect” or “indirectly connect.” The term “connect” may mean “mechanically connect” and/or “electrically connect.” The term “connected” may mean “electrically connected” or “electrically connected through no intervening transistor.” The term “insulate” may mean “electrically insulate” or “electrically isolate.” The term “conductive” may mean “electrically conductive.” The term “include” or “comprise” may mean “be made of.” The term “adjacent” may mean “immediately adjacent.” The expression that an element extends in a particular direction may mean that the element extends lengthwise in the particular direction and/or that the lengthwise direction of the element is in the particular direction. The term “defined” may mean “formed” or “provided.” The expression that a space or opening overlaps an object may mean that (the position of) the space or opening overlaps with (the position of) the object. The term “overlap” may be equivalent to “be overlapped by.” The expression that a first element overlaps with a second element in a plan view may mean that the first element overlaps the second element in direction perpendicular to a substrate. A thickness may be in a direction perpendicular to a substrate. A height may be with reference to a substrate. The terms “lower” and “upper” may be relative to a substrate. The expression “about A to about B” may mean “in a range of A to B.”

FIGS.1to6are schematic cross-sectional views illustrating structures formed in a method of manufacturing a display apparatus according to an embodiment.FIG.4is a view for explaining seed growth during a crystallization process.

Referring toFIG.1, after a substrate100is prepared, a buffer layer110may be formed on the substrate100, and an amorphous silicon layer120may be formed on the buffer layer110.

The substrate100may include glass or a polymer resin. The polymer resin may include at least one of polyethersulfone, polyarylate, polyether imide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyimide, polycarbonate, cellulose triacetate, cellulose acetate propionate, and the like.

The substrate100may include organic material layers and inorganic material layers that are alternately stacked. For example, the substrate100may include a first base layer, a first barrier layer, a second base layer, and a second barrier layer, which are sequentially stacked. The first base layer and the second base layer may each include an organic material, and the first barrier layer and the second barrier layer may each include an inorganic material.

The buffer layer110may be formed on the substrate100. The buffer layer110may prevent foreign matter, moisture, or external air from moving from the substrate100to the amorphous silicon layer120. The buffer layer110may include an inorganic material such as silicon oxide, silicon oxynitride, or silicon nitride, and may include a single layer or multiple layers.

The amorphous silicon layer120may be formed on the buffer layer110. The amorphous silicon layer120may include amorphous silicon. The amorphous silicon layer120may include a first layer121and a second layer123. The first layer121of the amorphous silicon layer120may be formed on the substrate100, and the second layer123may be formed on the first layer121. The buffer layer110may be between the first layer121of the amorphous silicon layer120and the substrate100.

The first layer121of the amorphous silicon layer120may refer to a lower layer (or a lower portion) of the amorphous silicon layer120in a thickness direction (i.e., a z direction) of the amorphous silicon layer120, and the second layer123of the amorphous silicon layer120may refer to an upper layer (or an upper portion) of the amorphous silicon layer120in the thickness direction (i.e., the z direction) of the amorphous silicon layer120.

The first layer121may correspond to a portion from a lower surface120aof the amorphous silicon layer120to a ⅓ point in the thickness direction of the amorphous silicon layer120, and the second layer123may correspond to a portion from the ⅓ point of the amorphous silicon layer120to an upper surface120bof the amorphous silicon layer120. That is, in the z direction, a thickness t2of the first layer121may be ⅓ of a thickness t1of the amorphous silicon layer120, and a thickness t3of the second layer123may be ⅔ of the thickness t1of the amorphous silicon layer120.

The thickness t1of the amorphous silicon layer120may be about 450 angstroms (Å) to about 500 Å. If the thickness t1of the amorphous silicon layer120is less than 450 Å, the thickness of a semiconductor layer140(seeFIG.6) manufactured using the amorphous silicon layer120may be too thin, such that the characteristics of a thin-film transistor TFT (seeFIG.6) including the semiconductor layer140may be unsatisfactory. If the thickness t1of the amorphous silicon layer120exceeds 500 Å, the thickness of the semiconductor layer140(seeFIG.5) manufactured using the amorphous silicon layer120may be too thick, such that the characteristics of a thin-film transistor TFT including the semiconductor layer140may be unsatisfactory. Since the thickness t1of the amorphous silicon layer120is about 450 Å to about 500 Å, the characteristics of the thin-film transistor TFT may be satisfactory.

The thickness t2of the first layer121of the amorphous silicon layer120may be about ⅓ of the thickness t1of the amorphous silicon layer120. For example, the thickness t1of the first layer121of the amorphous silicon layer120may be about 150 Å to about 170 Å.

If a/the hydrogen content in/of the amorphous silicon layer120is too high, during a crystallization process of crystallizing the amorphous silicon layer120into a polycrystalline silicon layer130(seeFIG.3), hydrogen in the amorphous silicon layer120may significantly explode, resulting in a substantial film breakage defect. In particular, if a/the hydrogen content in/of the second layer123of the amorphous silicon layer120is high, a significant film breakage defect may occur.

FIG.7is a graph showing values of a/the hydrogen content in/of an amorphous silicon layer according to deposition temperatures of the amorphous silicon layer according to one or more embodiments.

Referring toFIG.7, when the deposition temperature of the amorphous silicon layer120is 390° C., the hydrogen content in the amorphous silicon layer120is 3.5 at %, and the hydrogen content in the amorphous silicon layer120decreases as the deposition temperature of the amorphous silicon layer120increases. As the deposition temperature of the amorphous silicon layer120increases, hydrogen in the amorphous silicon layer120is released to the outside, and thus the hydrogen content in the amorphous silicon layer120decreases.

When heat treatment is performed on the amorphous silicon layer120, hydrogen contained in the amorphous silicon layer120may be released to the outside, and thus the hydrogen content in the amorphous silicon layer120may be reduced. The hydrogen content in the amorphous silicon layer120may be controlled by heat-treating the amorphous silicon layer120before the crystallization process of crystallizing the amorphous silicon layer120into the polycrystalline silicon layer130. By heat-treating the amorphous silicon layer120before the crystallization process, the hydrogen content in the amorphous silicon layer120may be lowered to prevent or reduce occurrences of film breakage defects during the crystallization process.

Referring back toFIG.1, the amorphous silicon layer120may be deposited on the buffer layer110at a temperature of about 390° C. to about 490° C. If the deposition temperature of the amorphous silicon layer120is less than about 390° C., the deposition temperature may be too low, and thus hydrogen in the amorphous silicon layer120and/or the second layer123may not be sufficiently released to the outside, such that the hydrogen content in the amorphous silicon layer120may be too high. As a result, a significant film breakage defect may occur during the crystallization process. On the other hand, if the deposition temperature of the amorphous silicon layer120exceeds about 490° C., the deposition temperature may be too high, and the amorphous silicon layer120may be damaged, such that the reliability (or characteristics) of the semiconductor layer140manufactured using the amorphous silicon layer120may be unsatisfactory. Since the amorphous silicon layer120is deposited at a temperature of about 390° C. to about 490° C., the hydrogen content in the amorphous silicon layer120may be sufficiently low, and thus damage to the amorphous silicon layer120may be prevented or reduced, and the characteristics of the thin-film transistor TFT including a semiconductor layer manufactured using the amorphous silicon layer120may be satisfactory.

A heat treatment process may be performed after a deposition process. That is, after the amorphous silicon layer120is deposited on the buffer layer110, the deposited amorphous silicon layer120may be heat-treated. The hydrogen content in the second layer123of the amorphous silicon layer120may be reduced through the heat treatment of the amorphous silicon layer120.

A heat treatment temperature in an operation of heat-treating the amorphous silicon layer120may be about 440° C. to about 500° C. If the heat treatment temperature is less than about 440° C., the heat treatment temperature may be too low, and thus hydrogen in the amorphous silicon layer120and/or the second layer123may not be sufficiently released to the outside, and thus the hydrogen content in the amorphous silicon layer120may be too high. As a result, a significant film breakage defect may occur during the crystallization process. On the other hand, if the heat treatment temperature exceeds about 500° C., the heat treatment temperature may be too high, and the amorphous silicon layer120may be damaged, and thus the reliability (or characteristics) of the semiconductor layer140manufactured through the amorphous silicon layer120may be unsatisfactory. Since the amorphous silicon layer120is heat-treated at a temperature of about 440° C. to about 500° C., the hydrogen content in the amorphous silicon layer120may be sufficiently low, and thus damage to the amorphous silicon layer120may be prevented or reduced, and the characteristics of the thin-film transistor TFT including the semiconductor layer manufactured using the amorphous silicon layer120may be satisfactory.

A heat treatment time (period) in an operation of heat-treating the amorphous silicon layer120may be about 300 seconds to about 360 seconds. If the heat treatment time is less than about 300 seconds, the heat treatment time may be too short, and thus hydrogen in the amorphous silicon layer120and/or the second layer123may not be released to the outside, such that the hydrogen content in the amorphous silicon layer120may be undesirably high. As a result, a significant film breakage defect may occur during the crystallization process. On the other hand, if the heat treatment time exceeds about 360 seconds, the heat treatment time may be too long, and thus the amorphous silicon layer120may be damaged, such that the reliability (or characteristics) of the semiconductor layer140manufactured using the amorphous silicon layer120may be unsatisfactory. Since the amorphous silicon layer120is heat-treated for a time in a range of about 300 seconds to about 360 seconds, the hydrogen content in the amorphous silicon layer120may be sufficiently low, and thus damage to the amorphous silicon layer120may be prevented or reduced, such that the characteristics of the thin-film transistor TFT including the semiconductor manufactured using the amorphous silicon layer120may be satisfactory.

FIG.8is a graph showing values of a crystallization margin according to values of a/the hydrogen content in/of an amorphous silicon layer according to one or more embodiments. The crystallization margin may refer to a crystallization energy region without stains.

Referring toFIG.8, the crystallization margin of a crystallization process increases as the hydrogen content in the amorphous silicon layer120increases. As the hydrogen content in the amorphous silicon layer120increases from 1.1 at % to 3.1 at %, the crystallization margin of a crystallization process of crystallizing the amorphous silicon layer120into the polycrystalline silicon layer130(seeFIG.3) may improve.

However, when the hydrogen content in the amorphous silicon layer120increases from 3.1 at % to 3.5 at %, the crystallization margin of the crystallization process decreases from 16 mJ/cm2to 13 mJ/cm2. Up to 3.1 at %, the higher the hydrogen content in the amorphous silicon layer120, the higher the crystallization margin of the crystallization process. However, when the hydrogen content in the amorphous silicon layer120is too high, defects such as significant film breakage may occur, such that the crystallization margin of the crystallization process may decrease.

Accordingly, the hydrogen content in the amorphous silicon layer120after the heat treatment operation is performed should be about 3 at % or less. Specifically, the hydrogen content in the amorphous silicon layer120after the heat treatment step is performed may be about 2 at % to about 3 at %.

When the hydrogen content in the amorphous silicon layer120is too low, the crystallization margin of the crystallization process may decrease; when the hydrogen content in the amorphous silicon layer120is too high, a film breakage defect may occur and thus the crystallization margin may decrease. Therefore, in order to increase the crystallization margin, it is necessary to control the hydrogen content in the amorphous silicon layer120. In particular, when the hydrogen content in the second layer123of the amorphous silicon layer120is too high, the probability of occurrence of a film breakage defect may increase, and thus it is necessary to optimize the hydrogen content in the second layer123of the amorphous silicon layer120.

Referring toFIG.2, after heat treatment is performed on the amorphous silicon layer120, an operation of doping the amorphous silicon layer120with impurities125may be performed. The impurities125may be hydrogen, hydrogen ions, or the like. The impurities125may include boron, phosphorus, arsenic, antimony, gallium, aluminum, or the like.

When heat treatment is performed on the amorphous silicon layer120, hydrogen in the amorphous silicon layer120may be released to the outside, and thus the hydrogen content in/of the amorphous silicon layer120may decrease. For example, both a/the hydrogen content in/of the first layer121of the amorphous silicon layer120and a/the hydrogen content in/of the second layer123of the amorphous silicon layer120may decrease. However, if the hydrogen content in the amorphous silicon layer120is too low, the crystallization margin of a crystallization process may decrease, and thus it is necessary to maintain sufficient hydrogen content in the amorphous silicon layer120. If the hydrogen content in the second layer123of the amorphous silicon layer120is too high, a film breakage defect may occur in the crystallization process, and thus it is desirable to increase the hydrogen content in/of the first layer121of the amorphous silicon layer120while minimizing an increase in the hydrogen content in/of the second layer123of the amorphous silicon layer120.

An operation of doping the amorphous silicon layer120with hydrogen may be an ion implantation process of implanting ionic hydrogen into the amorphous silicon layer120. The second layer123of the amorphous silicon layer120may be minimally doped with hydrogen, while the first layer121of the amorphous silicon layer120may be doped (or implanted) with a large amount of hydrogen. Accordingly, the content of hydrogen included in the first layer121of the amorphous silicon layer120may be significantly greater than the content of hydrogen included in the second layer123of the amorphous silicon layer120.

In the ion implantation process, ionic hydrogen may be implanted into the amorphous silicon layer120at an acceleration voltage in a range of about 3 keV to about 10 keV. If the acceleration voltage of the ion implantation process is less than 3 keV, a large amount of hydrogen may not reach the first layer121of the amorphous silicon layer120, and thus the hydrogen content in the second layer123of the amorphous silicon layer120may undesirably increase, which may cause a film breakage defect during the crystallization process. On the other hand, if the acceleration voltage of the ion implantation process is greater than 10 keV, the acceleration voltage may be too large, and thus, hydrogen may undesirably flow into the buffer layer110and/or the substrate100arranged under the amorphous silicon layer120. By implanting ionic hydrogen into the amorphous silicon layer120at an acceleration voltage in a range of about 3 keV to about 10 keV, the hydrogen content in the second layer123of the amorphous silicon layer120may be prevented from being significantly increased, and the hydrogen content in the first layer121of the amorphous silicon layer120may be sufficiently increased.

A/the dose amount of hydrogen in the ion implantation process may be about 1×1015atoms/cm3to about 1×1017atoms/cm3. If the dose amount of hydrogen is less than 1×1015atoms/cm3, the hydrogen content in the first layer121of the amorphous silicon layer120may be too low, and thus the crystallization margin may be unsatisfactory. On the other hand, if the dose amount of hydrogen exceeds 1×1017atoms/cm3, the amount of hydrogen may be too large, such that the hydrogen content in the second layer123of the amorphous silicon layer120may be undesirably high, and such that hydrogen may flow into the buffer layer110and/or the substrate100arranged under the amorphous silicon layer120. Since the dose amount of hydrogen in the ion implantation process is about 1×1015atom/cm3to about 1×1017atom/cm3, the hydrogen content in the second layer123of the amorphous silicon layer120may be desirably low, and the hydrogen content in the first layer121of the amorphous silicon layer120may be desirably high.

When heat treatment is performed on the amorphous silicon layer120at the temperature and/or time according to embodiments, the hydrogen content in/of the second layer123of the amorphous silicon layer120may be reduced, and thus film breakage defects during the crystallization process may be reduced or minimized.

The hydrogen content in the first layer121of the amorphous silicon layer120may be increased by implanting (or doping) hydrogen into the amorphous silicon layer120using the acceleration voltage and/or dose amount according to embodiments. By increasing the hydrogen content in/of the first layer121of the amorphous silicon layer120through an ion implantation process, the crystallization margin of a crystallization process may be increased.

Referring toFIGS.3and4, a crystallization process may be performed after the ion implantation process is performed. After hydrogen ions have been implanted into the amorphous silicon layer120to increase the hydrogen content in/of the first layer121of the amorphous silicon layer120, laser may be irradiated to the amorphous silicon layer120to crystallize the amorphous silicon layer120into the polycrystalline silicon layer130.

Referring toFIG.4, a seed127may be formed on the lower surface120aof the amorphous silicon layer120. The seed127may be/include a small amount of unmelted amorphous silicon, hydrogen, or another material. The seed127may be/include a small amount of unmelted amorphous silicon and hydrogen are combined with each other. The seed127may be/include a metallic material.

After laser irradiation on the amorphous silicon layer120, melted amorphous silicon may be solidified into polycrystalline silicon, and the polycrystalline silicon layer130may be formed.

The polycrystalline silicon layer130may include a third layer131and a fourth layer133. The third layer131of the polycrystalline silicon layer130may be formed on the buffer layer110and/or the substrate100, and the fourth layer133of the polycrystalline silicon layer130may be formed on the third layer131. The buffer layer110may be between the third layer131of the polycrystalline silicon layer130and the substrate100.

The third layer131of the polycrystalline silicon layer130may correspond to the first layer121of the amorphous silicon layer120, and the fourth layer133of the polycrystalline silicon layer130may correspond to the second layer123of the amorphous silicon layer120. The first layer121is crystallized to form the third layer131. The second layer123is crystallized to form the fourth layer133. The thickness of the first layer121may be substantially equal to the thickness of the third layer131, and the thickness of the second layer123may be substantially equal to the thickness of the fourth layer133. The third layer131of the polycrystalline silicon layer130may refer to a lower layer (or a lower portion) of the polycrystalline silicon layer130in a thickness direction (i.e., the z direction) of the polycrystalline silicon layer130, and the fourth layer133may refer to an upper layer (or an upper portion) of the polycrystalline silicon layer130in the thickness direction (i.e., the z direction) of the polycrystalline silicon layer130.

A/the hydrogen content in/of the third layer131of the polycrystalline silicon layer130may be greater than a/the hydrogen content in/of the fourth layer133of the polycrystalline silicon layer130. Because hydrogen is implanted into the first layer121of the amorphous silicon layer120through an ion implantation process, the hydrogen content in/of the third layer131may be greater than the hydrogen content in/of the fourth layer133. A/the hydrogen content in/of a lower surface130aof the polycrystalline silicon layer130may be greater than a/the hydrogen content in/of an upper surface130bof the polycrystalline silicon layer130.

When a laser is irradiated to the first layer121of the amorphous silicon layer120, hydrogen ions in the first layer121may combine with each other to form hydrogen gas, and as hydrogen ions combine with each other, energy may be radiated to the surroundings. A cooling time of the first layer121of the amorphous silicon layer120may be reduced because the energy is radiated to the surroundings, and the crystallization margin of a crystallization process may increase.

The uniformity of the generation of the seed127may increase as the cooling time of the melted silicon decreases. Therefore, the seed127may grow to form grains having a satisfactorily uniform size. The grain uniformity of the growing seed127may be improved due to hydrogen included in the first layer121. The sizes of the grains in the thickness direction (i.e., the z direction) of the polycrystalline silicon layer130may be uniform. Accordingly, an interface between grains of polycrystalline silicon included in the polycrystalline silicon layer130may be formed and oriented in the thickness direction (i.e., the z direction) of the polycrystalline silicon layer130. Advantageously, the crystallization margin of the crystallization process may increase.

Referring toFIG.5, after the crystallization process, the polycrystalline silicon layer130may be patterned to form the semiconductor layer140. The semiconductor layer140may include a fifth layer141and a sixth layer143. The fifth layer141of the semiconductor layer140may be formed on the buffer layer110and/or the substrate100, and the sixth layer143of the semiconductor layer140may be formed on the fifth layer141. The buffer layer110may be between the fifth layer141of the semiconductor layer140and the substrate100.

The fifth layer141of the semiconductor layer140may correspond to the third layer131of the polycrystalline silicon layer130, and the sixth layer143of the semiconductor layer140may correspond to the fourth layer133of the polycrystalline silicon layer130. The thickness of the fifth layer141may be substantially equal to the thickness of the third layer131, and the thickness of the sixth layer143may be substantially equal to the thickness of the fourth layer133. The fifth layer141of the semiconductor layer140may refer to a lower layer (or a lower portion) of the semiconductor layer140in a thickness direction (i.e., the z-direction) of the semiconductor layer140, and the sixth layer143may refer to an upper layer (or an upper portion) of the semiconductor layer140in the thickness direction (i.e., the z-direction) of the semiconductor layer140.

A/the hydrogen content in/of the fifth layer141of the semiconductor layer140may be greater than a/the hydrogen content in/of the sixth layer143of the semiconductor layer140. Because hydrogen is implanted into the first layer121of the amorphous silicon layer120through an ion implantation process, the hydrogen content in the fifth layer141may be greater than the hydrogen content in the sixth layer143. A/the hydrogen content in/of the lower surface of the semiconductor layer140may be greater than a/the hydrogen content in/of the upper surface of the semiconductor layer140.

Referring toFIG.6, a gate electrode150, an upper electrode163, connection electrodes171and173, and a light-emitting device200may be sequentially formed on the semiconductor layer140.

A first insulating layer113may be formed on the semiconductor layer140. The first insulating layer113may cover the semiconductor layer140. The first insulating layer113may include at least one of silicon oxide (SiO2), silicon nitride (SiNx), silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), zinc oxide (ZnOx), and the like. ZnOxmay include zinc oxide (ZnO) and/or zinc peroxide (ZnO2).

The gate electrode150may be formed on the first insulating layer113. The gate electrode150may overlap the semiconductor layer140. The semiconductor layer140may include a channel region and may a source region and a drain region on opposite sides of the channel region. The gate electrode150may overlap the channel region of the semiconductor layer140. The semiconductor layer140and the gate electrode150may be insulated from each other by the first insulating layer113. The gate electrode150may include at least one of aluminum (AI), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), copper (Cu), and the like, and may include a single layer or a multi-layer structure.

A thin-film transistor TFT may include the semiconductor layer140and the gate electrode150.

A second insulating layer115may be formed on the gate electrode150. The second insulating layer115may cover the gate electrode150. The second insulating layer115may include at least one of SiO2, SiNx, SiON, Al2O3, TiO2, Ta2O5. HfO2, ZnOx, and the like. ZnOxmay include ZnO and/or ZnO2.

A storage capacitor160may be formed on the substrate100. The storage capacitor160may include a lower electrode161and an upper electrode163. The lower electrode161may be positioned on the first insulating layer113. The lower electrode161and the gate electrode150may include the same material and be formed on the same layer. The upper electrode163may be positioned on the second insulating layer115. The second insulating layer115may function as a dielectric layer of the storage capacitor160.

The upper electrode163may include at least one of Al, Pt, Pd, Ag, Mg, Au, Ni, Nd, Ir, Cr, Li, Ca, Mo, Ti, W, Cu, and the like, and may include a single layer or a multi-layer structure.

A third insulating layer117may be formed on the upper electrode163. The third insulating layer117may cover the upper electrode163. The third insulating layer117may include at least one of SiO2, SiNx. SiON, Al2O3, TiO2, Ta2O5. HfO2, ZnOx, and the like. ZnOxmay include ZnO and/or ZnO2.

A first connection electrode171and/or a second connection electrode173may be formed on the third insulating layer117. The first connection electrode171and the second connection electrode173may include the same material and be formed on the same layer. The first connection electrode171and the second connection electrode173may each include at least one of Al, Pt, Pd, Ag, Mg, Au, Ni, Nd, Ir, Cr, Li, Ca, Mo, Ti, W, Cu, and the like, and may include a single layer or a multi-layer structure. The first connection electrode171and the second connection electrode173may each include Ti—Al—Ti.

AlthoughFIG.6shows that the first connection electrode171and the second connection electrode173are formed on the third insulating layer117, the present disclosure is not limited thereto. One of the first connection electrode171and the second connection electrode173may be omitted.

At least one of the first connection electrode171and the second connection electrode173may be electrically connected to the semiconductor layer140through a first contact hole CNT1.

A fourth insulating layer119may be formed on the first connection electrode171and the second connection electrode173. The fourth insulating layer119may include a polymer such as benzocyclobutene (BCB), polyimide, hexamethyldisiloxane (HMDSO), polymethyl methacrylate (PMMA) or polystyrene (PS), a polymer derivative having a phenol-based group, an acryl-based polymer, an imide-based polymer, an acryl ether-based polymer, an amide-based polymer, a fluorine-based polymer, a p-xylene-based polymer, and/or a vinyl alcohol-based polymer.

The light-emitting device200may be formed on the fourth insulating layer119. The light-emitting device200may include a first electrode210, an emission layer220, and a second electrode230, which are sequentially stacked. The first electrode210may be an anode, and the second electrode230may be a cathode.

The first electrode210may be formed on the fourth insulating layer119. The first electrode210may be connected to at least one of the first connection electrode171and the second connection electrode173through a second contact hole CNT2defined in the fourth insulating layer119, such that the light-emitting device200may be connected to the thin-film transistor TFT.

The first electrode210may be a (semi)transmissive electrode or a reflective electrode. The first electrode210may include a reflective layer including Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, and/or Cr, and may include a transparent or translucent electrode layer formed on the reflective layer. The transparent or translucent electrode layer may include at least of indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO), and aluminum zinc oxide (AZO). The first electrode210may have a stacked structure of ITO-Ag-ITO.

A pixel-defining layer180having an opening1800P exposing at least a portion of the first electrode210may be formed on the first electrode210. The opening1800P defined in the pixel-defining layer180may define a light-emitting region of light emitted from the light-emitting device200. The size/width of the opening1800P may correspond to the size/width of the light-emitting region.

The pixel-defining layer180may increase a distance between the edge of the first electrode210and the second electrode230, thereby preventing an arc at the edge of the first electrode210from occurring. The pixel-defining layer180may include one or more organic insulating materials, such as one or more of polyimide, polyamide, acrylic resin, benzocyclobutene, and phenol resin, and may be formed by spin coating or the like.

The emission layer220may be formed on the first electrode210. The emission layer220may be formed in the opening1800P defined in the pixel-defining layer180. The emission layer220may include a high molecular weight organic material or a low molecular weight organic material that emits light of a certain color. The emission layer220may include an inorganic light-emitting material or quantum dots.

The second electrode230may be formed on the emission layer220. The second electrode230may overlap the first electrode210. The second electrode230may include a conductive material having a low work function. The second electrode230may include a (semi)transparent layer including Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, Li, Ca, or an alloy of some of the above metals. The second electrode230may further include a layer including ITO, IZO, ZnO, or In2O3on the (semi)transparent layer. The second electrode230may cover an entire face of the substrate100.

Although not shown in the drawings, a first functional layer may be formed between the emission layer220and the first electrode210, and a second functional layer may be formed between the emission layer220and the second electrode230. The first functional layer may include a hole transport layer (HTL) and/or a hole injection layer (HIL). The second functional layer may include an electron transport layer (ETL) and/or an electron injection layer (EIL). The first functional layer and the second functional layer may be selectively arranged above and below the emission layer220. The first functional layer and/or the second functional layer may cover an entire face of the substrate100.

Although not shown in the drawings, an encapsulation member may be formed on the light-emitting device200. For example, a thin-film encapsulation layer or an encapsulation substrate may be formed on the light-emitting device200. The thin-film encapsulation layer may include at least one inorganic layer and at least one organic layer.

FIG.9is a schematic plan view of a display apparatus1according to an embodiment, andFIG.10is an equivalent circuit diagram of a pixel PX of the display apparatus1according to an embodiment.

Referring toFIGS.9and10, the display apparatus1may include a display area DA for displaying images and may include a peripheral area PA outside the display area DA. The display apparatus1may display images using light emitted from pixels PX positioned in the display area DA.

A substrate100may include glass, metal, plastic, or the like. The substrate100may include a flexible material and may be warped, bent, folded, or rolled. The flexible material may include ultra-thin glass, metal, or plastic.

Each pixel PX may include a display element, such as an organic light-emitting diode. The pixels PX may be arranged in one or more of a stripe configuration, a PENTILE™ configuration, a mosaic configuration, and the like to display images.

The display area DA may have a rectangular shape (as shown inFIG.9), a polygonal shape (such as a triangle, a pentagon, and/or a hexagon), a circular shape, an elliptical shape, and/or an irregular shape.

The peripheral area PA may not display images according to input signals. Wirings or pads may be arranged in the peripheral area PA. The wirings may transfer electric signals to the display area DA. A printed circuit board or a driver integrated circuit (IC) chip may be attached to the pads.

Referring toFIG.10, a pixel PX may include a pixel circuit PC and a light-emitting device200(shown inFIG.6) connected to the pixel circuit PC. The pixel circuit PC may be connected to a scan line SL and a data line DL. Referring toFIG.6, the light-emitting device200may include a first electrode210, an emission layer220, and a second electrode230. The second electrode230may receive a second driving voltage ELVSS.

The pixel circuit PC may include a first transistor T1, a second transistor T2, and a storage capacitor Cst. The first transistor T1may be a driving transistor in which the amount of a drain current is determined according to a gate-source voltage. The second transistor T2may be a switching transistor turned on/off according to a gate-source voltage, substantially a gate voltage. The first transistor T1and the second transistor T2may each be a thin-film transistor. The thin-film transistor TFT described with reference toFIG.6may be/represent at least one of the first transistor T1and the second transistor T2.

The storage capacitor Cst may be connected between a power line PL and a gate of the first transistor T1. The storage capacitor Cst may include an upper electrode and a lower electrode, the upper electrode being connected to the power line PL, and the lower electrode being connected to the gate of the first transistor T1. The storage capacitor Cst may store a voltage corresponding to a difference between a voltage transferred from the second transistor T2and a first driving voltage ELVDD supplied to the power line PL.

The first transistor T1may control the magnitude of a current flowing from the power line PL to the light-emitting device200according to a gate-source voltage. The light-emitting device200may emit light having brightness according to a driving current. The first transistor T1may include the gate, a drain, and a source, the gate being connected to the lower electrode of the storage capacitor Cst, the source being connected to the power line PL, and the drain being connected to the light-emitting device200.

The second transistor T2may transfer a data voltage Dm to the gate of the first transistor T1according to a scan signal Sn. The second transistor T2may include a gate, a drain, and a source, the gate being connected to the scan line SL, the source being connected to the data line DL, and the drain being connected to the gate of the first transistor T1and to the storage capacitor Cst.

FIG.10shows that the pixel circuit PC includes two transistors and one storage capacitor. The pixel circuit PC may include three or more transistors and/or two or more storage capacitors. The pixel circuit PC may include seven transistors and one storage capacitor. The pixel circuit PC may have nine transistors and two storage capacitors.

The display apparatus1may be manufactured according to the method described with reference toFIGS.1to5and may correspond toFIG.6.

According to embodiments, a display apparatus may include silicon layers with minimum defects.

The described embodiments should be considered in an illustrative sense and not for purposes of limitation. Descriptions of features or aspects within each embodiment should typically be considered as available for other similar features or aspects in other embodiments. While one or more embodiments have been described with reference to the figures, various changes in form and details may be made in the described embodiments without departing from the scope defined by the following claims.