Patent ID: 12238863

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those skilled in the art to which this disclosure belongs. It can be understood that these terms, such as those defined in commonly used dictionaries, should be interpreted as having meanings consistent with the background or context of the related technology and the present disclosure, and should not be interpreted in an idealized or overly formal manner, unless otherwise specified in the disclosed embodiments.

The terms “about”, “equal”, “equal to” or “same”, “substantially” or “roughly” are generally interpreted as within 20% of a given value or range, or as within 10%, 5%, 3%, 2%, 1%, or 0.5% of a given value or range. It should be noted that the amounts provided in the specification are approximate amounts, which means that even “about”, “approximate”, or “substantially” are not specified, the meanings of “about”, “approximate”, or “substantially” are still implied.

It should be noted that, in the following embodiments, the features of several different embodiments may be replaced, recombined, and mixed to complete other embodiments without departing from the spirit of the present disclosure. As long as the features of the various embodiments do not violate the spirit of the disclosure or conflict with each other, they can be mixed and matched arbitrarily.

Some embodiments of the disclosure are described below, and additional steps may be provided before, during, and/or after the various stages described in these embodiments. Some of the described stages may be replaced or eliminated in different embodiments. Semiconductor device structures may add additional components. Some of the described components may be replaced or eliminated in different embodiments. Although some of the embodiments discussed are performed in a particular order of steps, the steps may be performed in another logical order.

The term “substantially” as used herein indicates the value of a given quantity that can vary based on a particular technology node associated with the subject semiconductor device. In some embodiments, based on the particular technology node, the term “substantially” can indicate a value of a given quantity that varies within, for example, ±10% of a target (or intended) value.

It should be understood that the electronic device of the present disclosure may include a semiconductor device, a semiconductor packaging device, a display device, a radar device, a LIDAR device, an antenna device, a touch display device, a curved display device or a non-rectangular display device (free shape display), but not limited to this. The electronic device may be a bendable or flexible electronic device. The electronic device may include, for example, but not limited to, light-emitting diodes, liquid crystals, fluorescence, phosphors, other suitable display media, or a combination thereof. The light-emitting diodes may include, for example, organic light-emitting diodes (OLEDs), inorganic light-emitting diodes (LEDs), mini-light-emitting diodes (mini LEDs), micro-light-emitting diodes (micro-LEDs), quantum dots (QDs) light-emitting diodes (such as QLEDs, QDLEDs), other suitable materials or an arbitrary combination thereof, but not limited to. The display device may include, for example, but is not limited to, a tiled display device. The concepts or principles of the present disclosure may also be applied to a non-self-luminous liquid crystal display (LCD), but are not limited thereto.

The antenna device may be, for example, a5G antenna, a Beyond-5G antenna, a6G antenna, a liquid crystal antenna or other kinds of antennas, but is not limited thereto. The antenna device may include, for example, but is not limited to, a tiled antenna device. It should be noted that, the electronic device may be any arrangement or combination of the foregoing, but is not limited to this. In addition, the shape of the electronic device may be rectangular, circular, polygonal, a shape with curved edges, or other suitable shapes. The electronic device may have peripheral systems such as a driving system, a control system, a light source system, and a shelf system to support the display device, the antenna device or the tiled device. The electronic device of the present disclosure may be, for example, a display device, but is not limited thereto.

The present disclosure provides an electronic device and a method for forming the same. By forming a dummy via pattern in a substrate structure, the substrate structure can be prevented from warping due to uneven stress. Compared with conventional packaging structures of electronic devices, the electronic device disclosed in this disclosure can maintain the stability of the substrate structure without affecting the electrical requirements, and packaging structures formed by such electronic device may improve the functionality of the electronic unit through a via structure and a control unit. In addition, the formation of a dummy via structure electrically insulated from a circuit structure can be integrated into the fabrication process of a conductive via pattern. Therefore, the formation method of the present disclosure can manufacture electronic devices with better electrical and structural properties, or do not need to perform complicated manufacturing steps, thereby saving manufacturing costs.

FIG.1illustrates a cross-sectional view of an electronic device10according to some embodiments of the present disclosure. The electronic device10includes a substrate structure100, a control unit110, a first circuit structure120, and an electronic unit130. The substrate structure100has a conductive via pattern101and a dummy via pattern102. The control unit110is electrically connected to the conductive via pattern101, the first circuit structure120is electrically connected to the conductive via pattern101, and the electronic unit130is electrically connected to the control unit110through the first circuit structure120. The dummy via pattern102is electrically insulated from the first circuit structure120. According to some embodiments, the electronic device10may include at least one control unit110and at least one electronic unit130, but the number of which is not limited.

As shown inFIG.1, the substrate structure100may include a substrate material100M and the conductive via pattern101and the dummy via pattern102disposed in the substrate material100M. The substrate material100M may include hard or soft materials, such as glass, ceramics, polyimide (PI), polyethylene terephthalate (PET), steel plate, silicon base, other suitable materials, or a combination of the above materials, but not limited to.

The substrate structure100may include a transparent material or a translucent material. For example, in some embodiments, the substrate structure100has a through-glass via (TGV) structure, which includes the substrate material100M having an inorganic and amorphous glass material, and a conductive via material is disposed in the substrate material100M. For example, the substrate structure100including transparent material or translucent material can be used for processing from the other side of the component to be processed, such as laser processing, and is beneficial for the alignment of the circuit structures and elements on both sides, but not limited to this. According to some embodiments, the substrate structure100may include an opaque substrate, which can be processed on the other side through the configuration of alignment marks.

In some embodiments, the conductive via pattern101includes a first conductive via101A and a second conductive via101B. As shown inFIG.1, the first conductive via101A may be electrically connected to the control unit110through the first circuit structure120, and the second conductive via101B may be electrically connected to the electronic unit130through a portion of the first circuit structure120separated from the control unit110. However, the present disclosure is not limited thereto. In other embodiments, the control unit110and the electronic unit130may be electrically connected to a common conductive via through the first circuit structure120.

By disposing the dummy via pattern102in the substrate structure100, the substrate structure100can be prevented from warping due to uneven stress. Compared with packaging structures of conventional electronic devices, the electronic device10including the dummy via pattern102can maintain the stability of the substrate structure100without affecting the electrical requirements of the conductive via pattern101. Although the dummy via pattern102passing through the substrate material M is shown inFIG.1, the present disclosure is not limited thereto. In some embodiments, the dummy via pattern102is embedded in the substrate material M, and a top surface or a bottom surface of the dummy via pattern102is covered by the substrate material M. It should be understood that the present disclosure does not specifically limit the number, cross-sectional shape, and horizontal position of the vias included in the dummy via pattern102. For example, the conductive via101may be an I/O (input/output point) of an electronic device. When the number of I/O of the substrate is uneven, it may cause uneven stress on the substrate, thereby causing warpage. Therefore, the stress can be balanced by disposing the dummy via pattern102appropriately, but not limited thereto.

The material of the conductive via pattern101may include, for example, copper (Cu), tin (Sn), nickel (Ni), silver Ag), gold (Au), titanium (Ti), molybdenum (Mo), tungsten (W), aluminum (Al), other suitable conductive materials, or combinations thereof, but not limited thereto. The dummy via pattern102may include the same or similar material as the conductive via pattern101, but the disclosure is not limited thereto. In some embodiments, at least a portion of the dummy via pattern102includes an insulating material. For example, the parasitic capacitance can be reduced or the electrical interference caused to the nearby conductive via patterns101or circuit structures can be reduced, but not limited thereto.

The control unit110may be an element for controlling the electronic unit130, for example, a control element including a transistor. In some embodiments, the control unit110may be a thin film transistor (TFT) element. The control unit110may include a semiconductor layer112, a gate114, and a source/drain116. It should be noted that the aspect of the control unit110is not limited in this disclosure. For example, the control unit110may have top-gated, bottom-gated, or other suitable aspects, but is not limited thereto. In some embodiments, as shown inFIG.1, the control element110may be located above the substrate structure100, and the control unit110is located between the substrate structure100and the first circuit structure120. In addition, the semiconductor layer112, the gate114, and the source/drain116may be fully or partially embedded in a first insulating layer106and a second insulating layer108. In some embodiments, as shown inFIG.1, a top surface of the source/drain116is exposed above the second insulating layer108.

The material of the semiconductor layer112may include amorphous silicon, polysilicon, indium gallium zinc oxide (IGZO), other suitable semiconductor materials, or a combination thereof, but is not limited thereto. The material of the gate114may include Al, Ti, Mo, W, other suitable conductive materials, or a combination thereof, but is not limited thereto. The material of the source/drain116may include Al, Ti, Mo, W, other suitable conductive materials, or a combination thereof, but is not limited thereto. In some embodiments, the first insulating layer106and the second insulating layer108may include the same or similar material. Materials of the first insulating layer106and the second insulating layer108may include silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiOxNy), aluminum oxide (AlxOy), other suitable insulating materials, or a combination thereof, but not limited thereto. According to some embodiments, the thicknesses of the first insulating layer106and the second insulating layer108are greater than or equal to 500 nanometers (nm) and less than or equal to 5000 nm.

In some embodiments, the electronic device10further includes a buffer layer104disposed between the substrate structure100and the control unit110. As shown inFIG.1, the buffer layer104may cover the top surface of the dummy via pattern102. Since the material (such as copper) in the conductive via pattern101may diffuse to the control unit110at high temperature, by disposing the buffer layer104, the diffusion of the above material can be substantially blocked during high temperature processes to prevent the control unit110from being polluted. In some embodiments, to achieve the above purpose, the thickness of the buffer layer104is between about 400 nanometers (nm) and about 1500 nanometers (nm). In some embodiments, as shown inFIG.1, the first circuit structure120penetrates through the buffer layer104to be electrically connected to the conductive via pattern101. The material of the buffer layer104may include silicon nitride, silicon oxide, silicon oxynitride, aluminum oxide, other suitable insulating materials, or a combination thereof, but is not limited thereto.

In some embodiments, the electronic device10further includes a stress adjustment layer105disposed on the substrate structure100and located on the side of the substrate structure100opposite to the control unit110. As shown inFIG.1, the stress adjustment layer105may cover the bottom surface of the dummy via pattern102. By disposing the stress adjustment layer105on the substrate structure100, the stability of the substrate structure100can be further maintained when depositing components on the other side of the substrate structure100(such as the control unit110, the first circuit structure120, and the electronic unit130, etc.). The stress is balanced to avoid warping of the substrate structure100. In some embodiments, the coefficient of thermal expansion of the stress adjustment layer105is close to that of the insulating layers on the other side of the substrate structure100, and the insulating layers on the other side includes, for example, the buffer layer104, the first insulating layer106, and the second insulating layer108, etc. The material of the stress adjustment layer105may include silicon nitride, silicon oxide, silicon oxynitride, aluminum oxide, other suitable insulating materials, or a combination thereof, but is not limited thereto. The thickness of the stress adjustment layer105may be between 800 nanometers (nm) and about 3000 nanometers (nm).

Referring toFIG.1, the first circuit structure120is surrounded by a first dielectric layer122. The material of the first circuit structure120may include a material similar to that of the conductive via pattern101, such as Cu, Sn, Ni, Ag, Au, Ti, Mo, W, other suitable conductive materials, or a combination thereof, but not limited to this. The material of the first dielectric layer122may include polyimide (PI), polybenzoxazole PBO), benzocyclobutene (BCB), build-up material ABF (Ajinomoto Build-up Film), epoxy resin, other suitable dielectric materials, or a combination thereof, but not limited thereto.

In some embodiments, the electronic device10further includes an alignment component124disposed on the first circuit structure120and electrically connected to the electronic unit130. As shown inFIG.1, the alignment member124may have a cavity facing the electronic unit130. The alignment component124may be used to align the electronic unit130to a designated position above the first circuit structure120. In addition, by increasing the lateral stress that the electronic unit130can bear, the cavity of the alignment component124can be used to enhance the bonding strength between the first circuit structure120and the electronic unit130. The alignment component124may include a material similar to that of the first circuit structure120, but is not limited thereto. According to some embodiments, the alignment component124may be, for example, an under bump metallization (UBM), but not limited thereto.

The electronic unit130and the first circuit structure120may be electrically connected through a bonding material134. In some embodiments, as shown inFIG.1, the bonding material134is disposed on the alignment component124on the first circuit structure120, and the electronic unit130having an electrical connection portion132is disposed on the bonding material134. In some embodiments, there is a diffusion region136between the electrical connection portion132and the bonding material134, and the diffusion region136includes elements from the electrical connection portion132and the bonding material134.

The material of the bonding material134may include, for example, Au, Sn, Al, Cu, Ti, Ag, Ga, other suitable metals, or combinations thereof, but is not limited thereto. In some embodiments, the material of the bonding material134includes a mixture of particles of aforementioned metals and organic materials. The material of the electrical connection portion132includes Cu, Sn, Ni, Ag, Au, Ti, Mo, W, other suitable conductive materials, or a combination thereof, but is not limited thereto.

Depending on the application of the electronic device10, the electronic unit130may be various elements. For example, the electronic unit130may be a chip, a die, an integrated circuit, a diode, a capacitor, a resistor, an inductor, a sensing element, other suitable elements, or a combination thereof, but not limited thereto. The electronic device10further includes a protection layer140surrounding the electronic unit130. For example, the protection layer140can prevent moisture from affecting the electronic unit130or the circuit structure. According to some embodiments, the protection layer140may be in contact with at least two sides of the electronic unit130. According to some embodiments, at least one surface of the electronic unit130may be exposed but not in contact with the protection layer140. The material of the protection layer140may include silicone resin, epoxy resin, acrylic glue, other suitable materials, or a combination thereof, but is not limited thereto.

According to some embodiments, the protection layer140may be in contact with a side surface122SS of the first dielectric layer122. The protection layer140may also be in contact with a top surface108TS of the insulating layer108. Though the above configuration, the adhesion between different layers can be improved, which further improves the reliability of the electronic device, but not limited to.

In some embodiments, the electronic device10further includes a second circuit structure150disposed on the substrate structure100and opposite to the first circuit structure120. In some embodiments, the dummy via pattern102is electrically insulated from the second circuit structure150. As shown inFIG.1, for example, the dummy via pattern102and the second circuit structure150may be separated by the stress adjustment layer105. In some embodiments, the second circuit structure150penetrates through the stress adjustment layer105to be electrically connected to the conductive via pattern101. In some embodiments, the first circuit structure120is electrically connected to the second circuit structure150through the conductive via pattern101. In some embodiments, the second circuit structure150is surrounded by a second dielectric layer152. The second dielectric layer152may include a material similar to that of the first dielectric layer122, such as polyimide (PI), polybenzoxazole (PBO), benzocyclobutene (BCB), epoxy resin, ABF, other suitable dielectric materials, or a combination thereof, but not limited thereto.

In some embodiments, the electronic device10further includes an alignment component154disposed on the second circuit structure150. As shown inFIG.1, the alignment component154may have a cavity facing away from the substrate structure100. The alignment component154may be used to align the electronic device10to a designated location of an external circuit. In addition, the cavity of the alignment member154can be used to enhance the bonding strength between the electronic device10and the external circuit. The alignment component154may include a material similar to that of the alignment component124or the second circuit structure150, but not limited thereto. In some embodiments, as shown inFIG.1, a bonding material156is disposed on the alignment component154on the second circuit structure150, and the bonding material156can be used to bond the electronic device10to the external circuit. The aforementioned external circuit may include a printed circuit board (PCB) or a flexible printed circuit (FPC) board. For example, the first circuit structure120and the second circuit structure150may be, for example, a redistribution layer (RDL). Through the design of the redistribution layer, it is possible to flexibly design I/O or increase the fan-out range of the circuit structure. According to some embodiments, the alignment component124or the alignment component154may have a convex surface, a flat surface, a concave surface, or an arc surface, but not limited thereto. According to some embodiments, a surface of the alignment component124may be coplanar with or different from a surface of the dielectric layer122. In detail, the surface of the alignment component124may be higher than the surface of the dielectric layer122or the surface of the alignment component124may be lower than the surface of the dielectric layer122. According to some embodiments, a surface of the alignment component154may be coplanar with or different from a surface of the dielectric layer152. In detail, the surface of the alignment component154may be higher than the surface of the dielectric layer152or the surface of the alignment component154may be lower than the surface of the dielectric layer152.

FIG.2illustrates a cross-sectional view of an electronic device array20′ according to some embodiments of the present disclosure.FIG.2shows an electronic device array20′ including two electronic devices20, and each electronic device20has an electronic unit130and its corresponding first circuit structure120, control unit110, and second circuit structure150. In fact, the present disclosure does not limit the number of the electronic devices20included in the electronic device array20′ and the configuration of each electronic device20. For example, the electronic devices20may have a configuration similar to that of the electronic device10described with reference toFIG.1, and may also have a configuration where the control unit110and the electronic unit130are located on different sides of the substrate structure100(as shown inFIG.3). In addition, depending on the design requirements of the electronic device array20′, each electronic unit130may be the same, similar, or different kinds of elements, which is not limited in this disclosure. In some embodiments, there are connected conductive traces between the circuit structures of adjacent electronic devices20. Similar elements shown inFIGS.1and2are denoted by the same or similar reference numerals and may be formed with the same or similar materials and configurations, and detailed descriptions thereof are omitted here for simplicity.

FIG.3illustrates a cross-sectional view of an electronic device30according to some other embodiments of the present disclosure. The difference from the electronic device shown inFIG.1is that the control unit110and the electronic unit130of the electronic device30are located on different sides of the substrate structure100. That is, as shown inFIG.3, the control unit110is located below the substrate structure100, and the substrate structure100is located between the control unit110and the first circuit structure120. For example, through the above configuration, the control unit110can be prevented from interfering with the electronic unit130during operation, but it is not limited thereto.

In addition, in the embodiment shown inFIG.3, since the buffer layer104is disposed between the substrate structure100and the control unit110, the buffer layer104is also located below the substrate structure100. The stress adjustment layer105may be disposed on the side of the substrate structure100opposite to the control unit110such that the stress adjustment layer105is located between the substrate structure100and the electronic unit130. Similar elements shown inFIGS.1and3are denoted by the same or similar reference numerals and may be formed with the same or similar materials and configurations, and detailed descriptions thereof are omitted here for simplicity.

FIG.4illustrates a cross-sectional view of an electronic device40according to some other embodiments of the present disclosure. The difference from the electronic device shown inFIG.1is that a conductive material160is disposed between the substrate structure100and the first circuit structure120of the electronic device40. The substrate structure100of the electronic device40is electrically connected to the first circuit structure120through the conductive material160. The conductive material160may include materials similar to those of the first circuit structure120and the second circuit structure150, but is not limited thereto. In addition, similar elements shown inFIGS.1and4are denoted by the same or similar reference numerals and may be formed with the same or similar materials and configurations, and detailed descriptions thereof are omitted here for simplicity. By forming such electronic device40, the original process complexity of forming the first circuit structure120and the second circuit structure150on the upper and lower sides of the substrate structure100can be reduced.

FIGS.5A-5Fillustrate cross-sectional views of various stages of a manufacturing process of an electronic device according to some embodiments of the present disclosure.

Referring toFIG.5A, firstly, a substrate structure100having a conductive via pattern101and a dummy via pattern102is formed. In some embodiments, multiple via holes are formed in a substrate material100M using a removal process, and then materials for the conductive via pattern101and the dummy via pattern102are deposited within the via holes.

The above-mentioned removal process may include laser processing, a suitable etching process, or a combination thereof, but is not limited thereto. In an embodiment where the thickness of the substrate material100M is relatively thick, laser processing may be performed from both sides of the substrate material100M to form via holes with larger diameters at the top and bottom and smaller diameters in the middle. In this case, the resulted conductive via pattern101and dummy via pattern102have larger diameters at the top and bottom and smaller diameters at the middle, as shown inFIG.5A.

The process for depositing the conductive via pattern101may include, for example, physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), electroplating, other suitable processes, or a combination thereof, but not limited thereto. In some embodiments, the formation of the conductive via pattern101includes firstly depositing a seed layer in the via hole, and then depositing a conductive material on the seed layer. The material of the above-mentioned seed layer includes titanium (Ti), copper (Cu), other suitable conductive materials, or a combination thereof, but is not limited thereto. The aforementioned conductive materials include, for example, Cu, Sn, Ni, Ag, Au, Ti, Mo, W, other suitable conductive materials, or combinations thereof, but are not limited thereto.

The process for depositing the dummy via pattern102may include, for example, physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), electroplating, other suitable processes, or combinations thereof, but not limited to this. In some embodiments, the conductive via pattern101and the dummy via pattern102are formed simultaneously in a deposition process. In fact, the dummy via pattern102may also be formed in a different deposition process from the conductive via pattern101, and the dummy via pattern102may also include a different material from the conductive via pattern101.

Next, as shown inFIG.5A, a buffer layer104covering a top surface of the dummy via pattern102may be formed on the substrate structure100before forming the control unit. In this way, the material from the conductive via pattern101can be prevented from diffusing to the control unit110in the subsequent high temperature process. Moreover, a stress adjustment layer105may be formed on the substrate structure100and on the side opposite to the buffer layer104, wherein the thickness of the stress adjustment layer105is greater than that of the buffer layer104.

The process for depositing the buffer layer104may include, for example, physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), other suitable processes, or a combination thereof, but not limited to this. The process for depositing the stress adjustment layer105may be similar to that for depositing the buffer layer104, including, for example, physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), other suitable processes, or a combination thereof, but not limited to this.

Next, a control unit110electrically connected to the conductive via pattern101is formed. Referring toFIGS.5A and5B, firstly, a semiconductor layer112of the control unit110may be formed on the substrate structure100, for example, on the buffer layer104. In an embodiment where the control unit110is a transistor, the semiconductor layer112may include a channel layer. The formation of the semiconductor layer112may include a deposition process and a patterning process. The deposition process may include, for example, physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), other suitable processes, or combinations thereof, but is not limited thereto. The patterning process includes suitable lithography and/or etching processes. The lithography process may include resist coating (e.g., spin-on coating), soft baking, mask alignment, exposure, post-exposure bake, resist development, rinsing, drying (e.g., spin-drying and/or hard baking), other suitable lithography techniques, or a combination thereof, but not limited thereto. The etching process may include dry etching (for example, RIE etching), wet etching, other etching methods, or a combination thereof, but not limited thereto.

Next, the first insulating layer106may be formed on the semiconductor layer112. The process for forming the first insulating layer106may include, for example, physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), other suitable processes, or a combination thereof, but is not limited thereto. Next, a gate114and a source/drain116may be formed on the first insulating layer106. The process for forming the gate114and the source/drain116may include, for example, physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), electroplating, other suitable processes, or a combination thereof, but not limited to this. Between the formation of the gate114and the source/drain116, a second insulating layer108may be formed on the first insulating layer106and the gate114. In some embodiments, a portion of the first insulating layer106and the second insulating layer108are removed through an etching process to expose the semiconductor layer112, and then a conductive material for the source/drain116is deposited in openings left by removing the portion of the first insulating layer106and the second insulating layer108. The second insulating layer108may be formed by a deposition process similar to that of the first insulating layer106, which is not described in detail here for simplicity.

It should be understood that the present disclosure does not limit the formation sequence of each part of the control element110(such as the semiconductor layer112, the gate114, and the source/drain116) and each insulating layer (such as the first insulating layer106and the second insulating layer108). Those with ordinary skill in the art may adjust the formation sequence of the above layers according to the requirements of the manufacturing process. In addition, it should be understood that the present disclosure does not limit when to form the stress adjustment layer105. Those skilled in the art may form the stress adjustment layer105before, during, or after the formation of the control unit110according to the requirements of the process.

Referring next toFIG.5C, a first circuit structure120electrically connected to the conductive via pattern101may be formed, and the dummy via pattern102is electrically insulated from the first circuit structure120. Before, during, or after the formation of the first circuit structure120, a dielectric material may be deposited to form a first dielectric layer122surrounding the first circuit structure120. The process for depositing the first circuit structure120may include, for example, physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), electroplating, other suitable processes, or combinations thereof, but not limited to this. The process for forming the first dielectric layer122may include, for example, physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), other suitable processes, or a combination thereof, but not limited to this.

As shown inFIG.5C, in order to dispose an electronic unit130on the first circuit structure120, an alignment component124with a cavity facing away from the first circuit structure120may be formed on the first circuit structure120. The alignment component124may formed by forming an opening exposing the first circuit structure120on the first dielectric layer122and forming a conductive material in the opening. The formation of the alignment component124may include a deposition process and a patterning process.

The deposition process of the alignment component124may include, for example, physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), other suitable processes, or a combination thereof, but not limited thereto. The patterning process of the alignment component124includes suitable lithography and/or etching processes. The lithography process may include resist coating (e.g., spin-on coating), soft baking, mask alignment, exposure, post-exposure bake, resist development, rinsing, drying (e.g., spin-drying) and/or hard baking, other suitable lithography techniques, or a combination thereof, but not limited thereto. The etching process may include dry etching (for example, RIE etching), wet etching, other etching methods, or a combination thereof, but not limited thereto. In some embodiments, the resulted alignment component124may have a top portion that is higher than a top surface of the first dielectric layer122.

Referring toFIG.5D, the electronic unit130is disposed on the first circuit structure120, and the electronic unit130is electrically connected to the control unit110through the first circuit structure120. The disposition of the electronic unit130may include aligning any portion of the electronic unit130with the alignment component124. For example, in some embodiments, the electrical connection portion132of the electronic unit130is aligned with the alignment member124. Then, a heating step may be performed to bond the alignment component124and the electrical connection portion132through the bonding material134. After the electronic unit130is disposed, a protection layer140surrounding the electronic unit130may be formed. The process for forming the protection layer140may include, for example, physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), other suitable processes, or combinations thereof, but is not limited thereto.

In some embodiments, the control unit110is formed after the electronic unit130and the protection layer140are formed. More specifically, the protection layer140surrounding the electronic unit130may be formed in the electronic device where the control unit110has not been formed, and then the entire electronic device is flipped over and the control unit110is formed on the other side of the substrate structure100. In this way, an electronic device similar to that shown inFIG.3may be formed, wherein the substrate structure100is located between the electronic unit130and the control unit110. Through the above design, it is possible to prevent the control unit110from interfering with the electronic unit130during operation, but not limited thereto.

In some embodiments, before forming the control unit110, the first circuit structure120, and the electronic unit130, a conductive material160electrically connected to the conductive via pattern101is formed on the substrate structure100first. In this case, the protection layer140surrounding the electronic unit130may be formed first, and then the first circuit structure120is bonded to the conductive via pattern101of the substrate structure100with the conductive material160. In this way, an electronic device40including the conductive material160as shown inFIG.4may be formed. Through the above design, the process complexity of forming the first circuit structure120and the second circuit structure150on the upper and lower sides of the substrate structure100can be reduced, but not limited thereto.

Next, referring toFIG.5E, the formation of the electronic device may further include forming a second circuit structure150disposed on the substrate structure100and opposite to the first circuit structure120, and the dummy via pattern102is electrically insulated from the second circuit structure150. Before, during, or after the formation of the second circuit structure150, a dielectric material may be deposited to form a second dielectric layer152surrounding the second circuit structure150. The process for depositing the second circuit structure150may be similar to that of the first circuit structure120and is not further described here for simplicity. The process for depositing the second dielectric layer152may be similar to that of the first dielectric layer122, which is not further described here for simplicity.

As shown inFIG.5E, an alignment component154having a cavity facing away from the second circuit structure150may be formed on the second circuit structure150. The alignment component154may be formed by forming an opening exposing the second circuit structure150on the second dielectric layer152and depositing a conductive material in the opening. The process for depositing the conductive material of the alignment component154may be similar to that of the alignment component124, and is not otherwise described here for simplicity.

Referring next toFIG.5F, a bonding material156may be formed on the alignment component154. By forming the bonding material156, the resulted electronic device can be bonded to an external circuit through heating. In some embodiments, after the electronic device array including a plurality of electronic units130is formed, the electronic device array is diced with, for example, the cutting line L inFIG.5Fto form a plurality of electronic devices. Depending on the design requirements of each electronic device after dicing, each electronic unit130may be the same, similar, or different types of elements, which is not limited in the present disclosure.

It should be understood that the features in various embodiments of the present disclosure may be arbitrarily mixed and matched as long as they do not violate the spirit of the invention or conflict.

In summary, the present disclosure provides an electronic device and a method for forming the same. By forming a dummy via pattern in a substrate structure, the substrate structure can be prevented from warping due to uneven stress. Compared with conventional packaging structures of electronic devices, the electronic device disclosed in this disclosure can maintain the stability of the substrate structure without affecting the electrical requirements, and packaging structures formed by such electronic device may improve the functionality of the electronic unit through a via structure and a control unit. In addition, the formation of a dummy via structure electrically insulated from a circuit structure can be integrated into the fabrication process of a conductive via pattern. Therefore, the formation method of the present disclosure can manufacture electronic devices with better electrical and structural properties, or do not need to perform complicated manufacturing steps, thereby saving manufacturing costs.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.