Patent ID: 12211801

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

Other features and processes may also be included. For example, testing structures may be included to aid in the verification testing of the 3D packaging or 3DIC devices. The testing structures may include, for example, test pads formed in a redistribution layer or on a substrate that allows the testing of the 3D packaging or 3DIC, the use of probes and/or probe cards, and the like. The verification testing may be performed on intermediate structures as well as the final structure. Additionally, the structures and methods disclosed herein may be used in conjunction with testing methodologies that incorporate intermediate verification of known good dies to increase the yield and decrease costs.

FIGS.1through17illustrate cross-sectional views of various processing steps during formation of a chip package in accordance with some embodiments. A single package region is illustrated inFIGS.1through17, but multiple package regions may be packaged simultaneously, constituting a wafer level packaging process.

Referring toFIG.1, a carrier100having a de-bonding layer DB, a dielectric layer104and a seed layer SL1formed thereon is provided. The de-bonding layer DB is first formed on the carrier100, then the dielectric layer104is formed on the de-bonding layer DB. In some embodiments, the carrier100is a glass substrate, the de-bonding layer DB is a light-to-heat conversion (LTHC) release layer formed on the glass substrate, and the dielectric layer100is a photosensitive polybenzoxazole (PBO) layer. In alternative embodiments, the carrier100may be a ceramic substrate, the de-bonding layer DB may be a photo-curable release film whose viscosity is decreased by a subsequently performed photo-curing process or a thermal curable release film whose viscosity is decreased by a subsequently performed thermal-curing process, and the dielectric layer104may be made from other photosensitive or non-photosensitive dielectric materials.

After forming the dielectric layer104, a seed layer SL1is formed over the dielectric layer104. The seed layer SL1may be formed using, for example, physical vapor deposition (PVD) or the like. The PVD may be sputtering. In some embodiments, the seed layer SL1is a metal layer, which may be a single layer or a composite layer comprising sub-layers formed of different materials. In some embodiments, the seed layer SL1includes a titanium layer and a copper layer over the titanium layer.

Referring toFIG.2, after the carrier100having the de-bonding layer DB, the dielectric layer104and the seed layer SL1formed thereon is provided, a photoresist PR1is then formed and patterned on the seed layer SL1. The photoresist PR1may be formed by spin coating or the like and may be patterned by photolithography to form openings through the photoresist PR1such that portions of the seed layer SL1are exposed by the openings in the photoresist PR1.

A conductive material is then formed in the openings of the photoresist PR1and on the exposed portions of the seed layer SL1such that a plurality of conductive pillars TV are formed on the seed layer SL1. The conductive material may be formed by plating, such as electroplating, electroless plating, or the like. The conductive material may be a metal such as copper, titanium, tungsten, aluminum, or the like. The photoresist PR1is removed, and then portions of the seed layer SL1which are not covered by the conductive pillars TV are removed as shown inFIG.3. In some embodiments, the photoresist PR1may be removed by any acceptable process, such as by an ashing process, a stripping process, or the like. After the photoresist PR1is removed, the exposed portions of the seed layer SL1may then be removed by any acceptable process. In some embodiments, the seed layer SL1may be partially removed by etching process such as wet etching, dry etching, or the like.

Referring toFIG.4, semiconductor dies or devices110and120are then mounted on the dielectric layer104and may be surrounded by the conductive pillars TV. In some embodiments, the semiconductor dies110and120are adhered to the dielectric layer104through a die-attach film (DAF) (not shown). The semiconductor die110may be a logic die (e.g. central processing units, microcontrollers, etc.) while the semiconductor die120may be a memory die (e.g. high bandwidth memory (HBM) die, dynamic random access memory (DRAM) die, static random access memory (SRAM) die etc.). In some embodiment, the semiconductor die120may be a graphical processing unit (GPU) die. In some embodiments, semiconductor dies110and120may be power management dies (e.g., power management integrated circuit (PMIC) dies), radio frequency (RF) dies, sensor dies, micro-electro-mechanical-system (MEMS) dies, signal processing dies (e.g., digital signal processing (DSP) dies), front-end dies (e.g., analog front-end (AFE) dies), the like, or a combination thereof. The number of semiconductor dies provided on the dielectric layer is not limited to two. In some embodiments, only semiconductor die110or semiconductor die120is provided on dielectric layer104. In some alternative embodiments, other semiconductor dies may be provided on dielectric layer104in addition to semiconductor dies110and120.

The semiconductor dies110and120each includes an active surface having a plurality of die connectors114and124thereon (illustrated as only one for simplicity) respectively. In the semiconductor die110, a dielectric layer112laterally encapsulates the die connectors114, side surfaces of the die connectors114are in contact with the dielectric layer112, and top surfaces of the die connectors114are exposed through the dielectric layer112. In some alternative embodiments, the die connector114may be covered by and encapsulated in the dielectric layer112. In the semiconductor die120, the die connectors124are not encapsulated within a dielectric layer and therefore side surfaces and top surfaces of the die connectors124are exposed. In some embodiments, the semiconductor die120may include a dielectric layer that partially or fully encapsulates die connectors124. The conductive pillars TV, semiconductor die110and semiconductor die120may have different dimension along the vertical direction (i.e. different height).

After the semiconductor dies110and120are mounted on the dielectric layer104, an insulating encapsulant MC are formed to cover the dielectric layer104, the semiconductor dies110and120and the conductive pillars TV. The insulating encapsulant MC may be a molding compound, epoxy, or the like, and may be applied by a molding process (e.g. compression molding, transfer molding, or the like). The insulating encapsulant MC is applied to a level covering the top surfaces of the conductive pillars TV and the semiconductor dies110and120.

Referring toFIG.5, the insulating encapsulant MC are partially removed to expose the top surfaces of the conductive pillars TV, the die connectors114and the die connectors124. Preferably, after partially removing the insulating encapsulant MC, the top surface of the remaining insulating encapsulant MC is substantially leveled with the exposed top surfaces of the conductive pillars TV, the die connectors114and the die connectors124. The partial removal of the insulating encapsulant MC may be performed by a grinding process and/or a planarization process such as a chemical mechanical polishing (CMP) process.

Referring toFIGS.6through11, after partially removing the insulating encapsulant MC, a redistribution layer (RDL)130is formed over the semiconductor dies110and120, the conductive pillars TV and the insulating encapsulant MC. As illustrated inFIG.11, the RDL130includes a dielectric portion130a, a dielectric portion130b, conductive features138aand conductive features138b. Conductive features138aand conductive features138bare referred to as redistribution lines. In some embodiments, conductive features138aand conductive features138bare formed by a damascene process, described in detail below with reference toFIGS.6through9. In some embodiments, the RDL130is a fine pitch RDL having critical dimension less than 1.0 μm.

InFIG.6, dielectric portion130ais provided on the semiconductor dies110and120, the conductive pillars TV and the insulating encapsulant MC. The dielectric portion130ais then patterned to form via openings132exposing conductive pillars TV and semiconductor dies110and120. The via openings132may be formed to have a tapered shape in the cross-sectional view. The via openings132may be tapered to have a smaller diameter near the conductive pillar TV.

In detail, the dielectric portion130ais first evenly deposited, then a photolithography process is performed to pattern the dielectric portion130a, and then a curing process is performed on the patterned dielectric portion130a. In some embodiments, the even deposition of dielectric portion130aprovide a top surface that is substantially level or planar, which may be desirable in subsequent fabrication processes. In some embodiment, an additional planarization process such as CMP may be performed on the dielectric portion130abefore or after the patterning process. In some embodiments, the dielectric portion130ais formed of a polymer, which may be a photosensitive material such as PBO, polyimide, benzocyclobutene (BCB), or the like, that may be patterned using photolithography process. In some embodiments, the dielectric portion130amay be formed by any acceptable deposition process, such as spin coating, chemical vapor deposition (CVD), laminating, the like, or a combination thereof. After the dielectric portion130ais patterned and leaving behind a substantially level or planar top surface, the dielectric portion130amay have a thickness T1of between about 0.2 μm to about 5.0 μm.

Referring toFIG.7, a seed layer SL2is formed on the patterned dielectric portion130aand the exposed portions of the conductive pillar TV and the semiconductor dies110and120. That is, the seed layer SL2is formed on the dielectric portion130aconformal to the shape of the via openings132. The seed layer SL2may be formed using, for example, PVD or the like. The PVD may be sputtering. In some embodiments, the seed layer SL2is a metal layer, which may be a single layer or a composite layer comprising sub-layers formed of different materials. In some embodiments, the seed layer SL2includes a titanium layer and a copper layer over the titanium layer.

Referring toFIG.8, after the seed layer SL2is formed, a photoresist PR2is then formed over the seed layer SL2and patterned. The photoresist PR2is patterned to form a plurality of trenches above the via openings132which defines the conductive features formed therein in later processes. Details of the conductive features will be described below. The photoresist PR2may be patterned by photolithography to form plurality of trenches through the photoresist PR2such that portions of the seed layer SL2are exposed by the trenches in the photoresist PR2. The plurality of trenches includes openings134aformed directly over and exposing the via openings132, and trenches134bexposing seed layer SL2in communicating to the openings134a. As illustrated in the cross-sectional view ofFIG.8, the trenches134bare formed adjacent to the openings134a. In some embodiments, the openings134aand the trenches134bare not tapered.

Referring toFIG.9, after the photoresist PR2is formed and patterned, a conductive material is then formed in the openings134aand trenches134bof the photoresist PR2and on the exposed portions of the seed layer SL2such that conductive features138aand conductive features138bare formed on the seed layer SL2. The conductive material may be formed by plating, such as electroplating, electroless plating, or the like. The conductive material may be a metal such as copper, titanium, tungsten, aluminum, or the like. The photoresist PR2is removed, and then portions of the seed layer SL2which are not covered by the conductive features138aand138bare removed. In some embodiments, the photoresist PR2may be removed by any acceptable process, such as by an ashing process, a stripping process, or the like. After the photoresist PR2is removed, the exposed portion of the seed layer SL2may then be removed by any acceptable process. In some embodiments, the seed layer SL2may be partially removed by etching process such as wet etching, dry etching, or the like.

Still referring toFIG.9, the conductive features138arefer to the portion of conductive material embedded in the dielectric portion130a. That is, the conductive features138aare conductive vias which electrically connect the conductive pillar TV and the semiconductor dies110and120to the conductive features138bdisposed above the conductive features138a. The conductive features138brefer to conductive features that lies between the top surface of the dielectric portion130aand the top surface of the dielectric portion130b(as will be discussed later). In a top view (not shown), the conductive features138bmay be illustrated as fine pitched conductive traces that extends along the surface of the dielectric portion130afor increased routing density.

The conductive features138amay have a largest lateral width W1of between about 1.0 μm to about 5.0 μm. The conductive features138bmay have a lateral width (also referred to as line width) W2of between about 0.2 μm to about 0.9 μm. In some embodiments, the critical dimension of the conductive features138bis smaller than the critical dimension of the conductive features138a. In some embodiment, the critical dimension refers to the minimum lateral width of one conductive feature among plurality of conductive features. In some embodiments, the critical dimension of the conductive features138amay be between about 1.0 μm to about 5.0 μm. In some embodiments, the critical dimension of the conductive features138bmay be between about 0.2 μm to about 0.9 μm.

Referring toFIGS.10and11, a dielectric portion130bis formed over the dielectric portion130acovering the entirety of the conductive features138b. Due to the topography of conductive features138b, the dielectric portion130bformed thereon has a surface with low degree of planarization (DOP). That is, the dielectric portion130bmay have a plurality of protruding features corresponding to the conductive features138bdisposed thereunder. The dielectric portion130bwith a top surface of low DOP is shown inFIG.10. DOP is a measure of topography of a surface. Higher DOP indicates a surface is more planar, whereas low DOP indicates an uneven surface. Here, the DOP is evaluated using the equation

DOP=(1-tst)×100⁢%
wherein tsis the height of the protruding feature and t is the height of the feature underlying the protruding feature. The height of the protruding feature is measured from the base of the incline of the protruding feature vertically upwards to the peak level of the protruding feature. In some embodiment, the DOP of dielectric portion130bformed covering the conductive features138bmay be between about 48% and about 100%. In some embodiment, the dielectric portion130bis formed of a same material as the dielectric portion130a. In some embodiment, the dielectric portion130bmay be a polymer, which may be a photosensitive material such as PBO, polyimide, benzocyclobutene (BCB), or the like. In some embodiment, the dielectric portion130bmay be formed from a non-photosensitive material. The dielectric portion130bmay be formed by spin coating, lamination, chemical vapor deposition (CVD), the like, or a combination thereof.

InFIG.11, the uneven top surface of the dielectric portion130bis planarized to expose top surfaces of the conductive features138band achieve a high DOP of between about 90% to about 100%. That is, after planarizing the dielectric portion130b, the top surface of dielectric portion130band the top surface of the conductive features138bis substantially coplanar. The dielectric portion130bmay have a thickness T2after the planarization process. In some embodiments, thickness T2may be between about 0.2 μm to about 0.9 μm.

FIG.12illustrates the formation of additional RDL over the first RDL130. The additional RDL includes dielectric portion140, conductive features148aand conductive features148b. The materials used and the process of forming the additional RDL may be the same as the process of forming RDL130illustrated inFIGS.6through9.

In some embodiments, the additional RDL is a fine pitch RDL for high density routing having critical dimensions similar to the RDL130. In other words, the dielectric portion140may be similar to dielectric portion130a, the conductive features148amay be conductive vias that is similar to conductive features138a, and the conductive features148bmay be redistribution lines formed above conductive features148athat is similar to conductive features138b. Details of which are not repeated herein. In some embodiments, the materials used to form the additional RDL may be different from the RDL130. In an alternative embodiment, the formation of the additional RDL including the dielectric portion140, the conductive features148band148bshown inFIG.12is omitted. That is, only one fine pitch RDL130is formed. In some other embodiment, more than one additional fine pith RDL is formed on the RDL130. That is, the processes ofFIGS.6through11may be repeatedly performed on RDL130.

Due to the planarization of dielectric portion130band conductive features138aand138b, a surface with high DOP is provided for additional fine pitch RDL to be formed thereon. The high DOP allows the additional fine pitch RDL to be formed with larger process window, thus increasing the yield rate of fine pitch packaging process. That is, due to the dielectric portion130bhaving good surface planarity, the dielectric portion140may be formed with high DOP thereon. Subsequent patterning (i.e. photolithography) process performed thereon may have good resolution, and fine pitch redistribution layer may be achieved.

Referring toFIGS.13through14, after forming the additional redistribution layer with the dielectric portion140, conductive features148aand the conductive features148bas shown inFIG.12, a large scaled redistribution layer including dielectric portion150and conductive features154are formed thereon. The large scaled redistribution may have critical dimension between about 1 μm to about 50 μm.

InFIG.13, dielectric portion150is formed covering the entirety of conductive features148band patterned to expose some of the conductive features148b. In some embodiment, the dielectric portion150may be formed of a photosensitive dielectric material. The dielectric portion150may be formed with greater thickness and patterned with wider opening. Despite the topography of the conductive features148b, due to the relatively greater thickness of the dielectric portion150, a relatively high DOP may still be maintained. Moreover, because dielectric portion150does not correspond to a fine pitch redistribution layer, the patterning of dielectric portion150have a larger process window and planarization maybe omitted.

Referring toFIG.14, conductive features154are formed in the patterned openings of the dielectric portion150and on the top surface of the dielectric portion150. In some embodiment, a seed layer is first formed conformal to the patterned dielectric portion150, and photoresist is then formed on the seed layer and subsequently patterned to form openings exposing part of the seed layer. Conductive materials are then plated in the openings of the photoresist layer and on the exposed seed layer to form the conductive features154. Here, the conductive features154collectively refer to the conductive features which connects conductive feature148bto the top surface of the dielectric portion150and conductive features which is above the dielectric portion150which performs redistribution function. The process of forming conductive features154may be similar to the process of forming the conductive features138aand the conductive features138bdiscussed above with reference toFIGS.7to9.

InFIG.15, a dielectric portion160, under-ball metallurgies (UBM)162and conductive connectors164are formed. In detail, the dielectric portion160is formed on the dielectric portion150and covering the conductive features154. In some embodiments, the dielectric portion160is a photosensitive dielectric material. The dielectric portion160is then patterned to form openings exposing conductive features154. Conductive material is then plated in the openings to form the UBMs162. The process of forming UBMs162may be similar to the process of forming the conductive features138aand the conductive features138bdiscussed above with reference toFIGS.7to9.

After forming UBMs162, conductive connectors164are then formed on the UBMs162. In some embodiments, the conductive connectors164may be ball grid array (BGA) connectors, solder balls, metal pillars, controlled collapse chip connection (C4) bumps, micro bumps, or the like. The conductive connectors164may include conductive materials such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, or the like, or the combination thereof. In some embodiments, the conductive connectors may be formed by initially forming a layer of solder on the UBMs162followed by a reflow process. After forming the conductive connectors164, a package200with front side redistribution structure is accomplished.

Next, referring toFIG.16, after the conductive connectors164are formed, the dielectric layer104is de-bonded from the de-bonding layer DB such that the dielectric layer104is separated or delaminated from the de-bonding layer DB and the carrier100. In some embodiments, the de-bonding layer DB (e.g., the LTHC release layer) may be irradiated by an UV laser or other suitable photo curing process such that the dielectric layer104is peeled from the de-bonding layer DB and the carrier100. In some alternative embodiments, the de-bonding layer DB may be treated by an acceptable thermal curing process such that the dielectric layer104is peeled from the de-bonding layer DB and the carrier100.

After the de-bonding process, a plurality of packages200in wafer form is flipped and placed on a carrier tape170. The dielectric layer104is then patterned to form opening172exposing the seed layer SL1on the conductive pillar TV. In some embodiments, the dielectric layer104may be a photosensitive dielectric material and the patterning is performed by photolithography process.

Referring toFIG.17, a bonding of package300to package200is illustrated, thus forming a Package-on-Package (POP) structure. The bonding is performed through connectors174, which physically and electrically connects conductive pillars TV to metal pads302in the overlying package300. Connectors174connects to the conductive pillar TV through opening172. In some embodiments, package300includes semiconductor dies which may be memory dies such as SRAM dies, DRAM dies, or the like.

InFIG.18, an underfill UF is formed in the gap between packages200and the overlying packages300, and is cured. The underfill UF may be a polymer, an epoxy, a resin or the like. After the underfill UF is disposed and cured, a singulation process is performed to separate the plurality of packages200and packages300in wafer form into a plurality of individual packages400each having at least one package200and at least one package300.

FIGS.19through29illustrate cross-sectional views of various processing steps during formation of a redistribution structure in accordance with some other embodiments. A single package region is illustrated inFIGS.19through29, but multiple package regions may be packaged simultaneously, constituting a wafer level packaging process.

Referring toFIGS.19through24, a RDL230is formed over the semiconductor dies110and120, the conductive pillars TV and the insulating encapsulant MC. As illustrated inFIG.24, the RDL230includes a dielectric portion230a, a dielectric portion230b, conductive features238aand conductive features238b. Conductive features238aand conductive features238bare referred to as redistribution lines. In some embodiments, conductive features238aand conductive features238bare formed by a damascene process, described in detail below. In some embodiments, the RDL230is a fine pitch RDL having critical dimension less than 1.0 μm.

Referring toFIG.19, a package structure similar toFIG.5is provided. InFIG.19, a patterned dielectric portion230ais provided over the semiconductor dies110and120, the conductive pillars TV and the insulating encapsulant MC. In some embodiments, the dielectric portion230ais formed with a thickness T1similar to the dielectric portion130a. The dielectric portion230ais patterned to form openings243exposing the conductive pillars TV, the semiconductor dies110and the semiconductor dies120. The formation and patterning of dielectric portion230amay be similar to dielectric portion130aas discussed above with reference toFIG.6. Details of which are not repeated.

Referring toFIG.20, a dielectric portion230bis deposited into the openings234and over the dielectric portion230a. The dielectric portion230bis formed of a positive tone photosensitive dielectric material such as PBO, polyimide, BCB, phenolic, acrylate, phenolic-epoxy hybrid, or the like. The dielectric portion230bmay be formed by any acceptable deposition process, such as spin coating, chemical vapor deposition (CVD), laminating, the like, or a combination thereof. The use of positive tone photosensitive dielectric material allows openings with smaller dimension to be formed in subsequent patterning (i.e. exposure and developing) processes. In detail, a patterned photomask600is used to expose the dielectric portion230bto a light source (e.g. UV light source). The photomask600may have opaque portion which blocks and patterned transparent portions which allows light to pass through, as seen in arrows ofFIG.20.

After the exposure, the exposed portions of the dielectric portion230bis chemically altered and may be removed by use of developing solution. After removal of exposed portion, a patterned dielectric portion230bwith openings236aand openings236bare formed, as shown inFIG.21. Openings236aexpose the portions of dielectric portion where opening234are formed, thus exposing the conductive pillar TV and the semiconductor die110and the semiconductor die120. Openings236bexposes the portions of the dielectric portion230a. In some embodiments, openings236bcorrespond to trenches that extends along the top surface of the dielectric portion230a.

InFIG.22, a seed layer SL2is formed on the patterned dielectric portion230a, exposed portions of the dielectric portion230aand the exposed portions of the conductive pillar TV and the semiconductor dies110and120. That is, the seed layer SL2is formed on the dielectric portion230band conformal to the shape of the openings236aand openings236b. The seed layer SL2may be formed using, for example PVD or the like. The PVD may be sputtering. In some embodiments, the seed layer SL2is a metal layer, which may be a single layer or a composite layer comprising sub-layers formed of different materials. In some embodiments, the seed layer SL2includes a titanium layer and a copper layer over the titanium layer.

Referring toFIG.23, a conductive material234is then formed over the seed layer filling the openings236aand the openings236b. In some embodiments, the conductive material may be formed by plating, such as electroplating, electroless plating, or the like. The conductive material may be a metal such as copper, titanium, tungsten, aluminum, or the like. The conductive material is formed to a level that is above the top surface of the seed layer SL2disposed thereunder.

Referring toFIG.24, the conductive material234, seed layer SL2and dielectric portion230bare partially removed and planarized to define the conductive features238aand conductive features238b. That is, the excess portion of the conductive materials234and the seed layer SL2are removed. The partial removal and planarization process removes conductive material234and seed layer SL2that are disposed above the top surface of the dielectric portion230b. Accordingly, any conductive material234and/or seed layer SL2that electrically connects conductive material disposed in any two adjacent openings236aand openings236bare removed, leaving behind a substantially leveled top surface. In some embodiments, the partial removal and planarization of the conductive material234, seed layer SL2and dielectric portion230bmay be performed by a grinding process and/or a planarization process such as a chemical mechanical polishing (CMP) process. In some embodiments, the thickness T3of the dielectric portion230bafter the planarization process may between about 0.2 μm to about 0.9 μm.

Still referring toFIG.24, the conductive features238arefer to the portion of conductive material embedded in the dielectric portion230a. That is, the conductive features238aare conductive vias which electrically connect the conductive pillar TV and the semiconductor dies110and120to the conductive features238bdisposed above the conductive features238a. The conductive features238brefer to conductive features that is embedded in the dielectric portion230b. In a top view (not shown), the conductive features238bmay be illustrated as fine pitched conductive traces that extends along the surface of the dielectric portion230afor increased routing density.

In some embodiments, the conductive features238amay have dimensions similar to the conductive features138adiscussed above with reference toFIG.9. In some embodiments, the conductive features238bmay have dimensions similar to the conductive features138bdiscussed above with reference toFIG.9. In some embodiments, the critical dimension of the conductive features238bis smaller than the critical dimension of the conductive features238a. In some embodiments, the critical dimension of the conductive features238amay be between about 1.0 μm to about 5.0 μm. In some embodiments, the critical dimension of the conductive features238bmay be between about 0.2 μm to about 0.9 μm.

FIGS.25through26illustrates the formation of additional RDL240over the first RDL230. The RDL240includes dielectric portion240a, dielectric portion240b, conductive features248aand conductive features248b. The materials used and the process of forming the RDL240may be the same as the process of forming RDL230illustrated inFIGS.19through24.

In some embodiments, the RDL240is a fine pitch RDL for high density routing having critical dimensions similar to the RDL230. In other words, the dielectric portion240amay be similar to the dielectric portion230a, the dielectric portion240bmay be similar to the dielectric portion, the conductive features248amay be conductive vias that is similar to conductive features238a, and the conductive features248bmay be redistribution lines formed above conductive features248athat is similar to conductive features238b. In an alternative embodiment, the formation of the RDL240is omitted. That is, only one fine pitch RDL230is formed. In some other embodiment, more than one additional fine pith RDL240may be formed on the RDL230. That is, the processes ofFIGS.19through24may be repeatedly performed on RDL230.

Due to the removal of excess conductive material234and planarization to form the conductive features238aand conductive features238bdiscussed above with reference toFIG.24, a surface with high DOP is provided for additional fine pitch RDL240to be formed thereon. The high DOP allows the RDL240to be formed with larger process window, thus increasing the yield rate of fine pitch packaging process. That is, due to the top surface of RDL230having good surface planarity, the dielectric portion240aand dielectric portion240bmay be formed with high DOP thereon. Subsequent patterning (i.e. photolithography) process performed thereon may have good resolution, and fine pitch RDL240may be achieved.

Referring toFIGS.27through29, after the RDL240is formed, a large scaled RDL and conductive connectors164are formed. The large scaled RDL includes dielectric portion250, dielectric portion160, conductive features154and UBM162. InFIG.27, a dielectric portion250is formed over the RDL240. The top surface of the dielectric portion250may be substantially level due to the removal planarization of RDL240. In some embodiments, the dielectric portion250is formed of a photosensitive dielectric material similar to the dielectric portion150. The dielectric portion250may then be patterned to form opening exposing some conductive features248b. InFIG.28, conductive features154are formed in the patterned opening of dielectric portions250and on the top surface of the dielectric portion250. In some embodiment, the conductive features154are formed with a seed layer as discussed above with reference toFIG.14. Here, the conductive features154collectively refer to the conductive features which connects conductive feature248bto the top surface of the dielectric portion250and conductive features which is above the dielectric portion250which performs redistribution function.

InFIG.29, a dielectric portion160, an under-ball metallurgy (UBM)162and conductive connector164are formed with the similar material and method as discussed above with reference toFIG.15. The details of which are not repeated herein. Although not illustrated, after the formation of conductive connector164, the package may be de-bonded from the carrier100and flipped over for subsequent bonding to a package300and singulation process, similar to the process described with reference toFIGS.16to18.

FIGS.30through35illustrate cross-sectional views of various processing steps during formation of a redistribution structure in accordance with some other embodiments. A single package region is illustrated inFIGS.30through35, but multiple package regions may be packaged simultaneously, constituting a wafer level packaging process.

Referring toFIGS.30through33, an RDL is formed over the semiconductor dies110and120, the conductive pillars TV and the insulating encapsulant MC. As illustrated inFIG.33, the RDL includes a dielectric layer330, conductive features338aand conductive features338b. Conductive features338aand conductive features338bare referred to as redistribution lines. In some embodiments, conductive features338aand conductive features338bare formed by a damascene process, more particularly, a dual damascene process, described in greater detail below. In some embodiments, the RDL is a fine pitch RDL having critical dimension less than 1.0 μm.

Referring toFIG.30, a package structure similar toFIG.5is provided. InFIG.30, a dielectric layer330is provided over the semiconductor dies110and120, the conductive pillars TV and the insulating encapsulant MC. The dielectric layer330is formed of a positive tone photosensitive dielectric material such as PBO, polyimide, BCB, phenolic, acrylate, phenolic-epoxy hybrid, or the like. The dielectric layer330may be formed by any acceptable deposition process, such as spin coating, chemical vapor deposition (CVD), laminating, the like, or a combination thereof. The use of positive tone photosensitive dielectric material allows openings with smaller dimension to be formed in subsequent patterning (i.e. exposure and developing) processes.

Still referring toFIG.30, after forming the dielectric layer330, the dielectric layer330is patterned by photolithography using a patterned photomask600. The photomask600may have opaque portion which blocks and patterned transparent portions which allows light to pass through, as seen in arrows ofFIG.30. During the exposure process including one or more exposure steps, two regions E1and E2of the dielectric layer are exposed to the patterned light. Referring toFIG.30, region E1refers to the region with dashed lines which extends from the top surface of the dielectric layer330through to the bottom surface of the dielectric layer330. Region E2refers to the region with dashed lines which extends from the top surface of the dielectric layer330into dielectric layer330but not through to the bottom surface of the dielectric layer. Both regions correspond to individual tapered openings in the subsequent removal of the regions E1and regions E2.

In some embodiments, when the exposure process is a two-step process, regions E1may first be exposed to patterned light using a first photomask before exposing region E2using a second photomask or vice versa. In some embodiment, the exposure to regions E1and regions E2may be performed simultaneously in a single step using a half-tone photomask. After the exposure, the exposed portions of the dielectric layer330is chemically altered and may be removed by use of developing solution. After removal of exposed portions, a patterned dielectric layer330with openings336aand openings336bare formed, as shown inFIG.31. Openings336aare vias exposing the conductive pillar TV, the semiconductor die110and the semiconductor die120. Openings336bare recesses formed in the dielectric layer330. In some embodiments, openings336bcorrespond to trenches that extends along the dielectric layer330.

Referring toFIG.32, a seed layer is formed on the patterned dielectric layer330, the exposed portions of the conductive pillar TV and the semiconductor dies110and120. That is, a seed layer is formed on the dielectric portion230band conformal to the shape of the openings336aand openings336b. In some embodiments, the seed layer is formed with the material and method similar to the seed layer SL2discussed above with reference toFIG.22. After forming seed layer, a conductive material334is then formed over the seed layer filling the openings336aand the openings336bto a level that is above the top surface of the seed layer disposed thereunder. In some embodiments, the conductive material334is formed with the material and method similar to the conductive material234discussed above with reference toFIG.23.

Referring toFIG.33, the conductive material334, seed layer and dielectric layer330are partially removed and planarized to define the conductive features338aand conductive features338b. That is, the excess portion of the conductive materials334and the seed layer are removed. The partial removal and planarization process removes conductive material334and seed layer that are disposed above the top surface of the dielectric layer330similar to the removal of conductive material234discussed above with reference toFIG.24. Accordingly, a substantially leveled top surface is formed. In some embodiments, the thickness T4of the dielectric layer330after the planarization process may be between about 1.2 μm to about 5.9 μm.

Still referring toFIG.33, the conductive features338arefer to the portion of conductive material extending from the bottom surface of the dielectric layer330to the level of the bottom surface of opening336b(shown inFIG.31). That is, the conductive features338aare conductive vias which electrically connect the conductive pillar TV and the semiconductor dies110and120to the conductive features338bdisposed above the conductive features338a. The conductive features338brefer to conductive features that formed in openings corresponding to region E2. In a top view (not shown), the conductive features338bmay be illustrated as fine pitched conductive traces that extends along the surface of the dielectric layer330for increased routing density.

In some embodiments, the conductive features338amay have dimensions similar to the conductive features138adiscussed above with reference toFIG.9. In some embodiments, the conductive features338bmay have dimensions similar to the conductive features138bdiscussed above with reference toFIG.9. In some embodiments, the critical dimension of the conductive features338bis smaller than the critical dimension of the conductive features338a. In some embodiments, the critical dimension of the conductive features338amay be between about 1.0 μm to about 5.0 μm. In some embodiments, the critical dimension of the conductive features338bmay be between about 0.2 μm to about 0.9 μm.

FIG.34illustrates the formation of additional RDL similar to the RDL discussed with reference toFIGS.30through32. The additional RDL includes dielectric layer340and conductive material344. The materials used and the process of forming the dielectric layer and conductive material344may be the same as the process illustrated inFIGS.30through32.

Referring toFIG.35, excess portion of the conductive material344is removed and planarization is performed on the dielectric layer340. After planarization process, dielectric layer340include conductive features embedded therein. The conductive features embedded in dielectric layer340correspond to fine pitch redistribution lines similar to that of the conductive features338aand conductive features338b. In an alternative embodiment, formation of additional RDL including the dielectric layer340and the conductive features embedded therein may be omitted. That is, only one fine pitch RDL is formed. In some other embodiment, more than one additional fine pith RDL may be formed. That is, the processes ofFIGS.30through33may be repeatedly performed to form multiple fine pitch RDLs.

Still referring toFIG.35, after the fine pitch RDL is formed, a large scaled RDL and conductive connectors164are formed. The large scaled RDL includes dielectric portion250, dielectric portion160, conductive features154and UBM162. The large scaled RDL may be formed by materials and methods as discussed above with reference toFIGS.27through29. The details of which are not repeated herein. Although not illustrated, after the formation of conductive connector164, the package may be de-bonded from the carrier100and flipped over for subsequent bonding to a package300and singulation process, similar to the process described with reference toFIGS.16to18.

In the above-mentioned embodiments, a chip package having a fine pitch RDL for high routing density is provided. To reduce critical dimension of the fine pitch RDL, a surface with high degree of planarization (DOP) is provided for the formation every fine-pitch RDL. By providing high DOP surface, the process window of manufacturing fine pitch RDL may be increased, thereby increasing the yield rate of the package structures having at least one fine pitch RDL. Furthermore, the conductive features in the fine-pitch RDLs are formed by using the damascene (e.g. single damascene or dual damascene) process, allowing fine pitch to be achieved. Moreover, openings (e.g. trenches) defining the conductive features having fine line width or fine line spacing may be patterned on high resolution photoresists or positive-tone photosensitive dielectric layer to effectively decrease the critical dimension.

In accordance with some embodiments of the present disclosure, a chip package including a semiconductor die, an insulating encapsulant encapsulating the semiconductor die; and a first redistribution layer over the semiconductor die and the encapsulant is provided. The first redistribution includes a first redistribution portion and a second redistribution portion in contact with the first redistribution portion, the first redistribution portion being between the second redistribution portion and the semiconductor die, wherein the first redistribution portion includes a first dielectric portion and a plurality of first conductive features embedded in the first dielectric portion, the plurality of first conductive features electrically connecting the semiconductor die to the second redistribution portion, the second redistribution portion includes a second dielectric portion and a plurality of second conductive features embedded in the second dielectric portion and connected to the first conductive features, a top surface of the second dielectric portion is substantially level with top surfaces of the plurality of second conductive features.

In accordance with alternative embodiments of the present disclosure, a method for forming a chip package is provided. The method includes the following steps. Laterally encapsulating a semiconductor die with an insulating encapsulant; forming a first dielectric portion over the insulating encapsulant and the semiconductor die, the first dielectric portion comprising a plurality of via holes, forming a second dielectric portion over the first dielectric portion; and forming a plurality of first conductive features in the plurality of via holes and a plurality of second conductive features connected to the plurality of first conductive features, wherein the plurality of second conductive features are embedded in the second dielectric portion, and a top surface of the second dielectric portion is substantially level with top surfaces of the plurality of second conductive features.

In accordance with yet alternative embodiments of the present disclosure, another method of forming a chip package is provided. The method includes the following steps. Laterally encapsulating a semiconductor die with an insulating encapsulant, forming a redistribution layer, wherein forming the redistribution layer includes: forming a first dielectric layer over the insulating encapsulant and the semiconductor die, the first dielectric layer comprising a plurality of via holes and a plurality of trenches above the via holes, and forming a plurality of first conductive features in the via holes and a plurality of second conductive features in the trenches, wherein a top surface of the first dielectric layer is substantially level with top surfaces of the plurality of second conductive features.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.