Patent ID: 12216941

DETAILED DESCRIPTION

Embodiments will now be explained with reference to the accompanying drawings. The present invention is not limited to the embodiments. The drawings are schematic or conceptual. In the specification and the drawings, identical elements are denoted by like reference characters.

A memory system according to the present embodiment includes a memory area configured to store data therein. A controller controls writing data to be input to and/or reading data to be output from the memory area. A first connector inputs the data to be input to the memory area from a host and/or outputs the data to be output from the memory area to the host, and is removable from the host. A first holding part is electrically disconnected from the memory area and the first connector and including a first port, and holds identification information used to authenticate an authority to initialize the memory area. The first port outputs the identification information to the host when receiving, from the host, an initialization command that instructs initialization of at least the part of the memory area. The controller includes a second port and an authentication part. The second port receives the initialization command from the host and receives the identification information via the first port. The authentication part executes initialization of at least the part of the memory area based on the initialization command and the identification information received at the second port.

First Embodiment

FIG.1is a block diagram illustrating an example of the configuration of an information processing system1according to a first embodiment.

The information processing system1includes a memory system2and a host3. The memory system2and the host3transmit and receive data through an interface4such as NVMe (PCIe)™.

The memory system2is a storage having a data protection function incorporated therein. The memory system2is, for example, an SSD (Solid State Drive) or an HDD (Hard Disk Drive). For example, a NAND flash memory may be used in the memory system2. The data protection function is a TCG (Trusted Computing Group)-compliant protection function. Examples of the data protection function include a protection function by means of encryption to encrypt and store data, a protection function by means of locking to prohibit anyone other than certain individuals from accessing the area assigned to the certain individuals, and a protection function by means of both the encryption and locking.

The host3is a processing device external to the memory system2and is connectable to the memory system2and removable from the memory system2. For example, the host3is a server or a PC (personal computer) that uses the memory system2as a data storage. For another example, the host3is a dedicated device, to be used by a manufacturer of the memory system2, a manufacturer of the information processing system1, or a user, to perform several settings for the memory system2or to issue several commands to the memory system2. In the TCG standards, as one of the commands issued from the host, a revert command is defined. The revert command is a command that perform an operation of a revert to initializes the memory area. The initialization of the memory area is to restore the memory area to a state of pre-shipment, i.e., a state before shipping to a market from a factory, the state being no user data in an user area. In this state, a certain data, such as management data may be existing in a management area of the memory area. Thus, the initialization of at least the part of the memory area is performed.

The term, “revert command” can be referred as an initialization command. In the present embodiments, the host initializes the memory area21of the memory system by issuing the revert command to the memory system.

Also, the term “revert” refers to initializing the memory area21. In the following descriptions, initialization of the memory area21is sometimes referred to as “revert”. In either case, the host3is connectable to the memory system2and removable from the memory system2. The host3may be connected to an external network10to be capable of communicating with the external network10. For example, the host3transmits data received from the external network10to the memory system2through connectors C31and C21and the interface4. The host3receives data in the memory system2through the connectors C21and C31and the interface4, and transmits the data to the external network10. That is, the interface4is a so-called “in-band interface”.

The memory system2includes the memory area21, a memory controller22, the connector C21, connectors C22to C24, and a PIN holding part25.

The memory area21is an area configured to store therein data that can be used by a user, for example. Upon receiving a read command or a write command from the outside such as the host2, the memory controller22reads data from the memory area21, or writes data to the memory area21.

The PIN holding part25is, for example, a memory. The PIN holding part25includes a port Sinout. In the embodiment, the PIN holding part25holds identification information C_PIN as data used to authenticate a PSID (Physical Presence Security Identifier) authority. The PSID authority refers to an authority to initialize the memory area21. That is, when the PSID authority is given, it is possible to execute initializing of the memory area21. Usually, an identification information C_PIN is a form of a string of characters which is printed on a label attached to a package of the memory system2, or is printed on a housing of the memory system2or the like and uniquely given to each memory system. The PIN holding part25of this embodiment outputs the identification information C_PIN as data held or stored therein from the port Sinout. During an operation other than reverting, normally the PIN holding part25is electrically disconnected from constituent elements connected to the external network10, such as the memory area21, the connectors C21and C31, the interface4, and a data controller31. Here, the operation other than reverting is normal operations other than the reverting, i.e. other than the initialization of the memory area. Such the operations may include reading data to be output from the memory area21and writing data to be input to the memory area21.

The port Sinout is a serial bus input-output port. The port Sinout is electrically connected to the connector C22to be described later. The port Sinout receives a revert command from the host3. The port Sinout transmits the identification information C_PIN from the PIN holding part only when receiving the revert command. The port Sinout is electrically disconnected from the constituent elements connected to the external network10, such as the memory area21, the connectors C21and C31, the interface4, and the data controller31.

The memory controller22is a controller configured to control the memory area21. The memory controller22may be constituted by a processor such as a single CPU (Central Processing Unit) or a plurality of CPUs. When the PSID authority is given, the memory controller22can collectively invalidate the data in the memory area21in its entirety. The memory controller22can initialize the memory area21by invalidating the data in the memory area21in its entirety.

The memory controller22includes a hash holding part26, a PIN authentication part27, a port Sin, and a port Sclk2.

The hash holding part26is, for example, a memory. The hash holding part26holds a hash value of the identification information C_PIN. This hash value is obtained by converting the identification information C_PIN in advance by using a hash function, and is used to authenticate the identification information C_PIN.

The PIN authentication part27is, for example, a processor such as a CPU. The PIN authentication part27determines whether to execute reverting based on a revert command and the identification information C_PIN. The revert command is a command that instructs initialization of the memory area21.

The port Sin is a serial bus input port used for receiving a revert command. The port Sin is electrically connected to the connector C23to be described later. The port Sin receives a revert command from the host3. The port Sin receives the identification information C_PIN from the port Sinout.

At the time of executing reverting, the port Sin is connected to a port Sout and the port Sinout through a connection part33of the host3. That is, the port Sinout, the port Sin, and the port Sout short-circuit to each other at the time of executing reverting.

The connectors C21to C24are provided for external connection. The connectors C21to C24are removably connected to connectors C31to C34provided on the host3, respectively.

The connector C21is electrically connected to the memory area21. The connector C21is removably connected to the connector C31. The connector C21is connected to the connector C31by the interface4such as NVMe® (PCIe®) to be capable of communicating with the connector31. The connector C21is electrically disconnected from the PIN holding part25and the port Sinout.

The connector C22is electrically connected to the host3via the port Sinout. The connector C22is removably connected to the connector C32. The connector C22is used to receive a revert command and other data, and transmit the identification information C_PIN for the PSID authority. The connector C22is connected to the connector C32by a serial communication interface5to be capable of communicating with the connector C32. The connector C22is electrically disconnected from the connector C21. The interface5is a so-called “out-of-band interface”.

According to such configuration, the identification information C_PIN is not transmitted to the connector C21and the interface4. So a leakage of the identification information C_PIN to outside of the memory system2is prevented.

The connector C23is electrically connected to the port Sin. The connector C23is removably connected to the host3via the connector C33. The connector C23is used to receive a revert command, the identification information C_PIN for the PSID authority, and other data. The connector C23is connected to the connector C33by a serial communication interface6to be capable of communicating with the connector C33. The connector C23is electrically disconnected from the connector C21. The interface6is a so-called “out-of-band interface”.

The connector C24is connected to a port Sclk2. The port Sclk2is a serial bus input port to be used to receive a clock signal for synchronization between the memory system2and the host3. The connector C24is used to receive the clock signal. The connector C24is connected to the connector C34by a serial communication interface7to be capable of communicating with the connector C34. The connector C24is electrically disconnected from the connectors C21to C23, the port Sinout, and the port Sin.

The host3includes the data controller31, a command controller32, the connectors C31to C34, and the connection part33. The host3may be constituted by a processor such as a single CPU or a plurality of CPUs.

The data controller31is a controller configured to transmit and receive data between the external network10and the memory system2. The data controller31is constituted by, for example, a processor such as a CPU and a memory. The data controller31transmits data received from the external network10to the memory system2. The data controller31transmits data received from the memory system2to the external network10.

The command controller32is a controller configured to output a revert command to the memory system2. The command controller32is constituted by, for example, a processor such as a CPU and a memory. The command controller32controls a revert-command holding part35to transmit a revert command from the revert-command holding part35to the memory system2. The command controller32also transmits a clock signal to the memory system2through a port Sclk3and the connector C34.

The connector C31is electrically connected to the data controller31. The connector C31is removably connected to the connector C21. The connector C31is electrically disconnected from the connectors C32and C33and the port Sout.

The connector C32is electrically connected to the port Sout. The connector C32is removably connected to the connector C22of the memory system2. The connector C32is used to output a revert command. The connector C32is used to input the identification information C_PIN. The connector C32is electrically disconnected from the connector C31.

The connector C33is electrically connected to the port Sout. The connector C33is removably connected to the connector C23of the memory system2. The connector C33is used to output a revert command. The connector C33is used to output the identification information C_PIN. The connector C33is electrically disconnected from the connector C31.

The connector C34is connected to the port Sclk3. The connector C34is removably connected to the connector C24. The port Sclk3is a serial bus output port to be used to transmit a clock signal. The connector C34is electrically disconnected from the connectors C31to C33and the port Sout.

The connection part33is electrically connected to the connector C32, the connector C33, and the port Sout. The connection part33electrically short-circuits the connector C32, the connector C33, and the port Sout when reverting of the memory area21is executed. The connection part33outputs a revert command simultaneously to both the connectors C32and C33. Since the connection part33is electrically short-circuited to the connectors C32and C33, the connectors C22and C23of the memory system2are also short-circuited through the connectors C32and C33. With this configuration, the connection part33inputs the same revert command simultaneously to the connectors C22and C23. The connection part33inputs the identification information C_PIN output from the connector C22to the connector C23.

The command controller32includes the revert-command holding part35, the port Sout, and the port Sclk3.

The revert-command holding part35is, for example, a memory. The revert-command holding part35holds a revert command that is a command to be output to revert the memory area21.

The port Sout is a serial bus output port. The port Sout is used to output a revert command. The port Sout is electrically connected to the connectors C32and C33to be described later. The port Sout is electrically disconnected from the constituent elements connected to the external network10.

FIG.2is a diagram illustrating the configuration of the connection part33according to the first embodiment.

The connection part33includes a switch SW1and a switch SW2. Each of the switches SW1and SW2is constituted by, for example, a transistor. The switch SW1is connected between the port Sout and the connector C32. The switch SW2is connected between the port Sout and the connector C33. The switches SW1and SW2are electrically connected to the command controller32. The switches SW1and SW2are controlled simultaneously by the command controller32. The switches SW1and SW2enter a conductive state immediately before a revert command is issued. The switches SW1and SW2enter a non-conductive state after reverting is executed.

Next, operations of the information processing system1are described.

FIG.3is a sequence diagram illustrating an example of the operation of the information processing system1according to the first embodiment.

When a user requests reverting on the host3, the command controller32of the host3outputs a revert command from the port Sout. When reverting is requested on the host3, the command controller32of the host3brings the switches SW into a conductive state. With this operation, the port Sinout and the port Sin of the memory system2are short-circuited.

A revert command is input to the port Sin and the port Sinout of memory system2. Since the port Sin and the port Sinout of the memory system2are short-circuited, the revert command is input almost simultaneously to both the port Sin and the port Sinout.

Upon receiving the revert command at the port Sin, the memory controller22of the memory system2is on standby to receive the identification information C_PIN.

In contrast, upon receiving the revert command at the port Sinout, the PIN holding part25of the memory system2issues the identification information C_PIN on the PSID authority. The identification information C_PIN is output from the port Sinout and input to the port Sin.

Upon receiving the identification information C_PIN at the port Sin, the PIN authentication part27of the memory controller22converts the identification information C_PIN received from the port Sin into a hash value by using a hash function. Further, the PIN authentication part27compares the hash value obtained by converting the identification information C_PIN with the hash value held in advance in the hash holding part26. The identification information C_PIN can be safely authenticated by using the hash values.

When the hash value obtained from the identification information C_PIN matches the hash value held in the hash holding part26, the PIN authentication part27executes reverting of the memory area21.

When the hash value obtained from the identification information C_PIN does not match the hash value held in the hash holding part26, the IN authentication part27does not execute reverting of the memory area21.

In the information processing system1in the first embodiment, when reverting is not being executed, the identification information C_PIN is not leaked from the interface4to the external network10. The reason for this is that the PIN holding part25having the identification information C_PIN stored therein is electrically disconnected from the interface4configured to transmit and receive data, such as NVMe® (PCIe®).

In the first embodiment, the identification information C_PIN on the PSID authority is held in the memory controller22of the memory system2. The information processing system1in the first embodiment can initialize the memory area by using the identification information C_PIN on the PSID authority without optically reading identification information to obtain the PSID authority.

Meanwhile, a revert command is needed to execute reverting, and reverting is not executed by solely short-circuiting the port Sinout and the port Sin. Accordingly, the information processing system1can prevent the memory area from being accidentally initialized.

In the memory system2in the first embodiment, the PIN holding part25electrically disconnected from the external network10has the identification information C_PIN stored therein, so that the identification information C_PIN can be prevented from being leaked to the external network10.

Further Embodiment

FIG.4is a diagram illustrating the configuration of the connection part33according to a further embodiment of the first embodiment. The connection part33according to the further embodiment is a wiring configured to electrically connect the port Sout and the connectors C32and C33. The connection part33electrically short-circuits the port Sin and the port Sinout.

The further embodiment can achieve effects identical to those of the first embodiment.

Second Embodiment

FIG.5is a block diagram illustrating an example of the configuration of the information processing system1according to a second embodiment. The information processing system1according to the second embodiment includes the memory system2and the host3. In the second embodiment, the connection part33is provided in the memory system2.

The memory system2in the second embodiment includes the memory area21, the memory controller22, the PIN holding part25, the connection part33, the connectors C21and C24, and connectors C25and C26. Among these elements, the memory area21, the memory controller22, the PIN holding part25, and the connectors C21and C24are identical in configuration as those of the first embodiment.

The connection part33is electrically connected to the port Sin, the port Sinout, and the connector C25. The connection part33electrically short-circuits the connector C25, the port Sinout, and the port Sin when reverting is executed. The connection part33outputs a revert command received from the host3to the port Sinout and the port Sin. The connection part33outputs the identification information C_PIN received from the port Sinout to the port Sin.

The connection part33includes the switch SW1and the switch SW2. Each of the switches SW1and SW2is constituted by, for example, a transistor. The switches SW1and SW2are controlled by the command controller32.

The connector C25is electrically connected to both the port Sinout and the port Sin. The connector C25is removably connected to the host3via a connector C35. The connector C25is used to receive a revert command and other data, and transmit and receive the identification information C_PIN and other data. The connector C25is connected to the connector C35by the serial communication interface5to be capable of communicating with the connector C35.

The connector C26is electrically connected to the switches SW1and SW2. The connector C26is removably connected to the host3via a connector C36. The connector C26is used to receive control signals for the switches SW1and SW2. The connector C26is connected to the connector C36by a serial communication interface8to be capable of communicating with the connector C36.

Here, as similar to the connectors C22and C23, the connectors C25and C26are electrically disconnected from the connector C21. The interfaces5and8are a so-called “out-of-band interface”.

The host3in the second embodiment includes the data controller31, the command controller32, and the connectors C31, C34, C35, and C36. Among these elements, the data controller31, the command controller32, and the connectors C31and C34are identical in configuration as those of the first embodiment.

The connector C35is electrically connected to the port Sout. The connector C35is used to transmit a revert command and other data.

The connector C36is electrically connected to the command controller32. The connector C36is used to output control signals for the switches SW1and SW2.

The second embodiment can achieve effects identical to those of the first embodiment.

Third Embodiment

FIG.6is a block diagram illustrating an example of the configuration of the information processing system1according to a third embodiment. The information processing system1according to the third embodiment includes a plurality of memory systems2and one host3. In the third embodiment, the memory systems2are connected to the one host3.

Each of the memory systems2in the third embodiment includes the memory area21, the memory controller22, and the connectors C21, C23, and C24. Among these elements, the memory area21, the memory controller22, and the connector C21, C23, and C24are identical in configuration as those of the first embodiment.

The host3in the third embodiment includes the data controller31, the command controller32, the connection part33, and the connectors C31, C33, and C34. Among these elements, the data controller31is identical in configuration as that of the first embodiment.

The connection part33in the third embodiment is a wiring configured to electrically connect the port Sout and the connector C33.

The command controller32includes the revert-command holding part35and a PIN holding part36. The revert-command holding part35of these elements is identical in configuration as that of the first embodiment.

The PIN holding part36is, for example, a memory. The PIN holding part36holds the identification information C_PIN on each of the memory systems2. The PIN holding part36outputs, from the port Sout, the identification information C_PIN on a memory system2of the memory systems2, which is a revert target.

The connector C31is electrically connected to the data controller31. The connector C31is removably connected to the connector C21of each of the memory systems2. The connector C31is electrically disconnected from the connector C33and the port Sout.

The connector C33is electrically connected to the port Sout. The connector C33is removably connected to the connector C23of each of the memory systems2. The connector C33is used to output a revert command. The connector C33is used to output the identification information C_PIN. The connector C33is electrically disconnected from the connector C31.

The connector C34is connected to the port Sclk3. The connector C34is removably connected to the connector C24of each of the memory systems2. The connector C34is electrically disconnected from the connectors C31and C33and the port Sout.

FIG.7is a sequence diagram illustrating an example of the operation of the information processing system1according to the third embodiment.

When a user requests reverting on the host3, the revert-command holding part35of the host3outputs a revert command from the port Sout. After the revert command is output, the PIN holding part36outputs, from the port Sout, the identification information C_PIN on the memory system2which is a revert target.

The revert command and the identification information C_PIN are input to the port Sin of each of the memory systems2.

Upon receiving the identification information C_PIN at the port Sin, the PIN authentication part27of each of the memory systems2converts the identification information C_PIN received from the port Sin into a hash value by using a hash function. Further, the PIN authentication part27of each of the memory systems2compares the hash value obtained by converting the identification information C_PIN with the hash value held in advance in the hash holding part26.

When the hash value obtained from the identification information C_PIN matches the hash value held in the hash holding part26, the PIN authentication part27executes reverting of the memory area21.

When the hash value obtained from the identification information C_PIN does not match the hash value held in the hash holding part26, the PIN authentication part27does not execute reverting of the memory area21.

In the information processing system1according to the third embodiment, the host3can execute reverting only on a memory system2of the memory systems2, which is indicated by the identification information C_PIN.

In the third embodiment, the memory systems2are connected to the one host3. The host3can execute reverting only on a memory system2of the memory systems2, which is indicated by the identification information C_PIN.

Fourth Embodiment

FIG.8is a block diagram illustrating an example of the configuration of the information processing system1according to a fourth embodiment. The information processing system1according to the fourth embodiment includes a plurality of memory systems2and one host3. In the fourth embodiment, the memory systems2are connected to the one host3.

Each of the memory systems2in the fourth embodiment includes the memory area21, the memory controller22, the PIN holding part25, and the connectors C21to C24. Among these elements, the memory area21, the memory controller22, the PIN holding part25, the connectors C21, C23, and C24are identical in configuration as those of the first embodiment.

The connector C22is electrically connected to the port Sinout of the PIN holding part25. The connector C22is electrically disconnected from the host3.

The host3in the fourth embodiment includes the data controller31, the command controller32, the connection part33, and the connectors C31, C33, and C34. Among these elements, the data controller31, the command controller32, the connection part33, the connectors C31, C33, and C34are identical in configuration as those of the third embodiment.

The fourth embodiment can achieve effects identical to those of the third embodiment.

While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions. Indeed, the novel methods and systems described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the methods and systems described herein may be made without departing from the spirit of the inventions. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the inventions.

APPENDIX

(9) An information processing system comprising a memory system and a host removably connected to the memory system, whereinthe memory system includesa memory area configured to store data therein,a controller configured to control the memory area,a first connector configured to input the data from the host or output the data to the host, the first connector being removable from the host,a first holding part electrically disconnected from the memory area and the first connector during an operation other than initialization of the memory area, the first holding part being configured to hold identification information used to authenticate an authority to initialize the memory area,a first port connected to the first holding part, the first port being configured to output the identification information from the first holding part when receiving, from the host, an initialization command that instructs initialization of the memory area,a second port configured to receive the initialization command from the host and receive the identification information from the first port, andan authentication part configured to execute initialization of the memory area based on the initialization command and the identification information received at the second port, andthe host includesa second connector configured to input the data from the memory system or output the data to the memory system, the second connector being removable from the first connector,a second holding part configured to hold the initialization command, anda third port configured to output the initialization command from the second holding part to the first port.(10) The system of (9), wherein the first to third ports are electrically connected with each other in initializing the memory area.(11) The system of (9), wherein the authority is a PSID authority, where a PSID complies with TCG standards.(12) The system of (9), whereinthe memory system further includesa second connector electrically connected to the first port and removable from the host, anda third connector electrically connected to the second port and removable from the host, andthe host further includesfifth and sixth connectors removable from the second and third connectors, respectively, anda first wiring configured to electrically connect the fifth connector and the sixth connector to the third port.(13) The system of (9), whereinthe memory system further includesa second wiring configured to electrically connect the first port and the second port with each other, anda second connector electrically connected to the second wiring and removable from the host, andthe host further includes an eighth connector electrically connected to the third port and removable from the second connector.(14) The system of (9), whereina plurality of the memory systems are connected to the one host, andthe host further includes an identification-information holding part configured to hold identification information on each of the memory systems.(15) An information processing system comprising a plurality of memory systems and a host removably connected to the memory systems, whereineach of the memory systems includesa memory area configured to store data therein,a controller configured to control the memory area,a first connector configured to input the data from the host or output the data to the host, the first connector being removable from the host,a first port configured to receive an initialization command that instructs initialization of the memory area, and identification information used to authenticate an authority to initialize the memory area from the host, andan authentication part configured to execute initialization of the memory area based on the initialization command and the identification information received at the first port, andthe host includesa second connector configured to input the data from the memory system or output the data to the memory system, the second connector being removable from the first connector,a first holding part electrically disconnected from the memory area and the first connector during an operation other than initialization of the memory area, the first holding part being configured to hold the identification information,a second holding part configured to hold the initialization command, anda third port configured to output the initialization command and the identification information.(16) The system of (15), wherein the first to third ports are electrically connected with each other in initializing the memory area.(17) The system of (15), wherein the authority is a PSID (Physical Presence Security Identifier) authority, where a PSID complies with TCG (Trusted Computing Group) standards.(18) The system of (15), whereinthe memory system further includesa second connector electrically connected to the first port and removable from the host, anda third connector electrically connected to the second port and removable from the host, andthe host further includesfifth and sixth connectors removable from the second and third connectors, respectively, anda first wiring configured to electrically connect the fifth connector and the sixth connector to the third port.(19) The system of (15), whereinthe memory system further includesa second wiring configured to electrically connect the first port and the second port with each other, anda second connector electrically connected to the second wiring and removable from the host, andthe host further includes an eighth connector electrically connected to the third port and removable from the second connector.(20) The system of (15), whereina plurality of the memory systems are connected to the one host, andthe host further includes an identification-information holding part configured to hold identification information on each of the memory systems.