Patent ID: 12225792

DETAILED DESCRIPTION

Reference will now be made in more detail to aspects of some example embodiments, which are illustrated in the accompanying drawings, wherein like reference numerals refer to like elements throughout. In this regard, the present example embodiments may have different forms and should not be construed as being limited to the descriptions set forth herein. Accordingly, the example embodiments are merely described below, by referring to the figures, to explain aspects of the present description. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items. Throughout the disclosure, the expression “at least one of a, b or c” indicates only a, only b, only c, both a and b, both a and c, both b and c, all of a, b, and c, or variations thereof.

Various modifications may be applied to the present embodiments, and particular embodiments will be illustrated in the drawings and described in the detailed description. The effects and features of the disclosure, and a method to achieve the same will become more apparent from the following example embodiments that are described in more detail in conjunction with the accompanying drawings. However, embodiments according to the present disclosure are not limited to the following example embodiments and embodiments according to the present disclosure may be embodied in various forms.

The following example embodiments will now be described more fully with reference to the accompanying drawings. When describing aspects of example embodiments with reference to the accompanying drawings, the same or corresponding elements are denoted by the same reference numerals and a redundant description thereof will be omitted.

It will be understood that although the terms “first,” “second,” etc. may be used herein to describe various elements, these elements should not be limited by these terms. These elements are only used to distinguish one element from another.

As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise.

It will be understood that the terms “comprises” and/or “comprising” used herein specify the presence of stated features or elements, but do not preclude the presence or addition of one or more other features or elements.

It will be understood that when a layer, region, or element is referred to as being connected to another layer, region, or element, it can be directly connected to the other layer, region, or element or indirectly connected to the other layer, region, or element via intervening layers, regions, or elements.

Sizes of elements in the drawings may be exaggerated for convenience of description. In other words, because the sizes and thicknesses of elements in the drawings are arbitrarily illustrated for convenience of description, the following embodiments are not limited thereto.

In the following example embodiments, the x-axis, the y-axis and the z-axis are not limited to three axes of the rectangular coordinate system and may be interpreted in a broader sense. For example, the x-axis, the y-axis, and the z-axis may be perpendicular to one another or may represent different directions that are not perpendicular to one another.

When a certain embodiment may be implemented differently, a specific process order may be performed differently from the described order. For example, two consecutively described processes may be performed substantially at the same time or performed in an order opposite to the described order.

FIG.1is a schematic plan view of an example of a display panel10A according to some example embodiments.FIG.2is a schematic conceptual diagram of an area A ofFIG.1, andFIG.3is a schematic conceptual diagram of an area B ofFIG.2.FIG.4is a schematic conceptual diagram of an area C ofFIG.2.

Referring toFIG.1, the display panel10A according to some example embodiments may include a display area DA at which images are displayed and a peripheral area PA located outside the display area DA (e.g., around a periphery of the display area DA, or outside a footprint of the display area DA). Thus, it may be understood that a substrate100A provided in the display panel10A includes the display area DA and the peripheral area PA.

An edge of the display area DA may have overall a shape that is the same as or similar to a rectangle or a square. According to some example embodiments, corners on the edge of the display area DA may form a right angle, although according to some example embodiments, one or more corners may have a rounded corner. For example, as shown inFIGS.1and2, a first corner CN1on the edge of the display area DA may be round. Hereinafter, for convenience of description, an embodiment in which the corners on the edge of the display area DA are round as shown inFIGS.1and2will be mainly described in detail, but embodiments according to the present disclosure are not limited thereto.

For example, the display area DA may include a first edge E1and a second edge E2, which face each other, and a third edge E3and a fourth edge E4, which are between the first edge E1and the second edge E2and face each other. A pad area PADA is adjacent to the fourth edge E4among the first to fourth edges E1to E4. In this case, the first corner CN1that is round connects the first edge E1and the fourth edge E4to each other. In addition to the first corner CN1, a second corner CN2on the edge of the display area DA may be round. The second corner CN2connects the second edge E2and the fourth edge E4to each other. In addition, other portions on the edge of the display area DA may be round.

A plurality of pixels PX and wires via which an electrical signal is applied to the pixels PX may be located in the display area DA.

Each pixel PX may include a display element and a circuit unit for driving the display element. As an example, the display element may be an organic light-emitting device, and the circuit unit may include a plurality of transistors, a capacitor, etc.

Signal lines via which an electrical signal is applied to the pixels PX may include a plurality of scan lines SL, a plurality of data lines DL, etc. The scan lines SL each may extend in a first direction D1, and the data lines DL each may extend in a second direction D2. The scan lines SL may be arranged in, for example, a plurality of rows to transmit a scan signal to the pixels PX, and the data lines DL may be arranged in, for example, a plurality of columns to transmit a data signal to the pixels PX. The pixels PX each may be connected to a corresponding scan line SL of the scan lines SL and a corresponding data line DL of the data lines DL.

The peripheral area PA may surround the display area DA. The peripheral area PA may be an area in which pixels PX are not arranged and may include the pad area PADA, which is an area to which various electronic devices or printed circuit boards are attached. A voltage line that supplies power to drive the display element may be located in the peripheral area PA. A plurality of pads in the pad area PADA may be electrically connected to a film in which a driving integrated circuit (IC) D_IC is arranged.FIG.1illustrates a Chip on Film (COF) method in which the driving IC D_IC is arranged on the film electrically connected to the pads arranged on the substrate100A. According to some example embodiments, the driving IC D_IC may be directly arranged on the substrate100A using a Chip on Glass (COG) or Chip on Plastic (COP) method.

In addition, as shown inFIG.2, the peripheral area PA may include a bending area BA, and the bending area BA may be between the pad area PADA and the display area DA. In this case, by making the substrate100A bendable in the bending area BA, at least a portion of the pad area PADA may be located to overlap the display area DA. A bending direction is set such that the pad area PADA does not cover the display area DA, but the pad area PADA is located behind the display area DA. Accordingly, a user may recognize that the display area DA occupies most of the display panel10A.

FIG.3is a schematic conceptual diagram of an area B ofFIG.2and shows a portion of the first corner CN1. As shownFIGS.1and2, as observed by a user who uses the display device according to the present embodiment or an electronic device including the same under a normal usage environment, the user may recognize or perceive that the first corner CN1is round, that is, has a curved shape. However, in an environment in which wires having a width of several micrometers or several tens of micrometers are observable by enlarging the first corner CN1, as shown inFIG.3, the first corner CN1may appear to have a linear shape that is bent a plurality of times in the first direction D1and the second direction D2. Though the first corner CN1appears to have a linear shape that is bent a plurality of times (e.g., to form a stepped shape), as shown inFIG.3, by enlarging the first corner CN1, the first corner CN1is seen to be round, that is, have a curved shape. Therefore, hereinbelow, a case where the first corner CN1is round will be described.

The display area DA may include a dummy area DMA. The dummy area DMA may be provided along the first to fourth edges E1to E4and the first and second corners CN1and CN2of the display area DA, and may be located adjacent to a boundary between the display area DA and the peripheral area PA. A plurality of dummy pixels DPX may be arranged in the dummy area DMA. The dummy pixels DPX may surround the pixels PX and may be located adjacent to the peripheral area PA. InFIG.3, for convenience of description, only some of the pixels PX and some of the dummy pixels DPX in the display area DA are shown.

Connection lines200for transmitting, to signal lines connected to the pixels PX, an electrical signal supplied from the pads may be located on the substrate100A. For example, the signal lines may be the data lines DL, and the connection lines200may be arranged between the data lines DL and the pad area PADA and transmit, to the data lines DL, a data signal supplied from the pads in the pad area PADA.

The connection lines200may include first connection lines201and second connection lines203. The first connection lines201may be arranged in the display area DA, and the second connection lines203and third connection lines205may be arranged in the peripheral area PA. A portion of the first connection lines201may be arranged in the dummy area DMA. The second connection lines203and the third connection lines205may be arranged in a fan-out area FOA located in the peripheral area PA. The fan-out area FOA may be between the pad area PADA and the display area DA.

First connection lines201arranged on the left side of a first central line CL1passing through the center of the display panel10A in the first direction D1and first connection lines201arranged on the right side of the first central line CL1may be approximately bilaterally symmetrical with respect to the first central line CL1.

At least a portion of each first connection line201may be located on a different layer from the scan lines SL and the data lines DL of the pixels PX. Each first connection line201may include a first portion201aextending in the first direction D1, and a second portion201band a third portion201cextending in the second direction D2from both ends of the first portion201a.The first portion201aand may connect the second portion201band the third portion201cto each other, and the first portion201a,the second portion201b,and the third portion201cmay be formed as one body. A first portion201aof each of the first connection lines201may extend parallel to a scan line SL of each pixel PX and may partially overlap with or be adjacent to the scan line SL. The first portion201aof each first connection line201may extend parallel to a scan line SL arranged in one of the rows. A second portion201band a third portion201cof each first connection line201may extend parallel to a first data line DL1and may partially overlap with or be adjacent to the first data line DL1. The second portion201bof each first connection line201may extend parallel to a data line DL arranged in one of the columns. The third portion201cof each first connection line201may extend parallel to a second data line DL2arranged in one of the columns.

The first portion201aand the second portion201bas described above may be provided as at least one first portion201aand at least one second portion201b, respectively. In this case, the first portion201aand the second portion201bare alternately arranged and connected to each other. At this time, different first portions201amay be arranged to be parallel to different scan lines SL, respectively, and different second portions201bmay be arranged to be parallel to different data lines DL, respectively. In addition, the first connection line201as described above may extend in a direction away from the pad area PADA to be connected to the data line DL. That is, the first connection line201may extend away from the pad area PADA, from a portion of the first connection line201connected to the second connection line203toward a portion of the first connection line201connected to the data line DL. In this case, the first connection line201may be in the form of steps to sequentially extend away from the pad area PADA.

One end of the first connection line201may be connected to the first data line DL1, and the other end of the first connection line201may be connected to the second connection line203. That is, the first portion201aof the first connection line201may be connected to the first data line DL1at a first contact portion CNT1. In this case, the first contact portion CNT1may be in the form of a contact hole. The third portion201cof the first connection line201may be connected to the second connection line203. According to some example embodiments, the second connection line203may be a portion in which the second portion201bof the first connection line201extends to the peripheral area PA through the dummy area DMA, or a portion in which the third portion201cof the first connection line201, which will be described later, extends to the peripheral area PA through the dummy area DMA. One end of the second connection line203may be connected to the other end of the first connection line201, and the other end of the second connection line203may be connected to the pad area PADA.

The connection lines200may further include third connection lines205. One end of the third connection line205may be connected to the second data line DL2, and the other end of the third connection line205may be connected to the pad area PADA. The one end of the third connection line205may be connected to the second data line DL2in the dummy area DMA. The third connection line205may be a portion in which the second data line DL2that is not connected to the first connection line201extends to the peripheral area PA through the dummy area DMA.

In the case described above, according to some example embodiments, the data lines DL of the display panel10A may include only the first data lines DL1, and each first data line DL1may be connected to each first connection line201one by one. According to some example embodiments, the data lines DL of the display panel10A may include the first data lines DL1and the second data lines DL2. In this case, each first data line DL1may be connected to each pad through each first connection line201and each second connection line203, and each second data line DL2may be connected to each pad through each third connection line205. Hereinafter, for convenience of description, a case where the data lines DL include the first data line DL1and the second data line DL2will be mainly described in more detail.

The display panel10A may include first data line arrangement areas DLA1in which a plurality of first data lines DL1are arranged and a second data line arrangement area DLA2in which a plurality of second data lines DL2are arranged. In this case, the first data line arrangement area DLA1may be arranged outside the second data line arrangement area DLA2, and the second data line arrangement area DLA2may be arranged between the first data line arrangement areas DLA1that are symmetrically arranged with respect to the second data line arrangement area DLA2. Hereinbelow, for convenience of description, a case where the display panel10A includes the first data line arrangement areas DLA1and the second data line arrangement area DLA2will be mainly described in detail.

The first connection line201as described above may have various shapes. According to some example embodiments, the first connection line201may include the first portion201a,the second portion201b,and the third portion201c.In addition, the first connection lines201may all be connected to the first data lines DL1to correspond one by one to the first data lines DL1, respectively. According to some example embodiments, some of the first connection lines201may be connected to the first data lines DL1, and the others of the first connection lines201may not be connected to the first data lines DL1. In this case, the others of the first connection lines201which are not connected to the first data lines DL1may include only the third portion201c.When the first connection line201includes only the third portion201c, the third portion201cmay be connected to one of the second connection lines203. Hereinbelow, for convenience of description, a case where the first connection line201is connected to each first data line DL1will be mainly described in more detail.

FIGS.5A and5Bare equivalent circuit diagrams of any one pixel PX arranged on a display panel, according to some example embodiments.

Referring toFIG.5A, the pixel PX includes a pixel circuit PC and an organic light-emitting diode OLED, which is a display element connected to the pixel circuit PC. The pixel circuit PC may include a first transistor T1, a second transistor T2, and a capacitor Cst. Each pixel PX may emit, for example, red, green, blue, or white light from the organic light-emitting diode OLED. The first transistor T1and the second transistor T2may include thin-film transistors.

The second transistor T2, which is a switching transistor, may be connected to the scan line SL and the data line DL and may be configured to transmit, to the first transistor T1, a data signal input from the data line DL according to a switching voltage input from the scan line SL. The capacitor Cst may be connected to the second transistor T2and a power voltage line PL and may be configured to store a voltage corresponding to a difference between a voltage corresponding to the data signal received from the second transistor T2and a first power voltage ELVDD supplied through the power voltage line PL. The power voltage line PL may be spaced apart parallel to the scan line SL or the data line DL.

The first transistor T1, which is a driving transistor, may be connected to the power voltage line PL and the capacitor Cst and may be configured to control a driving current loled flowing through the organic light-emitting diode OLED from the power voltage line PL in response to a value of the voltage stored in the capacitor Cst. The organic light-emitting diode OLED may emit light having a certain luminance according to the driving current loled. An opposite electrode (e.g., a cathode) of the organic light-emitting diode OLED may receive a second power voltage ELVSS.

ThoughFIG.5Aillustrates that the pixel circuit PC includes two transistors and one capacitor, the embodiments according to the present disclosure are not limited thereto. The number of transistors and the number of capacitors may be variously changed according to the design of the pixel circuit PC.

Referring toFIG.5B, though it is shown that signal lines121,122,123, and DL, an initialization voltage line124, and a power voltage line PL are provided for each pixel PX, the embodiments according to the present disclosure are not limited thereto. According to some example embodiments, at least one of the signal lines121,122,123, or DL, the initialization voltage line124, and/or the power voltage line PL may be shared by neighboring pixels.

The signal lines include a first scan line121configured to transmit a first scan signal GW, a second scan line122configured to transmit a second scan signal GI, an emission control line123configured to transmit an emission control signal EM, and a data line DL that intersects with the first scan line121and is configured to transmit a data signal DATA. The second scan line122may be connected to a first scan line121in a next row or a previous row, and the second scan signal GI may be a first scan signal GW in a next row or a previous row.

The power voltage line PL may be configured to transmit a first power voltage ELVDD to the first transistor T1, and the initialization voltage line124may be configured to transmit, to the pixel PX, an initialization voltage VINT that initializes the first transistor T1and a pixel electrode of the organic light-emitting diode OLED.

The first scan line121, the second scan line122, the emission control line123, and the initialization voltage line124may extend in the first direction D1and may be arranged in each row to be spaced apart from each other. The data line DL and the power voltage line PL may extend in the second direction D2and may be arranged in each column to be spaced apart from each other.

The first scan line121and the second scan line122may be the scan lines SL shown inFIG.1. The scan lines SL may be connected to pixels PX arranged in a line. In this case, the first scan line121and the second scan line122may pass through one of the pixels PX arranged in a line. In addition, the first scan line121and the second scan line122respectively passing through each of the pixels PX arranged in a line may be configured to input different scan signals to each pixel PX according to driving of each pixel PX. In this case, a plurality of scan lines SL are provided, and the scan lines SL may be arranged in the respective rows to extend in the first direction D1and may be spaced apart from each other in the second direction D2.

The pixel circuit PC of the pixel PX may include first to seventh transistors T1, T2, T3, T4, T5, T6, and T7, and a capacitor Cst. The first to seventh transistors T1to T7may include thin-film transistors.

The first transistor T1is connected to the power voltage line PL via the fifth transistor T5and is electrically connected to the pixel electrode of the organic light-emitting diode OLED via the sixth transistor T6. The first transistor T1functions as a driving transistor and is configured to receive the data signal DATA according to a switching operation of the second transistor T2to supply the driving current loled to the organic light-emitting diode OLED.

The second transistor T2is connected to the first scan line121and the data line DL, and is turned on according to the first scan signal GW received through the first scan line121to perform a switching operation of transmitting, to a node N, the data signal DATA transmitted to the data line DL.

The third transistor T3is connected to the pixel electrode of the organic light-emitting diode OLED via the sixth transistor T6. The third transistor T3is turned on according to the first scan signal GW received through the first scan line121to diode-connect the first transistor T1.

The fourth transistor T4is turned on according to the second scan signal GI received through the second scan line122to transmit, to a gate electrode of the first transistor T1, the initialization voltage VINT from the initialization voltage line124, to thus initialize a gate voltage of the first transistor T1.

The fifth transistor T5and the sixth transistor T6are simultaneously (or concurrently) turned on according to the emission control signal EM received through the emission control line123to form a current path via which the driving current loled flows in a direction from the power voltage line PL to the organic light-emitting diode OLED.

The seventh transistor T7is turned on according to the second scan signal GI received through the second scan line122to transmit, to the pixel electrode of the organic light-emitting diode OLED, the initialization voltage VINT from the initialization voltage line124, to thus initialize the pixel electrode of the organic light-emitting diode OLED. The seventh transistor T7may be omitted.

ThoughFIG.5Billustrates a case where the fourth transistor T4and the seventh transistor T7are connected to the second scan line122, the embodiments according to the present disclosure are not limited thereto. According to some example embodiments, the fourth transistor T4may be connected to the second scan line122, and the seventh transistor T7may be connected to a separate wire to be driven according to a signal transmitted to the wire.

The capacitor Cst may be connected to the power voltage line PL and the gate electrode of the first transistor T1, to store and maintain a voltage corresponding to a difference between voltages at both ends to thus maintain a voltage applied to the gate electrode of the first transistor T1.

The organic light-emitting diode OLED may include the pixel electrode, a common electrode facing the pixel electrode, and an emission layer between the pixel electrode and the common electrode. The common electrode may receive the second power voltage ELVSS. The organic light-emitting diode OLED receives the driving current loled from the first transistor T1and emits light to display an image.

The dummy pixel DPX includes the same pixel circuit PC as the pixel PX ofFIGS.5A and5Band does not include some elements of the organic light-emitting diode OLED and thus may not emit light. According to some example embodiments, the dummy pixel DPX may not include a pixel electrode and may include an emission layer and an opposite electrode.

FIG.6is a schematic conceptual diagram of a first area S1ofFIG.1.FIG.7is an exemplary view of a pixel electrode131and a shielding member150arranged on first connection lines201, according to some example embodiments.FIG.8is a cross-sectional view of a first area taken along a line I-I′ ofFIG.7.

As shown inFIGS.6and7, first pattern areas X1divided between adjacent first connection lines201may be located in the first area S1formed by a first connection line201arranged outermost and a first connection line201arranged innermost. In this case, according to some example embodiments, each first connection line201may include at least one dummy pattern220c1or220d1arranged in the first pattern area X1. According to some example embodiments, each first connection line201may not include at least one dummy pattern220c1or220d1. Hereinbelow, for convenience of description, a case where the first connection line201includes the dummy patterns220c1and220d1will be mainly described in more detail.

The dummy patterns220c1and220d1may be arranged in the first pattern area X1. According to some example embodiments, a dummy line may be arranged in an area of the first area S1in which the first connection lines201are not arranged. The dummy line may be disconnected from the first connection lines201and may have various structures to divide the first pattern areas X1. For example, the dummy line may have a linear structure or a lattice structure.

The first connection lines201, the dummy patterns220c1and220d1of the first pattern area X1, and the dummy line may be arranged on the same layer. In addition, the first connection lines201, the dummy patterns220c1and220d1of the first pattern area X1, and the dummy line may be formed in the same process. In this case, the dummy patterns220c1and220d1and the dummy line may be in a floating state.

Because reflection characteristics of light in the first area S1become similar by the first pattern areas X1, the first area may be prevented or minimized from being recognized as divided according to an incident angle of light. The dummy patterns220c1and220d1may prevent signal interference between the first connection lines201and may enable a greater pattern density during the manufacturing process.

As shown inFIG.6, second portions201bof a pair of adjacent first connection lines201may be spaced apart from each other to exceed a length (second length) corresponding to an interval between a first scan line121and a second scan line122, which are adjacent in the second direction D2. In this case, the second portions201bof the first connection lines201each may pass through one first scan line121or one second scan line122. First portions201aof the pair of adjacent first connection lines201may be spaced apart from each other by a length (first length) or less corresponding to an interval between two data lines DL, which are adjacent in the first direction D1.

A display element may be arranged on the first connection lines201. In this case, according to some example embodiments, at least a portion of the first connection line201may be arranged to overlap a pixel electrode131in a plan view. According to some example embodiments, the first connection line201may be arranged not to overlap the pixel electrode131in a plan view. Hereinbelow, for convenience of description, a case where at least a portion of the first connection line201is arranged to overlap the pixel electrode131in a plan view will be mainly described in detail.

A plurality of pixels PX may be arranged in a display area DA of a substrate100B. A thin-film transistor TFT, a capacitor Cst, and a display element130electrically connected to the thin-film transistor TFT may be arranged in each pixel PX. The display element130may be the organic light-emitting diode OLED ofFIGS.5A and5B. The thin-film transistor TFT may be one of the transistors ofFIGS.5A and5B. For example, the thin-film transistor TFT shown inFIG.8may be the first transistor T1ofFIGS.5A and5B.

The substrate100B may include various materials such as a glass material, a metallic material, or a plastic material. According to some example embodiments, the substrate100B may be a flexible substrate and may include, for example, a polymer resin such as polyethersulfone (PES), polyacrylate, polyetherimide (PEI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyarlylate (PAR), polyimide (PI), polycarbonate (PC), or cellulose acetate propionate (CAP). The substrate100B may have a multi-layered structure including a layer including the aforementioned polymer resin, and an inorganic layer.

A buffer layer111may be located on the substrate100B as necessary. The buffer layer111may planarize a surface of the substrate100B or prevent impurities or the like from penetrating a semiconductor layer thereon. The buffer layer111may have a single-layered/multi-layered structure including an inorganic insulating material such as silicon oxide, silicon nitride, or silicon oxynitride. The buffer layer111may be omitted.

The thin-film transistor TFT may be arranged on the buffer layer111. The thin-film transistor TFT may include a semiconductor layer Act, a gate electrode125, a source electrode123S, and a drain electrode123D.

The semiconductor layer Act may include amorphous silicon, polycrystalline silicon, or an organic semiconductor material. The semiconductor layer Act may include a source region, a drain region, and a channel region between the source region and the drain region.

Considering adhesion to adjacent layers, surface flatness of layers to be stacked, and processability, the gate electrode125may include a single layer or a multi-layer including, for example, one or more materials of aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and copper (Cu).

A first insulating layer112may be arranged between the semiconductor layer Act and the gate electrode125. A second insulating layer113and a third insulating layer114may be arranged between the gate electrode125and the source electrode123S and between the source electrode123S and the drain electrode123D. The first insulating layer112, the second insulating layer113, and the third insulating layer114may include an inorganic material such as silicon oxide, silicon nitride, and/or silicon oxynitride. According to some example embodiments, the scan lines SL, the first scan line121, the second scan line122, and the emission control line123ofFIGS.5A and5Bmay be arranged on the same layer as the gate electrode125, that is, on the first insulating layer112.

The source electrode123S and the drain electrode123D may be electrically connected to the source region and the drain region of the semiconductor layer Act through contact holes formed in the first insulating layer112, the second insulating layer113, and the third insulating layer114, respectively.

The source electrode123S and the drain electrode123D may include a single layer or a multi-layer including, for example, one or more materials of Al, Pt, Pd, Ag, Mg, Au, Ni, Nd, Ir, Cr, Li, Ca, Mo, Ti, W, and Cu.

The capacitor Cst includes a lower electrode125hand an upper electrode127overlapping each other with the second insulating layer113therebetween. The capacitor Cst may overlap the thin-film transistor TFT. In this regard,FIG.8illustrates that the gate electrode125of the thin-film transistor TFT is the lower electrode125hof the capacitor Cst. According to some example embodiments, the capacitor Cst may not include the thin-film transistor TFT, and the lower electrode125hof the capacitor Cst may be a separate element independent from the gate electrode125of the thin-film transistor TFT. The capacitor Cst may be covered by the third insulating layer114. According to some example embodiments, the initialization voltage line124ofFIG.5Bmay be arranged on the same layer as the upper electrode127of the capacitor Cst, that is, on the second insulating layer113.

The pixel circuit including the thin-film transistor TFT and the capacitor Cst may be covered by a fourth insulating layer115and a fifth insulating layer116. The fourth insulating layer115and the fifth insulating layer116, which are planarization insulating layers, may be organic insulating layers. The fourth insulating layer115and the fifth insulating layer116may include an organic insulating material such as a general-purpose polymer such as polymethyl methacrylate (PMMA) or polystyrene (PS), polymer derivatives having a phenol-based group, an acryl-based polymer, an imide-based polymer, and an aryl ether-based polymer, an amide-based polymer, a fluorine-based polymer, a p-xylene-based polymer, a vinyl alcohol-based polymer, or blends thereof. According to some example embodiments, the fourth insulating layer115and the fifth insulating layer116may include polyimide.

Various conductive layers may be further arranged on the third insulating layer114. For example, the data line DL and the power voltage line PL may be arranged on the third insulating layer114, that is, the same layer as the source electrode123S and the drain electrode123D. In this case, the data line DL is not limited to the above layer and may be arranged on the fourth insulating layer115. However, hereinbelow, for convenience of description, a case where the data line DL and the power voltage line PL are arranged on the third insulating layer114will be mainly described in detail.

The fourth insulating layer115may be arranged on the data line DL and the power voltage line PL. As shown inFIG.8, a portion of the first connection line201(e.g., one of the first portion201aand the second portion201b), the dummy line, and the dummy patterns220c1and220d1may be arranged on the fourth insulating layer115. The first connection line201, the dummy line, and the dummy patterns220c1and220d1may include a single layer or a multi-layer including at least one of Al, Cu, Ti, or alloys thereof. The fifth insulating layer116may be arranged on the first connection line201, the dummy line, and the dummy patterns220c1and220d1. According to some example embodiments, in a plan view, a portion of the first connection line201(e.g., at least one of the dummy line or the dummy patterns220c1or220d1) may overlap the data line DL, and a portion of the first connection line201(e.g., the first portion201aor the second portion201b) may overlap the scan line SL.

In the case described above, the data line DL may be arranged on a different layer from the first portion201aof the first connection line201, the dummy line, and the dummy patterns220c1and220d1. For example, when the data line DL is arranged on the third insulating layer114, the first portion201aof the first connection line201, the dummy line, and the dummy patterns220c1and220d1may be arranged on the fourth insulating layer115. When the data line DL is arranged on the fourth insulating layer115, the second portion201bof the first connection line201, the dummy line, and the dummy patterns220c1and220d1may be arranged on the third insulating layer114. According to some example embodiments, the first connection line201may be entirely arranged on a different layer from the data line DL. Hereinbelow, for convenience of description, a case where the data line DL is arranged on the third insulating layer114, and the first portion201aof the first connection line201, the dummy line, and the dummy patterns220c1and220d1are arranged on the fourth insulating layer115will be mainly described in detail.

The display element130may be arranged on the fifth insulating layer116. The display element130may include the pixel electrode131, an opposite electrode135, and an intermediate layer133between the pixel electrode131and the opposite electrode135.

The pixel electrode131may include a conductive oxide such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO), or aluminum zinc oxide (AZO). According to some example embodiments, the pixel electrode131may include a reflective layer including Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, or compounds thereof. According to some example embodiments, the pixel electrode131may further include a layer including ITO, IZO, ZnO, or In2O3above/under the aforementioned reflective layer.

A shielding member150may be further arranged on the fifth insulating layer116. The shielding member150may extend in the first direction D1along a portion of an edge of the pixel electrode131so as not to overlap the pixel electrode131on a plane, and may be arranged above or under each row. The shielding member150may have a linear shape extending in the first direction D1or a zigzag shape according to the arrangement of pixel electrodes131in the same row. The shielding member150may include light-shielding metal. For example, the shielding member150may include Mo, Al, Cu, Ti, etc. and may include a multi-layer or a single layer including the above material. According to some example embodiments, the shielding member150may include a multi-layer of Ti/Al/Ti. The shielding member150may include the same material as the pixel electrode131. The shielding members150may be spaced apart from each other and provided independently for each row. The shielding members150may be floated or electrically connected to a constant voltage wire (e.g., a power voltage line, an initialization voltage line, etc.) to receive a constant voltage.

A sixth insulating layer117covering the edge of the pixel electrode131may be arranged on the fifth insulating layer116. The sixth insulating layer117may include an opening OP exposing a portion of the pixel electrode131, to thus define pixels. The sixth insulating layer117may include an organic material such as acryl, benzocyclobutene (BCB), polyimide, or hexamethyldisiloxane (HMDSO). Alternatively, the sixth insulating layer117may include the aforementioned inorganic material.

The intermediate layer133may be formed on the pixel electrode131exposed by the opening OP of the sixth insulating layer117. The intermediate layer133includes an emission layer. The emission layer may include a polymer organic material or a low molecular weight organic material that emits light of a certain color. The emission layer may be a red emission layer, a green emission layer, or a blue emission layer. Alternatively, the emission layer may have a multi-layered structure in which a red emission layer, a green emission layer, and a blue emission layer are arranged so as to emit white light, or may have a single-layered structure including a red emission material, a green emission material, and a blue emission material. According to some example embodiments, the intermediate layer133may include a first functional layer arranged under the emission layer and/or a second functional layer arranged above the emission layer. The first functional layer and/or the second functional layer may include an integral layer over the pixel electrodes131or may include a patterned layer to correspond to each of the pixel electrodes131.

The first functional layer may include a single layer or a multi-layer. For example, when the first functional layer includes a polymer material, the first functional layer is a hole transport layer (HTL) having a single-layered structure and may be formed with poly-(3,4)-ethylene-dihydroxy thiophene (PEDOT) or polyaniline (PANI). When the first functional layer includes a low molecular weight material, the first functional layer may include a hole injection layer (HIL) and an HTL.

The second functional layer may be omitted. For example, when the first functional layer and the emission layer include a polymer material, the second functional layer may be formed in order to improve the characteristics of an organic light-emitting diode. The second functional layer may include a single layer or a multi-layer. The second functional layer may include an electron transport layer (ETL) and/or an electron injection layer (EIL).

The opposite electrode135is arranged to face the pixel electrode131with the intermediate layer133therebetween. The opposite electrode135may include a conductive material having a low work function. For example, the opposite electrode135may include a (semi-)transparent layer including Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, Li, Ca, or alloys thereof. Alternatively, the opposite electrode135may further include a layer such as ITO, IZO, ZnO, or In2O3on a (semi-)transparent layer including the aforementioned material.

FIG.9Ais a schematic layout view of electrodes and wires according to some example embodiments.FIG.9Bis an enlarged view of an area E ofFIG.9A.FIGS.10A to10Care cross-sectional views taken along a line II-II′ ofFIG.9A. Hereinbelow, the same reference numerals as those inFIG.8mean the same members.

Referring toFIGS.9A to10C, the semiconductor layer Act may be arranged on the buffer layer111. The semiconductor layer Act may include amorphous silicon, polycrystalline silicon, or an organic semiconductor material. The semiconductor layer Act may have a curved shape in various shapes. As shown inFIG.9B, the semiconductor layer Act may include a channel region131aof the first transistor T1, a channel region131bof the second transistor T2, channel regions131c1and131c2of the third transistor T3, channel regions131d1and131d2of the fourth transistor T4, a channel region131eof the fifth transistor T5, a channel region131fof the sixth transistor T6, and a channel region131gof the seventh transistor T7. That is, the channel regions131ato131gof the first to seventh transistors T1to T7may be regions of the semiconductor layer Act. Because the channel region131aof the first transistor T1may be curved and thus be formed long, a driving range of a gate voltage applied to a gate electrode may be increased. The channel region131aof the first transistor T1may have a shape such as “,” “,” “M,” “W,” etc. Various embodiments are also possible. The channel region131gof the seventh transistor T7may be a region of a semiconductor layer extending from a previous row.

The semiconductor layer Act of the first to seventh transistors T1to T7may include a source region and a drain region on both sides of each of the channel regions131ato131g.As shown inFIGS.9A and9B, the semiconductor layer Act may include a source region176aand a drain region177aof the first transistor T1, a source region176band a drain region177bof the second transistor T2, a source region176cand a drain region177cof the third transistor T3, a source region176dand a drain region177dof the fourth transistor T4, a source region176eand a drain region177eof the fifth transistor T5, a source region176fand a drain region177fof the sixth transistor T6, and a source region176gand a drain region177gof the seventh transistor T7. In some cases, the source regions or the drain regions may be construed as source electrodes or drain electrodes of transistors, respectively. That is, for example, a source electrode and a drain electrode of the first transistor T1may correspond to the source region176aand the drain region177a,which are doped with impurities in the vicinity of the channel region131ain the semiconductor layer Act shown inFIG.9B, respectively. According to embodiments, locations of the source regions and the drain regions may be changed. The first insulating layer112may be located on the semiconductor layer Act.

A gate electrode125aof the first transistor T1, a gate electrode125bof the second transistor T2, gate electrodes125c1and125c2of the third transistor T3, gate electrodes125d1and125d2of the fourth transistor T4, a gate electrode125eof the fifth transistor T5, a gate electrode125fof the sixth transistor T6, and a gate electrode125gof the seventh transistor T7may be arranged on the first insulating layer112. In addition, the first scan line121, the second scan line122, and the emission control line123may be arranged on the first insulating layer112to extend in the second direction D2. The first scan line121, the second scan line122, and the emission control line123may include the same material as and may be arranged on the same layer as the gate electrodes of the first to seventh transistors T1to T7. The gate electrode125aof the first transistor T1may function as the lower electrode125hof the capacitor Cst.

The gate electrode125bof the second transistor T2and the gate electrodes125c1and125c2of the third transistor T3may be portions of the first scan line121intersecting with the semiconductor layer Act or portions protruding from the first scan line121. The gate electrodes125d1and125d2of the fourth transistor T4and the gate electrode125gof the seventh transistor T7may be portions of the second scan line122intersecting with the semiconductor layer Act or portions protruding from the second scan line122. The gate electrode125eof the fifth transistor T5and the gate electrode125fof the sixth transistor T6may be portions of the emission control line123intersecting with the semiconductor layer Act or portions protruding from the emission control line123. The gate electrode125aof the first transistor T1may be provided in an island type.

The gate electrodes125ato125gof the first to seventh transistors T1to T7may include a single layer or a multi-layer including one or more materials of Al, Pt, Pd, Ag, Mg, Au, Ni, Nd, Ir, Cr, Li, Ca, Mo, Ti, W, and Cu. The second insulating layer113may be arranged on the gate electrodes125ato125gof the first to seventh transistors T1to T7.

The upper electrode127of the capacitor Cst may be arranged on the second insulating layer113. An opening may be formed in the upper electrode127of the capacitor Cst. Through the opening, a node electrode174may allow the lower electrode125hof the capacitor Cst to be electrically connected to the drain region177cof the third transistor T3. The upper electrode127of the capacitor Cst may include a single layer or a multi-layer including one or more materials of Al, Pt, Pd, Ag, Mg, Au, Ni, Nd, Ir, Cr, Li, Ca, Mo, Ti, W, and Cu. The capacitor Cst may share the gate electrode125aof the first transistor T1as a lower electrode and may overlap the first transistor T1.

The initialization voltage line124and a shielding electrode129may be arranged on the second insulating layer113which is the same layer as the upper electrode127of the capacitor Cst. The initialization voltage line124and the shielding electrode129may include the same material as the upper electrode127of the capacitor Cst. The initialization voltage line124may extend in the second direction D2. The shielding electrode129may overlap the source region176bof the second transistor T2and the source/drain region176c/177cof the third transistor T3. The shielding electrode129may overlap the source/drain region176c/177cbetween the two channel regions131c1and131c2of the third transistor T3.

The third insulating layer114may be arranged on the upper electrode127of the capacitor Cst, the initialization voltage line124, and the shielding electrode129.

The first insulating layer112, the second insulating layer113, and the third insulating layer114may be an inorganic insulating layer including an inorganic material such as silicon oxide, silicon nitride, and/or silicon oxynitride.

The data line DL and the power voltage line PL extending in the first direction D1may be arranged on the third insulating layer114. The data line DL may be connected to the source region176bof the second transistor T2through a contact hole164formed in the first insulating layer112, the second insulating layer113, and the third insulating layer114. The power voltage line PL may be connected to the source region176eof the fifth transistor T5through a contact hole165formed in the first insulating layer112, the second insulating layer113, and the third insulating layer114. The power voltage line PL may be connected to the upper electrode127of the capacitor Cst through a contact hole168formed in the third insulating layer114. The power voltage line PL may be connected to the shielding electrode129through a contact hole169formed in the third insulating layer114. The power voltage line PL may include a protrusion172aprotruding from the power voltage line PL in an extension direction of the second scan line122. The protrusion172aof the power voltage line PL may overlap the second scan line122. The protrusion172aof the power voltage line PL may be arranged on a layer between the first connection line201and the second scan line122, and may overlap the first connection line201and the second scan line122, and thus electrical signal interference between the second scan line122and a portion (first portion201a) of the first connection line201parallel to the second scan line122may be blocked, thereby reducing parasitic capacitance between the first connection line201and the second scan line122.

The data line DL and the power voltage line PL may include Mo, Al, Cu, Ti, etc. and may include a multi-layer and a single layer. According to some example embodiments, the data line DL and the power voltage line PL may have a multi-layered structure of Ti/Al/Ti.

Various conductive layers may be further arranged on the third insulating layer114. For example, the node electrode174and connection electrodes173may be further formed on the third insulating layer114. One end of the node electrode174may be connected to the drain region177cof the third transistor T3and the drain region177dof the fourth transistor T4through a contact hole166formed in the first insulating layer112, the second insulating layer113, and the third insulating layer114, and the other end of the node electrode174may be connected to the gate electrode125aof the first transistor T1through a contact hole167formed in the second insulating layer113and the third insulating layer114. In this case, the other end of the node electrode174may be connected to the gate electrode125aof the first transistor T1through the opening formed in the upper electrode127of the capacitor Cst. One end of a connection electrode173may be connected to the initialization voltage line124through a contact hole161formed in the third insulating layer114, and the other end of the connection electrode173may be connected to the source region176dof the fourth transistor T4through a contact hole162formed in the first insulating layer112, the second insulating layer113, and the third insulating layer114. The connection electrode173may be connected to the drain region177fof the sixth transistor T6through a contact hole163formed in the first insulating layer112, the second insulating layer113, and the third insulating layer114.

The node electrode174and the connection electrodes173may include Mo, Al, Cu, Ti, etc. and may include a multi-layer or a single layer. According to some example embodiments, the node electrode174and the connection electrodes173may have a multi-layered structure of Ti/Al/Ti.

The fourth insulating layer115may be arranged on the data line DL and the power voltage line PL. The first connection line201may be arranged on at least one of the third insulating layer114or the fourth insulating layer115.

As described above, the first connection line201may include the first portion201aextending in the first direction D1and the second portion201bextending in the second direction D2. In addition, the first connection line201may further include a fourth portion201dconnecting the first portion201ato the second portion201b.In this case, the fourth portion201dmay extend in a direction between the first direction D1and the second direction D2. That is, as shown inFIG.9A, the fourth portion201dmay be arranged in a diagonal direction with respect to the first direction D1or the second direction D2. However, when there is a space, the fourth portion201dmay not be arranged, and the first portion201aand the second portion201bmay overlap each other. In this case, the first portion201aand the second portion201bmay be perpendicular to each other. However, hereinbelow, for convenience of description, a case where the first connection line201includes the fourth portion201dwill be mainly described in detail.

The fourth portion201dmay be formed as one body with at least one of the first portion201aor the second portion201b.In this case, the fourth portion201dmay be bent extending from one of the first portion201aand the second portion201b.

The first portion201aand the second portion201bas described above may be arranged on different layers or may be arranged on the same layer. According to some example embodiments, when the first portion201aand the second portion201bare arranged on different layers, the first portion201aand the second portion201bmay be connected to each other through a second contact portion CNT2. In this case, the second contact portion CNT2may be in the form of a contact hole. According to some example embodiments, when the first portion201aand the second portion201bare arranged on different layers, the first portion201aand the second portion201bmay be formed as one body and connected to each other.

The first portion201aand the second portion201bas described above may be arranged at various positions. For example, the first portion201amay be arranged between an emission control line123providing an emission control signal to one of pixels PX adjacent to each other and an initialization voltage line124providing an initialization voltage to the other pixels PX adjacent to each other. In this case, in a plan view, at least a portion of the first portion201amay not overlap the emission control line123and the initialization voltage line124, which are adjacent to each other. In addition, at least the portion of the first portion201amay or may not overlap a pixel electrode131of one of the pixels PX adjacent to each other. In a plan view, when at least the portion of the first portion201aoverlaps the pixel electrode131of one of the pixels PX adjacent to each other, the first portion201amay be arranged on a different layer from the pixel electrode131and may not be connected to the pixel electrode131. In addition, the first portion201amay be arranged on a different layer from the data line DL. In this case, the first portion201amay not be connected to a second data line DL2arranged in the second data line arrangement area DLA2and may be connected to only one first data line DL1arranged in the first data line arrangement area DLA1through the first contact portion CNT1.

At least one of the first portions201aas described above may be arranged to intersect with one of the scan lines SL in a plan view. In this case, the first portion201aand the scan line SL may be arranged on different layers and thus may not be connected to each other. For example, one first portion201amay be arranged to intersect with one of the first scan line121and the second scan line122in a plan view.

The second portion201bmay be arranged to be spaced apart from the data line DL. At this time, the second portion201bmay be arranged on a layer on which the data line DL is arranged or on a layer on which the data line DL is not arranged. In this case, when the second portion201bis arranged on the same layer as the data line DL, the second portion201bmay be spaced apart from the data line DL and thus may not be connected to the data line DL. In addition, the second portion201bmay be arranged to be parallel to the data line DL. According to some example embodiments, when the second portion201bis arranged on a different layer from the data line DL, the second portion201bmay be arranged on the data line DL to at least partially overlap the second portion201b.

The arrangement of the first connection line201and the data line DL as described above will be described in detail below.

Referring toFIG.10A, when the data line DL is arranged on the third insulating layer114, the first portion201amay be arranged on the fourth insulating layer115on which the data line DL is not arranged, and the second portion201bmay be arranged on the third insulating layer114on which the data line DL is arranged. In this case, the second portion201bmay be spaced apart from the data line DL on the third insulating layer114. In particular, the second portion201bmay be arranged to be parallel to the data line DL in a plan view. In this case, an end of the first portion201aand an end of the second portion201bmay overlap each other in a plan view and may be connected to each other through the second contact portion CNT2. According to some example embodiments, one of the end of the first portion201aand the end of the second portion201bmay overlap the fourth portion201dand may be connected to each other through the second contact portion CNT2.

Referring toFIG.10B, when the data line DL is arranged on the fourth insulating layer115, the first portion201amay be arranged on the third insulating layer114on which the data line DL is not arranged, and the second portion201bmay be arranged on the fourth insulating layer115on which the data line DL is arranged. At this time, the second portion201bmay be spaced apart from the data line DL on the fourth insulating layer115. In this case, the end of the first portion201aand the end of the second portion201bmay overlap each other in a plan view and may be connected to each other through the second contact portion CNT2. According to some example embodiments, one of the end of the first portion201aand the end of the second portion201bmay overlap the fourth portion201dand may be connected to each other through the second contact portion CNT2.

Referring toFIG.10C, the first portion201aand the second portion201bmay be arranged on the fourth insulating layer115on which the data line DL is not arranged. In this case, the data line DL may be arranged on the third insulating layer114. According to some example embodiments, when the data line DL is arranged on the fourth insulating layer115, the first portion201aand the second portion201bmay be arranged on the third insulating layer114. According to some example embodiments, when the first connection line201includes the fourth portion201d,the first portion201a,the second portion201b,and the fourth portion201dmay be arranged on the third insulating layer114or the fourth insulating layer115according to a shape in which the data line DL is arranged. In the case described above, the first connection line201may be formed as one body For example, the first portion201a, the second portion201b, and the fourth portion201dmay be formed as one body.

In the case described above, a first connection line201connected to the first data line DL1arranged in the first data line arrangement area DLA1may meet once a scan line SL (e.g., at least one of the first scan line121or the second scan line122) which is connected to pixels PX arranged in a line among the pixels PX and is configured to transmit a scan signal to each of the pixels PX arranged in a line.

In the case described above, in a case where each scan signal is applied when each pixel PX is driven, parasitic capacitance is generated between each scan line SL and the first connection line201according to a change in voltages of the scan signal applied to each scan line SL, which may cause coupling between each scan line SL and the first connection line201. In addition, when lengths of portions of the first connection line201, which are arranged parallel to the same scan line SL, are increased, a data signal transmitted through the first connection line201may include noise due to parasitic capacitance between the scan line SL and the portions of the first connection line201, which are parallel to each other. In this case, the first data line DL1connected to the first connection line201does not transmit an accurate signal to each pixel PX connected to the first data line DL1, and thus, a luminance of each pixel PX connected to the first data line DL1may be lowered. In addition, when the first connection line201is arranged in a straight line or is arranged to pass through pixel electrodes131of a number of pixels PX, a signal (or voltage) passing through the first connection line201may vary according to an operation of the pixel electrode131of each pixel PX.

However, by arranging the first connection line201alternately in the first direction D1and the second direction D2as described above, a length in which the first connection line201overlaps each scan line SL may be minimized. In addition, when one scan line SL (e.g., one of the first scan line121and the second scan line122, or one of the scan lines SL) is operated, the other scan line SL (e.g., the other of the first scan line121and the second scan line122, or the other of the scan lines SL) is not operated, and thus the influence of the scan lines SL on the signal passing through the first connection line201may be minimized.

Therefore, the display panel does not affect a data signal transmitted to the first data line DL1through the first connection line201, and thus, a luminance of a pixel PX in an area in which the first data line DL1is arranged may be accurately controlled.

FIG.11is a schematic layout view of electrodes and wires according to some example embodiments.

Referring toFIG.11, the first connection line201may include the first portion201a,the second portion201b,and the third portion201c.In this case, the first portion201aand the second portion201bmay be the same as or similar to those described above. The first portion201aand the second portion201bmay be arranged on different layers and connected to each other through the second contact portion CNT2. According to some example embodiments, the first portion201aand the second portion201bmay be arranged on the same layer and formed as one body. Hereinbelow, for convenience of description, a case where the first portion201aand the second portion201bare arranged on different layers and connected to each other through the second contact portion CNT2will be mainly described in detail.

In a plan view, each first portion201amay be arranged to cross only some of the data lines DL and may not cross the others of the data lines DL. For example, when ten data lines DL are arranged, one first portion201amay pass through only two of the ten data lines DL, and another first portion201amay pass through only another two of the ten data lines DL. In this case, the first portion201ais arranged on a different layer from each data line DL, and thus may not be connected to each data line DL. At this time, the data lines DL crossed by each first portion201ain a plan view are not limited to the above description.

The first portion201aas described above may be arranged in each pixel PX and may be arranged between an emission control line123and an initialization voltage line124, which are adjacent to each other. In particular, the first portion201amay be arranged between an emission control line123connected to one of the pixels PX adjacent to each other and an initialization voltage line124connected to the other of the pixels PX adjacent to each other. In this case, the first portion201amay be arranged parallel to the scan line SL. In addition, as described above, the first portion201amay or may not overlap pixel electrodes131of some of the pixels PX arranged in a line in a plan view. In this case, in a plan view, when the first portion201adoes not overlap the pixel electrode131, the first portion201amay be arranged between a pixel electrode131of one of the pixels PX adjacent to each other and an initialization voltage line124of the other pixels PX adjacent to each other.

The second portion201bmay be arranged in a different direction from the first portion201a.In this case, the second portion201bmay be arranged to be parallel to the data line DL. In this case, the second portion201bmay pass through at least one scan line SL. In particular, the second portion201bmay pass through one scan line SL. In this case, the second portion201bmay pass through a first scan line121and a second scan line122, which are connected to one pixel PX. According to some example embodiments, the second portion201bmay be arranged to pass only some of the scan lines SL. In particular, in this case, one of different second portions201bmay pass through some of the scan lines SL, and another of the different second portions201bmay pass through the others of the scan lines SL. That is, a second portion201bof one of the first connection lines201may pass through only some of the scan lines SL.

In the case described above, the first portion201aand the second portion201bmay be arranged as shown inFIGS.10A to10C.

The first connection line201may include a dummy connection line201-1including only the third portion201c.In this case, the dummy connection line201-1may be connected to a pad, and an end of the dummy connection line201-1may not be connected to other wires.

The first connection line201may include a branch portion201e.The branch portion201emay extend from at least one of the first portion201aor the second portion201b.In this case, an end of the branch portion201emay not be connected to other wires.

The first connection line201may further include a dummy line201f.The dummy line201fmay be spaced apart from the first portion201aand the second portion201b,and may also be spaced apart from the branch portion201eand the dummy connection line201-1. The first connection line201as described above may not include a separate dummy pattern.

Therefore, the display panel does not affect the data signal transmitted to the first data line DL1through the first connection line201, and thus the luminance of the pixel PX in the area in which the first data line DL1is arranged may be accurately controlled.

FIG.12is a schematic plan view of an example of a display panel10B according to some example embodiments.

The arrangement of the first connection lines201in the display panel10B is different from the arrangement of the first connection lines201in the display panel10A ofFIG.1, and the other configurations are the same. Hereinbelow, configurations different from those ofFIG.1will be mainly described.

Referring toFIG.12, at least a portion of each first connection line201may be located on a different layer from the scan lines SL and the data lines DL of the pixels PX. One end of the first connection line201may be connected to the first data line DL1, and the other end of the first connection line201may be connected to the second connection line203. One end of the first connection line201may be connected to the first data line DL1. For example, the second portion201bof the first connection line201may be connected to the first data line DL1at the first contact portion CNT1located in the dummy area DMA.

The third portion201cof the first connection line201may be connected to the second connection line203. According to some example embodiments, the second connection line203may be a portion in which the third portion201cof the first connection line201extends to the peripheral area PA through the dummy area DMA. One end of the second connection line203may be connected to the other end of the first connection line201, and the other end of the second connection line203may be located in the pad area PADA. The other end of the second connection line203may be connected to a pad arranged in the pad area PADA.

One end of the third connection line205may be connected to the second data line DL2, and the other end of the third connection line205may be located in the pad area PADA. One end of the third connection line205may be connected to the second data line DL2in the peripheral area PA or the dummy area DMA. The third connection line205may be a portion in which the second data line DL2extends to the peripheral area PA through the dummy area DMA.

Similarly, the first connection lines201may be located on different layers from the scan lines SL and the data lines DL of the pixels PX. One end of the first connection line201may be connected to the first data line DL1, and the other end of the first connection line201may be connected to the second connection line203. One end of the first connection line201may be connected to the first data line DL1in the dummy area DMA located at the second corner CN2. That is, the second portion201bof the first connection line201may be connected to the first data line DL1at the second contact portion CNT2located in the dummy area DMA.

The first data lines DL1are data lines arranged adjacent to the first corner CN1and the second corner CN2among the data lines DL. The second data lines DL2are data lines other than the first data lines DL1among the data lines DL, that is, data lines that are not connected to the first connection lines201.

The first connection lines201and the second connection lines203may connect first data lines DL1arranged on the left side of a second central line CL2to the pads in the pad area PADA. In this case, the first connection lines201and the second connection lines203may be arranged to be bilaterally symmetrical to the display area DA with respect to the first central line CL1. Because the first connection lines201are arranged in the display area DA and connect the first data lines DL1to the second connection lines203, the peripheral area PA around the first corner CN1and the second corner CN2may be minimized, and thus, a dead area may be reduced in the first corner CN1and the second corner CN2without a reduction in the display area DA.

First data lines DL1of which one ends are located at the first corner CN1may be connected to the first connection lines201and electrically connected to the second connection lines203. First data lines DL1of which one ends are located at the second corner CN2may be connected to the first connection lines201and electrically connected to the second connection lines203. Second data lines DL2spaced a certain distance from the first corner CN1and the second corner CN2may be directly connected to the third connection lines205.

A portion of a first connection line201, which is farthest from the pad area PADA in the second direction D2as described above, among the first connection lines201may be arranged between the first central line CL1and the first data line DL1connected to the first connection line201. For example, the first connection line201may be arranged to be symmetrical to each other with respect to the second central line CL2. In this case, the portion of the first connection line201, which is farthest from the pad area PADA, may be arranged on the second central line CL2. According to some example embodiments, the portion of the first connection line201, which is farthest from the pad area PADA, may be arranged between the first central line CL1and the second central line CL2or between the second central line CL2and the data line DL connected to the first central line CL1, which are shown inFIG.12. Hereinbelow, for convenience of description, a case where the first connection lines201are symmetrical with respect to the second central line CL2will be mainly described in detail.

Each portion of the first connection lines201arranged on both sides with respect to the second central line CL2may extend, as the first portion201aparallel to the scan line SL and the second portion201bparallel to the data line DL alternate with each other. In this case, first connection lines201symmetrical to the first connection lines201with respect to the first central line CL1may have the same structure as the first connection lines201. The first portions201aof the first connection lines201may extend parallel to the scan line SL at a first length corresponding to an interval between two adjacent data lines DL. The second portions201bof the first connection lines201may extend parallel to the data line DL at a second length corresponding to an interval between two adjacent scan lines SL. The first portions201aof the first connection lines201may overlap with or be adjacent to scan line SL. The second portions201bof the first connection lines201may overlap with or be adjacent to the data line DL.

Each portion of the first connection lines201arranged on both sides with respect to the second central line CL2may overall extend in a zigzag manner in a diagonal direction between the first direction D1and the second direction D2, as the first portion201aand the second portion201brepeat. That is, the first connection lines201may overlap scan lines SL in a plurality of rows and overlap data lines DL in a plurality of columns.

The pixels PX may be connected to the scan line SL in each row, and the pixels PX may simultaneously (or concurrently) receive a scan signal. As the first portion201aof the first connection line201extends parallel to one scan line SL at a length n times a distance between adjacent data lines DL, parasitic capacitance may be formed between the first portion201aof the first connection line201and the scan line SL, thereby causing coupling therebetween. Accordingly, a data signal transmitted to the data line DL connected to the first connection line201is changed, and thus deterioration in image quality due to oblique spots may occur.

The first connection lines201may extend in a zigzag manner through the pixels PX in the rows and columns. That is, the first portions201aof the first connection lines201are located in different rows, and thus, a length in which the first portion201aoverlaps the scan line SL in each row may be reduced than a case where the first connection lines201are formed in a straight line. A scan signal is applied to the scan lines SL arranged in different rows at different timings, and parasitic capacitance between the first connection lines201and the scan lines SL is distributed to the rows and thus may be reduced. Therefore, the influence of the scan lines SL on the data signal is minimized, and thus deterioration in image quality due to oblique spots may be prevented.

FIG.13is a schematic plan view of an example of a display panel10C according to some example embodiments.

The arrangement of the first connection lines201in the display panel10C ofFIG.13is different from the arrangement of the first connection lines201in the display panel10A ofFIG.1, and the other configurations are the same. Hereinbelow, configurations different from those ofFIG.1will be mainly described.

Referring toFIG.13, the first connection lines201may be located on different layers from the scan lines SL and the data lines DL of the pixels PX. One end of the first connection line201may be connected to the first data line DL1, and the other end of the first connection line201may be connected to the second connection line203. One end of the first connection line201may be connected to the first data line DL1. For example, the second portion201bof the first connection line201may be connected to the first data line DL1at the first contact portion CNT1located in the dummy area DMA.

The first portion201aand the third portion201cof the first connection line201may be connected to the second connection line203. According to some example embodiments, the second connection line203may be a portion in which the first portion201aor the third portion201cof the first connection line201extends to the peripheral area PA through the dummy area DMA. One end of the second connection line203may be connected to the other end of the first connection line201, and the other end of the second connection line203may be located in the pad area PADA. The other end of the second connection line203may be connected to a pad arranged in the pad area PADA.

One end of the third connection line205may be connected to the second data line DL2, and the other end of the third connection line205may be located in the pad area PADA. The other end of the third connection line205may be connected to a pad arranged in the pad area PADA. One end of the third connection line205may be connected to the second data line DL2in the peripheral area PA or the dummy area DMA. The third connection line205may be a portion in which the second data line DL2extends to the peripheral area PA through the dummy area DMA.

Similarly, the first connection lines201may be located on different layers from the scan lines SL and the data lines DL of the pixels PX. One end of the first connection line201may be connected to the first data line DL1, and the other end of the first connection line201may be connected to the second connection line203. One end of the first connection line201may be connected to the first data line DL1in the dummy area DMA located at the second corner CN2. That is, the second portion201bof the first connection line201may be connected to the first data line DL1at the second contact portion CNT2located in the dummy area DMA.

The first data lines DL1are data lines arranged adjacent to the first corner CN1and the second corner CN2among the data lines DL. The second data lines DL2are data lines other than the first data lines DL1among the data lines DL, that is, data lines that are not connected to the first connection lines201.

The first connection lines201and the second connection lines203may connect first data lines DL1arranged on the left side of the first central line CL1to the pads in the pad area PADA. In this case, the first connection lines201and the second connection lines203may be arranged to be bilaterally symmetrical to the display area DA with respect to the first central line CL1. Because the first connection lines201are arranged in the display area DA and connect the first data lines DL1to the second connection lines203, the peripheral area PA around the first corner CN1and the second corner CN2may be minimized, and thus, a dead area may be reduced in the first corner CN1and the second corner CN2without a reduction in the display area DA.

The first data lines DL1of which one ends are located at the first corner CN1may be connected to the first connection lines201and electrically connected to the second connection lines203. The first data lines DL1of which one ends are located at the second corner CN2may be connected to the first connection lines201and electrically connected to the second connection lines203. The second data lines DL2spaced a certain distance from the first corner CN1and the second corner CN2may be directly connected to the third connection lines205.

The first connection lines201as described above may be formed as opposed to that shown inFIG.1. For example, the first connection line201may include the first portion201aextending in the first direction D1, the second portion201bextending in the second direction D2, and the third portion201cconnecting the first connection line201to the second connection line203.

In this case, the first portion201aand the second portion201bmay be alternately repeated and connected to each other. At this time, a first portion201aconnected to the third portion201cmay be arranged at a distance farthest from the pad area PADA, compared to other first portions201aarranged in other areas. In addition, a first portion201aconnected to the first contact portion CNT1may be arranged at a distance closest to the pad area PADA. In the case described above, a portion of the first connection line201, which is closest to the first central line CL1, may be farthest from the pad area PADA, compared to other portions of the first connection line201.

The first connection lines201as described above may be arranged to be symmetrical with respect to the first central line CL1. In this case, the first connection lines201may have a shape similar to the shape shown inFIGS.9A and9B. In addition, the first connection lines201may be arranged in the shape shown inFIGS.10A to10C.

Accordingly, in the display panel10C, a scan signal is applied to the scan lines SL arranged in different rows at different timings, and parasitic capacitance between the first connection lines201and the scan lines SL is distributed to the rows and thus may be reduced. Therefore, the influence of the scan lines SL on the data signal is minimized, and thus deterioration in image quality due to oblique spots may be prevented.

FIG.14is a perspective view of a display device1including a display panel according to some example embodiments.FIGS.15A and15Bare cross-sectional views of the display device1taken along a line V-V′.

Referring toFIGS.14to15B, the display device1may include a transmission area OA, a display area DA, an intermediate area MA between the transmission area OA and the display area DA, and a peripheral area PA surrounding the display area DA. The display device1may provide a certain image by using light emitted from a plurality of pixels arranged in the display area DA.FIG.14illustrates that one transmission area OA is arranged inside the display area DA, and the transmission area OA may be entirely surrounded by the display area DA. The transmission area OA may be an area in which a component to be described later with reference toFIGS.15A and15Bis arranged. According to some example embodiments, the transmission area OA may be a transmission area in which holes through at least one element of the display device1is formed. According to some example embodiments, the transmission area OA may be a transmission area in which at least one element of the display device1does not include a hole.

The intermediate area MA may be arranged between the transmission area OA and the display area DA, and the display area DA may be surrounded by the peripheral area PA. The intermediate area MA and the peripheral area PA may be non-display areas in which pixels are not arranged. The intermediate area MA may be entirely surrounded by the display area DA, and the display area DA may be entirely surrounded by the peripheral area PA.

Referring toFIG.15A, the display device1may include a display panel10, an input sensing layer40arranged on the display panel10, and an optical functional layer50, which may be covered by a window60. The display device1may be various types of electronic devices such as mobile phones, laptop computers, and smartwatches.

The display panel10may be the display panel10A shown inFIG.1, the display panel10B shown inFIG.12, and the display panel10C shown inFIG.13. The display panel10will be described later with reference toFIGS.17A to17D.

The input sensing layer40may be located on the display panel10. The input sensing layer40may obtain coordinate information according to an external input, for example, a touch event. The input sensing layer40may include a sensing electrode (or touch electrode) and trace lines connected to the sensing electrode. The input sensing layer40may sense an external input using a mutual capacitance method and/or a self-capacitance method.

The input sensing layer40may be directly formed on the display panel10or may be separately formed and then coupled to the display panel10through an adhesive layer such as an optical clear adhesive. For example, the input sensing layer40may be continuously formed after a process of forming the display panel10, in which case, the input sensing layer40may be understood as a portion of the display panel10, and an adhesive layer may not be between the input sensing layer40and the display panel10. ThoughFIG.15Aillustrates that the input sensing layer40is between the display panel10and the optical functional layer50, according to some example embodiments, the input sensing layer40may be arranged on the optical functional layer50.

The optical functional layer50may include a reflection prevention layer. The reflection prevention layer may reduce reflectance of light (external light) incident from the outside toward the display panel10through the window60. The reflection prevention layer may include a retarder and a polarizer. The retarder may include a film-type retarder or a liquid crystal-type retarder, and may include a λ/2 retarder and/or a λ/4 retarder. The polarizer may include a film-type polarizer or a liquid crystal-type polarizer. The film-type polarizer may include a stretchable synthetic resin, and the liquid crystal-type polarizer may include liquid crystals arranged in a certain arrangement. The retarder and the polarizer each may further include a protection film. The protection films of the retarder and the polarizer may be defined as a base layer of the reflection prevention layer.

According to some example embodiments, the reflection prevention layer may include a black matrix and color filters. The color filters may be arranged considering colors of light emitted from each of the pixels of the display panel10. Each of the color filters may include a red, green, or blue pigment or dye. Alternatively, each of the color filters may further include quantum dots other than the aforementioned pigment or dye. Alternatively, some of the color filters may not include the aforementioned pigment or dye, and may include scattering particles such as titanium oxide.

According to some example embodiments, the reflection prevention layer may include a destructive interference structure. The destructive interference structure may include a first reflection layer and a second reflection layer arranged on different layers. A first reflected light and a second reflected light reflected respectively from the first reflection layer and the second reflection layer may destructively interfere with each other, and thus reflectance of external light may be reduced.

The optical functional layer50may include a lens layer. The lens layer may improve light output efficiency of light emitted from the display panel10or reduce color deviation. The lens layer may include a layer having a concave or convex lens shape, and/or a plurality of layers having different refractive indices. The optical functional layer50may include all of the aforementioned reflection prevention layer and the lens layer, or may include any one of the reflection prevention layer and the lens layer.

According to some example embodiments, the optical functional layer50may be continuously formed after a process of forming the display panel10and/or the input sensing layer40. In this case, an adhesive layer may not be between the optical functional layer50and the display panel10and/or between the display panel10and the input sensing layer40.

The display panel10, the input sensing layer40, and/or the optical functional layer50each may include an opening. In this regard,FIG.15Aillustrates that the display panel10, the input sensing layer40, and the optical functional layer50include a first opening10H, a second opening40H, and a third opening50H, respectively, and the first to third openings10H,40H, and50H overlap each other. The first to third openings10H,40H, and50H may be located to correspond to a first area OA. According to some example embodiments, one or more of the display panel10, the input sensing layer40, and the optical functional layer50may not include openings. For example, any one or two elements selected from among the display panel10, the input sensing layer40, and the optical functional layer50may not include openings. Alternatively, the display panel10, the input sensing layer40, and the optical functional layer50may not all include openings as shown inFIG.15B.

As described above, the transmission area OA may be a component area (e.g., a sensor area, a camera area, a speaker area, etc.) in which a component20for adding various functions to the display device1is located. The component20may be located in the first to third openings10H,40H, and50H as shown inFIG.15A. Alternatively, the component20may be located under the display panel10as shown inFIG.15B.

The component20may include an electronic element. For example, the component20may be an electronic element using light or sound. For example, the electronic element may be a sensor that outputs and/or receives light, such as an infrared sensor, a camera that captures an image by receiving light, a sensor that measures a distance or recognizes a fingerprint by outputting and sensing light or sound, a small lamp that outputs light, a speaker that outputs sound, etc. The electronic element using light may use light in various wavelength bands such as visible light, infrared light, ultraviolet light, etc. In some embodiments, the first area OA may be understood as a transmission area through which light and/or sound output from the component20to the outside or traveling toward the electronic element from the outside may be transmitted.

According to some example embodiments, when the display device1is used as a smartwatch or an instrument panel for a vehicle, the component20may be a member such as clock hands or needles indicating certain information (e.g., vehicle speed, etc.). When the display device1includes clock hands or an instrument panel for a vehicle, the component20may be exposed to the outside through the window60, and the window60may include an opening corresponding to the first area OA.

The component20may include element(s) related to the functions of the display panel10as described above or may include elements such as accessories that improve the aesthetics of the display panel10. According to some example embodiments, an optical clear adhesive or the like may be between the window60and the optical functional layer50.

FIGS.16A to16Dare schematic cross-sectional views of a display panel10according to some example embodiments.

Referring toFIG.16A, the display panel10may include a display layer400arranged on a substrate100. The display layer400may include layers between the substrate100and a thin-film encapsulation layer500.

The substrate100may include a glass material or a polymer resin. The substrate100may include various flexible or bendable materials. When the substrate100includes a polymer resin, the substrate100may include a multi-layer. For example, as shown in the enlarged view ofFIG.16A, the substrate100may include a first base layer101, a first barrier layer102, a second base layer103, and a second barrier layer104.

The first base layer101and the second base layer103each may include a polymer resin. For example, the first base layer101and the second base layer103may include a polymer resin such as PES, PAR, PEI, PEN, PET, PPS, PI, PC, cellulose triacetate (TAC), CAP, etc. The first base layer101and the second base layer103each may include a transparent polymer resin.

The first barrier layer102and the second barrier layer104are barrier layers that prevent penetration of external foreign substances and may include a single layer or a multi-layer including an inorganic material such as silicon nitride and silicon oxide.

The display layer400may include a plurality of pixels. The display layer400may include a display element layer400A including display elements arranged for each pixel, and a pixel circuit layer400B including a pixel circuit and insulating layers arranged for each pixel. Each pixel circuit may include a transistor and a storage capacitor, and each display element may include an organic light-emitting diode (OLED).

The display elements of the display layer400may be covered by an encapsulation member such as the thin-film encapsulation layer500, and the thin-film encapsulation layer500may include at least one inorganic encapsulation layer and at least one organic encapsulation layer. When the display panel10includes a substrate100including a polymer resin, and a thin-film encapsulation layer500including an inorganic encapsulation layer and an organic encapsulation layer, flexibility of the display panel10may be improved.

The display panel10may include a first opening10H penetrating the display panel10. The first opening10H may be located in the transmission area OA.FIG.16Aillustrates that the substrate100and the thin-film encapsulation layer500includes through holes100H and500H corresponding to the first opening10H of the display panel10, respectively. The display layer400may include a through hole400H corresponding to the transmission area OA.

According to some example embodiments, the substrate100may not include a through hole corresponding to the transmission area OA as shown inFIG.16B. The thin-film encapsulation layer500may not include the through hole corresponding to the transmission area OA. According to some example embodiments, as shown inFIG.16C, the display layer400may not include the through hole400H corresponding to the transmission area OA, and the display element layer400A may not be located in the transmission area OA.

ThoughFIGS.16A to16Cillustrate that the display element layer400A is not arranged in the transmission area OA, the embodiments according to the present disclosure are not limited thereto. According to some example embodiments, as shown inFIG.16D, an auxiliary display element layer400C may be located in the transmission area OA. The auxiliary display element layer400C may include a display element operating with a different structure and/or in a different method from the display element of the display element layer400A.

According to some example embodiments, each pixel of the display element layer400A may include an active organic light-emitting diode, and the auxiliary display element layer400C may include pixels each including a passive organic light-emitting diode. When the auxiliary display element layer400C includes a display element of the passive organic light-emitting diode, elements constituting a pixel circuit may not exist under the passive organic light-emitting diode. For example, a transistor and a storage capacitor are not included in a portion of the pixel circuit layer400B under the auxiliary display element layer400C.

According to some example embodiments, the auxiliary display element layer400C may include a display element of the same type (e.g., an active organic light-emitting diode) as the display element layer400A, but a pixel circuit thereunder may have a different structure. For example, the pixel circuit (e.g., a pixel circuit having a light-shielding layer between a substrate and a transistor, etc.) under the auxiliary display element layer400C may have a different structure from the pixel circuit under the display element layer400A. Alternatively, the display elements of the auxiliary display element layer400C may operate according to a control signal different from a control signal by which the display elements of the display element layer400A operate. A component (e.g., an infrared sensor, etc.) that does not require a relatively high transmittance may be arranged in the transmission area OA in which the auxiliary display element layer400C is arranged. In this case, the transmission area OA may be understood as both a component area and an auxiliary display area.

FIGS.17A to17Dare schematic cross-sectional views of a display panel10′ according to some example embodiments.

Unlike the display panel10described above with reference toFIGS.16A to16Dhaving the thin-film encapsulation layer500, the display panel10′ ofFIGS.17A to17Dmay include an encapsulation substrate500A and a sealant540.

As shown inFIGS.17A to17C, one or more of the substrate100, the display layer400, and the encapsulation substrate500A may include through holes100H,400H, and500AH corresponding to the transmission area OA. The display element layer400A may not be arranged in the transmission area OA, or the auxiliary display element layer400C may be arranged in the transmission area OA as shown inFIG.17D. The auxiliary display element layer400C is as described above with reference toFIG.16D.

The first connection lines201according to embodiments may have various shapes to minimize a wire resistor condenser without recognition of oblique spots due to coupling capacitance (parasitic capacitance) with the scan line SL. The first connection lines201each may have various shapes in which a portion extending in the first direction D1, a portion extending in the second direction D2, and a portion extending in a diagonal direction are mixed. The portions of the first connection lines201extending in the diagonal direction may have a zigzag shape (seeFIG.1,12, or13) in which a first sub-portion and a second sub-portion are repeated.

The structure of the first connection line201according to embodiments is not limited to the aforementioned display device and may be applied to display devices, in which an edge of a display area has at least one round corner, such as smartwatches or instrument panels for vehicles.

According to one or more embodiments, a display device, in which a dead area is reduced by connection lines in a display area and a data signal may be stably transmitted to pixels without an increase in manufacturing cost, may be provided. However, the scope of the embodiments is not limited to the above effect.

It should be understood that embodiments described herein should be considered in a descriptive sense only and not for purposes of limitation. Descriptions of features or aspects within each embodiment should typically be considered as available for other similar features or aspects in other embodiments. While one or more embodiments have been described with reference to the figures, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope as defined by the following claims.