Patent ID: 12243813

DETAILED DESCRIPTION OF THE EXAMPLE EMBODIMENTS

The following will now describe a connection structure for a semiconductor package and a method of forming the same according to example embodiments of the inventive concepts in conjunction with the accompanying drawings.

The advantages and aspects of the inventive concepts will be apparent through the appended claims and the specification discussed with reference to the accompanying drawings. The inventive concepts are distinctly claimed and particularly pointed out in the claims. However, the inventive concepts may best be understood by reference to the specification in conjunction with the accompanying drawings. In the specification, like reference numerals refer to like components throughout the accompanying drawings.

It will be understood that when an element or layer is referred to as being “over,” “above,” “on,” “connected to” or “coupled to” another element or layer, it can be directly over, above, on, connected or coupled to the other element or layer or intervening elements or layers may be present. In contrast, when an element is referred to as being “directly over,” “directly above,” “directly on,” “directly connected to” or “directly coupled to” another element or layer, there are no intervening elements or layers present. Like numerals refer to like elements throughout.

Spatially relative terms, such as “beneath,” “below,” “lower,” “over,” “above,” “upper” and the like, may be used herein for ease of description to describe one element's or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as “below” or “beneath” other elements or features would then be oriented “above” the other elements or features. Thus, the term “below” can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

FIGS.1A to1Gillustrate cross-sectional views showing a method of forming a connection structure for a semiconductor package according to example embodiments.FIG.1Hillustrates an enlarged cross-sectional view showing a portion ofFIG.1G.

Referring toFIG.1A, a carrier substrate100may be provided. The carrier substrate100may be a rigid substrate including a conductive material, a semiconductor material, or a dielectric material. For example, the carrier substrate100may be a bare silicon wafer or a glass substrate. A lower passivation layer105may be formed on the carrier substrate100.

The lower passivation layer105may include a dielectric material. For example, the lower passivation layer105may be formed by depositing silicon oxide, silicon nitride, or polymer. A dielectric material may be deposited on the lower passivation layer105, and then, patterned to form a first passivation layer110having one or more first openings111.

The first passivation layer110may include a material the same as or similar to that of the lower passivation layer105. For example, the first passivation layer110may include silicon oxide, silicon nitride, or polymer. Each of the first openings111may partially reveal the lower passivation layer105. When viewed in plan, each of the first openings111may have a circular shape, an elliptical shape, a rectangular shape, a polygonal shape, or an arbitrary shape.

An adhesive layer101may further be provided between the carrier substrate100and the lower passivation layer105. The adhesive layer101may be a photosensitive adhesive. In the following descriptions, the adhesive layer101will be omitted in the interest of brevity.

Referring toFIG.1B, the carrier substrate100may be provided thereon with a first seed layer112ahaving a relatively smaller thickness and a first conductive layer114ahaving a relatively larger thickness. The first seed layer112amay cover the first passivation layer110, and also cover the lower passivation layer105that is partially exposed through the first openings111. The first conductive layer114amay have a thickness sufficient enough to cover the first seed layer112aand fill the first openings111.

The first seed layer112amay be formed by plating or depositing metal or its alloy, such as copper (Cu), titanium (Ti), a combination thereof, or an alloy thereof, the same as or similar to that of the first conductive layer114a. The first conductive layer114amay be formed by an electroplating process using the first seed layer112a. The first conductive layer114amay include, for example, copper (Cu), aluminum (Al), nickel (Ni), gold (Au), silver (Ag), platinum (Pt), a combination thereof, or an alloy thereof.

Referring toFIG.1C, the first seed layer112aand the first conductive layer114amay be converted respectively into first seed patterns112and first conductive patterns114. For example, the first seed layer112amay be patterned to form the first seed patterns112separated from one another. Likewise, the first conductive layer114amay be patterned to form the first conductive patterns114separated from one another. The first seed layer112aand the first conductive layer114amay be patterned at the same time. The first conductive patterns114may fill corresponding first openings111and partially protrude upwardly from the first passivation layer110. The first seed patterns112may be provided below corresponding first conductive patterns114. For example, the first seed patterns112may cover bottom surfaces of the corresponding first conductive patterns114.

Each of the first conductive patterns114may have a “T” shape when viewed in cross-section. When viewed in cross-section, each of the first seed patterns112may have a curved shape that extends along the bottom surface of the corresponding first conductive pattern114. When viewed in plan, each of the first seed pattern112and the first conductive pattern114may have a circular shape, an elliptical shape, a rectangular shape, a polygonal shape, or an arbitrary shape.

Referring toFIG.1D, a second passivation layer120may be formed to cover the first passivation layer110. For example, a dielectric material may be deposited on the first passivation layer110, and then, patterned to form the second passivation layer120having one or more second openings121. The second passivation layer120may include a material the same as or similar to that of the first passivation layer110. For example, the second passivation layer120may include silicon oxide, silicon nitride, or polymer. Each of the second openings121may partially reveal the first conductive pattern114therebelow. When viewed in plan, each of the second openings121may have a circular shape, an elliptical shape, a rectangular shape, a polygonal shape, or an arbitrary shape.

Referring toFIG.1E, the second passivation layer120may be provided thereon with a second seed layer122ahaving a relatively smaller thickness and a second conductive layer124ahaving a relatively larger thickness. The second seed layer122amay cover the second passivation layer120, and also cover the first conductive patterns114that are partially exposed through the second openings121. The second conductive layer124amay have a thickness sufficient enough to cover the second seed layer122aand fill the second openings121.

The formation of the second seed layer122aand the second conductive layer124amay be the same as or similar to that of the first seed layer112aand the first conductive layer114adiscussed above with reference toFIG.1B. For example, the second seed layer122amay be formed by plating or depositing metal or its alloy, such as copper (Cu), titanium (Ti), a combination thereof, or an alloy thereof. The second conductive layer124amay be formed by an electroplating process in which the second seed layer122ais used to plate metal, such as copper (Cu) or its alloy.

Referring toFIG.1F, the second seed layer122aand the second conductive layer124amay be patterned at the same time. Therefore, the second seed layer122amay be formed into second seed patterns122separated from one another. Likewise, the second conductive layer124amay be formed into second conductive patterns124separated from one another. The second conductive patterns124may fill corresponding second openings121and have electrical connection with corresponding first conductive patterns114. The second seed patterns122may be provided below corresponding second conductive patterns124.

Each of the second conductive patterns124may have a line segment that horizontally extends on the second passivation layer120and a via segment that vertically penetrates the second passivation layer120. When viewed in cross-section, each of the second seed patterns122may have a curved shape that extends along a bottom surface of the corresponding second conductive pattern124.

Referring toFIG.1G, processes identical or similar to those discussed above with reference toFIGS.1A to1C or1D to1Fmay be performed to form on the second passivation layer120a third passivation layer130, third seed patterns132, and third conductive patterns134. The third conductive patterns134may be electrically connected to corresponding second conductive patterns124. A fourth passivation layer140, fourth seed patterns142, and fourth conductive patterns144may be formed on the third passivation layer130. The fourth conductive patterns144may be electrically connected to corresponding third conductive patterns134.

A first connection structure11may be provided through the processes discussed above. The first connection structure11may be formed in a wafer level or a chip level. For example, when the carrier substrate100is a bare silicon wafer or a glass substrate whose size (e.g., diameter) is identical or similar to that of the bare silicon wafer, a dicing process may further be performed to separate the wafer-level carrier substrate100into a plurality of chip-level first connection structures11.

Because the first connection structure11includes the rigid carrier substrate100, the first connection structure11may have mechanical and structural stability. Therefore, the first connection structure11may be prevented from warpage and/or damage, and also be easily handled in subsequent processes. The first connection structure11may be worked in subsequent processes, and then, utilized as a package substrate for a semiconductor package or an interposer substrate for any other semiconductor devices. These utilizations will be discussed below with reference toFIGS.3A to3D and4A to4F.

For the first connection structure11, the first conductive pattern114may serve as an under-bump-metal (UBM) to which a terminal, such as a solder ball, is to be attached. In contrast, each of the second and third conductive patterns124and134may serve as a redistribution layer electrically connected to the first conductive pattern114. The fourth conductive pattern144may be electrically connected to the first conductive pattern114through the second and third conductive patterns124and134, and may be used as a connection pad to which a terminal, such as a solder ball or a solder bump, is to be attached. For another example, the fourth conductive pattern144may serve as a redistribution layer.

In certain embodiments, the third conductive patterns134and/or the fourth conductive patterns144may not be formed. For example, the first connection structure11may include the first conductive patterns114serving as under-bump-metals (UBMs) and the second conductive patterns124serving as redistribution layers, but include neither the third conductive patterns134nor the fourth conductive patterns144. For another example, the first connection structure11may include the first conductive patterns114serving as under-bump-metals (UBMs), the second conductive patterns124serving as redistribution layers, and the fourth conductive patterns144serving as connection pads, but not include the third conductive patterns134. In other embodiments, the first connection structure11may further include conductive patterns serving as redistribution layers between the third conductive patterns134and the fourth conductive patterns144.

Each of the first, second, third, and fourth conductive patterns114,124,134, and144may have a head segment that horizontally extends on a corresponding one of the first, second, third, and fourth passivation layers110,120,130, and140, and a tail segment that vertically penetrates the corresponding one of the first, second, third, and fourth passivation layers110,120,130, and140. The head and tail segments of the first conductive pattern114may be integrally merged to constitute a single under-bump-metal (UBM). Differently, the tail segment of each of the second, third, and fourth conductive patterns124,134, and144may serve as a via. The head segment of each of the second and third conductive patterns124and134may be a redistribution layer, and the head segment of the fourth conductive pattern144may be a connection pad.

Referring toFIG.1H, the first conductive pattern114may have a thickness greater than those of the second, third, and fourth conductive patterns124,134, and144. For convenience of description, the first seed pattern112may be a constituent element included in the first conductive pattern114. This explanation will also be applicable to the second, third, and fourth conductive patterns124,134, and144.

The first conductive pattern114may have a first thickness T1greater than second, third, and fourth thicknesses T2, T3, and T4respectively of the second, third, and fourth conductive patterns124,134, and144. The second, third, and fourth thicknesses T2, T3, and T4may be the same or similar to each other. Alternatively, the second and third thicknesses T2and T3may be the same or similar to each other, and the fourth thickness T4may be greater or less than each of the second and third thicknesses T2and T3. The first thickness T1may indicate a total thickness of the first conductive pattern114, and each of the second, third, and fourth thicknesses T2, T3, and T4may indicate a thickness of a substantial portion, i.e., the head segment of a corresponding one of the second, third, and fourth conductive patterns124,134, and144.

The first, second, third, and fourth passivation layers110,120,130, and140may have different thicknesses from each other. For example, the first passivation layer110may have a first thickness Tp1the same as or similar to a third thickness Tp3of the third passivation layer130and a fourth thickness Tp4of the fourth passivation layer140. Alternatively, the first thickness Tp1may be greater or less than each of the third and fourth thicknesses Tp3and Tp4. The second passivation layer120may have a second thickness Tp2greater than each of the first, third, and fourth thicknesses Tp1, Tp3, and Tp4. Differently, the first, second, third, and fourth passivation layers110,120,130, and140may have the same or similar thickness.

Referring back toFIG.1G, as discussed above with reference toFIGS.1A to1D, the first conductive patterns114may be formed after the first passivation layer110is formed, and then, on the first passivation layer110, the second passivation layer120may be formed to cover the first conductive patterns114. Although the first conductive patterns114are thicker than the second, third, and fourth conductive patterns124,134, and144as discussed above with reference toFIG.1H, because the first passivation layer110is previously formed to surround the tail segments of the first conductive patterns114, the second passivation layer120may be formed to cover only the head segment of the first conductive pattern114, in which case the head segment has a thickness less than the first thickness T1of the first conductive pattern114. As a result, the second passivation layer120may be formed flat without undulation (or wavy shape) which will be discussed below.

Differently from that mentioned above, when a certain passivation layer is formed to cover the first conductive patterns114after the first conductive patterns114are formed relatively thick either on the carrier substrate100or on the lower passivation layer105, it may be likely that the certain passivation layer has undulation between neighboring first conductive patterns114. In case that the second conductive patterns124are formed on the certain passivation layer, the second conductive patterns124may bend along the undulation of the certain passivation layer. The certain passivation layer having the undulation may bring pattern abnormality to the second conductive patterns124formed on the certain passivation layer, and further cause pattern abnormality of any other conductive patterns formed on the second conductive patterns124. Such pattern abnormality of conductive patterns may lead to an electrical short or open between the conductive patterns.

According to example embodiments, because the first passivation layer110is formed before the first conductive patterns114, and then, the second passivation layer120is formed to cover the first conductive patterns114, the second passivation layer120may have a flat shape without undulation. Thus, conductive patterns may be prevented from problems such as pattern abnormality caused by undulations of passivation layers.

FIGS.2A to2Cillustrate cross-sectional views showing examples of the connection structure shown inFIG.1Gfor a semiconductor package according to example embodiments.

Referring toFIG.2A, a second connection structure12may be provided to further include at least one first dummy pattern114dand/or at least one second dummy pattern124d. For example, one or more first dummy patterns114dmay be formed simultaneously with the first conductive patterns114. Similarly, one or more second dummy patterns124dmay be formed simultaneously with the second conductive patterns124. Although not shown, third dummy patterns may further be formed on the third passivation layer130.

Each of the first dummy patterns114dmay be provided on the first passivation layer110between neighboring first conductive patterns114. The first seed patterns112may be provided between the first passivation layer110and the first dummy patterns114d. The first dummy patterns114dmay forbid the second passivation layer120to have undulation between the first conductive patterns114. When viewed in plan, each of the first dummy patterns114dmay have a rectangular shape, a polygonal shape, a circular shape, an elliptical shape, or an arbitrary shape.

Each of the second dummy patterns124dmay be provided on the second passivation layer120between neighboring second conductive patterns124. The second seed patterns122may be provided between the second passivation layer120and the second dummy patterns124d. The second dummy patterns124dmay forbid the third passivation layer130to have undulation between the second conductive patterns124. When viewed in plan, each of the second dummy patterns124dmay have a rectangular shape, a polygonal shape, a circular shape, an elliptical shape, or an arbitrary shape.

Referring toFIG.2B, a third connection structure13may be provided to further include first, second, third, and fourth additional patterns114g,124g,134g, and144g. For example, one or more first additional patterns114gmay be formed simultaneously with the first conductive patterns114. Each of the first additional patterns114gmay be provided on the first passivation layer110between neighboring first conductive patterns114. The first seed patterns112may be provided between the first passivation layer110and the first additional patterns114g. The position of the first additional patterns114gmay not be limited between the first conductive patterns114.

Similarly, the second, third, and fourth passivation layers120,130, and140may be respectively provided thereon with the second, third, and fourth additional patterns124g,134g, and144gthat are electrically connected to the first additional patterns114g. The second, third, and fourth additional patterns124g,134g, and144gmay be formed simultaneously with the second, third, and fourth conductive patterns124,134, and144, respectively. The first, second, third, and fourth additional patterns114g,124g,134g, and144gmay serve as conductive patterns either for electrical power delivery or for electrical ground. The first, second, and third additional patterns114g,124g, and134gmay prevent pattern abnormality such as undulation occurring when the second, third, and fourth passivation layers120,130, and140are formed.

The first, second, third, and fourth additional patterns114g,124g,134g, and144gmay have their planar shapes the same as or similar to those of the first, second, third, and fourth conductive patterns114,124,134, and144, respectively. For example, when viewed in plan, the first additional patterns114gmay have a shape, such as a circular shape, the same as or similar to that of the first conductive patterns114.

Referring toFIG.2C, a fourth connection structure14may be provided devoid of the lower passivation layer105. For example, the first passivation layer110may be formed directly on the carrier substrate100, or an adhesive layer (see101ofFIG.1) may be provided to form the first passivation layer110on the carrier substrate100. Optionally, the first dummy patterns114dand the second dummy patterns124dmay further be formed. Instead of the first and second dummy patterns114dand124d, the first to fourth additional patterns114gto144gmay further be formed as shown inFIG.2B.

FIGS.3A to3Dillustrate cross-sectional views showing a method of fabricating a semiconductor package according to example embodiments.

Referring toFIG.3A, a semiconductor chip200may be provided on the first connection structure11. The semiconductor chip200may include a memory circuit, a logic circuit, or a combination thereof. The semiconductor chip200may include chip pads210corresponding to the fourth conductive patterns114. Connection terminals220, such as solder balls, may be provided between the chip pads210and the fourth conductive patterns144. The semiconductor chip200may be electrically connected through the connection terminals220to the first connection structure11.

Referring toFIG.3B, a molding layer240may be formed on the first connection structure11, covering the semiconductor chip200. The molding layer240may include an epoxy molding compound (EMC). Optionally, before the molding layer240is formed, an under-fill layer230may further be formed between the first connection structure11and the semiconductor chip200. The under-fill layer230may include a material the same as or similar to that of the molding layer240.

Referring toFIG.3C, the carrier substrate100may be removed. When the carrier substrate100and the lower passivation layer105have therebetween the adhesive layer101shown inFIG.1A, the adhesive layer101may be irradiated with laser or ultraviolet radiation to detach the carrier substrate100from the lower passivation layer105. A patterning process may be performed on the lower passivation layer105that is revealed due to the detachment of the carrier substrate100, and thus, openings106may be formed to expose the first conductive patterns114. For example, the openings106may be formed by performing an etching process on the lower passivation layer105. Therefore, the openings106may establish locations on which external terminals are to be formed (see108ofFIG.3D), as will be discussed below. An etching process may be optionally performed to remove a portion of the first seed pattern112which is exposed through the opening106.

Referring toFIG.3D, external terminals108may be formed to have electrical connection with the first conductive patterns114. For example, a solder may be provided and reflowed to form the external terminals108, such as solder balls, corresponding to the first conductive patterns114. Hence, a semiconductor package1may be fabricated to include the semiconductor chip200mounted on the first connection structure11. The first connection structure11may serve as a package substrate of the semiconductor package1.

As discussed above with reference toFIG.3C, a portion of the first seed pattern112exposed through the opening106may be removed. Accordingly, the first seed pattern112may not be provided between the first conductive pattern114and the external terminal108. In this case, an intermetallic compound may not be created at an interface between the first conductive pattern114and the external terminal108. Additionally or alternatively, the solder used for the formation of the external terminal108may have improved wettability on the first conductive pattern114. The partial removal of the first seed pattern112may not be an essential process, and accordingly, may be omitted if not necessary.

FIGS.4A to4Fillustrate cross-sectional views showing examples of the semiconductor package shown inFIG.3Daccording to example embodiments.

Referring toFIG.4A, a semiconductor package2may be provided to include the semiconductor chip200mounted on the first connection structure11serving as a package substrate. A portion of the first seed pattern112exposed through the opening106may not be removed. Accordingly, the first seed pattern112may be interposed between the first conductive pattern114and the external terminal108.

The first connection structure11may be replaced with one of the second, third, and fourth connection structures12,13, and14, as will be discussed below with reference toFIGS.4B to4E. This detailed description may be as follows.

Referring toFIG.4B, a semiconductor package3may be provided to include the semiconductor chip200mounted on the second connection structure12serving as a package substrate. As discussed above with reference toFIG.2A, the second connection structure12may include one or more first dummy patterns114dformed on the first passivation layer110between neighboring first conductive patterns114, and one or more second dummy patterns124dformed on the second passivation layer120between neighboring second conductive patterns124. The first and second dummy patterns114dand124dmay be electrically isolated, and thus, may have no participation in electrical connection between the second connection structure12and the semiconductor chip200. As discussed above with reference toFIG.2A, the first and second dummy patterns114dand124dmay prevent pattern abnormality such as undulation occurring when the second and third passivation layers120and130are formed.

Referring toFIG.4C, a semiconductor package4may be provided to include the semiconductor chip200mounted on the third connection structure13serving as a package substrate. As discussed above with reference toFIG.2B, the third connection structure13may include the first, second, third, and fourth additional patterns114g,124g,134g, and144gformed respectively on the first, second, third, and fourth passivation layers110,120,130, and140. The first, second, third, and fourth additional patterns114g,124g,134g, and144gmay serve as conductive patterns required to provide power to the semiconductor chip200or to electrically ground the semiconductor chip200. As discussed above with reference toFIG.2B, the first, second, and third additional patterns114g,124g, and134gmay prevent pattern abnormality such as undulation occurring when the second, third, and fourth passivation layers120,130, and140are formed.

Referring toFIG.4D, a semiconductor package5may be provided to include the semiconductor chip200mounted on the fourth connection structure14serving as a package substrate. As discussed above with reference toFIG.2C, the fourth connection structure14may include the first dummy patterns114dformed on the first passivation layer110and/or the second dummy patterns124dformed on the second passivation layer120. Alternatively, the semiconductor package5may include, instead of the first and second dummy patterns114dand124d, the first to fourth additional patterns114gto144gformed respectively on the first to fourth passivation layers110to140, as shown inFIG.2B.

Referring toFIG.4E, a semiconductor package6may be configured identically or similarly to the semiconductor package5shown inFIG.4D. Differently from the semiconductor package5, the first passivation layer110may be partially etched and becomes thinner. For example, the first passivation layer110may undergo an etching process to remove surface damages or foreign substances from the first passivation layer110that are possibly produced when the carrier substrate100is detached from the first passivation layer110in the fourth connection structure14ofFIG.2C. Additionally or alternatively, the etching process may be performed to reduce a thickness of the first passivation layer110.

When the first passivation layer110decreases in thickness, the first conductive patterns114may protrude outwardly from the thinned first passivation layer110. The protrusion of the first conductive patterns114may increase contact areas between the first conductive patterns114and the external terminals108. The increased contact areas may reduce contact resistances between the first conductive patterns114and the external terminals108.

Referring toFIG.4F, a semiconductor package7may be provided to include the semiconductor chip200and a semiconductor package30that are mounted on the first connection structure11serving as a package substrate. The semiconductor package7may have a package-in-package configuration in which the semiconductor package30is mounted within the semiconductor package1ofFIG.3D. The first connection structure11may be replaced with one of the second, third, and fourth connection structures12,13, and14shown inFIGS.4B to4E.

The semiconductor package30may include one or more semiconductor chips320and330mounted on a package substrate300, bonding wires350that electrically connect the semiconductor chips320and330to the package substrate300, and a molding layer340that encapsulates the semiconductor chips320and330. The semiconductor package30may be provided within the molding layer240encapsulating the semiconductor chip200.

Some of the fourth conductive patterns144may be used for electrical connection between the first connection structure11and the semiconductor chip200. Others of the fourth conductive patterns144may be used for electrical connection between the first connection structure11and the semiconductor package30. For example, the first connection structure11and the semiconductor chip200may be electrically connected to each other through the connection terminals220, such as solder balls, between the chip pads210of the semiconductor chip200and some of the fourth conductive patterns144. The first connection structure11and the semiconductor package30may be electrically connected to each other through connection terminals360, such as solder balls, between the package substrate300and others of the fourth conductive patterns144.

The package substrate300may include an internal pattern302to which the bonding wires350and the connection terminals360are electrically connected. The internal pattern302may be configured identically or similarly to the first connection structure11. For example, the internal pattern302may include a lower conductive pattern314coupled to the connection terminal360, an upper conductive pattern334coupled to the bonding wire350, and an intermediate conductive pattern324electrically connecting the lower and upper conductive patterns314and334to each other.

The lower conductive pattern314may correspond to the first conductive pattern114, the upper conductive pattern334may correspond to the fourth conductive pattern144, and the intermediate conductive pattern324may correspond either to the second conductive pattern124or the third conductive pattern134. The formation of the package substrate300may be the same as or similar to that of the first connection structure11.

The package substrate300including the internal pattern302may serve as an interposer or a bi-layered redistribution layer. The first connection structure11may be replaced with one of the second, third, and fourth connection structures12,13, and14shown inFIGS.4B to4E. For example.FIG.5schematically illustrates the semiconductor package as shown inFIG.4F, except that the connection structure11is replaced by the connection structure13(refer toFIG.4C).

According to embodiments of the present disclosure with reference to, for example,FIGS.1G-4F, the conductive patterns (called “patterns” below) may have various widths and/or pitches. For example, with reference toFIG.1G, a width W1(in the left-right direction ofFIG.1G) of a first pattern (e.g., first conductive pattern114) may be greater than a width W2of a second pattern (e.g., e.g., one from among the second conductive pattern124and the third conductive pattern134) that is between the first pattern (e.g., first conductive pattern114) and a third pattern (e.g., fourth conductive pattern144), and the width W2of the second pattern (e.g., the one from among the second conductive pattern124and the third conductive pattern134) may be equal to or greater than a width W3of the third pattern (e.g., fourth conductive pattern144). Also, a pitch P1between patterns of the first pattern (e.g., first conductive pattern114) may be greater than a pitch P2between patterns of the second pattern (e.g., third conductive pattern134), and the pitch P2between the patterns of the second pattern (e.g., the one from among the second conductive pattern124and the third conductive pattern134) may be equal to or greater than a pitch P3between patterns of the third conductive pattern (e.g., fourth conductive pattern144). Each of the patterns may include a respective head segment and a respective tail segment. For example, the first pattern (e.g., first conductive pattern114) may include a first head segment and a first tail segment, the second pattern (e.g., the one from among the second conductive pattern124and the third conductive pattern134) may include a second head segment and a second tail segment, and the third pattern (e.g., fourth conductive pattern144) may include a third head segment and a third tail segment.

According to the inventive concepts, there may be no occurrence of pattern abnormality on a passivation layer between conductive patterns such as relatively thick under-bump-metals and on a certain pattern formed on the passivation layer. As such, the passivation layer or the certain pattern may be free of the pattern abnormality that possibly leads to electrical failure such as electrical short or open. In conclusion, a connection structure and a semiconductor package including the same may improve in structural stability and electrical characteristics.

This detailed description of the inventive concepts should not be construed as limited to the embodiments set forth herein, and it is intended that the inventive concepts cover the various combinations, the modifications and variations of the above-described embodiments without departing from the spirit and scope of the inventive concepts. The appended claims should be construed to include other embodiments.