Patent ID: 12224336

DETAILED DESCRIPTION OF THE EMBODIMENTS

Exemplary embodiments of the inventive concept will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

Hereinafter, two directions substantially parallel to an upper surface of a substrate and crossing each other may be referred to as first and second directions, respectively, and a direction substantially perpendicular to the upper surface of the substrate may be referred to as a third direction. In exemplary embodiments of the inventive concept, the first and second directions may be substantially perpendicular to each other.

FIGS.1and2are a plan view and a cross-sectional view, respectively, illustrating a semiconductor device in accordance with exemplary embodiments of the inventive concept.FIG.2includes cross-sections taken along lines A-A′ and B-B′, respectively, ofFIG.1.

Referring toFIGS.1and2, the semiconductor device may include a semiconductor pattern105on a substrate100, lower and upper impurity regions120and160, a spacer130, first and second conductive patterns144and146, a contact plug180, and first and second insulating interlayers150and170.

The substrate100may include a semiconductor material, e.g., silicon, germanium, silicon-germanium, etc., or111-V semiconductor compounds, e.g., GaP, GaAs, GaSb, etc. In exemplary embodiments of the inventive concept, the substrate100may be a silicon-on-insulator (SOI) substrate, or a germanium-on-insulator (GOI) substrate.

The lower impurity region120may be formed at an upper portion of the substrate100, and may include n-type or p-type impurities. The lower impurity region120may be formed at an entire upper portion of the substrate100, or may be partially formed at an upper portion of the substrate100. InFIGS.1and2, the lower impurity region120extends at least in the second direction, however, the inventive concept may not be limited thereto. For example, a plurality of lower impurity regions120may be formed under the semiconductor patterns,105, respectively, to be spaced apart from each other in the second direction. In other words, the lower impurity regions120may extend in the first direction.

The semiconductor pattern105may protrude from an upper surface of the lower impurity region120upwardly in the third direction. For example, the semiconductor pattern105may be formed at the upper portion of the substrate100. The semiconductor pattern105may be a remaining portion of an upper portion of the substrate100after partially etching an upper portion of the substrate100, and thus may include substantially the same material as the substrate100.

In exemplary embodiments of the inventive concept, the semiconductor pattern105may extend in the first direction, and a plurality of semiconductor patterns105may be spaced apart from each other in the second direction. InFIGS.1and2, three semiconductor patterns105spaced apart from each other in the second direction are shown, however, the inventive concept may not be limited thereto, and any number of semiconductor patterns105may be formed.

The spacer130may be formed on the lower impurity region120, which may be formed at the upper portion of the substrate100, and may cover a lower sidewall of each of the semiconductor patterns105. Thus, the spacer130may separate the lower impurity region120from the first and second conductive patterns144and146so that the lower impurity region120does not to contact the first and second conductive patterns144and146. The spacer130may include an oxide, e.g., silicon oxide or a nitride, e.g., silicon nitride.

The first conductive pattern144may be formed on the spacer130, and may surround and cover an upper sidewall of each of the semiconductor patterns105.

The second conductive pattern146may be formed on the spacer130to be connected to the first conductive pattern144. The second conductive pattern146may include a connection pattern146aand a pad146b. The connection pattern146amay be formed between the first conductive patterns144covering upper sidewalls of the semiconductor patterns105, respectively, spaced apart from each other in the second direction. For example, the connection pattern146amay extend in the second direction between a pair of first conductive patterns144. The pad146bmay be formed at an outer side of the first conductive patterns144in the second direction. For example, the pad146bmay be formed at opposite sides of a group of the first conductive patterns144arranged in the second direction.

The first and second conductive patterns144and146may include substantially the same material, e.g., a metal such as titanium, tantalum, tungsten, copper, aluminum, etc., a metal nitride such as titanium nitride, tantalum nitride, tungsten nitride, etc., an alloy thereof, a metal silicide, etc.

The first insulating interlayer150may be formed on the spacer130and the second conductive pattern146, and may cover a sidewall of the first conductive pattern144. The first insulating interlayer150may include an oxide, e.g., silicon oxide or a nitride, e.g., silicon nitride.

The upper impurity region160may be formed on each of the semiconductor patterns105, and may include n-type or p-type impurities. In exemplary embodiments of the inventive concept, the upper impurity region160may include impurities having the same conductivity type as impurities of the lower impurity region120. Referring toFIG.11B, the upper impurity region160may have a cross-section with a pentagon-like shape.

The second insulating interlayer170may be formed on the first insulating interlayer150and the first conductive pattern144, and may cover the upper impurity region160. The second insulating interlayer170may include an oxide, e.g., silicon oxide or a nitride, e.g., silicon nitride, and in some cases, may be merged with the first insulating interlayer150.

The contact plug180may extend through the first and second insulating interlayers150and170to contact an upper surface of the second conductive pattern146. For example, the contact plug180may contact one of the pads146b. In exemplary embodiments of the inventive concept, a pair of contact plugs180may be formed, and each of the contact plugs180may be formed on each of the pads146b. The contact plug180may include a metal, a metal nitride, a metal silicide, doped polysilicon, etc.

A first insulation layer including, e.g., silicon oxide and/or a second insulation layer including, e.g., a metal oxide may be further formed between the first and second conductive patterns144and146, and the spacer130and the semiconductor patterns105.

The semiconductor device may include the first conductive pattern144covering the upper sidewall of each of the semiconductor patterns105, and the first conductive pattern144may serve as a resistor. Thus, unlike a conventional resistor having a large area on the substrate100, the first conductive pattern144, which serves as the resistor, may have a relatively less horizontal area, since the first conductive patter144covers the upper sidewall of the semiconductor pattern105that protrudes in a vertical direction.

The semiconductor device including the resistor may include substantially the same structure as a transistor illustrated subsequently, except for some elements thereof, and thus may be formed by the same method. Accordingly, additional processes for forming the resistor are not needed, which may decrease the time and cost for fabrication of the semiconductor device.

The first conductive patterns144may be connected in series through the connection pattern146aof the second conductive pattern146, and thus a desired specific resistivity of the resistors may be easily obtained.

FIGS.3to11Bare plan views and cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with exemplary embodiments of the inventive concept. Particularly,FIGS.3,6,8and10are the plan views, andFIGS.4-5,7,9,11A and11Bare the cross-sectional views. Each of the cross-sectional views includes cross-sections taken along lines A-A′ and B-B′ of a corresponding plan view.

Referring toFIGS.3and4, hard masks110may be formed on a substrate100, and an upper portion of the substrate100may be etched using the hard masks110as an etching mask to form a plurality of semiconductor patterns105, each of which may protrude from the substrate100upwardly in the third direction, spaced apart from each other.

In exemplary embodiments of the inventive concept, each of the hard masks110may extend in the first direction, and a plurality of hard masks110may be spaced apart from each other in the second direction. Thus, each of the semiconductor patterns105may extend in the first direction, and a plurality of semiconductor patterns105may be spaced apart from each other in the second direction. InFIGS.3to11D, three hard masks110and three semiconductor patterns105are formed in the second direction, however, the inventive concept may not be limited thereto, and a plurality of hard masks110and a plurality of semiconductor patterns105may be formed. Each of the hard masks110may include a nitride, e.g., silicon nitride.

In an exemplary embodiment of the inventive concept, an ion implantation process may be performed into an upper portion of the substrate100to form a lower impurity region120. The lower impurity region120may be formed at an entire upper portion of the substrate100, or may be partially formed at an upper portion of the substrate100by a slant ion implantation process so that a plurality of lower impurity regions120may be formed to be spaced apart from each other.

A spacer layer may be formed on the substrate100having the semiconductor patterns105and the hard masks110thereon, and an upper portion of the spacer layer may be etched to form a spacer130covering a lower sidewall of each of the semiconductor patterns105.

Referring toFIG.5, a conductive layer140may be conformally formed on the spacer130, the semiconductor patterns105and the hard masks110.

Before forming the conductive layer140, a first insulation layer including, e.g., silicon oxide, and/or a second insulation layer including, e.g., a metal oxide, may be further formed on the spacer130, the semiconductor patterns105and the hard masks110.

Referring toFIGS.6and7, the conductive layer140may be etched using an etching mask.

In exemplary embodiments of the inventive concept, the etching mask may extend in the second direction to cover portions of the conductive layer140that are formed on the hard masks110and portions of the spacer130between the hard masks110, and the etching process may be an anisotropic etching process.

Thus, in an area covered by the etching mask, the conductive layer140may remain not only on sidewalls of the semiconductor patterns105and the hard masks110but also on an upper surface of each of the hard masks110, portions of the spacer130between the semiconductor patterns105, and portions of the spacer130at outer sides of the semiconductor patterns105in the second direction to form a preliminary second conductive pattern142extending in the second direction. In an area not covered by the etching mask, the conductive layer140may remain only on sidewalls of the semiconductor patterns105and the hard masks110to form a first conductive pattern144.

Accordingly, the first conductive pattern144surrounding the sidewalls of the semiconductor patterns105and the hard masks110, and the preliminary second conductive pattern142extending in the second direction to cover the semiconductor patterns105, the hard masks110, and portions of the spacer130adjacent thereto may be formed.

Referring toFIGS.8and9, a first insulating interlayer150may be formed on the preliminary second conductive pattern142, the first conductive pattern144, the hard masks110and the spacer130, and may be planarized until upper surfaces of the hard masks110may be exposed.

During the planarization process, portions of the preliminary second conductive pattern142on the hard masks110may be also removed, and thus the preliminary second conductive pattern142may remain on the sidewalls of the semiconductor patterns105and the hard masks110and a portion of the spacer130. Hereinafter, portions of the preliminary second conductive pattern142on the sidewalls of the semiconductor patterns105and the hard masks110may be considered as a portion of the first conductive pattern144previously formed, and a remaining portion of the preliminary second conductive pattern142, in other words, a portion of the preliminary second conductive pattern142on the portion of the spacer130not contacting the sidewalls of the semiconductor patterns105and the hard masks110but adjacent thereto may be referred to as a second conductive pattern146.

Thus, the first conductive pattern144may entirely surround upper sidewalls of the semiconductor patterns105and the hard masks110. Additionally, the second conductive pattern146may include a connection pattern146aand a pad146b, and may be connected to the first conductive pattern144. The connection pattern146amay be formed between the first conductive patterns144covering the upper sidewalls of the semiconductor patterns105spaced apart from each other in the second direction. The pad146bmay be formed on a portion of the spacer130, which is located at opposite side of a group of the first conductive patterns144arranged in the second direction.

The first conductive pattern144may serve as a resistor. The connection pattern146aof the second conductive pattern146may connect the first conductive patterns144with each other. For example, the connection pattern146amay be disposed between and contact adjacent first conductive patterns144. The pad146bof the second conductive pattern146may also contact a contact plug180(refer toFIGS.1and2) subsequently formed to be electrically connected thereto.

Referring toFIGS.10and11A, an upper portion of the first insulating interlayer150may be removed to form a recess exposing an upper portion of the first conductive pattern144, the exposed upper portion of the first conductive pattern144may be removed to expose hard masks110, and the exposed hard masks110may be removed.

In exemplary embodiments of the inventive concept, a bottom of the recess may be lower than upper surfaces of the semiconductor patterns105, and as the upper portions of the first insulating interlayer150and the first conductive pattern144are removed, upper portions of the semiconductor patterns105may be exposed.

For example, an ion implantation process may be performed on the exposed upper portions of the semiconductor patterns105to form upper impurity regions160, respectively. In exemplary embodiments of the inventive concept, the upper impurity region160may include impurities having the same conductivity type as the lower impurity region120.

Alternatively, referring toFIG.11B, after removing the exposed upper portions of the semiconductor patterns105, a selective epitaxial growth (SEG) process may be performed using upper surfaces of the semiconductor patterns105as a seed to form the upper impurity region160. In this case, the upper impurity region160may have a cross-section with a pentagon-like shape.

Referring toFIGS.1and2again, a second insulating interlayer170may be formed on the first insulating interlayer150, the first conductive patterns144and the upper impurity regions160, and the contact plugs180may be formed through the first and second insulating interlayers150and170to contact respective upper surfaces of the second conductive pattern146.

In exemplary embodiments of the inventive concept, each of the contact plugs180may not be formed on the connection pattern146aof the second conductive pattern146, but may be formed on the pad146bof the second conductive pattern146.

The semiconductor device may be manufactured by the above processes. As illustrated above, the first conductive pattern144surrounding the upper sidewalls of the semiconductor patterns105may be formed, so that a resistor having a small horizontal area may be formed. More specifically, a resistor in the form of the first conductive pattern144that has a small horizontal area may be formed.

Additionally, the semiconductor device may have substantially the same structure as a vertical transistor illustrated subsequently, except for some elements, and thus may be formed by the same method. Accordingly, additional processes for forming the resistor are not needed so as to decrease process time and cost.

The first conductive patterns144may be connected with each other in series through the connection pattern146aof the second conductive pattern146, and thus a desired specific resistivity may be easily obtained for the resistor.

FIG.12is a cross-sectional view illustrating a semiconductor device in accordance with exemplary embodiments of the inventive concept.FIG.12includes cross-sections taken along the lines A-A′ and B-B′, respectively, ofFIG.1.

This semiconductor device may be substantially the same as that ofFIGS.1and2, except for the lower impurity region120. Thus, like reference numerals refer to like elements, and repetitive descriptions thereon are omitted.

Referring toFIG.12, the lower impurity region120may include a base portion120aand a protrusion portion120b.

The base portion120aof the lower impurity region120may be formed at an upper portion of the substrate100, and may be formed at an entire upper portion of the substrate100or may extend in at least one direction, for example, in the second direction.

The protrusion portion120bof the lower impurity region120may protrude from the base portion120aupwardly in the third direction, and may contact a bottom surface of the semiconductor pattern105. Thus, the protrusion portion120bof the lower impurity region120may extend in the first direction, and a plurality of protrusion portions120bmay be spaced apart from each other in the second direction.

The base portion120aand the protrusion portion120bof the lower impurity region120may include substantially the same impurities.

The lower impurity region120may be formed by following processes.

An SEG process may be performed using an upper surface of the substrate100as a seed to form an impurity layer, a semiconductor layer may be formed on the impurity layer by an SEG process, the hard masks110may be formed on the semiconductor layer, and the semiconductor layer and an upper portion of the impurity layer may be etched using the hard masks110as an etching mask to form the semiconductor patterns105, and to form the protrusion portions120bof the lower impurity region120contacting a bottom surface of each of the semiconductor patterns105. Each of the semiconductor patterns105may protrude from the substrate100upwardly in the third direction and be spaced apart from each other. A lower portion of the impurity layer not etched during the etching process may remain as the base portion120aof the lower impurity region120.

FIGS.13and14are a plan view and a cross-sectional view, respectively, illustrating a semiconductor device in accordance with exemplary embodiments of the inventive concept.FIG.14includes cross-sections taken along lines C-C′ and D-D′, respectively, ofFIG.13.

This semiconductor device may be substantially the same as that ofFIGS.1and2, except for the first conductive pattern144. Thus, like reference numerals refer to like elements, and repetitive descriptions thereon are omitted.

Referring toFIGS.13and14, the first conductive pattern144may not cover the entire upper sidewall of each of the semiconductor patterns105, and a portion of each of the semiconductor patterns105not covered by the first conductive pattern144and a portion of the upper impurity region160thereon may be covered by a third insulating interlayer200.

In exemplary embodiments of the inventive concept, a sidewall of a first end of opposite ends in the first direction of each of the semiconductor patterns105may be covered by the first conductive pattern144, however, a sidewall of a second end of the opposite ends may not be covered by the first conductive pattern144. In exemplary embodiments of the inventive concept, a sidewall of a portion of the first conductive pattern144may be aligned along the second direction with a sidewall of the second conductive pattern146.

Thus, inFIGS.1and2, portions of the first conductive pattern144at opposite sides in the first direction of the pad146bof the second conductive pattern146may serve as a resistor, while inFIGS.13and14, only a portion of the first conductive pattern144at one side in the first direction of the pad146bof the second conductive pattern146may serve as a resistor.

The third insulating interlayer200may include substantially the same material as the second insulating interlayer170.

FIGS.15and16are a plan view and a cross-sectional view, respectively, illustrating a method of manufacturing a semiconductor device in accordance with exemplary embodiments of the inventive concept.FIG.16includes cross-sections taken along lines C-C′ and D-D′, respectively, ofFIG.15.

This method may include processes substantially the same as or similar to those illustrated with reference toFIGS.3to11andFIGS.1and2, and thus repetitive descriptions thereon are omitted.

Referring toFIGS.15and16, processes substantially the same as or similar to those illustrated with reference toFIGS.3to11may be performed, and the second insulating interlayer170may be formed.

A portion of the second insulating interlayer170may be etched to form an opening190exposing a portion of the first conductive pattern144covering a sidewall of an end in the first direction of each of the semiconductor patterns105, and the exposed portion of the first conductive pattern144may be removed by an etching process.

In exemplary embodiments of the inventive concept, the opening190may extend in the second direction, and thus portions of the first conductive patterns144covering sidewalls of the semiconductor patterns105spaced apart from each other in the second direction may be exposed to be removed. In exemplary embodiments of the inventive concept, a sidewall of the opening190may be aligned with a sidewall of the second conductive pattern146along the second direction, and thus by the etching process, a sidewall of the first conductive pattern144and a sidewall of the second conductive pattern146may be aligned with each other along the first direction.

Alternatively, a sidewall of the opening190may be closer to a central portion of each of the semiconductor patterns105in the first direction than to a sidewall of the second conductive pattern146in the first direction, and thus not only the first conductive pattern144but also a portion of the second conductive pattern146may be removed by the etching process. However, as a result, a sidewall of the first conductive pattern144in the first direction may be also aligned with a sidewall of the second conductive pattern146in the first direction.

Referring toFIGS.13and14again, a third insulating interlayer200may be formed to fill the opening190, and processes substantially the same as or similar to those illustrated with reference toFIGS.1and2may be performed to complete the fabrication of the semiconductor device.

FIGS.17to19are plan views illustrating layouts of semiconductor devices in accordance with exemplary embodiments of the inventive concept. These semiconductor devices may be substantially the same as that ofFIGS.1and2, except for the first conductive pattern144and/or the second conductive pattern146. Thus, like reference numerals refer to like elements, and repetitive descriptions thereon are omitted.

In order to avoid complex drawings, the first and second insulating interlayers150and170are not shown inFIGS.17to19.

Referring toFIG.17, the semiconductor device may include a resistor that may be formed by one first conductive pattern144surrounding one semiconductor pattern105, and thus there is no need for the connection pattern146aof the second conductive pattern146that may connect the first conductive patterns144covering sidewalls of the semiconductor patterns105, respectively.

In an exemplary embodiment of the inventive concept, the pads146bof the second conductive pattern146for contacting the contact plug180may be formed at opposite end portions, respectively, in the first direction of a same side in the second direction of the semiconductor pattern105. Alternatively, the pads146bof the second conductive pattern146for contacting the contact plug180may be formed at opposite end portions, respectively, in the first direction of opposite sides in the second direction of the semiconductor pattern105.

Referring toFIG.18, the connection patterns146aand the pads146bof the second conductive pattern146may be aligned with each other in the second direction at central portions in the first direction of the semiconductor patterns105.

Thus, in the semiconductor device ofFIGS.1and2, portions of the first conductive pattern144having different lengths in the first direction at opposite sides in the first direction of the pad146bof the second conductive pattern146may form a resistor, while in the semiconductor device ofFIG.18, portions of the first conductive pattern144having the same length in the first direction at opposite sides in the first direction of the pad146bof the second conductive pattern146may form a resistor.

Referring toFIG.19, the connection patterns146aand the pads146bof the second conductive pattern146may be arranged in a zigzag pattern in the second direction.

As illustrated above, by changing positions of the connection patterns146aof the second conductive pattern146for connecting the first conductive patterns144serving as resistors and surrounding the upper sidewalls of the semiconductor patterns105, the resistor having a desired specific resistivity may be easily formed.

FIGS.20and21are a plan view and a cross-sectional view, respectively, illustrating a semiconductor device in accordance with exemplary embodiments of the inventive concept.FIG.21includes cross-sections taken along lines A-A′ and B-B′ ofFIG.20.

This semiconductor device may be substantially the same as or similar to that ofFIGS.1and2, except for the second conductive pattern146. Thus, like reference numerals refer to like elements, and repetitive descriptions thereon are omitted.

Referring toFIGS.20and21, the semiconductor device nay not include the connection pattern146aof the second conductive pattern146, and may include only the pad146bof the second conductive pattern146. In other words, the connection pattern146amay not be provided between a pair of first conductive patterns144.

Thus, the first insulating interlayer150may be formed between a pair of first conductive patterns144covering upper sidewalls of a pair of semiconductor patterns105, respectively, spaced apart from each other in the second direction, and the pair of first conductive patterns144and the first insulating interlayer150may serve as a capacitor. The capacitor may have a capacitance that may be changed depending on an area of the first conductive patterns144serving as electrodes of the capacitor, which may be opposite to each other in the second direction, and a dielectric constant of a material of the first insulating interlayer150serving as a dielectric layer of the capacitor.

Unlike a conventional capacitor having a large horizontal area on the substrate100, the capacitor in accordance with exemplary embodiments of the inventive concept may include the first conductive patterns144covering the upper sidewalls of the semiconductor patterns105protruding in the vertical direction and the first insulating interlayer150therebetween, so as to have a reduced horizontal area.

The semiconductor device including the capacitor may have the same structure as a vertical transistor illustrated subsequently, except for some elements, and thus may be manufactured by the same method. Thus, additional processes for forming the transistor are not needed, so that process time and cost may be decreased.

FIGS.22and23are a plan view and a cross-sectional view, respectively, illustrating a method of manufacturing a semiconductor device in accordance with exemplary embodiments of the inventive concept.FIG.23includes cross-sections taken along lines A-A′ and B-B′ ofFIG.22.

This method may include processes substantially the same as or similar to those illustrated with reference toFIG.3to11andFIGS.1and2, and thus repetitive explanations are omitted.

Referring toFIGS.22and23, processes substantially the same as or similar to those illustrated with reference toFIGS.3to7may be performed.

However, only a pair of semiconductor patterns105may be formed to be spaced apart from each other in the second direction, and a pair of hard masks110may be formed to be spaced apart from each other in the second direction. A pair of etching masks may be spaced apart from each other such that each of the etching masks may cover a portion of the conductive layer140on sidewalls in the second direction of one of the semiconductor patterns105and a corresponding one of the hard masks110and an outside area in the second direction of the sidewalls thereof.

Thus, the conductive layer140may be etched using the pair of etching masks so that the conductive layer140may remain in an area covered by the pair of etching masks not only on the sidewalls of each of the semiconductor patterns105and each of the hard masks110but also on a portion of an upper surface of each of the hard masks110and on a portion of the spacer130in an outside area in the second direction of each of the semiconductor patterns105to form a pair of preliminary second conductive patterns142spaced apart from each other in the second direction. In an area not covered by the pair of etching masks, the conductive layer140may remain only on the sidewalls of each of the semiconductor patterns105and each of the hard masks110to form the first conductive pattern144.

Processes substantially the same as or similar to those illustrated with reference toFIGS.8to11andFIGS.1and2may be performed to complete the fabrication of the semiconductor device.

As illustrated above, the capacitor may be formed by forming the pair of first conductive patterns144surrounding the tipper sidewalls of the semiconductor patterns105, respectively, and facing each other in the second direction, and forming the first insulating interlayer150therebetween. This way, the capacitor may have a small horizontal area. Particularly, the contact plugs180for transferring a voltage to the capacitor may not be formed on the first conductive pattern144but on the pad146bof the second conductive pattern146, and thus during the etching process for forming the contact plugs180, the first conductive pattern144serving as the electrode of the capacitor may not be damaged. Accordingly, the capacitor may have improved electrical characteristics.

The semiconductor device may have the same structure as a vertical transistor illustrated subsequently, except for some elements, and thus may be formed by the same method. Accordingly, additional processes for forming the capacitor are not needed so as to decrease process time and cost.

FIGS.24to26are plan views illustrating layouts of semiconductor devices in accordance with exemplary embodiments of the inventive concept. These semiconductor devices may be substantially the same as that ofFIGS.20and21, except for the first conductive pattern144and/or the second conductive pattern146. Thus, like reference numerals refer to like elements, and repetitive descriptions thereon are omitted.

In order to avoid complex drawings, the first and second insulating interlayers150and170are not shown inFIGS.24to26.

Referring toFIG.24, the pad146bof each of the second conductive patterns146for contacting the contact plug180may contact an end portion of the first conductive pattern144in the first direction, wherein the first conductive pattern surrounds a sidewall of the semiconductor pattern105extending in the first direction.

InFIG.24, the pads146bof the second conductive patterns146are aligned in the second direction, however, the inventive concept may not be limited thereto. Thus, the pads146bof the second conductive patterns146may be formed at respective end portions of the first conductive patterns144such that the pads146bmay cross or overlap each other in the second direction.

Referring toFIG.25, the semiconductor device may include a first pair of semiconductor patterns including the semiconductor patterns105, respectively, each extending in the first direction and being spaced apart from each other in the first direction. The semiconductor device may also include a second pair of semiconductor patterns spaced apart from the first pair of semiconductor patterns in the second direction, which may include the semiconductor patterns105, respectively, each extending in the first direction and being spaced apart from each other in the first direction.

In exemplary embodiments of the inventive concept, one of the pads146bof the second conductive pattern146may be formed between end portions in the first direction of the first conductive patterns144, in the first pair of semiconductor patterns. Another one of the pads146bof the second conductive pattern146may be formed between end portions in the first direction of the first conductive patterns144, in the second pair of semiconductor patterns. In other words, the semiconductor pattern105surrounded by the first conductive pattern144may be formed at each of opposite sides in the first direction of each pad146bof the second conductive pattern146.

Referring toFIG.26, the semiconductor device may include a plurality of semiconductor patterns105spaced apart from each other in the second direction, and inFIG.26, four semiconductor patterns105are shown.

In exemplary embodiments of the inventive concept, a first pad among the pads146bof the second conductive pattern146may connect end portions of the first conductive patterns144surrounding sidewalls of odd-numbered ones of the plurality of semiconductor patterns105. A second pad among the pads146bof the second conductive pattern146may connect end portions of the first conductive patterns144surrounding sidewalls of even-numbered ones of the plurality of semiconductor patterns105. The contact plugs180may be formed on the first and second pads, respectively. Thus, the pads146bof the second conductive pattern146and the first conductive patterns144connected thereto may have a comb-like shape in a plan view.

As illustrated above, by changing locations of the pads146bof the second conductive pattern146for transferring a voltage to the first conductive patterns144, which may serve as electrodes of a capacitor and surround the sidewalls of the semiconductor patterns105, respectively, the capacitor may have a desired capacitance.

FIGS.27to29are a plan view and cross-sectional views illustrating a semiconductor device in accordance with exemplary embodiments of the inventive concept. Particularly,FIG.27is the plan view,FIG.28is a cross-sectional view taken along a line E-E′ ofFIG.27, andFIG.29is a cross-sectional view taken along a line F-F′ ofFIG.27.

This semiconductor device may include an active element such as a transistor, and a passive element such as a resistor and a capacitor. The transistor may be a vertical field effect transistor (vfet) having a vertical channel, and each of the resistor and the capacitor may have a structure similar to that of the vfet. In other words, the vfet may have a structure similar to that of the resistor and/or the capacitor previously illustrated, except for some elements. Thus, repetitive explanations on the same elements are omitted.

InFIGS.27to29, the semiconductor device includes the resistor ofFIG.17and the capacitor ofFIGS.20and21, however, the inventive concept may not be limited thereto. In other words, the semiconductor device may include one or more of the resistors shown inFIGS.1and2,FIG.12,FIGS.13and14,FIG.18, andFIG.19, and one of the capacitor shown inFIGS.24to26.

Referring toFIGS.27to29, the semiconductor device may include first, second and third structures on first, second and third regions I, II and III, respectively, of a substrate300.

In exemplary embodiments of the inventive concept, the first structure may be a vfet, the second structure may include a resistor, and the third structure may include a capacitor.

The first structure may include a first semiconductor pattern302, a first lower impurity region322, a first upper impurity region362, a spacer330, third and fourth conductive patterns342and343, and first, second and third contact plugs381,382and383on the first region I of the substrate300. The second structure may include a second semiconductor pattern304, a second lower impurity region324, a second upper impurity region364, the spacer330, fifth and sixth conductive patterns345and346, and a fourth contact plug3841on the second region II of the substrate300. The third structure may include a third semiconductor pattern306, a third lower impurity region326, a third tipper impurity region366, the spacer330, seventh and eighth conductive patterns348and349, and a fifth contact plug386on the third region III of the substrate300.

The first to third lower impurity regions322,324and326and the first to third upper impurity regions362,364and366may include impurities having the same conductivity type, e.g., n-type or p-type. For example, when the first lower impurity region322and the first upper impurity region362include n-type impurities, the first structure may be an n-type vfet, and when the first lower impurity region322and the first upper impurity region362include p-type impurities, the first structure may be a p-type vfet. However, in some cases, an n-type vfet and a p-type vfet both may be formed on the first region I of the substrate300, and in this case, the second lower and upper impurity regions324and364and the third lower and upper impurity regions326and366included in the second and third structures on the second and third regions II and III, respectively, of the substrate300may also include both of n-type impurities and p-type impurities.

In exemplary embodiments of the inventive concept, each of the first to third semiconductor patterns302,304and306may extend in the first direction, and upper surfaces of the first to third semiconductor patterns302,304and306may be substantially coplanar with each other. The first to third semiconductor patterns302,304and306may include substantially the same semiconductor material. InFIGS.27to29, one first semiconductor pattern302is formed on the first region I of the substrate300, however, the inventive concept may not be limited thereto. In other words, one or more than one first semiconductor pattern302may be formed on the first region I of the substrate300.

In exemplary embodiments of the inventive concept, the third, fifth and seventh conductive patterns342,345and348may surround entire upper sidewalls of the first, second and third semiconductor patterns302,304and306, respectively. The third, fifth and seventh conductive patterns342,345and348may have substantially the same thickness, and upper surfaces of the third, fifth and seventh conductive patterns342,345and348may be substantially coplanar with each other. The first to third upper impurity regions362,364and366may be formed on the first to third semiconductor patterns302,304and306, respectively, and thus upper surfaces of the first to third upper impurity regions362,364and366may not be covered by the third, fifth and seventh conductive patterns342,345and348, respectively.

The fourth conductive patterns343may be formed on portions of the spacer330at opposite sides, respectively, in the second direction of the first semiconductor pattern302. The sixth conductive patterns346may be formed on respective portions of the spacer330spaced apart from each other in the first direction at a side in the second direction of the second semiconductor pattern304. The eighth conductive patterns349may be formed on portions of the spacer330at opposite sides, respectively, in the second direction of the third semiconductor pattern306.

On the first region I of the substrate300, the first contact plug381extending through first and second insulating interlayers350and370to contact an upper surface of the fourth conductive pattern343, the second contact plug382extending through the second insulating interlayer370to contact an upper surface of the first upper impurity region362, and the third contact plug383extending through the first and second insulating interlayers350and370and the spacer330to contact an upper surface of the first lower impurity region322may be formed. On the second region II of the substrate300, the fourth contact plug384extending through the first and second insulating interlayers350and370to contact an upper surface of the sixth conductive pattern346may be formed. On the third region III of the substrate300, the fifth contact plug386extending through the first and second insulating interlayers350and370to contact an upper surface of the eighth conductive pattern349may be formed.

A first insulation layer including, e.g., silicon oxide and/or a second insulation layer including, e.g., a metal oxide may be further formed between the third to eighth conductive patterns342,343,345,346,348and349, and the spacer330and the first to third semiconductor patterns302,304and306.

The first structure may include the third conductive pattern342serving as a gate electrode, the first lower and upper impurity regions322and362serving as source/drain regions, and the first semiconductor pattern302serving as a channel. In this case, the first structure may be a vfet in which current may flow in the channel in the third direction between the source/drain regions spaced apart from each other in the third direction by a voltage applied through the second and third contact plugs382and383connected to the first upper and lower impurity regions362and322, respectively.

The fifth conductive pattern345in the second structure may surround the upper sidewall of the second semiconductor pattern304, and electrical signals may be applied to the fifth conductive pattern345by the sixth conductive pattern346and the fourth contact plugs384, so that the fifth conductive pattern345may serve as a resistor. No contact plugs may be connected to the second lower and upper impurity regions324and364in the second structure so that no electrical signals may be applied thereto. Even if electrical signals are applied to the second lower and upper impurity regions324and364, the second semiconductor pattern304may be in a floating state in the circuit. In other words, the second structure may be a passive element unlike the first structure, and the fifth conductive pattern345and the second semiconductor pattern304in the second structure may not serve as a gate structure and a channel of a transistor.

Electrical signals may be applied to the seventh conductive patterns348in the third structure by the eighth conductive patterns349and the fifth contact plugs386, and the seventh conductive patterns348and the first insulating interlayer350therebetween may serve as a capacitor. No contact plugs may be connected to the third lower and upper impurity regions326and366in the third structure so that no electrical signals may be applied thereto. Even if electrical signals are applied to the third lower and upper impurity regions326and366, the third semiconductor pattern306may be in a floating state in the circuit. In other words, the third structure may be a passive element unlike the first structure, and the seventh conductive patterns348and the third semiconductor pattern306in the third structure may not serve as a gate structure and a channel of a transistor.

The first to third structures may have similar structures with each other, except for some elements, and may be formed by the same method subsequently illustrated.

When the vfet is an n-type or a p-type transistor, the third conductive pattern342may include a metal, a metal nitride, a metal alloy, etc., having a proper workfunction, and thus the fifth conductive pattern345serving as a resistor and/or the seventh conductive patterns348serving as an electrode of a capacitor may also include the same material. Accordingly, by changing the material of the third conductive pattern342, the resistor may have a desired specific resistivity.

FIGS.30to35are plan views and cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with exemplary embodiments of the inventive concept. Particularly,FIGS.30,32and34are the plan views, andFIGS.31,33and35are cross-sectional views taken along lines E-E′ of corresponding plan views. This method may include processes substantially the same as or similar to those illustrated with reference toFIGS.1to11orFIGS.20to23, and thus repetitive explanations thereon are omitted.

Referring toFIGS.30and31, processes substantially the same as or similar to those illustrated with reference toFIGS.3to4may be performed.

In other words, first, second and third hard masks312,314and316may be formed on the first, second and third regions I, II and III, respectively, of the substrate300, upper portions of the substrate300may be etched using the first to third hard masks312,314and316as an etching mask to form first to third semiconductor patterns302,304and306, respectively, protruding upwardly from the substrate300in the third direction on the first to third regions I, II and ill of the substrate300.

In an exemplary embodiment of the inventive concept, an ion implantation process may be performed on an upper portion of the substrate300to form first to third lower impurity regions322,324and326on the first to third regions I, II and III, respectively, of the substrate300. Each of the first to third lower impurity regions322,324and326may be formed at an entire upper portion of the respective region of the substrate300, or a plurality of first lower impurity regions322, a plurality of second lower impurity regions324, and a plurality of third lower impurity regions326may be formed in the respective region of the substrate300.

A spacer330may be formed to cover lower sidewalls of the first to third semiconductor patterns302,304and306.

Referring toFIGS.32and33, processes substantially the same as or similar to those illustrated with reference toFIGS.5to7orFIGS.22to23may be performed so that a preliminary fourth conductive pattern341and a third conductive pattern342may be formed on the first region I of the substrate300, a preliminary sixth conductive pattern344and a fifth conductive pattern345may be formed on the second region II of the substrate300, and a preliminary eighth conductive pattern347and a seventh conductive pattern348may be formed on the third region III of the substrate300.

In exemplary embodiments of the inventive concept, the third, fifth and seventh conductive patterns342,345and348may cover the first, second and third semiconductor patterns302,304and306, respectively, and the first, second and third hard masks312,314and316, respectively. The preliminary fourth conductive pattern341may extend in the second direction to cover the first semiconductor pattern302, the first hard mask312, and a portion of the spacer330adjacent thereto in the second direction. A pair of preliminary sixth conductive patterns344may be formed to be spaced apart from each other in the first direction, and each of the preliminary sixth conductive patterns344may cover sidewalls of the second semiconductor pattern304and the second hard mask314, a portion of the second hard mask314adjacent thereto, and a portion of the spacer330adjacent thereto. A pair of preliminary eighth conductive patterns347be formed to be spaced apart from each other in the second direction, and may cover sidewalls of a pair of third semiconductor patterns306and a pair of third hard masks316, tipper surfaces of the third hard masks316adjacent thereto, and portions of the spacer330adjacent thereto.

InFIGS.32and33, the preliminary fourth conductive pattern341covers the first semiconductor pattern302, the first hard mask312, and portions of the spacer330at opposite sides in the second direction of the first semiconductor pattern302and the first hard mask312, however, the inventive concept may not be limited thereto. For example, the preliminary fourth conductive pattern341may cover a portion of the spacer330at one side in the second direction of the first semiconductor pattern302and the first hard mask312.

Referring toFIGS.34and35, processes substantially the same as or similar to those illustrated with reference toFIGS.8to11may be performed.

Thus, third, fifth and seventh conductive patterns342,345and348may be formed to surround upper sidewalls of the first, second and third semiconductor patterns302,304and306, respectively. Fourth conductive patterns343may be formed on respective portions of the spacer330at opposite sides in the second direction of the first semiconductor pattern302, sixth conductive patterns346may be formed on respective portions of the spacer330at one sidewall in the second direction of the second semiconductor pattern304, and eighth conductive patterns349may be formed on respective portions of the spacer330at opposite sides in the second direction of a pair of the third semiconductor patterns306.

First to third upper impurity regions362,364and366may be formed at respective tipper portions of the first to third semiconductor patterns302,304and306, and a first insulating interlayer350may be formed on the spacer330to cover the fourth, sixth and eighth conductive patterns343,346and349and sidewalls of the third, fifth and seventh conductive patterns342,345and348.

Referring toFIGS.27to29, processes substantially the same as or similar to those illustrated with reference toFIGS.1and2may be performed to complete the fabrication of the semiconductor device.

First to third contact plugs381,382and383may be formed on the first region I of the substrate300, a fourth contact plug384may be formed on the second region II of the substrate300, and a fifth contact plug386may be formed on the third region III of the substrate300.

As illustrated above, the vfet, the resistor, and the capacitor may be formed on the first, second, third regions I, II and III, respectively, of the substrate300, which may have substantially the same structure except for some elements. Thus, additional processes for forming the resistor and the capacitor are not needed so as to decrease process time and cost.

The semiconductor device according to an exemplary embodiment of the inventive concept may include a passive element such as a resistor and a capacitor having the similar structure to that of a vfet, and thus no additional processes for forming the passive element are needed. The resistor and the capacitor may be formed on a sidewall of a semiconductor pattern protruding in the vertical direction, and thus may have a reduced horizontal area. The resistor and the capacitor may have a desired specific resistivity and capacitance through a connection pattern for connecting conductive patterns with each other.

While the inventive concept has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by one of ordinary skill in the art that variations in form and detail may be made thereto without departing from the spirit and scope of the inventive concept as set forth in the claims.