Patent ID: 12204024

DESCRIPTION OF EMBODIMENTS

Hereinafter, modes for implementing the technology of the present disclosure (hereinafter referred to as “embodiments”) will be described in detail with reference to the drawings. The technology of the present disclosure is not limited to the embodiments. In the following description, the same reference numerals will be used for the same elements or elements having the same function, and redundant description will be omitted. Note that the description will be given in the following order.1. Explanation of light receiving device and distance measuring device of the present disclosure in general2. Measuring device according to embodiments3. Basic configuration of light receiving device using SPAD sensor4. Light receiving device according to embodiments4-1. First embodiment (example of retrieving signal from cathode electrode side)4-2. Second embodiment (example of retrieving signal from anode electrode side)4-3. Third embodiment (modification of first embodiment: example of another circuit configuration of four-input OR circuit)4-4. Fourth embodiment (modification of first embodiment: first example of method of retrieving pixel output)4-5. Fifth embodiment (modification of first embodiment: second example of method of retrieving pixel output)4-6. Sixth embodiment (modification of fourth embodiment: example of detecting number of incident photons)4-7. Seventh embodiment (modification of first embodiment: example of retrieving pixel output for each pixel)4-8. Eighth embodiment (example of chip structure of light receiving device)4-9. Ninth embodiment (first example in which recharge signal generation circuit includes ring oscillator)4-10. Tenth embodiment (second example in which recharge signal generation circuit includes ring oscillator)4-11. Eleventh embodiment (example of asymmetric delay element constituting ring oscillator)4-12. Twelfth embodiment (modification of eleventh embodiment: example of changing the number of series of elements having high on-resistance)4-13. Thirteenth embodiment (modification of eleventh embodiment: example of changing the number of parallel of elements having high on-resistance)5. Application example of technology according to the present disclosure (example of mobile body)6. Configuration that the present disclosure can take
<Explanation of Light Receiving Device and Distance Measuring Device of the Present Disclosure in General>

In the light receiving device and the distance measuring device of the present disclosure, the recharge control unit can be configured to, in a case where photons are incident on one or more light receiving units among light receiving units of a plurality of pixels that share a recharge control unit, perform recharging for all of the light receiving units of the plurality of pixels. Furthermore, the recharge control unit can have an OR circuit that takes the OR of logic signals whose logic is inverted at the time when photons are incident on one or more light receiving units, and can be configured to perform recharging according to an OR signal of the OR circuit.

The light receiving device and the distance measuring device of the present disclosure including the preferable configuration described above can have a configuration in which the light receiving unit includes a single photon avalanche diode. At this time, a configuration can be adopted in which a signal is retrieved from a cathode electrode side of the single photon avalanche diode, or a configuration can be adopted in which a signal is retrieved from an anode electrode side.

Furthermore, the light receiving device and the distance measuring device of the present disclosure including the preferable configuration described above can have a level conversion unit that converts the level of the OR signal of the OR circuit, and can be configured to output a conversion result of the level conversion unit as information for detecting the photon incidence timing. Alternatively, the light receiving device and the distance measuring device can have an exclusive OR circuit that retrieves the exclusive OR of logic signals whose logic is inverted at the time when photons are incident on one or more light receiving units, and a level conversion unit that converts the level of the exclusive OR signal of the exclusive OR circuit, and can be configured to output the conversion result of the level conversion unit as information for detecting the photon incidence timing.

Furthermore, the light receiving device and the distance measuring device of the present disclosure including the preferable configuration described above can have an adder that adds the number of photons incident on a plurality of pixels sharing the recharge control unit, and can be configured to output an addition result of the adder as information for detecting the number of incident photons. Alternatively, each of the input signals of the OR circuit can have a waveform shaping unit that performs processing for increasing the pulse width and outputs the result.

Furthermore, the light receiving device and the distance measuring device of the present disclosure including the preferable configuration described above can have a quenching circuit that lowers the applied voltage with respect to the single photon avalanche diode to the breakdown voltage. Then, the quenching circuit can have a second switch unit connected in parallel to a first switch unit, and can be configured to operate according to the output of the light receiving unit.

Furthermore, in the light receiving device and the distance measuring device according to an embodiment of the present disclosure including the preferable configuration described above, the recharge control unit can have a recharge signal generation circuit that generates a recharge signal for driving the first switch unit. Then, the recharge signal generation circuit can use a ring oscillator. Furthermore, the ring oscillator can be configured by using an asymmetric delay element having different rising delay time and falling delay time.

Furthermore, in the light receiving device and the distance measuring device of the present disclosure including the preferable configuration described above, the asymmetric delay element can include a CMOS inverter, and have a P-channel field effect transistor and an N-channel field effect transistor having different sizes. Furthermore, a configuration can be adopted in which the delay time of the asymmetric delay element can be varied.

Furthermore, in the light receiving device and the distance measuring device of the present disclosure including the preferable configuration described above, a configuration can be adopted in which, the number of series connections of the transistor having higher on-resistance among the P-channel field effect transistor and the N-channel field effect transistor is variable, and the delay time is set according to the number of series connections. Alternatively, a configuration may be adopted in which the number of parallel connections of the transistor having higher on-resistance is variable, and the delay time can be set according to the number of parallel connections.

Furthermore, the light receiving device and the distance measuring device according to an embodiment of the present disclosure including the preferable configuration described above can have a stacked structure in which a first semiconductor substrate on which the light receiving unit is arranged and a second semiconductor substrate on which the recharge control unit is arranged are stacked.

<Measuring Device According to Embodiments>

FIG.1is a schematic configuration diagram showing a distance measuring device according to an embodiment of the present disclosure. In a distance measuring device1according to the present embodiment, as a measuring method for measuring the distance to a subject10which is a measuring object, the time of flight (TOF) method is adopted which measures the time until light (for example, laser light) emitted toward the subject10is reflected by the subject10and returns. In order to realize the distance measurement by the TOF method, the distance measuring device1according to the present embodiment includes a light source20and a light receiving device30. Then, as the light receiving device30, a light receiving device according to an embodiment of the present disclosure which will be described later is used.

Specific configurations of the distance measuring device1according to the present embodiment are shown inFIGS.2A and2B. The light source20has, for example, a laser driver21, a laser light source22, and a diffusing lens23, and irradiates the subject10with laser light. The laser driver21drives the laser light source22under the control of a control unit40. The laser light source22includes, for example, a semiconductor laser, and emits laser light when driven by the laser driver21. The diffusing lens23diffuses the laser light emitted from the laser light source22and irradiates the subject10.

The light receiving device30has a light receiving lens31, a light sensor32, and a logic circuit33, and receives reflected laser light that is the irradiated laser light emitted by the laser irradiation unit20being reflected by the subject10and returning. The light receiving lens31condenses the reflected laser light from the subject10onto a light receiving surface of the light sensor32. The light sensor32receives the reflected laser light from the subject10that has passed through the light receiving lens31in units of pixels and performs photoelectric conversion.

An output signal of the light sensor32is supplied to the control unit40via the logic circuit33. Details of the light sensor32will be described later. The control unit40is constituted by, for example, a central processing unit (CPU) or the like, and controls the light source20and the light receiving device30, and measures time t until the laser light emitted from the light source20toward the subject10is reflected by the subject10and returns. On the basis of this time t, distance L to the subject10can be obtained. As a time measurement method, a timer is started at the timing of emitting pulse light from the light source20, the timer is stopped at the timing when the light receiving device30receives the pulse light, and the time t is measured. As another time measurement method, pulse light is emitted from the light source20at a predetermined cycle, a cycle when the light receiving device30receives the pulse light is detected, and the time t may be measured from the phase difference between the light emission cycle and the light reception cycle.

As the light sensor32, a two-dimensional array sensor (so-called area sensor) in which pixels including a light receiving unit are arranged in a two-dimensional array can be used, or a one-dimensional array sensor (so-called line sensor) in which pixels including a light receiving unit are linearly arranged can also be used.

In addition, in this embodiment, as the light sensor32, a sensor is used in which the light receiving unit of the pixel includes an element that generates a signal in response to the reception of photons, for example, a single photon avalanche diode (SPAD) element. That is, in the light receiving device30according to the present embodiment, the light receiving unit of the pixel includes the SPAD sensor. Note that, the light receiving unit is not limited to the SPAD element, and may be various elements such as an avalanche photo diode (APD).

<Basic Configuration of Light Receiving Device Using SPAD Sensor>

FIG.3shows a basic configuration of the light receiving device30using a SPAD sensor. Here, the basic configuration for one pixel is shown.

A pixel50uses the SPAD sensor51as a light receiving unit. The SPAD sensor51has a cathode electrode connected to a terminal52and an anode electrode connected to a low potential-Vbd(for example, −10V) side power supply, and generates a signal, specifically, a pulse signal in response to the reception of a photon hv. The SPAD sensor51is a high-performance light sensor capable of detecting incidence of single photon with photon detection efficiency (PDE).

As shown inFIG.4A, the pixels50including the SPAD sensor51are arranged in a two-dimensional array of M rows and N columns on the first semiconductor substrate to constitute a pixel array unit. The first semiconductor substrate in which the pixels50are arranged constitutes a sensor chip71. This sensor chip71corresponds to the light sensor32inFIG.2A.

A circuit unit60is provided for each pixel50. The circuit unit60includes a first switch unit61, a second switch unit62, a comparator63, a recharge control unit64, and a level conversion unit65. In the circuit unit60, the first switch unit61, the second switch unit62, and the comparator63constitute the pixel50together with the SPAD sensor51.

The first switch unit61is constituted by, for example, a P-channel type field effect transistor, is connected between a high-potential Veside power supply and the terminal52, and is a recharge switch that operates according to a recharge signal RCHG provided from the recharge control unit64. The first switch unit61recharges the SPAD sensor51in response to the recharge signal RCHG.

The second switch unit62is connected in parallel to the first switch unit61and constitutes a quenching circuit that performs quenching operation according to the output of the SPAD sensor51, more specifically, the output of the comparator63. The second switch unit62as a quench switch stops the avalanche phenomenon by lowering the voltage applied to the SPAD sensor51to the breakdown voltage by the quenching operation.

The comparator63converts the cathode potential of the SPAD sensor51to a logic level. A logic signal output from the comparator63is supplied to the second switch unit62as a quench signal QNCH and is also supplied to the recharge control unit64and the level conversion unit65.

The recharge control unit64generates the recharge signal RCHG on the basis of the logic signal output from comparator63. Then, the recharge control unit64performs on/off control of the first switch unit61on the basis of the recharge signal RCHG.

The level conversion unit65is a level-down circuit that levels down the potential Veof the logic level output from the comparator63to the power supply potential VDD(for example, about 1.1V) of the logic circuit33(seeFIG.2B) in the subsequent stage. The potential level-downed by the level conversion unit65is derived as a pixel output. In the logic circuit33at the subsequent stage, processing such as edge detection of the pixel output output from the level conversion unit65is performed.

FIG.4Bshows timing relationships among the cathode potential of the SPAD sensor51, the quench signal QNCH, and the recharge signal RCHG.

When photons are incident on the SPAD sensor51, a current flows through the SPAD sensor51by avalanche amplification, and the cathode potential of the SPAD sensor51decreases. In addition, when the cathode potential of the SPAD sensor51exceeds the comparison reference value (threshold value) of the comparator63, the logic of the quench signal QNCH changes from 0 to 1. In response to this, the second switch unit62is turned off, so that the quenching operation is performed.

Since the cathode potential of the SPAD sensor51is lowered to around 0V by the quenching operation by the second switch unit62, the avalanche amplification stops. Then, as the logic of the recharge signal RCHG changes from 1 to 0 to 1, the first switch unit61is turned on to recharge the SPAD sensor51. As a result, the cathode potential of the SPAD sensor51rises to Ve, and the SPAD sensor51returns to the initial state.

A series of operation described above, that is, a series of operation of current flowing in the SPAD sensor51, potential decreasing of the cathode potential of the SPAD sensor51, quenching, and recharging of the SPAD sensor51is repeated each time a photon enters the SPAD sensor51.

The circuit unit60having the above-described configuration is arranged in a two-dimensional array of M rows and N columns on the second semiconductor substrate. The second semiconductor substrate in which the circuit unit60is arranged constitutes a circuit chip72. The circuit chip72is stacked on the sensor chip71. Thereby, in the stacked structure of the sensor chip71and the circuit chip72, the circuit unit60is provided for each one pixel50. In other words, the occupied area of one pixel50and the occupied area of one circuit unit60are substantially equal.

Incidentally, in recent years, miniaturization of the pixel50has been advanced for the purpose of downsizing the chip size. However, as described above, in a case where the occupied areas of the pixel50and the circuit unit60are about the same and the relationship between the pixel50and the circuit unit60is in a one-to-one relationship, even if the pixel50is miniaturized, the occupied area (circuit area) of the circuit unit60does not decrease, so that the aperture ratio of the pixel50decreases. In other words, the circuit area of the circuit unit60becomes a bottleneck for miniaturization of the pixel50.

<Light Receiving Device According to Embodiments>

In the present embodiment, in the light receiving device30having the first switch unit61that recharges the SPAD sensor51and the recharge control unit64that controls the SPAD sensor51according to the output of the SPAD sensor51, the recharge control unit64is shared among the plurality of pixels50.

The recharge control unit64is shared among the plurality of pixels50in this way, so that, since the circuit area of the circuit unit60per pixel can be reduced, the aperture ratio can be increased while miniaturizing the pixel50. Furthermore, in a case of a stacked structure (seeFIG.4A) in which the sensor chip71and the circuit chip72are stacked, since the circuit area of the circuit unit60per pixel can be reduced, the pixel50is miniaturized, and further, the size of the chip size can be reduced or the number of pixels can be increased.

However, the technology of the present disclosure is not limited to application to the stacked structure. In other words, the technology of the present disclosure is also applicable to a so-called flat structure in which the circuit unit60is arranged on the same semiconductor substrate as the pixel array unit in which the pixels50are arranged. Details of the chip structure of the stacked structure and the flat structure will be described later.

Hereinafter, a specific example of the light receiving device30according to the present embodiment will be described.

First Embodiment

A first embodiment is an example of retrieving a signal from a cathode electrode side of the SPAD sensor51.FIG.5is a circuit configuration of the light receiving device30according to the first embodiment.

Here, a case where the recharge control unit64is shared among four pixels501to504is illustrated. The four pixels501to504are four pixels of two columns×two rows adjacent to each other in the column direction and the row direction in a matrix pixel array. However, the number of pixels sharing the recharge control unit64is not limited to four pixels. This point is similar in each of the embodiments described later. Furthermore, the second switch unit62as a quench switch provided for each SPAD sensor51is not shown for the sake of simplicity of the drawing. This is similar in each of the embodiments described later.

In the pixel501, the SPAD sensor511has a cathode electrode connected to a terminal521and an anode electrode connected to a low potential (−Vbd) side power supply, respectively. Then, the signal of the SPAD sensor511is retrieved through the terminal521from the cathode electrode side. This is similar in the other SPAD sensors512to514.

A first switch unit611serving as a recharge switch is constituted by, for example, a P-channel type field effect transistor, is connected between a high-potential (Ve) side power supply and the terminal52, and operates according to a recharge signal RCHG provided from the recharge control unit64. This is similar in the other first switch units612to614.

Signals retrieved from each cathode electrode of the SPAD sensors511to514through the terminals521to524are converted to the logical level by comparators631to634and then supplied to an input end of the recharge control unit64. In other words, each cathode electrode of the SPAD sensors511to514and the input end of the recharge control unit64are electrically connected via the terminals521to524and the comparators631to634, so that the recharge control unit64is shared among the four pixels501to504.

The recharge control unit64includes a four-input OR circuit641and a recharge signal generation circuit642. The OR circuit641obtains the OR of the logic signals retrieved from each cathode electrode of the SPAD sensors511to514supplied through the comparators631to634. The OR output of the OR circuit641is supplied to the recharge signal generation circuit642. The recharge signal generation circuit642generates the recharge signal RCHG by delaying the OR output of the OR circuit641by a predetermined delay time, and supplies the recharge signal RCHG to the first switch units611to614. As a result, the recharge control unit64performs the recharge control in response to the OR signal of the logic signal whose logic is inverted at the time when photons are incident on one or more of the SPAD sensors511to514.

The circuit operation of the light receiving device30according to the first embodiment will be described with reference to the timing waveform diagram ofFIG.6.FIG.6shows timing relationships of comparison outputs COMP_1to COMP_4of the comparators631to634for each of the SPAD sensors511to514and the OR output ORoutof the OR circuit641. Quenching based on the quench signal QNCH and recharging based on the recharge signal RCHG are as described inFIG.4B. In the timing waveform diagram ofFIG.6, the delay time is the delay time of the recharge signal generation circuit642.

In a case where the recharge control unit64is shared among the four pixels501to504, when photons are incident on one or more SPAD sensors among the SPAD sensors511to514of the four pixels501to504that share the recharge control unit64, recharge control is performed for all of the SPAD sensors511to514. In other words, the recharge control is (collectively) performed for the four pixels501to504. In this case, the SPAD sensor on which the photon is not incident may also be recharged. Therefore, when one SPAD sensor that fires earlier and another SPAD sensor fire (simultaneously fire) during the recharging period, in other words, if a photon enters another SPAD sensor at the timing of the recharge of the one SPAD sensor, the photon is lost (for example, in the case of the comparison output COMP_4of the comparator634inFIG.6).

However, by setting the recharge period as short as possible within a range not hindering the recharging operation, the loss of photons can be reduced. Accordingly, even if recharging is performed collectively for four pixels501to504, there is no problem in circuit operation.

As described above, in the light receiving device30according to the first embodiment, each cathode electrode of the SPAD sensors511to514and the input end of the recharge control unit64are electrically connected via the terminals521to524and the comparators631to634, so that the recharge control unit64is shared among four pixels501to504. By this sharing of the recharge control unit64, since the circuit area of the circuit unit60per pixel can be reduced, the aperture ratio can be increased while miniaturizing the pixel50.

Second Embodiment

A second embodiment is an example of retrieving a signal from an anode electrode side of the SPAD sensor51.FIG.7shows a circuit configuration of the light receiving device30according to the second embodiment.

In the pixel501, the SPAD sensor511has a cathode electrode connected to a high potential side power supply and an anode electrode connected to the terminal521, respectively. The power supply potential of the high potential side power supply is set to Vbd+Ve. Then, the signal of the SPAD sensor511is retrieved through the terminal521from the anode electrode side. This is similar in the other SPAD sensors512to514.

A first switch unit611serving as a recharge switch is constituted by, for example, an N-channel type field effect transistor, is connected between the terminal521and a low-potential (Vss) side power supply, and operates according to the recharge signal RCHG provided from the recharge control unit64. This is similar in the other first switch units612to614.

In addition, the anode electrodes of the SPAD sensors511to514and the input end of the recharge control unit64are electrically connected to each other through the terminals521to524and the comparators631to634. Due to this connection relationship, the recharge control unit64is shared among the four pixels501to504. Note that, the logic of the comparators631to634is inverted from that in the case of the first embodiment.

The recharge control unit64includes the four-input OR circuit641, the recharge signal generation circuit642, and an inverter643. The OR circuit641obtains the OR of the logic signals retrieved from each cathode electrode of the SPAD sensors511to514supplied through the comparators631to634. The OR output of the OR circuit641is supplied to the recharge signal generation circuit642. The recharge signal generation circuit642generates the recharge signal RCHG by delaying the OR output of the OR circuit641by a predetermined delay time. The inverter643inverts the logic of the recharge signal RCHG generated by the recharge signal generation circuit642and supplies the logic to the first switch units611to614.

Although the light receiving device30according to the second embodiment having the above configuration differs from the light receiving device30according to the first embodiment in that the logic of the comparators631to634and the recharge signal RCHG is inverted, the basic circuit operation is the same.

Third Embodiment

A third embodiment is a modification of the first embodiment, and is an example using another circuit configuration as the four-input OR circuit641.FIG.8shows a circuit configuration of the light receiving device30according to the third embodiment.

The light receiving device30according to the third embodiment has a circuit configuration using two two-input NOR circuits644,645and a two-input NAND circuit646instead of the four-input OR circuit641of the recharge control unit64. The NOR circuits644,645and the NAND circuit646have the same logic as that of the four-input OR circuit641, and obtain the OR of the logic signals of the SPAD sensors511to514supplied through the comparators631to634.

Note that, although the circuit configuration including the two NOR circuits644,645and the NAND circuit646has been described as an example of the other circuit configuration of the four-input OR circuit641, the circuit configuration is not limited to this circuit configuration, and other gate circuit configurations can be adopted as long as the logics are equivalent.

Fourth Embodiment

A fourth embodiment is a modification of the first embodiment, which is a first example of a method of retrieving pixel outputs.FIG.9shows a circuit configuration of the light receiving device30according to the fourth embodiment.

As is clear from the description inFIG.3, the pixel output is basically the output of each of the four pixels501to504. In the light receiving device30according to the fourth embodiment, the OR output ORoutof the four-input OR circuit641is retrieved as a pixel output through the level conversion unit65. The level conversion unit65converts the level of the OR output ORoutof the four-input OR circuit641to the power supply level of the logic circuit33at the subsequent stage, and outputs the information as information for detecting the photon incidence timing (pixel output).

The light receiving device30according to the fourth embodiment having the above configuration has a circuit configuration in which the level conversion unit65and circuits thereafter are also shared among the four pixels501to504. As a result, the circuit area of the circuit unit60per pixel can be reduced as compared with the case where the outputs of the four pixels501to504are derived. From the pixel output, the photon incidence timing to the SPAD sensors511to514can be detected.

Fifth Embodiment

A fifth embodiment is a modification of the first embodiment, which is a second example of a method of retrieving pixel outputs.FIG.10shows a circuit configuration of the light receiving device30according to the fifth embodiment.

In the light receiving device30according to the fifth embodiment, a four-input EX-OR circuit (exclusive-OR circuit)66that obtains the exclusive OR of logic signals whose logic is inverted at the time when photons are incident on one or more of the SPAD sensors511to514is used. In other words, the EX-OR circuit66obtains the exclusive OR of the logic signals of the SPAD sensors511to514supplied through the comparators631to634. Then, the exclusive logical output EXORoutis retrieved as a pixel output through the level conversion unit65. The level conversion unit65converts the level of the exclusive OR output ORoutof the four-input EX-OR circuit66, and outputs the information as information for detecting the photon incidence timing (pixel output).

FIG.11shows timing relationships among comparison outputs COMP_1to COMP_4of the comparators631to634, the OR output ORoutof the OR circuit641, and the exclusive OR output EXORoutof the EX-OR circuit66. The exclusive OR output EXORoutis used as the pixel output, so that, even if the second SPAD sensor fires before the recharge, the photon incidence timing can be detected.

Sixth Embodiment

A sixth embodiment is a modification of the fourth embodiment, and is an example of detecting the number of incident photons.FIG.12shows the circuit configuration of the light receiving device30according to the sixth embodiment.

In the light receiving device30according to the sixth embodiment, in addition to retrieving information for detecting the incident timing as a pixel output, information for detecting the number of incident photons to the SPAD sensors511to514is retrieved as a pixel output.

Specifically, the light receiving device30according to the sixth embodiment inputs each of the comparison outputs COMP_1to COMP_4of the comparators631to634to the adder67through the level conversion units651to654, the number of incident photons is counted by the adder67, and the addition output ADDoutis retrieved as a pixel output (information about the number of incidence).

FIG.13shows timing relationships among comparison outputs COMP_1to COMP_4of the comparators631to634, the OR output ORoutof the OR circuit641, and the addition output ADDoutof the adder67. By retrieving the addition output ADDoutof the adder67as the pixel output, it is possible to detect the number of incident photons from the pixel output to the SPAD sensors511to514.

Seventh Embodiment

A seventh embodiment is a modification of the first embodiment, and is an example in which the pixel output is retrieved for each pixel.FIG.14shows the circuit configuration of the light receiving device30according to the seventh embodiment.

In the light receiving device30according to the seventh embodiment, the comparison outputs COMP_1to COMP_4of the comparators631to634are retrieved as pixel outputs for each pixel through waveform shaping units681to684, respectively.

Specifically, the light receiving device30according to the seventh embodiment has the waveform shaping units681to684that performs processing of increasing the pulse width for each of the comparison outputs COMP_1to COMP_4(each input signal of the OR circuit641) of the comparators631to634, and outputs the result. The waveform shaping unit684includes a D-type flip-flop694in addition to the level conversion unit654that level-converts the comparison output COMP_4of the comparator634to the power supply potential VDD. This is similar in the other waveform shaping units681to683.

The D-type flip-flop694performs toggle operation in which the logic of the output is inverted each time an input is applied. As a result of this toggle operation, the D-type flip-flop694shapes the waveform of the comparison output COMP_4into a pulse signal having a pulse width wider than the comparison output COMP_4and makes the result a pixel output. This is similar in the other D type flip-flops691to693.FIG.15shows the timing relationship of the comparison outputs COMP_1to COMP_4of the comparators631to634. Each of the comparison outputs COMP_1to COMP_4becomes a pixel output through the waveform shaping units681to684.

Eighth Embodiment

An eighth embodiment is an example of the chip structure of the light receiving device30. As the chip structure of the light receiving device30, a stacked structure and a flat structure can be exemplified.

(Stacked Structure)

FIG.16shows an exploded perspective view of a stacked structure of the light receiving device30according to the eighth embodiment. Here, in order to facilitate understanding, a case where the number of pixels sharing the recharge control unit64is four, in other words, the SPAD sensors511to514having four pixels of two columns×two rows, and the circuit unit60including the shared recharge control unit64are shown.

The SPAD sensors511to514are arranged in a two-dimensional array on the sensor chip71including the first semiconductor substrate. The circuit unit60corresponding to the SPAD sensors511to514is formed on the circuit chip72including the second semiconductor substrate stacked on the sensor chip71.

The circuit unit60includes the first switch unit61(611to614) as a recharge switch, the second switch unit62as a quench switch, and the comparator63(631to634) that are provided for each SPAD sensor511to514, the recharge control unit64shared among the four pixels, and the like.

According to the stacked structure in which the sensor chip71and the circuit chip72are stacked of the above configuration, the recharge control unit64is shared among a plurality of pixels, so that the circuit area of the circuit unit60per pixel can be reduced, and thereby, the pixel50can be miniaturized, and further, the size of the chip size can be reduced.

Note that, in this example, the two-layer structure of the first-layer sensor chip71and the second-layer circuit chip72is described as an example of the stacked structure. However, the technology of the present disclosure is not limited to the two-layer structure, and three or more layered structure may be adopted.

(Flat Structure)

The technology of the present disclosure is not limited to the application to a chip structure having a stacked structure, and can also be applied to a chip structure having a flat structure.FIG.17shows a perspective view of a flat structure of the light receiving device30according to the eighth embodiment.

In the flat structure according to this example, on the same substrate as the sensor chip71in which the SPAD sensors511to514are arranged in a two-dimensional array, the circuit unit60including the first switch unit61, the second switch unit62, the comparator63, the recharge control unit64shared by four pixels, and the like, the logic circuit33, an I/O73, and a peripheral circuit74are integrated.

Also in the case of the flat structure of the above configuration, the recharge control unit64is shared among the plurality of pixels, so that, since the circuit area of the circuit unit60per pixel can be reduced, the aperture ratio can be increased while miniaturizing the pixel50.

Ninth Embodiment

A ninth embodiment is a first example in which the recharge signal generation circuit642of the recharge control unit64includes a ring oscillator.FIG.18shows a circuit configuration of the recharge signal generation circuit642according to the ninth embodiment.

The recharge signal generation circuit642according to the ninth embodiment includes a ring oscillator that oscillates by the connection in a ring shape of a two-input NAND circuit6421and a plurality of asymmetric delay elements64221to6422i. Here, the asymmetric delay element is a delay element in which the rising delay time td_rise_DLYand the falling delay time td_fall_DLYare different. An example of an asymmetric delay element is an inverter. In the input stage NAND circuit6421, the OR output ORoutof the OR circuit641is used as one input and the output of the last stage asymmetric delay element6422ias the recharge signal RCHG is used as the other input.

FIG.19shows a timing waveform diagram of each unit in the light receiving device30having the recharge signal generation circuit642of the above configuration.FIG.19shows the timing waveforms of the output of the OR circuit641, the output of the NAND circuit6421, the recharge signal RCHG, the cathode potential of the SPAD sensor51(511to514), and the output of the comparator63(631to634).

Using the ring oscillator having the above configuration as the recharge signal generation circuit642is preferable since a fine pulse width can be arbitrarily set for the recharge signal RCHG by adjusting the number of stages of the asymmetric delay elements64221to6422i. Note that, as shown inFIG.18, the four-input OR circuit641may have a circuit configuration including a combination of a four-input NOR circuit6411and an inverter6412.

Tenth Embodiment

A tenth embodiment is a second example in which the recharge signal generation circuit642of the recharge control unit64includes a ring oscillator.FIG.20shows a circuit configuration of the recharge signal generation circuit642according to the tenth embodiment.

The recharge signal generation circuit642according to the ninth embodiment includes the two-input NAND circuit6421and the plurality of asymmetric delay elements64221to6422i. On the other hand, the recharge signal generation circuit642according to the tenth embodiment uses a two-input NOR circuit6423instead of the two-input NAND circuit6421.

In using the two-input NOR circuit6423, the inverter6424is inserted in the path between the output end of the last stage asymmetric delay element6422iand the other input end of the NOR circuit6423. Furthermore, the four-input NOR circuit647is used in place of the four-input OR circuit641that takes the OR of the comparison outputs COMP_1to COMP_4of the comparators631to634. Thus, the recharge signal generation circuit642according to the tenth embodiment is a circuit having equivalent logic to the logic of the recharge signal generation circuit642according to the ninth embodiment.

Eleventh Embodiment

An eleventh embodiment is an example of an asymmetric delay element constituting the ring oscillator.FIG.21is a circuit configuration of an asymmetric delay element according to the eleventh embodiment. Here, the asymmetric delay element is exemplified as a four-stage configuration. However, the configuration is not limited thereto. This is similar in a twelfth embodiment and a thirteenth embodiment to be described later.

In the asymmetric delay element according to the eleventh embodiment, the first stage has a CMOS inverter configuration including a P-channel field effect transistor Qp1and an N-channel field effect transistor Qn1connected in series between the high potential side power supply and the low potential side power supply. Specifically, gate electrodes of the P-channel field effect transistor Qp1and the N-channel field effect transistor Qn1are connected in common to serve as input ends, and the drain electrodes are connected in common to serve as output ends.

Then, the transistor sizes of the P-channel field effect transistor Qp1and the N-channel field effect transistor Qn1are asymmetric. Specifically, if a channel width is W and a channel length is L, a transistor size W/L is set so that the P-channel field effect transistor Qp1is smaller than the N-channel field effect transistor Qn1. If the transistor size W/L is small, the on-resistance Ronis large, and if the transistor size W/L is large, the on-resistance Ronis small.

The second stage has a CMOS inverter configuration including a P-channel field effect transistor Qp2and an N-channel field effect transistor Qn2connected between the high potential side power supply and the low potential side power supply. In addition, the transistor size W/L is set so that the P-channel field effect transistor Qp2is larger than the N-channel field effect transistor Qn2.

The third stage has a CMOS inverter configuration including a P-channel field effect transistor Qp3and an N-channel field effect transistor Qn3. In addition, regarding the transistor size W/L, the setting is similar to that of the first stage CMOS inverter. The fourth stage has a CMOS inverter configuration including a P-channel field effect transistor Qp4and an N-channel field effect transistor Qn4. In addition, regarding the transistor size W/L, the setting is similar to that of the second stage CMOS inverter.

In the asymmetric delay element according to the eleventh embodiment having the above configuration, when the input signal transits from the high level to the low level, the transistor with the higher on-resistance Rondrives the next stage, so that the delay time becomes long. Conversely, when the input signal transits from the low level to the high level, the transistor with the smaller on-resistance Rondrives the next stage, so that the delay time becomes short. Accordingly, the rising delay time td_rise_DLYand the falling delay time td_fall_DLYare different.

Twelfth Embodiment

A twelfth embodiment is a modification of the eleventh embodiment, and is an example of switching the number of series (the number of series connections) of elements with high on-resistance constituting the CMOS inverter.FIG.22is a circuit configuration of the asymmetric delay element according to the twelfth embodiment.

In the asymmetric delay element according to the twelfth embodiment, the first stage has a CMOS inverter configuration including, for example, three P-channel field effect transistors Qp11, Qp12, and Qp13and an N-channel field effect transistor Qn11connected in series between the high potential side power supply and the low potential side power supply.

Specifically, gate electrodes of the P-channel field effect transistors Qp11, Qp12, and Qp13and the N-channel field effect transistor Qn11are connected in common to serve as input ends, and the drain electrodes of the field effect transistor Qp13and the field effect transistor Qn11are connected in common to serve as output ends.

In the first stage CMOS inverter of the above configuration, the P-channel field effect transistors Qp11, Qp12, and Qp13have higher on-resistance than the N-channel field effect transistor Qn11. Furthermore, for example, the sizes W/L of the P-channel field effect transistors Qp11, Qp12, and Qp13are set to be equal.

Furthermore, the P-channel field effect transistor Qp14is connected between the common connection node of the field effect transistor Qp11and the field effect transistor Qp12and the high potential side power supply. Moreover, the P-channel field effect transistor Qp15is connected between the common connection node of the field effect transistor Qp12and the field effect transistor Qp13and the high potential side power supply. A control signal D0is applied to the gate electrode of the P-channel field effect transistor Qp14, and a control signal D1is applied to the gate electrode of the P-channel field effect transistor Qp15.

Then, in accordance with the logic of the control signals D0, D1, the number of series connections of the P-channel field effect transistors Qp11, Qp12, and Qp13is changed. Specifically, when the control signals D0, D1are both logic 0, both the field effect transistors Qp14, Qp15are rendered conductive, so that only the field effect transistor Qp13is connected in series to the N-channel field effect transistor Qn11.

When the control signal D0is logic 0 and the control signal D1is logic 1, the field effect transistor Qp14is rendered conductive, and the field effect transistor Qp15is rendered non-conductive, so that the field effect transistors Qp12, Qp13are connected in series to the N-channel field effect transistor Qn11. When the control signals D0, D1are both logic 1, both the field effect transistors Qp14, Qp15are rendered non-conductive, so that the field effect transistors Qp11, Qp12, and Qp13are connected in series to the N-channel field effect transistor Qn11.

The second stage has a CMOS inverter configuration including a P-channel field effect transistor Qp21and, for example, three N-channel field effect transistors Qn21, Qn22, and Qn23connected in series between the high potential side power supply and the low potential side power supply. Specifically, gate electrodes of the P-channel field effect transistor Qp21and the N-channel field effect transistors Qn21, Qn22, and Qn23are connected in common to serve as input ends, and the drain electrodes of the field effect transistor Qp21and the field effect transistor Qn21are connected in common to serve as output ends.

In the second stage CMOS inverter of the above configuration, the N-channel field effect transistors Qn21, Qn22, and Qn23have higher on-resistance than the P-channel field effect transistor Qp21. Furthermore, for example, the sizes W/L of the N-channel field effect transistors Qn21, Qn22, and Qn23are set to be equal.

Furthermore, the P-channel field effect transistor Qp22is connected between the common connection node of the field effect transistor Qn21and the field effect transistor Qn22, and the low potential side power supply. Moreover, the P-channel field effect transistor Qp23is connected between the common connection node of the field effect transistor Qn22and the field effect transistor Qn23and the low potential side power supply. An inverted signal xD0of the control signal D0is applied to the gate electrode of the P-channel field effect transistor Qp22, and an inverted signal xD1of the control signal D1is applied to the gate electrode of the P-channel field effect transistor Qp23.

Then, in accordance with the logic of the control signals (inverted signals) xD0, xD1, the number of series connections of the N-channel field effect transistors Qn21, Qn22, Qn23is changed. Specifically, when the control signals xD0, xD1are both logic 0, both the field effect transistors Qp22, Qp23are rendered conductive, so that only the field effect transistor Qn21is connected in series to the P-channel field effect transistor Qp21.

When the control signals xD0is logic 1 and the control signal xD1is logic 0, the field effect transistor Qp22is rendered non-conductive, and the field effect transistor Qp23is rendered conductive, so that the field effect transistors Qn21, Qn22are connected in series to the P-channel field effect transistor Qp21. When the control signals D0, D1are both logic 1, both the field effect transistors Qp22, Qp23are rendered non-conductive, so that the field effect transistors Qn21, Qn22, Qn23are connected in series to the P-channel field effect transistor Qp21.

The third stage has a CMOS inverter configuration including, for example, three P-channel field effect transistors Qp31, Qp32, and Qp33and, the N-channel field effect transistor Qn31connected in series between the high potential side power supply and the low potential side power supply. Specifically, gate electrodes of the P-channel field effect transistors Qp31, Qp32, and Qp33and the N-channel field effect transistor Qn31are connected in common to serve as input ends, and the drain electrodes of the field effect transistor Qp33and the field effect transistor Qn31are connected in common to serve as output ends.

In the third stage CMOS inverter of the above configuration, the P-channel field effect transistors Qp31, Qp32, Qp33have higher on-resistance than the N-channel field effect transistor Qn31. Furthermore, for example, the sizes W/L of the P-channel field effect transistors Qp31, Qp32, and Qp33are set to be equal.

Furthermore, the P-channel field effect transistor Qp34is connected between the common connection node of the field effect transistor Qp31and the field effect transistor Qp32and the high potential side power supply. Moreover, the P-channel field effect transistor Qp15is connected between the common connection node of the field effect transistor Qp32and the field effect transistor Qp33and the high potential side power supply. A control signal D0is applied to the gate electrode of the P-channel field effect transistor Qp34, and a control signal D1is applied to the gate electrode of the P-channel field effect transistor Qp15. The circuit operation according to the logic of the control signals D0, D1is the same as that in the case of the first stage CMOS inverter.

The fourth stage has a CMOS inverter configuration including a P-channel field effect transistor Qp41and, for example, three N-channel field effect transistors Qn41, Qn42, and Qn43connected in series between the high potential side power supply and the low potential side power supply. Specifically, gate electrodes of the P-channel field effect transistor Qp41and the N-channel field effect transistors Qn41, Qn42, and Qn43are connected in common to serve as input ends, and the drain electrodes of the field effect transistor Qp41and the field effect transistor Qn41are connected in common to serve as output ends.

In the fourth stage CMOS inverter of the above configuration, the N-channel field effect transistors Qn41, Qn42, and Qn43have higher on-resistance than the P-channel field effect transistor Qp41. Furthermore, for example, the sizes W/L of the N-channel field effect transistors Qp41, Qp42, and Qp43are set to be equal.

Furthermore, the P-channel field effect transistor Qp42is connected between the common connection node of the field effect transistor Qn41and the field effect transistor Qp42and the low potential side power supply. Moreover, the P-channel field effect transistor Qp43is connected between the common connection node of the field effect transistor Qp42and the field effect transistor Qn43and the low potential side power supply. An inverted signal xD0of the control signal D0is applied to the gate electrode of the P-channel field effect transistor Qp42, and an inverted signal xD1of the control signal D1is applied to the gate electrode of the P-channel field effect transistor Qp43. The circuit operation according to the logic of the control signals (inverted signals) xD0, xD1is the same as that in the case of the second stage CMOS inverter.

As described above, in the asymmetric delay element according to the twelfth embodiment, the number of series connections of the field effect transistors having high on-resistance constituting the CMOS inverter is changed according to the logic of the control signals D0, D1. Specifically, in the CMOS inverters of the first and the third stages, the number of series connections of the P-channel field effect transistors is changed, and in the CMOS inverters of the second and fourth stages, the number of series connections of the N-channel field effect transistors is changed.FIG.23Ashows a truth table of the asymmetric delay element according to the twelfth embodiment.

The number of series connections of the field effect transistors having high on-resistance constituting the CMOS inverter is changed according to the logic of the control signals D0, D1, so that the delay time can be controlled. In the truth table ofFIG.23A, if the delay time when the control signals D0, D1are both logic 0 is td0, the delay time when the control signal D0is logic 0 and the control signal D1is logic 1 is td1, and the delay time when the control signals D0, D1are both logic 1 is td2, the magnitude relation td0<td1<td2is satisfied.

Thirteenth Embodiment

A thirteenth embodiment is a modification of the eleventh embodiment, and is an example of switching the number of parallel (the number of parallel connections) of elements with high on-resistance constituting the CMOS inverter.FIG.24shows a circuit configuration of the asymmetric delay element according to the thirteenth embodiment.

In the asymmetric delay element according to the thirteenth embodiment, in the first stage having a CMOS inverter including a P-channel field effect transistor Qp51and an N-channel field effect transistor Qn51connected in series between the high potential side power supply and the low potential side power supply, the P-channel field effect transistor Qp51has higher on-resistance than that of the N-channel field effect transistor Qn51. Then, for example, three P-channel field effect transistors having a high on-resistance, in other words, the field effect transistors Qp51, Qp52, and Qp53are connected in parallel.

Furthermore, the P-channel field effect transistor Qp54is connected between the P-channel field effect transistor Qp52and the high potential side power supply, and the P-channel field effect transistor Qp55is connected between the P-channel field effect transistor Qp53and the high potential side power supply. A control signal D0is applied to the gate electrode of the P-channel field effect transistor Qp54, and a control signal D1is applied to the gate electrode of the P-channel field effect transistor Qp55.

Then, in accordance with the logic of the control signals D0, D1, the number of parallel connections of the P-channel field effect transistors Qp51, Qp52, and Qp53is changed. Specifically, when the control signals D0, D1are both logic 0, both the field effect transistors Qp54, Qp55are rendered conductive, so that the field effect transistor Qp52and the field effect transistor Qp53are connected in parallel to the field effect transistor Qp51.

When the control signal D0is logic 0 and the control signal D1is logic 1, the field effect transistor Qp54is rendered conductive, and the field effect transistor Qp55is rendered non-conductive, so that the field effect transistor Qp52is connected in parallel to the field effect transistor Qp51. When the control signals D0, D1are both logic 1, both the field effect transistors Qp54, Qp55are rendered non-conductive, so that the field effect transistor Qp51is independently connected in series to the N-channel field effect transistor Qn51.

In the second stage having a CMOS inverter including a P-channel field effect transistor Qp61and an N-channel field effect transistor Qn61connected in series between the high potential side power supply and the low potential side power supply, the N-channel field effect transistor Qn61has higher on-resistance than that of the P-channel field effect transistor Qp61. Then, for example, three N-channel field effect transistors having a high on-resistance, in other words, the field effect transistors Qn61, Qn62, and Qn63are connected in parallel.

Furthermore, the P-channel field effect transistor Qp64is connected between the N-channel field effect transistor Qn62and the low potential side power supply, and the P-channel field effect transistor Qp65is connected between the N-channel field effect transistor Qn63and the low potential side power supply. An inverted signal xD0of the control signal D0is applied to the gate electrode of the P-channel field effect transistor Qp64, and an inverted signal xD1of the control signal D1is applied to the gate electrode of the P-channel field effect transistor Qp65.

Then, in accordance with the logic of the control signals (inverted signals) xD0, xD1, the number of parallel connections of the N-channel field effect transistors Qn61, Qn62, and Qn63is changed. Specifically, when the control signals D0, D1are both logic 0, both the field effect transistors Qp64, Qp65are rendered conductive, so that the field effect transistor Qn62and the field effect transistor Qn63are connected in parallel to the field effect transistor Qn61.

When the control signals xD0is logic 0 and the control signal xD1is logic 1, the field effect transistor Qp64is rendered conductive, and the field effect transistor Qp65is rendered non-conductive, so that the field effect transistor Qn62is connected in parallel to the field effect transistor Qn61. When the control signals xD0, xD1are both logic 1, both the field effect transistors Qp64, Qp65are rendered non-conductive, so that the field effect transistor Qn61is independently connected in series to the P-channel field effect transistor Qp61.

In the third stage having a CMOS inverter including a P-channel field effect transistor Qp71and an N-channel field effect transistor Qn71connected in series between the high potential side power supply and the low potential side power supply, the P-channel field effect transistor Qp71has higher on-resistance than that of the N-channel field effect transistor Qn71. Then, for example, three P-channel field effect transistors having a high on-resistance, in other words, the field effect transistors Qp71, Qp72, and Qp73are connected in parallel.

Furthermore, the P-channel field effect transistor Qp74is connected between the P-channel field effect transistor Qp72and the high potential side power supply, and the P-channel field effect transistor Qp75is connected between the P-channel field effect transistor Qp73and the high potential side power supply. A control signal D0is applied to the gate electrode of the P-channel field effect transistor Qp74, and a control signal D1is applied to the gate electrode of the P-channel field effect transistor Qp75. The circuit operation according to the logic of the control signals D0, D1is the same as that in the case of the first stage CMOS inverter.

In the fourth stage having a CMOS inverter including a P-channel field effect transistor Qp81and an N-channel field effect transistor Qn81connected in series between the high potential side power supply and the low potential side power supply, the N-channel field effect transistor Qn81has higher on-resistance than that of the P-channel field effect transistor Qp81. Then, for example, three N-channel field effect transistors having a high on-resistance, in other words, the field effect transistors Qn81, Qn82, and Qn83are connected in parallel.

Furthermore, the P-channel field effect transistor Qp84is connected between the N-channel field effect transistor Qn82and the low potential side power supply, and the P-channel field effect transistor Qp85is connected between the N-channel field effect transistor Qn83and the low potential side power supply. An inverted signal xD0of the control signal D0is applied to the gate electrode of the P-channel field effect transistor Qp84, and an inverted signal xD1of the control signal D1is applied to the gate electrode of the P-channel field effect transistor Qp85. The circuit operation according to the logic of the control signals (inverted signals) xD0, xD1is the same as that in the case of the second stage CMOS inverter.

As described above, in the asymmetric delay element according to the thirteenth embodiment, the number of parallel connections of the field effect transistors having high on-resistance constituting the CMOS inverter is changed according to the logic of the control signals D0, D1. Specifically, in the CMOS inverters of the first and the third stages, the number of parallel connections of the P-channel field effect transistors is changed, and in the CMOS inverters of the second and fourth stages, the number of parallel connections of the N-channel field effect transistors is changed.FIG.23Bshows a truth table of the asymmetric delay element according to the thirteenth embodiment.

The number of parallel connections of the field effect transistors having high on-resistance constituting the CMOS inverter is changed according to the logic of the control signals D0, D1, so that the delay time can be controlled. In the truth table ofFIG.23B, if the delay time when the control signals D0, D1are both logic 0 is td0, the delay time when the control signal D0is logic 0 and the control signal D1is logic 1 is td1, and the delay time when the control signals D0, D1are both logic 1 is td2, the magnitude relation td0<td1<td2is satisfied.

<Application Example of Technology According to the Present Disclosure>

The technology according to the present disclosure can be applied to various products. A more specific application example will be described below. For example, the technology according to the present disclosure may be realized as a distance measuring device mounted on any type of mobile body such as automobile, electric vehicle, hybrid electric vehicle, motorcycle, bicycle, personal mobility, airplane, drone, ship, robot, construction machine, agricultural machine (tractor).

(Mobile Body)

FIG.25is a block diagram showing a schematic configuration example of a vehicle control system7000which is an example of a mobile body control system to which the technology according to the present disclosure can be applied. The vehicle control system7000includes a plurality of electronic control units connected via a communication network7010. In the example shown inFIG.25, the vehicle control system7000includes a drive system control unit7100, a body system control unit7200, a battery control unit7300, a vehicle exterior information detection unit7400, a vehicle interior information detection unit7500, and an integrated control unit7600. The communication network7010connecting the plurality of control units may be, for example, an in-vehicle communication network conforming to an arbitrary standard such as the controller area network (CAN), the local interconnect network (LIN), the local area network (LAN), or the FlexRay (registered trademark).

Each control unit includes a microcomputer that performs operation processing according to various programs, a storage unit that stores programs executed by the microcomputer, parameters used for various operation, or the like, and a drive circuit that drives devices subjected to various control. Each control unit includes a network I/F for communicating with another control unit via the communication network7010, and includes a communication I/F for communication by wired communication or wireless communication with vehicle interior or exterior device, a sensor, or the like.FIG.25shows, as functional configuration of the integrated control unit7600, a microcomputer7610, a general-purpose communication I/F7620, a dedicated communication I/F7630, a positioning unit7640, a beacon reception unit7650, vehicle interior equipment I/F7660, an audio image output unit7670, an in-vehicle network I/F7680, and a storage unit7690. Similarly, each of the other control units includes a microcomputer, a communication I/F, a storage unit, and the like.

The drive system control unit7100controls the operation of the device related to the drive system of the vehicle according to various programs. For example, the drive system control unit7100functions as a control device of a driving force generation device for generating a drive force of a vehicle such as an internal combustion engine or a driving motor, a drive force transmission mechanism for transmitting a drive force to wheels, a steering mechanism that adjusts a wheeling angle of the vehicle, a braking device that generates a braking force of the vehicle, and the like. The drive system control unit7100may have a function as a control device such as antilock brake system (ABS), or an electronic stability control (ESC).

A vehicle state detection unit7110is connected to the drive system control unit7100. The vehicle state detection unit7110includes, for example, at least one of a gyro sensor that detects the angular velocity of the axis rotational motion of the vehicle body, an acceleration sensor that detects the acceleration of the vehicle, or a sensor for detecting an operation amount of an accelerator pedal, an operation amount of a brake pedal, steering of a steering wheel, an engine rotation speed, a wheel rotation speed, or the like. The drive system control unit7100performs operation processing using the signal input from the vehicle state detection unit7110and controls the internal combustion engine, the driving motor, the electric power steering device, the brake device, or the like.

The body system control unit7200controls the operation of various devices mounted on the vehicle according to various programs. For example, the body system control unit7200functions as a keyless entry system, a smart key system, a power window device, or a control device for various lamps such as a head lamp, a back lamp, a brake lamp, a turn indicator, or a fog lamp. In this case, radio waves transmitted from a portable device that substitutes keys or signals of various switches may be input to the body system control unit7200. The body system control unit7200receives input of these radio waves or signals and controls a door lock device, a power window device, a lamp, or the like of the vehicle.

The battery control unit7300controls a secondary battery7310that is a power supply source of the driving motor according to various programs. For example, information such as battery temperature, a battery output voltage or remaining capacity of the battery is input to the battery control unit7300from the battery device including the secondary battery7310. The battery control unit7300performs arithmetic processing using these signals and controls the temperature adjustment of the secondary battery7310, or the cooling device or the like included in the battery device.

The vehicle exterior information detection unit7400detects information outside the vehicle equipped with the vehicle control system7000. For example, at least one of the imaging unit7410or the vehicle exterior information detector7420is connected to the vehicle exterior information detection unit7400. The imaging unit7410includes at least one of a time of flight (ToF) camera, a stereo camera, a monocular camera, an infrared camera, or other cameras. The vehicle exterior information detector7420includes, for example, at least one of an environmental sensor for detecting the current weather or climate, or an ambient information detection sensor for detecting another vehicle, an obstacle, a pedestrian, or the like around the vehicle equipped with the vehicle control system7000.

The environmental sensor may be, for example, at least one of a raindrop sensor that detects rain, a fog sensor that detects mist, a sunshine sensor that detects sunshine degree, or a snow sensor that detects snowfall. The ambient information detection sensor may be at least one of an ultrasonic sensor, a radar device or a light detection and ranging, laser imaging detection and ranging (LIDAR) device. The imaging unit7410and the vehicle exterior information detector7420may be provided as independent sensors or devices, respectively, or may be provided as a device in which a plurality of sensors or devices are integrated.

Here,FIG.26shows an example of installation positions of the imaging unit7410and the vehicle exterior information detector7420. The imaging units7910,7912,7914,7916,7918are provided at, for example, at least one of a front nose, a side mirror, a rear bumper, or a back door, of the vehicle7900or an upper portion of a windshield in the vehicle compartment. The imaging unit7910provided for the front nose and the imaging unit7918provided in the upper portion of the windshield in the vehicle compartment mainly acquire an image ahead of the vehicle7900. The imaging units7912,7914provided in the side mirror mainly acquire an image of the side of the vehicle7900. The imaging unit7916provided in the rear bumper or the back door mainly acquires an image behind the vehicle7900. The imaging unit7918provided on the upper portion of the windshield in the vehicle compartment is mainly used for detecting a preceding vehicle, a pedestrian, an obstacle, a traffic signal, a traffic sign, a lane, or the like.

Note thatFIG.26shows an example of the imaging ranges of the imaging units7910,7912,7914,7916. An imaging range a indicates the imaging range of the imaging unit7910provided in the front nose, the imaging ranges b, c indicate the imaging ranges of the imaging units7912,7914provided in the side mirror, and the imaging range d indicates the imaging range of the imaging unit7916provided in the rear bumper or the back door. For example, by superimposing the image data imaged by the imaging units7910,7912,7914,7916, an overhead view image of the vehicle7900viewed from above is obtained.

The vehicle exterior information detectors7920,7922,7924,7926,7928,7930provided on the front, rear, side, or corner of the vehicle7900and the windshield in the upper portion of the vehicle compartment may be ultrasonic sensors or radar devices, for example. The vehicle exterior information detectors7920,7926,7930provided at the front nose, the rear bumper, or the back door of the vehicle7900, and the upper portion of the windshield of the vehicle compartment may be the LIDAR device, for example. These vehicle exterior information detectors7920to7930are mainly used for detecting a preceding vehicle, a pedestrian, an obstacle, or the like.

Returning toFIG.25, the description will be continued. The vehicle exterior information detection unit7400causes the imaging unit7410to image an image of the exterior of the vehicle and receives the imaged image data. Furthermore, the vehicle exterior information detection unit7400receives the detection information from the connected vehicle exterior information detector7420. In a case where the vehicle exterior information detector7420is an ultrasonic sensor, a radar device or a LIDAR device, the exterior information detection unit7400transmits ultrasonic waves, electromagnetic waves, or the like, and receives information of the received reflected waves. The vehicle exterior information detection unit7400may perform object detection processing or distance detection processing of a person, a car, an obstacle, a sign, a character on a road surface, or the like, on the basis of the received information. The vehicle exterior information detection unit7400may perform environment recognition processing for recognizing rainfall, fog, road surface condition, or the like on the basis of the received information. The vehicle exterior information detection unit7400may calculate the distance to the object outside the vehicle on the basis of the received information.

Furthermore, the vehicle exterior information detection unit7400may perform image recognition processing of recognizing a person, a car, an obstacle, a sign, a character on a road surface, or the like, on the basis of the received image data, or distance detection processing. The vehicle exterior information detection unit7400performs processing such as distortion correction or positioning on the received image data and combines the image data imaged by different imaging units7410to generate an overhead view image or a panorama image. The vehicle exterior information detection unit7400may perform viewpoint conversion processing using image data imaged by different imaging units7410.

The vehicle interior information detection unit7500detects vehicle interior information. For example, a driver state detection unit7510that detects the state of the driver is connected to the vehicle interior information detection unit7500. The driver state detection unit7510may include a camera for imaging the driver, a biometric sensor for detecting the biological information of the driver, a microphone for collecting sound in the vehicle compartment, and the like. The biometric sensor is provided on, for example, a seating surface, a steering wheel or the like, and detects biometric information of an occupant sitting on a seat or a driver holding a steering wheel. The vehicle interior information detection unit7500may calculate the degree of fatigue or the degree of concentration of the driver on the basis of the detection information input from the driver state detection unit7510, and may determine whether or not the driver is sleeping. The vehicle interior information detection unit7500may perform processing such as noise canceling processing on the collected sound signal.

The integrated control unit7600controls the overall operation of the vehicle control system7000according to various programs. An input unit7800is connected to the integrated control unit7600. The input unit7800is realized by a device such as a touch panel, a button, a microphone, a switch or a lever that can be input operated by an occupant, for example. Data obtained by performing speech recognition on the sound input by the microphone may be input to the integrated control unit7600. The input unit7800may be, for example, a remote control device using infrared rays or other radio waves, or an external connection device such as a mobile phone or a personal digital assistant (PDA) corresponding to the operation of the vehicle control system7000. The input unit7800may be, for example, a camera, in which case the occupant can input information by gesture. Alternatively, data obtained by detecting the movement of the wearable device worn by the occupant may be input. Moreover, the input unit7800may include, for example, an input control circuit or the like that generates an input signal on the basis of information input by an occupant or the like using the input unit7800and outputs the input signal to the integrated control unit7600. By operating the input unit7800, an occupant or the like inputs various data or instructs processing operation to the vehicle control system7000.

The storage unit7690may include a read only memory (ROM) that stores various programs to be executed by the microcomputer, and a random access memory (RAM) that stores various parameters, operation results, sensor values, or the like. Furthermore, the storage unit7690may be realized by a magnetic storage device such as a hard disc drive (HDD), a semiconductor storage device, an optical storage device, a magneto-optical storage device, or the like.

The general-purpose communication I/F7620is a general-purpose communication I/F that mediates communication with various devices existing in an external environment7750. A cellular communication protocol such as global system of mobile communications (GSM) (registered trademark), WiMAX, long term evolution (LTE), or LTE-advanced (LTE-A), or other wireless communication protocols such as a wireless LAN (Wi-Fi (registered trademark)), or Bluetooth (registered trademark), may be implemented in the general-purpose communication I/F7620. The general-purpose communication I/F7620may be connected to a device (for example, an application server or a control server) existing on an external network (for example, the Internet, a cloud network or a company specific network) via a base station or an access point, for example. Furthermore, the general-purpose communication I/F7620uses, for example, the peer to peer (P2P) technology to perform connection with a terminal existing in the vicinity of the vehicle (for example, a terminal of a driver, a pedestrian or a shop, or the machine type communication terminal (MTC).

The dedicated communication I/F7630is a communication I/F supporting a communication protocol formulated for use in a vehicle. For example, in the dedicated communication I/F7630, a standard protocol such as the wireless access in vehicle environment (WAVE) that is combination of lower layer IEEE 802.11p and upper layer IEEE 1609, the dedicated short range communications (DSRC), or the cellular communication protocol may be implemented. Typically, the dedicated communication I/F7630performs V2X communication that is concept including one or more of a vehicle to vehicle communication, a vehicle to infrastructure communication, a vehicle to home communication, and a vehicle to pedestrian communication.

The positioning unit7640receives a global navigation satellite system (GNSS) signal from a GNSS satellite (for example, a GPS signal from a global positioning system (GPS) satellite) and performs positioning, to generate position information including the latitude, longitude, and altitude of the vehicle. Note that the positioning unit7640may specify the current position by exchanging signals with the wireless access point or may acquire the position information from a terminal such as a mobile phone, a PHS or a smartphone having a positioning function.

The beacon reception unit7650receives, for example, radio waves or electromagnetic waves transmitted from a radio station or the like installed on the road, and acquires information such as the current position, congestion, road closure or required time. Note that the function of the beacon reception unit7650may be included in the dedicated communication I/F7630described above.

The vehicle interior equipment I/F7660is a communication interface that mediates connection between the microcomputer7610and various interior equipment7760existing in the vehicle. The vehicle interior equipment I/F7660may establish a wireless connection using a wireless communication protocol such as wireless LAN, Bluetooth (registered trademark), near field communication (NFC), or a wireless USB (WUSB). Furthermore, the vehicle interior equipment I/F7660may establish wired connection such as a universal serial bus (USB), a high-definition multimedia interface (HDMI (registered trademark)), or a mobile high-definition link (MHL) via a connection terminal not shown (and a cable if necessary). The vehicle interior equipment7760may include, for example, at least one of a mobile device or a wearable device possessed by an occupant, or an information device carried in or attached to the vehicle. Furthermore, the vehicle interior equipment7760may include a navigation device that performs a route search to an arbitrary destination. The vehicle interior equipment I/F7660exchanges control signals or data signals with these vehicle interior equipment7760.

The in-vehicle network I/F7680is an interface mediating communication between the microcomputer7610and the communication network7010. The in-vehicle network I/F7680transmits and receives signals and the like according to a predetermined protocol supported by the communication network7010.

The microcomputer7610of the integrated control unit7600controls the vehicle control system7000in accordance with various programs on the basis of information acquired via at least one of the general-purpose communication I/F7620, the dedicated communication I/F7630, the positioning unit7640, the beacon reception unit7650, the vehicle interior equipment I/F7660, or the in-vehicle network I/F7680. For example, the microcomputer7610may operate a control target value of the drive force generation device, the steering mechanism, or the braking device on the basis of acquired information inside and outside the vehicle, and output a control command to the drive system control unit7100. For example, the microcomputer7610may perform cooperative control for the purpose of function realization of an advanced driver assistance system (ADAS) including collision avoidance or impact mitigation of the vehicle, follow-up running based on inter-vehicle distance, vehicle speed maintenance running, vehicle collision warning, vehicle lane departure warning, or the like. Furthermore, the microcomputer7610may perform cooperative control for the purpose of automatic driving or the like by which a vehicle autonomously runs without depending on the operation of the driver by controlling the drive force generation device, the steering mechanism, the braking device, or the like on the basis of the acquired information on the surroundings of the vehicle.

The microcomputer7610may generate three-dimensional distance information between the vehicle and a surrounding structure, an object, a person, or the like on the basis of the information acquired via at least one of the general-purpose communication I/F7620, the dedicated communication I/F7630, the positioning unit7640, the beacon reception unit7650, the vehicle interior equipment I/F7660, or the in-vehicle network I/F7680, and create local map information including peripheral information on the current position of the vehicle. Furthermore, the microcomputer7610may predict danger such as collision of a vehicle, approach of a pedestrian, or entry into a road where traffic is stopped, or the like on the basis of acquired information to generate a warning signal. The warning signal may be, for example, a signal for generating an alarm sound or for turning on a warning lamp.

The audio image output unit7670transmits an output signal of at least one of audio and image to an output device capable of visually or audibly notifying the occupant of the vehicle or the outside of the vehicle, of information. In the example ofFIG.25, as an output device, an audio speaker7710, a display unit7720, and an instrument panel7730are illustrated. The display unit7720may include at least one of an on-board display or a head-up display, for example. The display unit7720may have an augmented reality (AR) display function. The output device may be other devices including a wearable device such as a headphone, a spectacular display worn by an occupant, a projector, a lamp, or the like other than these devices. In a case where the output device is a display device, the display device visually displays the result obtained by the various processing performed by the microcomputer7610or the information received from the other control unit in various formats such as text, image, table, or graph. Furthermore, in a case where the output device is an audio output device, the audio output device converts an audio signal including reproduced audio data, acoustic data, or the like into an analog signal, and outputs the result audibly.

Note that, in the example shown inFIG.25, at least two control units connected via the communication network7010may be integrated as one control unit. Alternatively, each control unit may be constituted by a plurality of control units. Moreover, the vehicle control system7000may include another control unit not shown. Furthermore, in the above description, some or all of the functions carried out by any one of the control units may be performed by the other control unit. That is, as long as information is transmitted and received via the communication network7010, predetermined operation processing may be performed by any control unit. Similarly, a sensor or device connected to any of the control units may be connected to another control unit, and a plurality of control units may transmit and receive detection information to and from each other via the communication network7010.

An example of the vehicle control system to which the technology according to the present disclosure can be applied has been described above. For example, the technology according to the present disclosure can be applied to the imaging units7910,7912,7914,7916,7918and the vehicle exterior information detectors7920,7922,7924,7926,7928,7930, among the configurations described above. In addition, by applying the technology according to the present disclosure, the circuit area per pixel can be reduced, so that it is possible to reduce the size of the imaging unit and the vehicle exterior information detector.

<Configuration that the Present Disclosure can Take>

The present disclosure can adopt the following configuration.

<<A. Light Receiving Device>>

[A-1] A light receiving device including:

a pixel array unit having a plurality of pixels each including a light receiving unit that generates a signal in response to reception of photons;a first switch unit that recharges the light receiving unit; anda recharge control unit that controls the first switch unit in accordance to output of the light receiving unit,the recharge control unit being shared among the plurality of pixels.
[A-2] The light receiving device described in [A-1] described above, in which,in a case where photons are incident on one or more light receiving units among light receiving units of a plurality of pixels that share the recharge control unit, the recharge control unit performs recharging for all of the light receiving units of the plurality of pixels.
[A-3] The light receiving device described in [A-2] described above, in whichthe recharge control unit has an OR circuit that takes the OR of logic signals whose logic is inverted at the time when photons are incident on one or more light receiving units, and performs recharging in response to an OR signal of the OR circuit.
[A-4] The light receiving device described in any of [A-1] to [A-3] described above, in whichthe light receiving unit includes a single photon avalanche diode.
[A-5] The light receiving device described in [A-4] described above, in whicha signal is retrieved from a cathode electrode side of the single photon avalanche diode.
[A-6] The light receiving device described in [A-4] described above, in whicha signal is retrieved from an anode electrode side of the single photon avalanche diode.
[A-7] The light receiving device described in [A-3] described above, includinga level conversion unit that converts the level of the OR signal of the OR circuit is provided, in which a conversion result of the level conversion unit is output as information for detecting the photon incidence timing.
[A-8] The light receiving device described in [A-3] described above, includingan exclusive OR circuit that retrieves the exclusive OR of logic signals whose logic is inverted at the time when photons are incident on one or more light receiving units, and a level conversion unit that converts the level of the exclusive OR signal of the exclusive OR circuit, in whicha conversion result of the level conversion unit is output as information for detecting the photon incidence timing.
[A-9] The light receiving device described in [A-3] described above, includingan adder is provided that adds the number of photons incident on a plurality of pixels sharing the recharge control unit, in which an addition result of the adder is output as information for detecting the number of incident photons.
[A-10] The light receiving device described in [A-3] described above, in whicheach of the input signals of the OR circuit has a configuration in which a waveform shaping unit is provided that performs processing for increasing the pulse width and outputs the result.
[A-11] The light receiving device described in [A-4] described above, includinga quenching circuit that lowers the applied voltage with respect to the single photon avalanche diode to a breakdown voltage.
[A-12] The light receiving device described in [A-11] described above, in whichthe quenching circuit is constituted by a second switch unit connected in parallel to a first switch unit, and operates according to the output of the light receiving unit.
[A-13] The light receiving device described in [A-1] described above, in whichthe recharge control unit has a recharge signal generation circuit that generates a recharge signal for driving the first switch unit, andthe recharge signal generation circuit includes a ring oscillator.
[A-14] The light receiving device described in [A-13] described above, in whichthe ring oscillator includes an asymmetric delay element having different rising delay time and falling delay time.
[A-15] The light receiving device described in [A-14] described above, in whichthe asymmetric delay element includes a CMOS inverter, and has a P-channel field effect transistor and an N-channel field effect transistor having different sizes.
[A-16] The light receiving device described in [A-15] described above, in whichthe delay time of the asymmetric delay element is variable.
[A-17] The light receiving device described in [A-16] described above, in whichthe number of series connections of the transistor having higher on-resistance among the P-channel field effect transistor and the N-channel field effect transistor is variable, and the delay time is set according to the number of series connections.
[A-18] The light receiving device described in [A-16] described above, in whichthe number of parallel connections of the transistor having higher on-resistance among the P-channel field effect transistor and the N-channel field effect transistor is variable, and the delay time is set according to the number of parallel connections.
[A-19] The light receiving device described in any of [A-1] to [A-18] described above, includinga stacked structure in which a first semiconductor substrate on which the light receiving unit is arranged, and a second semiconductor substrate on which the recharge control unit is arranged are stacked.
<<B. Distance Measuring Device>>
[B-1] A distance measuring device including a light source that irradiates an object to be measured with light, and a light receiving device that receives light reflected by the object to be measured, in whichthe light receiving device includes:a pixel array unit arranged with a plurality of pixels each including a light receiving unit;a first switch unit that recharges the light receiving unit; anda recharge control unit that controls the first switch unit in accordance to output of the light receiving unit,the recharge control unit being shared among the plurality of pixels.
[B-2] The distance measuring device described in [B-1] described above, in which,in a case where photons are incident on one or more light receiving units among light receiving units of a plurality of pixels that share the recharge control unit, the recharge control unit performs recharging for all of the light receiving units of the plurality of pixels.
[B-3] The distance measuring device described in [B-2] described above, in whichthe recharge control unit has an OR circuit that takes the OR of logic signals whose logic is inverted at the time when photons are incident on one or more light receiving units, and performs recharging in response to an OR signal of the OR circuit.
[B-4] The distance measuring device described in any of [B-1] to [B-3] described above, in whichthe light receiving unit includes a single photon avalanche diode.
[B-5] The distance measuring device described in [B-4] described above, in whicha signal is retrieved from a cathode electrode side of the single photon avalanche diode.
[B-6] The distance measuring device described in [B-4] described above, in whicha signal is retrieved from an anode electrode side of the single photon avalanche diode.
[B-7] The distance measuring device described in [B-3] described above, in whicha level conversion unit that converts the level of the OR signal of the OR circuit is provided, and a conversion result of the level conversion unit is output as information for detecting photon incidence timing.
[B-8] The distance measuring device described in [B-3] described above, in whichan exclusive OR circuit that retrieves exclusive OR of logic signals whose logic is inverted at the time when photons are incident on one or more light receiving units, and a level conversion unit that converts the level of the exclusive OR signal of the exclusive OR circuit are provided, andthe conversion result of the level conversion unit is output as information for detecting the photon incidence timing.
[B-9] The distance measuring device described in [B-3] described above, in whichan adder is provided that adds the number of photons incident on a plurality of pixels sharing the recharge control unit, and an addition result of the adder is output as information for detecting the number of incident photons.
[B-10] The distance measuring device described in [B-3] described above, in whicheach of the input signals of the OR circuit has a configuration in which a waveform shaping unit is provided that performs processing for increasing the pulse width and outputs the result.
[B-11] The distance measuring device described in [B-4] described above, includinga quenching circuit that lowers the applied voltage with respect to the single photon avalanche diode to a breakdown voltage.
[B-12] The distance measuring device described in [B-11] described above, in whichthe quenching circuit is constituted by a second switch unit connected in parallel to a first switch unit, and operates according to the output of the light receiving unit.
[B-13] The distance measuring device described in [B-1] described above, in whichthe recharge control unit has a recharge signal generation circuit that generates a recharge signal for driving the first switch unit, andthe recharge signal generation circuit includes a ring oscillator.
[B-14] The distance measuring device described in [B-13] described above, in whichthe ring oscillator includes an asymmetric delay element having different rising delay time and falling delay time.
[B-15] The distance measuring device described in [B-14] described above, in whichthe asymmetric delay element includes a CMOS inverter, and has a P-channel field effect transistor and an N-channel field effect transistor having different sizes.
[B-16] The distance measuring device described in [B-15] described above, in whichthe delay time of the asymmetric delay element is variable.
[B-17] The distance measuring device described in [B-16] described above, in whichthe number of series connections of the transistor having higher on-resistance among the P-channel field effect transistor and the N-channel field effect transistor is variable, and the delay time is set according to the number of series connections.
[B-18] The distance measuring device described in [B-16] described above, in whichthe number of parallel connections of the transistor having higher on-resistance among the P-channel field effect transistor and the N-channel field effect transistor is variable, and the delay time is set according to the number of parallel connections.
[B-19] The distance measuring device described in any of [B-1] to [B-18] described above, includinga stacked structure in which a first semiconductor substrate on which the light receiving unit is arranged, and a second semiconductor substrate on which the recharge control unit is arranged are stacked.

It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and alterations may occur depending on design requirements and other factors insofar as they are within the scope of the appended claims or the equivalents thereof.

REFERENCE SIGNS LIST

1Distance measuring device10Subject (object to be measured)20Light source21Laser driver22Laser light source23Diffusing lens30Light receiving device31Light receiving lens32Light sensor33Circuit unit40Control unit50(501to504) Pixel51(511to514) SPAD sensor60Circuit unit61(611to614) First switch unit62Second switch unit63(631to634) Comparator64Recharge control unit65Level conversion unit71Sensor chip72Circuit chip