Patent ID: 12255647

The present disclosure is susceptible to various modifications and alternative forms, and some representative embodiments have been shown by way of example in the drawings and will be described in detail herein. It should be understood, however, that the invention is not intended to be limited to the particular forms disclosed. Rather, the disclosure is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention as defined by the appended claims.

DETAILED DESCRIPTION OF THE ILLUSTRATED EMBODIMENTS

Various embodiments are described with reference to the attached figures, where like reference numerals are used throughout the figures to designate similar or equivalent elements. The figures are not necessarily drawn to scale and are provided merely to illustrate aspects and features of the present disclosure. Numerous specific details, relationships, and methods are set forth to provide a full understanding of certain aspects and features of the present disclosure, although one having ordinary skill in the relevant art will recognize that these aspects and features can be practiced without one or more of the specific details, with other relationships, or with other methods. In some instances, well-known structures or operations are not shown in detail for illustrative purposes. The various embodiments disclosed herein are not necessarily limited by the illustrated ordering of acts or events, as some acts may occur in different orders and/or concurrently with other acts or events. Furthermore, not all illustrated acts or events are necessarily required to implement certain aspects and features of the present disclosure.

For purposes of the present detailed description, unless specifically disclaimed, and where appropriate, the singular includes the plural and vice versa. The word “including” means “including without limitation.” Moreover, words of approximation, such as “about,” “almost,” “substantially,” “approximately,” and the like, can be used herein to mean “at,” “near,” “nearly at,” “within 3-5% of,” “within acceptable manufacturing tolerances of,” or any logical combination thereof. Similarly, terms “vertical” or “horizontal” are intended to additionally include “within 3-5% of” a vertical or horizontal orientation, respectively. Additionally, words of direction, such as “top,” “bottom,” “left,” “right,” “above,” and “below” are intended to relate to the equivalent direction as depicted in a reference illustration; as understood contextually from the object(s) or element(s) being referenced, such as from a commonly used position for the object(s) or element(s); or as otherwise described herein. Further, it is noted that the term “signal” means a waveform (e.g., electrical, optical, magnetic, mechanical or electromagnetic) capable of traveling through a medium such as DC, AC, sinusoidal-wave, triangular-wave, square-wave, vibration, and the like.

Embodiments of this disclosure relate to a system that reduces power consumption for a memory module in a microcontroller system by providing fine-grained voltage adjustment capabilities. The system includes multiplexors that dynamically switch between voltage rails from a voltage source to deliver customized voltage options for individual or groups of memory blocks in the memory module, based on an operational parameter of the memory blocks. Thus, as the microcontroller system switches between an active mode and a deep sleep mode, a customized voltage may be delivered to individual memory blocks based on their workload, storage status, process control speed, temperature, etc. This results in a minimally necessary voltage being applied to the individual memory block and the memory module, thereby significantly reducing power consumption of the microcontroller system.

FIGS.1A-1Bare a block diagram of an example low power microcontroller system100. The low power microcontroller system100includes a central processing unit (CPU)110. In some embodiments, the CPU110in this example is Cortex M4F (CM4) with a floating point unit. The CPU110includes a System-bus interface112, a Data-bus interface114, and an Instruction-bus interface116. It is to be understood, that other types of general CPUs, or other processors such as DSPs or NPUs may incorporate the principles described herein.

The System-bus interface112is coupled to a Cortex M4 advanced peripheral bus (APB) bridge120that is coupled to an advanced peripheral bus (APB) direct memory access (DMA) module122. The microcontroller system100includes a Data Advanced eXtensible Interface (DAXI)124, a tightly coupled memory (TCM)126, a cache128, and a boot ROM130. The Data-bus interface114allows access to the DAXI124, the TCM126, the cache128, and the boot read only memory (ROM)130. The Instruction-bus interface116allows access to the TCM126, the cache128, and the boot ROM130. In this example, the DAXI interface124provides write buffering and caching functionality for the microcontroller system100. The DAXI interface124improves performance when accessing peripherals like the SRAM and the MSPIs.

An Advanced Peripheral Bus (APB)132and an Advanced eXtensible Interface (AXI) bus134are provided for communication between components on the microcontroller system100. The APB132is a low speed and low overhead interface that is used for communicating with peripherals and registers that do not require high performance and do not change often (e.g., when a controller wants to set configuration bits for a serial interface). The AXI bus134is an ARM standard bus protocol that allows high speed communications between multiple masters and multiple busses. This is useful for peripherals that exchange large amounts of data (e.g., a controller that talks to an ADC and needs to transfer ADC readings to a microcontroller or a GPU that talks to a memory and needs to transfer a large amount of graphics data to/from memories).

A fast general purpose input/output (GPIO) module136is coupled to the APB bridge120. A GPIO module138is coupled to the fast GPIO module136. The APB132is coupled to the GPIO module138. The APB132is coupled to a series of Serial Peripheral Interface/Inter-Integrated Circuit (SPI/I2C) interfaces140and a series of Multi-bit Serial Peripheral Interfaces (MSPI)s142. The MSPIs142are also coupled to the AXI bus134and provide access to external memory devices.

The APB132is also coupled to a SPI/I2C interface144, a universal serial bus (USB) interface146, an analog to digital converter (ADC)148, an Integrated Inter-IC Sound Bus (I2S) interface150, a set of Universal Asynchronous Receiver/Transmitters (UART)s152, a timer module154, a watch dog timer circuit156, a series of pulse density modulation (PDM) interfaces158, a low power audio ADC160, a cryptography module162, a Secure Digital Input Output/Embedded Multi-Media Card (SDIO/eMMC) interface164, and a SPI/I2C slave interface module166. The PDM interfaces158may be connected to external digital microphones. The low power audio ADC160may be connected to an external analog microphone through internal programmable gain amplifiers (PGA).

A system non-volatile memory (NVM), which is 2 MB in size in this example, is accessible through the AXI bus134. A system static random access memory (SRAM)170, which is 1 MB in this example is accessible through the AXI bus134. The microcontroller system100further includes a display interface172and a graphics interface174that are coupled to the APB bus132and the AXI bus134.

Components of the disclosed microcontroller system100are further described by U.S. Provisional Ser. No. 62/557,534, titled “Very Low Power Microcontroller System,” filed Sep. 12, 2017; U.S. application Ser. No. 15/933,153, filed Mar. 22, 2018 titled “Very Low Power Microcontroller System,” (Now U.S. Pat. No. 10,754,414), U.S. Provisional Ser. No. 62/066,218, titled “Method and Apparatus for Use in Low Power Integrated Circuit,” filed Oct. 20, 2014; U.S. application Ser. No. 14/855,195, titled “Peripheral Clock Management,” (Now U.S. Pat. No. 9,703,313), filed Sep. 15, 2015; U.S. application Ser. No. 15/516,883, titled “Adaptive Voltage Converter,” (Now U.S. Pat. No. 10,338,632), filed Sep. 15, 2015; U.S. application Ser. No. 14/918,406, titled “Low Power Asynchronous Counters in a Synchronous System,” (Now U.S. Pat. No. 9,772,648), filed Oct. 20, 2015; U.S. application Ser. No. 14/918,397, titled “Low Power Autonomous Peripheral Management,” (Now U.S. Pat. No. 9,880,583), filed Oct. 20, 2015; U.S. application Ser. No. 14/879,863, titled “Low Power Automatic Calibration Method for High Frequency Oscillators,” (Now U.S. Pat. No. 9,939,839), filed Oct. 9, 2015; U.S. application Ser. No. 14/918,437, titled “Method and Apparatus for Monitoring Energy Consumption,” (Now U.S. Pat. No. 10,578,656), filed Oct. 20, 2015; U.S. application Ser. No. 17/081,378, titled “Improved Voice Activity Detection Using Zero Crossing Detection,” filed Oct. 27, 2020, U.S. application Ser. No. 17/081,640, titled “Low Complexity Voice Activity Detection Algorithm,” filed Oct. 27, 2020, all of which are hereby incorporated by reference.

FIG.2shows a block diagram of an analog module200that interfaces external components with the microcontroller system100inFIG.1. The analog module200supplies power to different components of the microprocessor system100as well as providing clocking signals to the microcontroller system100. The analog module200includes a Single Inductor Multiple Output (SIMO) buck converter210, a core low drop-out (LDO) voltage regulator212, and a memory LDO voltage regulator214. The SIMO buck converter210supplies DC voltage at different levels to components and devices of the microcontroller system100inFIG.1and the analog module200inFIG.2. The LDO voltage regulator212supplies power to processor cores of the microcontroller system100, while the memory LDO voltage regulator214supplies power to volatile memory devices of the microcontroller system100, such as the SRAM170. A switch module216represents switches that allow connection of power to the different components of the microcontroller system100.

The SIMO buck converter210is coupled to an external inductor220. The module200is coupled to a core VDD (VDDC) capacitor222and a memory VDD (VDDF) capacitor224. The VDDC capacitor222smooths the voltage output of the core LDO voltage regulator212and the SIMO buck converter210. The VDDF capacitor224smooths the voltage output of the memory LDO voltage regulator214and the SIMO buck converter210. The analog module200is also coupled to an external crystal226.

The SIMO buck converter210is coupled to a high frequency resistor-capacitor (HFRC) oscillator circuit230, a low frequency resistor-capacitor (LFRC) circuit232, and a temperature-sensitive voltage reference generator (TVRG) circuit234. A calibrated voltage reference generator (CVRG) circuit236is coupled to the SIMO buck converter210, the core LDO voltage regulator212, and the memory LDO voltage regulator214. Thus, both voltage compensation and temperature compensation are performed on the voltage sources. A set of current reference circuits238is provided as well as a set of voltage reference circuits240.

In this example, the LDO voltage regulators212,214are optionally used to power up the microcontroller system100. The more efficient SIMO buck converter210is preferably used to power the same components.

A crystal oscillator circuit242is coupled to the external crystal226. The crystal oscillator circuit242, LFRC oscillator232, and HFRC oscillator230together serve as a set of clock sources244. The clock sources244include multiple clocks providing different frequency signals to the components on the microcontroller system100.

The analog module200also includes a process control monitor (PCM)250and a test multiplexor252. Both the PCM250and the test multiplexor252allow testing and trimming of the microcontroller system100prior to shipment. The PCM250includes test structure that allow programming of the compensation voltage regulator236. The test multiplexor252allows trimming of different components on the microcontroller system100. The analog module200includes a power monitoring module254that allows power levels to different components on the microcontroller system100to be monitored. The power monitoring module254, in this example, includes multiple state machines that determine when power is required by different components of the microprocessor system100. The power switch module216connects voltages generated by the SIMO buck converter210and LDOs212and214with voltage rails that support components of the microprocessor system100. The analog module200includes a low power audio module260for audio channels, a microphone bias module262for biasing external microphones, and a general purpose analog to digital converter264.

FIGS.3-4show schematic block diagrams of systems300,400including memory modules320,420with fine-grained voltage adjustment capabilities, respectively. In some embodiments, the memory module320may be the SRAM170, the cache128, or the tightly coupled memory TCM126inFIG.1. The memory module320includes one or more memory blocks (alternatively ‘arrays’, ‘macros’, or ‘banks’)3201,3202,3203, . . . ,320n. The memory blocks3201,3202,3203, . . . ,320nhave a structure in which data is stored in bitcells that are arranged in rows and columns. In some embodiments, such as the one shown inFIG.3, each of the memory blocks3201,3202,3203, . . . ,320nis electrically connected to a corresponding one of a plurality of multiplexors3401,3402,3403, . . . ,340n. However, such1:1correspondence between a memory block and a multiplexor may not be implemented in other embodiments, where a single multiplexor may be electrically connected to more than one memory block (e.g., the system400ofFIG.4).

In some embodiments, each of the memory blocks3201,3202,3203, . . . ,320nincludes means for measuring temperature such that the applied voltage can be adjusted based on the temperature of each of the memory blocks3201,3202,3203, . . . ,320n. In some embodiments, such as in the example embodiment ofFIG.3, this can be accomplished by temperature sensors3251,3252,3253, . . . ,325ndisposed in each of the memory blocks3201,3202,3203, . . . ,320n. The temperature sensors3251,3252,3253, . . . ,325nmeasure temperature via closed-loop hardware or alternatively, via software. In other embodiments, such as the in the example embodiment ofFIG.4, this can be accomplished by a single temperature sensor425(FIG.4). The measured temperature is used for dynamically adjusting the voltage delivered to each of the memory blocks3201,3202,3203, . . . ,320n. In some embodiments, the temperature can be measured for each of the memory blocks3201,3202,3203, . . . ,320n(FIG.3), while in others, the temperature can be measured for the entire memory module420(FIG.4).

The system300includes a voltage generation module310, which supplies voltage from a voltage source such a converter or a voltage regulator. In some embodiments of the low power microcontroller system100, the voltage generation module310may be the SIMO buck converter210(FIG.2), which is the main voltage source of the microcontroller system100and ensures maximum power efficiency. The SIMO buck converter210ensures maximum power efficiency by minimizing the overhead of generating multiple voltage rails. In other embodiments, the voltage generation module310may be a voltage regulator such as, but not limited to, a low dropout regulator (LDO), switched capacitance converter, or another step-down voltage regulator that is located proximal to the memory module320.

The voltage generation module310supplies voltage through two or more voltage rails, by electrical connection, to each of the plurality of multiplexors3401,3402,3403, . . . ,340n. In some embodiments, such as the one shown inFIG.3, the voltage generation module310provides exactly two voltage rails to the inputs to each of the plurality of multiplexors3401,3402,3403, . . . ,340n. However, in different embodiments, more than two voltage rails may be connected between the voltage generation module310and each of the plurality of multiplexors3401,3402,3403, . . . ,340n. Each of the voltage rails provide a different voltage option, preset or customizable, to the memory blocks connected through the corresponding multiplexor. For example, two voltage rails from the voltage generation module310provides two different voltage options for the memory block3201through the multiplexor3401, two voltage rails from the voltage generation module310provides two different voltage options for the memory block3202through the multiplexor3402, and so on. Thus, the multiplexors3401,3402,3403, . . . ,340ncan be controlled via a selection signal to output one of the voltage rails depending on the required voltage to operate the corresponding attached memory block such as the memory block3201.

In some embodiments, the voltage options may be standard (e.g., 0V, 0.3V, 0.4V, 0.5V, 0.7V, 1.8V, etc.) for each of the memory blocks3201,3202,3203, . . . ,320n. In other embodiments, the voltage options may be unique for each of the memory blocks3201,3202,3203, . . . ,320n. Further, in some embodiments, the voltage rails may provide a same or a different voltage to each of the memory blocks3201,3202,3203, . . . ,320n, or across different memory modules320. The voltage options are generally a function of manufacturing process corners (e.g., voltage is set to a higher value at “slow” process corners and a lower value at “fast” process corners to compensate for manufacturing variations, ensuring that logic gate delay remains approximately constant across all manufacturing conditions), and temperature. For clarity, a “slow” process corner is one in which transistor parameters including, but not limited to, gate length, threshold voltage, and gate oxide thickness are shifted to cause the transistor to operate more slowly than a “typical” transistors. Similarly, a “fast” process corner is one in which transistor parameters are shifted to cause the transistor to operate faster than “typical” transistors.

The temperature based voltage options may include tuning voltage higher at low temperatures for sub-threshold and near-threshold circuits and higher at high temperatures for super-threshold circuits. In conventional circuits, a transistor is operated in either an “off” state or an “on” state. A transistor can transition from the “off” state to the “on” state by applying a voltage across its gate and source terminals that exceeds a value known as the threshold voltage. Conventional circuits typically operate in a super-threshold region with a supply voltage (i.e., VDD) much higher than this threshold voltage to ensure robust operation and that the transistor operates like an ideal “switch.” However, it has been shown that a transistor still exhibits switch-like behavior if the supply voltage is only slightly above the threshold voltage (near-threshold operation) or below the threshold voltage (sub-threshold operation).

The voltage options delivered through the voltage rails are calibrated during a manufacturing test phase. Each memory module320and process control monitors (e.g., PCM250inFIG.2) therein are observed to determine the correct voltage option and corresponding voltage selection signal for each of the memory blocks3201,3202,3203, . . . ,320n, in the memory module320. This is achieved by applying an initial low voltage option to each of the memory blocks3201,3202,3203, . . . ,320n, then observing whether the memory block remains functional. In the case of calibrating a retention voltage, the memory block is placed in deep sleep mode at the initial low voltage for data retention, returned to active mode at a higher safe operating voltage, and then measured to determine whether any bitcells therein are corrupted in the process. In the case of calibrating a functional voltage, the memory block is operated (e.g., read or written) at the initial low voltage, returned to a higher safe operating voltage, and then measured to determine whether any bitcells therein are corrupted in the process. If bitcells in the memory block are corrupted (resulting in a “bad” memory block), a voltage option higher than the initial voltage option is applied, and if bitcells in the memory block are not corrupted (resulting in a “good” memory block), then a lower than the initial voltage option is applied. Thus, an iterative process is used to determine a first known working voltage option at which the bitcells do not get corrupted. Finally, the voltage options deliverable through the voltage rails are determined as the ones having some margin over the first known working voltage options for each of the memory blocks.

The plurality of multiplexors3401,3402,3403, . . . ,340nmay be located within each of the memory blocks3201,3202,3203, . . . ,320n, outside the memory blocks but within the memory module320, or within the voltage generation module310. Each of the plurality of multiplexors3401,3402,3403, . . . ,340nis an independently-controllable electronic device configured to select one or more voltage rails received as input and provide a single output corresponding to the selected voltage rail. Each of the plurality of multiplexors3401,3402,3403, . . . ,340nis configured to switch between the two or more voltage rails based on an operational parameter of each of the memory blocks3201,3202,3203, . . . ,320n. The operational parameter may be a manufacturing process corner of the memory block, a read or write delay, a minimum operating voltage, storage status of the memory block, an operating mode of the memory block, a temperature of the memory block, and the like. In some embodiments, the operating mode of each memory block could be a power mode such as an active mode, a standby mode, and a deep sleep mode. The active mode corresponds to a state where the low power microcontroller system100is fully operational. The standby mode corresponds to a state where the low power microcontroller system100is in a short period of inactivity, can be intermittently awakened by a sudden activity, and the memory module stores data in a low power or retention mode. The deep sleep mode corresponds to a state where the low power microcontroller system100is in a long period of inactivity, and the memory module stores data in a retention mode.

Instead of having a centralized voltage generation module generating multiple rails, a single voltage (or small number of voltages) may be generated that are then distributed to a number of local voltage regulators that serve a single memory block (or a small number of memory blocks). The local voltage regulator can be configured to provide a unique voltage for its own memory block. So instead of providing a selection signal to a local multiplexor, a tuning signal to is provided to the local voltage regulator for a single or multiple memory blocks.

In some embodiments, each of the plurality of multiplexors3401,3402,3403, . . .340nis configured and/or programmed to select the voltage options from the voltage rails. Additionally, or alternatively, the system300may include a voltage selection module330configured and/or programmed to select the voltage options from the voltage rails. The voltage selection module330is electrically connected to each of the plurality of multiplexors3401,3402,3403, . . . ,340n. The voltage selection module330may be implemented as a hardware or a software. When implemented as hardware, the voltage selection module330selects voltage options from the voltage rails based on data that may be stored in a memory device350in the voltage selection module330, in a separate dedicated memory module, or in each of the memory blocks3201,3202,3203, . . . ,320n. The selected voltage options may be set once during a manufacturing test phase (i.e., they are set statically). The selected voltage options may also be periodically updated based on the operational parameter thereof (i.e., the voltage options are dynamically adjusted based on such data). The memory device used to store voltage selection options may be any suitable memory such as an SRAM, a NVM, a set of registers, or the like. When implemented as software, the voltage selection module330performs the steps of the method500described below.

Whether implemented as hardware or as software, the voltage selection module330selects a voltage rail based on the operational parameter of each of the memory blocks3201,3202,3203, . . . ,320n, such that a voltage required to retain or operate on data therein is minimized, resulting in reduced power consumption during active mode, standby mode, and/or deep sleep mode. The voltage selection module330then generates an independent voltage selection signal based on the selected voltage rail. This voltage selection signal is then transmitted to the corresponding one of the plurality of multiplexors3401,3402,3403, . . . ,340n, which turns on and electrically connects the selected voltage rail to the corresponding one of the memory blocks3201,3202,3203, . . . ,320n, for which the voltage rail was selected. The voltage selection signals are generally a function of process corner, temperature, operating mode (e.g., an active mode, a standby node, a deep sleep mode), etc.

Referring toFIG.4, a schematic block diagram of a system400including a memory module420with fine-grained voltage adjustment capabilities, is shown. In some embodiments, the memory module420may be the SRAM170, the cache128, or the tightly coupled memory TCM126(FIG.1). The system400represents a different embodiment than the system300. The memory module420includes four groups of memory blocks-(i) a first group having two memory blocks42011,42012, (ii) a second group having four memory blocks42021,42022,42023,42024, (iii) a third group having four memory blocks42031,42032,42033,42034, and (iv) a fourth group having eight memory blocks42041,42042,42043,42044,42045,42046,42047,42048. The first group of memory blocks42011,42012is electrically connected to a multiplexor4401, which receives five voltage rails from a voltage generation module410. The second group of memory blocks42021,42022,42023,42024is electrically connected to a multiplexor4402, which receives three voltage rails from the voltage generation module410. The third group of memory blocks42031,42032,42033,42034is electrically connected to a multiplexor4403, which receives four voltage rails from the voltage generation module410. The fourth group of memory blocks42041,42042,42043,42044,42045,42046,42047,42048is electrically connected to a multiplexor4404, which receives two voltage rails from the voltage generation module410. As demonstrated by the example ofFIG.4, any number of memory blocks can be electrically connected to a single multiplexor.

The memory module420includes a means for measuring temperature such that the applied voltage can be adjusted based on the temperature of the entire memory module420. In some embodiments, such as in the example embodiments ofFIG.4, this can be accomplished by a single temperature sensor425disposed in the memory module420. The temperature sensor425measures temperature via closed-loop hardware or alternatively, via software. In other embodiments, the temperature of the memory module420can be accomplished by a temperature-sensitive analog circuit425disposed in the memory module420. An example of the temperature-sensitive analog circuit425is a voltage generator that has been designed to have a tunable complementary-to-absolute temperature (CTAT) characteristic, and thus a known temperature coefficient, such that voltage varies inversely proportional to the measured temperature. The measured temperature is used for dynamically adjusting the voltage delivered to the memory blocks in the memory module420. This type of dynamic adjustment of voltage is especially useful when the applied voltage is in the near-threshold or sub-threshold range. Circuits operating in near-threshold or sub-threshold range are highly sensitive to temperature, and dynamic adjustment of the voltage can compensate for this sensitivity.

The system400includes a voltage generation module410, which is the same or substantially similar to the voltage generation module310. In some embodiments of the low power microcontroller system100, the voltage generation module410may be the SIMO buck converter210(FIG.2), which is the main voltage source of the microcontroller system100and ensures maximum power efficiency. In other embodiments, the voltage generation module410may be a voltage regulator such as, but not limited to, a low dropout regulator (LDO) or another step-down voltage regulator that is located proximal to the memory module420.

As illustrated byFIG.4, more than two voltage rails may be connected between the voltage generation module410and the multiplexors4401,4402,4403,4404. The number of voltage rails for each of the multiplexors4401,4402,4403,4404may also be unequal. The voltage generation module410supplies voltage through five, three, four, and two voltage rails, by electrical connection, to the multiplexors4401,4402,4403,4404respectively.

Further, the number of memory blocks receiving voltage connection from the multiplexors4401,4402,4403,4404may be equal to, greater than or lesser than the number of voltage rails connecting to the multiplexors4401,4402,4403,4404. For example, the multiplexor4403electrically connects four voltage rails to four memory blocks42031,42032,42033,42034; the multiplexor4402electrically connects three voltage rails to four memory blocks42021,42022,42023,42024; the multiplexor4404electrically connects two voltage rails to two sets of four memory blocks in series42041,42042,42043,42044,42045,42046,42047,42049; and the multiplexor4401electrically connects five voltage rails to two memory blocks42011,42012. The multiplexors4401,4402,4403,4404are same as or substantially similar to the multiplexors3401,3402,3403, . . . ,340n, described above with respect toFIG.3.

As described above with respect toFIG.3, each of the voltage rails in provide a different voltage option, preset or customizable, to the memory blocks connected through the corresponding multiplexor. Further, each of the voltage rails may deliver a sub-threshold, near-threshold, or super-threshold voltage. In some embodiments, the voltage options for each of the memory blocks42011,42012,42021,42022,42023,42024,42031,42032,42033,42034,42041,42042,42043,42044,42045,42046,42047,42049may be standard or unique. Further, in some embodiments, the voltage rails may provide a same or a different voltage to each of the memory blocks42011,42012,42021,42022,42023,42024,42031,42032,42033,42034,42041,42042,42043,42044,42045,42046,42047,42049, or across different memory modules420.

In the example embodiment ofFIG.4, the multiplexors4401,4402,4403,4404are located within the memory module420and outside the memory blocks. Alternatively, the multiplexors4401,4402,4403,4404may be located within the voltage generation module410. Each of the multiplexors4401,4402,4403,4404is configured to switch between the voltage rails based on an operational parameter of each of the four groups having the memory blocks42011,42012,42021,42022,42023,42024,42031,42032,42033,42034,42041,42042,42043,42044,42045,42046,42047,42048The operational parameter may be a manufacturing process corner of the memory block, a minimum operating voltage, storage status of the memory block, an operating mode of the memory block, a temperature of the memory block, and the like. In some embodiments, the operating mode of each memory block could be a power mode such as an active mode, a functional deep sleep mode, and a baseline deep sleep mode.

In some embodiments, each of the multiplexors4401,4402,4403,4404is configured and/or programmed via selection signal to select the voltage options from the voltage rails. Additionally, or alternatively, the system400may include a voltage selection module430configured and/or programmed to select the voltage options from the voltage rails. The voltage selection module430is electrically connected to each of the multiplexors4401,4402,4403,4404. The voltage selection module430is same or substantially similar to the voltage selection module330, and may be implemented as a hardware or a software. Similar to the system300, a separate memory such as registers may be used to store voltage options for each of the memory blocks for the selection signals to each of the multiplexors4401,4402,4403,4404.

FIG.5is a block diagram of a method500of providing fine-grained voltage adjustment to a memory module such as one of the memory modules inFIGS.3-4. The method500is representative of example machine-readable instructions for providing the voltage adjustment based on workload of the memory module. In this example, the machine readable instructions comprise an algorithm for execution by: (i) a processor; (ii) a controller; and/or (iii) one or more other suitable processing device(s). The algorithm may be embodied in software stored on tangible non-transitory computer-readable media such as flash memory, CD-ROM, floppy disk, hard drive, digital video (versatile) disk (DVD), or other memory devices. However, persons of ordinary skill in the art will readily appreciate that the entire algorithm and/or parts thereof can alternatively be executed by a device other than a processor and/or embodied in firmware or dedicated hardware in a well-known manner (e.g., it may be implemented by an application specific integrated circuit [ASIC], a programmable logic device [PLD], a field programmable logic device [FPLD], a field programmable gate array [FPGA], discrete logic, etc.). For example, any or all of the components of the interfaces can be implemented by software, hardware, and/or firmware. Also, some or all of the machine readable instructions represented by the block diagram ofFIG.5may be implemented manually. Further, although the example algorithm is described with reference to the block diagram illustrated inFIG.5, persons of ordinary skill in the art will readily appreciate that many other methods of implementing the example machine readable instructions may alternatively be used. For example, the order of execution of the blocks may be changed, and/or some of the blocks described may be changed, eliminated, or combined.

In some embodiments, the method500may be performed by a voltage selection module that is implemented using hardware or software. Example voltage selection modules330,430are described above, with respect toFIG.3andFIG.4, respectively.

The method500begins in step510where an operational parameter of an individual memory block within a memory module is determined. The memory module includes a plurality of the memory blocks. The operational parameter may be a manufacturing process corner of the memory block, a minimum operating voltage, storage status of the memory block, an operating mode of the memory block, a temperature of the memory block, and the like. In some embodiments, the operating mode is a power mode such as an active mode, a functional deep sleep mode, and a baseline deep sleep mode, as noted above.

In step520, one of a plurality of voltage rails is selected by a voltage generation module based on the operational parameter. This ensures that a voltage required to retain data in the individual memory block of the memory module is minimized. In some embodiments, the voltage generation module may be a buck converter or a SIMO buck converter that is a central voltage source, as described above. Alternatively, the voltage generation module may be a voltage regulator such as, but not limited to, a low dropout regulator (LDO) or another step-down voltage regulator located proximal to the memory module.

In step530, a voltage selection signal is generated based on the selected voltage rail. The voltage selection signal is independent for each individual memory block. The voltage selection signal is subsequently transmitted to a multiplexor to electrically connect the individual memory block to the selected voltage rail. The selected voltage rail delivers a voltage which may be sub-threshold, near-threshold, or super-threshold. In some embodiments, the voltage rails may deliver a same or a different voltage to each of the memory blocks, or across different memory modules.

Advantageously, the systems and methods according to the present disclosure provide for fine-grained voltage adjustment capabilities of a memory module in a low power microcontroller system. Customized voltage options supplied to individual memory blocks in the memory module helps minimize power consumption of the memory module during active and deep sleep modes, without compromising the data stored in the memory module.

As used in this application, the terms “component,” “module,” “system,” or the like, generally refer to a computer-related entity, either hardware (e.g., a circuit), a combination of hardware and software, software, or an entity related to an operational machine with one or more specific functionalities. For example, a component may be, but is not limited to being, a process running on a processor (e.g., digital signal processor), a processor, an object, an executable, a thread of execution, a program, and/or a computer. By way of illustration, both an application running on a controller, as well as the controller, can be a component. One or more components may reside within a process and/or thread of execution, and a component may be localized on one computer and/or distributed between two or more computers. Further, a “device” can come in the form of specially designed hardware, generalized hardware made specialized by the execution of software thereon that enables the hardware to perform specific function, software stored on a computer-readable medium, or a combination thereof.

The terminology used herein is for the purpose of describing particular embodiments only, and is not intended to be limiting of the invention. As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. Furthermore, to the extent that the terms “including,” “includes,” “having,” “has,” “with,” or variants thereof, are used in either the detailed description and/or the claims, such terms are intended to be inclusive in a manner similar to the term “comprising.”

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art. Furthermore, terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art, and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

While various embodiments of the present invention have been described above, it should be understood that they have been presented by way of example only, and not limitation. Although the invention has been illustrated and described with respect to one or more implementations, equivalent alterations and modifications will occur or be known to others skilled in the art upon the reading and understanding of this specification and the annexed drawings. In addition, while a particular feature of the invention may have been disclosed with respect to only one of several implementations, such feature may be combined with one or more other features of the other implementations as may be desired and advantageous for any given or particular application. Thus, the breadth and scope of the present invention should not be limited by any of the above described embodiments. Rather, the scope of the invention should be defined in accordance with the following claims and their equivalents.