Patent ID: 12211833

DETAILED DESCRIPTION

The present invention has been particularly shown and described with respect to certain embodiments and specific features thereof. The embodiments set forth herein below are to be taken as illustrative rather than limiting. It should be readily apparent to those of ordinary skill in the art that various changes and modifications in form and detail may be made without departing from the spirit and scope of the present invention.

Before the further description of the preferred embodiment, the specific terms used throughout the text will be described below.

The terms “on,” “above,” and “over” used herein should be interpreted in the broadest manner such that “on” not only means “directly on” something but also includes the meaning of “on” something with an intermediate feature or a layer therebetween, and that “above” or “over” not only means the meaning of “above” or “over” something but can also include the meaning it is “above” or “over” something with no intermediate feature or layer therebetween (i.e., directly on something).

The ordinal numbers, such as “first”, “second”, etc., used in the description and the claims are used to modify the elements in the claims and do not themselves imply and represent that the claim has any previous ordinal number, do not represent the sequence of some claimed element and another claimed element, and do not represent the sequence of the manufacturing methods, unless an addition description is accompanied. The use of these ordinal numbers is only used to make a claimed element with a certain name clear from another claimed element with the same name.

The term “forming” or the term “disposing” are used hereinafter to describe the behavior of applying a layer of material to the substrate. Such terms are intended to describe any possible layer forming techniques including, but not limited to, thermal growth, sputtering, evaporation, chemical vapor deposition, epitaxial growth, electroplating, and the like.

Please refer toFIG.1,FIG.2A, andFIG.2B.FIG.1is a schematic drawing illustrating an electrostatic discharge protection structure101according to a first embodiment of the present invention,FIG.2Ais a schematic equivalent circuit diagram of an electrostatic discharge protection structure according to an embodiment of the present invention, andFIG.2Bis a schematic equivalent circuit diagram of an electrostatic discharge protection structure according to another embodiment of the present invention. As shown inFIG.1, the electrostatic discharge protection structure101includes a semiconductor substrate10, a gate structure50, a first well region12of a first conductivity type, a first doped region22of the first conductivity type, a second doped region24of a second conductivity type, a third doped region32of the first conductivity type, and a fourth doped region34of the second conductivity type. The gate structure50is disposed on the semiconductor substrate10. The first well region12is disposed in the semiconductor substrate10. The first doped region22is disposed in the first well region12. The second doped region24is disposed in the first well region12. The second doped region24is connected with the first doped region22, and the second doped region24is an emitter of a first bipolar junction transistor (BJT). The third doped region32is disposed in the semiconductor substrate10. The fourth doped region34is disposed in the semiconductor substrate10. The third doped region32and the second doped region24are located at two opposite sides of the gate structure50in a first horizontal direction D1. The fourth doped region34is connected with the third doped region32, and the third doped region32is an emitter of a second bipolar junction transistor. The area occupied by the emitter may be reduced by the doped region of the conductivity type different from that of the doped region used as the emitter of the bipolar junction transistor and connected with the doped region used as the emitter of the bipolar junction transistor. Therefore, the emitter injection efficiency of the corresponding bipolar junction transistor may be lowered, and the holding voltage and/or other related electrical performance of the electrostatic discharge protection structure may be enhanced accordingly.

In the present invention, the first conductivity type is complementary to the second conductivity type. The second conductivity type may be N type when the first conductivity type is P type, and the second conductivity type may be P type when the first conductivity type is N type. For example, when the first conductivity type is P type and the second conductivity type is N type, the second doped region24may be an emitter of an NPN BJT, and the third doped region32may be an emitter of a PNP BJT. Comparatively, when the first conductivity type is N type and the second conductivity type is P type, the second doped region24may be an emitter of a PNP BJT, and the third doped region32may be an emitter of an NPN BJT, but not limited thereto. In some embodiments, the doped regions and the well regions may be formed by performing suitable doping processes (such as implantation processes or other doping approaches) to the semiconductor substrate10. For example, some regions of the semiconductor substrate10may be doped with N type dopants for forming N type doped regions or N type well regions, or some regions of the semiconductor substrate10may be doped with P type dopants for forming P type doped regions or P type well regions. The N type dopants described above may include phosphorus (P), arsenic (As), or other suitable N-type dopant materials, and the P type dopants described above may include boron (B), gallium (Ga), or other suitable P type dopant materials.

Specifically, in some embodiments, a vertical direction D3 may be regarded as a thickness direction of the semiconductor substrate10, and the semiconductor substrate10may have a top surface and a bottom surface opposite to the top surface in the vertical direction D3. The gate structure50described above may be disposed on the top surface of the semiconductor substrate10, and the first doped region22, the second doped region24, the third doped region32, and the fourth doped region34may be located at a side relatively adjacent to the top surface. Additionally, in some embodiments, the horizontal directions (such as the first horizontal direction D1 and the second horizontal direction D2 orthogonal to the first horizontal direction D1) may be substantially orthogonal to the vertical direction D3, and the horizontal directions may be parallel with the top surface and/or the bottom surface of the semiconductor substrate10, but not limited thereto. In this description, a distance between the bottom surface of the semiconductor substrate10and a relatively higher location and/or a relatively higher part in the vertical direction D3 is greater than a distance between the bottom surface of the semiconductor substrate10and a relatively lower location and/or a relatively lower part in the vertical direction D3. The bottom or a lower portion of each component may be closer to the bottom surface of the semiconductor substrate10in the vertical direction D3 than the top or upper portion of this component. Another component disposed above a specific component may be regarded as being relatively far from the bottom surface of the semiconductor substrate10in the vertical direction D3, and another component disposed under a specific component may be regarded as being relatively closer to the bottom surface of the semiconductor substrate10in the vertical direction D3.

In some embodiments, the second doped region24may directly contact the first doped region22, and the fourth doped region34may directly contact the third doped region32. Additionally, a part of the second doped region24may be located between the first doped region22and the gate structure50in the first horizontal direction D1, and a part of the fourth doped region34may be located between the third doped region32and the gate structure50in the first horizontal direction D1. In some embodiments, the second doped region24may surround the first doped region22in the first horizontal direction D1 and/or in the second horizontal direction D2, and the fourth doped region34may surround the third doped region32in the first horizontal direction D1 and/or in the second horizontal direction D2, but not limited thereto.

In some embodiments, the electrostatic discharge protection structure101may further include a second well region14of the second conductivity type and a third well region16of the second conductivity type, and the second well region14and the third well region16may be disposed in the first well region12. In some embodiments, the third doped region32and the fourth doped region34may be located above the second well region14in the vertical direction D3, and the third well region16may be partly located between the third doped region32and the second well region14in the vertical direction D3 and partly located between the fourth doped region34and the second well region14in the vertical direction D3. In some embodiments, a dopant concentration in the third well region16may be lower than a dopant concentration in the fourth doped region34and higher than a dopant concentration in the second well region14, and the dopant concentration in the third well region16may vary with gradient in a specific direction (such as in the vertical direction D3, but not limited thereto), but not limited thereto. In some embodiments, the second well region24, the first well region12, and the second doped region14(or the second well region14and the third well region16) may form the first bipolar junction transistor described above, and the third doped region32, the second well region14(or the second well region14and the third well region16) and the first well region12may form the second bipolar junction transistor described above, but not limited thereto.

In some embodiments, the gate structure50may include a gate dielectric layer52and a gate electrode54disposed on the gate dielectric layer52. The gate dielectric layer52may include gate oxide, high dielectric constant (high-k) dielectric materials, or other suitable dielectric materials, and the gate electrode54may include non-metallic electrically conductive materials (such as doped polysilicon) or metallic electrically conductive materials, but not limited thereto. In some embodiments, the gate structure50, the second doped region24, the fourth doped region34, and the first well region12may form a metal oxide semiconductor (MOS) structure, and the first bipolar junction transistor and the second bipolar junction transistor described above may be regarded as parasite bipolar junction transistors in this MOS structure, but not limited thereto. For example, when the first conductivity type is P type and the second conductivity type is N type, the MOS structure described above may be an NMOS structure, and the MOS structure described above may be a PMOS structure when the first conductivity type is N type and the second conductivity type is P type, but not limited thereto. Additionally, in some embodiments, the second doped region24may be electrically connected to a first electrode92, and the fourth doped region34may be electrically connected to a second electrode94. For example, the second doped region24may be electrically connected to the first electrode92via one or a plurality of contact structure CT2 disposed on the second doped region24, and the fourth doped region34may be electrically connected to the second electrode94via one or a plurality of contact structure CT4 disposed on the fourth doped region34. It is worth noting that the third doped region32is not electrically connected to the second electrode94directly as there is not any contact structure disposed on the third doped region32, a diode (such as a reverse diode) may be formed between the third doped region32and the fourth doped region34, and the diode may be electrically connected to the second bipolar junction transistor described above. The diode may be used to further enhance the holding voltage and/or other related electrical performance of the electrostatic discharge protection structure, but not limited thereto.

In some embodiments, the first doped region22may be electrically connected to the first electrode92via one or a plurality of contact structures CT1 disposed on the first doped region22, and the gate structure50may be electrically connected to the first electrode92via one or a plurality of contact structures CT5 disposed on the gate structure50, but not limited thereto. In addition, each contact structure may include a low resistivity material (such as copper, aluminum, tungsten, and so forth) and a barrier layer (such as titanium nitride, tantalum nitride, or other suitable electrically conductive barrier materials) surrounding the low resistivity material, but not limited thereto. As shown inFIG.1andFIG.2A, in some embodiments, a diode RD may be formed between the third doped region32and the fourth doped region34. Two terminals of the diode RD may be electrically connected to the second electrode94and the second bipolar junction transistor T2, respectively, and the emitter E1 of the first bipolar junction transistor T1 may be electrically connected to the first electrode92. In some embodiments, the second doped region24may be regarded as the emitter E1 of the first bipolar junction transistor T1, the first well region12may be regarded as the base B1 of the first bipolar junction transistor T1, and the second well region14and/or the third well region16may be regarded as the collector C1 of the first bipolar junction transistor T1. Additionally, the third doped region32may be regarded as the emitter E2 of the second bipolar junction transistor T2, the second well region14and/or the third well region16may be regarded as the base B2 of the second bipolar junction transistor T2, and the first well region12may be regarded as the collector C2 of the second bipolar junction transistor T2. Therefore, the base B1 of the first bipolar junction transistor T1 may be electrically connected with the collector C2 of the second bipolar junction transistor T2, and the collector C1 of the first bipolar junction transistor T1 may be electrically connected with the base B2 of the second bipolar junction transistor T2. Additionally, the resistance R1 illustrated inFIG.2Amay be regarded as a resistance of the first well region12, and the resistance R2 illustrated inFIG.2Amay be regarded as a resistance of the second well region14and/or the third well region16, but not limited thereto.

As shown inFIG.1andFIG.2A, in some embodiments, the first conductivity type may be P type and the second conductivity type may be N type. Under this situation, the first bipolar junction transistor T1 may be an NPN BJT, the second bipolar junction transistor T2 may be a PNP BJT, the first electrode92may be a cathode, and the second electrode94may be an anode. Comparatively, as shown inFIG.1andFIG.2B, in some embodiments, the first conductivity type may be N type and the second conductivity type may be P type. Under this situation, the first bipolar junction transistor T1 may be a PNP BJT, the second bipolar junction transistor T2 may be an NPN BJT, the first electrode92may be an anode, and the second electrode94may be a cathode.

As shown inFIG.1, in some embodiments, the electrostatic discharge protection structure101may further include an isolation structure40and a doped region26of the first conductivity type. The doped region26may be disposed in the semiconductor substrate10, and at least a part of the isolation structure40may be disposed in the semiconductor substrate10and located between the second doped region24and the doped region26. In some embodiments, the isolation structure40may include a field oxide layer, trench isolation, or other suitable insulating isolation structures, and the doped region26may be electrically connected to the first electrode92via one or a plurality of contact structures CT3 disposed on the doped region26, but not limited thereto.

Please refer toFIG.1andFIG.3.FIG.3is a schematic drawing illustrating a top view of an electrostatic discharge protection structure according to an embodiment of the present invention. In some embodiments,FIG.1may be regarded as a cross-sectional schematic diagram of an area in the electrostatic discharge protection structure illustrated inFIG.3, but not limited thereto. As shown inFIG.1andFIG.3, in some embodiments, the electrostatic discharge protection structure101may include a plurality of the gate structures50, a plurality of the first doped regions22, a plurality of the second doped regions24, and a plurality of the third doped regions32. Each of the gate structures50may extend in the second horizontal direction D2, the third doped regions32and the fourth doped region34may be located between two gate structures50, and two first doped regions22and two second doped regions24may be located at the relative outer sides of the two gate structures50in the first horizontal direction D1. In some embodiments, the structure illustrated inFIG.3may be regarded as a structure including two MOS structures sharing one fourth doped region34, but not limited thereto. In some embodiments, each of the first doped regions22and each of the third doped regions32may extend in the second horizontal direction D2, respectively, and each of the third doped regions32may be located between the corresponding gate structure50and the contact structure CT4 in the first horizontal direction D1, but not limited thereto. Additionally, the isolation structure40may surround the second doped regions24and the fourth doped region34, and the isolation structure40may be disposed between the doped region26and the second doped region24and disposed between the doped region26and the fourth doped region34. It is worth noting that the layout design of the electrostatic discharge protection structure101is not limited to the condition shown inFIG.3and may be further modified according to some design considerations.

The following description will detail the different embodiments of the present invention. To simplify the description, identical components in each of the following embodiments are marked with identical symbols. For making it easier to understand the differences between the embodiments, the following description will detail the dissimilarities among different embodiments and the identical features will not be redundantly described.

Please refer toFIG.4.FIG.4is a schematic drawing illustrating a top view of an electrostatic discharge protection structure102according to a second embodiment of the present invention. As shown inFIG.4, in some embodiments, each of the first doped regions22may include a first portion22A and a plurality of second portions22B. Each of the second portions22B is directly connected with the first portion22A, each of the second portions22B is located between the first portion22A and the fourth doped region34in the first horizontal direction D1, and the second portions22B are repeatedly arranged in the second horizontal direction D2. In some embodiments, the first portion22A may extend in the second horizontal direction D2, and each of the second portions22B may be regarded as a protruding portion extending towards the gate structure50in the first horizontal direction D1, but not limited thereto. Additionally, the second doped region24disposed between the first portion22A and the gate structure50in the first horizontal direction D1 may include a plurality of first sub portions24P. Each of the first sub portions24P may be located between the first portion22A and the fourth doped region34in the first horizontal direction D1, and the first sub portions24P and the second portions22B may be alternately arranged in the second horizontal direction D2. Additionally, the third doped region32may include a plurality of second sub portions32P arranged in the second horizontal direction D2 and separated from one another, and each of the second sub portions32P may be disposed corresponding to and substantially aligned with one of the first sub portions24P in the first horizontal direction D1.

By the allocation described above, the area occupied by the second doped region24at the anode terminal or the cathode terminal may be relatively reduced (compared with the electrostatic discharge protection structure in the first embodiment described above, such as the condition illustrated inFIG.3) in the electrostatic discharge protection structure102of this embodiment by the disposition of the second portions22B of the first doped region22, and the emitter injection efficiency of the bipolar junction transistor corresponding to the second doped region24may be further lowered accordingly. In addition, the third doped region32may be divided into the second sub portions32P separated from one another for being located corresponding to the first sub portions24P separated from one another in the first horizontal direction D1. Therefore, the area occupied by the third doped region32at the anode terminal or the cathode terminal may be relatively reduced, and the emitter injection efficiency of the bipolar junction transistor corresponding to the third doped region32may be further lowered accordingly. In other words, by the disposition approach described above, the emitter injection efficiency of the parasite bipolar junction transistor in the electrostatic discharge protection structure102may be lowered, and the holding voltage and/or other related electrical performance of the electrostatic discharge protection structure may be enhanced. In some embodiments, an area of each of the second portions22B in the vertical direction Z may be greater than or equal to an area of each of the first sub portions24P in the vertical direction Z, but not limited thereto. For example, in some embodiments, the area of each of the second portions22B in the vertical direction Z may be substantially equal to the area of each of the first sub portions24P in the vertical direction Z, and the length of each of the second sub portions32P in the second horizontal direction D2, the length of each of the first sub portions24P in the second horizontal direction D2, and the length of each of the second portions22B in the second horizontal direction D2 may be substantially equal to one another, but not limited thereto. Additionally, in some embodiments, the corresponding contact structure CT1 and the corresponding contact structure CT2 may be disposed on each of the second portions22B and each of the first sub portions24P, respectively, and there is not any contact structure disposed on and directly contacting the second sub portions32P, but not limited thereto.

Please refer toFIG.5andFIG.6.FIG.5is a schematic drawing illustrating a top view of an electrostatic discharge protection structure103according to a third embodiment of the present invention, andFIG.6is a schematic drawing illustrating a top view of an electrostatic discharge protection structure104according to a fourth embodiment of the present invention. As shown inFIG.5andFIG.6, in some embodiments, the area of each of the second portions22B in the vertical direction D3 may be greater than the area of each of the first sub portions24P in the vertical direction D3 for further reducing the area occupied by the second doped region24and further lowering the emitter injection efficiency of the bipolar junction transistor corresponding to the second doped region24. In addition, because the area of the second portions22B is increased, the spacing between the second sub portions32P disposed corresponding to the first sub portions24P may be increased accordingly, and the area occupied by the third doped region32may be further reduced for lowering the emitter injection efficiency of the bipolar junction transistor corresponding to the third doped region32. For example, in some embodiments, the length of each of the second portions22B in the second horizontal direction D2 may be substantially twice the length of each of the first sub portions24P in the second horizontal direction D2 (such as the condition shown inFIG.5), the length of each of the second portions22B in the second horizontal direction D2 may be substantially triple the length of each of the first sub portions24P in the second horizontal direction D2 (such as the condition shown inFIG.6), or other suitable proportion of the length of each of the second portions22B to the length of each of the first sub portions24P may be applied, and the length of each of the second sub portions32P in the second horizontal direction D2 may be substantially equal to the length of each of the first sub portions24P in the second horizontal direction D2, but not limited thereto. Additionally, it is worth noting that the first portion22A and the second portions22B of the first doped region22, the first sub portions24P of the second doped region24, and/or the second sub portions32P of the third doped region32illustrated inFIGS.4-6described above may also be applied in other embodiments of the present inventions according to some design considerations.

Please refer toFIG.7andFIG.1.FIG.7is a schematic drawing illustrating an electrostatic discharge protection structure105according to a fifth embodiment of the present invention. As shown inFIG.7, the third well region16described above may be disposed in the electrostatic discharge protection structure105without the second well region in the first embodiment described above (such as the second well region14illustrated inFIG.1). In the electrostatic discharge protection structure105, the second doped region24, the first well region12, and the third well region16may form the first bipolar junction transistor described above, and the third doped region32, the third well region16, and the first well region12may form the second bipolar junction transistor described above, but not limited thereto. It is worth noting that the design where the third well region16is disposed in the electrostatic discharge protection structure without disposing the second well region as shown inFIG.7may also be applied in other embodiments of the present inventions according to some considerations.

Please refer toFIG.8andFIG.1.FIG.8is a schematic drawing illustrating an electrostatic discharge protection structure106according to a sixth embodiment of the present invention. As shown inFIG.8, the second well region14described above may be disposed in the electrostatic discharge protection structure106without the third well region in the first embodiment described above (such as the third well region16illustrated inFIG.1). In the electrostatic discharge protection structure106, the second doped region24, the first well region12, and the second well region14may form the first bipolar junction transistor described above, and the third doped region32, the second well region14, and the first well region12may form the second bipolar junction transistor described above, but not limited thereto. It is worth noting that the design ofFIG.8with the second well region14disposed in the electrostatic discharge protection structure and without the third well region may also be applied in other embodiments of the present inventions according to some considerations.

Please refer toFIG.9.FIG.9is a schematic drawing illustrating an electrostatic discharge protection structure107according to a seventh embodiment of the present invention. As shown inFIG.9, in some embodiments, the electrostatic discharge protection structure107may further include a fifth doped region28of the first conductivity type disposed in the first well region12, and the first doped region22and the second doped region24may be located above the fifth doped region28in the vertical direction D3. In some embodiments, the fifth doped region28may be regarded as an electrostatic discharge doped region for adjusting the breakdown voltage of the corresponding bipolar junction transistor and/or further lowering the emitter injection efficiency of the corresponding bipolar junction transistor. For instance, the dopant concentration and/or the depth of the fifth doped region28may be adjusted for achieving the effects described above, but not limited thereto. Additionally, the fifth doped region28may be regarded as a P type electrostatic discharge (PESD) doped region when the first conductivity type is P type, and the fifth doped region28may be regarded as an N type electrostatic discharge (NESD) doped region when the first conductivity type is N type, but not limited thereto. In some embodiments, the dopant concentration in the fifth doped region28may vary with gradient in a specific direction (such as in the vertical direction D3, but not limited thereto. It is worth noting that the fifth doped region28illustrated inFIG.9may also be applied in other embodiments of the present inventions according to some design considerations.

Please refer toFIG.10.FIG.10is a schematic drawing illustrating an electrostatic discharge protection structure108according to an eighth embodiment of the present invention. As shown inFIG.10, in some embodiments, the fifth doped region28may be disposed under the second doped region24in the vertical direction D3, and the first doped region22may not be disposed above the fifth doped region28in the vertical direction D3. In other words, the dopant concentration of the fifth doped region28, the depth of the fifth doped region28, and the relative position relationship between the fifth doped region28and other doped regions may be adjusted according to some design considerations. For instance, the fifth doped region28may cover at least a part of the second doped region24in the vertical direction D3, or the e fifth doped region28may cover the first doped region22and the second doped region24in the vertical direction D3 (such as the condition illustrated inFIG.9), but not limited thereto.

Please refer toFIG.11.FIG.11is a schematic drawing illustrating an electrostatic discharge protection structure109according to a ninth embodiment of the present invention. As shown inFIG.11, in the electrostatic discharge protection structure109, the third doped region32may be electrically connected to the second electrode94via one or a plurality of contact structures CT6 disposed on the third doped region32, and the diode described above may not be formed between the third doped region32and the fourth doped region34when the fourth doped region34is electrically connected to the second electrode94via the contact structure CT4, but not limited thereto. It is worth noting that the design where the third doped region32and the fourth doped region34are electrically connected to the second electrode94via the contact structure CT6 and the contact structure CT4, respectively, as shown inFIG.11may also be applied in other embodiments of the present inventions according to some considerations.

Please refer toFIG.12.FIG.12is a schematic drawing illustrating an electrostatic discharge protection structure110according to a tenth embodiment of the present invention. As shown inFIG.12, in some embodiments, the electrostatic discharge protection structure110may further include a sixth doped region36of the first conductivity type disposed in the first well region12, and the third doped region32may be located above the sixth doped region36in the vertical direction D3. In some embodiments, the sixth doped region36may be regarded as an electrostatic discharge doped region for adjusting the breakdown voltage of the corresponding bipolar junction transistor and/or further lowering the emitter injection efficiency of the corresponding bipolar junction transistor. For instance, the dopant concentration and/or the depth of the sixth doped region36may be adjusted for achieving the effects described above, but not limited thereto. Additionally, the sixth doped region36may be regarded as a PESD doped region when the first conductivity type is P type, and the sixth doped region36may be regarded as an NESD doped region when the first conductivity type is N type, but not limited thereto. It is worth noting that the sixth doped region36illustrated inFIG.12may also be applied in other embodiments of the present inventions according to some design considerations.

Please refer toFIG.13.FIG.13is a schematic drawing illustrating an electrostatic discharge protection structure111according to an eleventh embodiment of the present invention. As shown inFIG.13, in some embodiments, the sixth doped region36may be disposed under the third doped region32and the fourth doped region34in the vertical direction D3. Therefore, the third doped region32and the fourth doped region34may be located above the sixth doped region36in the vertical direction D3. In other words, the dopant concentration of the sixth doped region36, the depth of the sixth doped region36, and the relative position relationship between the sixth doped region36and other doped regions may be adjusted according to some design considerations. For instance, the sixth doped region36may cover the third doped region32and the fourth doped region34in the vertical direction D3, or the sixth doped region36may only cover the third doped region32in the vertical direction D3 (such as the condition illustrated inFIG.12), but not limited thereto. In some embodiments, a diode may be formed between the sixth doped region36and the fourth doped region34, but not limited thereto.

Please refer toFIG.14.FIG.14is a schematic drawing illustrating an electrostatic discharge protection structure112according to a twelfth embodiment of the present invention. As shown inFIG.14, in some embodiments, the electrostatic discharge protection structure112may further include a seventh doped region38of the second conductivity type disposed in the first well region12, and the third doped region32may be located above the seventh doped region38in the vertical direction D3. In some embodiments, the seventh doped region38may be regarded as an electrostatic discharge doped region for adjusting the breakdown voltage of the corresponding bipolar junction transistor and/or further lowering the emitter injection efficiency of the corresponding bipolar junction transistor. For instance, the dopant concentration and/or the depth of the seventh doped region38may be adjusted for achieving the effects described above, but not limited thereto. Additionally, the seventh doped region38may be regarded as an NESD doped region when the second conductivity type is N type, and the seventh doped region38may be regarded as a PESD doped region when the second conductivity type is P type, but not limited thereto. In some embodiments, at least a part of the seventh doped region38may be disposed in the third well region16and/or the second well region14, but not limited thereto. It is worth noting that the seventh doped region38illustrated inFIG.14may also be applied in other embodiments of the present inventions according to some design considerations.

Please refer toFIG.15.FIG.15is a schematic drawing illustrating an electrostatic discharge protection structure113according to a thirteenth embodiment of the present invention. As shown inFIG.15, in some embodiments, the seventh doped region38described above may be disposed in the electrostatic discharge protection structure113without disposing the second well region and the third well region in the first embodiment described above (such as the second well region14and the third well region16illustrated inFIG.1). In the electrostatic discharge protection structure113, the second bipolar junction transistor described above may be formed with the third doped region32, the seventh doped region38, and the first well region12, but not limited thereto. It is worth noting that the design where the seventh doped region38is disposed in the electrostatic discharge protection structure without disposing the first well region and the second well region as shown inFIG.15may also be applied in other embodiments of the present inventions according to some considerations.

Please refer toFIG.16.FIG.16is a schematic drawing illustrating an electrostatic discharge protection structure114according to a fourteenth embodiment of the present invention. As shown inFIG.16, in some embodiments, the third doped region32and the fourth doped region34may be located above the seventh doped region38in the vertical direction D3, and the seventh doped region38may cover the third doped region32and the fourth doped region34in the vertical direction D3, but not limited thereto. It is worth noting that the design where the seventh doped region38covers the third doped region32and the fourth doped region34as shown inFIG.16may also be applied in other embodiments of the present inventions according to some considerations.

Please refer toFIG.17.FIG.17is a schematic drawing illustrating an electrostatic discharge protection structure115according to a fifteenth embodiment of the present invention. As shown inFIG.17, in some embodiments, the third doped region32may be located under the fourth doped region34in the vertical direction D3, the diode described above may be formed between the third doped region32and the fourth doped region34, and the diode may be regarded as a vertical parasitic reverse diode, but not limited thereto. In some embodiments, the second well region14may be located under the third doped region32and the fourth doped region34in the vertical direction D3. In some embodiments, the third well region described above may be disposed between the second well region14and the third doped region32and disposed between the second well region14and the fourth doped region34, or the second well region14inFIG.16may be replaced by the third well region. In addition, the first doped region22and the second doped region24may be located above the fifth doped region28in the vertical direction D3, and the fifth doped region28may cover the first doped region22and the second doped region24in the vertical direction D3, but not limited thereto. In some embodiments, the fifth doped region28may be disposed under the second doped region24in the vertical direction D3 only (such as the condition shown inFIG.10), but not limited thereto. It is worth noting that the design where the third doped region32is disposed under the fourth doped region34in the vertical direction D3 as shown inFIG.17may also be applied in other embodiments of the present inventions according to some considerations.

To summarize the above descriptions, according to the electrostatic discharge protection structure in the present invention, the doped regions of different conductivity types may be connected with doped regions used as the emitters of bipolar junction transistors for reducing the emitter injection efficiency and enhancing the holding voltage and/or other related electrical performance of the electrostatic discharge protection structure.

Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.