Patent ID: 12243839

DETAILED DESCRIPTION

To provide a better understanding of the present invention to those of ordinary skill in the art, several exemplary embodiments of the present invention will be detailed as follows, with reference to the accompanying drawings using numbered elements to elaborate the contents and effects to be achieved. The accompanying drawings are included to provide a further understanding of the embodiments, and are incorporated in and constitute a part of this specification. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. Other embodiments may be utilized and that structural, logical and electrical changes may be made without departing from the spirit and scope of the present invention.

It should be readily understood that the meaning of “on”, “above”, “over” and the like in the present disclosure should be interpreted in the broadest manner such that these terms not only means “directly on something” but also includes the meaning of “on something with an intermediate feature or a layer therebetween”.

Furthermore, spatially relative terms, such as “beneath”, “below”, “under’, “lower”, “above”, “upper”, “on”, “over” and the like may be used herein to describe one element or feature's spatial relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

FIG.1toFIG.5are schematic cross-sectional diagrams illustrating the steps of forming a bonded semiconductor structure according to a first embodiment of the present invention.FIG.6is a partial enlarged view of the bonded semiconductor structure shown inFIG.5. Please refer toFIG.1. A first device wafer100is provided. The first device wafer100includes a substrate110, an interconnection layer114disposed on the substrate110, and a first bonding structure layer121disposed on the interconnection layer114. The substrate110may be a silicon substrate, a silicon-on-insulator (SOI) substrate, a silicon germanium (SiGe) substrate, a III-V semiconductor substrate, or a substrate made of other suitable semiconductor materials. A plurality of semiconductor devises112may be formed in the substrate110. The semiconductor devises112may include transistors, diodes, capacitors, inductors, resistors, and/or any other types of active or passive electrical components, but are not limited thereto. The interconnection layer114includes multiple dielectric material layers and a plurality of conductive structures formed in the dielectric material layers. The dielectric material layers of the interconnection layer114may include silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbonitride (SiCN), nitride doped silicon carbide (NDC), low-k dielectric materials such as fluorinated silica glass (FSG), hydrogenated silicon oxycarbide (SiCOH), spin-on glass, porous low-k dielectric materials, organic polymer dielectric materials, or other suitable dielectric materials. The conductive structures of the interconnection layer114are made of metal materials, such as cobalt (Co), copper (Cu), aluminum (Al), tungsten (W), nickel (Ni), platinum (Pt), tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), a compound of the above materials, a composite layer or an alloy of the above materials, but are not limited thereto. For the sake of simplicity, only the conductive structures112in the topmost portion of the interconnection layer114are shown in the drawings of the present invention, while other detailed structures of the interconnection layer114are not shown. According to an embodiment of the present invention, the conductive structures112may include copper (Cu). In some embodiments, the interconnection layer114may further include circuit elements such as, but not limited to, capacitors, inductors, resistors, embedded memory, which are not shown for the sake of simplicity.

The first bonding structure layer121includes a first dielectric layer122, a first bonding layer124on the first dielectric layer122, and a plurality of first bonding pads126formed in the first bonding layer124and the first dielectric layer122. The top surfaces of the first bonding pads126are exposed from the first bonding layer124. The bottom surfaces of the first bonding pads126are in direct contact with the conductive structures112. The material of the first dielectric layer122may be selected from the materials for forming the dielectric material layers of the interconnection layer114, and will not be repeated herein for the sake of simplicity. According to an embodiment of the present invention, the first dielectric layer122may include silicon oxide (SiO2). The first bonding layer124may include a dielectric material that may form covalent bonding with another bonding layer of another device wafer through a wafer level bonding process, and may include silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), or silicon carbonitride (SiCN), but is not limited thereto. According to an embodiment of the present invention, the first bonding layer124includes silicon carbonitride (SiCN). The first bonding pad126may include any conductive metal that may be bonded to another bonding pad of another device wafer through a wafer level bonding process. According to an embodiment of the present invention, the first bonding pads126may include copper (Cu). The first bonding structure layer121may be formed through the following steps: successively forming the first dielectric layer122and the first bonding layer124on the interconnection layer114, performing a patterning process (such as a photolithography-etching process) to form a plurality of openings (not shown) through the first dielectric layer122and the first bonding layer124, depositing a metal layer (such as a copper layer) on the first bonding layer124to fill up the openings, and then performing a removal process (such as a chemical mechanical process) to remove the unnecessary portions of the metal layer outside the openings to obtain a first bonding pad126in each of the openings.

The shape of the opening may be controlled by adjusting process parameters of the etching process. According to an embodiment of the present invention, the opening may have a trapezoid cross-sectional shape, so that the first bonding pad126formed by filling metal in the opening may also have a trapezoid cross-sectional shape. According to an embodiment of the present invention, at this process stage, the first bonding pad126may have a thickness T1. The top surface of the first bonding pad126is approximately flush with the surface of the first bonding layer124.

Please refer toFIG.2. Subsequently, a removal process P1is performed on the first device wafer100to remove portions of the first bonding pads126, so that a recessed portion130having a depth DI (depth from the surface of the first bonding layer124) may be formed above each of the first bonding pads126. A top surface126aof the first bonding pad126lower than the surface of the first bonding layer124and a sidewall124sof the first bonding layer124are exposed from the recessed portion130. The removal process P1may be a wet etching process, a dry etching process, or a chemical mechanical polishing process that have etching selectivity between the materials of the first bonding pad126and the first bonding layer124. According to an embodiment of the present invention, the removal process P1may be a continuation of the chemical mechanical polishing process for forming the first bonding pads126(the chemical mechanical process to remove the unnecessary portions of the metal layer outside the openings). According to another embodiment of the present invention, removal process P1may be another chemical mechanical polishing process with increased etching selectivity between the materials of the first bonding pad126and the first bonding layer124. According to an embodiment of the present invention, a portion of the first bonding layer124may also be removed during the removal process P1, so that the angle of the sidewall124sof the first bonding pad124or the width of the recessed portion130after the removal process P1may be different from that before the removal process P1. According to an embodiment of the present invention, as shown inFIG.2, the angle A1between the sidewall124sof the first bonding layer124and the top surface126aof the first bonding pad126may be larger than 90 degrees. The width W1of the recessed portion130(the width of the recessed portion130near the surface of the first bonding layer124) may be slightly larger than the width of the top surface126aof the first bonding pad126. After the removal process P1, the first bonding layer124has a thickness T4, and the first bonding pad126has a thickness T2. The thickness T2is smaller than the thickness T1.

Please refer toFIG.3. A second device wafer200is provided. The second device wafer200includes a substrate210, an interconnection layer214disposed on the substrate210, and a second bonding structure layer221disposed on the interconnection layer214. A plurality of semiconductor devises212may be formed in the substrate210. The semiconductor devises212may include transistors, diodes, capacitors, inductors, resistors, and/or any other types of active or passive electrical components, but are not limited thereto. The interconnection layer214may include multiple dielectric material layers and a plurality of conductive structures formed in the dielectric material layers. For the sake of simplicity, only the conductive structure212in the topmost portion of the interconnection layer214is shown in the drawings. In some embodiments, the interconnection layer214may include circuit elements such as, but not limited to, capacitors, inductors, resistors, embedded memory, which are not shown for the sake of simplicity.

The second bonding structure layer221includes a second dielectric layer222, a second bonding layer124on the second dielectric layer222, and a plurality of second bonding pads226formed in the second bonding layer224and the second dielectric layer222. The top surfaces of the second bonding pads226are exposed from the second bonding layer224. The bottom surfaces of the second bonding pads226are in direct contact with the conductive structures220. The materials of the substrate210, the interconnection layer214, the conductive structures220, the second dielectric layer222, the second bonding layer224, and the second bonding pads226may be referred to the materials of the substrate110, the interconnection layer114, the conductive structures120, the first dielectric layer122, the first bonding layer124, and the first bonding pads126previously mentioned, and will not be repeated herein for the sake of simplicity. According to an embodiment of the present invention, the conductive structure220may include copper (Cu), the second dielectric layer222may include silicon oxide (SiO2), the second bonding layer224may include silicon carbonitride (SiCN), the second bonding pad226may include copper (Cu). According to an embodiment of the present invention, at this process stage, the second bonding pad226may have a thickness T3. The top surface of the second bonding pad226may be approximately flush with the surface of the second bonding layer224at this stage.

Please refer toFIG.4. Subsequently, a removal process P2is performed on the second device wafer200to remove a portion of the second bonding layer224, so that a protruding portion2260of each of the second bonding pad226may protrude from the surface of the second bonding layer224. The top surface226aand the sidewall226sof the protruding portion2260are exposed from the second bonding layer224. The removal process P2may be a wet etching process, a dry etching process, or a chemical mechanical polishing process that have etching selectivity between the materials of the second bonding pad226and the second bonding layer224. According to an embodiment of the present invention, the removal process P2is a wet etching process. When the second bonding layer224includes silicon carbonitride (SiCN), the removal process P2may use phosphoric acid (H3PO4) to etch the second bonding layer224. As shown inFIG.4, after the removal process P2, the second bonding layer224may have a thickness T5, and the second bonding pad226may still have the thickness T3. The thickness T5is smaller than the thickness T4of the first bonding layer124shown inFIG.2. The thickness T3is larger than the thickness T2of the first bonding pad126shown inFIG.2.

Please refer toFIG.5. Subsequently, a bonding process P3is performed to bond the first device wafer100and the second device wafer200, thereby a bonded semiconductor structure410may be produced.

The bonding process P3may include performing an alignment step to arrange the first device wafer100and the second device wafer200in a way that the second bonding layer224and the first bonding layer124are face to face and in direct contact and the protruding portions2260of the second bonding pads226are aligned and placed into the corresponding recessed portions130. After that, an anneal step of the bonding process P3may be performed to promote formation of covalent bonds between the first bonding layer124and the second bonding layer224and diffusions between the metal materials of the first bonding pad126and the second bonding pad226, thereby securely bonding the first device wafer100and the second device wafer200together. In some embodiments, the first device wafer100and the second device wafer200may be subjected to surface treatments before the bonding process P3to remove surface particles and/or improve the bonding properties. According to an embodiment of the present invention, the process temperature of the anneal step of the bonding process P3may be between 100° C. and 400° C., but is not limited thereto.

Please refer toFIG.6. The bonded semiconductor structure410provided by the present invention includes a first device wafer100and a second device wafer200disposed on the first device wafer100. The first device wafer100includes a first dielectric layer112, a first bonding pad126formed in the first dielectric layer112, and a first bonding layer124on the first dielectric layer112. The second device wafer200includes a second dielectric layer222, a second bonding layer224disposed on the second dielectric layer222, and a second bonding pad126formed in the second dielectric layer222and extending through the second bonding layer224and the first bonding layer124. The second bonding layer224is bonded with the first bonding layer124at a dielectric bonding interface310. The second bonding pad126is bonded with the first bonding pad126at a conductive bonding interface320.

More particularly, the present invention uses the protruding portions2260of the second device wafer200in conjunction with the recessed portions130of the first device wafer100to bond the device wafers, so that the dielectric bonding interface310and the conductive bonding interface320may have a step-height H. The height of the step-height H is related to the depth DI (shown inFIG.2) of the recessed portion130. For example, in some embodiments where the depth DI of the recessed portion130approximately equals to the thickness T4of the first bonding layer124, the height of the step-height H may approximately equal to the thickness T4of the first bonding layer124. In this embodiment, the width W3of the recessed portion130may be controlled to allow the sidewall124sof the first bonding layer124directly contacting the sidewall226sof the protruding portion2260of the second bonding pad226. By utilizing the concave/convex design of the protruding portions2260of the second bonding pads226and the recessed portions130located above the first bonding pads126to bond the first device wafer100and the second device wafer200, a larger bonding process window which is able to tolerate the surface topography variations caused by uneven surface of the underlying interconnection layers and/or CMP loading effect may be achieved. In this way, an intimate contact and improved bonding quality between the first bonding pads126of the first device wafer100and the second bonding pads226of the second device wafer200may be achieved.

The following description will detail the different embodiments of the present invention. To simplify the description, identical components in each of the following embodiments are marked with identical symbols. For making it easier to understand the differences between the embodiments, the following description will detail the dissimilarities among different embodiments and the identical features will not be redundantly described.

FIG.7is a schematic cross-sectional diagram showing a bonded semiconductor structure420according to a second embodiment of the present invention. In this embodiment, the width W1of the recessed portion130(shown inFIG.2) may be larger than the width of the top surface226aof the protruding portion2260of the second bonding pad226. In this way, a larger space for thermal expansion of the metal material of the second bonding pad226during the anneal step of the bonding process P3may be provided. As a result, after the bonding process P3, a step portion2262of the second bonding pad226adjacent to the dielectric bonding interface310may be formed by thermal expansion of the metal material of the second bonding pad226, which may be helpful for securing the bonding between the first device wafer100and the second device wafer200. Besides, the stress at the bonding interface caused by thermal expansion of the metal material of the second bonding pad226may be released, and the risk of metal extrusion and electrical shorting between bonding pads may be reduced. A larger alignment margin between the protruding portion2260and the recessed portion130may also be obtained.

FIG.8is a schematic cross-sectional diagram showing a bonded semiconductor structure430according to a third embodiment of the present invention. In this embodiment, the width W1of the recessed portion130(shown inFIG.2) may be much larger than the width of the top surface226aof the protruding portion2260of the second bonding pad226. Accordingly, after the bonding process P3, the thermal expanded protruding portion2260of the second bonding pad226may not completely fill the recessed portion130. As shown inFIG.8, an air gap330may be formed between the sidewall226sof the protruding portion2260of the second bonding pad226and the sidewall124sof the first bonding layer124. The sidewall226sand the sidewall124sare spaced apart by the air gap330. The air gap330may provide more stress buffer to the bonding interface between the first device wafer100and the second device wafer200.

FIG.9is a schematic cross-sectional diagram showing a bonded semiconductor structure440according to a fourth embodiment of the present invention.FIG.10is a schematic cross-sectional diagram showing a bonded semiconductor structure450according to a fifth embodiment of the present invention. As shown inFIG.9, by controlling the removal process P1to make the depth DI of the recessed portion130(shown inFIG.2) larger than the thickness T4of the first bonding layer124, the second bonding pad226of the bonded semiconductor structure440may pass through the entire thickness of the first bonding layer124. The step-height H between the dielectric bonding interface310and the conductive bonding interface320may be larger than the thickness T4of the first bonding layer124.

On the other hand, as shown inFIG.10, the depth DI of the recessed portion130(shown inFIG.2) may be smaller than the thickness T4of the first bonding layer124after the removal process P1. Accordingly, the second bonding pad226of the bonded semiconductor structure440may only pass through a portion of the thickness T4of the first bonding layer124. The step-height H between the dielectric bonding interface310and the conductive bonding interface320may be smaller than the thickness T4of the first bonding layer124.

In light of the above, the bonded semiconductor structure provided by the present invention is formed by bonding the first device wafer and the second device wafer while the first bonding pads of the first device wafer are recessed from the surface of the first bonding layer of the first device wafer and in conjunction with the protruding portions of the second bonding pads protruding from the surface of the second bonding layer of the second device wafer. In this way, the problem of defective bonding between the bonding pads caused by uneven surface of the interconnection layer and/or recessed surface of the bonding pad may be prevented. The bonding quality and correct signal transmission between the first device wafer and the second device wafer may be guaranteed.

Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.