Patent ID: 12243687

Repeat use of reference characters in the present specification and drawing is intended to represent same or analogous features or elements of the invention.

DETAILED DESCRIPTION OF REPRESENTATIVE EMBODIMENTS

It is to be understood by one of ordinary skill in the art that the present discussion is a description of exemplary embodiments only, and is not intended as limiting the broader aspects of the present invention, which broader aspects are embodied in the exemplary construction.

Generally speaking, the present invention is directed to an electrical component array including one or more heat sink layers. The component array can include a stacked configuration of multilayer ceramic components, which can include external terminals (e.g., at respective ends of the components). The heat sink layers can be arranged between respective pairs of the multilayer ceramic components, for example in an alternating configuration. The heat sink layers can selectively connect the external terminals of the components. The heat sink layer can draw heat from the multilayer ceramic components. The heat can flow through the heat sink layer to the edges of the array such that the heat can be removed from the array by conduction. Heat can then dissipate from the electrical component array to the ambient environment through convection to reduce the temperature of the electrical component array.

Such heat dissipation can improve the power capacity of the array. For example, the array can have a greater power capacity than a conventional stacked capacitor array of the same footprint (e.g., corresponding with a case size of the array). An area power capacity of the array can be defined as the power capacity of the array (e.g., in watts) divided by a footprint of the array (e.g., in square millimeters). Thus, an array according to the present disclosure can provide greater power handling capacity without requiring additional surface area (or real estate) on a mounting surface, such as a printed circuit board.

As examples, in some embodiments the array can have a power capacity of greater than about 0.1 W, in some embodiments greater than about 0.1 W, in some embodiments greater than about 0.5 W, in some embodiments greater than about 1 W, in some embodiments greater than about 5 W, and in some embodiments greater than about 10 W.

A volume power capacity of the array can be defined as the power capacity of the array (e.g., in watts) divided by a volume of the array (e.g., in cubic millimeters). Inclusion of heat sink layers as described herein can increase the volume power capacity of the array by facilitating heat flow out of and away from the components to be dissipated from the array.

As example, in some embodiments, the array can have a power capacity of greater than about 0.02 W/mm2, in some embodiments greater than about 0.05 W/mm2, in some embodiments greater than about 0.1 W/mm2, and in some embodiments greater than about 0.5 W/mm2.

The array can be formed in a variety of sizes. As examples the array can have a length that ranges from about 0.04 mm to about 5 mm or greater, in some embodiments from about 0.1 mm to about 4 mm, in some embodiments from about 0.2 mm to about 3 mm, and in some embodiments from about 0.5 mm to about 2 mm. The array can have a width that ranges from about 0.02 mm to about 5 mm or greater, in some embodiments from about 0.05 mm to about 4 mm, in some embodiments from about 0.1 mm to about 3 mm, and in some embodiments from about 0.3 mm to about 2 mm. As examples, the array can have an EIA case size (in thousands of the inches) that ranges from 0303 to 2010, in some embodiments from 0402 to 1515.

In some embodiments, each component of the array can be or include a multilayer ceramic capacitor such that the capacitors are arranged in parallel. The array can be used in applications where a high capacitance is desired. For example, the array can exhibit capacitance values of 0.1 μF or more, in some embodiments about 1 μF or more, in some embodiments 10 μF or more, and in some embodiments 1000 μF or more.

However, in other embodiments, relatively low capacitance values can be achieved, such as less than 0.1 μF, in some embodiments less than 500 nF, in some embodiments less than 100 nF, in some embodiments less than 10 nF, and in some embodiments less than 1 nF.

The array can include a variety of types of electrical components. In some embodiments, the array can include multiple capacitors without other types of electrical components. In other embodiments, the array can include a combination of various different types of components, such as a multilayer capacitor, a multilayer varistor, a multilayer capacitor, and a resistor (e.g., a thin film resistor). As examples, the array can include a heat sink layer between two multilayer varistors; the array can include a heat sink layer between two multilayer resistors; and the array can include a heat sink layer between a multilayer varistor and a multilayer capacitor. One or ordinary skill in the art will understand that various other combinations are possible within the scope of the present disclosure.

The array can include a range of multilayer ceramic components. For example, in some embodiments, the array can include two multilayer ceramic components with a heat sink layer arranged between the multilayer ceramic components. In other embodiments, the array can include 3 or more multilayer ceramic components, in some embodiments 4 or more, in some embodiments 5 or more, in some embodiments 6 or more, in some embodiments 10 or more, in some embodiments 20 or more, and in some embodiments 50 or more multilayer ceramic components. Heat sink layers can be arranged between each respective pair of multilayer ceramic components or between selective pairs of multilayer ceramic components.

In other embodiments, the array can include a heat sink layer arranged between two components, one or more of which be a component other than multilayer ceramic components. For instance, the heat sink layer can be arranged between a monolithic microwave integrated circuit (MMIC) and one or more of a multilayer ceramic component, a diode, a substrate, a GaN based component, a field-programmable gate array, integrated circuit component, or other suitable component. In other embodiments, the heat sink layer can be arranged between any suitable combination of components or devices described above and herein.

A first multilayer ceramic component can have a first terminal at a first end and a second terminal at a second end that is opposite the first end in a first direction. A second multilayer ceramic component can be spaced apart from the first multilayer ceramic component in a second direction that is perpendicular to the first direction. The second multilayer ceramic component can have a first terminal at a first end and a second terminal at a second end that is opposite the first end in the first direction. A heat sink layer can be arranged between the first multilayer ceramic component and the second component in the second direction. A first metallization layer can be formed on the heat sink layer and can electrically connect the first terminal of the first multilayer ceramic component with the first terminal of the second multilayer ceramic component. A second metallization layer can be formed on the heat sink layer and can electrically connect the second terminal of the first multilayer ceramic component with the second terminal of the second multilayer ceramic component. Thus, the heat sink layer can electrically connect the first and second multilayer ceramic components to form the array.

In some embodiments, the heat sink layer can include one or more additional metallization layers. For example, a third metallization layer that is electrically isolated from each of the first and second metallization can be formed of the heat sink layer. The third metallization layer can contact one or both of the first and second electrical components. The third metallization layer can improve heat conduction from the electrical components into the heat sink layer to improve heat dissipation away from the electrical components.

The heat sink layer can have a range of dimensions. For example, the heat sink layer can have a thickness in the second direction that ranges from about 0.01 mm to about 50 mm, in some embodiments from about 0.1 mm to about 5 mm, in some embodiments from about 0.2 mm to about 4 mm, in some embodiments from about 0.3 mm to about 3 mm, and in some embodiments from about 0.4 mm to about 1.5 mm.

The heat sink layer(s) can include a material that is thermally conductive and electrically resistive. The heat sink layer can include a material having a thermal conductivity between about 100 W/m·° C. and about 300 W/m·° C. at about 22° C., in some embodiments between about 125 W/m·° C. and about 250 W/m·° C. at about 22° C., in some embodiments between about 150 W/m·° C. and about 200 W/m·° C. at about 22° C. As examples, the heat sink layer can include aluminum nitride, beryllium oxide, aluminum oxide, boron nitride, silicon nitride, magnesium oxide, zinc oxide, silicon carbide, any suitable ceramic material, and mixtures thereof.

As is known in the art, thermal resistivity and thermal conductivity of a material are inversely related. Thus, a low thermal resistivity correlates with a high thermal conductivity. In some embodiments, the heat sink layer may be made from any suitable material having a generally low thermal resistivity (e.g., less than about 6.67×10−3m·° C./W), and a generally high electrical resistivity (e.g., greater than about 1014Ω·cm). A thermal resistivity of 6.67×10−3m·° C./W is equivalent with a thermal conductivity of about 150 W/m·° C. In other words, suitable materials for the heat sink layer may have a generally high thermal conductivity, such as greater than about 150 W/m·° C.

For example, in some embodiments, the heat sink layer may be made from a material having a thermal conductivity between about 100 W/m·° C. and about 300 W/m·° C. at about 22° C. In other embodiments, the heat sink layer may be made from a material having a thermal conductivity between about 125 W/m·° C. and about 250 W/m·° C. at about 22° C. In other embodiments, the heat sink layer may be made from a material having a thermal conductivity between about 150 W/m·° C. and about 200 W/m·° C. at about 22° C.

As example, the heat sink layer may comprise aluminum nitride, beryllium oxide, aluminum oxide, boron nitride, silicon nitride, magnesium oxide, zinc oxide, silicon carbide, any suitable ceramic material, and mixtures thereof. Any suitable material that is electrically resistive and thermally conductive may be used, however.

For example, in some embodiments, the heat sink layer may be made primarily from aluminum nitride. The heat sink layer may contain additives or impurities. In other embodiments, the heat sink layer includes beryllium oxide. For example, in some embodiments the heat sink layer may be made from any suitable composition including beryllium oxide. In some embodiments, the heat sink layer may be made primarily from beryllium oxide.

In some embodiments, the terminals may include an outer layer over an inner layer. The inner layer may be magnetic in some embodiments, and non-magnetic in other embodiments. The outer layer may be formed from any suitable material, including, for example, corrosion-resistant materials. For example, in some embodiments, the terminals may comprise an outer layer of gold, silver, platinum, nickel, and/or a mixture or compound thereof. For example, in one embodiment, one or more of the terminals may include an outer layer of gold disposed over a magnetic substrate, such as a magnetic or magnetized metal. In some embodiments, the substrate may include a metal such as copper or steel. In another embodiment, one of more of the terminals may include an outer layer, such as gold, disposed over a non-magnetic substrate, such as a ceramic, for example. In other embodiments, the outer layer may be gold, silver, platinum, nickel, copper, steel, and/or any other suitable material. Similarly, in other embodiments, the substrate may be gold, silver, platinum, nickel, copper, steel, and/or any other suitable material. Moreover, in some embodiments, the terminals may not include an outer layer (e.g., may include a single layer).

The array may be manufactured or fabricated using any suitable technique. For example, the heat sink layer(s) can be deposited on the multilayer capacitors or other ceramic components. Various physical and/or chemical deposition processes can be employed. Additionally or alternatively, the ceramic components can be dipped to form the heat sink layer(s) as a film (e.g., a thin film and/or thick film).

The terminals of the components and/or metallization layers of the heat sink may be formed using any suitable process, including, for example, chemical or vapor deposition on the heat sink layer and/or components. Alternatively, in some embodiments, the terminals may be formed by dipping portions of the components and/or heat sink layer(s) in a liquid form of the terminal material and then allowing the terminal material to harden. The terminals may then be additionally shaped or finished using any suitable method, including for example, grinding or sanding. In some embodiments, the above process may be repeated to produce terminals having multiple layers, e.g., a gold plating over a magnetic or non-magnetic layer.

The components and/or heat sink layer(s) (if formed separate from the component(s)) can be stacked together to form the array. The terminals of the components and/or heat sink layer(s) can be joined together using solder and/or heat to melt and fuse the terminals.

Lead frames can be coupled to the terminals of the components and/or heat sink layer(s). Alternatively, one or more additional layers can be formed over the terminals and/or metallization layers. For example, the component can be configured for surface mounting using soldering, brazing, or the like.

In some embodiments, a length of the first component and/or array (e.g., between first terminals and the second terminals) can be greater than a width of the first component and/or a width of the array. However, in some embodiments, a length of the components and/or array in the first direction can be greater than a width of the components and/or array in the third direction. This configuration can be referred to as a “reverse geometry” configuration. For example, a ratio of the length to the width of the array may be less than 1, in some embodiments less than about 0.8, in some embodiments less than about 0.7, in some embodiments less than about 0.6, and in some embodiments less than about 0.5.

I. Example Embodiments

FIGS.1A and1Billustrate a perspective view and an exploded perspective view, respectively, of an example embodiment of a component array100. The component array100can include a first multilayer ceramic component102having a first terminal104at a first end106and a second terminal108at a second end110opposite the first end106in a first direction112. The component array100can generally have a monolithic, rectangular prism configuration.

A second multilayer ceramic component113can be spaced apart from the first multilayer ceramic component102in a second direction114that is perpendicular to the first direction112. The second multilayer ceramic component113can have a first terminal115at a first end116and a second terminal118at a second end120that is opposite the first end116in the first direction112.

A heat sink layer122can be arranged between the first multilayer ceramic component102and the second component in112the second direction114. For example, the components102,113and heat sink layer122can be stacked together to form the array100.

The heat sink layer122can include one or more metallization layers. The metallization layers can improve heat conduction and/or selectively electrically connect various terminals of the components102,113. For example, the heat sink layer122can include a first metallization layer124formed on the heat sink layer122. The first metallization layer124can electrically connect the first terminal104of the first multilayer ceramic component102with the first terminal115of the second multilayer ceramic component113. A second metallization layer126can be formed on the heat sink layer122and electrically connecting the second terminal108of the first multilayer ceramic component102with the second terminal118of the second multilayer ceramic component113.

The metallization layers124,126can facilitate heat conduction out of the first multilayer ceramic component102and the second multilayer ceramic component114. As indicated above, the heat sink layer122can include a material having a thermal conductivity from about 150 W/m·° C. to about 300 W/m·° C. at about 22° C. As examples, the heat sink layer122can include aluminum nitride or beryllium oxide.

The heat sink layer122can generally be arranged between the first multilayer ceramic component102and the second multilayer ceramic component113. For example, the second multilayer ceramic component113can include a top planar surface128(FIG.1B). The first multilayer ceramic component102can include a bottom planar surface130(FIG.1B). The heat sink layer122can be arranged between and/or contact each of the top planar surface128of the second multilayer ceramic component113and the bottom planar surface130of the first multilayer ceramic component102. The heat sink layer122can include a top planar surface132and a bottom planar surface134. The top planar surface132of the heat sink layer122can be arranged opposite the bottom planar130surface of the first multilayer ceramic component102. For example, the top planar surface132of the heat sink layer122can directly contact the bottom planar130surface of the first multilayer ceramic component102. The bottom planar surface134of the heat sink layer122can be arranged opposite the top planar surface128of the second multilayer ceramic component113. For example, the bottom planar surface134of the heat sink layer122can directly contact the top planar surface128of the second multilayer ceramic component113. Thus, the heat sink layer122can be sandwiched between the ceramic components102,113.

One or more of the metallization layers124,126can wrap around the heat sink layer such that one or more of the metallization layers124,126are formed on each of the top planar surface132of the heat sink layer122and the bottom planar surface134of the heat sink layer122. Such a wrap around configuration can facilitate electrical connection between the first terminal104of the first multilayer ceramic component102and the first terminal115of the second multilayer ceramic component113and/or between the second terminal108of the first multilayer ceramic component102and the second terminal118of the second multilayer ceramic component113.

The component array100can include one or more lead frames136,138. A first lead frame136can be electrically coupled with (e.g., affixed to) the first terminal104of the first multilayer ceramic component102, the first terminal115of the second multilayer ceramic component113, and/or the first metallization layer124formed on the heat sink layer122. A second lead frame138can be electrically coupled with (e.g., affixed to) the second terminal108of the second multilayer ceramic component113, the second terminal118of the second multilayer ceramic component113, and/or the second metallization layer126formed on the heat sink layer122.

The heat sink layer122can have a thickness141in the second direction114. For example, in some embodiments, the thickness141can range from about 0.1 mm to about 5 mm.

The component array100can be configured for mounting in a variety of configurations. For example, the component array100can be configured for mounting such that the planar surfaces128,130,132,134of the components102,113and/or heat sink layer122are arranged parallel to a mounting surface140. For example, one or more of the lead frames136,138can include one or more leads139that extends in the second direction114for mounting the array100to the mounting surface140such that the second direction114is perpendicular to the mounting surface140. The leads139can have a variety of configurations such as through-hole leads, J-style leads, L-style leads, or any other suitable lead configurations.

In some embodiments, the electrical components102,113and heat sink layer122of the component array100can generally have the same dimensions in the first direction112and third direction113, such that the component array100has a generally monolithic and/or rectangular prism configuration. For example, the first component102can have a length146in the first direction112and a width148in the third direction144. The heat sink layer122and second component113can generally have the same length146and width148as the first component102. Referring toFIG.1B, the heat sink layer122can have a length150in the first direction112and a width152in the third direction144. The length150of the heat stink layer122can be approximately equal to the length146of the first component102. The width152of the heat sink layer122can be approximately equal to the width148of the first component102.

In some embodiments, the electrical components102,113and heat sink layer122of the component array100can generally have the same dimensions in the first direction112and third direction144, such that the component array100has a monolithic, rectangular prism configuration. More specifically, the length146of the component array100can generally correspond to the larger of a length of the first component102and a length of the second component113in the first direction112. A length147of the first component102can be approximately equal to a length149of the second component113, and thus equal to the length146of the component array100.

In other embodiments, however, the length150of the heat sink layer122can be greater than or less than the length146of the first component102. For example, the length150of the heat sink layer122can be greater than one or both of the length(s)147,149of the components102,113such that the heat sink layer122extends away from the first component102and/or second component113in the first direction112.

Similarly, the width152of the heat sink layer122can be greater than or less than the width148of the first component102. For example, the width152of the heat sink layer122can be greater than the width148of the first component102such that the heat sink layer122extends outward in the third direction144from the first component102. For example, portions of the heat sink layer122that extend outward in the third direction144from the first component102can increase thermal convection between the heat sink layer122and an ambient environment. Such portions of the heat sink layer122can act as thermal fins.

Referring toFIGS.2A and2B, in other embodiments, a component array200can be configured for mounting such that one or more planar surfaces228,230,232,234of components202,213and/or a heat sink layer222are arranged parallel to a mounting surface240. Reference numerals inFIGS.2A and2Bgenerally correspond to features and elements ofFIG.1. The lead frames136,138can include one or more leads139that extends in a third direction144that is perpendicular to each of the first direction112and the second direction114.

In some embodiments, the heat sink layer322can include one or more additional metallization layers, which can improve head conduction from the components to the heat sink layer(s). For example,FIGS.3A and3Billustrate a perspective view and a bottom view, respectively, of an example embodiment of a heat sink layer322that includes a third metallization layer346according to aspects of the present disclosure. A third metallization layer346can be formed on at least one of a top planar surface332of the heat sink layer322or a bottom planar surface334of the heat sink layer322. The third metallization layer346can be electrically isolated from each of a first metallization layer324and a second metallization layer326. The third metallization layer346can include a first portion348formed on the top planar surface332of the heat sink layer322, a second portion350formed on the bottom planar surface334of the heat sink322, and a third portion352connecting the first portion348and the second portion350.

FIGS.4A and4Billustrate a perspective view and a bottom view, respectively, of an example embodiment of a heat sink layer422that includes a third metallization layer446formed on the top planar surface432of the heat sink layer432and a fourth metallization layer456formed on the bottom planar surface434of the heat sink422. The third metallization layer446can be electrically isolated from each of the first metallization layer424and the second metallization layer426.

FIG.5illustrates a perspective view of another embodiment of a component array500that can include the heat sink layer322ofFIG.3Barranged between a first component502and a second component513. The first portion348(FIG.3A) of the third metallization layer346can contact the first component502. The second portion352(FIG.3B) of the third metallization layer346can contact the second component513. As shown inFIG.5, the second portion350of the third metallization layer346can be exposed along an exterior of the component array500.

In some embodiments, the length146of the first component102and/or array100(e.g., between first terminals104,115and the second terminals108,118) can be greater than the width148of the first component102and/or array100, for example as illustrated inFIGS.1A through5. However, referring toFIG.6, in some embodiments, a length646of the components602,613and/or array600in the first direction112can be greater than a width648of the components602,613and/or array600in the third direction144(e.g., as a “reverse geometry” component). For example, a ratio of the length646to the width648may be less than 1, in some embodiments less than about 0.8, in some embodiments less than about 0.7, in some embodiments less than about 0.6, and in some embodiments less than about 0.5.

II. Applications

In some embodiments, the array can be configured as a stacked capacitor array. Each component of the array can be or include a multilayer ceramic capacitor such that the capacitors are arranged in parallel. In other embodiments, the array can include a mixture of components (e.g., capacitors, varistors, resistors, etc.).

The array may be employed in a wide variety of applications. Examples include digital circuits, hybrid circuits, and analog circuits. For instance, the array can be employed in laser optics drivers, gallium-nitride-based devices, monolithic microwave integrated circuits, other integrated circuits, high speed digital serializer and/or de-serializer integrated circuits, field-programmable gate arrays, and/or direct-to-radiofrequency conversion devices. As additional examples, the array can be included in power conversion circuits (e.g., input and/or output filters in DC/DC converters), power supplies (e.g., switch mode power supplies, telecommunication network circuits and/or devices, motor drive filters, and hybrid power applications. Other suitable applications may include, for instance, waveguides, RF applications (e.g., delay lines), antenna structures, matching networks, resonant circuits, and other applications. Further, the array can be used in a variety of aerospace applications. As one example, the array can be employed in circuits and/or devices in missiles (e.g., hypersonic missiles), aerospace instrumentation panels, or the like.

The array can provide a variety of benefits, including increased power capacity as described herein. Further in some embodiments and/or applications, the array can reduce radiation emission (e.g., alpha particles, beta particles, etc.).

Referring toFIG.7, in one example application configuration700, a separate component702may be mounted on top of the component array100, for example as described above with reference toFIGS.1A and1B. The component array100can act as both a heat sink and capacitive energy source. For example, the component702can have a first terminal704connected with the first terminal104of the first multilayer ceramic component102and a second terminal706connected with the second terminal126of the first multilayer ceramic component102and a second terminal706. Thus, in this example application configuration700, the separate component702can be electrically connected in parallel with the component array100. However, other configurations are possible. For instance, the separate component702can be electrically connected in series with the component array100. The separate component702can include additional terminals and/or be connected with components in addition to the component array100.

Example separate components702include transistors, diodes, resistors, varistors, other passive devices, electronic circuits, or components thereof. As one example, the separate component702can be or include a Gallium Nitride (GaN) transistor, such as a high mobility transistor (HEMT).

III. Test Methods

A capacitance of the array may be measured according to MIL-STD-202 Method 305, using a Keithley 3330 Precision LCZ meter with a DC bias of 0.0 volts, 1.1 volts, or 2.1 volts (1 volt root-mean-squared sinusoidal signal). The operating frequency is 1 KHz, and the temperature is about 25° C. The relative humidity may be 25% or 85%.

Power Capacity

The power capacity of the array can be defined as a power level that produces a steady state temperature of about 85° C. The power capacity can be measured using a Keithley 2400 series Source Measure Unit (SMU), for example, a Keithley 2410-C SMU.

The array may be subjected to a sinusoidal input signal at a variety of frequencies and amplitudes. The array may initially be at a typical room temperature (24.8° C.). The sinusoidal input signal may be applied at a test frequency. An amplitude of the sinusoidal input signal can be iteratively increased until the array reaches a steady temperate of about 85° C.

More specifically, the array can be subjected to a steady state power level (e.g., about 300 MHz sinusoidal signal with a root-mean-square power of 1 W) until the filter assembly reached a steady state temperature. The power level can then be increased by a fixed step amount (e.g., 1 W) and maintained at the new higher power level (e.g., about 300 MHz sinusoidal signal with a root-mean-square power of 2 W, 3 W, 4 W, etc.). This process can be repeated until the steady state temperature of the array is about 85° C. The applied power at that point can be measured as the power capacity of the array. The above procedure may be repeated using a variety of frequencies to establish the power capacity of the array across a range of frequencies, if desired.

An area power capacity of the array can be calculated by dividing the measured power capacity of the array by an area or footprint of the array. A volume power capacity of the array can be calculated by dividing the measured power capacity of the array by a volume of the array.

These and other modifications and variations of the present invention may be practiced by those of ordinary skill in the art, without departing from the spirit and scope of the present invention. In addition, it should be understood that aspects of the various embodiments may be interchanged both in whole or in part. Furthermore, those of ordinary skill in the art will appreciate that the foregoing description is by way of example only, and is not intended to limit the invention so further described in such appended claims.