Patent ID: 12190814

DETAILED DESCRIPTION OF THE EMBODIMENTS

In the following description, for the purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of various embodiments or implementations of the disclosure. As used herein “embodiments” and “implementations” are interchangeable words that are non-limiting examples of devices or methods disclosed herein. It is apparent, however, that various embodiments may be practiced without these specific details or with one or more equivalent arrangements. Here, various embodiments do not have to be exclusive nor limit the disclosure. For example, specific shapes, configurations, and characteristics of an embodiment may be used or implemented in another embodiment.

The terminology used herein is for the purpose of describing particular embodiments and is not intended to be limiting. As used herein, the singular forms, “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. Moreover, the terms “comprises,” “comprising,” “includes,” and/or “including,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, components, and/or groups thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. It is also noted that, as used herein, the terms “substantially,” “about,” and other similar terms, are used as terms of approximation and not as terms of degree, and, as such, are utilized to account for inherent deviations in measured, calculated, and/or provided values that would be recognized by one of ordinary skill in the art.

In the description, the expression “is the same” may mean “substantially the same”. That is, it may be the same enough to convince those of ordinary skill in the art to be the same. In other expressions, “substantially” may be omitted.

Although the terms “first,” “second,” etc. may be used herein to describe various types of elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another element. Thus, a first element discussed below could be termed a second element without departing from the teachings of the disclosure.

When an element, such as a layer, is referred to as being “on,” or “connected to,” another element or layer, it may be directly on or connected to the other element or layer or intervening elements or layers may be present. To this end, the term “connected” may refer to physical, electrical, and/or fluid connection, with or without intervening elements. When a component is described herein to “connect” another component to the other component or to be “connected to” other components, the components may be connected to each other as separate elements, or the components may be integral with each other.

For the purposes of this disclosure, “at least one of X, Y, and Z” and “at least one selected from the group consisting of X, Y, and Z” may be construed as X only, Y only, Z only, or any combination of two or more of X, Y, and Z, such as, for instance, XYZ, XYY, YZ, and ZZ. Also, in the specification and the claims, the term “and/or” is intended to include any combination of the terms “and” and “or” for the purpose of its meaning and interpretation. For example, “A and/or B” may be understood to mean “A, B, or A and B.” The terms “and” and “or” may be used in the conjunctive or disjunctive sense and may be understood to be equivalent to “and/or.”

Spatially relative terms, such as “below,” “under,” “above,” “higher,” “side” (e.g., as in “sidewall”), and the like, may be used herein for descriptive purposes, and, thereby, to describe one elements relationship to another element(s) as illustrated in the drawings. Spatially relative terms are intended to encompass different orientations of an apparatus in use, operation, and/or manufacture in addition to the orientation depicted in the drawings. For example, if the apparatus in the drawings is turned over, elements described as “below” other elements or features would then be oriented “above” the other elements or features. Thus, the example term “below” can encompass both an orientation of above and below. Furthermore, the apparatus may be otherwise oriented (e.g., rotated 90 degrees or at other orientations), and, as such, the spatially relative descriptors used herein interpreted accordingly.

As customary in the field, some embodiments are described and illustrated in the accompanying drawings in terms of functional blocks, units, and/or modules. Those skilled in the art will appreciate that these blocks, units, and/or modules are physically implemented by electronic (or optical) circuits, such as logic circuits, discrete components, microprocessors, hard-wired circuits, memory elements, wiring connections, and the like, which may be formed using semiconductor-based fabrication techniques or other manufacturing technologies. In the case of the blocks, units, and/or modules being implemented by microprocessors or other similar hardware, they may be programmed and controlled using software (e.g., microcode) to perform various functions discussed herein and may optionally be driven by firmware and/or software. It is also contemplated that each block, unit, and/or module may be implemented by dedicated hardware, or as a combination of dedicated hardware to perform some functions and a processor (e.g., one or more programmed microprocessors and associated circuitry) to perform other functions. Also, each block, unit, and/or module of some example embodiments may be physically separated into two or more interacting and discrete blocks, units, and/or modules without departing from the scope of the disclosure. Further, the blocks, units, and/or modules of some example embodiments may be physically combined into more complex blocks, units, and/or modules without departing from the scope of the disclosure.

Hereinafter, various embodiments of the disclosure will be described in detail with reference to the accompanying drawings so that those of ordinary skill in the art may easily implement the disclosure. The disclosure may be embodied in various different forms and is not limited to the embodiments described herein.

In order to clearly describe the disclosure, parts that are not related to the description are omitted, and the same or similar components are denoted by the same reference numerals throughout the specification. Therefore, the reference numerals described above may also be used in other drawings.

Unless otherwise specified, the illustrated embodiments are to be understood as providing example features of the disclosure. Therefore, unless otherwise specified, the features, components, modules, layers, films, panels, regions, and/or aspects, etc. (hereinafter individually or collectively referred to as “elements”), of the various embodiments may be otherwise combined, separated, interchanged, and/or rearranged without departing from the disclosure.

The size and thickness of each component shown in the drawings are arbitrarily shown for convenience of description, and thus the disclosure is not necessarily limited to those shown in the drawings. In the drawings, thicknesses may be exaggerated to clearly express the layers and regions.

Various embodiments are described herein with reference to sectional and/or exploded illustrations that are schematic illustrations of embodiments and/or intermediate structures. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments disclosed herein should not necessarily be construed as limited to the particular illustrated shapes of regions, but are to include deviations in shapes that result from, for instance, manufacturing. In this manner, regions illustrated in the drawings may be schematic in nature and the shapes of these regions may not reflect actual shapes of regions of a device and, as such, are not necessarily intended to be limiting.

Unless otherwise defined or implied herein, all terms (including technical and scientific terms) used have the same meaning as commonly understood by those skilled in the art to which this disclosure pertains. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and should not be interpreted in an ideal or excessively formal sense unless clearly defined in the specification.

FIG.1is a schematic block diagram illustrating a display device according to an embodiment.

Referring toFIG.1, a display device100according to an embodiment may include a pixel unit110, a scan driver120, a data driver130, a timing controller140, a first initialization driver150, a second initialization driver160, a compensation driver170, and an emission driver180.

The display device100may be a flat panel display device, a flexible display device, a curved display device, a foldable display device, a bendable display device, or the like. The display device100may be a transparent display device, a head mounted display device, a wearable display device, or the like. The display device100may be applied to various electronic devices such as smart phones, tablets, smart pads, TVs, monitors, and the like.

The display device100may be an organic light emitting display device, a liquid crystal display device, a self-light emitting display device including an inorganic light emitting element, or the like. However, the display device100is not limited thereto.

The pixel unit110may include pixels PXij positioned to be connected to multiple vertical lines, for example, data lines DL1to DLn (where n may be a natural number) and multiple horizontal lines. Although not shown in the drawings, the pixels PXij may receive voltages from an external power source. The pixel unit110may receive a data voltage corresponding to an input image from the data driver130through the data lines DL1to DLn. The pixel unit110may receive driving signals for driving multiple pixel circuits included in the pixel unit110from multiple drivers included in the display device100through the horizontal lines. Referring toFIG.1, the drivers may be the scan driver120, the first initialization driver150, the second initialization driver160, the compensation driver170, and/or the emission driver180.

In an embodiment, transistors included in a pixel PXij may be P-type transistors (for example, P-type oxide thin film transistors). For example, an oxide thin film transistor may be a low temperature polycrystalline oxide (LTPO) thin film transistor. However, the transistors are not limited thereto. For example, an active pattern (semiconductor layer) included in the transistors may include an inorganic semiconductor (for example, amorphous silicon or poly silicon) or an organic semiconductor. In another embodiment, at least one of the transistors included in the display device100and/or the pixel PXij may be replaced with an N-type transistor.

The timing controller140may generate multiple control signals for controlling the drivers included in the display device100, including a data driving control signal DCS, in response to synchronization signals supplied from outside. Referring toFIG.1, the control signals may be a scan driving control signal SCS, a data driving control signal DCS, a first initialization driving control signal ICS1, a second initialization driving control signal ICS2, a compensation driving control signal CCS, or an emission driving control signal ECS. The control signals generated by the timing controller140may each be supplied to corresponding drivers. For example, inFIG.1, the data driving control signal DCS for controlling the data driver130may be supplied to the data driver130. For example, a scan driving control signal SCS for controlling the scan driver120may be supplied to the scan driver120. For example, a first initialization driving control signal ICS1for controlling the first initialization driver150may be supplied to the first initialization driver150. For example, a second initialization driving control signal ICS2for controlling the second initialization driver160may be supplied to the second initialization driver160. For example, a compensation driving control signal CCS for controlling the compensation driver170may be supplied to the compensation driver170. For example, an emission driving control signal ECS for controlling the emission driver180may be supplied to the emission driver180.

Each of the control signals supplied to the drivers may include a control start signal and clock signals. The control start signal may control a timing of a driving control signal. Referring toFIG.1, the control start signal may be a scan signal GWi (or GW), a first initialization signal GRi (or GR), a second initialization signal GIi (or GI), a compensation control signal EM1i(or EM1), or an emission control signal EM2i(or EM2). The clock signals may be used to shift the control start signal.

The scan driver120may receive the scan driving control signal SCS from the timing controller140. The scan driver120receiving the scan driving control signal SCS may supply a scan signal GW to the pixel unit110through the horizontal lines. The scan signal GW may be a signal for applying a data voltage to a gate electrode of a driving transistor included in a pixel PXij at a time point (e.g., a predetermined or selectable time point).

The first initialization driver150may receive the first initialization driving control signal ICS1from the timing controller140. The first initialization driver150receiving the first initialization driving control signal ICS1may supply a first initialization signal GR to the pixel unit110through the horizontal lines. The first initialization signal GR may be a signal for applying a reference voltage to the gate electrode of the driving transistor included in the pixel PXij to initialize the gate electrode of the driving transistor.

The second initialization driver160may receive the second initialization driving control signal ICS2from the timing controller140. The second initialization driver160receiving the second initialization driving control signal ICS2may supply a second initialization signal GI to the pixel unit110through the horizontal lines. The second initialization signal GI may be a signal for applying an initialization voltage to an anode electrode of a light emitting element included in the pixel PXij to initialize the anode electrode of the light emitting element.

The compensation driver170may receive the compensation driving control signal CCS from the timing controller140. The compensation driver170receiving the compensation driving control signal CCS may supply a compensation control signal EM1to the pixel unit110through the horizontal lines. In an embodiment, the compensation driving control signal CCS may be a signal for compensating a threshold voltage of the driving transistor included in the pixel PXij.

The emission driver180may receive the emission driving control signal ECS from the timing controller140. The emission driver180receiving the emission driving control signal ECS may supply an emission control signal EM2to the pixel unit110through the horizontal lines. In an embodiment, the emission control signal EM2may be a signal for controlling light emitting from the light emitting element included in the pixel PXij.

For example, each of the drivers may sequentially supply a driving control signal to the horizontal lines. For example, the scan driver120may sequentially supply a scan signal GW among n scan signals GW1to GWn to a corresponding line (e.g., a horizontal line) among n horizontal lines. In case that the scan signal GW is sequentially supplied, the pixels PXij may be selected in units of horizontal lines. To this end, the scan signal GW may be set to a gate-on voltage (for example, a logic high level) so that the transistors included in the pixels PXij may be turned on.

A method of sequentially supplying a driving control signal to the horizontal lines by other drivers and the scan driver120may be the same, and a description thereof will be omitted.

InFIG.1, the scan driver120, the first and second initialization drivers150and160, the compensation driver170, and the emission driver180are shown as being located (or disposed) on both sides of the pixel unit110. However, locations of the drivers are not limited thereto. For example, the compensation driver170and the emission driver180may be located (or disposed) below the pixel unit110.

In an embodiment, an image displayed from the display device100may include multiple emission cycles within one frame period.

FIG.2is a schematic diagram of an equivalent circuit of a pixel ofFIG.1.

Referring toFIG.2, for convenience of description, a pixel PXij positioned on and connected to an i-th horizontal line (or i-th pixel row) and a j-th data line DLj (or DL) is shown, where i and j may be natural numbers.

Referring toFIG.2, the pixel PXij may include a light emitting element LD, a driving transistor DT, first to fourth transistors T1to T4, a storage capacitor Cst, and a hold capacitor Chold.

The driving transistor DT may be connected between a terminal of a first power source ELVDD and the light emitting element LD (or a second node N2), and may have a gate electrode connected to a first node N1. The driving transistor DT may control an amount of current flowing from the first power source ELVDD to a second power source ELVSS through the light emitting element LD in response to a voltage of the first node N1. In an embodiment, the voltage level of the first power source ELVDD may be higher than the voltage level of the second power source ELVSS.

The light emitting element LD may be connected between the second node N2and a terminal of the second power source ELVSS. For example, an anode electrode of the light emitting element LD may be connected to the second node N2, and a cathode electrode of the light emitting element LD may be connected to the terminal of the second power source ELVSS. The light emitting element LD may generate light with a luminance in response to the amount of current (driving current) supplied from the driving transistor DT. In an embodiment, the light emitting element LD may be an organic light emitting diode including an organic light emitting layer. In another embodiment, the light emitting element LD may be an inorganic light emitting element including an inorganic material. In another embodiment, the light emitting element LD may be a light emitting element composed of a combination of an inorganic material and an organic material. In another embodiment, the light emitting element LD may have a form in which multiple inorganic light emitting elements are connected in parallel and/or in series between the second power source ELVSS and the second node N2.

The first transistor T1may be connected between a reference power source and the first node N1. A first initialization control signal GR may be applied to a gate electrode of the first transistor T1. In case that the first initialization control signal GR is applied to the gate electrode of the first transistor T1, the first transistor T1may be turned on, and a reference voltage Vref may be applied to the gate electrode of the driving transistor DT.

The second transistor T2may be connected between an initialization power source and the second node N2. A second initialization control signal GI may be provided to a gate electrode of the second transistor T2. In case that the second initialization control signal GI is provided to the gate electrode of the second transistor T2, the second transistor T2may be turned on, and an initialization voltage Vint may be applied to the anode electrode of the light emitting element LD.

The third transistor T3may be connected between a data line DL and the first node N1. The scan signal GW may be provided to a gate electrode of the third transistor T3. In case that the scan signal GW is provided to the gate electrode of the third transistor T3, the third transistor T3may be turned on, and a data voltage Vdata may be applied to the gate electrode of the driving transistor DT.

The fourth transistor T4may be connected between the terminal of the first power source ELVDD and the driving transistor DT. The emission control signal EM2may be provided to a gate electrode of the fourth transistor T4. The fourth transistor T4may be an emission control transistor. For example, in case that the emission control signal EM2is provided to the gate electrode of the fourth transistor T4, the fourth transistor T4may be turned on, and the driving current may flow from the first power source ELVDD to the light emitting element LD through the driving transistor DT. The light emitting element LD may emit light based on the driving current flowing through the light emitting element LD. An emission period of the light emitting element LD may be determined corresponding to a turn-on period of the fourth transistor T4.

The storage capacitor Cst may be connected between the first node N1and the second node N2. The storage capacitor Cst may store a voltage corresponding to a voltage difference between the gate electrode of the driving transistor DT and a source electrode of the driving transistor DT.

The hold capacitor Chold may be connected between the terminal of the first power source ELVDD and the second node N2. The hold capacitor Chold may stabilize a voltage of the second node N2.

FIGS.3A and3Bare schematic graphs illustrating an operation of the pixel ofFIG.2.

Referring toFIG.3A, in case that the display device displays an image, one frame period1FP corresponding to one image frame may include a non-emission period NEP and an emission period EP. The non-emission period NEP may include a first initialization period P1, a compensation period P2, a data writing period P3, and a second initialization period P4.

Referring toFIG.3A, in an embodiment, in the first initialization period P1, the gate electrode of the driving transistor DT and the anode electrode of the light emitting element LD may be initialized. At a time point t1, the first transistor T1may be turned on as the first initialization control signal GR is provided to the gate electrode of the first transistor T1. As the first transistor T1is turned on, the reference voltage Vref may be applied from the reference power source to the gate electrode of the driving transistor DT. At a time point t2, the second transistor T2may be turned on as the second initialization control signal GI is provided to the gate electrode of the second transistor T2. As the second transistor T2is turned on, the initialization voltage Vint may be applied from the initialization power source to the anode electrode of the light emitting element LD. At a time point t3, the second transistor T2may be turned off.

In the compensation period P2, a threshold voltage Vth of the driving transistor DT may be compensated. At a time point t4, the fourth transistor T4may be turned on as the emission control signal EM2is provided to the gate electrode of the fourth transistor T4. As the fourth transistor T4is turned on, a current may flow from the first power source ELVDD to the second node N2through the driving transistor DT. A voltage Vref−Vth corresponding to a difference between the reference voltage Vref applied to the gate electrode of the driving transistor DT and the threshold voltage Vth of the driving transistor DT may be applied to the second node N2by source follow. At a time point t5, the fourth transistor T4may be turned off, and at a time point t6, the first transistor T1may be turned off.

In the data writing period P3, the data voltage Vdata may be applied to the gate electrode of the driving transistor DT. At a time point t7, the third transistor T3may be turned on as the scan signal GW is provided to the gate electrode of the third transistor. As the third transistor T3is turned on, the data voltage Vdata may be applied to the gate electrode of the driving transistor DT. A phenomenon in which the data voltage Vdata applied to the first node N1affects the voltage of the second node N2may be minimized by the hold capacitor Chold connected between the terminal of the first power source ELVDD and the second node N2. The third transistor T3may be turned off at a time point t8.

In the second initialization period P4, the anode electrode of the light emitting element LD may be initialized. At a time point t9, the second transistor T2may be turned on as the second initialization signal GI is provided to the gate electrode of the second transistor T2. As the second transistor T2is turned on, the initialization voltage Vint may be applied to the anode electrode of the light emitting element LD. In an embodiment, the second initialization period P4may be omitted.

During the emission period EP, the light emitting element LD may emit light under the control of the fourth transistor T4. At a time point t11, the fourth transistor T4may be turned on as the emission control signal EM2is provided to the gate electrode of the fourth transistor T4. As the fourth transistor T4is turned on, the driving current may flow from the first power source ELVDD to the light emitting element LD through the driving transistor DT. Accordingly, the light emitting element LD may emit light. The fourth transistor T4may be turned off at a time point t12.

In case that the frame driving shown inFIG.3Ais repeated, a relatively long non-emission period NEP may be included within one frame period1FP, and flicker may be visually recognized by a user. To reduce the flicker, as shown inFIG.3B, control signals EM2, GI, GR, and GW may be provided to the pixel PXij so that multiple emission cycles Cycle1, Cycle2, Cycle3, and Cycle4are included in one frame period1FP. The emission cycles Cycle1, Cycle2, Cycle3, and Cycle4may include a first emission cycle Cycle1, a second emission cycle Cycle2, a third emission cycle Cycle3, and a fourth emission cycle Cycle4.

Referring toFIG.3B, one frame period1FP may include the emission cycles Cycle1, Cycle2, Cycle3, and Cycle4, and each of the emission cycles Cycle1, Cycle2, Cycle3, and Cycle4may include an emission period (see, e.g., EP ofFIG.3A) in which a light emitting element LD included in a pixel PXij emits light and a non-emission period (see, e.g., NEP ofFIG.3A) in which a light emitting element LD included in a pixel PXij does not emit light. In second to fourth emission cycles Cycle2, Cycle3, and Cycle4, the light emitting element LD may emit light in case that the emission control signal EM2is at a high level and may not emit light in case that the emission control signal EM2is at a low level.

In an embodiment, in the first emission cycle Cycle1, initialization of the gate electrode of the driving transistor DT and the anode electrode of the light emitting element LD, threshold voltage Vth compensation of the driving transistor DT, and data writing may be performed. In the second to fourth emission cycles Cycle2, Cycle3, and Cycle4, initialization of the gate electrode of the driving transistor DT and data writing may not be performed. Within one frame period1FP, the emission cycles Cycle1, Cycle2, Cycle3, and Cycle4may have a same length.

As described above, since non-emission periods NEP are periodically repeated within one frame period1FP, a luminance difference between frames is reduced, thereby reducing the flicker.

FIG.3Bshows an embodiment in which one frame period1FP has four emission cycles Cycle1, Cycle2, Cycle3, and Cycle4, but the disclosure is not limited thereto. For example, one frame period1FP may include two or eight emission cycles, depending on design and/or conditions.

FIG.4Ais a schematic diagram of an equivalent circuit of a pixel illustrating a voltage drop at a source node of a driving transistor due to kick-back.FIG.4Bis a schematic graph illustrating a voltage drop at a source node of a driving transistor due to kick-back.

Referring toFIG.4A, the pixel PXij may include a parasitic capacitor Cp between the second node N2and the gate electrode of the fourth transistor T4to which the emission control signal EM2is provided. The second node N2and a source node of the driving transistor DT may be the same. As the emission control signal EM2transitions from a high level to a low level, the voltage of the second node N2may drop due to kick-back. A degree to which the voltage of the second node N2decreases due to kick-back may vary depending on the position of the pixel PXij in a display panel. For example, as the position of the pixel PXij in the display panel is farther from a stage circuit (for example, the compensation driver170or the emission driver180ofFIG.1) from which the emission control signal EM2is provided, a voltage drop at the second node N2due to kick-back may increase due to a resistance-capacitance delay (RC delay).

Referring toFIG.4B, in the second to fourth emission cycles Cycle2, Cycle3, and Cycle4among the emission cycles Cycle1, Cycle2, Cycle3, and Cycle4included in one frame period1FP, the voltage drop at the second node N2due to kick-back Kick-back may occur. In the compensation period included in each of the second to fourth emission cycles Cycle2, Cycle3, and Cycle4, the voltage drop at the second node N2due to kick-back Kick-back may occur at time points a1, a2, and a3at which the emission control signal EM2falls to the low level.

The pixel unit110ofFIG.1may include multiple pixel rows (e.g., i pixel rows, where i may be a natural number) including multiple pixels PXij, and the emission control signal EM2may be sequentially provided to the pixel rows in a compensation operation. The degree of voltage drop at the second node N2due to kick-back may be different for each of the pixels PXij included in one pixel row. Accordingly, unintended stains such as mura may be visually recognized from the display panel.

FIG.5is a schematic diagram of an equivalent circuit of a pixel according to an embodiment.

Referring toFIGS.1and5, the pixel PXij may include a fourth transistor T4and a fifth transistor T5connected between the terminal of the first power source ELVDD and the driving transistor DT. The compensation control signal EM1may be provided to a gate electrode of the fourth transistor T4from the compensation driver170. The emission control signal EM2may be provided to a gate electrode of the fifth transistor T5from the emission driver180.

The fourth transistor T4may be a transistor for controlling a compensation operation for compensating the threshold voltage Vth of the driving transistor DT. In the compensation period, in case that the compensation control signal EM1is provided to the gate electrode of the fourth transistor T4, the fourth transistor T4may be turned on. Accordingly, a voltage corresponding to the threshold voltage Vth of the driving transistor DT may be applied to the storage capacitor Cst.

The fifth transistor T5may be a transistor for controlling a light emitting operation of the light emitting element LD. In the emission period (see, e.g., EP ofFIG.6A), in case that the emission control signal EM2is provided to the gate electrode of the fifth transistor T5, the fifth transistor T5may be turned on, and the driving current may flow from the first power source ELVDD to the light emitting element LD through the driving transistor DT. The light emitting element LD may emit light based on the driving current flowing through the light emitting element LD. The emission period of the light emitting element LD may be determined corresponding to a turn-on period of the fifth transistor T5.

FIGS.6A and6Bare schematic graphs illustrating an operation of a pixel according to an embodiment.

Referring toFIG.6A, one frame period1FP corresponding to one image frame may include a non-emission period NEP and an emission period EP. The non-emission period NEP may include a first initialization period P1′, a compensation period P2′, a data writing period P3′, and a second initialization period P4′.

In an embodiment, in the first initialization period P1′, the gate electrode of the driving transistor DT and the anode electrode of the light emitting element LD may be initialized. At a time point t1′, the first transistor T1may be turned on as the first initialization control signal GR is provided to the gate electrode of the first transistor T1. As the first transistor T1is turned on, the reference voltage Vref may be applied from the reference power source to the gate electrode of the driving transistor DT. At a time point t2′, the second transistor T2may be turned on as the second initialization control signal GI is provided to the gate electrode of the second transistor T2. As the second transistor T2is turned on, the initialization voltage Vint may be applied from the initialization power source to the anode electrode of the light emitting element LD. At a time point t3′, the second transistor T2may be turned off.

In the compensation period P2′, the threshold voltage Vth of the driving transistor DT may be compensated. At a time point t4′, the fourth transistor T4may be turned on as the compensation control signal EM1is provided to the gate electrode of the fourth transistor T4. As the fourth transistor T4is turned on, a voltage Vref-Vth corresponding to a difference between the reference voltage Vref applied to the gate electrode of the driving transistor DT and the threshold voltage Vth of the driving transistor DT may be applied to the second node N2by the source follow. At a time point t5′, the fourth transistor T4may be turned off, and at a time point t6, the first transistor T1may be turned off.

In the data writing period P3′, the data voltage Vdata may be applied to the gate electrode of the driving transistor DT. At a time point t7′, the third transistor T3may be turned on as the scan signal GW is provided to the gate electrode of the third transistor T3. As the third transistor T3is turned on, the data voltage Vdata may be applied to the gate electrode of the driving transistor DT. A phenomenon in which the data voltage Vdata applied to the first node N1affects the voltage of the second node N2may be minimized by the hold capacitor Chold connected between the terminal of the first power source ELVDD and the second node N2. The third transistor T3may be turned off at a time point t8′.

In the second initialization period P4′, the anode electrode of the light emitting element LD may be initialized. At a time point t9′, the second transistor T2may be turned on as the second initialization signal GI is provided to the gate electrode of the second transistor T2. As the second transistor T2is turned on, the initialization voltage Vint may be applied to the anode electrode of the light emitting element LD. In an embodiment, the second initialization period P2′ may be omitted.

During the emission period EP, the light emitting element LD may emit light under the control of the fifth transistor T5. At a time point t11′, the fifth transistor T5may be turned on as the emission control signal EM2is provided to the gate electrode of the fifth transistor T5. As the fifth transistor T5is turned on, the driving current may flow from the first power source ELVDD to the light emitting element LD through the driving transistor DT. Accordingly, the light emitting element LD may emit light. The fifth transistor T5may be turned off at a time point t12′.

Unlike the description with reference toFIGS.2and3A, in the pixel PXij shown inFIG.5, an operation of compensating the threshold voltage Vth of the driving transistor DT and an operation of emitting light from the light emitting element LD may be controlled by different transistors. For example, the operation of compensating the threshold voltage Vth of the driving transistor DT may be controlled by applying the compensation control signal EM1to the fourth transistor T4in the compensation period P2′. For example, the operation of emitting light from the light emitting element LD may be controlled by applying the emission control signal EM2to the fifth transistor T5in the emission period EP.

Referring toFIG.6B, one frame period1FP may include multiple emission cycles Cycle1, Cycle2, Cycle3, and Cycle4, and each of the emission cycles Cycle1, Cycle2, Cycle3, and Cycle4may include an emission period (see, e.g., EP ofFIG.6A) in which a light emitting element LD included in a pixel PXij emits light and a non-emission period (see, e.g., NEP ofFIG.6A) in which a light emitting element LP included in a pixel PXij does not emit light. In second to fourth emission cycles Cycle2, Cycle3, and Cycle4, the light emitting element LD may emit light in case that the emission control signal EM2is at a high level and may not emit light in case that the emission control signal EM2is at a low level.

In an embodiment, in a first emission cycle Cycle1, initialization of the gate electrode of the driving transistor DT and the anode electrode of the light emitting element LD, threshold voltage Vth compensation of the driving transistor DT, data writing, and light emitting from the light emitting element LD may be performed. In the second to fourth emission cycles Cycle2, Cycle3, and Cycle4, initialization of the gate electrode of the driving transistor DT, threshold voltage Vth compensation of the driving transistor DT, and data writing may not be performed. For example, in one frame period1FP, only the initialization of the anode electrode of the light emitting element LD and the light emitting from the light emitting element LD may be performed in the emission cycles Cycle2, Cycle3, and Cycle4other than the first emission cycle Cycle1.

Unlike the pixel PXij shown inFIG.2, in the pixel PXij shown inFIG.5, an operation of compensating the threshold voltage Vth of the driving transistor DT and an operation of emitting light from the light emitting element LD may be independently performed by compensation control signal EM1and emission control signal EM2output from separate emission drivers (see, e.g., the compensation driver170and the emission driver180ofFIG.1) to gate electrodes of the fourth and fifth transistors T4and T5. Accordingly, the operation of compensating the threshold voltage Vth of the driving transistor DT may be performed only in the first emission cycle Cycle1among the emission cycles Cycle1, Cycle2, Cycle3, and Cycle4.

In case that the operation of compensating the threshold voltage Vth is performed only in the first emission cycle Cycle1, the voltage drop at the second node N2due to kick-back Kick-back as described with reference toFIG.4Bmay not occur in the emission cycles Cycle2, Cycle3, and Cycle4other than the first emission cycle Cycle1. Therefore, a phenomenon in which stains, such as mura, are visually recognized due to a deviation of voltage drop between second nodes N2of the pixels PXij, which may occur due to kick-back Kick-back, may be improved.

In the pixel PXij of the display device according to the embodiment of the disclosure, an operation of compensating a threshold voltage Vth and an operation of emitting light from a light emitting element LD may be controlled by different transistors included in the pixel PXij. Accordingly, a mura phenomenon that may occur in a display panel due to kick-back of an emission control signal provided to the pixel PXij in the operation of compensating the threshold voltage Vth may be improved.

The above description is an example of technical features of the disclosure, and those skilled in the art to which the disclosure pertains will be able to make various modifications and variations. Therefore, the embodiments of the disclosure described above may be implemented separately or in combination with each other.

Therefore, the embodiments disclosed in the disclosure are not intended to limit the technical spirit of the disclosure, but to describe the technical spirit of the disclosure, and the scope of the technical spirit of the disclosure is not limited by these embodiments. The protection scope of the disclosure should be interpreted by the following claims, and it should be interpreted that all technical spirits within the equivalent scope are included in the scope of the disclosure.