Patent ID: 12193168

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

FIG.1AthroughFIG.1Lare schematic cross-sectional views of structures produced at various stages of a manufacturing method of a semiconductor device10(shown inFIG.1L) according to some embodiments of the present disclosure. Referring toFIG.1A, a conductive plate100(or metal plate) is provided. In some embodiments, a material of the conductive plate100is selected from the group consisting of nickel-iron alloy 42 (alloy containing 42% nickel and 58% iron; 42Ni-58Fe), nickel-iron alloy 52 (alloy containing 50.5% nickel and 48.5% iron; 50.5Ni-48.5Fe) and Kovar (nickel-cobalt ferrous alloy containing 29% nickel, 17% cobalt and 54% iron; 29Ni-17Co-54Fe). In certain embodiments, a lower coefficient of thermal expansion (CTE) of the conductive plate100is achieved by using nickel-iron alloy 42 as a material of the conductive plate100. In certain embodiments, a thickness T1of the conductive plate100is in a range from 25 μm to 600 μm. However, the disclosure is not limited thereto, and the thickness of the conductive plate100may be adjusted based on product requirements.

Referring toFIG.1AandFIG.1B, the conductive plate100is patterned to form ducts D. In some embodiments, the ducts D pass through the patterned conductive plate100from one side to the opposite side. That is, the ducts D may extend from an upper surface100uof the patterned conductive plate100to an opposite bottom surface100b. The ducts D may have a first end opening on the upper surface100uof the patterned conductive plate100and a second end opening on the bottom surface100bof the patterned conductive plate100, crossing the patterned conductive plate100for its entire thickness T1. In some embodiments, the opposite first and second ends of the ducts D are vertically aligned (i.e., are aligned along a thickness direction of the conductive plate100). In certain embodiments, a mechanical drilling or punching process is performed to open the ducts D. In certain embodiments, a chemical etching (e.g., using FeCl3) process is performed to form the ducts D. In some embodiments, the ducts D are formed in an array arrangement on the patterned conductive plate100. That is, adjacent ducts D may open on the patterned conductive plate100keeping a regular distance along one or more directions. In some alternative embodiments, the distance of adjacent ducts D may vary based on actual design requirements. In some embodiments, regions of the same patterned conductive plate100may present different arrangements of the ducts D or distances between adjacent ducts D. For example, in a first region (not shown) of a patterned conductive plate100the ducts D may be aligned along a first direction and misaligned along a second direction perpendicular to the first direction, whilst in a second region (not shown) of the same patterned conductive plate100the ducts D may be aligned along both of the first direction and the second direction. The distributions or the shape of the ducts D may be optimized to release mechanical stresses incurred during subsequent manufacturing steps. Furthermore, the present disclosure poses no limitation to the number of ducts D formed on the patterned conductive plate100, and said number may be adjusted based on product requirements.

Referring toFIG.1C, a core dielectric layer200is provided which wraps the patterned conductive plate100. In some embodiments, the core dielectric layer200extends over the upper surface100uof the patterned conductive plate100and fills the ducts D. In some embodiments, the core dielectric layer200further covers an outer edge100eof the patterned conductive plate100. In some embodiments, the outer edge100econnects the upper surface100uand the bottom surface100bof the patterned conductive plate100. In some embodiments, the core dielectric layer200exposes the bottom surface100bof the patterned conductive plate100. A thickness T2of the core dielectric layer200may be larger than a thickness T1of the patterned conductive plate100. In some embodiments, a ratio between the thickness T1of the patterned conductive plate100over the thickness T2of the core dielectric layer200is in the range from 5% to 95%. A material of the core dielectric layer200is not particularly limited, and may include molding compound, Ajinomoto build-up film, polymeric materials (e.g., polyimide, polyester, benzocyclobutene (BCB), polybenzoxazole, or the like), prepreg, resin coated copper (RCC), photo image dielectric (PID), phenolic paper, phenolic cotton paper, woven fiberglass cloth, impregnated woven fiberglass cloth, or a combination thereof. In some embodiments, the core dielectric layer200is laminated over the patterned conductive plate100. In some alternative embodiments, the core dielectric layer200is formed by molding (e.g., compression molding) or other suitable techniques. In some embodiments, the patterned conductive plate100is subjected to a micro-roughening treatment before providing the core dielectric layer200, to enhance adhesion and decrease the occurrence of delamination.

In some embodiments, referring toFIG.1D, through holes TH are formed in the core dielectric layer200. In some embodiments, the through holes TH extend from the upper surface200uto the bottom surface200bof the core dielectric layer200. In some embodiments, the through holes TH are located within the ducts D. The through holes TH may run parallel to the ducts D along a vertical direction (thickness direction). The core dielectric layer200may partially fill the ducts D to define the through holes TH. That is, upon formation of the through holes TH in the core dielectric layer200, no additional portions of the patterned conductive plate100are exposed. In some embodiments, the through holes TH may be formed by removing portions of the core dielectric layer200by mechanical or laser drilling, etching, or other suitable removal techniques, for example. A desmear treatment may be performed using plasma to remove residues remaining in the through holes TH. In some embodiments, the surface of the core dielectric layer200exposed within the through holes TH is subjected to a micro-roughening treatment to promote deposition of conductive material during subsequent process steps.

In some embodiments, referring toFIG.1E, a metallization layer300may be provided over portions of the core dielectric layer200. The metallization layer300may include via portions310disposed in the through holes TH in a thickness direction of the core dielectric layer200, and pad portions320disposed in a contiguous manner with (attached to) the via portions310over the upper and bottom surfaces200uand200bof the core dielectric layer200. The core dielectric layer200may separate the metallization layer300from the patterned conductive plate100. In some embodiments, the metallization layer300may further include trace portions325as connecting tracks. In some embodiments, the trace portions325define a metallization pattern on the core dielectric layer200. In some embodiments, the metallization layer300may partially wrap the core dielectric layer200and extend towards the bottom surface100bof the patterned conductive plate100without physically contacting the patterned conductive plate100. That is, the metallization layer300may include openings O1exposing the bottom surface100bof the patterned conductive plate100and portions of the core dielectric layer200. In some embodiments, the via portions310, the pad portions320, and the trace portions325of the metallization layer300are formed by plating the through holes TH with a conductive material to a predetermined thickness (e.g., plating copper through electroless plating/electrochemical plating). In some embodiments, the via portions310, the pad portions320and the trace portions325of the metallization layer300are formed by the same plating process. In some embodiments, the conductive material includes copper, aluminum, platinum, nickel, titanium, tantalum, chromium, gold, silver, tungsten, a combination thereof, or the like. Throughout the description, the term “copper” is intended to include substantially pure elemental copper, copper containing unavoidable impurities, and copper alloys containing elements such as tantalum, indium, tin, zinc, manganese, chromium, titanium, germanium, strontium, platinum, magnesium, aluminum or zirconium, etc. During the formation of the metallization layer300an auxiliary mask (not shown) may be used to prevent shortening between the metallization layer300and the patterned conductive plate100. In some embodiments, the auxiliary mask includes a photoresist layer.

Referring toFIG.1F, a via filler400may be disposed to fill the spaces surrounded by the via portions310of the metallization layer300formed in the through holes TH, and via caps330may be formed over the via filler400. In some embodiments, via caps330disposed at both ends of a through hole TH and the via portions310lining the side surface of the same through hole TH may enclose the via filler400disposed in the same through hole TH. In some embodiments, the via filler400includes an insulating material, such as solder mask material, via plugging material, epoxy resins, or the like. In some alternative embodiments, the via filler400includes a conductive material. In certain embodiments, the via filler400may be formed by a roller coating process, or a screen printing process. In some embodiments, the material of the via filler400may be the same material used for the metallization layer300. In some embodiments the via caps330are formed after the via filler400, for example during a plating step. Formation of the via filler400and the via caps330completes the formation of a plated through via PTH. In some embodiments, the via caps330merge with the pad portions320which are formed during a different plating step. As such, in some embodiments the metallization layer300is formed via two (or more) plating steps. In one embodiment, a planarization process may be included to flatten the metallic features. Formation of the metallization layer300completes a core layer CL of a circuit board according to some embodiments of the present disclosure. In some embodiments, the core layer CL is considered to include the patterned conductive plate100, the core dielectric layer200, and the metallization layer300. In some embodiments, the core layer CL further includes the via filler400.

In some embodiments, referring toFIG.1G, an upper dielectric material layer510aand a lower dielectric material layer610aare respectively formed over opposite surfaces of the core layer CL. In some embodiments, the upper dielectric material layer510aextends over the entire upper surface200uof the core dielectric layer200, physically contacting the core dielectric layer200and the metallization layer300. In some embodiments, at least the core dielectric layer200is interposed between the patterned conductive plate100and the upper dielectric material layer510a. Portions of the metallization layer300may also be disposed between the patterned conductive plate100and the upper dielectric material layer510a. In some embodiments, because the bottom surface100bof the patterned conductive plate100is exposed by the core dielectric layer200, the lower dielectric material layer610aphysically contacts the patterned conductive layer100, the core dielectric layer200and the metallization layer300. In some embodiments, the lower dielectric material layer610aelectrically insulate the patterned conductive plate100from the metallization layer300. In some embodiments, the upper dielectric material layer510aand the lower dielectric material layer610ainclude the same material. In some alternative embodiments, the upper dielectric material layer510aand the lower dielectric material layer610ainclude different materials. In some embodiments, materials of the upper dielectric material layer510aand the lower dielectric material layer610ainclude polyimide, epoxy resin, acrylic resin, phenol resin, benzocyclobutene (BCB), polybenzooxazole (PBO), or any other suitable polymer-based dielectric material. The dielectric material layers510aand610amay be formed by suitable fabrication techniques such as spin-on coating, chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), or the like. In some embodiments, the material of the lower dielectric material layer610ais different from the material of the core dielectric layer200.

Referring toFIG.1H, in some embodiments a temporary carrier TC is provided on a side of the lower dielectric material layer610afurther away from the core layer CL. That is, the lower dielectric material layer610amay be sandwiched between the core layer CL and the temporary carrier TC. In some embodiments, the temporary carrier TC is a glass substrate, a metal plate, a plastic supporting board or the like, but other suitable substrate materials may be used as long as the materials are able to withstand the subsequent steps of the process. In some embodiments, a de-bonding layer (not shown) is provided on the temporary carrier TC to facilitate peeling the temporary carrier TC away from the manufacturing intermediate when required by the manufacturing process. In some embodiments, the de-bonding layer includes a light-to-heat conversion (LTHC) release layer.

Referring toFIG.1I, in some embodiments, the upper dielectric material layer510a(shown inFIG.1H) is patterned to form an upper dielectric layer510including openings O2exposing portions of the metallization layer300. Thereafter, conductive vias520may be formed in the openings O2electrically contacting the metallization layer300. In some embodiments, multiple dielectric layers511,512,513amay be stacked over the upper dielectric layer510and the conductive vias520, including embedded conductive layers531,532electrically interconnected by conductive vias521,522. The conductive layers531and532may include multiple conductive patterns respectively formed over the dielectric layers511and512. In some embodiments, the conductive vias520,521,522establish electrical connection between the conductive layers531,532and the metallization layer300. In some embodiments, the topmost dielectric layer513acovers the conductive layer532disposed on the underlying dielectric layer512and the conductive vias522embedded in the dielectric layer512. In some embodiments, materials of the conductive layers531and532and of the conductive vias520,521,522include aluminum, titanium, copper, nickel, tungsten, alloys or combination thereof. The conductive layers531,532and the conductive vias520,521,522may be formed by, for example, electroplating, deposition, and/or photolithography and etching. In some embodiments, a material and a manufacturing process of the dielectric layers511,512,513ais similar to what previously described for the upper dielectric layer510, and a description thereof is omitted herein. It should be noted that the number of the conductive layers531,532, the number of conductive vias520,521,522, and the number of the dielectric layers510,511,512,513aillustrated inFIG.1Iare merely for illustrative purposes, and the disclosure is not limited thereto. In some alternative embodiments, more or fewer conductive layers, dielectric layers and conductive vias are formed depending on the circuit design. In these embodiments, the conductive layers are sandwiched between adjacent dielectric layers and are interconnected with one another by the conductive vias.

In some embodiments, referring toFIG.1IandFIG.1J, the temporary carrier TC is removed. In some embodiments, if the de-bonding layer (e.g., a LTHC release layer) is included, the de-bonding layer is irradiated with a UV laser so that the carrier TC and the de-bonding layer are easily peeled off from the lower dielectric material layer610a. Nevertheless, the de-bonding process is not limited thereto, and other suitable de-bonding methods may be used in some alternative embodiments. With the removal of the temporary carrier TC, the lower dielectric material layer610abecomes exposed and available for further processing.

In some embodiments, referring toFIG.1JandFIG.1K, the topmost dielectric layer513amay be patterned to form a topmost dielectric layer513exposing the underlying conductive vias522and portions of the conductive layer532. A conductive layer533may be formed over the topmost dielectric layer513. The conductive layer533may be connected to the underlying conductive layers531,532and the underlying conductive vias520,521,522by conductive vias523wrapped by the topmost dielectric layer513. Similarly, the lower dielectric material layer610a(shown inFIG.1J) may be patterned to form a lower dielectric layer610exposing the metallization layer300. Conductive vias620may be embedded in the lower dielectric layer610to contact the metallization layer300, and establish electrical connection between the metallization layer300and a conductive layer630formed over the lower dielectric layer610. A material and a formation method of the conductive layer533and the conductive vias523may be selected from similar options to the ones described above for the conductive layers531,532and the conductive vias520,521,522, and a description thereof is omitted herein. Patterned mask layers540and640may be optionally formed over the outermost dielectric layers513and610, respectively. For example, the patterned mask layer540includes openings O3exposing at least a portion of the outermost conductive layer533and, optionally, of the outermost conductive vias523. In some embodiments, the patterned mask layer640includes openings O4exposing portions of the conductive layer630and the conductive vias620. In some embodiments, a material of the patterned mask layers540,640include polymeric materials, or other suitable insulating materials. In some embodiments, the material of the patterned mask layers540,640includes silica, barium sulfate, epoxy resin, a combination thereof, or the like. The materials of the patterned mask layers540,640serving as solder masks may be selected to withstand the temperatures of molten conductive materials (e.g., solders, metals, and/or metal alloys) to be subsequently disposed within the openings O3, O4. In some embodiments, the patterned mask layer540includes different materials than the patterned mask layer640. In some alternative embodiments, the patterned mask layers540,640include the same material. The patterned mask layers540,640may be formed by lamination, printing (e.g., screen printing), spin-coating or the like. Curing steps, patterning steps, or both may be required according to the materials and method chosen for the fabrication of the patterned mask layers540,640. In some embodiments, the lower dielectric layer610, the conductive vias620and the conductive layer630may be considered a lower build-up stack600. In some embodiments, the lower build-up stack600may also include the patterned mask layer640. The formation of the outermost conductive layers533,630or, if included, of the patterned mask layers540,640may complete a circuit board700according to some embodiments of the disclosure.

In some embodiments, the circuit board700includes a core layer CL sandwiched between a build-up stack500and the lower dielectric layer610. In some embodiments, the build-up stack500includes the stacked upper dielectric layers510,511,512,513, the conductive layers531,532,533sandwiched between pairs of adjacent dielectric layers511,512,513, and the conductive vias520,521,522,523electrically connecting the conductive layers531,532,533among themselves and with the metallization layer300of the core layer CL In some embodiments, the upper build-up stack500further includes the patterned mask layer540disposed over the topmost dielectric layer513. In some embodiments, the lower dielectric layer610may act as a passivation layer for the metallization layer300exposed by the core layer CL, with the patterned mask layer640(if included) acting as a solder mask. The conductive layer630and the conductive vias620provide electrical connection to the metallization layer300.

Referring toFIG.1L, in some embodiments at least one semiconductor package800is connected to the printed circuit board700to form a semiconductor device10. For example, the semiconductor package800may be connected to the upper side of the printed circuit board700where the upper build-up stack500is formed. The disclosure is not limited neither by the type nor the number of semiconductor packages800connected to the printed circuit board700. In the drawings of the present disclosure, a Chip-on-Wafer (CoW) package is shown as the semiconductor package800for purpose of illustration. However, it will be apparent that other types of semiconductor packages may be used to produce semiconductor devices including the printed circuit boards disclosed herein, and all these semiconductor devices are intended to fall within the scope of the present description and of the attached claims. For example, System-On-Chip, (SoC) Integrated-Fan-Out (InFO) packages, Chip-On-Wafer-On-Substrate (CoWoS), three-dimensional integrated circuit (3DIC), Package-on-Package (PoP) systems etc. may all be used as the semiconductor packages800, alone or in combination.

The non-limiting, exemplary package800shown inFIG.1Kmay include semiconductor dies810,820,830, bonded to an interposer840and encapsulated by an encapsulant850. In some embodiments, the semiconductor dies810,820,830include semiconductor substrates having active components (e.g., transistors or the like) and optionally passive components (e.g., resistors, capacitors, inductors, or the like) formed therein. The semiconductor dies810,820,830may be connected to the interposer840via connectors812,822,832. In some embodiments, the connectors812,822,832include copper, copper alloys, or other conductive materials, and may be formed by deposition, plating, or other suitable techniques. In some embodiments, the connectors812,822,832are prefabricated structures attached over the contact pads of the semiconductor dies810,820,830. In some embodiments, the connectors812,814,816include solder balls, ball grid array (BGA) connectors, metal pillars, controlled collapse chip connection (C4) bumps, micro bumps, bumps formed via electroless nickel-electroless palladium-immersion gold technique (ENEPIG), a combination thereof (e. g, a metal pillar with a solder ball attached), or the like. In some embodiments, an underfill may be formed to protect the connectors812,814,816from mechanical stresses. Each of the semiconductor dies810,820,830may independently be or include a logic die, such as a central processing unit (CPU) die, a graphic processing unit (GPU) die, a micro control unit (MCU) die, an input-output (I/O) die, a baseband (BB) die, or an application processor (AP) die. In some embodiments, one or more of the semiconductor dies810,820,830include a memory die such as a high bandwidth memory die. In some embodiments, the semiconductor dies810,820,830may be the same type of dies or perform the same functions. In some embodiments, the semiconductor dies810,820,830may be different types of dies or perform different functions. In some embodiments, the semiconductor die810includes a logic die, and the semiconductor dies820and830include memory dies. In some embodiments, the semiconductor dies820and830include memory stacks, in which multiple electrically connected chips are stacked on top of each other. Generally speaking, the semiconductor package800may include a wide variety of devices, such as processors, resistors, capacitors, transistors, diodes, fuse devices, memories, discrete electronic devices, power coupling devices or power systems, thermal dissipation devices, combinations thereof, or the like formed therein. The interposer840may include conductive vias842formed therein to provide vertical electrical connection, allowing the semiconductor dies810,820,830to be connected to external devices via the circuit board700. Some of the conductive vias842may electrically connect the semiconductor dies810,820,830.

In some embodiments, the semiconductor package800may be connected to the circuit board700via connectors910,920. In some embodiments, connectors910,920may be selected from similar options as previously described for the connectors812,814,816. In some embodiments, the connectors910,920include metals such as copper, nickel, or the like. In some embodiments, the connectors910are formed on the semiconductor package800and the connectors920are formed on the circuit board700(for example, in the openings O3of the upper build-up stack500). The connectors910on the semiconductor package800may be jointed to the connectors920to provide electrical connection between the semiconductor package800and the circuit board700. For example, solder paste (not shown) may be applied on either or both of the connectors910,920before placing the semiconductor package800over the circuit board700, and the connectors910,920may be soldered together during a reflow process. In some embodiments, under-bump metallurgies (not shown) may be formed between the connectors910and the interposer840and between the connectors920and the portions of the conductive layer533exposed by the openings O3. According to some embodiments, connectors930may be formed in the openings O4of the patterned mask layer640to allow integration of the semiconductor device10within larger systems (not shown).

In some embodiments, as shown inFIG.1L, a build-up stack500is built only on one side of the circuit board700. In some embodiments, inclusion of only the upper build-up stack500on the circuit board700(i.e., without a corresponding build-up stack on an opposite side) would lead to serious warpage issues were the patterned conductive plate100not included in the core layer CL of the circuit board700. That is, because the patterned conductive plate100is included in the circuit board700, the overall mechanical stability may be increased, rendering possible to have a build-up stack500on one side only of the circuit board700, with external connectors930disposed on an opposite side of the circuit board700over a single dielectric layer610and an optional patterned mask layer640. In some embodiments, the patterned conductive plate100is embedded in a single core dielectric layer200. The bottom surface100bof the patterned conductive plate100may be exposed by the core dielectric layer200and may be in direct contact with the lower dielectric layer610. In some embodiments, when the patterned conductive plate100is embedded in a single core dielectric layer200, the manufacturing process may be simplified in terms of number of steps and materials required, thus lowering the unitary manufacturing cost. In some embodiments, the patterned conductive plate100may help to dissipate the heat generated during the usage of the semiconductor device10, thus increasing the reliability of the semiconductor device10.

FIG.2shows a schematic cross-sectional view of the circuit board700according to some embodiments of the disclosure. The cross-sectional view ofFIG.2is taken in a plane normal to the plane of view illustrated inFIG.1L, lying at the level I-I shown inFIG.1L. In some embodiments, as shown inFIG.2, the distribution of the ducts D varies throughout the patterned conductive plate100, and may be optimized to reduce warpage issues while taking into account the final distribution of the semiconductor devices800(shown inFIG.1L) over the circuit board700. In some embodiments, the ducts D are filled by portions of the core dielectric layer200defining the through holes TH, where the via portion310of the metallization layer300and the via filler400are disposed. The via portion310of the metallization layer300may be disposed in between the via filler400and the core dielectric layer200. In the view ofFIG.2, the core dielectric layer200, the metallization layer300and the via filler400may form a concentric structure disposed within the ducts D. The core dielectric layer200may further extend along the outer edge100eof the patterned conductive plate100.

InFIG.3is shown a cross-sectional view of a semiconductor device20according to some embodiments of the disclosure. The semiconductor device20may include the circuit board710and the semiconductor package800. The semiconductor device20ofFIG.3may be similar to the semiconductor device10ofFIG.1L, and the following description will focus on some of the differences between the two semiconductor devices10and20. The circuit board710included in the semiconductor device20includes the upper build-up stack500disposed between the core layer CL and the semiconductor package800, and a lower build-up stack600disposed between the core layer CL and the connectors930. The lower build-up stack600includes the lower dielectric layer610, the conductive vias620and conductive layer630electrically connected to the metallization layer300and the patterned mask layer640. Furthermore the build-up stack600includes a second dielectric layer611and a second conductive layer631disposed between the lower dielectric layer610and the patterned mask layer640. The second conductive layer631may be disposed between the second dielectric layer611and the patterned mask layer640, and may be electrically connected to the conductive layer630by the conductive vias621. As in the semiconductor device10ofFIG.1L, in the semiconductor device20ofFIG.3, the patterned conductive plate100physically contacts the lower dielectric layer610, but the metallization layer300does not electrically contact the patterned conductive plate100. In some embodiments, the lower build-up stack600includes less dielectric layers610,611, and conductive layers630,631than the upper build-up stack500. However, it should be noted that the number of the conductive layers630,631, the number of conductive vias620,621, and the number of the dielectric layers610,611illustrated inFIG.3are merely for illustrative purposes, and the disclosure is not limited thereto. In some alternative embodiments, more conductive layers, dielectric layers and conductive vias are formed depending on the circuit design. In these embodiments, the conductive layers are sandwiched between adjacent dielectric layers and are interconnected with one another by the conductive vias.

In light of the foregoing, the patterned conductive plate included in the core layer of the circuit boards of the present disclosure may enhance the structural rigidity of the circuit board, thus reducing the possibility of failure because of warpage during subsequent manufacturing processes. In some embodiments, the patterned conductive plate allows a heavily asymmetric distribution of dielectric layers between build-up stacks on opposite sides of the circuit board. In some embodiments, because fewer layers are included in the build-up stacks, the manufacturing costs are reduced and the yields are increased. In some embodiments, the patterned conductive plate may also enhance the thermal dissipation of the circuit board, and provide improved electrical inductance and resistance properties of the core layer. In some embodiments, as the through hole vias establishing double-sided communication between opposite sides of the circuit board may be filled with rigid material (e.g., metal), a further increase in structural stability may also be achieved.

In accordance with some embodiments of the disclosure, a circuit board includes a patterned conductive plate, a core dielectric layer, a metallization layer, a first build-up stack, and a second build-up stack. The patterned conductive plate has channels extending from a top surface of the patterned conductive plate to an opposite bottom surface of the patterned conductive plate. The core dielectric layer extends on and covers the top surface and side surfaces of the patterned conductive plate. The metallization layer extends on the core dielectric layer and within the channels of the patterned conductive plate. The core dielectric layer insulates the metallization layer from the patterned conductive plate. The first build-up stack is disposed on a side of the top surface of the patterned conductive plate and includes conductive layers alternately stacked with dielectric layers. The conductive layers are electrically connected to the metallization layer. The second build-up stack is disposed on a side of the bottom surface of the patterned conductive plate. The second build-up stack includes a bottommost dielectric layer and a bottommost conductive layer. The bottommost dielectric layer covers the bottom surface of the patterned conductive plate. The bottommost conductive layer is disposed on the bottommost dielectric layer and is electrically connected to the metallization layer. The first build-up stack includes more conductive layers and dielectric layers than the second build-up stack.

In accordance with some embodiments of the disclosure, a semiconductor device includes a conductive plate, a core dielectric layer, metallic vias, metal pads, an insulating via filler, via caps, dielectric layers, and conducive layers. The conductive plate has through holes extending from one side of the conductive plate to an opposite side of the conductive plate. The core dielectric layer extends on the one side of the conductive plate and lines the through holes of the conductive plate. The metallic vias are formed on the core dielectric layer within the through holes of the conductive plate. The metal pads are formed on a top surface and a bottom surface of the core dielectric layer, and are integrally formed with the metallic vias. The insulating via filler is disposed on the metallic vias and fills the through holes of the conductive plate. The conductive layers are electrically connected to the metal pads. The via caps, the metallic vias, and the metal pads are electrically insulated from the conductive plate.

In accordance with some embodiments of the disclosure, a circuit board includes a core layer, a lower dielectric layer, a lower conductive layer, an upper dielectric layer, and an upper conductive layer. The core layer includes a patterned conductive plate, a core dielectric layer, and plated through vias. The core dielectric layer covers all surfaces of the patterned conductive plate except for exposing a bottom surface of the patterned conductive plate. The plated through vias extend through the patterned conductive plate and the core dielectric layer, and are electrically insulated from the patterned conductive plate. The lower dielectric layer extends directly on and covers the bottom surface of the patterned conductive plate, and has openings exposing portions of the plated through vias. The lower conductive layer, extends on the lower dielectric layer and contacts the plated through vias in the openings of the lower dielectric layer. The upper dielectric layer extends on the core layer at an opposite side than the lower conductive layer. The upper dielectric layer includes openings exposing the plated through vias. The upper conductive layer extends on the upper dielectric layer and contacts the plated through vias in the openings of the upper dielectric layer. The core dielectric layer and the lower dielectric layer electrically insulate the patterned conductive plate.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.