Patent ID: 12243934

DETAILED DESCRIPTION

The present disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Embodiments disclosed herein are merely examples and are not intended to be limiting. For example, dimensions of elements are for illustration only and should not be construed to limit ranges or values of those dimensions in accordance with the disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. The present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper,” “top,” “bottom” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. The term “horizontal” is defined as a plane parallel to the conventional plane or main surface of a wafer or substrate, regardless of the orientation of the wafer or substrate. The term “vertical” refers to a direction perpendicular to the horizontal as defined above. It will be understood that, although the terms “first,” “second,” “third,” etc may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present disclosure.

Numerous benefits and advantages are achieved by way of the present disclosure over conventional techniques. For example, embodiments provide a raised channel region that provides a large surface area for interactions with a gate electrode. The large contact area of the channel region with the gate electrode enhances electromagnetic field interactions between the gate electrode and the channel region. As the channel region is further reduced, variations of the channel width account for a larger portion of the total width, that can adversely affect the channel mobility and channel resistance. A reduced channel width causes an increase in a threshold voltage of a semiconductor device. Embodiments overcome problems associated with reduced channel widths by providing channel structures including doped two-dimensional (2D) material layers that enhance channel mobility and threshold voltages of a semiconductor device. High design flexibility can be achieved by selecting a suitable number of doped 2D material layers and doping concentration profiles in the channel structures.

FIG.1Ais a perspective view of a portion of a semiconductor device10according to some embodiments.FIG.1Ahas been simplified for the sake of clarity and to better illustrate the concepts of the present subject matter. Additional features may be incorporated into the semiconductor device10, and some of the features described below may be replaced or eliminated for other embodiments of the semiconductor device10. The semiconductor device10is a fin-based semiconductor device, such as a FinFET device, and the concepts of the present disclosure apply equally to other alternatives. Referring toFIG.1A, the semiconductor device10includes a FinFET100formed on a substrate101. Suitable substrate101can be a semiconductor substrate or a non-semiconductor substrate. For example, the substrate101may include a bulk silicon substrate. In some embodiments, the substrate101may include an elementary semiconductor, such as silicon or germanium in a crystalline structure, a compound semiconductor, e.g., silicon germanium, silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide, or combinations thereof. Possible substrate101may also include a semiconductor-on-insulator (SOI) substrate. In an embodiment, the substrate101is a silicon layer of an SOI substrate. The substrate101can include various doped regions depending on design requirements, e.g., n-type wells or p-type wells. The doped regions are doped with p-type dopants, e.g., boron, n-type dopants, e.g., phosphorous or arsenic, or combination thereof. The doped regions may be formed directly on the substrate101, in a P-well structure, in an N-well structure, in a dual-well structure, on a raised structure, or in a raised structure. The substrate101may also include various active regions for forming N-type metal-oxide-semiconductor transistor (NMOS) devices and P-type semiconductor transistor (PMOS) devices.

The substrate101also includes a plurality of isolation regions102to electrically isolate circuit devices, e.g., the FinFET100. In the illustrated embodiment, the isolation regions102includes a shallow trench isolation (STI) structure. The isolation regions102includes any suitable isolation material, such as a semiconductor oxide, a semiconductor nitride, a semiconductor oxynitride, a semiconductor carbide, fluoride-doped silicate glass (FSG), low-k dielectric material, or the like. The isolation regions102may be formed using any suitable deposition process including thermal growth, atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), and other suitable deposition processes.

The FinFET100includes a raised structure (fin structure)103extending over the upper surface101aof the substrate101, an interfacial layer104formed on the raised structure103, and a gate electrode105formed on a portion of the interfacial layer104. In the case where the silicon layer of the SOI substrate is used, the silicon layer is used to form the raised structure. In some embodiments, the raised structure103is made of the same material as the substrate101. In other embodiments, the raised structure (fin structure)103is heteroepitaxially grown and continuously extends from the substrate101. In the example ofFIG.1A, the substrate is a silicon substrate, and the raised structure103is made of silicon. The silicon layer of the raised structure103may be intrinsic, or doped with an n-type impurity or a p-type impurity. InFIG.1A, one raised structure (fin structure) is disposed over the substrate101. However, the number of fin structures is not limited to one. The number of fin structures can be two or more. The raised structure103includes a lower portion103A embedded in the isolation regions102. The lower portion103A is referred to as a well region. The upper portion of the raised structure103that is covered by the gate electrode105is referred to as a channel region.

In the example ofFIG.1A, the interfacial layer104is formed over the entire surface of the raised structure103. In an embodiment, the interfacial layer104may cover a middle portion of the raised structure103, and the gate electrode105is formed on the middle portion of the raised structure103that is covered by the interfacial layer104. In certain embodiments, the interfacial layer104is a gate dielectric layer disposed on the channel region, and the gate electrode is disposed on the gate dielectric layer. The portion of the raised structure not covered by the gate dielectric layer functions as a source and/or drain of the FinFET100. The interfacial layer (gate dielectric layer)104includes a single layer or alternatively a multi-layer structure having one or more dielectric materials, such as a single layer of silicon oxide, silicon nitride, high-k dielectric material, any suitable dielectric material, or a multi-layer of two or more of these materials. Examples of high-k dielectric material includes HfO2, HfSiO, HfSiON, HMO, HfSiO, HfZrO, Pr2O3, zirconium oxide, aluminum oxide, titanium oxide, hafnium dioxide-alumina (HfO2—Al2O3) alloy. The gate electrode105includes one or more layers of any suitable material, such as polysilicon, aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, tantalum nitride, nickel silicide, cobalt silicide, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, metal alloys, and/or combinations thereof. The gate structure can be formed using a gate last process.

The FinFET100includes a pair of opposing source/drain regions106, each of the source/drain regions106includes various doped semiconductor materials, and a channel region107positioned between the source/drain regions106. The flow of carriers (electrons for an n-channel device and holes for a p-channel device) through the channel region107is controlled by a voltage applied to the gate electrode105. In the example shown inFIG.1A, the channel region107is raised above the upper surface101aof the substrate101and in contact with the substrate. The gate electrode105is disposed on three side surfaces of the channel region107. The electromagnetic field interactions between the gate electrode105and the channel region107reduce leakage and short channel effects associated with small semiconductor devices.

In an embodiment, the raised structure103is a portion of the substrate101that extends through the isolation regions102. In an embodiment, the channel region107has an upper surface co-planar with an upper surface of the source/drain regions106. In an embodiment, the channel region107has an upper surface that is lower than an upper surface of the source/drain regions106. In an embodiment, the raised structure103is a separate semiconductor structure formed on the substrate101. In an exemplary embodiment, the substrate101includes silicon, and the raised structure103is formed as a protruding portion of the substrate101. In another exemplary embodiment, the raised structure103includes SiGe.

FIG.1Bis a cross-sectional view of the portion of the semiconductor device10ofFIG.1Ataken along the line A-A.FIG.1Cis a cross-sectional view of the portion of the semiconductor device10ofFIG.1Ataken along the line B-B. As shown inFIGS.1B and1C, the channel region107is disposed between the source/drain region106, the interfacial layer104is disposed on the channel region107, and the gate electrode105is disposed on the interfacial layer104. In an embodiment, the interfacial layer104is formed directly on the raised structure103to any suitable thickness using any suitable process including thermal growth, atomic layer deposition (ALD), chemical vapor deposition (CVD), spin-on deposition and other suitable deposition processes. In an embodiment, the interfacial layer104may also be formed on the upper surface of the substrate and the isolation regions.

FIG.2Ais a perspective view of a portion of a semiconductor device20according to some embodiments. Referring toFIG.2A, the semiconductor device20is similar to the semiconductor device10except that the channel region is suspended over the substrate. Accordingly, description in relation to the elements illustrated inFIG.1Ais applicable to the elements inFIG.2Aas appropriate. The semiconductor device20includes a gate-all-around (GAA) device200that has a raised structure (fin)203extending over the upper surface101aof the substrate101, and a gate stack209formed on a portion of the raised structure203. The GAA device200also includes a channel region207suspended over the substrate and a pair of source/drain regions206disposed on opposite sides of the channel region207. The gate stack209includes one or more gate dielectric layers204and a gate electrode205disposed on the one or more gate dielectric layers (seeFIGS.2B and2C). The one or more gate dielectric layers204include a single layer of silicon oxide, silicon nitride, high-k dielectric material, any suitable dielectric material, or a multi-layer of two or more of these materials. Examples of high-k dielectric material includes HfO2, HfSiO, HfSiON, HMO, HfSiO, HfZrO, Pr2O3, zirconium oxide, aluminum oxide, titanium oxide, hafnium dioxide-alumina (HfO2—Al2O3) alloy. The gate electrode205includes one or more layers of any suitable material, such as polysilicon, aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, tantalum nitride, nickel silicide, cobalt silicide, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, metal alloys, and/or combinations thereof. The gate stack209can be formed using a gate-last process.

The gate stack209surrounds (wraps) the channel region207, i.e., the gate stack209is formed on a top surface, sidewall surfaces, and a bottom surface of the channel region207. Each of the source/drain regions206includes various doped semiconductor materials. The flow of carriers (electrons for an n-channel device and holes for a p-channel device) through the channel region207is controlled by a voltage applied to the gate electrode205of the gate stack209. In the example shown inFIG.2A, the channel region207is raised above the upper surface101aof the substrate101and suspended over the substrate101. In this embodiment, the channel region207is suspended over the substrate101via the source/drain regions206, i.e., the source/drain regions206are formed on (in direct contact with) the substrate101and are coupled to each other through the channel region207, which forms a bridging structure extending along the direction of B-B, and the gate stack209surrounds the channel region207on all four surface sides (top, sidewall, and bottom sides).

FIG.2Bis a cross-sectional view of the portion of the semiconductor device20ofFIG.2Ataken along the line A-A, andFIG.2Cis a cross-sectional view of the portion of the semiconductor device20ofFIG.2Ataken along the line B-B. Referring toFIGS.2B and2C, the channel region207is suspended over the substrate101and forms a bridging structure connecting the source/drain regions206, i.e., the channel region207is suspended over the substrate101and supported by the source/drain regions206. The gate stack including one or more dielectric layers204and a gate electrode205on the one or more dielectric layers204is formed on all sides (top surface, bottom surface, and side surfaces) of the channel region207. In this embodiment, the gate electrode205does not have contact with the substrate101, as indicated by an air gap between the gate stack209and the substrate101. In some other embodiments, the gate stack209can be in contact with the substrate101.

FIG.3Ais a perspective view of a portion of a semiconductor device30according to some embodiments. Referring toFIG.3A, the semiconductor device30is similar to the semiconductor device10except for the differences described herein. Accordingly, description in relation to the elements illustrated inFIG.1Ais applicable to the elements inFIG.3Aas appropriate. The semiconductor device30includes a FinFET300that has a suspending structure303disposed over the upper surface101aof the substrate101. The suspending structure303is supported by a gate structure309formed on a surface portion of the substrate101. The suspending structure303includes a channel region307and a pair of source/drain regions306disposed on opposite sides of the channel region307. The gate structure309includes one or more gate dielectric layers304and a gate electrode305disposed on the one or more gate dielectric layers (seeFIGS.3B and3C). The one or more gate dielectric layers304include a single layer of silicon oxide, silicon nitride, high-k dielectric material, any suitable dielectric material, or a multi-layer of two or more of these materials. Examples of high-k dielectric material includes HfO2, HfSiO, HfSiON, HMO, HfSiO, HfZrO, Pr2O3, zirconium oxide, aluminum oxide, titanium oxide, hafnium dioxide-alumina (HfO2—Al2O3) alloy. The gate electrode305includes one or more layers of any suitable material, such as polysilicon, aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, tantalum nitride, nickel silicide, cobalt silicide, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, metal alloys, and/or combinations thereof. The gate structure309surrounds (wraps) the channel region307, i.e., the gate structure309is formed on a top surface, sidewall surfaces, and a bottom surface of the channel region307. Each of the source/drain regions306includes various doped semiconductor materials. The flow of carriers (electrons for an n-channel device and holes for a p-channel device) through the channel region307is controlled by a voltage applied to the gate electrode305of the gate structure309. In the example shown inFIG.3A, the source/drain regions306, and the channel region307are disposed above the upper surface101aof the substrate101and supported by the gate stack309, which is disposed on the substrate101. In this embodiment, the source/drain regions306and the channel region307are suspended over the substrate101via the gate structure309, which is formed on (in direct contact with) the substrate101. In some other embodiments, the gate structure309may include a dielectric layer310disposed between the gate structure309and the substrate101configured to electrically insulate the conductive portion of the gate structure. In some embodiments, the dielectric layer310can include SiO2, SiN, SiON, and combinations thereof. In some embodiments, the dielectric layer310is omitted.

FIG.3Bis a cross-sectional view of the portion of the semiconductor device30ofFIG.3Ataken along the line A-A, andFIG.3Cis a cross-sectional view of the portion of the semiconductor device30ofFIG.3Ataken along the line B-B. Referring toFIGS.3B and3C, the channel region307and the source/drain regions306are suspended over the substrate101. The gate structure309including one or more dielectric layers304and a gate electrode305on the one or more dielectric layers304is disposed on all sides (i.e., surrounds or wraps) the channel region307and provides support to the channel region307and the source/drain regions306.

The embodiments illustrated and described with reference toFIGS.1A-1C,FIGS.2A-2C, andFIGS.3A-3Cprovide semiconductor structures for forming FinFET devices and GAA devices. It is understood that embodiments of the present disclosure are not so limited.

As used herein, the term “2D material” may refer to crystalline solids consisting of a single layer of atoms. The term “pristine material” refers to a material which has not been subject to a pre-treatment, e.g., an oxidation treatment, a plasma treatment, and the like. For example, a pristine silicon (Si) or silicon germanium (SiGe) material means a Si or SiGe material containing no significant density of oxygen, hydrogen, or other non-Si or SiGe materials or elements. The semiconductor structure having a first portion of a 2D material layer on the top surface and a second portion of the 2D material layer on sidewall surfaces of the channel region and a pristine channel material on the 2D material layer improves short channel performance and channel mobility of a semiconductor device (FinFET). Details of doped 2D material layers will be described in more detail below with reference toFIGS.11-12.

FIG.4is a cross-sectional view of a semiconductor structure40according to an embodiment. Referring toFIG.4, the semiconductor structure40includes a substrate401, a channel region407disposed on the substrate401and including a doped two-dimensional (2D) material layer411having a first portion411aon a top surface and a second portion411bon sidewall surfaces of the channel layer407, a semiconductor layer412on the 2D material layer411, an interfacial layer404on the semiconductor layer412, and a gate electrode405on the interfacial layer404. In an embodiment, the semiconductor layer412is a pristine channel material layer. In an embodiment, the channel region407, the doped 2D material layer411, and the semiconductor layer412form a channel region of a semiconductor device, e.g., a transistor. In an embodiment, the 2D material layer411may include one or more monolayers of 2D materials stacked with each other. The one or more monolayers of 2D materials can be doped with a p-type dopant or an n-type dopant. The 2D material layer411can have an approximate constant doping concentration and/or a gradient of doping concentration (graded doping concentration). The semiconductor structure40also includes a shallow trench isolation structure (STI)102surrounding active regions of the substrate401.

FIG.5is a cross-sectional view of a semiconductor structure50according to an embodiment. Referring toFIG.5, the semiconductor structure50includes a substrate501, a channel region507disposed on the substrate501and having a doped 2D material layer511on its upper surface, an interfacial layer504on the doped 2D material layer511and sidewall surfaces of the channel region507, a gate electrode505on the interfacial layer504, and a shallow trench isolation structure (STI)102surrounding active regions of the substrate501. In an embodiment, the doped 2D material layer511on the top surface of the channel region507improves short channel performance and channel mobility of a semiconductor device. In an embodiment, the 2D material layer511may include one or more monolayers of 2D materials stacked on top of each other. In an embodiment, the 2D material layer511has a thickness in a range between about 0.5 nm and about 30 nm. The one or more monolayers of 2D materials can be doped with a p-type dopant or an n-type dopant. In an embodiment, the 2D material layer511can have an approximate constant doping concentration and/or a graded doping concentration.

FIG.6is a cross-sectional view of a semiconductor structure60according to another embodiment. Referring toFIG.6, the semiconductor structure60includes a substrate601, a channel region607having an alternating stack613of doped 2D material layers611and semiconductor layers612formed on the substrate601, an interfacial layer604on a top surface and sidewall surfaces of the channel region607including the alternating stack613, a gate electrode605on the interfacial layer604, and a shallow trench isolation structure (STI)102surrounding active regions of the substrate601. In an embodiment, the semiconductor layers612each may include a pristine channel material. The doped 2D material layers611may be referred to as semiconductor nanosheets. The semiconductor layers612may be referred to as spacers or sheet-to-sheet spacers. It is understood that the number of doped material layers611and pristine channel material layer612can be any integer number. In the example shown inFIG.6, three doped material layers and two pristine channel material layers are used in the channel region, but it is understood that the number is illustrative only and is chosen for describing the example embodiment and should not be limiting. For example, the semiconductor structure60can have a first doped 2D material layer formed as a bottom portion of the channel region, and a last doped 2D material layer formed as a top portion of the channel region.

FIG.7is a cross-sectional view of a semiconductor structure70according to an embodiment. Referring toFIG.7, the semiconductor structure70includes a substrate701, and a channel region707suspended over the substrate701and including a doped two-dimensional (2D) material layer711. The doped 2D material layer includes a upper portion711aon an upper surface, a second portion711bon opposite sidewall surfaces, and a bottom portion711con a lower surface of the channel layer707. The semiconductor structure70also includes a semiconductor layer712on the 2D material layer711, an interfacial layer704surrounding the semiconductor layer712, and a gate electrode705surrounding the interfacial layer704. In an embodiment, the semiconductor layer712is a pristine channel material layer. The semiconductor structure70also includes a shallow trench isolation structure (STI)102surrounding active regions of the substrate701. In an embodiment, the semiconductor structure also includes a gate dielectric layer710disposed on the active regions of the substrate.

FIG.8is a cross-sectional view of a semiconductor structure80according to an embodiment. Referring toFIG.8, the semiconductor structure80includes a substrate801, a channel region807suspended over the substrate801and including a doped two-dimensional (2D) material layer811on its upper surface, an interfacial layer804surrounding the channel region807including the doped 2D material layer811, and a gate electrode805surrounding the interfacial layer804. In an embodiment, the semiconductor structure80also includes a shallow trench isolation structure (STI)102surrounding active regions of the substrate801and a gate dielectric layer810disposed on the active regions of the substrate801.

FIG.9is a cross-sectional view of a semiconductor structure90according to an embodiment. Referring toFIG.9, the semiconductor structure90includes a substrate901, a channel region907suspended over the substrate901and including a doped two-dimensional (2D) material, an interfacial layer904surrounding the channel region907, and a gate electrode905surrounding the interfacial layer904. In an embodiment, the semiconductor structure90also includes a shallow trench isolation structure (STI)102surrounding active regions of the substrate901and a gate dielectric layer910disposed on the active regions of the substrate901. In an embodiment, the doped 2D material has a non-uniform doping concentration. In an embodiment, doped 2D material has a graded doping profile that linearly increases from the bottom to the top of the channel region907. In an embodiment, the doped 2D material has a graded doping profile that exponentially increases from the bottom to the top of the channel layer907. A graded doping concentration can enhance the conductivity of the channel layer907. For example, the linearly or exponentially increasing graded doping concentration can be obtained by progressively increasing the doping precursor concentration when forming the doped 2D material in the channel region907. A semiconductor device having doping concentration gradients exhibits high drive current, low off-leakage, low parasitic capacitance, and low body effect when operating a low supply voltages.

FIG.10is a cross-sectional view of a semiconductor structure1000according to an embodiment. Referring toFIG.10, the semiconductor structure1000includes a substrate1001, a channel structure1007having a stack1013of alternating doped 2D material layers1011and semiconductor layers1012over the substrate, an interfacial layer1004surrounding the channel structure1007including the stack1013, a gate electrode1005surrounding the interfacial layer1004, and a shallow trench isolation structure (STI)102surrounding active regions of the substrate1001. In an embodiment, the semiconductor structure1000optionally includes a gate dielectric layer1010disposed on the active regions of the substrate1001. In the example shown inFIG.10, three doped 2D material layers1011and two semiconductor layers1012are used in the channel region, but it is understood that the number is illustrative only and is chosen for describing the example embodiment and should not be limiting. In some embodiments, the semiconductor layers include a pristine channel material.

FIGS.4through10provide different exemplary semiconductor structures according to some embodiments. These semiconductor structures have been simplified for the sake of clarity and for illustration of the concepts of the present disclosure. It is understood that additional features can be incorporated into these semiconductor structures, and some of the features can be replaced or eliminated in other embodiments.

FIG.11is a molecular diagram of a two-dimension material110according to some embodiments. Referring toFIG.11, a molecular diagram of a graphene includes a plurality of carbon atoms1101arranged along a single plane1102for forming the two-dimension material110. Pristine graphene has high carrier mobility, but does not have an energy bandgap, so that graphene cannot be turned off effectively, which may be required for many transistors. In some embodiments, graphene can be doped with one or more impurities to enhance channel mobility. In some embodiments, the graphene can be doped with boron (B), aluminum (Al), gallium (Ga), and others to create an energy bandgap for a p-channel semiconductor device. In some other embodiments, the graphene can be doped with nitrogen (N), sulfur (S), phosphorous (P), and others for an n-channel semiconductor device In an embodiment, graphene layers can be epitaxially grown or deposited by chemical vapor deposition (CVD). The graphene layer has a very small thickness of about 0.5 nm. In some embodiments, the graphene can be doped with dopant concentrations in a range from about 1E19 (1019) atoms/cm3to 1E22 (122) atoms/cm3.

FIG.12is a molecular diagram of a two-dimension material120according to some embodiments. Referring toFIG.12, a transition metal atoms1211form a middle layer in the middle and the chalcogen atoms forms a first layer1212aover the transition metal atoms1211and a second layer1212bunder the layer of the transition metal atoms1211. The transition metal atoms1211can be W atoms, Mo atoms, Ti atoms, Nb atoms, Zr atoms, Ga atoms, Sn atoms, and the like. The chalcogen atoms1212can be S atoms, Se atoms, Te atoms, and the like. In the example shown inFIG.12, each of the transition metal atoms1211is bonded to four chalcogen atoms1212, and each chalcogen atoms1212is bonded to two transition metal atoms1211. Similar to graphene, transition metal dichalcogenide materials have high conductivity and carrier mobility suitable for forming thin-sheet FinFET and GAA devices. In some embodiments, the 2D material of MoS2, WS2, WSe2, MoSe2may represent a semiconducting alternative to graphene. In some embodiments, the MoS2, WS2, WSe2, MoSe2may be doped with dopant concentrations in a range from about 1×1019atoms/cm3to about 1×1022atoms/cm3.

FIG.13is a flowchart illustrating a method130of manufacturing a semiconductor device according to some exemplary embodiments. It is understood that additional steps can be provided before, during, and after steps of method130, and some of the steps can be replaced or eliminated for other embodiments of the method. The method130includes providing a substrate (step1301). The substrate may be substantially similar to the substrate101,401-1001ofFIGS.1-10. The substrate may include an elementary semiconductor, a compound semiconductor, an insulator, or other suitable substrate materials. The substrate may have a raised structure including a channel region, source/drain regions disposed on opposite sides of the channel region, and a gate structure on the channel region. The raised structure may be formed using photolithography processes including forming a photoresist layer, patterning the photoresist layer, etching the substrate to produce the raised structure with a suitable height and width protruding above the remainder of the substrate. The raised structure thus formed can include a plurality of protruding regions and a plurality of recesses which separate the protruding regions. The raised structure is used to form one or more FinFET devices or GAA FET devices. In an embodiment, the substrate is a silicon substrate, and a pristine semiconductor layer is epitaxially grown on the substrate, and the raised structure is then formed by a photolithography process, i.e., the channel region includes silicon. In an embodiment, the substrate is a silicon substrate, and a pristine semiconductor layer including silicon germanium (SiGe) is heteroepitaxially grown on the substrate, and the raised structure including SiGe is formed by a photolithography process. In an embodiment, the pristine semiconductor layer is deposited on the substrate by chemical vapor deposition. Step1301also includes forming an isolation trench structure in the recesses, e.g., a shallow trench isolation structure (STI) surrounding active regions of the substrate. The STI may include a semiconductor oxide, a semiconductor nitride, a semiconductor oxynitride, SiOCN, fluorosilicate glass (FSG), a low-k dielectric material, or the like formed using a chemical vapor deposition (CVD) process, a spin-on process, and other suitable deposition process.

The method130also includes forming a 2D material layer on the channel region of the raised structure. In an embodiment, the 2D material layer may include graphene that is deposited using an aqueous solution of graphene oxide. In some embodiments, the 2D material layer includes grapheme-based material by a dry thermal release tape process. In an embodiment, the 2D material layer may include a MoS2layer, a MoSe2layer, a WS2layer, or a WSe2layer. The method130also includes doping the 2D material layer by performing an ion implantation process (step1302). In an embodiment, the ion implantation may include p-type dopants, e.g., boron (B). In another embodiment, the ion implantation may include n-type dopants, e.g., nitrogen (N). The ion implantation can be performed at a vertical implantation and/or at an implantation angle relative to the surface of the substrate.

In an embodiment, the method130optionally includes forming a pristine channel material layer on the doped 2D material layer (step1303) and removing a portion of the pristine channel material layer and a portion of the doped 2D material layer in the recesses (step1304) to expose a surface of the substrate. Steps1303and1304are optional, so that the steps are indicated by dotted line boxes. The method130further includes forming an interfacial layer on the pristine channel material layer and the exposed surface of the substrate. The method130also includes heating the semiconductor device to thermally bond the interfacial layer with the pristine channel material layer (step1305). In some embodiments, the thermal bonding is performed at a temperature ranging from about 400° C. to about 1200° C. If the temperature is small than 400° C., the leakage current of the device increases, in some instances. If the temperature is great than 1200° C., the dopants diffuses into the nearby semiconductor material, resulting in insufficient dopant concentration, in some instances. The method130further includes other fabrication processes (step1306), such as forming a patterned gate electrode on the interfacial layer, forming an interlayer dielectric layer, forming through-holes extending through the interlayer dielectric layer, and filling the through-holes with a conductive material to form contacts that are electrically coupled to the gate electrode and the source/drain regions.

FIGS.14A-14Fare cross-sectional views illustrating intermediate steps of forming a portion of a semiconductor device according to embodiments.FIGS.14A-14Fwill be described together with reference toFIG.13. Referring toFIG.14Aand step1301, a portion of the semiconductor device is shown having already undergone several process operations. A raised structure having three channel regions1407is disposed on a substrate1401, a recess region1402is disposed between the channel regions1407and can be filled with an insulating material. Referring toFIG.14Band step1302, a 2D material layer1408is formed on the channel regions1407by chemical vapor deposition. An ion implantation1409is performed on the 2D material layer1408. The ion implantation1409including N-type dopants (e.g., N) or P-type dopants (e.g., B) can be performed vertically and/or at an oblique angle with respect to the surface of the substrate1401. In some embodiments, the ion implant process can adjust the implant energy, the dopant dose, and the implant temperature to vary the doping concentration along the thickness of the 2D material layer1408. In some embodiments, the ion implant process also adjusts the implant parameters to provide a desired or target doping concentration profile to the 2D material layer1408. Thereafter, a semiconductor material (e.g., Si or SiGe)1410is blanket deposited on the doped 2D material layer1408, as shown inFIG.14Cand step1303. In some embodiments, the semiconductor material1410includes a pristine channel semiconductor material. Referring toFIG.14Dand step1304, a portion of the pristine channel material and a portion of the doped 2D material layer are removed by etching to expose a surface region of the substrate. In an exemplary etch process, a patterned mask layer, e.g., SiN, is formed over the channel regions1407by chemical vapor deposition, and a reactive ion etching process is carried out to anisotropically etch the portion of the pristine channel material and a portion of the doped 2D material layer in the recess region1402. Referring toFIG.14Eand step1305, a conformal interfacial layer1411is formed (blanket deposited) on the pristine channel material layer and the exposed surface of the substrate. The conformal interfacial layer1411includes an insulating material to reduce a roughness at the interface between a subsequent formed gate electrode and the pristine channel material. Thereafter, a thermal treatment is carried out to thermally bond the interfacial layer with the pristine channel material. In an embodiment, the thermal treatment is carried out at a temperature from about 400° C. to about 1200° C. Referring toFIG.14Fand step1306, a conductive layer is formed on the interfacial layer1411form a gate electrode1412, an interlayer dielectric layer1413is formed over the gate electrode1412, a planarizing process, e.g., a chemical mechanical polishing (CMP), is carried out to planarize the upper surface of the interlayer dielectric layer1413. In an embodiment, the conductive layer can include one or more layers of any suitable material, such as polysilicon, aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, tantalum nitride, nickel silicide, cobalt silicide, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, metal alloys, and/or combinations thereof. One of skill in the art will appreciate that other process steps can also be performed, and various alterations and modifications may be practiced. For example, source/drain regions can be formed in a gate last process, the interlayer dielectric layer can be formed on the source/drain regions, through-holes can be formed extending through the interlayer dielectric layer, and the through-holes can be filled with a conductive material to form contacts that are electrically coupled to the gate electrode, the source/drain regions.

FIG.14Fis a cross-sectional view illustrating a channel structure1400according to an embodiment. The channel structure1400includes the channel region1407disposed on the substrate1401, the doped 2D material layer1408disposed on an upper surface and sidewall surfaces of the channel region1407, the pristine channel material1410disposed on the doped 2D material layer1408, the interfacial layer1411disposed on the pristine channel material1410, and the gate electrode1412disposed on the interfacial layer1411. In an embodiment, the channel region1407has a width of about 2 nm to about 10 nm, and a height of about 40 nm to about 70 nm. In some embodiments, the doped 2D material layer1408has one to about 20 layers, and a thickness of about 0.5 nm to about 10 nm The thickness of about 0.5 nm indicates that the doped 2D material layer has a single layer of graphene, and the thicknesses of about 10 nm indicates that the doped 2D material layer has about 20 layers of graphene. In some embodiments, the pristine channel material has a thickness of about 2 nm and about 20 nm, and a width of about 5 nm to about 200 nm. It is understood that the number of channel regions1407on the substrate1401can be any integer number. In the example shown inFIG.14F, three channel regions are used, but it is understood that the number is illustrative only and is chosen for describing the example embodiment and should not be limiting.

FIG.15is a flowchart illustrating a method150of manufacturing a semiconductor device according to some exemplary embodiments. It is understood that additional steps can be provided before, during, and after steps of method150, and some of the steps can be replaced or eliminated for other embodiments of the method. The method150includes providing a substrate (step1501). The substrate may be substantially similar to the substrate to the substrate101,401-1001ofFIGS.1-10. The substrate may include an elementary semiconductor, a compound semiconductor, an insulator, or other suitable substrate materials. The method150also includes forming a pristine channel layer on the substrate. The pristine channel layer may include silicon (Si) or silicon germanium (SiGe) and may be formed by chemical vapor deposition (CVD). Other methods of forming a pristine layer of Si and SiGe will be apparent to those skilled in the art of semiconductor fabrication. The method150also includes forming a 2D material layer is on the pristine channel layer (step1502). Thereafter, an ion implantation is carried out to dope impurities or dopants onto the 2D material layer. The dopants can be p-type dopants (e.g., B) or n-type dopants (e.g., N) (step1503). The method150also includes performing a thermal treatment to thermally bond the doped 2D material layer to the pristine layer (step1504). The thermal treatment is performed at a temperature ranging between about 400° C. to about 1200° C. The method150further includes performing an etch process to define a channel structure. The etch process may include forming a patterned mask layer on the doped 2D material layer and etching the doped 2D material layer, the pristine channel layer and a portion of the substrate using the patterned mask layer as a mask to form the channel structure (step1505). The method150further includes forming an interfacial layer over the channel structure (step1506). The method150also includes other fabrication processes (step1507), such as forming a patterned gate electrode on the interfacial layer, forming source/drain regions in the substrate, forming an interlayer dielectric layer, forming through-holes extending through the interlayer dielectric layer, and filling the through-holes with a conductive material to form contacts that electrically coupled to the gate electrode, the source/drain regions.

FIGS.16A-16Gare cross-sectional views illustrating intermediate steps of forming a portion of a semiconductor device150according to embodiments taken in a transversal direction across a channel structure, the transversal direction is perpendicular to a longitudinal direction across the channel region and the source/drain regions.FIGS.16A-16Gwill be described together with reference toFIG.15. Referring toFIG.16Aand step1501, a substrate1601is provided. The substrate1601may be substantially similar to the substrate101,401-1001shown and described with reference toFIGS.1-10. Referring toFIG.16Band step1502, a pristine channel layer1602is formed on the substrate1601, and a 2D material layer1603is formed on the pristine channel layer1602by chemical vapor deposition. In an embodiment, the substrate is a silicon substrate, and the pristine channel layer1602is epitaxially grown on the silicon substrate, i.e., the pristine channel layer includes silicon. In an embodiment, the substrate is a silicon substrate, and the pristine channel layer1602including silicon germanium (SiGe) is heteroepitaxially grown on the silicon substrate. In an embodiment, a pristine silicon layer including substantially pure silicon or pristine silicon germanium layer can be formed by atomic layer deposition (ALD) and chemical vapor deposition (CVD). The 2D material layer1603can include one or more layers of graphene or transition metal dichalcogenide, such as MoS2, MoSe2, MoTe2, WS2, and WSe2. In an exemplary embodiment, a graphene layer can be formed by epitaxial graphene growth. For example, a silicon carbide dielectric is used as a seed layer to promote the epitaxial growth of the graphene on the pristine channel layer1602. In another exemplary embodiment, a graphene layer can be formed by chemical vapor deposition directly on the pristine channel layer1602. The 2D material layer1603may be doped by adding impurities to control mobility.

Referring toFIG.16Cand step1503, an ion implantation1609is performed on the 2D material layer1603. The ion implantation1609including N-type dopants (e.g., N) or P-type dopants (e.g., B) can be performed vertically and/or at an oblique angle with respect to the surface of the substrate1601. The doped 2D material layer1603is indicated by a shaded box. In some embodiments, the ion implant process can adjust the implant energy, the dopant dose, and the implant temperature to vary the doping concentration along the thickness of the 2D material layer1603. In some embodiments, the ion implant process also adjusts the implant parameters to provide a desired or target doping concentration profile to the 2D material layer1603. Referring toFIG.16Dand step1504, a thermal treatment1610is carried out to thermally bond the doped 2D material layer1603to the pristine channel layer1602(the bonding interface1623is shown as a thick line). In an embodiment, the thermal treatment1610is carried out at a temperature from about 400° C. to about 1200° C.

Referring toFIG.16Eand step1505, an etching process is performed on the doped 2D material layer1603and the pristine channel layer1602. In some embodiments, the etching process includes forming a photoresist layer1615over the doped 2D material layer1603and patterning it to expose portions of the doped 2D material layer1603, and the pristine channel layer1602that are to be removed by an etchant. In an embodiment ofFIG.16E, the photoresist layer1615has been patterned to leave the photoresist material over the doped 2D material layer1603. An exemplary photoresist layer1615includes a photosensitive material that causes the photoresist layer to undergo a property change when exposed to light. This property change can be used to selectively remove exposed or unexposed portions of the photoresist layer1615. The etching process is then performed on the doped 2D material layer1603and the pristine channel layer1602. The etching process may include any suitable etching process including dry etching, wet etching, and/or other etching methods, e.g., reactive ion etching (RIE). In some embodiments, the etching process includes multiple etching steps with different etchants, each targeting a particular material. Referring toFIG.16E, the etching process selectively removes portions of the doped 2D material layer1603and the pristine channel layer1602to define one or more channel structures1607. The channel structure1607includes a lower portion including a pristine channel region portion1602A and a upper portion including a doped 2D material layer portion1603A. In some embodiments, the etching process may removes a portion of the substrate1601, as indicated by a dashed line. Thereafter, the patterned photoresist1615is removed.

Referring toFIG.16Fand step1506, a conformal interfacial layer1611is blanket deposited on the pristine channel material layer and the exposed surface of the substrate. In some embodiments, the interfacial layer1611is formed by oxidation process, such as a thermal oxidation operation or a wet oxidation operation. In further embodiments, one or more dielectric materials are formed over the interfacial layer1611. The conformal interfacial layer1611includes an insulating material to reduce a roughness at the interface between a subsequent formed gate electrode and the channel structure. Referring toFIG.16Gand step1507, a conductive layer is formed on the interfacial layer1611to form a gate electrode1612, an interlayer dielectric layer1613is formed on the gate electrode1612, a planarizing process, e.g., a chemical mechanical polishing (CMP) process, is carried out to planarize the upper surface of the interlayer dielectric layer1613. In an embodiment, the conductive layer can include one or more layers of any suitable material, such as polysilicon, aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, tantalum nitride, nickel silicide, cobalt silicide, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, metal alloys, and/or combinations thereof. In some embodiments, the interfacial layer1611is selectively formed over a top surface of the doped 2D material layer portion1603A and along sidewalls of the pristine channel region portion1602A and1603. In other words, a top surface of substrate1601between two adjacent fin structures is exposed to the gate electrode1612. One of skill in the art will appreciate that other process steps can also be performed, and various alterations and modifications may be practiced. For example, source/drain regions can be formed in a gate-last process, an interlayer dielectric layer can be formed on the source/drain regions, through-holes can be formed extending through the interlayer dielectric layer, and the through-holes can be filled with a conductive material to form contacts that are electrically coupled to the gate electrode, the source/drain regions.

FIG.16Gis a cross-sectional view illustrating a channel structure1600according to an embodiment. The channel structure1600includes the channel region1607disposed on the substrate1601, the channel region1607includes the lower portion including the pristine channel region portion1602A and the upper portion including the doped 2D material layer portion1603A. The channel structure1600also includes the interfacial layer1611disposed on the upper surface and sidewall surfaces of the doped 2D material layer portion1603A, sidewall surfaces of the pristine channel region portion1602A, and the exposed surface portion of the substrate1601. The channel structure1600also includes the gate electrode1612disposed on the interfacial layer1611. In an embodiment, the channel region1607has a width of about 5 nm to about 200 nm, and a height of about 40 nm to about 80 nm, the doped 2D material layer portion1603A has one to about 60 layers, and a thickness of about 0.5 nm to about 30 nm. It is understood that the number of channel regions1607on the substrate1601can be any integer number. In the example shown inFIG.16G, three channel regions are used, but it is understood that the number is illustrative only and is chosen for describing the example embodiment and should not be limiting.

FIG.16His a cross-sectional view of an enlarged portion of a channel structure1607.FIG.16Iis a graph illustrating different doping concentration profile across the thickness of a doped 2D material layer according to some embodiments. The horizontal (x-axis) axis represents the doping concentration, and the vertical (y-axis) axis represents the thickness of the doped 2D material layer. In an embodiment, the doped 2D material layer has an approximate constant doping profile (indicated by line1621) that is a target doping concentration across the thickness of the doped 2D material layer. In an embodiment, the doped 2D material layer has an exponential doping profile that increases across the thickness of doped 2D material layer, e.g., from the lower region to the upper region (indicated by line1622). In an embodiment, the doped 2D material layer has a step-wise doping profile that increases across the thickness of doped 2D material layer, e.g., from the lower region to the upper region (indicated by line1623). In an embodiment, the doped 2D material layer has a linear doping profile (indicated by line1624) that increases across the thickness of doped 2D material layers. In some embodiments, the range of the doping concentration profile can increase by one, two, or three orders of magnitude across the thickness of the doped 2D material layer.

FIG.17is a flowchart illustrating a method170of manufacturing a semiconductor device according to some exemplary embodiments. It is understood that additional steps can be provided before, during, and after steps of method170, and some of the steps can be replaced or eliminated for other embodiments of the method. The method170includes providing a substrate (step1701). The substrate may be substantially similar to the substrate to the substrate101,401-1001ofFIGS.1-10. The substrate may include an elementary semiconductor, a compound semiconductor, an insulator, or other suitable substrate materials. The method170also includes forming a first pristine channel layer on the substrate. The first pristine channel layer may include silicon (Si) or silicon germanium (SiGe) and may be formed by chemical vapor deposition (CVD). Other methods of forming a pristine layer of Si and SiGe will be apparent to those skilled in the art of semiconductor fabrication. The method170also includes forming a 2D material layer is on the pristine channel layer (step1702). Thereafter, an ion implantation is carried out to dope impurities or dopants onto the 2D material layer. The dopants can be p-type dopants (e.g., B) or n-type dopants (e.g., N) (step1703). The method170also includes repeating steps1702and1703until a predetermined number of alternating pristine channel layers and doped 2D material layers are formed (step1704). The method170also includes performing a thermal treatment to thermally bond the alternating doped 2D material layers and the pristine channel layers (step1705). The thermal treatment is performed at a temperature ranging between about 400° C. to about 1200° C. The method170further includes performing an etch process to define a channel structure. The etch process may include forming a patterned mask layer on the top doped 2D material layer of the alternating doped 2D material layers and pristine channel layers and etching the alternating doped 2D material layers and the pristine channel layers using the patterned mask layer as a mask to form the channel structure (step1706). The method170further includes forming an interfacial layer over the channel structure (step1707). The method170also includes other fabrication processes (step1708), such as forming a patterned gate electrode on the interfacial layer, forming source/drain regions in the substrate, forming an interlayer dielectric layer, forming through-holes extending through the interlayer dielectric layer, and filling the through-holes with a conductive material to form contacts that electrically coupled to the gate electrode, the source/drain regions.

FIGS.18A-18Hare cross-sectional views illustrating intermediate steps of forming a portion of a semiconductor device according to embodiments taken in a transversal direction across a channel structure, the transversal direction is perpendicular to a longitudinal direction across the channel region and the source/drain regions.FIGS.18A-18Hwill be described together with reference toFIG.17. Referring toFIG.18Aand step1701, a substrate1801is provided. The substrate1801may be substantially similar to the substrate101,401-1001shown and described with reference toFIGS.1-10. Referring toFIG.18Band step1702, a pristine channel layer1802is formed on the substrate1801, and a 2D material layer1803is formed on the pristine channel layer1802by chemical vapor deposition. Referring toFIG.18Cand step1703, an ion implantation1809is performed on the 2D material layer1803. In some embodiments, the ion implant process can adjust the implant energy, the dopant dose, and the implant temperature to vary the doping concentration along the thickness of the 2D material layer1803. In some embodiments, the ion implant process also adjusts the implant parameters to provide a desired or target doping concentration profile to the 2D material layer1803. The steps1702and1703of forming the pristine channel layer1802, the 2D material layer1803, and doping the 2D material layer1803with impurities andFIGS.18A to18Care substantially the same as those of steps1502and1503andFIGS.16A to16C, respectively. Accordingly, they will not be described in detail herein for the sake of brevity.

Referring toFIG.18Dand step1704, a second pristine channel layer1802ais formed on the doped 2D material layer1803, and a second doped 2D material layer1803ais formed on the second pristine channel layer1802a. A third pristine channel layer1802bis formed on the second doped 2D material layer1803a, and a third doped 2D material layer1803bis formed on the third pristine channel layer1802b, and so forth until a predetermined number of alternating pristine channel layers and doped 2D material layers are formed.

Referring toFIG.18Eand step1705, a thermal treatment1810is carried out to thermally bond the alternating doped 2D material layers1803and the pristine channel layers1802together. In an embodiment, the thermal treatment1810is carried out at a temperature from about 400° C. to about 1200° C.

Referring toFIG.18Fand step1706, an etching process is performed on the alternating doped 2D material layers and the pristine channel layers. In some embodiments, the etching process includes forming a photoresist layer (not shown) over the top doped 2D material layer1603and a patterned hard mask layer, e.g., SiN, (not shown)) on the photoresist layer, patterning the photoresist layer to expose portions of the top doped 2D material layer, and remove portions of the alternating stack of doped 2D material layers and pristine channel layers using the patterned hard mask as a mask to define a channel structure1807. In some embodiments, the etch process may remove a portion of the substrate1801, as indicated by a dotted line. The photoresist layer and the hard mask layer are then removed.

Referring toFIG.18Gand step1707, a conformal interfacial layer1811is formed (e.g., blanket deposited) on the channel structure1807and the exposed surface of the substrate. The blanket interfacial layer1811includes an insulating material to reduce a roughness at the interface between a subsequent formed gate electrode and the channel structure. Referring toFIG.18Hand step1708, a conductive layer is formed on the interfacial layer1811form a gate electrode1812, an interlayer dielectric layer1813is formed over the gate electrode1812, a planarizing process, e.g., a chemical mechanical polishing (CMP), is carried out to planarize the upper surface of the interlayer dielectric layer1813. In an embodiment, the conductive layer can include one or more layers of any suitable material, such as polysilicon, aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, tantalum nitride, nickel silicide, cobalt silicide, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, metal alloys, and/or combinations thereof. One of skill in the art will appreciate that other process steps can also be performed, and various alterations and modifications may be practiced. For example, source/drain regions can be formed in a gate-last process, an interlayer dielectric layer can be formed on the source/drain regions, through-holes can be formed extending through the interlayer dielectric layer, and the through-holes can be filled with a conductive material to form contacts that are electrically coupled to the gate electrode, the source/drain regions.

FIG.18Gis a cross-sectional view illustrating a channel structure1800according to an embodiment. The channel structure1800includes the channel region1807disposed on the substrate1801, the channel region1807includes a stack of alternating layers of a plurality of pristine channel layers1802and a plurality of doped 2D material layers1803. The channel structure1800also includes the interface1811disposed on the channel region1807and on the exposed surface portion of the substrate1802. The channel structure1800also includes the gate electrode1812on the channel structure1800. In an embodiment, the channel region1807has a width of about 5 nm to about 200 nm, and a height of about 40 nm to about 80 nm, each of the doped 2D material layers has one to about 60 layers, and a thickness of about 0.5 nm to about 30 nm. It is understood that the number of alternating layers of a plurality of pristine channel layers and a plurality of doped 2D material layers can have any integer number. In the example shown inFIG.18H, a stack of three alternating pristine channel layers and doped 2D material layers are used, and three channel regions1807are shown, but it is understood that the number is illustrative only and is chosen for describing the example embodiment and should not be limiting. In other words, the number of the repeating sequences of pristine channel layers1802and doped 2D material layers1803are not limited to three, and may be as few as 1 and more than 3, e.g., 20, 40, or 60. By selecting the number of the stacked sequences, a driving current of a field effect transistor can be adjusting.

FIG.18Iis a cross-sectional view of an enlarged portion of a channel structure1807. Referring toFIG.18I, the channel structure1807includes a stack of alternating layers of a plurality of pristine channel layers1802and a plurality of doped 2D material layers1803, e.g., a first pristine channel layer1802, a first doped 2D material layer1803on the first pristine channel layer1802, a second pristine channel layer1802A on the first doped 2D material layer1803, a second doped 2D material layer1803A on the second pristine channel layer1802A, a third pristine channel layer1802B on the second doped 2D material layer1803A, and a third doped 2D material layer1803B on the third pristine channel layer1802B. In one embodiment, the first doped 2D material layer1803has a first thickness T1, the second doped 2D material layer1803A has a second thickness T2, and the third doped 2D material layer1803B has a third thickness T3. The first, second, and third thicknesses may have the same thickness or different thicknesses.

FIG.18Jis a graph illustrating different doping concentration profile across the thickness of a doped 2D material layer in the channel structure1807according to some embodiments. The horizontal (x-axis) axis represents the doping concentration, and the vertical (y-axis) axis represents the thickness of the doped 2D material layers. In an embodiment, each of the doped 2D material layers1803,1803A, and1803B has an approximate constant doping profile (indicated by line1821,1821a, and1821b, respectively) that is a target doping concentration across the thickness of the doped 2D material layers. In an embodiment, each of the doped 2D material layers has an exponential doping profile that increases across the thickness of doped 2D material layers, e.g., from the lower region to the upper region (indicated by line1822,1822a, and1822b, respectively). In an embodiment, each of the doped 2D material layers has a step-wise doping profile that increases across the thickness of doped 2D material layers, e.g., from the lower region to the upper region (indicated by line1823,1823a, and1823b, respectively). In an embodiment, one or more of the doped 2D material layers has a doping profile that decreases from the middle region to the peripheral regions, as indicated by lines1822c,1822d. In certain embodiments, each of the doped 2D material layers has a linear doping profile (indicated by lines1824,1824a,1824b) that increases across the thickness of doped 2D material layers. In some embodiments, the range of the doping concentration profile can increase by one, two, or three orders of magnitude across the thickness of the doped 2D material layer.

FIG.19shows a channel structure1900according to an embodiment. The channel structure1900is formed over a substrate1901.FIG.19is a cross-sectional view taken along line A-A ofFIG.3A.FIG.19is similar toFIG.3Bexcept for the differences described herein. In some embodiments, the channel structure1900includes a channel region1907including a doped 2D material layer1908surrounding the channel region1907, a semiconductor layer1902surrounding the doped 2D material layer1908, an interfacial layer1911of a dielectric material surrounding the pristine semiconductor layer1902, and a gate electrode1912surrounding the interfacial layer1911. In an embodiment, the semiconductor layer1902includes a pristine channel material.

In an embodiment, the substrate1901includes a trench isolation structure102, e.g., a shallow trench isolation (STI) region, in the substrate, and a gate dielectric layer1910disposed between a portion of the main surface of the substrate and the gate electrode1912. The gate dielectric layer1910includes one or more layers of a dielectric material, such as silicon oxide, silicon nitride, or high-k dielectric material, or combinations thereof. In an embodiment, the substrate1901includes an elementary semiconductor, e.g., silicon, germanium, a compound semiconductor including silicon carbide, gallium arsenide, gallium phosphide, an alloy semiconductor, such as silicon germanium, gallium arsenic phosphide, a silicon-on-insulator structure, or a combination thereof. In some embodiments, the substrate1901can be doped with p-type dopants (e.g., boron, indium, aluminum, or gallium) or n-type dopants (e.g., phosphorous or arsenic). The channel region2007may have the same material or different materials than the substrate2001. In an embodiment, the doped 2D material layer1908includes one or more doped layers of graphene. The graphene layer has a very small thickness of 0.5 nm. In an embodiment, the doped 2D material layer includes or one or more doped sub-layers of transition metal dichalcogenide (TMD) material. The TMD material may include a compound of transition metal atoms (Mo, W, Ti, or the like), and chalcogen atoms (S, Se, Te, or the like). A sublayer of the TMD material has a very small thickness. For example, a MoS2monolayer has a thickness of about 0.65 nm. In some embodiments, the doped 2D material layer1908may include one or more sub-layers of MoS2, WS2, MoSe2, MoTe2, and combinations thereof.

The interfacial layer1911includes one or more layers of a dielectric material, such as silicon oxide, silicon nitride, or high-k dielectric material, and/or combinations thereof. Examples of high-k dielectric material include HfO2, HfOSiO, HfSiON, zirconium oxide, aluminum oxide, titanium oxide, or combination thereof. The gate electrode1912includes polysilicon, carbon material, metal, metal alloy, or combinations thereof.

In some embodiments, the channel region1907has a length in a range from about 2 nm to about 100 nm and a height in a range from about 2 nm to about 80 nm. The doped 2D material layer1908has a thickness in a range from about 0.5 nm to about 10 nm. The pristine semiconductor layer1902has a thickness in a range from about 2 nm to about 20 nm.

FIG.20shows a channel structure2000according to an embodiment. The channel structure2000is formed over a substrate2001.FIG.20is a cross-sectional taken along line A-A ofFIG.3A.FIG.20is similar toFIG.3Bexcept for the differences described herein. In some embodiments, the channel structure2000includes a channel region2007, a doped 2D material layer2008disposed on an upper surface of the channel region2007, an interfacial layer2011of a dielectric material surrounding (wrapping around) the channel region2007including the doped 2D material layer2008, and a gate electrode2012surrounding the interfacial layer2011.

In an embodiment, the substrate2001includes a trench isolation structure102, e.g., a shallow trench isolation (STI) region in the substrate, and a gate dielectric layer2010disposed between a portion of its main surface and the gate electrode2012. In an embodiment, the substrate2001includes an elementary semiconductor, e.g., silicon, germanium, a compound semiconductor including silicon carbide, allium arsenide, gallium phosphide, an alloy semiconductor, such as silicon germanium, gallium arsenic phosphide, a silicon-on-insulator structure, or a combination thereof. In some embodiments, the substrate2001can be doped with p-type dopants (e.g., boron, indium, aluminum, or gallium) or n-type dopants (e.g., phosphorous or arsenic). The channel region2007may have the same material or different materials than the substrate2001. In an embodiment, the doped 2D material layer2008can include one or more doped layers of graphene. In an embodiment, the doped 2D material layer can include or one or more doped sub-layers of transition metal dichalcogenide (TMD) material. The TMD material may include a compound of transition metal atoms (Mo, W, Ti, or the like), and chalcogen atoms (S, Se, Te, or the like). A sublayer of the TMD material has a very small thickness. For example a MoS2monolayer has a thickness of about 0.65 nm. In some embodiments, the doped 2D material layer2008may include one or more sub-layers of MoS2, WS2, MoSe2, MoTe2, and combinations thereof.

In some embodiments, the channel region2007has a length in a range from about 2 nm to about 120 nm and a height in a range from about 2 nm to about 100 nm. The doped 2D material layer2008has a thickness in a range from about 0.5 nm to about 30 nm.

In some embodiments, the doped 2D material layer2008has a constant doping profile with dopant concentrations in a range from about 1E19 (1019) atoms/cm3to 1E22 (1022) atoms/cm3. In some embodiments, the doped 2D material layer2008has a non-constant doping profile, e.g., a graded doping profile with a linear or exponential doping concentration in a range from 1E19 atoms/cm3to 1E22 atoms/cm3that increases from the lower surface (bottom region) to the upper surface (top region) of the doped 2D material layer2008. In an embodiment, doped 2D material layer2008has a step-wise doping concentration profile that increases from the lower surface (bottom region) to the upper surface (top region). As used herein, a constant doping profile refers to a material layer that has an approximate constant concentration of dopant across the thickness of the material layer. A linear doping profile refers to a material layer that linearly increases across the thickness of the material layer. An exponential doping profile refers to a material layer that exponentially increases across the thickness of the material layer.

FIG.21shows a channel structure2100according to an embodiment. The channel structure2100is formed over a substrate2101.FIG.21is a cross-sectional taken along line A-A ofFIG.3A.FIG.21is similar toFIG.3Bexcept for the differences described herein. In some embodiments, the channel structure2100includes a channel region2107having a stack2108of a plurality of alternating layers2108nof doped 2D material sublayers2108and pristine semiconductor layers2102. In some embodiments, the plurality of alternating layers includes two to 80 alternating layers with a top layer being a doped 2D material sublayer2108tand a bottom being a doped 2D material sublayer2108b. The channel structure2100further includes an interfacial layer2111of a dielectric material surrounding (wrapping around) the channel region2107including the doped 2D material layer2108, and a gate electrode2112surrounding the interfacial layer2111.

In an embodiment, the substrate2101includes a trench isolation structure102, e.g., a shallow trench isolation (STI) region in the substrate, and a gate dielectric layer2110disposed between a portion of its main surface and the gate electrode2112. In an embodiment, the substrate2101includes an elementary semiconductor, e.g., silicon, germanium, a compound semiconductor including silicon carbide, allium arsenide, gallium phosphide, an alloy semiconductor, such as silicon germanium, gallium arsenic phosphide, a silicon-on-insulator structure, or a combination thereof. In some embodiments, the substrate1901can be doped with p-type dopants (e.g., boron, indium, aluminum, or gallium) or n-type dopants (e.g., phosphorous or arsenic). The channel region2107may have the same material or different materials than the substrate2101. In an embodiment, the doped 2D material layer2108can include one or more doped layers of graphene. In an embodiment, the doped 2D material layer can include or one or more doped sub-layers of transition metal dichalcogenide (TMD) material. The TMD material may include a compound of transition metal atoms (Mo, W, Ti, or the like), and chalcogen atoms (S, Se, Te, or the like). A sublayer of the TMD material has a very small thickness. For example a MoS2 monolayer has a thickness of about 0.65 nm. In some embodiments, the doped 2D material layer2108may include one or more sub-layers of MoS2, WS2, MoSe2, MoTe2, and combinations thereof.

In some embodiments, the channel region2107has a length in a range from about 2 nm to about 120 nm and a height in a range from about 2 nm to about 100 nm. Each doped 2D material sublayer of the doped 2D material layer2108has a thickness in a range from about 0.5 nm to about 30 nm.

In some embodiments, each sublayer of the doped 2D material layer2108has a constant doping profile that is substantially constant across the thickness of the sublayer. In an embodiment, the constant doping profile has dopant concentrations that varies less than 10 percent of a constant doping concentration ranging from about 1E19 (1019) atoms/cm3to 1E22 (1019) atoms/cm3. In other embodiments, each sublayer of the doped 2D material layer2008has a non-constant doping profile, e.g., a graded doping profile with a linear or exponential doping concentration that decreases from the middle portion of the sublayer toward its upper surface (top region) and lower surface (bottom region), the top sublayer2108thas a doping concentration that decreases from the upper region to the lower region, and the bottom sublayer2108bhas a doping concentration that increases from the lower region to the upper region.

FIG.22shows a channel structure2200according to an embodiment. The channel structure2200is formed over a substrate2201.FIG.22is a cross-sectional taken along line A-A ofFIG.3A.FIG.22is similar toFIG.3Bexcept for the differences described herein. In some embodiments, the channel structure2200includes a channel region2207having a doped 2D material layer2208disposed in its center region, a pristine material layer2202surrounding the channel region2207, an interfacial layer2211of a dielectric material surrounding (wrapping around) the pristine material layer2202, and a gate electrode2212surrounding the interfacial layer2211.

In an embodiment, the substrate2201includes a trench isolation structure102, e.g., a shallow trench isolation (STI) region in the substrate, and a gate dielectric layer2210disposed between a portion of its main surface and the gate electrode2212. In an embodiment, the substrate2201includes an elementary semiconductor, e.g., silicon, germanium, a compound semiconductor including silicon carbide, allium arsenide, gallium phosphide, an alloy semiconductor, such as silicon germanium, gallium arsenic phosphide, a silicon-on-insulator structure, or a combination thereof. In some embodiments, the substrate2201can be doped with p-type dopants (e.g., boron (B), indium (In), aluminum (Al), or gallium (Ga)) or n-type dopants (e.g., nitrogen (N), phosphorous (P), sulfur (S), or arsenic (As)). The channel region2207may have the same material or different materials than the substrate2201. In an embodiment, the doped 2D material layer2208can include one or more doped layers of graphene. In an embodiment, the doped 2D material layer can include or one or more doped sub-layers of transition metal dichalcogenide (TMD) material. The TMD material may include a compound of transition metal atoms (Mo, W, Ti, or the like), and chalcogen atoms (S, Se, Te, or the like). A sublayer of the TMD material has a very small thickness. For example a MoS2 monolayer has a thickness of about 0.65 nm. In some embodiments, the doped 2D material layer2208may include one or more sub-layers of MoS2, WS2, MoSe2, MoTe2, and combinations thereof.

In some embodiments, the channel region2207has a length in a range from about 2 nm to about 100 nm and a thickness in a range from about 2 nm to about 20 nm. The doped 2D material layer2208has a thickness in a range from about 2 nm to about 50 nm. In some embodiments, the doped 2D material layer2208has a constant doping profile with dopant concentrations in a range from about 1E19 (1019) atoms/cm 3 to 1E22 (1022) atoms/cm3.

FIG.23is a perspective view illustrating a fin-type semiconductor device23according to an embodiment. The semiconductor device23includes a fin-type semiconductor structure having a source region231, a drain region232, a channel region disposed between the source and drain regions231,232, and a gate electrode233disposed on the channel region.

FIG.24is a cross-sectional view illustrating a fin-type semiconductor device24comprising a channel region240including a doped 2D material layer (shaded area) having an upper surface portion241on an upper surface of the channel region, and side surface portions242disposed on sidewall surfaces of the channel region according an embodiment. The semiconductor device24also includes a semiconductor layer243on the doped 2D material layer, an interfacial layer IL on the semiconductor layer, and a gate electrode Gate on the interfacial layer IL. In an embodiment, the semiconductor layer243is a pristine semiconductor layer.

FIG.25is a cross-sectional view illustrating a fin-type semiconductor device25comprising a channel region250including a doped 2D material layer (shaded area)251on an upper surface of the channel region, an interfacial layer IL on the doped 2D material layer and sidewall surfaces of the channel region, and a gate electrode Gate on the interfacial layer IL according an embodiment.

FIG.26is a cross-sectional view illustrating a fin-type semiconductor device26comprising a channel region260including a stack of alternating doped 2D material layers (shaded area)261and semiconductor layers262on the silicon substrate, an interfacial layer IL on the stack of alternating doped 2D material layers and semiconductor layers, and a gate electrode Gate on the interfacial layer IL according an embodiment. In an embodiment, the semiconductor layers262are pristine semiconductor layers.

FIG.27is a cross-sectional view illustrating a fin-type semiconductor device27comprising a channel region270including a stack of alternating doped 2D material layers (shaded area)271and semiconductor layers272on the silicon substrate, an interfacial layer IL on the stack of alternating doped 2D material layers and pristine semiconductor layers, and a gate electrode Gate on the interfacial layer IL according an embodiment. The stack configuration is similar to that ofFIG.26except that the bottom layer is a doped 2D material layer on the silicon substrate. In an embodiment, the semiconductor layers362are pristine semiconductor layers.

FIG.28is a perspective view illustrating a semiconductor device28according to an embodiment. The semiconductor device28includes a gate-all-around (GAA) semiconductor structure having a source region281, a drain region282, a channel region disposed between the source and drain regions, and a gate electrode283surrounding the channel region.

FIG.29is a cross-sectional view illustrating a GAA semiconductor device29comprising a channel region290including a doped 2D material layer (shaded area) having an upper surface portion291on a top surface of the channel region, side surface portions292disposed on sidewall surfaces of the channel region, and a lower surface portion293on a bottom surface of the channel region according an embodiment. The semiconductor device29also includes a semiconductor layer294on the doped 2D material layer, an interfacial layer IL on the semiconductor layer, and a gate electrode Gate on the interfacial layer IL. In an embodiment, the semiconductor layer294is a pristine semiconductor layer.

FIG.30is a cross-sectional view illustrating a GAA semiconductor device comprising a channel region including a doped 2D material layer (shaded area)300in the channel region, a semiconductor material layer301surrounding the doped 2D material layer, an interfacial layer IL surrounding the doped 2D material layer, and a gate electrode Gate surrounding the interfacial layer IL according an embodiment. In an embodiment, the semiconductor material layer301is a pristine semiconductor layer.

FIG.31is a cross-sectional view illustrating a GAA semiconductor device31comprising a channel region310including a doped 2D material layer (shaded area)311on an upper surface of the channel region, an interfacial layer IL surrounding the channel region including the doped 2D material layer, and a gate electrode Gate surrounding the interfacial layer IL according an embodiment.

FIG.32is a cross-sectional view illustrating a GAA semiconductor device32comprising a channel region320including a stack of alternating doped 2D material layers (shaded area)321and semiconductor layers322on the silicon substrate, an interfacial layer IL on the stack of alternating doped 2D material layers and semiconductor layers, and a gate electrode Gate on the interfacial layer IL according an embodiment. In an embodiment, the semiconductor layers322are pristine semiconductor layers. The dotted line box323represents a portion of the doped material layer and indicates that the doped 2D material layer may include one or more monolayers of doped graphene or one or more monolayers of doped MoS2, WS2, MoSe2, MoTe2, and combinations thereof. The dotted line box323can be a portion of a doped material layer or the entire doped material layer.

FIG.33is a perspective view of a multi-gate and multiple stacked channel device33according to an embodiment.FIG.34is a cross-sectional view of the device33according to an embodiment along the line X-X′. Referring toFIG.33andFIG.34, the multi-gate and multiple stacked channel device33includes a substrate3301, a shallow trench isolation structure3302on the substrate3301, a gate structure1300disposed between source/drain regions902and surrounding multiple stacked channel regions208disposed between the source/drain regions902, an opening1402adjacent the gate structure1300, a cap layer1702filling a top portion of the opening1402, a contact etch stop layer (CESL)1002on the source/drain regions902, an interlayer dielectric (ILD) layer1004on the source/drain regions902. contacts1902extending through the ILD layer1004and the CESL1002and on the source/drain regions902, a spacer802adjacent the opening1402. Referring toFIG.34, an air gap1602includes a first sidewall interfacing the gate structure1300and a second sidewall interfacing the source/drain regions902. In some embodiments, the multiple stacked channel regions208include a doped 2D material layer similar or the same as the doped 2D material layer shown and described with reference toFIGS.29to32.

FIGS.35to38illustrate a carrier (e.g., electrons) concentration across channel regions240to270of the FinFET devices24to27, respectively, when the FinFET devices24to27are turned on. The light-shaded areas denote low carrier concentration, and dark-shaded areas denote high carrier concentration. Similarly,FIGS.39to42illustrate a carrier (e.g., electrons) concentration across channel regions290to320of the GAA semiconductor devices29to32, respectively, when the semiconductor devices29to32are turned on. The light-shaded areas denote low carrier concertation, and dark-shaded areas denote high carrier concentration.

FIGS.43-45provide exemplary ranges associated with the heights, widths, and thicknesses of exemplary channel structures including doped 2D material layers for a fin-type semiconductor device according to some embodiments.

FIGS.46-49provide exemplary ranges associated with the heights, widths, and thicknesses of exemplary channel structures including doped 2D material layers for a gate-around type (GAA) semiconductor device according to some embodiments.

In an embodiment, a semiconductor device includes a substrate, a semiconductor structure on the substrate and comprising a source region, a drain region, and a channel region disposed between the source region and the drain region and including a doped two-dimensional (2D) material layer comprising a first portion on an upper surface of the channel region, an interfacial layer on the first portion of the doped 2D material layer and on sidewalls of the channel region, and a gate electrode on the interfacial layer. In some exemplary embodiments, the doped 2D material layer extends across the channel region. In an embodiment, the doped 2D material layer has a graded doping concentration across its thickness.

In an embodiment, a semiconductor device includes a substrate, a semiconductor structure suspending over the substrate and comprising a source region, a drain region, and a channel region disposed between the source region and the drain region, the channel region includes a doped two-dimensional (2D) material layer comprising a first portion on an upper surface of the channel region. In an embodiment, the semiconductor device further includes an interfacial layer surrounding the channel region including the first portion of the doped 2D material layer, and a gate electrode surrounding the interfacial layer.

In an embodiment, a method of fabricating a semiconductor device includes: providing a substrate having a semiconductor structure formed thereon, forming a doped two-dimension material layer on the semiconductor structure, forming a material semiconductor layer on the doped two-dimension material layer, forming an interfacial layer on the pristine channel material layer, and forming a gate electrode on the interfacial layer. In an embodiment, the semiconductor layer is a pristine channel material layer.

The foregoing merely outlines features of embodiments of the disclosure. Various modifications and alterations to the described embodiments will be apparent to those skilled in the art in view of the teachings herein. Those skilled in the art will appreciate that equivalent constructions do not depart from the scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.