Patent ID: 12205673

DETAILED DESCRIPTION

Various embodiments described herein provide for a read data strobe (RDQS) path having variation compensation (e.g., voltage and temperature compensation), delay lines, or both, where the RDQS path can be included by a physical (PHY) interface for a memory device, such as a Double Data Rate (DDR) Dynamic Random-Access Memory (DRAM) memory device.

Generally, there is a DQ path and a DQ pin for each bit of data (e.g., each bit of a data word) to be transferred during a read operation or a write operation on the DDR memory device. Additionally, during a read operation or a write operation, the DQS path provides a DQ strobe (DQS) signal that operates as a clock signal for synchronizing and sampling read and write data (e.g., read and write data bits) conveyed (e.g., provided) over one or more DQ paths. With respect to a DDR memory device, two data bits (e.g., of a data word) are transferred over each DQ path per a cycle of a DQS signal transmitted over a DQS path-one data bit transferred on a positive edge of the DQS signal and another data bit is transferred on a negative edge of the DQS signal. Some memory systems have a DQS path for read operations (read DQS (RDQS) path) and a separate DQS path for write operations (write DQS (WDQS) path). To achieve reliable data transfer, signals (such as DQS signals) for read/write operations in a DDR-based memory system adhere to strict timing requirements. Usually, this adherence becomes more difficult as the operating frequency of the DDR-based memory device increases (e.g., due to the data line skew, duty cycle distortion, jitter, and the like).

Various embodiments described herein reduce power, reduce circuit area, improve timing margins, or some combination thereof of a read data path coupled to a memory device, such as a read data path of a PHY interface in a DDR memory system (e.g., Low Power (LP) DDRx memory system, such as a LPDDR5 memory system). In particular, a read data path architecture of some embodiments comprises a read DQS (RDQS) path, and one or more logic blocks, logic gates, and delay line components in the RDQS path can be compensated (e.g., voltage and temperature (VT) compensated) for effects (e.g., VT drift) caused to by a voltage or a temperature variation. In this way, various embodiments can improve power, performance, or area (PPA) for the read data path coupled to a memory device.

For some embodiments, a RDQS path comprises a base delay line component, adder delay line components, rise delay line components, and fall delay line components. In this way, various embodiments, delay line components in a RDQS path are split (e.g., divided) into a hierarchy/architecture of delay line components (e.g., four levels of delay line components) that does not currently exist in conventional RDQS path. The delay line components of the RDQS path can be used to adjust (e.g., position) read data strobe (RDQS) signals provided (e.g., conveyed) by the RDQS path at the center of data bits carried by data signals provided (e.g., conveyed) by data paths (e.g., DQ paths). For some embodiments, the base delay line component is used to provide skew between data signal provided by data paths (e.g., DQ paths) and a read data strobe signal (RDQS signal) provided by the RDQS path, which is a common delay in the RDQS path for all data paths (e.g., all data signals carrying data bits); each adder data line component is used to provide de-skewing per a data path (e.g., per a DQ path); and each rise delay line component and fall delay line component is used to compensate for duty cycle distortion (DCD) by creating offset between rise and fall edges of data strobe signals provided by the RDQS path. Additionally, some embodiments provide for a process (e.g., algorithm) for training a base delay line component, adder delay line components, rise delay line components, and fall delay line components of a RDQS path described herein.

By use of various embodiments, data paths (e.g., DQ paths) of a memory system can avoid replication of logic gates and logic blocks (e.g., combinatorial logic) of the RDQS path in each of the data paths (e.g., in each DQ path), which conventional memory systems may do for purposes of tracking delay drifts caused by voltage and temperature variations (e.g., keeping the phase of data signals on each DQ path relative to read data strobe signals on the RDQS path the same after VT drift). Further, the use of single adder delay line component for a pair of rise and fall delay line components in the RDQS path can enable the rise and fall delay line components to leverage the delay range of the single adder delay line component so that the rise and fall delay line components can support a smaller range of delays (and delay codes) than otherwise possible. In this way, various embodiments can save power and area with respect to the rise and fall delay line components.

Some embodiments use at least two master delay loops (MDLs), each comprising a master delay line component, to facilitate compensation for effects caused to circuit elements (e.g., increased signal delay) by a voltage or a temperature variation. For instance, a first MDL (or first MDL sub-circuit) comprising a first master delay line component (also referred to herein as “MW”) and a first phase detector can be used to determine (e.g., obtain) VT drift information of one or more delay elements included by the RDQS path based on a code of the first master delay line component (also referred to as MW code) that controls a delay applied by the first master delay line component in the first MDL. A second MDL (or second MDL sub-circuit) comprising a second master delay line component (also referred to herein as “MR”), a network of components modeling one or more logic gates or logic blocks included by the RDQS path, and a second phase detector can be used to determine (e.g., obtain) VT drift information of one or more delay elements included by the RDQS path and VT drift information of the one or more logic gates or logic blocks. According to some embodiments, the first phase detector is operatively coupled to the output of the first master delay line component, and the MW code is updated (e.g., adjusted) such that a phase difference (as determined by the first phase detector) between a clock signal and an output signal of the first master delay line component is maintained at a predetermined value, such as three-hundred sixty degrees or 2π radians. Additionally, for some embodiments, the second phase detector is operatively coupled to the output of the network of components, the network of components is operatively coupled to the output of the second master delay line component, and the MR code is updated (e.g., adjusted) such that a phase difference (as determined by the second phase detector) between a clock signal and an output signal of the network of components is maintained at a predetermined value, such as three-hundred sixty degrees or 2π radians. In particular, some embodiments compensate for an increase of delay in the network of components (of the second MDL) after the VT drift by adjusting the MR code to decrease the delay applied by the second master delay line component (e.g., by decreasing the MR code), and compensate for a decrease of delay in the network of components (of the second MDL) after the VT drift by adjusting the MR code to increase the delay applied by the second master delay line component (e.g., by increasing the MR code). The first master delay loop and the second master delay loop can operate in parallel. For some embodiments, VT drift information of the one or more delay elements included by the RDQS path can be determined based on the MW code, and VT drift information of the one or more logic gates or logic blocks included by the RDQS path can be determined by subtracting the MR code from MW code (e.g., at initialization and after VT drift). The determined VT drift information of the one or more delay elements and the VT drift information of the one or more logic gates or logic blocks can be used to update (e.g., adjust) the codes of the base delay line component, the adder delay line components, the rise delay line components, and the fall delay line components of the RDQS path. In this way, the total delay in the RDQS path can be maintained at a constant after VT drift.

As used herein, a delay line component can apply a delay (e.g., of a determined amount) to a signal passing through the delay line component, where the amount of delay applied is based on a code (e.g., delay line code) that is received as input by the delay line component. For instance, different values of the code can correspond to different amounts of delay. The delay line component can comprise a digital delay line (DDL) component, which can generate a delayed signal based on an input signal and one or more settings (e.g., delay values) applied to the digital delay line component.

Reference will now be made in detail to embodiments of the present disclosure, examples of which are illustrated in the appended drawings. The present disclosure may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein.

FIG.1is a block diagram illustrating an example electronic device100that comprises an example read data strobe (RDQS) path from a memory device comprising variation compensation and delay lines104(hereafter, the RDQS path104) from a memory device102, in accordance with various embodiments. The electronic device100may comprise any electronic device that uses a memory and a processor, such as a central processor unit (CPU) or a graphics processing unit (GPU). For instance, the electronic device100may comprise, without limitation, a computer (e.g., a server computer, a client computer, a personal computer (PC), a tablet computer, a laptop computer, a netbook), a set-top box (STB), a personal digital assistant (PDA), an entertainment media system, a cellular telephone, a smart phone, a mobile device, a wearable device (e.g., a smart watch), a smart home device (e.g., a smart appliance), other smart devices, a web appliance, a network router, a network switch, a network bridge, or any electronic device capable of executing instructions with respect to a memory.

As shown, the electronic device100includes a memory device102, the RDQS path104coupled to the memory device102, one or more data (DQ) paths106coupled to the memory device102, a master delay loops108, and a memory controller110. According to various embodiments, the RDQS path104comprises a base delay line component, adder delay line components, rise delay line components, and fall delay line components as described herein. Additionally, for some embodiments, the master delay loops108comprises at least two master delay loops that are used to determine information (e.g., VT drift information) for the RDQS path104and to update (e.g., adjust) codes of one or more delay line components of the RDQS path104. Any one or more of the components described may be implemented using hardware alone or a combination of hardware and software. Moreover, any two or more components of the electronic device100may be combined into a single component, and the functions described herein for a single component may be subdivided among multiple components.

To avoid obscuring illustrated embodiments with unnecessary detail, various functional components (e.g., modules) that are not germane to conveying an understanding of the illustrated embodiments may have been omitted from the figures described herein. Various additional functional components may be supported by the electronic device100to facilitate additional functionality that is not specifically described herein.

The memory device102comprises one or more memory cells or memory devices, each of which may comprise some form of random access memory (RAM), such as Dynamic Random-Access Memory (DRAM) or Static Random-Access Memory (SRAM). Though illustrated as a separate component, for some embodiments, the RDQS path104and the one or more DQ paths106can form part of the memory device102. For some embodiments, the memory device102comprises DDR Dynamic Random-Access Memory (DRAM), such as Double Data Rate 3 (DDR3), Double Data Rate 4 (DDR4), Low Power Double Data Rate 3 (LPDDR3), and Low Power Double Data Rate 4 (LPDDR4), and Low Power Double Data Rate 5 (LPDDR5).

Though not illustrated, the electronic device100includes a PHY, which can comprise one or more electronic signal paths (e.g., individual lines coupling pins of the memory device102and the memory controller110) such that data, address, command, protocol, control, clock, and other information can be carried between the memory device102and the memory controller110as electronic signals. The PHY can comprise an interconnect, such as a link or a bus. Among the electronic signals carried, the PHY can carry one or more data signals for data to be written to, or read from, the memory device102(e.g., a memory cell of the memory device102). Additionally, the PHY can carry one or more signals, which can facilitate writing data to, or reading data from, the memory device102(e.g., a memory cell of the memory device102). The PHY can further comprise a memory socket, such as a SIMM or DIMM socket, configured to connect to a particular memory module package. For some embodiments, at least one of the RDQS path104and the one or more DQ paths106forms part of the PHY.

The memory controller110manages exchange of data to and from the memory device102. To facilitate this, the memory controller110can exchange data, address, command, protocol, control, clock, and other information with the memory device102over various paths, including the RDQS path104or the one or more DQ paths106. For some embodiments, the RDQS path104and the one or more DQ paths106facilitate exchange of data to be read from the memory device102.

For various embodiments, the RDQS path104and the one or more DQ paths106couple the memory controller110to the memory device102. The one or more DQ paths106can provide (e.g., convey) one or more data signals that carry data bits to be written to the memory device102for storage, and can provide (e.g., convey) one or more data signals that carry data bits read from the memory device102. For some embodiments, the RDQS path104provide (e.g., convey) data strobe signals for sampling the data bits from the data signals provided by the one or more DQ paths106. For some embodiments, such as where the memory device102comprises one or more DDR memory devices, a given data signal on an individual data path (of the one or more DQ paths106) can carry two data bits per clock cycle to or from the memory device102, where a data strobe signal provided (e.g., conveyed) by the DQS path (e.g., RDQS path104) can be generated based on the clock cycle.

More regarding some embodiments of the RDQS path104and the one or more DQ paths106is described below with respect to the other figures described herein.

FIG.2is a diagram illustrating an example read data strobe (RDQS) path202having variation compensation and delay lines, in accordance with various embodiments.FIG.2also illustrates example data (DQ) paths204associated with the RDQS path202, which can provide data signals carrying data bits (e.g., with respect to different data bit positions of a data word) read from a memory device (e.g.,102). For instance, the DQ paths204can comprise eight data paths for data bit positions 7:0 (positions 7 through 0) for an 8-bit data word (e.g., DQ<7:0>), with each DQ path204comprising a receiver (RX) buffer250(e.g., buffers X1<7:0>), which can operatively couple to a corresponding DQ pin (e.g., a corresponding pad) of a memory device (e.g., DQ_PAD<7:0>). The DQ paths204can include an additional data path for a data mask inversion (DMI) signal, which can comprise a receiver (RX) buffer250(e.g., buffer X1<8>) that operatively couples to a corresponding DMI pin (e.g., pad) of a memory device (e.g., DMI_PAD). As shown, for various embodiments, the DQ paths204do not include a replica of one or more logic blocks or logic gates of the RDQS path202.

During operation, the RDQS path202can receive a read DQ strobe (RDQS) signal from the memory device, where the received RDQS signal can serve as a clock signal for providing different data strobe signals (e.g., RDQS_R<X>, RDQS_F<X>, RDQS_DMI_R, RDQS_DMI_F) for sampling data bits from different data signals provided (e.g., conveyed) by the DQ paths204—data signals for different data bit positions (e.g., DQ<7:0>) read from a memory device and a DMI signal provided (e.g., conveyed) by the memory device. Where the memory device is a DDR memory device, the RDQS path202provides two read DQ strobe (RDQS) signals for each individual path included by the DQ paths204. For instance, a DQ<X> path for data bit position X can have a RDQS signal (e.g., rise RDQS signal) that enables a data bit to be sampled from a data signal of the DQ<X> path at a rising edge of the RDQS signal received by the RDQS path202, and a RDQS signal (e.g., fall RDQS signal) that enables a data bit to be sampled from the same data signal (of DQ<X> path) at a falling edge of the RDQS signal received by the RDQS path202. In particular, for a data signal provided (e.g., conveyed) by a DQ<X> path, a RDQS signal for sampling a data bit from the data signal on a rising edge of a strobe signal can be designated by RDQS_R<X> inFIG.2, and a RDQS signal for sampling a data bit from the data signal on a falling edge of the strobe signal can be designated by RDQS_F<X> inFIG.2. Likewise, the RDQS signals for sampling bits from a data signal provided (e.g., conveyed) by the DMI path can use a rising edge RDQS signal designated by RDQS_DMI_R, and a falling edge RDQS signal designated by RDQS_DMI_F.

In accordance with various embodiments, the RDQS path202comprises a base delay line component216(BASE DL), a plurality of adder delay line components220(ADDER DLs), and a plurality of delay line components230that include rise delay line components (R_DLs) and fall delay line components (F_DLs). The base delay line component216can be operatively coupled (via the RX buffer210and the clock gate212) to an output of the memory device that provides a read data strobe signal. Additionally, the base delay line component216can be used to provide (e.g., introduce) skew between data signal provided by the DQ paths204and a RDQS signal received by the RDQS path202, which is a common delay in the RDQS path202for all data paths of the DQ paths204. Each adder data line component can be used to provide (e.g., introduce) de-skewing per a data path of the DQ paths204. With respect to a given data path of the DQ paths204, a rise delay line component (e.g.,234) and a fall delay line component (e.g.,238) can compensate for duty cycle distortion (DCD) present in the RDQS path202by creating offset between a rise edge RDQS signal received by the rise delay line component and a fall edge RDQS signal being received by the fall delay line component. Each individual delay line component of the RDQS path204can be adjusted based on a code (e.g., delay line code) associated with the individual delay line component.

As shown, the RDQS path202comprises the RX buffer210for receiving a RDQS signal from the memory device, a clock gate212(CK gate212) operatively coupled to an output of the RX buffer210, a level down shifter214operatively coupled to an output of the clock gate212, the base delay line component216operatively coupled to an output of the level shifter214, and a tree of buffers218that operatively couples an output of the base delay line component216to design for test (DFT) multiplexers (e.g., DFT mux222) of the RDQS path202. Additionally, the RDQS path202comprises the adder delay line components220, where each of the adder delay line components220is operatively coupled to an output of a corresponding DFT multiplexer (e.g., the adder delay line component224is operatively coupled to an output of the DFT mux222). The RDQS path202comprises single-ended to differential converter (SD) components (e.g., SD232) that are each operatively coupled to a corresponding output of one of the adder delay line components220. Each SD component operatively couples one rise delay line component (e.g., rise delay line component234) and one fall delay line component (e.g., fall delay line component240) for an individual path included by the DQ paths204(e.g., DQ<0> path). In particular, an individual rise delay line component (e.g.,234) can output a rising-edge read data strobe signal for sampling a data bit, from a data signal provided by a data path in the DQ paths204(e.g., DQ<0> path) corresponding to the individual rise delay line component, on a rising edge of the read data strobe signal. An individual fall delay line component (e.g.,238) can output a falling-edge read data strobe signal for sampling a data bit, from a data signal provided by a data path in the DQ paths204(e.g., DQ<0> path) corresponding to the individual fall delay line component, on a falling edge of the read data strobe signal received by the RDQS path204.

The RDQS path202also comprises level up shifters, each of which is operatively coupled to an output of a different one of the components230. For instance, a level up shifter236is operatively coupled to an output of the rise delay line component234and outputs a RDQS signal (RDQS_R<0>) for sampling a data bit from a data signal provided by the DQ<0> path on a rising edge of the RDQS signal received by the RDQS path202. A level up shifter238is operatively coupled to an output of the fall delay line component238and outputs a RDQS signal (RDQS_F<0>) for sampling a data bit from a data signal provided by the DQ<0> path on a falling edge of the RDQS signal received by the RDQS path202.

According to some embodiments, components216,218,222,220,230,232are in a regulated supply domain (VDDR) while the remaining components are in a core supply domain (VDD). In comparison to the core supply domain, the regulated supply domain can be used to minimize the timing loss due to power supply noise induced jitter. The crossing from the core supply domain to the regulated supply domain is facilitate via the level down shifter214, while the crossing from the regulated supply domain to core supply domain is facilitated via the level up shifters236and238.

FIGS.3,4,5A, and5Bare diagrams illustrating example master delay loops for use with a read data strobe (RDQS) path, in accordance with various embodiments. Referring now toFIG.3, a first master delay loop (MDL)300comprises a first master delay line component310, and a first phase detector314that is operatively coupled to an output of the first master delay line component310. The first master delay line component310can receive a clock signal, and generate a first delayed clock signal based on the clock signal and a first master delay line code of the first master delay line component310. The first phase detector314can determine a first phase difference between the clock signal and the first delayed clock signal, where the first MDL300can be configured to apply a first code update to the first master delay line code based on the first phase difference. The clock signal can be generated by a phase-lock loop (PLL) clock generator, and the frequency of the clock signal can be ½ the data rate.

A second master delay loop (MDL)302comprises a second master delay line component320, a network of components322that is operatively coupled to an output of the second master delay line component320, and a second phase detector324that is operatively coupled to an output of the network of components322. For some embodiments, the network of components322can model one or more logic gates or logic blocks (e.g., combinatorial logic) included by the RDQS path but not included by an individual data path of the set of data paths (e.g., DQ paths204). The second master delay line component320can receive the clock signal (same as the first master delay line component310), and generate a second delayed clock signal based on the clock signal and a second master delay line code of the second master delay line component320. The network of components322can generate a third delayed clock signal based on the second delayed clock signal from the second master delay line component320. The second phase detector324can determine a second phase difference between the clock signal and the third delayed clock signal, where the second MDL302can be configured to apply a second code update to the second master delay line code based on the second phase difference.

According to various embodiments, the first and the second MDLs300,302facilitate updates (e.g., adjustments) to codes of one or more of the base delay line component (e.g.,216), the plurality of adder delay line components (e.g.,220), the plurality of rise delay line components (e.g.,230), and the plurality of fall delay line components (e.g.,230) of a RDQS path (e.g.,202). In particular, the first MDL300can be used to determine (e.g., obtain) VT drift information of one or more delay elements included by the RDQS path based on a code of the first master delay line component310(also referred to as MW code) that controls a delay applied by the first master delay line component310in the first MDL300. A second MDL302can be used to determine (e.g., obtain) VT drift information of one or more delay elements included by the RDQS path and VT drift information of one or more logic gates or logic blocks of the network of components322.

At initialization of the first MDL300, the MW code can be adjusted (e.g., by microcontroller, which can implement a full state machine) until a phase difference Z1 (e.g., first phase difference) between points A and B is equal to 2π radians (e.g., delay difference between A and B is 2 unit intervals (UI), where 1 UI is equal to 1/data rate). Similarly, at initialization of the second MDL302, the MR code can be adjusted (e.g., by microcontroller, which can implement a full state machine) until a phase difference Z2 (e.g., second phase difference) between points A and B is equal to 2π radians. The resulting, initial MW and MR codes can be referred to herein as MWIcode and MRIcode.

During an initial training process of the RDQS path (e.g.,202), codes of the delay line components of the RDQS path can be updated (e.g., adjusted) to initially train the relative position of data signals on DQ paths and data strobe signals on the RDQS path such that the data strobe signals positioned at the center of data bits carried by the data signals. A microcontroller (not shown) can facilitate this training process, and determine one or more code updates for the base delay line code, adder delay line codes of the plurality of adder delay line components, rise delay line codes of the plurality of rise delay line components, and fall delay line codes of the plurality of fall delay line components. More regarding the initial training of codes of the delay line components of the RDQS path is illustrated and described with respect toFIG.10.

After some time, when voltage and temperature (VT) drifts, the MW code and the MR code can be adjusted again (e.g., by microcontroller) until the phase differences between points A and B reaches 2π radians again. In this way, some embodiments compensate for an increase of delay in the network of components322after the VT drift by adjusting the MR code (e.g., decreasing the MR code) to decrease the delay applied by the second master delay line component320, and compensate for a decrease of delay in the network of components322after the VT drift by adjusting the MR code (e.g., increasing the MR code) to increase the delay applied by the second master delay line component320. The resulting MW and MR codes (obtained after VT drift) can be referred herein as MWFand MRF. Based on the MWFcode and the MRFcode, the codes of the delay line components of the RDQS path can be updated (e.g., adjusted) such that the relative position of data signals on DQ paths and data strobe signals on the RDQS path is maintained after VT drift. For example, a microcontroller (not shown) can be used to determine one or more code updates for the base delay line code, adder delay line codes of the plurality of adder delay line components, rise delay line codes of the plurality of rise delay line components, and fall delay line codes of the plurality of fall delay line components based on the first master delay line code (e.g., MWFcode) and the second master delay line code (e.g., MRFcode). Herein, codes of delay line components of a RDQS path updated based on the first master delay line code (e.g., MW code) and the second master delay line code (e.g., MR code) can be referred to as secondary codes, as these codes are determined or updated based on VT drift information provided by the first and the second master delay line codes.

The following provides calculations performed (e.g., by a microcontroller) to use the first master delay line code (e.g., MW code) and the second master delay line code (e.g., MR code) to update the codes of the delay line components of the RDQS path. In particular, the following calculations in Table 1 can be used to compensate for delay change due to VT drift in delay elements used in the RDQS path (e.g.,202).

TABLE 1VariablesMWI= MW code at initialization,MWF= MW code after VT driftMRI= MR code at initialization,MRF= MR code after VT drift,DEI= Delay element's delay at initialization (ps),DEF= Delay element's delay after VT drift (ps),SI= Secondary code of a delay line component (e.g.,base, adder, rise, fall) at initialization,SF= Secondary code of the delay line component afterVTdrift,CI= Combo delay at initialization (ps),CF= Combo delay after VT drift (ps)Master DelayGiven that in the first master delay line component,Loopdelay difference between A and B = 2UI:CalculationsMWI* DEI= 2UI, MWF* DEF= 2UIAs a such:MWI* DEI= MWF* DEF(Equation 1)SecondaryDelay provided by delay line components of RDQSCodepath after VT drift needs to be equal to the delayCalculationprovided by the delay line components provided atinitialization. This means that:SF* DEF= SI* DEI(Equation2)Based on Equation1 and Equation2, we determine:SF= SI* (MWF/MWI) (Equation3)Secondary code of all delay line components (e.g.,base, adder, rise and fall delay line components) can beupdated using Equation3.
By use of Equation3 of Table 1, various embodiments can use the first and the second MDLs300,302to update secondary codes of the base, adder, rise and fall delay line components of a RDQS path to compensate for delay change due to VT drift in delay elements of the RDQS path.

After using Formula 3 to update secondary codes of the base, adder, rise and fall delay line components of a RDQS path, the following calculations in Table 2 can be used to compensate for delay change due to VT drift in logic blocks and logic gates (e.g., combinatorial logic) in the RDQS path (e.g.,202). In particular, some embodiments use the calculations of Table 2 to update the code of the base delay line component for delay change due to VT drift in logic blocks and logic gates in the RDQS path.

TABLE 2VariablesMWI= MW code at initialization,MWF= MW code after VT driftMRI= MR code at initialization,MRF= MR code after VT drift,DEI= Delay element's delay at initialization (ps),DEF= Delay element's delay after VT drift (ps),SI= Secondary code of a delay line component (e.g.,base, adder, rise, fall) at initialization,SF= Secondary code of the delay line component afterVT drift,CI= Combo delay at initialization (ps),CF= Combo delay after VT drift (ps)VT DriftDelay of second master delay line component +Logic DelayDelay of logic blocks and logic gates of RDQS pathEvaluation(logic delay):N * UI {where “N” depends on a divider ratio; the valueof N can depend on the data rate and can be selected toavoid false locking of a read side MDL; e.g., for 8533Mbps , N can be 6}MRI* DEI+ CI= N * UI , MRF* DEF+ CF= N * UIMRI* DEI+ CI= MRF* DEF+ CFCI− CF= MRF* DEF− MRI* DEICI− CF= DEF* (MRF− {MRI* DEI/DEF})This results in Equation 4:CI− CF= DEF* (MRF− {MRI* MWF/MWI})[where (DEI/DEF) of Equation3 is substitutedwith (MWF/MWR) from Formula 3)]CalculationsEquation 4 provides the VT drift information of delayfor Com-of logic blocks and logic gates of RDQS path (logicpensatingdelay). This delay can be adjusted against the delayfor VTprovided by the base delay line component. ForDrift ofexample, if after VT drift, logic delay reduces, the codeLogic Delayfor the base delay line component can be increased tocompensate for the logic delay decrease, so that the totaldelay remains constant.Accordingly, based on Equation 4:CI− CF= DEF* (MRF− {MRI* MWF/MWI})Logic delay change in units of delay elements:ΔC = (CI− CF)/ DEFΔC = MRF− {MRI* MWF/MWI} (Equation 5)Accordingly, if (MRF/MRI) > (MWF/MWI), the code ofthe base delay line component is increased, else the codeof the base delay line component is decreased.The code of the base delay line component is the oneobtained using Equation 3 plus ΔC:SF+ ΔC (Equation 6)
By use of Equation 6 of Table 2, various embodiments can use the first and the second MDLs300,302to update secondary code of the base delay line component of a RDQS path to compensate for delay change due to VT drift in logic blocks and logic gates of the RDQS path.

Depending on the embodiment, the frequency with which secondary codes are updated can depend on a memory system's timing margins (e.g., more margin means secondary updates can be triggered less frequently) and how fast the memory system's voltage and temperature drifts. For some embodiments, the MR and MW codes are monitored, and secondary code updates are triggered in response to a MR or MW code changing more than a predetermined threshold value (e.g., user defined threshold value).

Where the delay of the network of components322is larger than 2UI, the second MDL302can lead to an inaccurate determination of a MR code (e.g., false locking of the MR code) to a value corresponding to a phase difference higher than 2π radians (e.g., 4π radians, 6π radians, and the like) rather than a phase difference of 2π radians. To avoid such inaccuracies (e.g., false locking of MR code), some embodiments can divide the clock signal by a factor that depends on the frequency value of the clock signal and the characterization of the network of components322across process, voltage, and temperature (PVT). An example of a second MDL that divides a clock signal is illustrated and described with respect toFIG.5.

Referring now toFIG.4, an example of the network of components322is illustrated. According to various embodiments, the network of components322comprises one or more logic blocks and logic gates of the RDQS path (e.g.,202) that are not included by any of the DQ paths (e.g.,204). By including the network of components322, the second MDL302can enable an embodiment to obviate the need to replicate the network of components322in each of the DQ paths (e.g.,204) as conventional technologies do. As shown, the network of components322comprises a clock gate402, a level down shifter404operatively coupled to the clock gate402, a zero delay element (ZDE)406operatively coupled to the level down shifter404, a series of buffers410operatively coupled to the ZDE406, a design for test (DFT) multiplexer412operatively coupled to the series of buffers410, a ZDE414operatively coupled to the DFT multiplexer412, a single-ended to differential converter (SD)416operatively coupled to the ZDE414, a ZDE418operatively coupled to the SD416, and a level up shifter420operatively coupled to the ZDE418. For some embodiments, the logic blocks and logic gates included by the network of components322represent those present in the RDQS path202ofFIG.2. For instance, the clock gate402can correspond to the clock gate212, the level down shifter404can correspond to the level down shifter214, the ZDE406can correspond to the base delay line component216, the series of buffers410can correspond to the tree of buffers218, the DFT multiplexer412can correspond to the DFT multiplexers (e.g.,222) of the RDQS path202, the ZDE414can correspond to the adder delay line components220, the SD416can correspond to the SDs (e.g.,232) of the RDQS path202, the ZDE418can correspond to rise and fall delay line components230, and the level up shifter420can correspond to the level up shifters (e.g.,236,238) of the RDQS path202.

Referring now toFIG.5A, an example of a second MDL502configured to divide a clock signal is illustrated. Like the second MDL302ofFIG.3, the second MDL502comprises the second master delay line component320, the network of components322that is operatively coupled to an output of the second master delay line component320, and the second phase detector324that is operatively coupled to an output of the network of components322. Unlike the second MDL302ofFIG.3, the second MDL502comprises a frequency divider504that is configured to receive a clock signal and generate a frequency divided clock signal generated based on the clock signal and a selection input value (SEL<1:0>) of the frequency divider504. According to some embodiments, the selection input value is determined based on a factor that depends on the frequency value of the clock signal and the characterization of the network of components322across process, voltage, and temperature (PVT). The following Table 3 presents example selection input values and division ratios based on a data rate of the memory system and the network of components having a delay in the range of 200 ps-600 ps.

TABLE 3Data rateFrequency(Mbps)SEL<1:0>Division Ratio<24002'b 0012400 to 56002'b 0125600 to 85332'b 103>85332'b 114

For instance, at a data rate of 8533 Mbps, with the combinational delay the network of components322varying between 200 ps to 600 ps across PVT, to avoid false locking of the MR code, the clock signal can be divided by the frequency divider504by a division ratio of 3 (e.g., based on the max combinational delay being less than 6UI at a data rate of 8533 Mbps). For some embodiments, the factors and division ratios (e.g., enumerated in Table 3) can be determined based on testing or experimentation of a system.

Referring now toFIG.5B, a multi-mode MDL550is presented, where the multi-mode MDL550is configured to operate as a first MDL (e.g.,300) when set to a first mode, and to operate as a second MDL (e.g.,502) that divides a clock signal (to avoid false code locking) when set to a second mode. For some embodiments, the MDL550combines the functionality of the first MDL (e.g.,300) and the second MDL (e.g.,502) and, accordingly, can be used in place of the first MDL (e.g.,300) and the second MDL (e.g.,502). In doing so, multi-mode MDL550can provide some embodiments with more efficient design (e.g., occupies less circuit design area than have the two separate MDLs). As shown, the multi-mode MDL550comprises a frequency divider552, multiplexers554,556,558, a master DL560, a network of components562, and a phase detector564. For some embodiments, the frequency divider552operates similar to the frequency divider504ofFIG.5A, the master DL560is similar to either the first master DL310or the second master DL320ofFIG.3, the network of components562is similar to the network of components322ofFIG.3, and the phase detector564is similar to either the first phase detector314or the second phase detector324ofFIG.3.

InFIG.5B, an input of the frequency divider552receives a clock signal, an output of the frequency divider552is operatively coupled to a first input of the multiplexer554, and a second input of the multiplexer554receives the clock signal. An output of the multiplexer554is operatively coupled to an input of the master DL560and operatively coupled to a first input and a second input of the multiplexer558. For some embodiments, the multiplexer558is similar to the multiplexer556and intended to function as a dummy multiplexer to help track VT drift of the multiplexer556. For instance, as a dummy multiplexer, the multiplexer558can cancel the delay of the multiplexer556, so that delay of the multiplexer556does not impact the phase difference detected by the phase detector564between clocks between the two circuit networks. An output of the master DL560is operatively coupled to an input of the network of components562and operatively coupled to a second input of the multiplexer556. An output of the network of components562is operatively coupled to a first input of the multiplexer556. An output of the multiplexer556is operatively coupled to a first input of the phase detector564, and output of the multiplexer558is operatively coupled to a second input of the phase detector564.

According to some embodiments, each of the multiplexers554,556,558comprises a multiplexer selection input that receives a MDL_MODE input value of determines a current mode of operation of the multi-mode MDL550. In particular, when the MDL_MODE input value is set to 0, the multi-mode MDL550can operate as a first MDL (e.g.,300) and be used to determine a MW code (e.g., based an update to the master delay line code of the master DL560in view of the phase difference determined by the phase detector564), and when the MDL_MODE input value is set to 1, the multi-mode MDL550can operate as a second MDL (e.g.,502) and be used to determine a MR code (e.g., based an update to the master delay line code of the master DL560in view of the phase difference determined by the phase detector564). During operation, the MDL_MODE input value can be initially set to 0, the multi-mode MDL550can then lock, the MW code can be obtained after the lock, and the MW code can be stored in a separate register. Thereafter, the MDL_MODE input value can be set to 1, an appropriate SEL<1:0> setting can be set (e.g., to avoid false locking of the MR code), and then a fresh relock can be performed to obtain the MR code. In this way, the write and read side MDL codes are obtained at initialization and after VT drift.

FIG.6Apresents a timing diagram that illustrates a case of where false locking of a MR code would result for the second MDL302, which does not include a frequency divider as described herein. For the graphs600, D0 represents a zero code delay of the second MDL302, D1 represents a combination delay at initialization (e.g., 200 ps), D2 represents a combination delay after VT drift (e.g., 250 ps), X represents a delay of the second master delay line component320required for lock at initialization, and Y represents a delay of the second master delay line component320required for lock after VT drift.

FIG.6Bpresents a timing diagram that illustrates a case of where applying an appropriate division ratio (e.g., 3) by the frequency divider504can help avoid false locking of the MR code of the second MDL502, in accordance with various embodiments. For the graphs602, D0 represents a zero code delay of the second MDL502, D1 represents a combination delay at initialization (e.g., 200 ps), D2 represents a combination delay after VT drift (e.g., 250 ps), X represents a delay of the second master delay line component320required for lock at initialization, and Y represents a delay of the second master delay line component320required for lock after VT drift. In particular, the graphs602illustrate that |X−Y| is equal to |D2−D1|, which facilitates correct determination of VT drift information using the second MDL502. Based on the following Table 4, the correct locking of the MR code could be achieved by the second MDL502using a division ratio selection of 3 (SEL<1:0> of the frequency divider504being set to 2′b 10 for a data rate between 5600 to 8533).

TABLE 4Data RateSEL<1:0> ofFrequency(Mbps)Frequency DividerDivision Ratio<24002'b 0012400 to 56002'b 0125600 to 85332'b 103>85332'b 114

FIG.7presents a timing diagram700that illustrate use of pre-amble edges702,704of a read data strobe (RDQS) signal, in accordance with various embodiments. In particular, the timing diagram700shows an example of where pre-amble edges702,704of the RDQS signal are used to sample bits. Various embodiments use the pre-amble edges of the RDQS signal given that the DQ paths (e.g.,202) do not include replica one or more logic blocks and logic gates of RDQS path and, as such, data signals on the DQ paths will arrive earlier than the RDQS signal at the sampling flops. For instance, a 4TWCK or 3TWCK (Time Period of Write Clock) pre-amble edges of the RDQS signal can be used for memory system. Traditionally, 4TWCK and 3TWCK pre-ample edge of the RDQS signal are used to minimize ISI of present within RDQS input/output signals and not used to sample data bits. For some embodiments, after the delay line components of the RDQS are trained, the read gate is enabled such that one or more pre-amble edges of the RDQS signal are used to start sample bits carried by data signals provided by one or more DQ paths.

FIGS.8through10are flowcharts illustrating example methods800,900,1000for a read data strobe (RDQS) path having variation compensation and delay lines, in accordance with various embodiments. For some embodiments, at least some portion of the methods800,900, or1000is performed by a RDQS path similar to the RDQS path described herein, such as the RDQS path202ofFIG.2. Additionally, for some embodiments, one or more operations of at least one of the methods800,900, or1000is performed by a microcontroller (e.g., of the PHY interface or the memory system). Depending on the embodiment, an operation of an example method described herein may be repeated in different ways or involve intervening operations not shown. Though the operations of example methods may be depicted and described in a certain order, the order in which the operations are performed may vary among embodiments, including performing certain operations in parallel. Further, for some embodiments, a method described herein may have more or fewer operations than otherwise depicted.

ReferringFIG.8, the method800illustrates an example of using a read data strobe path, in accordance with various embodiments. At operation802, an initial training process is performed on delay line components of the read data strobe path (e.g., by a microcontroller). Operation802can be performed prior the determination of one or more code updates to delay line components of the read data strobe path. More regarding the initial training process is illustrated and described with respect toFIG.10, and more regarding the determination of code updates to delay line components of the read data strobe path is illustrated and described with respect toFIGS.3and9.

During operation804, one or more data paths (e.g., DQ paths), which are operatively coupled to a memory device, provide one or more data signals carry data bits read from the memory device. During operation806, a read data strobe path (e.g., RDQS path), which is operatively coupled to the memory device, data strobe signals for sampling the data bits from the data signals provided by the one or more data paths. For various embodiments, the read data strobe path comprises a base delay line component, a plurality of adder delay line components operatively coupled to an output of the base delay line component, a plurality of rise delay line components operatively coupled to outputs of the plurality of adder delay line components, and a plurality of fall delay line components operatively coupled to the outputs of the plurality of adder delay line components. As shown, operations810through816can be performed as part of operation806.

At operation810, the read data strobe path generates, by a base delay line component of the read data strobe path, a first delayed data strobe signal based on a first data strobe signal and a base delay line code of the base delay line component. The first data strobe signal can be generated based on a read data strobe signal (e.g., RDQS signal) received by the read data strobe path from the memory device. As noted herein, the read data strobe signal can serve as a clock signal for sampling of data signals on the one or more data paths carrying data bits read from the memory device.

For operation812, the read data strobe path generates, by an individual adder delay line component of the read data strobe path, a second delayed data strobe signal based on a second data strobe signal received by the individual adder delay line component and based on an adder delay line code of the individual adder delay line component. For some embodiments, the individual adder delay line component is operatively coupled to an output of the base delay line component. Additionally, for some embodiments, the second data strobe signal is generated based on the first delayed data strobe signal generated by operation810.

At operation814, the read data strobe path generates, by an individual rise delay line component of the read data strobe path, a third delayed data strobe signal based on a third data strobe signal received by the individual rise delay line component and based on a rise delay line code of the individual rise delay line component. The third delayed data strobe signal can represent a rising-edge data strobe data signal that the individual rise delay line component outputs for sampling data bits from a data signal provided by a data path in the set of data paths that corresponds to the individual rise delay line component. For some embodiments, the individual rise delay line component is operatively coupled to an output of the individual adder delay line component. Additionally, for some embodiments, the third data strobe signal is generated based on the second delayed data strobe signal from the individual adder delay line component, which generated the second delayed data strobe signal during operation812.

With respect to operation816, the read data strobe path generates, by an individual fall delay line component of the read data strobe path, a fourth delayed data strobe signal based on a fourth data strobe signal received by the individual fall delay line component and based on a fall delay line code of the individual fall delay line component. The fourth delayed data strobe signal can represent a falling-edge data strobe data signal that the individual fall delay line component outputs for sampling data bits from a data signal provided by a data path in the set of data paths that corresponds to the individual fall delay line component. For some embodiments, the individual fall delay line component is operatively coupled to an output of the individual adder delay line component. Additionally, for some embodiments, the fourth data strobe signal is generated based on the second delayed data strobe signal from the individual adder delay line component, which generated the second delayed data strobe signal during operation812.

Referring now toFIG.9, the method900illustrates an example of using a first and a second master delay loop (MDL), in accordance with various embodiments. At operation902, a first master delay loop sub-circuit generates, by a first master delay line component of the first master delay loop sub-circuit, a first delayed clock signal based on a clock signal received by the first master delay line component and based on a first master delay line code of the first master delay line component. At operation904, the first master delay loop sub-circuit determines, by a first phase detector of the first master delay loop sub-circuit, a first phase difference between the clock signal (as received by the first phase detector) and the first delayed clock signal from the first master delay line component, which generates the first delayed clock signal during operation902. Accordingly, for some embodiments, the first phase detector is operatively coupled to an output of the first master delay line component.

For operation906, a first code update to the first master delay line code is applied based on the first phase difference. Depending on the embodiment, the first code update can be determined and applied by the first master delay loop sub-circuit or a microcontroller that is separate from the first master delay loop sub-circuit. By updating the first master delay line code based on the first phase difference, the first master delay loop sub-circuit effectively implements a feedback loop. As noted herein, the first master delay line code as updated can be used to determine compensation for VT drift in delay elements of the read data strobe path.

During operation908, a second master delay loop sub-circuit generates, by a second master delay line component of the second master delay loop sub-circuit, a second delayed clock signal based on the clock signal received by the first master delay line component and a second master delay line code of the second master delay line component. At operation910, the second master delay loop sub-circuit generates, by a network of components of the second master delay loop sub-circuit, a third delayed clock signal based on the second delayed clock signal from the second master delay line component (generated during operation908). For some embodiments, the network of components is operatively coupled to an output of the second master delay line component. In various embodiments, the network of components is configured to model one or more logic blocks and logic gates (e.g., combinatorial logic) of the read data strobe path that are not included by an individual data path of the set of data paths. For operation912, the second master delay loop sub-circuit determines, by a second phase detector of the second master delay loop sub-circuit, a second phase difference between the clock signal (as received by the second phase detector) and the third delayed clock signal from the network of components, which generates the third delayed clock signal during operation910. Accordingly, for some embodiments, the second phase detector is operatively coupled to an output of the network of components.

For operation914, a second code update to the second master delay line code is applied based on the second phase difference. Depending on the embodiment, the second code update can be determined and applied by the second master delay loop sub-circuit or a microcontroller that is separate from the second master delay loop sub-circuit. By updating the second master delay line code based on the second phase difference, the second master delay loop sub-circuit effectively implements a feedback loop. As noted herein, the second master delay line code as updated can be used to determine compensation for VT drift in logic blocks and logic gates of the read data strobe path.

Eventually, at operation916, based on the first master delay line code and the second master delay line code, a microcontroller can determine one or more code updates for the base delay line code, adder delay line codes of adder delay line components, rise delay line codes of rise delay line components, and fall delay line codes of fall delay line components of the read data strobe path. For some embodiments, operation916comprises determining, based on the first code update, a first set of code updates for the adder delay line codes of the plurality of adder delay line components, for the rise delay line codes of the plurality of rise delay line components, and for the fall delay line codes of the plurality of fall delay line components, and determining, based on the first code update and the second code update, a third code update to the base delay line code. Depending on the embodiment, operation916can use one or more equations of Table 1 and Table 2 to determine one or more code updates for the base delay line code, the adder delay line components, the rise delay line components, and the fall delay line components.

Referring now toFIG.10, the method1000illustrates an example of initially training codes of delay line components of a read data strobe path, in accordance with various embodiments. For some embodiments, the method1000illustrates an example of an initial training process performed by operation802of the method800. Depending on the embodiment, a microcontroller (e.g., implementing a full state machine) can be used to perform the operations of method1000.

At operation1002, a microcontroller sweeps a base delay line code of a base delay line component (of a read data strobe path) through a range of different possible values while delay line codes of all other delay line components in the read data strobe path are set to a value (e.g., code zero) corresponding to application of zero delay. For instance, while the base delay line code of the base delay line component is swept through the range, the code of all adder delay line components, rise delay line components, and fall delay line components can be set to a value of 0.

During the sweeping performed by operation1002, at operation1004, the microcontroller determines a plurality of value pairs the base delay line code, where each individual value pair of the plurality of value pairs corresponds to a different delayed data strobe signal outputted by the plurality of rise delay line components and the plurality of fall delay line components. For example, during operation1004, the microcontroller can record base delay line codes which causes sampling of leading and trailing edges of all data bits. For instance, the base delay line code recorded for the leading edge of a rise strobe signal for data bit position X can be code LRX, the base delay line code recorded for the trailing edge of the rise strobe signal for data bit position X can be code TRX, the leading edge of a fall strobe signal for data bit position X can be code LFX, and the base delay line code recorded for the trailing edge of the fall strobe signal for data bit position X can be code TFX. In this way, LRXand TRXcan form a value pair for the base delay line code in association with a rise strobe signal for a data path, and LFXand TFXcan form a value pair for the base delay line code in association with a fall strobe signal for the same data path. Accordingly, for nine data bit positions (e.g., eight DQ paths and a DMI path), the microcontroller can record the following codes: (LR0, TR0, LF0, TF0) through (LR8, TR8, LF8, TF8) for data bit positions 0 through 8. Accordingly, LR0can be the leading-edge code for a data signal provided by DQ<0> path sampled using read data strobe signal RDQS_R0, and LF0can be the leading-edge code for the data signal provided by DQ<0> path sampled using read data strobe signal RDQS_F0, TR0can be the trailing-edge code the data signal provided by DQ<0> path sampled using read data strobe signal RDQS_R0, and TF0can be the trailing-edge code for the data signal provided by DQ<0> path sampled using read data strobe signal RDQS_F0. The recording of codes can occur in parallel.

At operation1006, the microcontroller determines, based on the plurality of value pairs, a plurality of average values corresponding to the plurality of value pairs. For example, the microcontroller can determine (e.g., compute) the base delay line code to be DR0=average code value of (LR0, TR0) for obtaining the optimal capturing position for a data signal provided by DQ<0> path using read data strobe signal RDQS_R0. Similar operations can be performed for determining optimal capturing codes DR1, DR2, . . . DR7corresponding to DQ<1> path, DQ<2> path, . . . . DQ<7> path using corresponding read data strobe signals RDQS_R1, RDQS_R2, . . . . RDQS_R7. Likewise, the microcontroller can determine (e.g., compute) the base delay line codes for the rise data strobe signals. For example, the microcontroller can determine the base delay line code to be DF0=average code value of (LF0, TF0) for obtaining the optimal capturing position for a data signal provided by DQ<0> path using read data strobe signal RDQS_F0. Similar operations can be performed for determining optimal capturing codes DF1, DF2, . . . . DF7corresponding to DQ<1> path, DQ<2> path, DQ<7> path using corresponding read data strobe signals RDQS_F1, RDQS_F2, . . . . RDQS_F7.

Thereafter, operations1008through1014determine the initial values for delay line components of the read data strobe path based on the plurality of average values determined by operation1006. In particular, at operation1008, the microcontroller determines a minimum value in the plurality of average values, the minimum value being set as an initial value for the base delay line code. For instance, the microcontroller determines a base delay line code DTRAIN=min (DR0, DR1, . . . . DR8, DF0, DF1, . . . . DF8).

At operation1010, the microcontroller determines, based on the plurality of average values and at least a portion of the plurality of value pairs, initial values for adder delay line codes of the plurality of adder delay line components. For instance, the microcontroller determines codes for each of the adder delay line components 0 through N as follows: ATRAIN_N=min[(DRN−DTRAIN), (DFN−DTRAIN)], where adder delay line component N corresponds to a data path N.

During operation1012, the microcontroller determines, based on at least a portion of the plurality of value pairs, initial values for rise delay line codes of the plurality of rise delay line components. For instance, the microcontroller determines codes for each of rise delay line components 0 through N as follows: RTRAIN_N=DRN−DFNif DRN≥DFNelse 0, where rise delay line component N corresponds to a data path N.

For operation1014, the microcontroller determines, based on at least a portion of the plurality of value pairs, initial values for fall delay line codes of the plurality of fall delay line components. For instance, the microcontroller determines codes for each of fall delay line components 0 through N as follows: FTRAIN_N=DFN−DRNif DRN≤DFNelse 0, where rise delay line component N corresponds to a data path N.

FIG.11is a block diagram illustrating components of a machine1100, according to some example embodiments, able to read instructions from a machine-readable medium (e.g., a machine-readable storage medium) and perform any one or more of the methodologies discussed herein. Specifically,FIG.11shows a diagrammatic representation of the machine1100in the example form of a system, within which instructions1102(e.g., software, a program, an application, an applet, an app, a driver, or other executable code) for causing the machine1100to perform any one or more of the methodologies discussed herein may be executed. For example, the instructions1102include executable code that causes the machine1100to execute one of the methods800,900,1000. In this way, these instructions1102transform the general, non-programmed machine1100into a particular machine programmed to carry out the described and one of the illustrated methods800,900,1000in the manner described herein. The machine1100may operate as a standalone device or may be coupled (e.g., networked) to other machines.

By way of non-limiting example, the machine1100may comprise or correspond to a computer (e.g., a server computer, a client computer, a personal computer (PC), a tablet computer, a laptop computer, or a netbook), a smart phone, a mobile device, or any machine capable of executing the instructions1102, sequentially or otherwise, that specify actions to be taken by the machine1100. Further, while only a single machine1100is illustrated, the term “machine” shall also be taken to include a collection of machines1100that individually or jointly execute the instructions1102to perform any one or more of the methodologies discussed herein.

The machine1100may include processors1104, memory1106, a storage unit1108, and I/O components1110, which may be configured to communicate with each other such as via a bus1112. In an example embodiment, the processors1104(e.g., a central processing unit (CPU), a reduced instruction set computing (RISC) processor, a complex instruction set computing (CISC) processor, a graphics processing unit (GPU), a digital signal processor (DSP), an application specific integrated circuit (ASIC), a radio-frequency integrated circuit (RFIC), another processor, or any suitable combination thereof) may include, for example, a processor1114and a processor1116that may execute the instructions1102. The term “processor” is intended to include multi-core processors1104that may comprise two or more independent processors (sometimes referred to as “cores”) that may execute instructions1102contemporaneously. AlthoughFIG.11shows multiple processors1104, the machine1100may include a single processor with a single core, a single processor with multiple cores (e.g., a multi-core processor), multiple processors with a single core, multiple processors with multiple cores, or any combination thereof.

The memory1106(e.g., a main memory or other memory storage) and the storage unit1108are both accessible to the processors1104such as via the bus1112. The memory1106and the storage unit1108store the instructions1102embodying any one or more of the methodologies or functions described herein. The instructions1102may also reside, completely or partially, within the memory1106, within the storage unit1108, within at least one of the processors1104(e.g., within the processor's cache memory), or any suitable combination thereof, during execution thereof by the machine1100. Accordingly, the memory1106, the storage unit1108, and the memory of the processors1104are examples of machine-readable media.

As used herein, “machine-readable medium” means a device able to store instructions and data temporarily or permanently and may include, but is not limited to, random-access memory (RAM), read-only memory (ROM), buffer memory, flash memory, optical media, magnetic media, cache memory, other types of storage (e.g., erasable programmable read-only memory (EEPROM)), and/or any suitable combination thereof. The term “machine-readable medium” should be taken to include a single medium or multiple media (e.g., a centralized or distributed database, or associated caches and servers) able to store the instructions1102. The term “machine-readable medium” shall also be taken to include any medium, or combination of multiple media, that is capable of storing instructions (e.g., instructions1102) for execution by a machine (e.g., machine1100), such that the instructions, when executed by one or more processors of the machine (e.g., processors1104), cause the machine to perform any one or more of the methodologies described herein (e.g., methods800,900,1000). Accordingly, a “machine-readable medium” refers to a single storage apparatus or device, as well as “cloud-based” storage systems or storage networks that include multiple storage apparatus or devices. The term “machine-readable medium” excludes signals per se.

Furthermore, the “machine-readable medium” is non-transitory in that it does not embody a propagating signal. However, labeling the tangible machine-readable medium as “non-transitory” should not be construed to mean that the medium is incapable of movement—the medium should be considered as being transportable from one real-world location to another. Additionally, since the machine-readable medium is tangible, the medium may be considered to be a machine-readable device.

The I/O components1110may include a wide variety of components to receive input, provide output, produce output, transmit information, exchange information, capture measurements, and so on. The specific I/O components1110that are included in a particular machine1100will depend on the type of the machine1100. For example, portable machines such as mobile phones will likely include a touch input device or other such input mechanisms, while a headless server machine will likely not include such a touch input device. It will be appreciated that the I/O components1110may include many other components that are not specifically shown inFIG.11. The I/O components1110are grouped according to functionality merely for simplifying the following discussion and the grouping is in no way limiting. In various example embodiments, the I/O components1110may include input components1118and output components1120. The input components1118may include alphanumeric input components (e.g., a keyboard, a touch screen configured to receive alphanumeric input, a photo-optical keyboard, or other alphanumeric input components), point-based input components (e.g., a mouse, a touchpad, a trackball, a joystick, a motion sensor, or another pointing instrument), tactile input components (e.g., a physical button, a touch screen that provides location and/or force of touches or touch gestures, or other tactile input components), audio input components, and the like. The output components1120may include visual components (e.g., a display such as a plasma display panel (PDP), a light emitting diode (LED) display, a liquid crystal display (LCD), a projector, or a cathode ray tube (CRT)), acoustic components (e.g., speakers), haptic components (e.g., a vibratory motor, resistance mechanisms), other signal generators, and so forth.

Communication may be implemented using a wide variety of technologies. The I/O components1110may include communication components1122operable to couple the machine1100to a network1124or devices1126via a coupling1128and a coupling1130respectively. For example, the communication components1122may include a network interface component or another suitable device to interface with the network1124. In further examples, the communication components1122may include wired communication components, wireless communication components, cellular communication components, near field communication (NFC) components, Bluetooth® components (e.g., Bluetooth® Low Energy), Wi-Fi® components, and other communication components to provide communication via other modalities. The devices1126may be another machine or any of a wide variety of peripheral devices.

Modules, Components and Logic

Certain embodiments are described herein as including logic or a number of components, modules, or mechanisms. Modules may constitute either software modules (e.g., code embodied on a machine-readable medium or in a transmission signal) or hardware modules. A hardware module is a tangible unit capable of performing certain operations and may be configured or arranged in a certain manner. In example embodiments, one or more computer systems (e.g., a standalone, client, or server computer system) or one or more hardware modules of a computer system (e.g., a processor or a group of processors) may be configured by software (e.g., an application or application portion) as a hardware module that operates to perform certain operations as described herein.

In various embodiments, a hardware module may be implemented mechanically or electronically. For example, a hardware module may comprise dedicated circuitry or logic that is permanently configured (e.g., as a special-purpose processor, such as a field-programmable gate array (FPGA) or an ASIC) to perform certain operations. A hardware module may also comprise programmable logic or circuitry (e.g., as encompassed within a general-purpose processor or other programmable processor) that is temporarily configured by software to perform certain operations. It will be appreciated that the decision to implement a hardware module mechanically, in dedicated and permanently configured circuitry, or in temporarily configured circuitry (e.g., configured by software) may be driven by cost and time considerations.

Accordingly, the term “hardware module” should be understood to encompass a tangible entity, be that an entity that is physically constructed, permanently configured (e.g., hardwired), or temporarily configured (e.g., programmed) to operate in a certain manner and/or to perform certain operations described herein. Considering embodiments in which hardware modules are temporarily configured (e.g., programmed), each of the hardware modules need not be configured or instantiated at any one instance in time. For example, where the hardware modules comprise a general-purpose processor configured using software, the general-purpose processor may be configured as respective different hardware modules at different times. Software may accordingly configure a processor, for example, to constitute a particular hardware module at one instance of time and to constitute a different hardware module at a different instance of time.

Hardware modules can provide information to, and receive information from, other hardware modules. Accordingly, the described hardware modules may be regarded as being communicatively coupled. Where multiple of such hardware modules exist contemporaneously, communications may be achieved through signal transmission (e.g., over appropriate circuits and buses that connect the hardware modules). In embodiments in which multiple hardware modules are configured or instantiated at different times, communications between such hardware modules may be achieved, for example, through the storage and retrieval of information in memory structures to which the multiple hardware modules have access. For example, one hardware module may perform an operation and store the output of that operation in a memory device to which it is communicatively coupled. A further hardware module may then, at a later time, access the memory device to retrieve and process the stored output. Hardware modules may also initiate communications with input or output devices, and can operate on a resource (e.g., a collection of information).

The various operations of example methods described herein may be performed, at least partially, by one or more processors that are temporarily configured (e.g., by software) or permanently configured to perform the relevant operations. Whether temporarily or permanently configured, such processors may constitute processor-implemented modules that operate to perform one or more operations or functions. The modules referred to herein may, in some example embodiments, comprise processor-implemented modules.

Similarly, the methods described herein may be at least partially processor-implemented. For example, at least some of the operations of a method may be performed by one or more processors or processor-implemented modules. The performance of certain of the operations may be distributed among the one or more processors, not only residing within a single machine, but deployed across a number of machines. In some example embodiments, the processor or processors may be located in a single location (e.g., within a home environment, an office environment, or a server farm), while in other embodiments the processors may be distributed across a number of locations.

The one or more processors may also operate to support performance of the relevant operations in a “cloud computing” environment or as a “software as a service” (SaaS). For example, at least some of the operations may be performed by a group of computers (as examples of machines including processors), with these operations being accessible via a network (e.g., the Internet) and via one or more appropriate interfaces (e.g., APIs).

Electronic Apparatus and System

Embodiments may be implemented in digital electronic circuitry, in computer hardware, firmware, or software, or in combinations of them. Embodiments may be implemented using a computer program product, for example, a computer program tangibly embodied in an information carrier, for example, in a machine-readable medium for execution by, or to control the operation of, data processing apparatus, for example, a programmable processor, a computer, or multiple computers.

A computer program can be written in any form of programming language, including compiled or interpreted languages, and it can be deployed in any form, including as a standalone program or as a module, subroutine, or other unit suitable for use in a computing environment. A computer program can be deployed to be executed on one computer or on multiple computers at one site, or distributed across multiple sites and interconnected by a communication network.

In example embodiments, operations may be performed by one or more programmable processors executing a computer program to perform functions by operating on input data and generating output. Method operations can also be performed by, and apparatus of example embodiments may be implemented as, special purpose logic circuitry (e.g., an FPGA or an ASIC).

The computing system can include clients and servers. A client and server are generally remote from each other and typically interact through a communication network. The relationship of client and server arises by virtue of computer programs running on the respective computers and having a client-server relationship to each other. In embodiments deploying a programmable computing system, it will be appreciated that both hardware and software architectures merit consideration. Specifically, it will be appreciated that the choice of whether to implement certain functionality in permanently configured hardware (e.g., an ASIC), in temporarily configured hardware (e.g., a combination of software and a programmable processor), or in a combination of permanently and temporarily configured hardware may be a design choice.

FIG.12is a diagram illustrating one possible design process flow for generating a circuit, including embodiments to implement a read data strobe path from a memory device as described herein, and in various embodiments, to integrate the read data strobe path with a larger integrated circuit comprising different design blocks. As illustrated, the overall design flow1200includes a design phase1210, a device fabrication phase1220, a design verification phase1230, and a device verification phase1240. The design phase1210involves an initial design input operation1201where the basic elements and functionality of a device are determined, as well as revisions based on various analyses and optimization of a circuit design. This design input operation1201is where instances of an EDA circuit design file are used in the design and any additional circuitry is selected. The initial strategy, tactics, and context for the device to be created are also generated in the design input operation1201, depending on the particular design algorithm to be used.

In some embodiments, following an initial selection of design values in the design input operation1201, timing analysis and optimization according to various embodiments occurs in an optimization operation1211, along with any other automated design processes. One such process may be the automated design of a partitioned root search for error locator polynomial functions in RS FEC decoding. As described below, design constraints for blocks of a circuit design generated with design inputs in the design input operation1201may be analyzed using hierarchical timing analysis, according to various embodiments. While the design flow1200shows such optimization occurring prior to a layout instance1212, such hierarchical timing analysis and optimization may be performed at any time to verify operation of a circuit design. For example, in various embodiments, constraints for blocks in a circuit design may be generated prior to routing of connections in the circuit design, after routing, during register transfer level (RTL) operations, or as part of a final signoff optimization or verification prior to a device fabrication operation1222.

After design inputs are used in the design input operation1201to generate a circuit layout, and any optimization operations1211are performed, a layout is generated in the layout instance1212. The layout describes the physical layout dimensions of the device that match the design inputs. This layout may then be used in the device fabrication operation1222to generate a device, or additional testing and design updates may be performed using designer inputs or automated updates based on design simulation1232operations or extraction, 3D modeling, and analysis1244operations. Once the device is generated, the device can be tested as part of device test1242operations, and layout modifications generated based on actual device performance.

As described in more detail below, design updates1236from the design simulation1232, design updates1246from the device test1242, the 3D modeling and analysis1244operations, or the design input operation1201may occur after an initial layout instance1212is generated. In various embodiments, whenever design inputs are used to update or change an aspect of a circuit design, a timing analysis and optimization operation1211may be performed.

For example, in various embodiments, a user may provide an input to a computing device indicating placement of elements of a circuit within a first portion of a circuit design, including description of circuitry for a read data strobe path from a memory device described herein. An output to a display of the computing device may show details of a circuit design, and may further be used to generate results of the timing analysis, or may show recommended optimizations or automatically performed adjustments to the circuit design based on the timing analysis. Further inputs to the computing device may involve adjustments as user design inputs, with additional timing analysis and optimization initiated via user operation of the computing device. In some embodiments, a computing device may be used to generate circuit design files describing circuitry corresponding to embodiments described herein. Such circuit design files may be used as outputs to generate photolithographic masks or other control files and components used to generate circuits that operate in accordance with various embodiments described herein.

Throughout this specification, plural instances may implement components, operations, or structures described as a single instance. Although individual operations of one or more methods are illustrated and described as separate operations, one or more of the individual operations may be performed concurrently, and nothing requires that the operations be performed in the order illustrated. Structures and functionality presented as separate components in example configurations may be implemented as a combined structure or component. Similarly, structures and functionality presented as a single component may be implemented as separate components. These and other variations, modifications, additions, and improvements fall within the scope of the subject matter herein.

Although an overview of the inventive subject matter has been described with reference to specific example embodiments, various modifications and changes may be made to these embodiments without departing from the broader scope of embodiments of the present disclosure.

The embodiments illustrated herein are described in sufficient detail to enable those skilled in the art to practice the teachings disclosed. Other embodiments may be used and derived therefrom, such that structural and logical substitutions and changes may be made without departing from the scope of this disclosure. The detailed description, therefore, is not to be taken in a limiting sense, and the scope of various embodiments is defined only by the appended claims, along with the full range of equivalents to which such claims are entitled.

As used herein, the term “or” may be construed in either an inclusive or exclusive sense. The terms “a” or “an” should be read as meaning “at least one,” “one or more,” or the like. The use of words and phrases such as “one or more,” “at least,” “but not limited to,” or other like phrases shall not be read to mean that the narrower case is intended or required in instances where such broadening phrases may be absent.

Boundaries between various resources, operations, components, engines, and data stores are somewhat arbitrary, and particular operations are illustrated in a context of specific illustrative configurations. Other allocations of functionality are envisioned and may fall within a scope of various embodiments of the present disclosure. In general, structures and functionality presented as separate resources in the example configurations may be implemented as a combined structure or resource. Similarly, structures and functionality presented as a single resource may be implemented as separate resources. These and other variations, modifications, additions, and improvements fall within a scope of embodiments of the present disclosure as represented by the appended claims. The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense.

The description above includes systems, methods, devices, instructions, and computer media (e.g., computing machine program products) that embody illustrative embodiments of the disclosure. In the description, for the purposes of explanation, numerous specific details are set forth in order to provide an understanding of various embodiments of the inventive subject matter. It will be evident, however, to those skilled in the art, that embodiments of the inventive subject matter may be practiced without these specific details. In general, well-known instruction instances, protocols, structures, and techniques are not necessarily shown in detail.