Patent ID: 12245438

DETAILED DESCRIPTION

In some semiconductor manufacturing operations, voids may be formed between layers of material deposited over a substrate, and other materials may be deposited in the voids (e.g., between the layers of material) to form various circuit structures. For example, in some memory applications, voids may be formed between layers of a dielectric material, and features of a memory array, such as access lines or memory cells (e.g., of different levels of the memory array), may be formed from materials deposited between the layers of the dielectric material. However, in some examples, features formed from the layers of dielectric material may lack sufficient mechanical support for subsequent processing, which may be associated with mechanical instability (e.g., buckling, deformation) of the features formed from the layers of dielectric material during processing. In some examples, such mechanical instability may lead to poor tolerances or failure to implement circuit structures of a semiconductor device, among other issues.

In accordance with examples as disclosed herein, a semiconductor device (e.g., a memory die) may include pier structures formed in contact with features formed from alternating layers of materials deposited over a substrate, which may provide mechanical support for subsequent processing. For example, a memory die may include alternating layers of a first material and a second material, which may be formed into various cross-sectional patterns. In some examples, the alternating layers may be formed into a pair of interleaved comb structures. Pier structures may be formed in contact with the cross sectional patterns such that, when either the first material or the second material is removed (e.g., in a selective etching operation) to form voids (e.g., along a direction relative to the substrate), the pier structures provide mechanical support of the cross-sectional pattern of the remaining material. By implementing such pier structures, the voids may be formed with improved stability or tolerances, such that formation of features within the voids (e.g., circuit structures, access lines, memory cells) may be performed with reduced variability or otherwise improved consistency. In some examples, the piers may further act as a separator between memory cells or other features of the memory die. For example, the piers may extend into at least a portion of the interleaved comb structures, and may accordingly act as barriers during subsequent depositions of materials.

Features of the disclosure are initially described in the context of memory devices and arrays with reference toFIGS.1,2,3A, and3B. Features of the disclosure are described in the context of steps of a manufacturing process of a memory array with reference toFIGS.4A-20. These and other features of the disclosure are further illustrated by and described with reference to an apparatus diagram and flowcharts that relate to dense piers for three-dimensional memory arrays as described with reference toFIGS.21-22.

FIG.1illustrates an example of a memory device100that supports dense piers for three-dimensional memory arrays in accordance with examples as disclosed herein. In some examples, the memory device100may be referred to as or include a memory die, a memory chip, or an electronic memory apparatus. The memory device100may be operable to provide locations to store information (e.g., physical memory addresses) that may be used by a system (e.g., a host device coupled with the memory device100, for storing information, for reading information).

The memory device100may include one or more memory cells105that each may be programmable to store different logic states (e.g., a programmed one of a set of two or more possible states). For example, a memory cell105may be operable to store one bit of information at a time (e.g., a logic 0 or a logic 1). In some examples, a memory cell105(e.g., a multi-level memory cell105) may be operable to store more than one bit of information at a time (e.g., a logic 00, logic 01, logic 10, a logic 11). In some examples, the memory cells105may be arranged in an array.

A memory cell105may store a logic state using a configurable material, which may be referred to as a memory element, a storage element, a memory storage element, a material element, a material memory element, a material portion, or a polarity-written material portion, among others. A configurable material of a memory cell105may refer to a chalcogenide-based storage component. For example, a chalcogenide storage element may be used in a phase change memory cell, a thresholding memory cell, or a self-selecting memory cell, among other architectures.

In some examples, the material of a memory cell105may include a chalcogenide material or other alloy including selenium (Se), tellurium (Te), arsenic (As), antimony (Sb), carbon (C), germanium (Ge), silicon (Si), or indium (In), or various combinations thereof. In some examples, a chalcogenide material having primarily selenium (Se), arsenic (As), and germanium (Ge) may be referred to as a SAG-alloy. In some examples, a SAG-alloy may also include silicon (Si) and such chalcogenide material may be referred to as SiSAG-alloy. In some examples, SAG-alloy may include silicon (Si) or indium (In) or a combination thereof and such chalcogenide materials may be referred to as SiSAG-alloy or InSAG-alloy, respectively, or a combination thereof. In some examples, the chalcogenide glass may include additional elements such as hydrogen (H), oxygen (O), nitrogen (N), chlorine (CI), or fluorine (F), each in atomic or molecular forms.

In some examples, a memory cell105may be an example of a phase change memory cell. In such examples, the material used in the memory cell105may be based on an alloy (such as the alloys listed above) and may be operated so as to change to different physical state (e.g., undergo a phase change) during normal operation of the memory cell105. For example, a phase change memory cell105may be associated with a relatively disordered atomic configuration (e.g., a relatively amorphous state) and a relatively ordered atomic configuration (e.g., a relatively crystalline state). A relatively disordered atomic configuration may correspond to a first logic state (e.g., a RESET state, a logic 0) and a relatively ordered atomic configuration may correspond to a second logic state (e.g., a logic state different than the first logic state, a SET state, a logic 1).

In some examples (e.g., for thresholding memory cells105, for self-selecting memory cells105), some or all of the set of logic states supported by the memory cells105may be associated with a relatively disordered atomic configuration of a chalcogenide material (e.g., the material in an amorphous state may be operable to store different logic states). In some examples, the storage element of a memory cell105may be an example of a self-selecting storage element. In such examples, the material used in the memory cell105may be based on an alloy (e.g., such as the alloys listed above) and may be operated so as to undergo a change to a different physical state during normal operation of the memory cell105. For example, a self-selecting memory cell105may have a high threshold voltage state and a low threshold voltage state. A high threshold voltage state may correspond to a first logic state (e.g., a RESET state, a logic 0) and a low threshold voltage state may correspond to a second logic state (e.g., a logic state different than the first logic state, a SET state, a logic 1).

During a write operation (e.g., a programming operation) of a self-selecting or thresholding memory cell105, a polarity used for a write operation may influence (e.g., determine, set, program) a behavior or characteristic of the material of the memory cell105, such as a thresholding characteristic (e.g., a threshold voltage) of the material. A difference between thresholding characteristics of the material of the memory cell105for different logic states stored by the material of the memory cell105(e.g., a difference between threshold voltages when the material is storing a logic state ‘0’ versus a logic state ‘1’) may correspond to the read window of the memory cell105.

The memory device100may include access lines (e.g., row lines115each extending along an illustrative x-direction, column lines125each extending along an illustrative y-direction) arranged in a pattern, such as a grid-like pattern. Access lines may be formed with one or more conductive materials. In some examples, row lines115, or some portion thereof, may be referred to as word lines. In some examples, column lines125, or some portion thereof, may be referred to as digit lines or bit lines. References to access lines, or their analogues, are interchangeable without loss of understanding. Memory cells105may be positioned at intersections of access lines, such as row lines115and the column lines125. In some examples, memory cells105may also be arranged (e.g., addressed) along an illustrative z-direction, such as in an implementation of sets of memory cells105being located at different levels (e.g., layers, decks, planes) along the illustrative z-direction. In some examples, a memory device100that includes memory cells105at different levels may be supported by a different configuration of access lines, decoders, and other supporting circuitry than shown.

Operations such as read operations and write operations may be performed on the memory cells105by activating access lines such as one or more of a row line115or a column line125, among other access lines associated with alternative configurations. For example, by activating a row line115and a column line125(e.g., applying a voltage to the row line115or the column line125), a memory cell105may be accessed in accordance with their intersection. An intersection of a row line115and a column line125, among other access lines, in various two-dimensional or three-dimensional configuration may be referred to as an address of a memory cell105. In some examples, an access line may be a conductive line coupled with a memory cell105and may be used to perform access operations on the memory cell105. In some examples, the memory device100may perform operations responsive to commands, which may be issued by a host device coupled with the memory device100or may be generated by the memory device100(e.g., by a local memory controller150).

Accessing the memory cells105may be controlled through one or more decoders, such as a row decoder110or a column decoder120, among other examples. For example, a row decoder110may receive a row address from the local memory controller150and activate a row line115based on the received row address. A column decoder120may receive a column address from the local memory controller150and may activate a column line125based on the received column address.

The sense component130may be operable to detect a state (e.g., a material state, a resistance state, a threshold state) of a memory cell105and determine a logic state of the memory cell105based on the detected state. The sense component130may include one or more sense amplifiers to convert (e.g., amplify) a signal resulting from accessing the memory cell105(e.g., a signal of a column line125or other access line). The sense component130may compare a signal detected from the memory cell105to a reference135(e.g., a reference voltage, a reference charge, a reference current). The detected logic state of the memory cell105may be provided as an output of the sense component130(e.g., to an input/output component140), and may indicate the detected logic state to another component of the memory device100or to a host device coupled with the memory device100.

The local memory controller150may control the accessing of memory cells105through the various components (e.g., a row decoder110, a column decoder120, a sense component130, among other components). In some examples, one or more of a row decoder110, a column decoder120, and a sense component130may be co-located with the local memory controller150. The local memory controller150may be operable to receive information (e.g., commands, data) from one or more different controllers (e.g., an external memory controller associated with a host device, another controller associated with the memory device100), translate the information into a signaling that can be used by the memory device100, perform one or more operations on the memory cells105and communicate data from the memory device100to a host device based on performing the one or more operations. The local memory controller150may generate row address signals and column address signals to activate access lines such as a target row line115and a target column line125. The local memory controller150also may generate and control various signals (e.g., voltages, currents) used during the operation of the memory device100. In general, the amplitude, the shape, or the duration of an applied signal discussed herein may be varied and may be different for the various operations discussed in operating the memory device100.

The local memory controller150may be operable to perform one or more access operations on one or more memory cells105of the memory device100. Examples of access operations may include a write operation, a read operation, a refresh operation, a precharge operation, or an activate operation, among others. In some examples, access operations may be performed by or otherwise coordinated by the local memory controller150in response to access commands (e.g., from a host device). The local memory controller150may be operable to perform other access operations not listed here or other operations related to the operating of the memory device100that are not directly related to accessing the memory cells105.

In some examples, the memory device100may include pier structures formed in contact with features formed from alternating layers of materials deposited over a substrate, which may provide mechanical support for subsequent processing. For example, a memory device100may include alternating layers of a first material and a second material, which may be formed into various cross-sectional patterns. In some examples, the alternating layers may be formed into a pair of interleaved comb structures. Pier structures may be formed in contact with the cross sectional patterns such that, when either the first material or the second material is removed (e.g., in a selective etching operation) to form voids (e.g., along a direction relative to the substrate), the pier structures provide mechanical support of the cross-sectional pattern of the remaining material. By implementing such pier structures, the voids may be formed with improved stability or tolerances, such that formation of features within the voids (e.g., circuit structures such as the row decoder110or column decoder120, access lines such as the row lines115or the word lines125, memory cells such as the memory cell105) may be performed with reduced variability or otherwise improved consistency. In some examples, the piers may further act as a separator between memory cells105or other features of the memory device100. For example, the piers may extend into at least a portion of the interleaved comb structures, and may accordingly act as barriers during subsequent depositions of materials.

The memory device100may include any quantity of non-transitory computer readable media that support dense piers for three-dimensional memory arrays. For example, a local memory controller150, a row decoder110, a column decoder120, a sense component130, or an input/output component140, or any combination thereof may include or may access one or more non-transitory computer readable media storing instructions (e.g., firmware) for performing the functions ascribed herein to the memory device100. For example, such instructions, if executed by the memory device100, may cause the memory device100to perform one or more associated functions as described herein.

FIGS.2,3A, and3Billustrate an example of a memory array200that supports dense piers for three-dimensional memory arrays in accordance with examples as disclosed herein. The memory array200may be included in a memory device100, and illustrates an example of a three-dimensional arrangement of memory cells105that may be accessed by various conductive structures (e.g., access lines).FIG.2illustrates a top section view (e.g., SECTION A-A) of the memory array200relative to a cut plane A-A as shown inFIGS.3A and3B.FIG.3Aillustrates a side section view (e.g., SECTION B-B) of the memory array200relative to a cut plane B-B as shown inFIG.2.FIG.3Billustrates a side section view (e.g., SECTION C-C) of the memory array200relative to a cut plane C-C as shown inFIG.2. The section views may be examples of cross-sectional views of the memory array200with some aspects (e.g., dielectric structures) removed for clarity. Elements of the memory array200may be described relative to an x-direction, a y-direction, and a z-direction, as illustrated in each ofFIGS.2,3A, and3B. Although some elements included inFIGS.2,3A, and3B are labeled with a numeric indicator, other corresponding elements are not labeled, although they are the same or would be understood to be similar, in an effort to increase visibility and clarity of the depicted features. Further, although some quantities of repeated elements are shown in the illustrative example of memory array200, techniques in accordance with examples as described herein may be applicable to any quantity of such elements, or ratios of quantities between one repeated element and another.

In the example of memory array200, memory cells105and word lines205may be distributed along the z-direction according to levels230(e.g., decks, layers, planes, as illustrated inFIGS.3A and3B). In some examples, the z-direction may be orthogonal to a substrate (not shown) of the memory array200, which may be below the illustrated structures along the z-direction. Although the illustrative example of memory array200includes four levels230, a memory array200in accordance with examples as disclosed herein may include any quantity of one or more levels230(e.g., 64 levels, 128 levels) along the z-direction.

Each word line205may be an example of a portion of an access line that is formed by one or more conductive materials (e.g., one or more metal portions, one or more metal alloy portions). As illustrated, a word line205may be formed in a comb structure, including portions (e.g., projections, tines) extending along the y-direction through gaps (e.g., alternating gaps) between pillars220. For example, as illustrated, the memory array200, may include two word lines205per level230(e.g., according to odd word lines205-a-n1and even word lines205-a-n2for a given level, n), where such word lines205of the same level230may be described as being interleaved (e.g., with portions of an odd word line205-a-n1projecting along the y-direction between portions of an even word line205-a-n2, and vice versa). In some examples, an odd word line205(e.g., of a level230) may be associated with a first memory cell105on a first side (e.g., along the x-direction) of a given pillar220and an even word line (e.g., of the same level230) may be associated with a second memory cell105on a second side (e.g., along the x-direction, opposite the first memory cell105) of the given pillar220. Thus, in some examples, memory cells105of a given level230may be addressed (e.g., selected, activated) in accordance with an even word line205or an odd word line205.

Each pillar220may be an example of a portion of an access line that is formed by one or more conductive materials (e.g., one or more metal portions, one or more metal alloy portions). As illustrated, the pillars220may be arranged in a two-dimensional array (e.g., in an xy-plane) having a first quantity of pillars220along a first direction (e.g., eight pillars along the x-direction, eight rows of pillars), and having a second quantity of pillars220along a second direction (e.g., five pillars along the y-direction, five columns of pillars). Although the illustrative example of memory array200includes a two-dimensional arrangement of eight pillars220along the x-direction and five pillars220along the y-direction, a memory array200in accordance with examples as disclosed herein may include any quantity of pillars220along the x-direction and any quantity of pillars220along the y-direction. Further, as illustrated, each pillar220may be coupled with a respective set of memory cells105(e.g., along the z-direction, one or more memory cells105for each level230). A pillar220may have a cross-sectional area in an xy-plane that extends along the z-direction. Although illustrated with a circular cross-sectional area in the xy-plane, a pillar220may be formed with a different shape, such as having an elliptical, square, rectangular, polygonal, or other cross-sectional area in an xy-plane.

The memory cells105each may include a chalcogenide material. In some examples, the memory cells105may be examples of thresholding memory cells. Each memory cell105may be accessed (e.g., addressed, selected) according to an intersection between a word line205(e.g., a level selection, which may include an even or odd selection within a level230) and a pillar220. For example, as illustrated, a selected memory cell105-aof the level230-a-3may be accessed according to an intersection between the pillar220-a-43and the word line205-a-32.

A memory cell105may be accessed (e.g., written to, read from) by applying an access bias (e.g., an access voltage, Vaccess, which may be a positive voltage or a negative voltage) across the memory cell105. In some examples, an access bias may be applied by biasing a selected word line205with a first voltage (e.g., Vaccess/2) and by biasing a selected pillar220with a second voltage (e.g., −Vaccess/2), which may have an opposite sign relative to the first voltage. Regarding the selected memory cell105-a, a corresponding access bias (e.g., the first voltage) may be applied to the word line205-a-32, while other unselected word lines205may be grounded (e.g., biased to 0V). In some examples, a word line bias may be provided by a word line driver (not shown) coupled with one or more of the word lines205.

To apply a corresponding access bias (e.g., the second voltage) to a pillar220, the pillars220may be configured to be selectively coupled with a sense line215(e.g., a digit line, a column line, an access line extending along the y-direction) via a respective transistor225. In some examples, the transistors225may be vertical transistors (e.g., transistors having a channel along the z-direction, transistors having a semiconductor junction along the z-direction), which may be formed above the substrate of the memory array200using various techniques (e.g., thin film techniques). In some examples, a selected pillar220, a selected sense line215, or a combination thereof may be an example of a selected column line125described with reference toFIG.1(e.g., a bit line).

The transistors225may be activated by gate lines210(e.g., activation lines, selection lines, a row line, an access line extending along the x-direction) coupled with respective gates of a set of the transistors225(e.g., a set along the x-direction). In other words, each of the pillars220may have a first end (e.g., towards the negative z-direction, a bottom end) configured for coupling with an access line (e.g., a sense line215). In some examples, the gate lines210, the transistors225, or both may be considered to be components of a row decoder110(e.g., as pillar decoder components). In some examples, the selection of (e.g., biasing of) pillars220, or sense lines215, or various combinations thereof, may be supported by a column decoder120, or a sense component130, or both.

To apply the corresponding access bias (e.g., −Vaccess/2) to the pillar220-a-43, the sense line215-a-4may be biased with the access bias, and the gate line210-a-3may be grounded (e.g., biased to 0V) or otherwise biased with an activation voltage. In an example where the transistors225are n-type transistors, the gate line210-a-3being biased with a voltage that is relatively higher than the sense line215-a-4may activate the transistor225-a(e.g., cause the transistor225-ato operate in a conducting state), thereby coupling the pillar220-a-43with the sense line215-a-4and biasing the pillar220-a-43with the associated access bias. However, the transistors225may include different channel types, or may be operated in accordance with different biasing schemes, to support various access operations.

In some examples, unselected pillars220of the memory array200may be electrically floating when the transistor225-ais activated, or may be coupled with another voltage source (e.g., grounded, via a high-resistance path, via a leakage path, along an end of the pillars220opposite from the transistors225) to avoid a voltage drift of the pillars220. For example, a ground voltage being applied to the gate line210-a-3may not activate other transistors coupled with the gate line210-a-3, because the ground voltage of the gate line210-a-3may not be greater than the voltage of the other sense lines215(e.g., which may be biased with a ground voltage or may be floating). Further, other unselected gate lines210, including gate line210-a-5as shown inFIG.3A, may be biased with a voltage equal to or similar to an access bias (e.g., −Vread/2, or some other negative bias or bias relatively near the access bias voltage), such that transistors225along an unselected gate line210are not activated. Thus, the transistor225-bcoupled with the gate line210-a-5may be deactivated (e.g., operating in a non-conductive state), thereby isolating the voltage of the sense line215-a-4from the pillar220-a-45, among other pillars220.

In a write operation, a memory cell105may be written to by applying a write bias (e.g., where Vaccess=Vwrite, which may be a positive voltage or a negative voltage) across the memory cell105. In some examples, a polarity of a write bias may influence (e.g., determine, set, program) a behavior or characteristic of the material of the memory cell105, such as the threshold voltage of the material. For example, applying a write bias with a first polarity may set the material of the memory cell105with a first threshold voltage, which may be associated with storing a logic 0. Further, applying a write bias with a second polarity (e.g., opposite the first polarity) may set the material of the memory cell with a second threshold voltage, which may be associated with storing a logic 1. A difference between threshold voltages of the material of the memory cell105for different logic states stored by the material of the memory cell105(e.g., a difference between threshold voltages when the material is storing a logic state ‘0’ versus a logic state ‘1’) may correspond to the read window of the memory cell105.

In a read operation, a memory cell105may be read from by applying a read bias (e.g., where Vaccess=Vread, which may be a positive voltage or a negative voltage) across the memory cell105. In some examples, a logic state of the memory cell105may be evaluated based on whether the memory cell105thresholds in the presence of the applied read bias. For example, such a read bias may cause a memory cell105storing a first logic state (e.g., a logic 0) to threshold (e.g., permit a current flow, permit a current above a threshold current), and may not cause a memory cell105storing a second logic state (e.g., a logic 1) to threshold (e.g., may not permit a current flow, may permit a current below a threshold current).

In some examples, the memory array200may include pier structures formed in contact with features formed from alternating layers of materials deposited over a substrate, which may provide mechanical support for subsequent processing. For example, a memory array200may include alternating layers of a first material and a second material, which may be formed into various cross-sectional patterns. In some examples, the alternating layers may be formed into a pair of interleaved comb structures, such as the word lines205. Pier structures may be formed in contact with the cross sectional patterns such that, when either the first material or the second material is removed (e.g., in a selective etching operation) to form voids (e.g., along a direction relative to the substrate), the pier structures provide mechanical support of the cross-sectional pattern of the remaining material. By implementing such pier structures, the voids may be formed with improved stability or tolerances, such that formation of features within the voids may be performed with reduced variability or otherwise improved consistency. In some examples, the piers may further act as a separator between memory cells105or other features of the memory array200. For example, the piers may extend into at least a portion of the interleaved comb structures, and may accordingly act as barriers during subsequent depositions of materials.

FIGS.4A,4B, and4Cillustrate examples of a step of a manufacturing process of a memory array that supports dense piers for three-dimensional memory arrays in accordance with examples as disclosed herein.

FIG.4Aillustrates a top-down view of a step of the manufacturing process of a memory array400-a. In some cases, the memory array400-amay include an alternating stack of materials formed over a substrate405. For example, the memory array400-amay include one or more layers or tiers of a first material410and one or more layers or tiers of a second material415. The manufacturing process may include forming the stack of materials, for example by depositing each layer of the stack of layers. In some examples, the first material410may be a dielectric material, such as an oxide material. Additionally, the second material415may be an example of another dielectric material, such as a nitride material.

In some cases, the manufacturing process may further include forming a set of cavities420through the stack of materials. For example, the set of cavities420may be formed by performing a vertical etch through the stack of materials using a first etching mask. In some cases, the etching may terminate above the substrate405. That is, the substrate405may not be etched during the etching process.

FIG.4Billustrates a cross-sectional view a step of the manufacturing process of a memory array400-balong section line A-A′, whileFIG.4Cillustrates a cross-sectional view a step of the manufacturing process of a memory array400-calong section line C-C′.FIG.4Amay illustrate the top-down view sectioned through one of the layers of the second material415.

FIGS.5A,5B, and5Cillustrate examples of a step of the manufacturing process of a memory array that supports dense piers for three-dimensional memory arrays in accordance with examples as disclosed herein.

FIG.5Aillustrates a top-down view of a step of the manufacturing process of a memory array500-a. In some examples, the step of the manufacturing process of the memory array500-amay include forming a set of piers505. A pier505may be an example of a support structure, such as a pillar or column of dielectric material which adheres to or supports the stack of materials. In some examples, a pier505may provide mechanical support to the stack of material during subsequent steps of the manufacturing process. For example, a pier505may limit movement of the stack of materials in the x-direction, the y-direction, the z-direction, or any combination thereof.

For example, the manufacturing process may include depositing a pier material, such as a dielectric material, into each of the set of cavities420. The dielectric material may fill the set of cavities420, and may contact each of the layers (e.g., each layer of the first material410and each layer of the second material415). Additionally or alternatively, a pier505may include a dielectric liner material, such as an oxide or a nitride (e.g., the first material410or the second material415), and a filler material, such as an aluminum oxide (AlOx), an oxide, or polysilicon. Accordingly, the set of piers505may provide mechanical support for the stack of materials during subsequent steps of the manufacturing process. In some examples, the dielectric material of the piers505may be the same as the dielectric material of the first material410. Alternatively, the piers505and the first material410may be examples of different materials or combinations of materials. For example, the piers505may include an oxide liner.

In some examples, forming the set of piers505may include a polishing step. For instance, after depositing the pier material, the stack of materials may be polished or planarized, for example using a chemical mechanical polishing (CMP) procedure.

FIG.5Billustrates a cross-sectional view a step of the manufacturing process of a memory array500-balong section line A-A′, whileFIG.5Cillustrates a cross-sectional view a step of the manufacturing process of a memory array500-calong section line C-C′.FIG.5Amay illustrate the top-down view sectioned through one of the layers of the second material415.

FIGS.6A,6B,6C, and6Dillustrate examples of a step of the manufacturing process of a memory array that supports dense piers for three-dimensional memory arrays in accordance with examples as disclosed herein.

FIG.6Aillustrates a top-down view of a step of the manufacturing process of a memory array600-a. In some cases, the memory array600-amay include a set of cavities605. The set of cavities605may be formed by etching (e.g., via a second vertical etch using a second mask) or removing material from the stack of materials (e.g., the first material410and the second material415). In some cases, forming the set of cavities605may expose at least a portion of sidewalls of the piers505, as well exposing portions of the stack of materials (e.g., as illustrated inFIG.6C). Additionally, forming the set of cavities605may expose portions of the substrate405. In some examples, the etching process to form the set of cavities605may be selective to the material of the set of piers505. That is, the etching process may selectively remove material, such as the first material410and the second material410, while preserving the material of the set of piers505(e.g., the second dielectric material). Accordingly, the pattern used to etch the set of cavities605may include a stripe, which may cover at least a portion of the set of piers505. Alternatively, the pattern used to etch the set of cavities605may etching a set of isolated holes (e.g., corresponding to the location of each cavity605of the set of cavities605). In such cases, the etching process may be directional (e.g., etching along the z direction).

In some cases, a length610in the y-direction of each cavity605of the set of cavities605may be less than a length615in the y-direction of each pier505of the set of piers505. For example, each pier505may extend past respective adjacent cavities605, which may provide increased mechanical support (e.g., relative to a pier having a same length as a corresponding cavity), for example by more effectively truncating a memory cell formed in a cavity605(e.g., around a bit line pillar in the cavity605). Accordingly, memory cells formed in a cavity605and in contact with a pier505may be less likely to experience manufacturing defects, which may increase the final density of a manufactured memory array.

Forming the set of cavities605may define a set of interleaved comb structures, such as a first comb structure620-aand a second comb structure620-b. In some cases, each comb structure of the set of interleaved comb structure may include a set of “teeth” or tines extending horizontally (e.g., in the x-direction) from a base. The tines of the first comb structure620-amay alternate (e.g., in the y-direction) with the tines of the second comb structure620-b. The set of interleaved comb structures may correspond to one or more word line plates (e.g., the first comb structure620-amay include a set of first word lines, and the second comb structure620-bmay include a set of second word lines), as described in greater detail with reference toFIGS.8A,8B, and8C. In some examples, forming the set of interleaved comb structures using two etching steps (e.g., the etching of the piers505and the etching of the cavities605) may reduce complexity of the manufacturing process relative to other manufacturing process which may use a greater quantity of etching steps to form a set of interleaved comb structures.

FIG.6Billustrates a cross-sectional view a step of the manufacturing process of a memory array600-balong section line A-A′,FIG.6Cillustrates a cross-sectional view a step of the manufacturing process of a memory array600-balong section line B-B′, andFIG.6Dillustrates a cross-sectional view a step of the manufacturing process of a memory array600-calong section line C-C′.FIG.6Amay illustrate the top-down view sectioned through one of the layers of the second material415.

FIGS.7A,7B, and7Cillustrate examples of a step of the manufacturing process of a memory array that supports dense piers for three-dimensional memory arrays in accordance with examples as disclosed herein.

FIGS.7A and7Billustrates a top-down views of a step of the manufacturing process of a memory array700-a.FIG.7Aillustrates a view of the memory array700-aat a first level corresponding to the second material415, whileFIG.7Billustrates a view of the memory array700-bat a second level corresponding to the first material410. Additionally,FIG.7Cillustrates a cross-sectional view a step of the manufacturing process of a memory array700-calong section line B-B′.

In some cases, the manufacturing process may include removing or exhuming the second material415(e.g., the nitride material). For example, the second material415may be removed using an etching procedure (e.g., an omnidirectional etch, a horizontal etch). In some cases, the process to remove the second material415may be selective to the second material415. That is, other materials of the memory array700-a, such as the first material410, the substrate405, the piers505, or any combination thereof may remain. In some cases, removing the second material415may leave a set of voids705. The set of voids705may separate the layers of the first material410, which may induce stress on the tines of the set of interleaved comb structures.

Accordingly, after the second material415has been removed, the set of piers505may provide mechanical support for the tines of the set of interleaved comb structures. For example, the set of piers505may remain in contact with the layers of the first material410, and may prevent or reduce movement of the tines of the set of comb structures during this and subsequent steps of the manufacturing process.

FIGS.8A,8B, and8Cillustrate examples of a step of the manufacturing process of a memory array that supports dense piers for three-dimensional memory arrays in accordance with examples as disclosed herein.

FIG.8Aillustrates a top-down view of a step of the manufacturing process of a memory array800-a. In some cases, the manufacturing process may include forming a set of word lines or word line plates in the memory array800-a. For example, the manufacturing process may include depositing one or more materials in the set of voids705.

In some examples, an interface material, such as a barrier material805, may be deposited into the set of voids705. The barrier material805may coat or cover portions of the tines of the interleaving comb structure, as illustrated inFIG.8C. For example, the barrier material805may be deposited to be in contact with the layers of the first material of the first comb structure620-aand the second comb structure620-b. In some cases, the barrier material805may be deposited in contact with at a portion of the exposed portions of the set of piers505.

Subsequently, a conductive material810may be deposited in the set of voids705. The conductive material810may be an example of metallic material, such as tungsten (W), and may form the conductive portion of a word line plate. In some case, the conductive material810may be deposited in contact with the barrier material805, and may fill the remaining portions of the set of voids705. The barrier material805may be a conductive material, and may be a ceramic material or ceramic metal. Examples of materials for barrier material805include titanium nitride (TiN), titanium silicon nitride (TiSiN), tungsten nitride (WN), tungsten silicon nitride (WSiN), or other materials. The barrier material805may act as a barrier between the conductive material810and the dielectric materials, such as the first material410and the piers505. The barrier material805and the conductive material810may be deposited to fill most or all of the set of voids705. In some cases, the barrier material805and the conductive material810may fill at least a portion of each cavity of the set of cavities605.

FIG.8Billustrates a top-down view of a step of the manufacturing process of a memory array800-b, whileFIG.8Cillustrates a cross-sectional view a step of the manufacturing process of a memory array800-calong section line B-B′. The top-down view shown inFIG.8Amay correspond to a section of the stack of layers within one of the prior voids705, while the top-down view shown inFIG.8Bmay correspond to a section of the stack of layers within one of the layers of the first material410.

FIGS.9A,9B, and9Cillustrate examples of a step of the manufacturing process of a memory array that supports dense piers for three-dimensional memory arrays in accordance with examples as disclosed herein.

FIG.9Aillustrates a top-down view of a step of the manufacturing process of a memory array900-a. The memory array900-amay illustrate a view at the first level (e.g., as described with reference toFIGS.7A and7B). In some cases, the step of the manufacturing process of the memory array900-amay be performed subsequent to the step of the manufacturing process of the memory array800-aas described with reference toFIG.8A. In some cases, during the step of the manufacturing process of the memory array900-a, at least a portion of the deposited word line materials (e.g., the barrier material805, the conductive material810) may be removed, for example by etching or recessing. In some examples, the recessing may recess the barrier material805and the conductive material810into the set of interleaved comb structures (e.g., as described with reference toFIG.6A). Accordingly, the recessing may form a set of word lines or word line plates, such as a first word line915-a(e.g., an even word line) and a second word line915-c(e.g., an odd word line).

FIG.9Billustrates a top-down view of a step of the manufacturing process of a memory array900-b. The memory array900-bmay illustrate a view at the second level (e.g., as described with reference toFIGS.7A and7B). In some examples, the recessing may expose at least portions of the layers of the first material410. For example, the recessing may remove the barrier material805and the conductive material810from the set of cavities605.

FIG.9Cillustrates a cross-sectional view a step of the manufacturing process of a memory array900-calong section line B-B′. As illustrated inFIG.9C, the recessing may form a set of cavities or recesses905between the layers of the first material410. In some examples, the depths of the recesses905(e.g., in the y-direction) may be such that the piers505(extended above the first material410for clarity) extend beyond the recesses905. That is, the length615of a pier in the y-direction may be greater than a separation910between recesses905on alternate word lines. Accordingly, a memory cell in a recess905may experience greater mechanical stability, which may increase the likelihood of correctly forming a memory cell and thus may increase the final density of a memory array.

FIGS.10A and10Billustrate examples of a step of the manufacturing process of a memory array that supports dense piers for three-dimensional memory arrays in accordance with examples as disclosed herein.

FIG.10Aillustrates a top-down view of a step of the manufacturing process of a memory array1000-a. The memory array1000-amay illustrate a view at the first level (e.g., as described with reference toFIGS.7A and7B). In some cases, the step of the manufacturing process of the memory array1000-amay be performed subsequent to the step of the manufacturing process of the memory array900-aas described with reference toFIG.9A.

The step of the manufacturing process of the memory array1000-amay be part of forming a memory cell at least partially in the recesses905. In some cases, the memory cell may include an electrode material1005may be deposited in each cavity605. The electrode material1005may be an example of a conductive material, and may allow for the flow of current between a storage component of the memory cell (described in greater detail with reference toFIG.17A) and the word line (e.g., the word line915-aor the word line915-b). In some examples, the electrode material1005may be in contact both of the interleaving comb structures. Accordingly, after being deposited, the electrode material1005may be in contact with both the first word line915-aand the second word line915-b.

In some examples, the piers505may act as separators for the cavities605. For example, because the piers505extend beyond the cavities (e.g., in the y-direction), the piers505may act as a barrier for the electrode material1005, such that the electrode material1005deposited in each cavity605are separated by respective piers505.

FIG.10Billustrates a cross-sectional view a step of the manufacturing process of a memory array1000-balong section line B-B′. In some cases, as illustrates inFIG.10B, the electrode material1005may fill the recesses905, and may cover the exposed substrate405in each cavity605.

FIGS.11A and11Billustrate examples of a step of the manufacturing process of a memory array that supports dense piers for three-dimensional memory arrays in accordance with examples as disclosed herein.

FIG.11Aillustrates a top-down view of a step of the manufacturing process of a memory array1100-a. In some cases, the step of the manufacturing process of the memory array1100-amay be performed subsequent to the step of the manufacturing process of the memory array1000-aas described with reference toFIG.9A.FIG.11Billustrates a cross-sectional view a step of the manufacturing process of a memory array1100-balong section line B-B′.

In some cases, the manufacturing process may include a recess or etch of the electrode material1005. For example, the electrode material1005may be recessed to cover a side wall of the word line plate in each recess905. leaving a side wall of the first material410of each layer exposed to the cavity605.

FIGS.12A and12Billustrate examples of a step of the manufacturing process of a memory array that supports dense piers for three-dimensional memory arrays in accordance with examples as disclosed herein. The memory array1200-amay illustrate a view at the first level (e.g., as described with reference toFIGS.7A and7B). In some cases, the step of the manufacturing process of the memory array1200-amay be performed subsequent to the step of the manufacturing process of the memory array1100-aas described with reference toFIG.11A.

The step of the manufacturing process of the memory array1200-amay include depositing a placeholder or sacrificial material1205in the set of cavities605. In some cases, the sacrificial material1205may provide support prior to depositing a storage material, or may hold a place for the storage material for steps of the manufacturing process occurring prior to depositing the storage material. In such cases, at least a portion of the sacrificial material1205may be removed in a subsequent step of the manufacturing process, as described in greater detail with reference toFIG.16. In some examples, the sacrificial material1205may be in contact both of the interleaving comb structures. Accordingly, after being deposited, the sacrificial material1205may be in contact with the electrode material1005for both the first word line915-aand the second word line915-b.

In some examples, the piers505may act as separators for the cavities605. For example, because the piers505extend beyond the cavities (e.g., in the y-direction), the piers505may act as a barrier for the sacrificial material1205, such that the sacrificial materials1205deposited in each cavity605are separated by respective piers505.

FIG.12Billustrates a cross-sectional view a step of the manufacturing process of a memory array1200-balong section line B-B′. In some cases, as illustrates inFIG.12B, the sacrificial material1205may fill the recesses905, and may cover the exposed substrate405in each cavity605.

FIGS.13A and13Billustrate examples of a step of the manufacturing process of a memory array that supports dense piers for three-dimensional memory arrays in accordance with examples as disclosed herein.

FIG.13Aillustrates a top-down view of a step of the manufacturing process of a memory array1300-a. In some cases, the step of the manufacturing process of the memory array1300-amay be performed subsequent to the step of the manufacturing process of the memory array1200-aas described with reference toFIG.12A.FIG.13Billustrates a cross-sectional view a step of the manufacturing process of a memory array1200-balong section line B-B′.

In some cases, the manufacturing process may include a recess or etch of the sacrificial material1205. For example, the sacrificial material1205may be recessed to cover a side wall of the word line plate in each recess905. leaving a side wall of the first material410of each layer exposed to the cavity605.

FIGS.14A,14B,14C, and14Dillustrate examples of a step of the manufacturing process of a memory array that supports dense piers for three-dimensional memory arrays in accordance with examples as disclosed herein.

FIG.14Aillustrates a top-down view of a step of the manufacturing process of a memory array1400-a. In some cases, the memory array1400-amay illustrate a manufacturing step in which a set of pillars1405are formed. The set of pillars may include an electrode material1410, a barrier material1415, and a conductive material1420. In some cases, the electrode material1410may be the same material as the electrode material1005, the barrier material1415may be the same material as the barrier material805, and the conductive material1420may be the same material as the conductive material810. The set of pillars1405may be coupled with bit lines (e.g., via selection transistors in substrate405), and accordingly may be used to access a memory cells of the memory array1400-a. In some cases, the quantity of pillars1405may be equal or substantially equal to the quantity of piers505. That is, there may be approximately one pier505per pillar1405, which may correspond to a dense pier aspect ratio.

In some cases, the set of pillars1405may be formed using one or more steps, as illustrated inFIGS.14B,14C, and14D. For example,FIG.14Billustrates a cross-sectional view a step of the manufacturing process of a memory array1400-balong section line B-B′. The manufacturing process may include depositing the electrode material1410into each of the set of cavities605. In some cases, the electrode material1410may be deposited in contact with each layer of the first material410and the sacrificial material1205of each recess905. Additionally, the electrode material1410may be deposited in contact with the substrate405.

FIG.14Cillustrates a cross-sectional view a step of the manufacturing process of a memory array1400-calong section line B-B′. The manufacturing process may include etching or removing a portion of the electrode material1410in each cavity605. For example, the electrode material1410may be etched to expose the substrate405in each cavity605.

FIG.14Dillustrates a cross-sectional view a step of the manufacturing process of a memory array1400-dalong section line B-B′. The manufacturing process may include depositing one or more materials in the each of the set of cavities605. For example, manufacturing process may include depositing the barrier material1415. In some cases, the barrier material1415may be deposited in contact with the electrode material1410on the side walls of the cavity605. Additionally, the barrier material1415may be depositing in contact with the substrate405.

The manufacturing process may further include depositing the conductive material1420. For example, the conductive material1420may be depositing in contact with the barrier material1415, and may fill the remaining portion of the cavity605. In some cases, forming the set of pillars1405may further include performing a planarization process, for example, using a CMP procedure, to smooth or polish the top of the memory array1400-a.

FIG.15illustrates an example of a top-down view of a step of a manufacturing process of a memory array1500that supports dense piers for three-dimensional memory arrays in accordance with examples as disclosed herein. In some cases, the step of the manufacturing process of the memory array1500may be performed subsequent to the step of the manufacturing process of the memory array1400-das described with reference toFIG.14D.

The step of the manufacturing process of the memory array1500may include forming a set of cavities1505. For example, one or more of the piers505may be removed to form the set of cavities1505, for instance using a vertical etch. In some cases, removing the one or more piers505may expose at least one side wall of each pillar1405, as well as at least one side wall of the electrode material1005and the sacrificial material1205.

Although the example illustrated inFIG.15shows every other pier505being removed, other quantities are contemplated. For example, each pier505may be removed to form the set of cavities1505. In some examples, an intermediate quantity of piers505may be removed (e.g., a quantity between every other pier505and each pier505). In some examples, removing at least every other pier may allow for memory cell formation, as described in greater detail with reference toFIGS.16through19.

FIG.16illustrates an example of a top-down view of a step of a manufacturing process of a memory array1600that supports dense piers for three-dimensional memory arrays in accordance with examples as disclosed herein. In some cases, the manufacturing process may include removing or etching at least a portion of the sacrificial material1205. For example, the manufacturing process may include a lateral recess operation to remove at least a portion of the sacrificial material1205exposed in each cavity1505. In some cases, removing the portion of the sacrificial material1205may form a set of recesses1605in each cavity1505. In some cases, because at least a portion of the sacrificial material1205is in contact with a pier505, each pier505may support a respective sacrificial material1205during the lateral recess.

FIGS.17A,17B, and17Cillustrate examples of a step of a manufacturing process of a memory array that supports dense piers for three-dimensional memory arrays in accordance with examples as disclosed herein.

FIG.17Aillustrates a top-down view of a step of a manufacturing process of a memory array1700-a. In some cases, the step of the manufacturing process of the memory array1700-amay be performed subsequent to the step of the manufacturing process of the memory array1600as described with reference toFIG.16.FIG.17Billustrates a cross-sectional view a step of a manufacturing process of a memory array1700-balong section line B-B′, whileFIG.17Cillustrates a cross-sectional view a step of a manufacturing process of a memory array1700-calong section line C-C′.

The step of the manufacturing process of the memory array1700-amay include depositing a storage material1705in the set of cavities1505. In some cases, the storage material1705may be a material configured to store a logic state of a memory cell, such as a chalcogenide glass or a chalcogenide alloy. In some examples, the storage material1705may be in contact with both of the interleaving comb structures at the step of the manufacturing process illustrated inFIG.17A. Accordingly, after being deposited, the storage material1705may be in contact with both the first word line915-aand the second word line915-b.

In some examples, prior to depositing the storage material1705, the manufacturing process may include pretreating the set of cavities1505, for example by depositing a sealing layer, or by applying a plasma treatment, such as with ammonia (NH3).

FIGS.18A and18Billustrate examples of a step of a manufacturing process of a memory array that supports dense piers for three-dimensional memory arrays in accordance with examples as disclosed herein.

FIG.18Aillustrates a top-down view of a step of a manufacturing process of a memory array1800-a. In some cases, the step of the manufacturing process of the memory array1800-amay be performed subsequent to the step of the manufacturing process of the memory array1700-aas described with reference toFIG.17A.FIG.18Billustrates a cross-sectional view a step of the manufacturing process of a memory array1200-balong section line C-C′.

In some cases, the manufacturing process may include a recess or etch of the storage material1705. For example, the storage material1705may be recessed to form a set of memory cells1805in each of the cavities1505. In some cases, each memory cell1805may be coupled with a pillar1405and a word line915-aor915-b(e.g., a single layer and tine of a comb structure of the set of interleaved comb structures).

FIGS.19A and19Billustrate examples of a step of a manufacturing process of a memory array that supports dense piers for three-dimensional memory arrays in accordance with examples as disclosed herein.

FIG.19Aillustrates a top-down view of a step of a manufacturing process of a memory array1900-a. In some cases, the step of the manufacturing process of the memory array1900-amay be performed subsequent to the step of the manufacturing process of the memory array1800-aas described with reference toFIG.18A.FIG.19Billustrates a cross-sectional view a step of a manufacturing process of a memory array1900-balong section line C-C′.

The step of the manufacturing process of the memory array1900-amay include depositing a sealing material1905, which may be an example of a dielectric material, in the set of cavities1505. In some cases, the sealing material1905may be deposited in contact with each memory cell1805of each cavity1505. Additionally, the sealing material1905may cover the exposed sidewall of each pillar1405(e.g., the sidewall of each pillar1405exposed in each cavity1505). In some examples, the sealing material1905may additionally cover the exposed layers of the first material410and the barrier material805(e.g., the portions exposed by the cavities1505).

FIGS.20A and20Billustrate examples of a step of a manufacturing process of a memory array that supports dense piers for three-dimensional memory arrays in accordance with examples as disclosed herein.

FIG.20Aillustrates a top-down view of a step of a manufacturing process of a memory array2000-a. In some cases, the step of the manufacturing process of the memory array2000-amay be performed subsequent to the step of the manufacturing process of the memory array1900-aas described with reference toFIG.19A.FIG.20Billustrates a cross-sectional view a step of a manufacturing process of a memory array2000-balong section line C-C′.

The step of the manufacturing process of the memory array2000-amay include depositing a gap fill material2005in the set of cavities1505. In some cases, the gap fill material2005may be deposited in contact with the sealing material1905. Additionally, the gap fill material2005may fill the remaining portion of each of the cavities1505. In some cases, the gap fill material2005may be an example of a dielectric material, such as a same material as the piers505. Alternatively, the gap fill material2005may be an example of a different dielectric material.

The sealing material1905along with the gap fill material2005in each cavity1505may form a set of respective dielectric portions. In some cases, forming the set of dielectric portions may further include performing a planarization process, for example, using a CMP procedure, to smooth or polish the top of the memory array2000-a. In some examples, the dielectric portions may have a length in the y direction which is greater than the length615of the cavities605. That is, the dielectric portions may extend at least partially into the word lines915-aand915-b. Accordingly, the dielectric portions may form a single continuous surface between the word lines915-aand915-b.

In some examples, manufacturing a memory array, such as the memory array2000-a, may be performed by manufacturing a set of discrete decks or tiles, which may be joined together to form a memory array. In such examples, different tiles may be isolated from each other, for example by an edge cut. In some cases, the edge cut may be performed using a pier etch (e.g., a same etch used to create the set of cavities420).

In some examples, a cross-sectional area of piers505in an xy-plane may be relatively larger at distances nearer to the substrate405(e.g., due to taper along the z-direction resulting from an etching operation to form cavities605), or edges of piers505along an x-direction, along a y-direction, or along a z-direction may be rounded or chamfered (e.g., due to material removal operations or other processing during operations after forming piers505). In some examples, such tapering, rounding, or chamfering may be apparent at an interface between piers505and other materials, including electrode material1410, barrier material1415, or sacrificial material1205, among other interfacing materials deposited after the formation of the piers505. For example, an interface between piers505and electrode material1510may have a tapered profile with a positive slope (e.g., a slope that is less than vertical) of a surface of pier505and a negative slope (e.g., a slope that is more than vertical) of electrode material1410at the interface.

FIG.21shows a block diagram2100of a process controller2120that supports dense piers for three-dimensional memory arrays in accordance with examples as disclosed herein. The process controller2120may be an example of aspects of a process controller as described with reference toFIGS.1through20. The process controller2120, or various components thereof, may be an example of means for performing various aspects of dense piers for three-dimensional memory arrays as described herein. For example, the process controller2120may include a layer stack formation component2125, a pier formation component2130, a word line formation component2135, a cavity formation component2140, a pillar formation component2145, a memory cell formation component2150, a dielectric portion formation component2155, or any combination thereof. Each of these components may communicate, directly or indirectly, with one another (e.g., via one or more buses).

The layer stack formation component2125may be configured as or otherwise support a means for depositing a stack of layers over a substrate, the stack of layers including alternating layers of a first material and a second material, where the first material includes a dielectric material. The pier formation component2130may be configured as or otherwise support a means for forming a plurality of piers through the stack of layers based at least in part on forming a first plurality of cavities through the stack of layers and filling the first plurality of cavities with a third material, where the third material includes a second dielectric material, and where each of the alternating layers of the first material and the second material is in contact with each pier of the plurality of piers. The word line formation component2135may be configured as or otherwise support a means for forming a plurality of first word lines and a plurality of second word lines based at least in part on removing the second material to form an interleaved pair of comb structures including the first material and a first plurality of voids, and depositing a fourth material in the first plurality of voids. The cavity formation component2140may be configured as or otherwise support a means for forming a second plurality of cavities through the stack of dielectric layers, where a sidewall of each cavity of the second plurality of cavities is in contact with a sidewall of a respective pier of the plurality of piers. The pillar formation component2145may be configured as or otherwise support a means for forming a plurality of pillars in the second plurality of cavities. In some examples, the cavity formation component2140may be configured as or otherwise support a means for forming a third plurality of cavities between the plurality of pillars based at least in part on removing at least some of the piers of the plurality of piers, each cavity of the third plurality of cavities exposing a respective first sidewall of a pillar of the plurality of pillars. The memory cell formation component2150may be configured as or otherwise support a means for forming a plurality of memory cells based at least in part on depositing a memory material in each cavity of the third plurality of cavities, each memory cell of the plurality of memory cells coupled between a pillar of the plurality of pillars and a word line of the plurality of first word lines or the plurality of second word lines. The dielectric portion formation component2155may be configured as or otherwise support a means for forming a plurality of dielectric portions based at least in part on depositing a fourth dielectric material in each cavity of the third plurality of cavities.

In some examples, the dielectric portion formation component2155may be configured as or otherwise support a means for forming a plurality of dielectric seals based at least in part on depositing a fifth dielectric material in each cavity of the third plurality of cavities, where forming the plurality of dielectric portions is performed after forming the plurality of dielectric seals.

In some examples, the memory cell formation component2150may be configured as or otherwise support a means for depositing an electrode material in each cavity of the second plurality of cavities, the electrode material in contact with a first word line of the plurality of first word lines or a second word line of the plurality of second word lines. In some examples, the memory cell formation component2150may be configured as or otherwise support a means for depositing a sacrificial material in contact with the electrode material in each cavity of the second plurality of cavities, where forming the plurality of pillars is performed after depositing the sacrificial material.

In some examples, a length of each cavity of the first plurality of cavities in a first horizontal direction is greater than a length of each cavity of the second plurality of cavities in the first horizontal direction.

In some examples, forming the second plurality of voids includes removing each pier of the plurality of piers.

In some examples, forming the second plurality of voids includes removing alternating piers of the plurality of piers.

In some examples, each cavity of the third plurality of cavities exposes at least portions of respective second and third sidewalls of the pillar of the plurality of pillars.

In some examples, the second dielectric material is the same as the dielectric material.

In some examples, to support forming the plurality of first word lines and forming the plurality of second word lines, the word line formation component2135may be configured as or otherwise support a means for depositing a barrier material in contact with the layers of the first material of the first comb structure and in contact with the layers of the first material of the second comb structure. In some examples, to support forming the plurality of first word lines and forming the plurality of second word lines, the word line formation component2135may be configured as or otherwise support a means for depositing a conductive material in contact with the barrier material to fill remaining portions of the first plurality of voids.

In some examples, to support forming the plurality of pillars, the pillar formation component2145may be configured as or otherwise support a means for depositing an electrode material in contact with walls of the plurality of second cavities. In some examples, to support forming the plurality of pillars, the pillar formation component2145may be configured as or otherwise support a means for depositing a barrier material in contact with the layers of the electrode material in each of the plurality of second cavities. In some examples, to support forming the plurality of pillars, the pillar formation component2145may be configured as or otherwise support a means for depositing a conductive material in contact with the barrier material to fill remaining portions of the plurality of second cavities.

In some examples, the memory material includes a chalcogenide.

FIG.22shows a flowchart illustrating a method2200that supports dense piers for three-dimensional memory arrays in accordance with examples as disclosed herein. The operations of method2200may be implemented by a process controller or its components as described herein. For example, the operations of method2200may be performed by a process controller as described with reference toFIGS.1through21. In some examples, a process controller may execute a set of instructions to control the functional elements of the device to perform the described functions. Additionally or alternatively, the process controller may perform aspects of the described functions using special-purpose hardware.

At2205, the method may include depositing a stack of layers over a substrate, the stack of layers including alternating layers of a first material and a second material, where the first material includes a dielectric material. The operations of2205may be performed in accordance with examples as disclosed herein. In some examples, aspects of the operations of2205may be performed by a layer stack formation component2125as described with reference toFIG.21.

At2210, the method may include forming a plurality of piers through the stack of layers based at least in part on forming a first plurality of cavities through the stack of layers and filling the first plurality of cavities with a third material, where the third material includes a second dielectric material, and where each of the alternating layers of the first material and the second material is in contact with each pier of the plurality of piers. The operations of2210may be performed in accordance with examples as disclosed herein. In some examples, aspects of the operations of2210may be performed by a pier formation component2130as described with reference toFIG.21.

At2215, the method may include forming a plurality of first word lines and a plurality of second word lines based at least in part on removing the second material to form an interleaved pair of comb structures including the first material and a first plurality of voids, and depositing a fourth material in the first plurality of voids. The operations of2215may be performed in accordance with examples as disclosed herein. In some examples, aspects of the operations of2215may be performed by a word line formation component2135as described with reference toFIG.21.

At2220, the method may include forming a second plurality of cavities through the stack of dielectric layers, where a sidewall of each cavity of the second plurality of cavities is in contact with a sidewall of a respective pier of the plurality of piers. The operations of2220may be performed in accordance with examples as disclosed herein. In some examples, aspects of the operations of2220may be performed by a cavity formation component2140as described with reference toFIG.21.

At2225, the method may include forming a plurality of pillars in the second plurality of cavities. The operations of2225may be performed in accordance with examples as disclosed herein. In some examples, aspects of the operations of2225may be performed by a pillar formation component2145as described with reference toFIG.21.

At2230, the method may include forming a third plurality of cavities between the plurality of pillars based at least in part on removing at least some of the piers of the plurality of piers, each cavity of the third plurality of cavities exposing a respective first sidewall of a pillar of the plurality of pillars. The operations of2230may be performed in accordance with examples as disclosed herein. In some examples, aspects of the operations of2230may be performed by a cavity formation component2140as described with reference toFIG.21.

At2235, the method may include forming a plurality of memory cells based at least in part on depositing a memory material in each cavity of the third plurality of cavities, each memory cell of the plurality of memory cells coupled between a pillar of the plurality of pillars and a word line of the plurality of first word lines or the plurality of second word lines. The operations of2235may be performed in accordance with examples as disclosed herein. In some examples, aspects of the operations of2235may be performed by a memory cell formation component2150as described with reference toFIG.21.

At2240, the method may include forming a plurality of dielectric portions based at least in part on depositing a fourth dielectric material in each cavity of the third plurality of cavities. The operations of2240may be performed in accordance with examples as disclosed herein. In some examples, aspects of the operations of2240may be performed by a dielectric portion formation component2155as described with reference toFIG.21.

In some examples, an apparatus as described herein may perform a method or methods, such as the method2200. The apparatus may include features, circuitry, logic, means, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor), or any combination thereof for performing the following aspects of the present disclosure:

Aspect 1: A method, apparatus, or non-transitory computer-readable medium including operations, features, circuitry, logic, means, or instructions, or any combination thereof for depositing a stack of layers over a substrate, the stack of layers including alternating layers of a first material and a second material, where the first material includes a dielectric material; forming a plurality of piers through the stack of layers based at least in part on forming a first plurality of cavities through the stack of layers and filling the first plurality of cavities with a third material, where the third material includes a second dielectric material, and where each of the alternating layers of the first material and the second material is in contact with each pier of the plurality of piers; forming a plurality of first word lines and a plurality of second word lines based at least in part on removing the second material to form an interleaved pair of comb structures including the first material and a first plurality of voids, and depositing a fourth material in the first plurality of voids; forming a second plurality of cavities through the stack of dielectric layers, where a sidewall of each cavity of the second plurality of cavities is in contact with a sidewall of a respective pier of the plurality of piers; forming a plurality of pillars in the second plurality of cavities; forming a third plurality of cavities between the plurality of pillars based at least in part on removing at least some of the piers of the plurality of piers, each cavity of the third plurality of cavities exposing a respective first sidewall of a pillar of the plurality of pillars; forming a plurality of memory cells based at least in part on depositing a memory material in each cavity of the third plurality of cavities, each memory cell of the plurality of memory cells coupled between a pillar of the plurality of pillars and a word line of the plurality of first word lines or the plurality of second word lines; and forming a plurality of dielectric portions based at least in part on depositing a fourth dielectric material in each cavity of the third plurality of cavities.

Aspect 2: The method, apparatus, or non-transitory computer-readable medium of aspect 1, further including operations, features, circuitry, logic, means, or instructions, or any combination thereof for forming a plurality of dielectric seals based at least in part on depositing a fifth dielectric material in each cavity of the third plurality of cavities, where forming the plurality of dielectric portions is performed after forming the plurality of dielectric seals.

Aspect 3: The method, apparatus, or non-transitory computer-readable medium of any of aspects 1 through 2, further including operations, features, circuitry, logic, means, or instructions, or any combination thereof for depositing an electrode material in each cavity of the second plurality of cavities, the electrode material in contact with a first word line of the plurality of first word lines or a second word line of the plurality of second word lines and depositing a sacrificial material in contact with the electrode material in each cavity of the second plurality of cavities, where forming the plurality of pillars is performed after depositing the sacrificial material.

Aspect 4: The method, apparatus, or non-transitory computer-readable medium of any of aspects 1 through 3 where a length of each cavity of the first plurality of cavities in a first horizontal direction is greater than a length of each cavity of the second plurality of cavities in the first horizontal direction.

Aspect 5: The method, apparatus, or non-transitory computer-readable medium of any of aspects 1 through 4 where forming the second plurality of voids includes removing each pier of the plurality of piers.

Aspect 6: The method, apparatus, or non-transitory computer-readable medium of any of aspects 1 through 5 where forming the second plurality of voids includes removing alternating piers of the plurality of piers.

Aspect 7: The method, apparatus, or non-transitory computer-readable medium of any of aspects 1 through 6 where each cavity of the third plurality of cavities exposes at least portions of respective second and third sidewalls of the pillar of the plurality of pillars.

Aspect 8: The method, apparatus, or non-transitory computer-readable medium of any of aspects 1 through 7 where the second dielectric material is the same as the dielectric material.

Aspect 9: The method, apparatus, or non-transitory computer-readable medium of any of aspects 1 through 8 where forming the plurality of first word lines and forming the plurality of second word lines includes operations, features, circuitry, logic, means, or instructions, or any combination thereof for depositing a barrier material in contact with the layers of the first material of the first comb structure and in contact with the layers of the first material of the second comb structure and depositing a conductive material in contact with the barrier material to fill remaining portions of the first plurality of voids.

Aspect 10: The method, apparatus, or non-transitory computer-readable medium of any of aspects 1 through 9 where forming the plurality of pillars includes operations, features, circuitry, logic, means, or instructions, or any combination thereof for depositing an electrode material in contact with walls of the plurality of second cavities; depositing a barrier material in contact with the layers of the electrode material in each of the plurality of second cavities; and depositing a conductive material in contact with the barrier material to fill remaining portions of the plurality of second cavities.

Aspect 11: The method, apparatus, or non-transitory computer-readable medium of any of aspects 1 through 10 where the memory material includes a chalcogenide.

It should be noted that the methods described herein describe possible implementations, and that the operations and the steps may be rearranged or otherwise modified and that other implementations are possible. Further, portions from two or more of the methods may be combined.

An apparatus is described. The following provides an overview of aspects of the apparatus as described herein:

Aspect 12: An apparatus, including: a plurality of first word lines distributed along a vertical direction relative to a substrate, where each of the plurality of first word lines includes a plurality of first word line members extending in a first horizontal direction relative to the substrate, the plurality of first word lines separated by a dielectric material in the vertical direction; a plurality of second word lines distributed along the vertical direction, where each of the plurality of second word lines includes a plurality of second word line members that are interleaved with the plurality of first word line members for a corresponding first word line of the plurality of first word lines, the plurality of second word line members separated from the plurality the plurality of first word line members in a second horizontal direction perpendicular to the first horizontal direction; a plurality of dielectric structures extending in the vertical direction, each dielectric structure of the plurality of dielectric structures in contact with a word line member of the plurality of first word line members for each of the plurality of first word lines and in contact with a respective second word line member of the plurality of second word line members for each of the plurality of second word lines, where a separation between a portion of the respective first word line member in contact with a dielectric structure and a portion of the respective second word line member in contact with the dielectric structure is a first length along the second horizontal direction and a separation between a portion of the respective first word line member not in contact with the dielectric structure and a portion of the respective second word line member not in contact with the dielectric structure is a second length along the second horizontal direction that is less than the first length; a plurality of conductive pillars between the plurality of first word lines and the plurality of second word lines; a first plurality of memory cells, each memory cell of the first plurality of memory cells electrically coupled with a respective word line of the plurality of first word lines and a respective pillar of the plurality of conductive pillars; and a second plurality of memory cells, each memory cell of the second plurality of memory cells electrically coupled with a respective word line of the plurality of second word lines and a respective pillar of the plurality of conductive pillars.

Aspect 13: The apparatus of aspect 12, where the plurality of dielectric structures includes: a first plurality of dielectric portions between a first plurality of adjacent pairs of the plurality of conductive pillars, each of the first plurality of dielectric portions having sidewalls that are a single continuous surface between a plurality of first word line members and a plurality of second word line members; and a second plurality of dielectric portions between a second plurality of adjacent pairs of the plurality of conductive pillars, each of the second plurality of dielectric portions having extensions that extend at least partially between a conductive pillar of the plurality of conductive pillars and the plurality of first word line members and at least partially between the conductive pillar and the plurality of second word line members.

Aspect 14: The apparatus of aspect 13, where each of the extensions of the second plurality of dielectric portions is in contact with one or more of the first plurality of memory cells or one or more of the second plurality of memory cells.

Aspect 15: The apparatus of any of aspects 13 through 14, where each of the second plurality of dielectric portions includes a dielectric seal material and an oxide material.

Aspect 16: The apparatus of aspect 15, where the dielectric seal material forms a perimeter of the second plurality of dielectric portions.

Aspect 17: The apparatus of any of aspects 13 through 16, where each of the first plurality of dielectric portions is separated from one or more of the first plurality of memory cells that are coupled with a first one of the first plurality of adjacent pairs of the plurality of conductive pillars by a material that is different from a material of the first plurality of dielectric portions.

Aspect 18: The apparatus of any of aspects 12 through 17, further including: a plurality of dielectric seals, each dielectric seal of the plurality of dielectric seals between a respective dielectric portion of the plurality of dielectric portions and a respective conductive pillar of the plurality of conductive pillars.

Aspect 19: The apparatus of any of aspects 12 through 18, where each of the plurality of dielectric structures have a third length in the second horizontal direction, the third length greater than the second length.

An apparatus is described. The following provides an overview of aspects of the apparatus as described herein:

Aspect 20: An apparatus having a memory array formed by a process including: depositing a stack of layers over a substrate, the stack of layers including alternating layers of a first material and a second material, where the first material includes a dielectric material; forming a plurality of piers through the stack of layers based at least in part on forming a first plurality of cavities through the stack of layers and filling the first plurality of cavities with a third material, where the third material includes a second dielectric material, and where each of the alternating layers of the first material and the second material is in contact with each pier of the plurality of piers; forming a plurality of first word lines and a plurality of second word lines based at least in part on removing the second material to form an interleaved pair of comb structures including the first material and a first plurality of voids, and depositing a fourth material in the first plurality of voids; forming a second plurality of cavities through the stack of dielectric layers, where a sidewall of each cavity of the second plurality of cavities is in contact with a sidewall of a respective pier of the plurality of piers; forming a plurality of pillars in the second plurality of cavities; forming a third plurality of cavities between the plurality of pillars based at least in part on removing at least some of the piers of the plurality of piers, each cavity of the third plurality of cavities exposing a respective sidewall of a pillar of the plurality of pillars; forming a plurality of memory cells between pillars and word lines based at least in part on depositing a memory material in each cavity of the third plurality of cavities, each pillar of the plurality of pillars coupled with a respective first memory cell of the plurality of memory cells and coupled with a respective second memory cell of the plurality of memory cells; and forming a plurality of dielectric portions based at least in part on depositing a fourth dielectric material in each cavity of the third plurality of cavities.

Aspect 21: The apparatus of aspect 20, where the process further includes: forming a plurality of dielectric seals based at least in part on depositing a fifth dielectric material in each cavity of the third plurality of cavities, where forming the plurality of dielectric portions is performed after forming the plurality of dielectric seals.

Aspect 22: The apparatus of any of aspects 20 through 21, where the process further includes: depositing an electrode material in each cavity of the second plurality of cavities, the electrode material in contact with a first word line of the plurality of first word lines or a second word line of the plurality of second word lines; and depositing a sacrificial material in contact with the electrode material in each of cavity of the second plurality of cavities, where forming the plurality of pillars is performed after depositing the sacrificial material.

Aspect 23: The apparatus of any of aspects 20 through 22, where a length of each cavity of the first plurality of cavities in a first horizontal direction is greater than a length of each cavity of the second plurality of cavities in the first horizontal direction.

Aspect 24: The apparatus of any of aspects 20 through 23, where forming the third plurality of cavities includes removing each pier of the plurality of piers.

Aspect 25: The apparatus of any of aspects 20 through 24, where forming the third plurality of cavities includes removing alternating piers of the plurality of piers.

Information and signals described herein may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof. Some drawings may illustrate signals as a single signal; however, the signal may represent a bus of signals, where the bus may have a variety of bit widths.

The terms “electronic communication,” “conductive contact,” “connected,” and “coupled” may refer to a relationship between components that supports the flow of signals between the components. Components are considered in electronic communication with (or in conductive contact with or connected with or coupled with) one another if there is any conductive path between the components that can, at any time, support the flow of signals between the components. At any given time, the conductive path between components that are in electronic communication with each other (or in conductive contact with or connected with or coupled with) may be an open circuit or a closed circuit based on the operation of the device that includes the connected components. The conductive path between connected components may be a direct conductive path between the components or the conductive path between connected components may be an indirect conductive path that may include intermediate components, such as switches, transistors, or other components. In some examples, the flow of signals between the connected components may be interrupted for a time, for example, using one or more intermediate components such as switches or transistors.

The term “coupling” refers to condition of moving from an open-circuit relationship between components in which signals are not presently capable of being communicated between the components over a conductive path to a closed-circuit relationship between components in which signals are capable of being communicated between components over the conductive path. When a component, such as a controller, couples other components together, the component initiates a change that allows signals to flow between the other components over a conductive path that previously did not permit signals to flow.

The term “isolated” refers to a relationship between components in which signals are not presently capable of flowing between the components. Components are isolated from each other if there is an open circuit between them. For example, two components separated by a switch that is positioned between the components are isolated from each other when the switch is open. When a controller isolates two components, the controller affects a change that prevents signals from flowing between the components using a conductive path that previously permitted signals to flow.

The term “layer” or “level” used herein refers to a stratum or sheet of a geometrical structure (e.g., relative to a substrate). Each layer or level may have three dimensions (e.g., height, width, and depth) and may cover at least a portion of a surface. For example, a layer or level may be a three-dimensional structure where two dimensions are greater than a third, e.g., a thin-film. Layers or levels may include different elements, components, or materials. In some examples, one layer or level may be composed of two or more sublayers or sublevels.

As used herein, the term “electrode” may refer to an electrical conductor, and in some examples, may be employed as an electrical contact to a memory cell or other component of a memory array. An electrode may include a trace, wire, conductive line, conductive layer, or the like that provides a conductive path between elements or components of a memory array.

The devices discussed herein, including a memory array, may be formed on a semiconductor substrate, such as silicon, germanium, silicon-germanium alloy, gallium arsenide, gallium nitride, etc. In some examples, the substrate is a semiconductor wafer. In other examples, the substrate may be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or epitaxial layers of semiconductor materials on another substrate. The conductivity of the substrate, or sub-regions of the substrate, may be controlled through doping using various chemical species including, but not limited to, phosphorous, boron, or arsenic. Doping may be performed during the initial formation or growth of the substrate, by ion-implantation, or by any other doping means.

A switching component or a transistor discussed herein may represent a field-effect transistor (FET) and comprise a three terminal device including a source, drain, and gate. The terminals may be connected to other electronic elements through conductive materials, e.g., metals. The source and drain may be conductive and may comprise a heavily-doped, e.g., degenerate, semiconductor region. The source and drain may be separated by a lightly-doped semiconductor region or channel. If the channel is n-type (i.e., majority carriers are electrons), then the FET may be referred to as a n-type FET. If the channel is p-type (i.e., majority carriers are holes), then the FET may be referred to as a p-type FET. The channel may be capped by an insulating gate oxide. The channel conductivity may be controlled by applying a voltage to the gate. For example, applying a positive voltage or negative voltage to an n-type FET or a p-type FET, respectively, may result in the channel becoming conductive. A transistor may be “on” or “activated” when a voltage greater than or equal to the transistor's threshold voltage is applied to the transistor gate. The transistor may be “off” or “deactivated” when a voltage less than the transistor's threshold voltage is applied to the transistor gate.

The description set forth herein, in connection with the appended drawings, describes example configurations and does not represent all the examples that may be implemented or that are within the scope of the claims. The term “exemplary” used herein means “serving as an example, instance, or illustration,” and not “preferred” or “advantageous over other examples.” The detailed description includes specific details to providing an understanding of the described techniques. These techniques, however, may be practiced without these specific details. In some instances, well-known structures and devices are shown in block diagram form to avoid obscuring the concepts of the described examples.

In the appended figures, similar components or features may have the same reference label. Further, various components of the same type may be distinguished by following the reference label by a dash and a second label that distinguishes among the similar components. If just the first reference label is used in the specification, the description is applicable to any one of the similar components having the same first reference label irrespective of the second reference label.

The functions described herein may be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions may be stored on or transmitted over as one or more instructions or code on a computer-readable medium. Other examples and implementations are within the scope of the disclosure and appended claims. For example, due to the nature of software, functions described herein can be implemented using software executed by a processor, hardware, firmware, hardwiring, or combinations of any of these. Features implementing functions may also be physically located at various positions, including being distributed such that portions of functions are implemented at different physical locations.

For example, the various illustrative blocks and modules described in connection with the disclosure herein may be implemented or performed with a general-purpose processor, a DSP, an ASIC, an FPGA or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general-purpose processor may be a microprocessor, but in the alternative, the processor may be any processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).

As used herein, including in the claims, “or” as used in a list of items (for example, a list of items prefaced by a phrase such as “at least one of” or “one or more of”) indicates an inclusive list such that, for example, a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Also, as used herein, the phrase “based on” shall not be construed as a reference to a closed set of conditions. For example, an exemplary step that is described as “based on condition A” may be based on both a condition A and a condition B without departing from the scope of the present disclosure. In other words, as used herein, the phrase “based on” shall be construed in the same manner as the phrase “based at least in part on.”

Computer-readable media includes both non-transitory computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another. A non-transitory storage medium may be any available medium that can be accessed by a general purpose or special purpose computer. By way of example, and not limitation, non-transitory computer-readable media can comprise RAM, ROM, electrically erasable programmable read-only memory (EEPROM), compact disk (CD) ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other non-transitory medium that can be used to carry or store desired program code means in the form of instructions or data structures and that can be accessed by a general-purpose or special-purpose computer, or a general-purpose or special-purpose processor. Also, any connection is properly termed a computer-readable medium. For example, if the software is transmitted from a website, server, or other remote source using a coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, then the coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave are included in the definition of medium. Disk and disc, as used herein, include CD, laser disc, optical disc, digital versatile disc (DVD), floppy disk and Blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above are also included within the scope of computer-readable media.

The description herein is provided to enable a person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be apparent to those skilled in the art, and the generic principles defined herein may be applied to other variations without departing from the scope of the disclosure. Thus, the disclosure is not limited to the examples and designs described herein, but is to be accorded the broadest scope consistent with the principles and novel features disclosed herein.