Patent ID: 12190405

DETAILED DESCRIPTION

The increase in AI training model complexity and size has brought with it a significant increase in time to train. Multiple platforms with a copy of all or part of the model can work closely in an HPC manner to execute AI training algorithms in a parallel distributed manner. As a result, these platforms communicate with one another by high speed, low latency networks.

FIG.1depicts an example AI training solution. An AI training platform (e.g., System Node) includes 2 CPUs and 8 GPUs and 8 High Speed network interface controllers (NICs) that communicate using Ethernet, InfiniBand, Omni-Path, etc. However, the numbers and ratios of CPUs, GPUs, and NICs may vary. The CPUs, GPUs, and NICs can communicate via a local platform input output (IO) bus (e.g., Peripheral Component Interconnect express (PCIe), Compute Express Link (CXL), or Intel® Ultra Path Interconnect (UPI)). The design of the IO bus can provide CPU, NIC or GPU may to another CPU, NIC or GPU within the platform. However, the throughput performance of the IO bus may vary depending on which pair of devices are interacting. As such, a GPU can be physically proximate to a NIC, such as for frequent communication. One or more integrated NICs may communicate with proprietary protocols, or standardized remote direct memory access (RDMA) protocols (e.g., InfiniBand, remote direct memory access (RDMA) over Converged Ethernet (RoCE), RoCEv2, and so forth).

During AI training workloads, the AI model can be executed in a distributed manner across multiple GPUs within the platform. GPUs can utilize multiple high speed connections (two shown for brevity, but 1-10 or more can be used). Connections can be arranged in an on-platform GPU-to-GPU connection topology. Connections can include direct GPU-to-GPU links (e.g., a point-to-point, multiple-to-multiple, or all-to-all topology) or it may utilize internal or external switches in a variety of other topologies (e.g., CLOS, torus, mesh, etc.). One existing example of such GPU-to-GPU is nvLink (Nvidia®).

System Node platforms can be connected with other system node platforms via switching fabric100. Switching fabric100can provide system node-to-system node communications for distributed AI training applications, access to storage, and access to the control functions (e.g., job scheduling, provisioning, etc.) for the cluster and datacenter. In addition, some deployments may utilize network connectivity of control network102. Control network102can be to a CPU Platform Controller Hub (PCH) and Baseboard Management Controller (BMC) integrated NIC or a discrete NIC (not shown) to manage platform operations such as power utilization, environmentals (e.g., voltage, power, cooling, heater), server shutdown, server boot, server reboot, etc. Control plane network may also be connected to low speed control plane interfaces on switches (not shown) in switching fabric.

FIG.2depicts an on-premises deployment of platforms for AI training or HPC. A High Performance Computing (HPC) cluster can include compute, storage and control plane. Storage, compute and control can be separated virtually or physically. For example, compute can utilize artificial intelligence (AI) communications libraries or Message Passing Interface (MPI). Storage can include parallel filesystem (filesys), filesys routing or bridging. Control plane can perform job management, operating system (OS) provisioning, fabric management, and server and IO device management. Services, such as filesystem (FS server), boot/provisioning, login (e.g., end user access from wide area network (WAN) or local area network (LAN)), Management (Mgmt) nodes can perform fabric management, job scheduling and other functions or services. Mgmt nodes can utilize CPUs without GPUs, but can utilize GPUs.

In cloud deployments in a datacenter or across datacenters, nodes can communicate via a reconfigurable hyperscale switching fabric (e.g., switching fabric100). In the data centers, a server (e.g., boot, filesystem, management (mgmt) node, etc.) can interact with virtual clusters. A server can utilize a discrete NIC connected with a device interface to single fabric for storage, compute and control traffic. Some NICs support RDMA over Converged Ethernet (RoCE), Transmission Control Protocol over Internet Protocol (TCP/IP) support with security, virtualization, etc. One or more of the compute nodes is an instance of the System Node shown inFIG.1.

FIG.3depicts a control plane software stack. Control of system node NICs can be accomplished using a switching fabric100or a dedicated control network102. Management or service nodes can execute centralized software defined networking (SDN) control applications and utilize a control network (e.g.,100or102) and its Ethernet switches to communicate via one or more of the control plane NICs.

In a system node, sockets stack delivers control plane commands to a control plane agent. The control plane agent accesses, by NIC driver APIs, NIC registers and firmware across the PCIe bus to perform control plane operations such as querying telemetry data, configuring port attributes, configuring quality of service (QoS), security specifications, etc. As shown inFIG.3, control plane commands may be delivered to the control plane agents via network interface controller (NIC)300connected to the control plane via switching fabric100or control network102and the control plane agents may perform control plane operations to configure other NICs302(e.g., NICs integrated into one or more GPUs) in the platform. Control plane operations may include topology querying, switch status, and switch configuration. Control plane operations for primary network switches may be communicated via the primary network or via the control network.

At least to reduce latency of communications between GPUs, one or more NICs can be integrated into a GPU so that a same semiconductor die or a system on chip (SoC) can include a GPU and one or more integrated NICs for GPU-to-GPU communications. In some examples, a device interface is not used to provide communications between the NIC and GPU and a bus or other communications medium is used. Note that reference to GPU can instead refer to an XPU or an accelerator. An integrated NIC can use a reliability protocol to communicate with other integrated NICs to copy data from a first memory to a second memory by remote direct memory access (RDMA). Examples of reliability protocols are described herein.

Some example integrated NICs perform topology discovery to discover other integrated NICs. A management node can manage integrated NICs via a fabric. Out of band configuration of integrated NICs can occur. Integrated NICs can be configured to use a device interface such as PCIe or CXL or different even proprietary interfaces in order for the control plane agent to access registers and control operations within the integrated NICs.

FIG.4depicts an example system. A scale out fabric or network520provides communications between compute nodes. Nodes can communicate with a data center via smart NICs or other types of NIC devices. The scale out network may be used to communicate with nodes in a POD. The size of a POD depends on datacenter design, but may typically be 10 s to 1000 s of compute nodes, while the data center can be at a scale of 100,000 s of nodes.

A tenant renting resources to run an AI training job in the cloud may be assigned a subset of compute nodes within a single POD along with other service nodes (Filesystem, job management, etc.) within the data center.

FIG.5depicts an example system. System node500-0can include one or more CPUs502-0to502-P (where P is an integer) and one or more GPUs504-0that communicate with one or more CPUs502-0to502-P and one or more GPUs504-0of one or more other system nodes500-1to500-N (where N is an integer). Various examples of one or more GPUs504-0are described herein at least with respect toFIGS.10A,10B,10C,10D, and/or13.

A smartNIC or other network interface device508-0may provide connectivity using links and features such as RDMA and offloads including hardware and programmable engines. The smartNIC or other network interface device508-0can be used for data center communications between system node500-0and other system nodes500-1to500-N or non-compute nodes (e.g., storage, boot, management, control node, etc.). For example, network interface device508-0can include one or more of: a network interface controller (NIC), a remote direct memory access (RDMA)-enabled NIC, router, switch, forwarding element, infrastructure processing unit (IPU), or data processing unit (DPU). Various examples of network interface devices are described at least with respect toFIG.11. Description of system node500-0can apply to one or more of system nodes500-1to500-N.

GPU-to-GPU connections506-0can be utilized for communications among GPUs of GPUs504-0. Scale-out fabric520can provide communication between one or more of GPUs504-0and one or more GPUs of another system node. One or more of GPUs504-0can be coupled to one or more of GPUs504-0through one or more interfaces or NICs to GPU-to-GPU connections506-0and scale-out fabric520. One or more of GPUs504-0can include multiple interfaces or NICs. A first set of one or more interfaces or NICs built into GPU can connect to GPU-to-GPU connections506-0. GPU-to-GPU connections506-0can transmit and receive communications in a manner consistent with one or more of: Intel® Omni-Path, Ethernet, Nvidia® NVLink, CXL, InfiniBand, or other protocols.

A second set of one or more interfaces or NICs built into GPU can connect to scale-out fabric520. Various examples of interfaces or NICs connected to GPU-to-GPU connections506-0and scale-out fabric520are described with respect toFIGS.7and8. Scale-out fabric520can transmit and receive communications in a manner consistent with one or more of: Intel® Omni-Path, Ethernet, Nvidia® NVLink, CXL, InfiniBand, or other protocols.

As shown in an example perspective of at least one GPU of GPUs504-0, a GPU can include GPU compute circuitry540and at least NIC0and NIC1. Various examples of NIC0and NIC1are described herein at least with respect toFIGS.7,8, and/or11.

NIC0and NIC1can perform remote direct memory read or write operations between memory devices. For example, NIC0can be utilized to read or write data between GPUs of a single system node whereas NIC1can be used to read or write data between GPUs of within a system node or among different system nodes. NIC0can utilize lower security requirements than that of NIC1, For example, for transactions using NIC0and NIC1, virtual address protection can be performed in a memory management unit (MMU). NIC1can utilize virtual local area network (VLAN) tagging and authentication to limit source and destination, VxLANs, access control lists (ACLs), and so forth. NICs0and1can become part of the PCIe (or CXL) topology within a System Node and can be used by CPUs and GPUs in the System Node.

As part of reducing GPU NIC silicon die space and power usage, support for in-band control plane protocols by NIC0and/or NIC1, which are integrated into a GPU, can be reduced. As such, to retain flexibility and performance of control plane protocols, smartNIC508-0(or the optional platform NIC connected to Control Network530) can provide security and control functions for system node500-0. SmartNIC508-0can configure system node NICs, CPUs, GPUs, and other devices with storage protocols, security, control operations based on communications from storage and control network512. A software defined networking (SDN) controller can configure storage protocols, security (e.g., virtual local area networks (VLANs), Virtual Extensible LAN (VXLANs), multi-tenant partitioning, data encryption, etc.), by performing control operations for system nodes500-0to500-N.

Out-of-band management ports of switches of scale out fabric520can be connected to storage and control network512and/or control plane network530for control plane operations such as topology query, switch status, and switch configuration. In the case of topology query, an in-band query to discover a topology of GPU NICs can be performed by control plane packet in-band transmission by GPU NICs, as described at least with respect toFIG.9. By reducing control plane traffic in scale-out fabric520, overhead and latency jitter on scale-out fabric520can be reduced.

For example, scale-out fabric520can support non-standard protocols to reduce overhead and increase message throughput. For example, scale-out fabric520can utilize one or more Protocol-independent Packet Processors (P4) programmable switches to implement changes to Ethernet headers and protocols to remove fields for increased message rate or reduced overhead.

Switches of scale-out fabric520need not use control plane security features such as packet encryption and authentication. Instead, low overhead approaches such as virtual local area network (VLAN) or isolation via routing can prevent cloud tenants from accessing nodes not assigned to them. However, switches of scale-out fabric520can use control plane security features such as packet encryption and authentication.

One or more interfaces or NICs can be built into GPU by formation on a same integrated circuit chip or different integrated circuit chips, same die or different dies, or same package or different packages. GPU and NICs can be communicatively coupled using chip-to-chip communications, die-to-die communications, packet-based communications, communications over a device interface, fabric-based communications, and so forth. A die-to-die communications can be consistent with Embedded Multi-Die Interconnect Bridge (EMIB) or utilize an interposer. GPU-to-GPU connections506-0can be on-platform with the GPUs, whereby GPU-to-GPU connections and optionally related switches could be part of a set of boards and cards of System Node500-0.

Control network530can provide communications involving one or more of: PCH, BMC, voltage control, temperature control (e.g., heating, fans or cooling)), system administrator traffic, system control (e.g., shutdown, boot, reboot). Access to scale-out network530can occur using a NIC integrated into CPUs502-0to502-P.

By use of a network and fabric, GPUs can communicate by low overhead, low latency and high bandwidth via scale out fabric520at least for distributed multi-GPU applications such as HPC or AI-training.

FIG.6depicts an example system. System node600is similar to system node500and includes at least one discrete NIC610-0directly coupled to GPUs504-0. Various examples of one or more GPUs604-0are described herein at least with respect toFIGS.10A,10B,10C,10D, and/or13. A GPU can be flexibly configured to use a variety of types of NICs or connections (e.g., discrete NIC, integrated NIC, Ethernet NIC, Intel® Omnipath, etc.) and a variety of types of interfaces. Configuration of type of NIC or connection to use can occur at one or more: hardware design time, hardware manufacture, system configuration time, runtime, or others.

NIC610-0can provide communication to one or more of GPUs604-0of system node600-0and other GPUs of other system nodes through scale-out fabric520. NIC610-0can be configured with features from third party vendors and such features can include RDMA, low latency memory access, low latency message passing, optimized collective operations, proprietary or standard protocols for high speed low latency communications, etc. NIC610-0can be connected to one or more GPUs604-0via a device interface or can be accessible for use by CPUs502-0to502-P via a device interface. NIC610-0can be implemented as a network interface device and provide communication with protocols beyond those available by NIC0and NIC1and perform additional operations beyond those of NIC0and NIC1, such as accelerator operations or offload operations. For example, NIC610-0can communicate using TCP, RDMA, or proprietary protocols, and can perform data encryption, data decryption, data compression, data de-compression, message tag matching, collectives offloads, or other accelerator operations described herein, and so forth.

FIG.7depicts circuitry of a GPU. For example, GPU compute718can utilize communications subsystem700, that is integrated into a GPU as a NIC or interface. Some examples of GPU compute718can include elements of at leastFIGS.10A,10B,10C,10D, and/or13. A GPU may have more than two or more of subsystem700to increase a number of GPU-to-GPU connections and communications bandwidth.

Communications subsystem700may be configured to transmit and receive a mixture of GPU-to-GPU communications (e.g., via scale-out fabric506) or scale out fabric communications (e.g., via scale-out fabric520). Ratios of mixture of GPU-to-GPU communications or scale out fabric communications can be configurable at runtime or platform design time, allowing flexibility to design and deploy platforms for a specific sets of applications. Communications subsystem700can be configured at boot time at utilize bridges706or Ethernet bridges708.

For example, bridges706can provide communications via fabric for GPU-to-multiple GPU connections. For example, bridges706can provide a network connection such as Intel® XeLink, Intel® Omni-Path, Ethernet, Nvidia® NVLink, CXL, InfiniBand, or other protocols.

Ethernet bridges708can provide at least one Ethernet connection between GPU compute718to one or more GPUs via a scale out network. Ethernet bridges708can perform Ethernet packet processing for transmitted and received packets. The scale out network can be consistent with one or more of: Ethernet, Intel® Omni-Path, Intel® XeLink, Nvidia® NVLink, CXL, InfiniBand, or other protocols. Ethernet bridges708can transmit a mixture of GPU-to-GPU connection traffic (e.g.,506-0) and scale out fabric traffic (e.g.,520) from a port, and a switch710could forward traffic to provide GPU traffic to one or more interfaces722, to scale out fabric via Ethernet bridges708, or to reliability and congestion management circuitries712. A switch could also forward traffic from one interface722to interface724. Interface724can be similar to interface722. While merely interface722and724are shown, more than two interfaces can be utilized by GPU compute718. GPU-to-GPU traffic can be received by switch710and provided to another GPU via switch710associated with the other GPU or via scale-out fabric. Switch710can provide connection to another GPU compute device.

Serdes702can receive packets from a scale out fabric and transmit packets to scale out fabric. Physical layer protocol block704can perform Ethernet media access control (MAC) and physical coding sublayer (PCS) operations for Ethernet packets from Bridges706and/or Ethernet bridges708. In some examples, multiple Serdes are used, allowing multiple connections per instance of subsystem700.

Reliability and congestion management circuitries712can include one or more reliability and congestion management circuitries for communications to or from GPU compute718or memory720. Communications can occur between different addressable memory regions of a same memory device or different addressable memory regions of different memory device. For example, GPU-to-GPU communications for GPUs of a same system can read or write data between different addressable memory regions of a same memory device or different addressable memory regions of different memory device.

Reliability and congestion management circuitries712can perform a reliable transport for communications using GPU-to-GPU connections (e.g., GPU-to-GPU connections506-0) and/or scale-out fabric (e.g., scale-out fabric520), described next. For example, reliable transport can utilize a reliable transport protocol that tracks one or more gaps in received packet sequence numbers using a bitmap and indicates to a sender of packets non-delivered packets to identify a range of delivered packets. The bitmap can identify delivered packets and undelivered packets for one or more connections. Indicating to a sender of packets non-delivered packets to identify a range of delivered packets can include providing negative acknowledgement sequence range indicating a start and end of non-delivered packets. A range of delivered packets can be indicated by providing a sequence range indicating a start and end of non-delivered packets. A range of delivered packets can be identified by providing a sequence range indicating an acknowledgement up to and including a sequence number. Re-transmitting one or more packets can occur based on receipt of an indication of a range of non-delivered packets or timeout. For an example operation of reliability and congestion management circuitries712, see, for example, U.S. Patent Application publication 2022/0085916, entitled “SCALABLE PROTOCOL-AGNOSTIC RELIABLE TRANSPORT.”

Reliability and congestion management circuitries712can provide reliable communications, including performing packet loss recovery and congestion management. Reliable transport technologies can include one or more of: RDMA over Converged Ethernet (RoCE), Transmission Control Protocol (TCP), User Datagram Protocol (UDP), quick UDP Internet Connections (QUIC), High Precision Congestion Control (HPCC) (e.g., Li et al., “HPCC: High Precision Congestion Control” SIGCOMM (2019)), or other reliable transport protocols.

Bridges and direct memory access (DMA) circuitry714can copy data to and from GPU compute718and/or memory720(via interconnect716) using load or store memory semantics and perform control functions (such as fence and flush). In connection with data reads from memory720and writes to memory720, bridges and DMA circuitry714can perform direct memory access operations and apply configured memory access permissions and memory address translation tables (e.g., virtual to physical address translation).

Interconnect716can provide an interface to GPU compute718. The interconnect can include an Intel® Multi-die Fabric Interface (MDFI), CXL, PCIe or other proprietary IO buses internal to the GPU, and so forth. GPUs can be formed on a same or different silicon die than that of interconnect. Interconnect716can provide an interface to GPU computational circuitry718and memory720to bridges and DMA circuitry714.

FIG.8depicts an example of a GPU. GPU compute718and memory720can utilize communication subsystem700and/or PCIe switch800for communications with one or more other GPUs. For example, GPU compute718utilize PCIe switch800to access a discrete NIC (e.g., NIC610-0) to communicate with one or more other GPUs. For example, communications pins of a GPU socket can provide for PCIe connectivity to discrete NIC directly to the GPU.FIG.8shows communications pins can be multiplexed between the communications subsystem700and switch800. Switch800can provide a connection to discrete PCIe NIC via communications pins802, resulting in the discrete NIC being part of the overall platform topology via the connection. For example, where switch800and communication pins802are consistent with PCIe, discrete NIC can be part of the overall platform topology, such that discrete NIC610-0may be used as discussed, at least with respect toFIG.6.FIG.8depicts use of a PCIe interface. However, other examples may make use of CXL, proprietary interfaces or other IO/memory buses and their corresponding switches.

FIG.9depicts an example control plane software stack similar toFIG.3. As in the stack ofFIG.3, control operations and queries may be delivered to the Control Plane Agents via Ethernet NICs901connected to the Control Plane (e.g., network512or530). In addition, switches904of scale-out fabric520may use in-band packets, such as Link Layer Discovery Protocol (LLDP), to identify which GPU NIC906is connected to a given scale-out switch904port. Such topology query operations can permit Centralized SDN Control Plane Application900to identify network topology and connectivity of scale-out fabric520(e.g., which host name and MAC address is connected to a given scale out fabric switch904port). SDN application900may use the network topology and connectivity to further perform telemetry collection, routing determination, react to changes in the network and so forth via operations sent directly to Scale Out Switches904and/or via the Control Plane Agents to NIC Driver908.

Topology discovery can be performed without execution of a full standard TCP/IP network stack on the GPU with integrated NIC906. Instead, a GPU and/or GPU with integrated NIC906can execute an LLDP protocol and perform and manage RDMA communications and a CPU can execute a full TCP/IP stack (e.g., IP forwarding, TCP protocol, UDP protocol, and so forth) for the Control Plane Ethernet NIC901. In some examples, a GPU need only support an LLDP protocol and RDMA communications for integrated NIC906.

FIGS.10A-10Ddepict example GPU compute components.FIG.10Aillustrates a parallel processor1000. The parallel processor1000may be a GPU, GPGPU or the like as described herein. The various components of the parallel processor1000may be implemented using one or more integrated circuit devices, such as programmable processors, application specific integrated circuits (ASICs), or field programmable gate arrays (FPGA).

The parallel processor1000includes a parallel processing unit1002. The parallel processing unit includes an I/O unit1004that enables communication with other devices, including other instances of the parallel processing unit1002. The I/O unit1004may be directly connected to other devices. For instance, the I/O unit1004connects with other devices via the use of a hub or switch interface, such as a memory hub. The connections between the memory hub105and the I/O unit1004form a communication link. Within the parallel processing unit1002, the I/O unit1004connects with a host interface1006and a memory crossbar1016, where the host interface1006receives commands directed to performing processing operations and the memory crossbar1016receives commands directed to performing memory operations.

When the host interface1006receives a command buffer via the I/O unit1004, the host interface1006can direct work operations to perform those commands to a front end1008. In one embodiment the front end1008couples with a scheduler1010, which is configured to distribute commands or other work items to a processing cluster array1012. The scheduler1010configures processing cluster array1012is properly configured and in a valid state before tasks are distributed to the processing clusters of the processing cluster array1012. The scheduler1010may be implemented via firmware logic executing on a microcontroller. The microcontroller implemented scheduler1010is configurable to perform complex scheduling and work distribution operations at coarse and fine granularity, enabling rapid preemption and context switching of threads executing on the processing cluster array1012. Preferably, the host software can prove workloads for scheduling on the processing cluster array1012via one of multiple graphics processing doorbells. In other examples, polling for new workloads or interrupts can be used to identify or indicate availability of work to perform. The workloads can then be automatically distributed across the processing cluster array1012by the scheduler1010logic within the scheduler microcontroller.

The processing cluster array1012can include up to “N” processing clusters (e.g., cluster1014A, cluster1014B, through cluster1014N). At least one of cluster1014A-1014N of the processing cluster array1012can execute a large number of concurrent threads. The scheduler1010can allocate work to the clusters1014A-1014N of the processing cluster array1012using various scheduling and/or work distribution algorithms, which may vary depending on the workload arising for a type of program or computation. The scheduling can be handled dynamically by the scheduler1010or can be assisted in part by compiler logic during compilation of program logic configured for execution by the processing cluster array1012. Optionally, different clusters1014A-1014N of the processing cluster array1012can be allocated for processing different types of programs or for performing different types of computations.

The processing cluster array1012can be configured to perform various types of parallel processing operations. For example, the processing cluster array1012is configured to perform general-purpose parallel compute operations. For example, the processing cluster array1012can include logic to execute processing tasks including filtering of video and/or audio data, performing modeling operations, including physics operations, and performing data transformations.

The processing cluster array1012is configured to perform parallel graphics processing operations. In such embodiments in which the parallel processor1000is configured to perform graphics processing operations, the processing cluster array1012can include additional logic to support the execution of such graphics processing operations, including, but not limited to texture sampling logic to perform texture operations, as well as tessellation logic and other vertex processing logic. Additionally, the processing cluster array1012can be configured to execute graphics processing related shader programs such as, but not limited to vertex shaders, tessellation shaders, geometry shaders, and pixel shaders. The parallel processing unit1002can transfer data from system memory via the I/O unit1004for processing. During processing the transferred data can be stored to on-chip memory (e.g., parallel processor memory1022) during processing, then written back to system memory.

In embodiments in which the parallel processing unit1002is used to perform graphics processing, the scheduler1010may be configured to divide the processing workload into approximately equal sized tasks, to better enable distribution of the graphics processing operations to multiple clusters1014A-1014N of the processing cluster array1012. In some of these embodiments, portions of the processing cluster array1012can be configured to perform different types of processing. For example, a first portion may be configured to perform vertex shading and topology generation, a second portion may be configured to perform tessellation and geometry shading, and a third portion may be configured to perform pixel shading or other screen space operations, to produce a rendered image for display. Intermediate data produced by one or more of the clusters1014A-1014N may be stored in buffers to allow the intermediate data to be transmitted between clusters1014A-1014N for further processing.

During operation, the processing cluster array1012can receive processing tasks to be executed via the scheduler1010, which receives commands defining processing tasks from front end1008. For graphics processing operations, processing tasks can include indices of data to be processed, e.g., surface (patch) data, primitive data, vertex data, and/or pixel data, as well as state parameters and commands defining how the data is to be processed (e.g., what program is to be executed). The scheduler1010may be configured to fetch the indices corresponding to the tasks or may receive the indices from the front end1008. The front end1008can configure the processing cluster array1012to a valid state before the workload specified by incoming command buffers (e.g., batch-buffers, push buffers, etc.) is initiated.

At least one of the one or more instances of the parallel processing unit1002can couple with parallel processor memory1022. The parallel processor memory1022can be accessed via the memory crossbar1016, which can receive memory requests from the processing cluster array1012as well as the I/O unit1004. The memory crossbar1016can access the parallel processor memory1022via a memory interface1018. The memory interface1018can include multiple partition units (e.g., partition unit1020A, partition unit1020B, through partition unit1020N) that can couple to a portion (e.g., memory unit) of parallel processor memory1022. The number of partition units1020A-1020N may be configured to be equal to the number of memory units, such that a first partition unit1020A has a corresponding first memory unit1024A, a second partition unit1020B has a corresponding second memory unit1024B, and an Nth partition unit1020N has a corresponding Nth memory unit1024N. In other embodiments, the number of partition units1020A-1020N may not be equal to the number of memory devices.

The memory units1024A-1024N can include various types of memory devices, including dynamic random-access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), including graphics double data rate (GDDR) memory. Optionally, the memory units1024A-1024N may also include 3D stacked memory, including but not limited to high bandwidth memory (HBM). Persons skilled in the art will appreciate that the specific implementation of the memory units1024A-1024N can vary and can be selected from one of various conventional designs. Render targets, such as frame buffers or texture maps may be stored across the memory units1024A-1024N, allowing partition units1020A-1020N to write portions of a render target in parallel to efficiently use the available bandwidth of parallel processor memory1022. In some embodiments, a local instance of the parallel processor memory1022may be excluded in favor of a unified memory design that utilizes system memory in conjunction with local cache memory.

Optionally, one or more of the clusters1014A-1014N of the processing cluster array1012has the ability to process data that will be written to one or more of the memory units1024A-1024N within parallel processor memory1022. The memory crossbar1016can be configured to transfer the output of at least one of cluster1014A-1014N to one or more of partition unit1020A-1020N or to another cluster1014A-1014N, which can perform additional processing operations on the output. At least one of cluster1014A-1014N can communicate with the memory interface1018through the memory crossbar1016to read from or write to various external memory devices. In one of the embodiments with the memory crossbar1016the memory crossbar1016has a connection to the memory interface1018to communicate with the I/O unit1004, as well as a connection to a local instance of the parallel processor memory1022, enabling the processing units within the different processing clusters1014A-1014N to communicate with system memory or other memory that is not local to the parallel processing unit1002. Generally, the memory crossbar1016may, for example, be able to use virtual channels to separate traffic streams between the clusters1014A-1014N and the partition units1020A-1020N.

While a single instance of the parallel processing unit1002is illustrated within the parallel processor1000, other numbers of instances of the parallel processing unit1002can be included. For example, multiple instances of the parallel processing unit1002can be provided on a single add-in card, or multiple add-in cards can be interconnected. For example, the parallel processor1000can be an add-in device, which may be a graphics card such as a discrete graphics card that includes one or more GPUs, one or more memory devices, and device-to-device or network or fabric interfaces. The different instances of the parallel processing unit1002can be configured to inter-operate even if the different instances have different numbers of processing cores, different amounts of local parallel processor memory, and/or other configuration differences. Optionally, some instances of the parallel processing unit1002can include higher precision floating point units relative to other instances. Systems incorporating one or more instances of the parallel processing unit1002or the parallel processor1000can be implemented in a variety of configurations and form factors, including but not limited to desktop, laptop, or handheld personal computers, servers, workstations, game consoles, and/or embedded systems. An orchestrator can form composite nodes for workload performance using one or more of: disaggregated processor resources, cache resources, memory resources, storage resources, and networking resources.

FIG.10Bis a block diagram of a partition unit1020. The partition unit1020may be an instance of one of the partition units1020A-1020N ofFIG.10A. As illustrated, the partition unit1020includes an L2 cache1021, a frame buffer interface1025, and a ROP1026(raster operations unit). The L2 cache1021is a read/write cache that is configured to perform load and store operations received from the memory crossbar1016and ROP1026. Read misses and urgent write-back requests are output by L2 cache1021to frame buffer interface1025for processing. Updates can also be sent to the frame buffer via the frame buffer interface1025for processing. In one embodiment the frame buffer interface1025interfaces with one of the memory units in parallel processor memory, such as the memory units1024A-1024N ofFIG.10A(e.g., within parallel processor memory1022). The partition unit1020may additionally or alternatively also interface with one of the memory units in parallel processor memory via a memory controller (not shown).

In graphics applications, the ROP1026is a processing unit that performs raster operations such as stencil, z test, blending, and the like. The ROP1026then outputs processed graphics data that is stored in graphics memory. In some embodiments the ROP1026includes or couples with a CODEC1027that includes compression logic to compress depth or color data that is written to memory or the L2 cache1021and decompress depth or color data that is read from memory or the L2 cache1021. The compression logic can be lossless compression logic that makes use of one or more of multiple compression algorithms. The type of compression that is performed by the CODEC1027can vary based on the statistical characteristics of the data to be compressed. For example, in one embodiment, delta color compression is performed on depth and color data on a per-tile basis. In one embodiment the CODEC1027includes compression and decompression logic that can compress and decompress compute data associated with machine learning operations. The CODEC1027can, for example, compress sparse matrix data for sparse machine learning operations. The CODEC1027can also compress sparse matrix data that is encoded in a sparse matrix format (e.g., coordinate list encoding (COO), compressed sparse row (CSR), compress sparse column (CSC), etc.) to generate compressed and encoded sparse matrix data. The compressed and encoded sparse matrix data can be decompressed and/or decoded before being processed by processing elements or the processing elements can be configured to consume compressed, encoded, or compressed and encoded data for processing.

The ROP1026may be included within at least one processing cluster (e.g., cluster1014A-1014N ofFIG.10A) instead of within the partition unit1020. In such embodiment, read and write requests for pixel data are transmitted over the memory crossbar1016instead of pixel fragment data. The processed graphics data may be displayed on a display device, such as one of the one or more display device(s), routed for further processing by processor(s), or routed for further processing by one of the processing entities within a parallel processor1000.

FIG.10Cis a block diagram of a processing cluster1014within a parallel processing unit. For example, the processing cluster is an instance of one of the processing clusters1014A-1014N ofFIG.10A. The processing cluster1014can be configured to execute many threads in parallel, where the term “thread” refers to an instance of a particular program executing on a particular set of input data. Optionally, single-instruction, multiple-data (SIMD) instruction issue techniques may be used to support parallel execution of a large number of threads without providing multiple independent instruction units. Alternatively, single-instruction, multiple-thread (SIMT) techniques may be used to support parallel execution of a large number of generally synchronized threads, using a common instruction unit configured to issue instructions to a set of processing engines within at least one of the processing clusters. Unlike a SIMD execution regime, where all processing engines typically execute identical instructions, SIMT execution allows different threads to more readily follow divergent execution paths through a given thread program. Persons skilled in the art will understand that a SIMD processing regime represents a functional subset of a SIMT processing regime.

Operation of the processing cluster1014can be controlled via a pipeline manager1032that distributes processing tasks to SIMT parallel processors. The pipeline manager1032receives instructions from the scheduler1010ofFIG.10Aand manages execution of those instructions via a graphics multiprocessor1034and/or a texture unit1036. The illustrated graphics multiprocessor1034is an exemplary instance of a SIMT parallel processor. However, various types of SIMT parallel processors of differing architectures may be included within the processing cluster1014. One or more instances of the graphics multiprocessor1034can be included within a processing cluster1014. The graphics multiprocessor1034can process data and a data crossbar1040can be used to distribute the processed data to one of multiple possible destinations, including other shader units. The pipeline manager1032can facilitate the distribution of processed data by specifying destinations for processed data to be distributed via the data crossbar1040.

At least one of graphics multiprocessor1034within the processing cluster1014can include an identical set of functional execution logic (e.g., arithmetic logic units, load-store units, etc.). The functional execution logic can be configured in a pipelined manner in which new instructions can be issued before previous instructions are complete. The functional execution logic supports a variety of operations including integer and floating-point arithmetic, comparison operations, Boolean operations, bit-shifting, and computation of various algebraic functions. The same functional-unit hardware could be leveraged to perform different operations and other combinations of functional units may be present.

The instructions transmitted to the processing cluster1014constitute a thread. A set of threads executing across the set of parallel processing engines is a thread group. A thread group executes the same program on different input data. At least one thread within a thread group can be assigned to a different processing engine within a graphics multiprocessor1034. A thread group may include fewer threads than the number of processing engines within the graphics multiprocessor1034. When a thread group includes fewer threads than the number of processing engines, one or more of the processing engines may be idle during cycles in which that thread group is being processed. A thread group may also include more threads than the number of processing engines within the graphics multiprocessor1034. When the thread group includes more threads than the number of processing engines within the graphics multiprocessor1034, processing can be performed over consecutive clock cycles. Optionally, multiple thread groups can be executed concurrently on the graphics multiprocessor1034.

The graphics multiprocessor1034may include an internal cache memory to perform load and store operations. Optionally, the graphics multiprocessor1034can forego an internal cache and use a cache memory (e.g., level 1 (L1) cache1048) within the processing cluster1014. At least one graphics multiprocessor1034also has access to level 2 (L2) caches within the partition units (e.g., partition units1020A-1020N ofFIG.10A) that are shared among all processing clusters1014and may be used to transfer data between threads. The graphics multiprocessor1034may also access off-chip global memory, which can include one or more of local parallel processor memory and/or system memory. A memory external to the parallel processing unit1002may be used as global memory. Embodiments in which the processing cluster1014includes multiple instances of the graphics multiprocessor1034can share common instructions and data, which may be stored in the L1 cache1048.

At least one processing cluster1014may include an MMU1045(memory management unit) that is configured to map virtual addresses into physical addresses. In other embodiments, one or more instances of the MMU1045may reside within the memory interface1018ofFIG.10A. The MMU1045includes a set of page table entries (PTEs) used to map a virtual address to a physical address of a tile and optionally a cache line index. The MMU1045may include address translation lookaside buffers (TLB) or caches that may reside within the graphics multiprocessor1034or the L1 cache1048of processing cluster1014. The physical address is processed to distribute surface data access locality to allow efficient request interleaving among partition units. The cache line index may be used to determine whether a request for a cache line is a hit or miss.

In graphics and computing applications, a processing cluster1014may be configured such that at least one graphics multiprocessor1034is coupled to a texture unit1036for performing texture mapping operations, e.g., determining texture sample positions, reading texture data, and filtering the texture data. Texture data is read from an internal texture L1 cache (not shown) or in some embodiments from the L1 cache within graphics multiprocessor1034and is fetched from an L2 cache, local parallel processor memory, or system memory, as needed. At least one graphics multiprocessor1034outputs processed tasks to the data crossbar1040to provide the processed task to another processing cluster1014for further processing or to store the processed task in an L2 cache, local parallel processor memory, or system memory via the memory crossbar1016. A preROP1042(pre-raster operations unit) is configured to receive data from graphics multiprocessor1034, direct data to ROP units, which may be located with partition units as described herein (e.g., partition units1020A-1020N ofFIG.10A). The preROP1042unit can perform optimizations for color blending, organize pixel color data, and perform address translations.

It will be appreciated that the core architecture described herein is illustrative and that variations and modifications are possible. Other numbers of processing units, e.g., graphics multiprocessor1034, texture units1036, preROPs1042, etc., may be included within a processing cluster1014. Further, while only one processing cluster1014is shown, a parallel processing unit as described herein may include other numbers of instances of the processing cluster1014. Optionally, at least one processing cluster1014can be configured to operate independently of other processing clusters1014using separate and distinct processing units, L1 caches, L2 caches, etc.

FIG.10Dshows an example of the graphics multiprocessor1034in which the graphics multiprocessor1034couples with the pipeline manager1032of the processing cluster1014. The graphics multiprocessor1034has an execution pipeline including but not limited to an instruction cache1052, an instruction unit1054, an address mapping unit1056, a register file1058, one or more general purpose graphics processing unit (GPGPU) cores1062, and one or more load/store units1066. The GPGPU cores1062and load/store units1066are coupled with cache memory1072and shared memory1070via a memory and cache interconnect1068. The graphics multiprocessor1034may additionally include tensor and/or ray-tracing cores1063that include hardware logic to accelerate matrix and/or ray-tracing operations.

The instruction cache1052may receive a stream of instructions to execute from the pipeline manager1032. The instructions are cached in the instruction cache1052and dispatched for execution by the instruction unit1054. The instruction unit1054can dispatch instructions as thread groups (e.g., warps), with at least one thread of the thread group assigned to a different execution unit within GPGPU core1062. An instruction can access a local, shared, or global address space by specifying an address within a unified address space. The address mapping unit1056can be used to translate addresses in the unified address space into a distinct memory address that can be accessed by the load/store units1066.

The register file1058provides a set of registers for the functional units of the graphics multiprocessor1034. The register file1058provides temporary storage for operands connected to the data paths of the functional units (e.g., GPGPU cores1062, load/store units1066) of the graphics multiprocessor1034. The register file1058may be divided between at least one of the functional units such that at least one functional unit is allocated a dedicated portion of the register file1058. For example, the register file1058may be divided between the different warps being executed by the graphics multiprocessor1034.

The GPGPU cores1062can include floating point units (FPUs) and/or integer arithmetic logic units (ALUs) that are used to execute instructions of the graphics multiprocessor1034. In some implementations, the GPGPU cores1062can include hardware logic that may otherwise reside within the tensor and/or ray-tracing cores1063. The GPGPU cores1062can be similar in architecture or can differ in architecture. For example and in one embodiment, a first portion of the GPGPU cores1062include a single precision FPU and an integer ALU while a second portion of the GPGPU cores include a double precision FPU. Optionally, the FPUs can implement the IEEE 754-2008 standard for floating point arithmetic or enable variable precision floating point arithmetic. The graphics multiprocessor1034can additionally include one or more fixed function or special function units to perform specific functions such as copy rectangle or pixel blending operations. One or more of the GPGPU cores can also include fixed or special function logic.

The GPGPU cores1062may include SIMD logic capable of performing a single instruction on multiple sets of data. Optionally, GPGPU cores1062can physically execute SIMD4, SIMD8, and SIMD16 instructions and logically execute SIMD1, SIMD2, and SIMD32 instructions. The SIMD instructions for the GPGPU cores can be generated at compile time by a shader compiler or automatically generated when executing programs written and compiled for single program multiple data (SPMD) or SIMT architectures. Multiple threads of a program configured for the SIMT execution model can be executed via a single SIMD instruction. For example and in one embodiment, eight SIMT threads that perform the same or similar operations can be executed in parallel via a single SIMD8 logic unit.

The memory and cache interconnect1068is an interconnect network that connects at least one of the functional units of the graphics multiprocessor1034to the register file1058and to the shared memory1070. For example, the memory and cache interconnect1068is a crossbar interconnect that allows the load/store unit1066to implement load and store operations between the shared memory1070and the register file1058. The register file1058can operate at the same frequency as the GPGPU cores1062, thus data transfer between the GPGPU cores1062and the register file1058is very low latency. The shared memory1070can be used to enable communication between threads that execute on the functional units within the graphics multiprocessor1034. The cache memory1072can be used as a data cache for example, to cache texture data communicated between the functional units and the texture unit1036. The shared memory1070can also be used as a program managed cached. The shared memory1070and the cache memory1072can couple with the data crossbar1040to enable communication with other components of the processing cluster. Threads executing on the GPGPU cores1062can programmatically store data within the shared memory in addition to the automatically cached data that is stored within the cache memory1072.

FIG.11depicts an example network interface device. Various hardware and software resources in the network interface can be in a GPU-integrated NIC, network interface device, or smartNIC, as described herein. In some examples, network interface1100can be implemented as a network interface controller, network interface card, a host fabric interface (HFI), or host bus adapter (HBA), and such examples can be interchangeable. Network interface1100can be coupled to one or more servers using a bus, PCIe, CXL, or DDR. Network interface1100may be embodied as part of a system-on-a-chip (SoC) that includes one or more processors, or included on a multichip package that also contains one or more processors.

Some examples of network device1100are part of an Infrastructure Processing Unit (IPU) or data processing unit (DPU) or utilized by an IPU or DPU. An xPU can refer at least to an IPU, DPU, GPU, GPGPU, or other processing units (e.g., accelerator devices). An IPU or DPU can include a network interface with one or more programmable pipelines or fixed function processors to perform offload of operations that could have been performed by a CPU. The IPU or DPU can include one or more memory devices. In some examples, the IPU or DPU can perform virtual switch operations, manage storage transactions (e.g., compression, cryptography, virtualization), and manage operations performed on other IPUs, DPUs, servers, or devices.

Network interface1100can include transceiver1102, processors1104, transmit queue1106, receive queue1108, memory1110, and bus interface1112, and DMA engine1152. Transceiver1102can be capable of receiving and transmitting packets in conformance with the applicable protocols such as Ethernet as described in IEEE 802.3, although other protocols may be used. Transceiver1102can receive and transmit packets from and to a network via a network medium (not depicted). Transceiver1102can include PHY circuitry1114and media access control (MAC) circuitry1116. PHY circuitry1114can include encoding and decoding circuitry (not shown) to encode and decode data packets according to applicable physical layer specifications or standards. MAC circuitry1116can be configured to perform MAC address filtering on received packets, process MAC headers of received packets by verifying data integrity, remove preambles and padding, and provide packet content for processing by higher layers. MAC circuitry1116can be configured to assemble data to be transmitted into packets, that include destination and source addresses along with network control information and error detection hash values.

Processors1104can be a combination of: a processor, core, graphics processing unit (GPU), field programmable gate array (FPGA), application specific integrated circuit (ASIC), or other programmable hardware device that allow programming of network interface1100. For example, a “smart network interface” or SmartNIC can provide packet processing capabilities in the network interface using processors1104.

Processors1104can include a programmable processing pipeline that is programmable by one or more of: Protocol-independent Packet Processors (P4), Software for Open Networking in the Cloud (SONiC), Broadcom® Network Programming Language (NPL), Nvidia® CUDA®, DOCA™, Infrastructure Programmer Development Kit (IPDK), or x86 compatible executable binaries or other executable binaries. A programmable processing pipeline can include one or more match-action units (MAUs) that can schedule packets for transmission using one or multiple granularity lists, as described herein. Processors, FPGAs, other specialized processors, controllers, devices, and/or circuits can be used utilized for packet processing or packet modification. Ternary content-addressable memory (TCAM) can be used for parallel match-action or look-up operations on packet header content.

Packet allocator1124can provide distribution of received packets for processing by multiple CPUs or cores using receive side scaling (RSS). When packet allocator1124uses RSS, packet allocator1124can calculate a hash or make another determination based on contents of a received packet to determine which CPU or core is to process a packet.

Interrupt coalesce1122can perform interrupt moderation whereby network interface interrupt coalesce1122waits for multiple packets to arrive, or for a time-out to expire, before generating an interrupt to host system to process received packet(s). Receive Segment Coalescing (RSC) can be performed by network interface1100whereby portions of incoming packets are combined into segments of a packet. Network interface1100provides this coalesced packet to an application.

Direct memory access (DMA) engine1152can copy a packet header, packet payload, and/or descriptor directly from host memory to the network interface or vice versa, instead of copying the packet to an intermediate buffer at the host and then using another copy operation from the intermediate buffer to the destination buffer.

Memory1110can be a type of volatile or non-volatile memory device and can store any queue or instructions used to program network interface1100. Transmit queue1106can include data or references to data for transmission by network interface. Receive queue1108can include data or references to data that was received by network interface from a network. Descriptor queues1120can include descriptors that reference data or packets in transmit queue1106or receive queue1108. Bus interface1112can provide an interface with host device (not depicted). For example, bus interface1112can be compatible with or based at least in part on PCI, PCI Express, PCI-x, Serial ATA, and/or USB (although other interconnection standards may be used), or proprietary variations thereof.

FIG.12depicts an example process. At1202, a system with at least one graphics processing unit with integrated network interface controllers can be connected to at least three networks. A first of the at least two networks can include a GPU-to-GPU connection for connecting GPUs of the system to other GPUs in the system. A second of the at least two networks can include a scale-out fabric. The scale-out fabric can be used to provide communications between CPUs, GPUs, or other devices (e.g., accelerators) of the system with CPUs, GPUs, or other devices (e.g., accelerators) of one or more other systems. Communications via the first and/or second networks can utilize a reliability protocol.

At1204, a network interface device of the system with at least one graphics processing unit with integrated network interface controllers can be connected to the second switching network. For example, the network interface device can include a discrete network interface device that is communicatively coupled to at least one GPU and provides communications, via the second switching network, between CPUs, GPUs, or other devices (e.g., accelerators) of the system with CPUs, GPUs, or other devices (e.g., accelerators) of one or more other systems.

At1206, a second network interface device of the system with at least one graphics processing unit with integrated network interface controllers can be connected to a third network. The third network can include a storage and control network. The storage and control network can provide communications for configuring operations of CPUs, GPUs, devices (e.g., accelerators), the network interface device, and/or one or more integrated network interface controllers. Operations can include storage protocols or security features (e.g., VLAN, VxLAN, partitioning, encryption, etc.). For example, the storage and control network can provide communications among CPUs, GPUs, devices (e.g., accelerators), the network interface device, and/or one or more integrated network interface controllers and CPUs, GPUs, devices (e.g., accelerators), the network interface device, and/or one or more integrated network interface controllers of one or more other system nodes.

FIG.13depicts an example computing system. Components of system1300(e.g., processor1310, accelerators1342, network interface1350, memory subsystem1320, and so forth) can be utilized in a system node, as described herein. System1300includes processor1310, which provides processing, operation management, and execution of instructions for system1300. Processor1310can include any type of microprocessor, central processing unit (CPU), graphics processing unit (GPU), processing core, or other processing hardware to provide processing for system1300, or a combination of processors. Processor1310controls the overall operation of system1300, and can be or include, one or more programmable general-purpose or special-purpose microprocessors, digital signal processors (DSPs), programmable controllers, application specific integrated circuits (ASICs), programmable logic devices (PLDs), or the like, or a combination of such devices.

In one example, system1300includes interface1312coupled to processor1310, which can represent a higher speed interface or a high throughput interface for system components that needs higher bandwidth connections, such as memory subsystem1320or graphics interface components1340, or accelerators1342. Interface1312represents an interface circuit, which can be a standalone component or integrated onto a processor die. Where present, graphics interface1340interfaces to graphics components for providing a visual display to a user of system1300. In one example, graphics interface1340can drive a high definition (HD) display that provides an output to a user. High definition can refer to a display having a pixel density of approximately 100 PPI (pixels per inch) or greater and can include formats such as full HD (e.g., 1080p), retina displays, 4K (ultra-high definition or UHD), or others. In one example, the display can include a touchscreen display. In one example, graphics interface1340generates a display based on data stored in memory1330or based on operations executed by processor1310or both. In one example, graphics interface1340generates a display based on data stored in memory1330or based on operations executed by processor1310or both.

Accelerators1342can be a fixed function or programmable offload engine that can be accessed or used by a processor1310. For example, an accelerator among accelerators1342can provide compression (DC) capability, cryptography services such as public key encryption (PKE), cipher, hash/authentication capabilities, decryption, or other capabilities or services. In some embodiments, in addition or alternatively, an accelerator among accelerators1342provides field select controller capabilities as described herein. In some cases, accelerators1342can be integrated into a CPU socket (e.g., a connector to a motherboard or circuit board that includes a CPU and provides an electrical interface with the CPU). For example, accelerators1342can include a single or multi-core processor, graphics processing unit, logical execution unit single or multi-level cache, functional units usable to independently execute programs or threads, application specific integrated circuits (ASICs), neural network processors (NNPs), programmable control logic, and programmable processing elements such as field programmable gate arrays (FPGAs) or programmable logic devices (PLDs). Accelerators1342can provide multiple neural networks, CPUs, processor cores, general purpose graphics processing units, or graphics processing units can be made available for use by artificial intelligence (AI) or machine learning (ML) models. For example, the AI model can use or include one or more of: a reinforcement learning scheme, Q-learning scheme, deep-Q learning, or Asynchronous Advantage Actor-Critic (A3C), combinatorial neural network, recurrent combinatorial neural network, or other AI or ML model. Multiple neural networks, processor cores, or graphics processing units can be made available for use by AI or ML models.

Memory subsystem1320represents the main memory of system1300and provides storage for code to be executed by processor1310, or data values to be used in executing a routine. Memory subsystem1320can include one or more memory devices1330such as read-only memory (ROM), flash memory, one or more varieties of random access memory (RAM) such as DRAM, or other memory devices, or a combination of such devices. Memory1330stores and hosts, among other things, operating system (OS)1332to provide a software platform for execution of instructions in system1300. Additionally, applications1334can execute on the software platform of OS1332from memory1330. Applications1334represent programs that have their own operational logic to perform execution of one or more functions. Processes1336represent agents or routines that provide auxiliary functions to OS1332or one or more applications1334or a combination. OS1332, applications1334, and processes1336provide software logic to provide functions for system1300. In one example, memory subsystem1320includes memory controller1322, which is a memory controller to generate and issue commands to memory1330. It will be understood that memory controller1322could be a physical part of processor1310or a physical part of interface1312. For example, memory controller1322can be an integrated memory controller, integrated onto a circuit with processor1310.

While not specifically illustrated, it will be understood that system1300can include one or more buses or bus systems between devices, such as a memory bus, a graphics bus, interface buses, or others. Buses or other signal lines can communicatively or electrically couple components together, or both communicatively and electrically couple the components. Buses can include physical communication lines, point-to-point connections, bridges, adapters, controllers, or other circuitry or a combination. Buses can include, for example, one or more of a system bus, a Peripheral Component Interconnect (PCI) bus, a Hyper Transport or industry standard architecture (ISA) bus, a small computer system interface (SCSI) bus, a universal serial bus (USB), or an Institute of Electrical and Electronics Engineers (IEEE) standard 1394 bus (Firewire).

In one example, system1300includes interface1314, which can be coupled to interface1312. In one example, interface1314represents an interface circuit, which can include standalone components and integrated circuitry. In one example, multiple user interface components or peripheral components, or both, couple to interface1314. Network interface1350provides system1300the ability to communicate with remote devices (e.g., servers or other computing devices) over one or more networks. Network interface1350can include an Ethernet adapter, wireless interconnection components, cellular network interconnection components, USB (universal serial bus), or other wired or wireless standards-based or proprietary interfaces. Network interface1350can transmit data to a device that is in the same data center or rack or a remote device, which can include sending data stored in memory.

Network interface1350can include one or more of: a network interface controller (NIC), a remote direct memory access (RDMA)-enabled NIC, SmartNIC, router, switch, or network-attached appliance. Some examples of network interface1350are part of an Infrastructure Processing Unit (IPU) or data processing unit (DPU) or utilized by an IPU or DPU. An xPU can refer at least to an IPU, DPU, GPU, GPGPU, or other processing units (e.g., accelerator devices). An IPU or DPU can include a network interface with one or more programmable pipelines or fixed function processors to perform offload of operations that could have been performed by a CPU.

In one example, system1300includes one or more input/output (I/O) interface(s)1360. I/O interface1360can include one or more interface components through which a user interacts with system1300(e.g., audio, alphanumeric, tactile/touch, or other interfacing). Peripheral interface1370can include any hardware interface not specifically mentioned above. Peripherals refer generally to devices that connect dependently to system1300. A dependent connection is one where system1300provides the software platform or hardware platform or both on which operation executes, and with which a user interacts.

In one example, system1300includes storage subsystem1380to store data in a nonvolatile manner. In one example, in certain system implementations, at least certain components of storage1380can overlap with components of memory subsystem1320. Storage subsystem1380includes storage device(s)1384, which can be or include any conventional medium for storing large amounts of data in a nonvolatile manner, such as one or more magnetic, solid state, or optical based disks, or a combination. Storage1384holds code or instructions and data1386in a persistent state (e.g., the value is retained despite interruption of power to system1300). Storage1384can be generically considered to be a “memory,” although memory1330is typically the executing or operating memory to provide instructions to processor1310. Whereas storage1384is nonvolatile, memory1330can include volatile memory (e.g., the value or state of the data is indeterminate if power is interrupted to system1300). In one example, storage subsystem1380includes controller1382to interface with storage1384. In one example controller1382is a physical part of interface1314or processor1310or can include circuits or logic in both processor1310and interface1314.

A volatile memory is memory whose state (and therefore the data stored in it) is indeterminate if power is interrupted to the device. Dynamic volatile memory uses refreshing the data stored in the device to maintain state. One example of dynamic volatile memory incudes DRAM (Dynamic Random Access Memory), or some variant such as Synchronous DRAM (SDRAM). An example of a volatile memory include a cache. A memory subsystem as described herein may be compatible with a number of memory technologies, such as those consistent with specifications from JEDEC (Joint Electronic Device Engineering Council) or others or combinations of memory technologies, and technologies based on derivatives or extensions of such specifications.

A non-volatile memory (NVM) device is a memory whose state is determinate even if power is interrupted to the device. In one embodiment, the NVM device can comprise a block addressable memory device, such as NAND technologies, or more specifically, multi-threshold level NAND flash memory (for example, Single-Level Cell (“SLC”), Multi-Level Cell (“MLC”), Quad-Level Cell (“QLC”), Tri-Level Cell (“TLC”), or some other NAND). A NVM device can also comprise a byte-addressable write-in-place three dimensional cross point memory device, or other byte addressable write-in-place NVM device (also referred to as persistent memory), such as single or multi-level Phase Change Memory (PCM) or phase change memory with a switch (PCMS), Intel® Optane™ memory, NVM devices that use chalcogenide phase change material (for example, chalcogenide glass), a combination of one or more of the above, or other memory.

A power source (not depicted) provides power to the components of system1300. More specifically, power source typically interfaces to one or multiple power supplies in system1300to provide power to the components of system1300. In one example, the power supply includes an AC to DC (alternating current to direct current) adapter to plug into a wall outlet. Such AC power can be renewable energy (e.g., solar power) power source. In one example, power source includes a DC power source, such as an external AC to DC converter. In one example, power source or power supply includes wireless charging hardware to charge via proximity to a charging field. In one example, power source can include an internal battery, alternating current supply, motion-based power supply, solar power supply, or fuel cell source.

In an example, system1300can be implemented using interconnected compute sleds of processors, memories, storages, network interfaces, and other components. High speed interconnects can be used such as: Ethernet (IEEE 802.3), remote direct memory access (RDMA), InfiniBand, Internet Wide Area RDMA Protocol (iWARP), Transmission Control Protocol (TCP), User Datagram Protocol (UDP), quick UDP Internet Connections (QUIC), RDMA over Converged Ethernet (RoCE), Peripheral Component Interconnect express (PCIe), Intel QuickPath Interconnect (QPI), Intel® Ultra Path Interconnect (UPI), Intel On-Chip System Fabric (IOSF), Omni-Path, Compute Express Link (CXL), Universal Chiplet Interconnect Express (UCIe), HyperTransport, high-speed fabric, NVLink, Advanced Microcontroller Bus Architecture (AMBA) interconnect, OpenCAPI, Gen-Z, Infinity Fabric (IF), Cache Coherent Interconnect for Accelerators (CCIX), 3GPP Long Term Evolution (LTE) (4G), 3GPP 5G, and variations thereof. Data can be copied or stored to virtualized storage nodes or accessed using a protocol such as NVMe over Fabrics (NVMe-oF) or NVMe.

Communications between devices can take place using a network that provides die-to-die communications; chip-to-chip communications; circuit board-to-circuit board communications; and/or package-to-package communications.

Embodiments herein may be implemented in various types of computing, smart phones, tablets, personal computers, and networking equipment, such as switches, routers, racks, and blade servers such as those employed in a data center and/or server farm environment. The servers used in data centers and server farms comprise arrayed server configurations such as rack-based servers or blade servers. These servers are interconnected in communication via various network provisions, such as partitioning sets of servers into Local Area Networks (LANs) with appropriate switching and routing facilities between the LANs to form a private Intranet. For example, cloud hosting facilities may typically employ large data centers with a multitude of servers. A blade comprises a separate computing platform that is configured to perform server-type functions, that is, a “server on a card.” Accordingly, each blade includes components common to conventional servers, including a main printed circuit board (main board) providing internal wiring (e.g., buses) for coupling appropriate integrated circuits (ICs) and other components mounted to the board.

In some examples, various systems of GPUs and network interface devices described herein can be used in connection with a base station (e.g., 3G, 4G, 5G and so forth), macro base station (e.g., 5G networks), picostation (e.g., an IEEE 802.11 compatible access point), nanostation (e.g., for Point-to-MultiPoint (PtMP) applications), micro data center, on-premise data centers, off-premise data centers, edge network elements, edge network computing elements, multi-access edge computing (MEC), cloud gaming servers, fog network elements, and/or hybrid data centers (e.g., data center that use virtualization, cloud and software-defined networking to deliver application workloads across physical data centers and distributed multi-cloud environments).

FIG.14depicts an example network interface device. Network interface device1400manages performance of one or more processes using one or more of processors1406, processors1410, accelerators1420, memory pool1430, or servers1440-0to1440-N, where N is an integer of 1 or more. In some examples, processors1406of network interface device1400can execute one or more processes, applications, VMs, containers, microservices, and so forth that request performance of workloads by one or more of: processors1410, accelerators1420, memory pool1430, and/or servers1440-0to1440-N. Network interface device1400can utilize network interface1402or one or more device interfaces to communicate with processors1410, accelerators1420, memory pool1430, and/or servers1440-0to1440-N. Network interface device1400can utilize programmable pipeline1404to process packets that are to be transmitted from network interface1402or packets received from network interface1402.

Programmable pipeline1404and/or processors1406can be configured or programmed using languages based on one or more of: P4, Software for Open Networking in the Cloud (SONiC), C, Python, Broadcom Network Programming Language (NPL), Nvidia® CUDA®, Nvidia® DOCA™, Infrastructure Programmer Development Kit (IPDK), or x86 compatible executable binaries or other executable binaries.

Various examples may be implemented using hardware elements, software elements, or a combination of both. In some examples, hardware elements may include devices, components, processors, microprocessors, circuits, circuit elements (e.g., transistors, resistors, capacitors, inductors, and so forth), integrated circuits, ASICs, PLDs, DSPs, FPGAs, memory units, logic gates, registers, semiconductor device, chips, microchips, chip sets, and so forth. In some examples, software elements may include software components, programs, applications, computer programs, application programs, system programs, machine programs, operating system software, middleware, firmware, software modules, routines, subroutines, functions, methods, procedures, software interfaces, APIs, instruction sets, computing code, computer code, code segments, computer code segments, words, values, symbols, or any combination thereof. Determining whether an example is implemented using hardware elements and/or software elements may vary in accordance with any number of factors, such as desired computational rate, power levels, heat tolerances, processing cycle budget, input data rates, output data rates, memory resources, data bus speeds and other design or performance constraints, as desired for a given implementation. A processor can be one or more combination of a hardware state machine, digital control logic, central processing unit, or any hardware, firmware and/or software elements.

Some examples may be implemented using or as an article of manufacture or at least one computer-readable medium. A computer-readable medium may include a non-transitory storage medium to store logic. In some examples, the non-transitory storage medium may include one or more types of computer-readable storage media capable of storing electronic data, including volatile memory or non-volatile memory, removable or non-removable memory, erasable or non-erasable memory, writeable or re-writeable memory, and so forth. In some examples, the logic may include various software elements, such as software components, programs, applications, computer programs, application programs, system programs, machine programs, operating system software, middleware, firmware, software modules, routines, subroutines, functions, methods, procedures, software interfaces, API, instruction sets, computing code, computer code, code segments, computer code segments, words, values, symbols, or any combination thereof.

According to some examples, a computer-readable medium may include a non-transitory storage medium to store or maintain instructions that when executed by a machine, computing device or system, cause the machine, computing device or system to perform methods and/or operations in accordance with the described examples. The instructions may include any suitable type of code, such as source code, compiled code, interpreted code, executable code, static code, dynamic code, and the like. The instructions may be implemented according to a predefined computer language, manner, or syntax, for instructing a machine, computing device or system to perform a certain function. The instructions may be implemented using any suitable high-level, low-level, object-oriented, visual, compiled and/or interpreted programming language.

One or more aspects of at least one example may be implemented by representative instructions stored on at least one machine-readable medium which represents various logic within the processor, which when read by a machine, computing device or system causes the machine, computing device or system to fabricate logic to perform the techniques described herein. Such representations, known as “IP cores” may be stored on a tangible, machine readable medium and supplied to various customers or manufacturing facilities to load into the fabrication machines that actually make the logic or processor.

The appearances of the phrase “one example” or “an example” are not necessarily all referring to the same example or embodiment. Any aspect described herein can be combined with any other aspect or similar aspect described herein, regardless of whether the aspects are described with respect to the same figure or element. Division, omission, or inclusion of block functions depicted in the accompanying figures does not infer that the hardware components, circuits, software and/or elements for implementing these functions would necessarily be divided, omitted, or included in embodiments.

Some examples may be described using the expression “coupled” and “connected” along with their derivatives. These terms are not necessarily intended as synonyms for each other. For example, descriptions using the terms “connected” and/or “coupled” may indicate that two or more elements are in direct physical or electrical contact with each other. The term “coupled,” however, may also mean that two or more elements are not in direct contact with each other, but yet still co-operate or interact with each other.

The terms “first,” “second,” and the like, herein do not denote any order, quantity, or importance, but rather are used to distinguish one element from another. The terms “a” and “an” herein do not denote a limitation of quantity, but rather denote the presence of at least one of the referenced items. The term “asserted” used herein with reference to a signal denote a state of the signal, in which the signal is active, and which can be achieved by applying any logic level either logic 0 or logic 1 to the signal. The terms “follow” or “after” can refer to immediately following or following after some other event or events. Other sequences of steps may also be performed according to alternative embodiments. Furthermore, additional steps may be added or removed depending on the particular applications. Any combination of changes can be used and one of ordinary skill in the art with the benefit of this disclosure would understand the many variations, modifications, and alternative embodiments thereof.

Disjunctive language such as the phrase “at least one of X, Y, or Z,” unless specifically stated otherwise, is otherwise understood within the context as used in general to present that an item, term, etc., may be either X, Y, or Z, or any combination thereof (e.g., X, Y, and/or Z). Thus, such disjunctive language is not generally intended to, and should not, imply that certain embodiments require at least one of X, at least one of Y, or at least one of Z to each be present. Additionally, conjunctive language such as the phrase “at least one of X, Y, and Z,” unless specifically stated otherwise, should also be understood to mean X, Y, Z, or any combination thereof, including “X, Y, and/or Z.’”

Illustrative examples of the devices, systems, and methods disclosed herein are provided below. An embodiment of the devices, systems, and methods may include any one or more, and any combination of, the examples described below.

Example 1 includes one or more examples, and includes an apparatus comprising: a first graphics processing unit (GPU) with at least one integrated communications system, wherein the at least one integrated communications system is to apply a reliability protocol to communicate with a second at least one integrated communications system associated with a second GPU to copy data from a first memory region to a second memory region and wherein the first memory region is associated with the first GPU and the second memory region is associated with the second GPU.

Example 2 includes one or more examples, wherein the at least one integrated communications system comprises a communications system integrated into a same integrated circuit or system on chip (SoC) as that of the first GPU and the second at least one integrated communications system comprises a communications system integrated into a same integrated circuit or SoC as that of the first GPU and the second GPU.

Example 3 includes one or more examples, wherein the at least one integrated communications system comprises: direct memory access (DMA) circuitry; reliable transport circuitry; and a network interface controller.

Example 4 includes one or more examples, wherein the at least one integrated communications system is to perform topology discovery to discover the second at least one integrated communications system.

Example 5 includes one or more examples, comprising a device interface to communicatively couple the at least one integrated communications system to one or more execution units of the first GPU.

Example 6 includes one or more examples, comprising a first memory associated with the first GPU and a second memory associated with the second GPU, wherein the first memory comprises a source of data and the second memory comprises a destination of data.

Example 7 includes one or more examples, comprising: a network interface device to receive and apply control configurations for the at least one integrated communications system and the second at least one integrated communications system.

Example 8 includes one or more examples, wherein the at least one integrated communications system and the second at least one integrated communications system are to communicate with at least one GPU of another system.

Example 9 includes one or more examples, comprising: a network interface device to provide communications among the first GPU, the second GPU, and at least one GPU of another system.

Example 10 includes one or more examples, comprising: at least one central processing unit communicatively coupled to the first GPU and the second GPU, wherein the at least one central processing unit is to communicate with at least one GPU of another system using the at least one integrated communications system and the second at least one integrated communications system.

Example 11 includes one or more examples, comprising: a GPU-to-GPU connection to provide communication between the at least one integrated communications system and the second at least one integrated communications system.

Example 12 includes one or more examples, comprising: fabric to provide communication among the first and second GPUs and at least one GPU of another system.

Example 13 includes one or more examples, and includes at least one non-transitory computer-readable medium comprising instructions stored thereon, that if executed, cause one or more processors to: configure at least one network interface device of a first graphics processing unit (GPU) to configure data planes of one or more other network interface devices, wherein the at least one network interface device is to use a reliability protocol to communicate with another at least one network interface device associated with a second GPU to copy data from a first memory to a second memory and wherein the first memory is associated with the first GPU and the second memory is associated with the second GPU.

Example 14 includes one or more examples, comprising instructions stored thereon, that if executed, cause one or more processors to: perform topology discovery to discover at least one network interface device.

Example 15 includes one or more examples, wherein: the at least one network interface device of a first GPU comprises a communications system integrated into a same integrated circuit or system on chip (SoC) as that of the first GPU and the another at least one network interface device associated with a second GPU comprises a communications system integrated into a same integrated circuit or SoC as that of the second GPU.

Example 16 includes one or more examples, and includes a method comprising: in an integrated circuit with multiple graphics processing units (GPUs): providing communications among the multiple GPUs by communications systems integrated into the multiple GPUs and a GPU-to-GPU connection, providing communications among the multiple GPUs and at least one GPU of another integrated circuitry by a communications systems integrated into the multiple GPUs and a switching network, configuring the communications systems integrated into the multiple GPUs by a network interface device coupled to a control network.

Example 17 includes one or more examples, wherein a first communications systems of the communications systems integrated into the multiple GPUs is integrated into a same integrated circuit or system on chip (SoC) as that of a first GPU of the multiple GPUs and a second communications systems of the communications systems integrated into the multiple GPUs is integrated into a same integrated circuit or SoC as that of a second GPU of the multiple GPUs.

Example 18 includes one or more examples, wherein the communications among the multiple GPUs utilize reliable transport.

Example 19 includes one or more examples, comprising: one or more switches, in a scale out network, performing topology discovery to discover at least one GPU of the multiple GPUs.

Example 20 includes one or more examples, comprising: providing communications among central processing units, accelerators, and GPUs by selection among at least one of the communications systems integrated into the multiple GPUs or a network interface device.