Patent ID: 12211775

DESCRIPTION

This disclosure, its aspects and implementations, are not limited to the specific components, assembly procedures or method elements disclosed herein. Many additional components, assembly procedures and/or method elements known in the art consistent with the intended semiconductor packages will become apparent for use with particular implementations from this disclosure. Accordingly, for example, although particular implementations are disclosed, such implementations and implementing components may comprise any shape, size, style, type, model, version, measurement, concentration, material, quantity, method element, step, and/or the like as is known in the art for such semiconductor packages, and implementing components and methods, consistent with the intended operation and methods.

Referring toFIG.1, an implementation of a semiconductor package2is illustrated. As illustrated the semiconductor package2includes two substrates4,6. In this implementation, the substrates4,6are direct bonded copper (DBC) substrates that have 2 layers of copper bonded to each side of a dielectric material. While not illustrated in the cross sectional view ofFIG.1, the surface of the electrically conductive layer of each of the substrates4,6that faces the interior of the package includes various traces formed therein allow for electrical routing and physical and mechanical attachment of one or more semiconductor die and other passive/active electrical components inside the package to the substrate. In this particular implementation, the package includes an insulated gate bipolar transistor (IGBT)8and a fast recovery diode (FRD)10. Spacers12,14, and16are used to ensure that sufficient distance between the first substrate4and the second substrate6is maintained. Various layers of solder18,20, and22are used to couple the spacers12,14, and16and the die8,10to the first substrate4and the second substrate6. The external electrical connections of the package2are made through leads24,26which, during manufacture, were coupled to/part of a lead frame. Because lead26is electrically connected to both the first substrate4and to the second substrate6, lead26includes an upset portion28and a downset portion30. The thickness of the spacers12,14,16and the solders all add to the overall thickness of the package2. In various implementations, the ability to thin the package design illustrated inFIG.1may be determined by the minimum distance that needs to be maintained between lead24and substrate4to ensure that, at the operating voltage and current of the package, the encapsulating material32is able to provide sufficient electrical isolation. In various implementations, the lead's26upset and downset may be the limiting factor on how thin the package2can become.

Referring toFIG.2, another implementation of a semiconductor package34is illustrated in cross section that also includes a first substrate36and a second substrate38and two semiconductor devices40,42. In this implementation, there are no physically separate spacers from the semiconductor devices40,42as the die are coupled to the first substrate36and the second substrate38through the various pads of the semiconductor devices40,42. In this implementation, external electrical connections for the package take the form of lead44and lead40which are both physically coupled to both the first substrate36and the second substrate38. In this implementation, a gap48is provided in the electrically conductive material of the second substrate38that faces the semiconductor devices40,42and which electrically isolates the lead44from the second substrate38. As illustrated inFIG.2the leads46,44both have coined or thinned ends which allow the thickness of the lead coupled between the substrates to be thinner than the overall thickness of each lead measured in a direction perpendicular with a cross-section of the package. As illustrated inFIG.2, the package34includes no spacers and the leads44,46do not need to include any upset or downset portions but can remain arranged substantially in a same plane that is parallel relative to planes formed by the largest planar surfaces of the first substrate36and second substrate38, respectively. Because of the elimination of the spacers, the total thickness of the package34is thinner than the total possible thickness of the package2illustrated inFIG.1. The ability to electrically isolate the lead44is what enables the elimination of the upset/downset portions of the leads26,32illustrated inFIG.1. Various lead and substrate implementations that involve electrical isolation will be described in additional detail throughout this document.

Referring toFIG.3, a top view of a second substrate38is illustrated. As illustrated, various pads50are coupled over the electrically conductive material52of the second substrate38to aid in coupled with the electrical devices that will be coupled thereto. While the use of the pads50is illustrated in the implementation illustrated inFIG.3, in other implementations, however, electrical devices may be coupled directly to the electrically conductive material42of the second substrate38. The materials that may be used to coupled the die/electrical components to the pads or electrically conductive material may be, by non-limiting example, solder, silver sintering material, copper sintering material, silver, copper, silver alloys, copper alloys, electrically conductive epoxy, thermally conductive epoxy, die attach materials, or any other material capable of bonding the semiconductor die to the pad or electrically conductive material. As illustrated, a first group of leads54and a second group of leads56are both physically coupled to the second substrate38. The first group of leads54are physically coupled to the second substrate38but, as can be observed inFIG.3, the leads are electrically isolated from the electrically conductive material52by being coupled to electrically isolated islands58formed in the electrically conductive material52. In contrast, the second group of leads56are coupled to electrically conductive traces60formed in the electrically conductive material52of the second substrate38that permit the semiconductor devices to electrically connect with these leads. As illustrated, the electrically isolated first group of leads54is located on one side62of the second substrate38and can also be located on one side64of the substrate38as leads66,68are also coupled to electrically isolated islands70,72in the electrically conductive material52of the second substrate38. In various implementations however, electrically isolated leads may be physically coupled on only one side of the substrate. As illustrated, in other implementations, electrically isolated and electrically coupled leads may be intermixed and/or be arranged and alternating patterns as lead74is coupled to an electrically isolated islands76adjacent to the second group of leads56that are electrically coupled with the second substrate38.

In various implementations, the structure illustrated with respect to second substrate38can also be carried out on first substrate36at the same time or in various implementations only on first substrate36. The presence of the electrically isolated islands is what permits the physical and non-electrical coupling to either of the substrates. Where the electrically isolated islands include copper, they form electrically isolated copper islands.

In various implementations, the relative thicknesses of the three layers of the first substrate36and the second substrate38may be about 0.30 mm, 0.32 mm, and 0.30 mm. In various other implementations, however, the substrates36,38may include one, two, or more than three layers and the thicknesses of the various layers may be greater or less than that of the implementation illustrated inFIG.2. In various implementations, the thickness of the various leads measured in package cross-section may be between about 0.6 mm to about 0.8 mm, though the thicknesses may be greater or thinner in various implementations. In various implementations, the total package thickness may be between about 2.6 mm to about 2.4 mm. In various implementations, electrically conductive material52of the second substrate and electrically conductive material of the first substrate36may be, by non-limiting example, copper, a copper alloy, aluminum, an aluminum alloy, any combination thereof, or any other electrically conductive film, layer, or material. The leads used in various package implementations may be formed of any of a wide variety of electrically conductive materials and may or may not be coated with various other electrically conductive materials as well. The bonding materials used to physically and/or electrically couple the leads, the die, and the substrates may be, by non-example, solders, die attach films, sintering materials, or any other systems or materials used to couple semiconductor components or metallic components together.

Referring toFIG.5, an exploded perspective view of the package ofFIG.2is illustrated that shows the second substrate38and the first substrate36along with the first group of leads54and second group of leads56. In this view it is apparent that during assembly of the package one or more electrical devices will be placed/coupled with the pads50and the various leads bonded/coupled to the second substrate38followed by the first substrate being flipped over and bonded over top of the die and the leads and a similar fashion to the bonding process used the second substrate38. Because the first group of leads54is coupled only to the electrically isolated islands58, when the leads54are coupled to the first substrate36both a physical and electrical connection are formed with the first substrate36. Following the physical and electrical coupling of the first substrate36and the second substrate38, referring toFIG.4, an encapsulant is then applied over the first substrate and the second substrate which may leave at least a portion of the first substrate and the second substrate exposed with along with a portion of the leads54and56. In various package implementations, an additional mold compound or gel compound may be applied between the first substrate36and the second substrate36around the semiconductor devices prior to application of the encapsulant78. The process of applying the mold/gel compound will be discussed further in this document.

Referring toFIG.6, a detail cross sectional view of a lead80is illustrated that is physically and electrically coupled to the first substrate82and second substrate84like the second group of leads56illustrated inFIG.5. Referring toFIG.7, a detail cross sectional view of lead86is illustrated that is physically coupled to the first substrate88and to second substrate but is only electrically coupled to the first substrate88because of electrically isolated island92formed in the surface of the electrically conductive material of the second substrate90. The structure illustrated inFIG.7can be reversed as illustrated inFIG.8where the lead94is only physically coupled to first substrate96but also physically and electrically coupled to second substrate98as electrically isolated island100prevents electrical connection with the first substrate96. As a way of allowing the distance between substrates to be decreased,FIG.9illustrates how the lead102can be coined/thinned at a first end104that is ultimately physically coupled (and in this case, electrically coupled) with first substrate106and with second substrate108.FIG.10illustrates a coined lead110physically and electrically coupled with first substrate112and physically coupled only with the second substrate114through electrically isolating island116.FIG.11illustrates the reverse physical arrangement with coined lead118which is physically coupled only to first substrate120and physically and electrically coupled the second substrate122.

In various semiconductor package implementations, various implementations of methods of forming a semiconductor package may be utilized. Implementations of the method may include physically and electrically coupling a first group of leads to a first substrate. The leads and substrate type used in this method implementation may be any disclosed in this document. The method may also include physically coupling a second group of leads to the first substrate using electrically isolated islands that correspond with each of the second group of leads. In some implementations, each lead may have only one corresponding electrical isolated island; in other implementations, however, two or more of the leads may be coupled to the same electrically isolated island. The method may also include physically and electrically coupling a second substrate to the first group of leads and to the second group of leads. In various method implementations, if the first group of leads is only to be physically coupled to the first substrate, the order of the coupling steps changes correspondingly meaning that the electrically conductive islands are now being coupled with the first group of leads rather than with the second group of leads. Those of ordinary skill the art will readily appreciate the various combinations of method steps that may be formed with each of a wide variety of leads to determine which are physically and electrically and those that are only physically coupled to either of the two substrates during various methods of forming a semiconductor package.

In various method implementations one or more semiconductor die and/or various electrical components, whether active or passive, may be coupled between the first substrate and the second substrate. In various method implementations the one or more semiconductor die and/or electrical components may be coupled to the first substrate at the same time as or along with the coupling of the first group of leads and the second group of leads. In other implementations however, the one or more semiconductor die and/or the electrical components may be coupled to the second substrate prior to the second substrate being physically and electrically coupled with the first group of leads and with the second group of leads. In some obligations, one or more of the semiconductor die and/or one or more of the electrical components may be coupled to either or both of the first substrate and the second substrate prior to the physical and electrical coupling of the second substrate to the first substrate through the one or more of the leads.

In various method implementations, the method may include coining/thinning the first group of leads and a second group of leads. This process of coining/thinning may take place prior to the leads being physically coupled to the first substrate or may take place as part of the coupling process in various implementations. In other implementations, the ends of the leads may be thinned by etching some portion of the ends of the leads, such as, by non-limiting example, half etching the ends of the leads. In various method implementations, the various leads may be coupled to two or more sides of the semiconductor package. For semiconductor packages that are not rectangular, the various leads may be coupled along various edges, sides, or at various locations along a perimeter of the package.

In various package implementations, the thickness of the package can be a challenge to achieving encapsulation between the first substrate and the second substrate. In particular implementations, the use of a pre-mold/premolded lead frame/lead/set of leads may be utilized to assist in the molding process. Referring toFIG.13, a lead124is illustrated that has a molded material126formed on both sides of the lead that is designed to couple with the edges132,134of the first substrate128and second substrate130to form a seal between the edges132,134and the lead124. Because of the presence of the seal, mold/gel material136is prevented from flowing out from around the leads and the edges132,134of the first substrate128and the second substrate130during the filling/molding process as indicated by arrow138. Without the presence of the pre-mold126, during the molding process there may be no dam or other barrier to prevent flow of the material out between the first substrate128and second substrate130is illustrated inFIG.12around lead124. In various implementations, the mold/gel material may be, by non-limiting example, a gel fill material, a chip coating material, an epoxy, a resin, an epoxy resin, mold compound, any combination thereof, or any other material capable of filling the space between the first substrate and the second substrate. In various implementations, no mold/gel material may be used, and the space between the first substrate and the second substrate may be left separated by air to form an air gap. The use of an air gap may be used where the size of the semiconductor die in the package is smaller relative to the size of the first substrate and the second substrate.

In various method implementations the pre-mold may be applied to the lead124prior to coupling with either the first substrate128or second substrate130. In implementations, the pre-mold material196may be applied following coupling of the lead124to either or both the first substrate128and the second substrate130. In various implementations where coined leads are employed, a coined lead may be used in place of the lead124in any of the method or structure implementations disclosed herein. The various gel/mold materials used internally in the package may be, by non-example, a silicone, an epoxy, a resin, any combination thereof, or any other molding reporting compound. In various method implementations, the gel/mold material may be delivered by capillary flow into the space between the first substrate128and the second substrate130. In other implementations, the material may be pre-dispensed prior to coupling of the first substrate128of the second substrate130and then spread as the first substrate128is pressed/placed over the second substrate130. In various implementations the use of the mold/gel material136may aid in increasing creepage or clearance and the package.

The various package implementations disclosed herein may allow the package to have solid support between the first substrate and the second substrate which can improve clamping during the encapsulation process and may also ease the control of the stack of substrates and leads at the three dimensional reflow process. The use of the electrically isolated islands may also allow the leadframe that contains the various leads to be flat without having to include any upset or downset portions. This ability to work with a flat leadframe may reduce the overall complexity of the leadframe manufacturing process and reduce cost. The result of the use of electrically isolated islands also has the effect that the electrical connection of each pins/terminal to the first substrate and the second substrate is defined by the patterned and electrically conductive material on each substrate.

Various implementations of semiconductor packages like those disclosed herein may be used for a wide variety of semiconductor die types to form a wide variety of electrical components. For example, the semiconductor package implementations disclosed herein may permit a spacer-free half bridge dual side cooled power module to be formed. The ability to dual side cool the package may be a direct result of allowing material of the first substrate and material of the second substrate to be exposed through the encapsulant on both sides of the package that permits cooling components to be attached to each side as in the implementation illustrated inFIG.2. In other implementations, the use of a premolded lead frame to increase clearance/creepage distance may enable the package to be used for an inverter system.

While in various implementations disclosed in this document the use of spacers has not been illustrated, spacers may still be employed to help support the first substrate and second substrate and locations where a semiconductor die or electrical component is not present. Because of the thickness of the package designs disclosed herein, however, the thickness of the spacer may be reduced and/or the size of the spacer increased as a result. A larger spacer can enhance thermal transfer through the package from the electrical components. Various package designs disclosed herein may also have a lower bill of materials cost because any spacers used may be able to be bare metal and thinner than in packages that include leads with upset and downset portions. Also, in various implementations, standard thickness substrates like direct bonded copper substrates may be able to be employed in a package that has thinner overall thickness than that ordinarily possible with such substrates.

Additionally, because the package is thinner overall, less mold compound is needed which can further reduce cost. Because in various package implementations the use of multiple solder layers in combination with spacers to achieve a precisely controlled height above each die and/or electrical component is not needed, processes involved in performing true height of the solders or using solder pre-forms may not be required. Also, in various method implementations, the thinner thickness of the package may permit the need for no grinding of the encapsulant by eliminating the needed to overmold. Because no preforms may be used, no solder preform pick and place operations may be needed in the package assembly process to ensure that solders reach proper heights in various locations on the package during assembly. In some implementations the dispensing of solder may also not be used in favor of solder printing using stencil or squeegee printing techniques which may reduce the cost and/or complexity of the process. The ability to eliminate the upset and down set portions of the leads may also allow the manufacturing process to be carried out in a panel form with one single planar lead frame panel used during processing of multiple semiconductor packages. Also, during manufacturing, the thinner package may make it easier to use x-ray metrology because the electrically conductive layers included in the package may be thinner.

In various method and package implementations disclosed herein the use of holes through the material of the first substrate and/the second substrate may be employed to reduce the risk of voids being formed during the gel/mold process. In various implementations, the warpage of the package may be managed by designing the first substrate and/or the second substrate in particular ways to manage the stress and/or employing particular mold compound that have desired warpage characteristics.

Where the description above refers to particular implementations of semiconductor packages and implementing components, sub-components, methods and sub-methods, it should be readily apparent that a number of modifications may be made without departing from the spirit thereof and that these implementations, implementing components, sub-components, methods and sub-methods may be applied to other semiconductor packages.