Patent ID: 12211846

DETAILED DESCRIPTION

Advantages and features of the inventive concepts and methods of accomplishing the same may be understood more readily by reference to the following detailed description of example embodiments and the accompanying drawings. The inventive concepts may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concepts of the invention to those skilled in the art, and the inventive concepts will only be defined by the appended claims. In the drawings, the thickness of layers and regions are exaggerated for clarity.

It will be understood that when an element or layer is referred to as being “on,” “connected to,” or “coupled to” another element or layer, it can be directly on, directly connected to or coupled to another element or layer or intervening elements or layers may be present. In contrast, when an element is referred to as being “directly on,” “directly connected to” or “directly coupled to” another element or layer, there are no intervening elements or layers present. Like numbers refer to like elements throughout. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items. In addition, it will also be understood that when a layer is referred to as being “between” two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.

It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. Thus, for example, a first element, a first component or a first section discussed below could be termed a second element, a second component or a second section without departing from the teachings of the inventive concepts.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of example embodiments. As used herein, the singular forms “a,” “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It is noted that the use of any and all examples, or example terms provided herein is intended merely to better illuminate the invention and is not a limitation on the scope of the invention unless otherwise specified. Further, unless defined otherwise, all terms defined in generally used dictionaries may not be overly interpreted.

In the drawing figures, the dimensions of layers and regions may be exaggerated for clarity of illustration. Like reference numerals refer to like elements throughout. The same reference numbers indicate the same components throughout the specification.

Spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as “below” or “beneath” other elements or features would then be oriented “above” the other elements or features. Thus, the example term “below” can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

Example embodiments are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of example embodiments. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, example embodiments should not be construed as limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an implanted region illustrated as a rectangle will, typically, have rounded or curved features and/or a gradient of implant concentration at its edges rather than a binary change from implanted to non-implanted region. Likewise, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation takes place. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of example embodiments.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which example embodiments belong. It will be further understood that terms, such as those defined in commonly-used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein. As used herein, expressions such as “at least one of,” when preceding a list of elements, modify the entire list of elements and do not modify the individual elements of the list.

When the terms “about” or “substantially” are used in this specification in connection with a numerical value, it is intended that the associated numerical value include a tolerance of ±10% around the stated numerical value. Moreover, when reference is made to percentages in this specification, it is intended that those percentages are based on weight, i.e., weight percentages. The expression “up to” includes amounts of zero to the expressed upper limit and all values therebetween. When ranges are specified, the range includes all values therebetween such as increments of 0.1%. Moreover, when the words “generally” and “substantially” are used in connection with geometric shapes, it is intended that precision of the geometric shape is not required but that latitude for the shape is within the scope of the disclosure. Although the tubular elements of the embodiments may be cylindrical, other tubular cross-sectional forms are contemplated, such as square, rectangular, oval, triangular and others.

Although corresponding plan views and/or perspective views of some cross-sectional view(s) may not be shown, the cross-sectional view(s) of device structures illustrated herein provide support for a plurality of device structures that extend along two different directions as would be illustrated in a plan view, and/or in three different directions as would be illustrated in a perspective view. The two different directions may or may not be orthogonal to each other. The three different directions may include a third direction that may be orthogonal to the two different directions. The plurality of device structures may be integrated in a same electronic device. For example, when a device structure (e.g., a memory cell structure or a transistor structure) is illustrated in a cross-sectional view, an electronic device may include a plurality of the device structures (e.g., memory cell structures or transistor structures), as would be illustrated by a plan view of the electronic device. The plurality of device structures may be arranged in an array and/or in a two-dimensional pattern.

Although the drawings regarding a semiconductor device according to some example embodiments exemplify a fin-type transistor (FinFET) comprising a channel region in a fin-type pattern shape, example embodiments are not limited thereto. It is of course possible that a semiconductor device according to some example embodiments may include a tunneling transistor (tunneling FET), a transistor comprising nanowire, a transistor comprising nano-sheet, or a three-dimensional (3D) transistor. Further, a semiconductor device according to some example embodiments may include a bipolar junction transistor, a laterally diffused metal oxide semiconductor (LDMOS) transistor, and so on.

Moreover, while a semiconductor device according to some example embodiments is exemplified as a multi-channel transistor using fin-type pattern, the semiconductor device may be a planar transistor as well.

Hereinbelow, a semiconductor device according to some example embodiments will be explained with reference toFIGS.1to5B.

FIG.1is a layout diagram provided to explain a semiconductor device according to some example embodiments.FIG.2is a cross sectional view taken on lines A-A and B-B ofFIG.1.FIG.3illustrates the first gate structure portion and the third gate structure portion ofFIG.2in enlargement.FIGS.4A to4Dare various examples of a cross sectional view taken on line C-C ofFIG.1.FIGS.5A and5Bare various examples of a cross sectional view taken on line D-D ofFIG.1.

Referring toFIGS.1to5B, the semiconductor device according to some example embodiments may include a first fin-type pattern110, a second fin-type pattern310, a first gate structure120, a second gate structure220, a third gate structure320, a fourth gate structure420, a first contact170, and a second contact370.

The substrate100may include a first region I and a second region II. The first region I and the second region II may be the regions that are spaced apart from each other, or connected with each other. Further, the transistor formed in the first region I and the transistor formed in the second region II may be of a same type, or different types from each other.

The substrate100may be a bulk silicon or a silicon-on-insulator (SOI). Alternatively, the substrate100may be a silicon substrate, or may include other substance such as, for example, silicon germanium, silicon germanium on insulator (SGOI), indium antimonide, lead telluride compound, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide, but not limited thereto.

In the first region I, the first fin-type pattern110, the first gate structure120, the second gate structure220, and the first contact170may be formed.

The first fin-type pattern110may extend longitudinally on the substrate100and in a first direction X1. The first fin-type pattern110may protrude from the substrate100.

The first fin-type pattern110may be a part of the substrate100, and may include an epitaxial layer grown from the substrate100.

The first fin-type pattern110may include an element semiconductor material such as silicon or germanium, for example. Further, the first fin-type pattern110may include a compound semiconductor such as, for example, IV-IV group compound semiconductor or III-V group compound semiconductor.

Specifically, take the IV-IV group compound semiconductor for instance, the first fin-type pattern110may be a binary compound or a ternary compound including, for example, at least two or more of carbon (C), silicon (Si), germanium (Ge), or tin (Sn), or the above-mentioned binary or ternary compound doped with a IV group element.

Take the III-V group compound semiconductor for instance, the first fin-type pattern110may be one of a binary compound, a ternary compound or a quaternary compound which is formed by a combination of a III group element which may be at least one of aluminum (Al), gallium (Ga), or indium (In), with a V group element which may be one of phosphorus (P), arsenic (As) or antimony (Sb).

In the semiconductor device according to some example embodiments, it is assumed that the first fin-type pattern110is a silicon fin-type pattern.

The field insulating film105may be formed to surround a portion of the first fin-type pattern110. The first fin-type pattern110may be defined by the field insulating film105. Accordingly, a portion of the first fin-type pattern110may protrude upward higher than an upper surface of the field insulating film105.

The field insulating film105may include, for example, an oxide film, a nitride film, an oxynitride film, or a film combining an oxide film, a nitride film, an oxynitride film.

UnlikeFIG.4A, inFIG.4C, a first field liner106may be additionally formed between the field insulating film105and the first fin-type pattern110, and between the field insulating film105and the substrate100.

The first field liner106may be formed along a sidewall of the first fin-type pattern110surrounded by the field insulating film105, and along an upper surface of the substrate100. The first field liner106may not protrude upward higher than an upper surface of the field insulating film105.

The first field liner106may include at least one of, for example, polysilicon, amorphous silicon, silicon oxynitride, silicon nitride, or silicon oxide.

Further, unlikeFIG.4A, inFIG.4D, a second field liner107and a third field liner108may be additionally formed between the field insulating film105and the first fin-type pattern110, and between the field insulating film105and the substrate100.

The second field liner107may be formed along the sidewall of the first fin-type pattern110surrounded by the field insulating film105, and along the upper surface of the substrate100.

The third field liner108may be formed on the second field liner107. The third field liner108may be formed along the second field liner107.

The second field liner107may include, for example, polysilicon or amorphous silicon. The third field liner108may include, for example, silicon oxide.

The first gate structure120may extend in a second direction Y1. The first gate structure120may be formed to intersect the first fin-type pattern110.

The first gate structure120may include a first gate electrode130, a first gate insulating film125, and a first gate spacer135.

The second gate structure220may extend in the second direction Y1. The second gate structure220may be formed to intersect the first fin-type pattern110. The second gate structure220may be spaced apart from the first gate structure120by a first distance L1.

The second gate structure220may include a second gate electrode230, a second gate insulating film225, and a second gate spacer235.

The first gate spacer135and the second gate spacer235may be formed on the first fin-type pattern110, respectively. The first gate spacer135may define a first trench135textending in the second direction Y1. The second gate spacer235may define a second trench235textending in the second direction Y1.

An outer sidewall of the first gate spacer135may be a first sidewall120aof the first gate structure and a second sidewall120bof the first gate structure that extend in the second direction Y1. Further, an outer sidewall of the second gate spacer235may be a sidewall220aof the second gate structure.

Further, depending on examples, the first gate spacer135and the second gate spacer235may serve as the guides to form self-aligned contacts. Accordingly, the first gate spacer135and the second gate spacer235may include a material having etch selectivity with respect to a first interlayer insulating film180which will be described below.

The first gate spacer135and the second gate spacer235may each include at least one of, for example, silicon nitride (SiN), silicon oxynitride (SiON), silicon dioxide (SiO2), silicon oxycarbonitride (SiOCN), and a combination thereof.

As illustrated, the first gate spacer135and the second gate spacer235may each be a single film. However, this is provided only for convenience of illustration and example embodiments are not limited thereto.

When the first gate spacer135and the second gate spacer235are a plurality of films, at least one of the films of the first gate spacer135and the second gate spacer235may include a low-k dielectric material such as silicon oxycarbonitride (SiOCN).

Further, when the first gate spacer135and the second gate spacer235are a plurality of films, at least one of the films of the first gate spacer135and the second gate spacer235may have a L-shape.

Further, when the first gate spacer135and the second gate spacer235are a plurality of films, the first gate spacer135and the second gate spacer235may each be a combination of an L-shaped film and an I-shaped film.

The first gate insulating film125may be formed on the first fin-type pattern110and the field insulating film105. The first gate insulating film125may be formed along the sidewall and the bottom surface of the first trench135t. The first gate insulating film125may be formed along a profile of the first fin-type pattern110protruding upward higher than the field insulating film105, and along the upper surface of the field insulating film105and the inner sidewall of the first gate spacer135.

Further, an interfacial layer126may be additionally formed between the first gate insulating film125and the first fin-type pattern110. Although not illustrated, referring toFIG.2, an interfacial layer may also be additionally formed between the first gate insulating film125and the first fin-type pattern110.

As illustrated inFIG.4B, the interfacial layer126may be formed along the profile of the first fin-type pattern110that protrudes higher than the upper surface of the field insulating film105, although example embodiments are not limited thereto.

The interfacial layer126may extend along the upper surface of the field insulating film105according to a method used for forming the interfacial layer126.

Hereinbelow, example embodiments are explained by referring to drawings in which illustration of the interfacial layer126is omitted for convenience of explanation.

The second gate insulating film225may be formed on the first fin-type pattern110. The second gate insulating film225may be formed along the sidewall and the bottom surface of the second trench235t.

Description of the second gate insulating film225may be similar to or the same as that of the first gate insulating film125, and will not be redundantly described below.

The first gate insulating film125and the second gate insulating film225may each include, for example, at least one of silicon oxide, silicon oxynitride, silicon nitride, or a high-k dielectric material with a higher dielectric constant than silicon oxide.

For example, the high-k dielectric material may include one or more of hafnium oxide, hafnium silicon oxide, hafnium aluminum oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, or lead zinc niobate.

Further, while the high-k dielectric material described above is explained main with reference to oxides, alternatively, the high-k dielectric material may include one or more of the nitride (e.g., hafnium nitride) or the oxynitride (e.g., hafnium oxynitride) of the metal materials described above, but not limited thereto.

The first gate electrode130may be formed on the first gate insulating film125. The first gate electrode130may fill the first trench135t.

The second gate electrode230may be formed on the second gate insulating film225. The second gate electrode230may fill the second trench235t.

As illustrated, the first gate electrode130and the second gate electrode230may be single films. However, this is provided only for convenience of illustration and example embodiments are not limited thereto. That is, it is of course possible that the first gate electrode130and the second gate electrode230may each include a plurality of films such as a barrier film, a work function adjustment film, a filling film, and so on.

The first gate electrode130and the second gate electrode230may include at least one of, for example, titanium nitride (TiN), tantalum carbide (TaC), tantalum nitride (TaN), titanium silicon nitride (TiSiN), tantalum silicon nitride (TaSiN), tantalum titanium nitride (TaTiN), titanium aluminum nitride (TiAlN), tantlum aluminum nitride (TaAlN), tungsten nitride (WN), ruthenium (Ru), titanium aluminum (TiAl), titanium aluminum carbonitride (TiAlC—N), titanium aluminum carbide (TiAlC), titanium carbide (TiC), tantalum carbonitride (TaCN), tungsten (W), aluminum (Al), copper (Cu), cobalt (Co), titanium (Ti), tantalum (Ta), nickel (Ni), platinum (Pt), nickel platinum (Ni—Pt), niobium (Nb), niobium nitride (NbN), niobium carbide (NbC), molybdenum (Mo), molybdenum nitride (MoN), molybdenum carbide (MoC), tungsten carbide (WC), rhodium (Rh), palladium (Pd), iridium (Ir), osmium (Os), silver (Ag), gold (Au), sinc (Zn), vanadium (V), and a combination thereof.

The first gate electrode130and the second gate electrode230may each include a conductive metal oxide, a conductive metal oxynitride, and so on, and an oxidized form of the materials described above.

The first source/drain140may be formed between the first gate structure120and the second gate structure220. The first source/drain140may be formed adjacent to the first sidewall120aof the first gate structure.

The second source/drain145may be formed adjacent to the second sidewall120bof the first gate structure.

As illustrated, the first source/drain140and the second source/drain145may include an epitaxial layer formed within the first fin-type pattern110, although example embodiments are not limited thereto. The first source/drain140and the second source/drain145may be impurity regions formed within the first fin-type pattern110, and may include an epitaxial layer formed along a profile of the first fin-type pattern110.

For example, the first source/drain140and the second source/drain145may be raised source/drains.

As illustrated inFIGS.5A and5B, the first source/drain140may not include an outer circumference extending along the upper surface of the field insulating film105, but this is provided only for convenience of explanation and the example embodiments are not limited thereto. That is, the first source/drain140may include an outer circumference extending along the upper surface of the field insulating film105and being in surface-contact with the field insulating film105.

When the semiconductor device in the first region I according to some example embodiments is a PMOS transistor, the first source/drain140and the second source/drain145may include a compressive stress material. For example, the compressive stress material may be a material such as SiGe that has a higher lattice constant compared to Si. For example, the compressive stress material can enhance mobility of the carrier in the channel region by exerting compressive stress on the first fin-type pattern110.

Alternatively, when the semiconductor device in the first region I according to some example embodiments is an NMOS transistor, the first source/drain140and the second source/drain145may include a tensile stress material. For example, when the first fin-type pattern110is silicon, the first source/drain140and the second source/drain145may be a material such as SiC that has a smaller lattice constant than the silicon. For example, the tensile stress material can enhance mobility of the carrier in the channel region by exerting tensile stress on the first fin-type pattern110.

Meanwhile, when the semiconductor device in the first region I according to some example embodiments is an NMOS transistor, the first source/drain140and the second source/drain145may include a same material as the first fin-type pattern110, i.e., silicon.

In the second region II, the second fin-type pattern310, the third gate structure320, the fourth gate structure420, and the second contact370may be formed.

The second fin-type pattern310may extend longitudinally on the substrate100in a third direction X2. The second fin-type pattern310may protrude from the substrate100.

The second fin-type pattern310may be a part of the substrate100, and may include an epitaxial layer grown from the substrate100.

Like the first fin-type pattern110, the second fin-type pattern310may include a variety of semiconductor materials. However, in the semiconductor device according to some example embodiments, it is assumed that the second fin-type pattern310is a silicon fin-type pattern.

The third gate structure320may extend in a fourth direction Y2. The third gate structure320may be formed to intersect the second fin-type pattern310.

The third gate structure320may include a third gate electrode330, a third gate insulating film325, and a third gate spacer335.

The fourth gate structure420may extend in the fourth direction Y2. The fourth gate structure420may be formed to intersect the second fin-type pattern310. The fourth gate structure420may be spaced apart from the third gate structure320by a second distance L2.

The fourth gate structure420may include a fourth gate electrode430, a fourth gate insulating film425, and a fourth gate spacer435.

The third gate spacer335and the fourth gate spacer435may be formed on the second fin-type pattern310, respectively. The third gate spacer335may define a third trench335textending in the fourth direction Y2. The fourth gate spacer435may define a fourth trench435textending in the fourth direction Y2.

An outer sidewall of the third gate spacer335may be a first sidewall320aof the third gate structure and a second sidewall320bof the third gate structure that extend in the fourth direction Y2. Further, an outer sidewall of the fourth gate spacer435may be a sidewall420aof the fourth gate structure.

Description about the third gate spacer335and the fourth gate spacer435may be substantially similar to or the same as the description about the first gate spacer135and the second gate spacer235, and therefore, will not be redundantly described below.

The third gate insulating film325may be formed on the second fin-type pattern310. The third gate insulating film325may be formed along the sidewall and a bottom surface of the third trench335t.

The fourth gate insulating film425may be formed on the second fin-type pattern310. The fourth gate insulating film425may be formed along the sidewall and the bottom surface of the fourth trench435t.

Description of the third gate insulating film325and the fourth gate insulating film425may be substantially similar to or the same as that of the first gate insulating film125, and therefore, will not be redundantly described below.

The third gate insulating film325and the fourth gate insulating film425may each include, for example, at least one of silicon oxide, silicon oxynitride, silicon nitride, or a high-k dielectric material with a higher dielectric constant than silicon oxide.

The third gate electrode330may be formed on the third gate insulating film325. The third gate electrode330may fill the third trench335t.

The fourth gate electrode430may be formed on the fourth gate insulating film425. The fourth gate electrode430may fill the fourth trench435t.

The materials and stack structures of the third gate electrode330and the fourth gate electrode430will not be redundantly described below, as the description may be substantially similar to or the same as that of the first gate electrode130and the second gate electrode230.

The third source/drain340may be formed between the third gate structure320and the fourth gate structure420. The third source/drain340may be formed adjacent to the first sidewall320aof the third gate structure.

The fourth source/drain345may be formed adjacent to the second sidewall320bof the third gate structure.

As illustrated, the third source/drain340and the fourth source/drain345may include an epitaxial layer formed within the second fin-type pattern310, although example embodiments are not limited thereto. The third source/drain340and the fourth source/drain345may be impurity regions formed within the second fin-type pattern310, and may include an epitaxial layer formed along a profile of the second fin-type pattern310.

For example, the third source/drain340and the fourth source/drain345may be raised source/drains.

When the semiconductor device in the second region II according to some example embodiments is a PMOS transistor, the third source/drain340and the fourth source/drain345may include a compressive stress material. For example, the compressive stress material may be a material such as SiGe that has a higher lattice constant compared to Si. For example, the compressive stress material can enhance carrier mobility in the channel region by exerting compressive stress on the second fin-type pattern310.

Alternatively, when the semiconductor device in the second region II according to some example embodiments is an NMOS transistor, the third source/drain340and the fourth source/drain345may include a tensile stress material. For example, when the first fin-type pattern310is silicon, the third source/drain340and the fourth source/drain345may be a material such as SiC that has a smaller lattice constant than silicon. For example, the tensile stress material can enhance carrier mobility in the channel region by exerting tensile stress on the second fin-type pattern310.

Meanwhile, when the semiconductor device in the second region II according to some example embodiments is an NMOS transistor, the third source/drain340and the fourth source/drain345may include a same material as the second fin-type pattern310, i.e., silicon.

The first interlayer insulating film180may be formed on the substrate100of the first region I. The first interlayer insulating film180may cover the first fin-type pattern110, the first source/drain140, and the second source/drain145.

The first interlayer insulating film180may surround the first sidewall120aof the first gate structure, the second sidewall120bof the first gate structure, and the sidewall220aof the second gate structure.

The upper surface of the first interlayer insulating film180may be in the same plane as the upper surface of the first gate structure120and the upper surface of the second gate structure220.

The first interlayer insulating film180may include a first lower interlayer insulating film181and a first upper interlayer insulating film182stacked on the substrate100in a sequential order.

The first lower interlayer insulating film181may be formed on the first fin-type pattern110. The first lower interlayer insulating film181may surround a portion of the first sidewall120aof the first gate structure, a portion of the second sidewall120bof the first gate structure, and a portion of the sidewall220aof the second gate structure.

For example, the first lower interlayer insulating film181may include silicon oxide, silicon oxynitride, silicon nitride, flowable oxide (FOX), Tonen silazene (TOSZ), undoped silica glass (USG), borosilica glass (BSG), phosphosilica glass (PSG), borophosphosilica glass (BPSG), plasma enhanced tetraethyl orthosilicate (PETEOS), fluoride silicate glass (FSG), carbon doped silicon oxide (CDO), xerogel, aerogel, amorphous fluorinated carbon, organo silicate glass (OSG), parylene, bis-benzocyclobutenes (BCB), SiLK, polyimide, porous polymeric material, or a combination thereof, but not limited thereto.

The first upper interlayer insulating film182may be formed on the first lower interlayer insulating film181. The first upper interlayer insulating film182may surround the first sidewall120aof the first gate structure, the second sidewall120bof the first gate structure, and the sidewall220aof the second gate structure that are not surrounded by the first lower interlayer insulating film181.

For example, the first upper interlayer insulating film182may include silicon oxide, silicon oxynitride, silicon nitride, flowable oxide (FOX), Tonen silazene (TOSZ), undoped silica glass (USG), borosilica glass (BSG), phosphosilica glass (PSG), borophosphosilica glass (BPSG), plasma enhanced tetraethyl orthosilicate (PETEOS), fluoride silicate glass (FSG), carbon doped silicon oxide (CDO), xerogel, aerogel, amorphous fluorinated carbon, organo silicate glass (OSG), parylene, bis-benzocyclobutenes (BCB), SiLK, polyimide, porous polymeric material, or a combination thereof, but not limited thereto.

The first lower interlayer insulating film181is not interposed between the first upper interlayer insulating film182and the sidewalls120a,120bof the first gate structure, nor between the first upper interlayer insulating film182and the sidewall220aof the second gate structure.

The first lower interlayer insulating film181may surround the sidewall of the first gate structure120to a height that corresponds to the thickness t11of the first lower interlayer insulating film181. Further, the first upper interlayer insulating film182may surround the sidewall of the first gate structure120to a height that corresponds to the thickness t12of the first upper interlayer insulating film182.

Further, the boundary surface between the first lower interlayer insulating film181and the first upper interlayer insulating film182may be a curved surface, for example. When forming the first lower interlayer insulating film181by using dry etch process and then forming the first upper interlayer insulating film182on the first lower interlayer insulating film181, the boundary surface between the first lower interlayer insulating film181and the first upper interlayer insulating film182may be a curved surface.

The second interlayer insulating film380may be formed on the substrate100of the second region II. The second interlayer insulating film380may cover the second fin-type pattern310, the third source/drain340, and the fourth source/drain345.

The second interlayer insulating film380may surround the first sidewall320aof the third gate structure, the second sidewall320bof the third gate structure, and the sidewall420aof the fourth gate structure420.

The upper surface of the second interlayer insulating film380may be in the same plane as, for example, the upper surface of the third gate structure320and the upper surface of the fourth gate structure420.

The second interlayer insulating film380may include a second lower interlayer insulating film381and a second upper interlayer insulating film382stacked on the substrate100in a sequential order.

The second lower interlayer insulating film381may be formed on the second fin-type pattern310. The second lower interlayer insulating film381may surround a portion of the first sidewall320aof the third gate structure, a portion of the second sidewall320bof the third gate structure, and a portion of the sidewall420aof the fourth gate structure.

The second upper interlayer insulating film382may be formed on the second lower interlayer insulating film381. The second upper interlayer insulating film382may surround the first sidewall320aof the third gate structure, the second sidewall320bof the third gate structure, and the sidewall420aof the fourth gate structure that are not surrounded by the second lower interlayer insulating film381.

The second lower interlayer insulating film381is not interposed between the second upper interlayer insulating film382and the sidewalls320a,320bof the third gate structure, nor between the second upper interlayer insulating film382and the sidewall420aof the fourth gate structure.

The second lower interlayer insulating film381may surround the sidewall of the third gate structure320to a height that corresponds to the thickness t21of the second lower interlayer insulating film381. Further, the second upper interlayer insulating film382may surround the sidewall of the third gate structure320to a height that corresponds to the thickness t22of the second upper interlayer insulating film382.

Further, the boundary surface between the second lower interlayer insulating film381and the second upper interlayer insulating film382may be a curved surface, for example.

The second lower interlayer insulating film381may include a same material as the first lower interlayer insulating film181.

Hereinbelow, it is assumed that the second upper interlayer insulating film382includes the same material as the first upper interlayer insulating film182, but example embodiments are not limited thereto.

A third interlayer insulating film190may be formed on the first interlayer insulating film180and the second interlayer insulating film380. The third interlayer insulating film190may be formed on the first region I and the second region II of the substrate100, for example.

For example, the third interlayer insulating film190may include silicon oxide, silicon oxynitride, silicon nitride, flowable oxide (FOX), Tonen silazene (TOSZ), undoped silica glass (USG), borosilica glass (BSG), phosphosilica glass (PSG), borophosphosilica glass (BPSG), plasma enhanced tetraethyl orthosilicate (PETEOS), fluoride silicate glass (FSG), carbon doped silicon oxide (CDO), xerogel, aerogel, amorphous fluorinated carbon, organo silicate glass (OSG), parylene, bis-benzocyclobutenes (BCB), SiLK, polyimide, porous polymeric material, or a combination thereof, but not limited thereto.

The first contact170may be formed between the first gate structure120and the second gate structure220. The first contact170may be formed adjacent to the first sidewall120aof the first gate structure.

The first contact170may be formed within the third interlayer insulating film190and the first interlayer insulating film180. The first contact170may not contact the first gate structure120and the second gate structure220. The first contact170may be connected with the first source/drain140.

The first contact170may have a first width W1. For example, the first width W1of the first contact170may be based on or correlated to the respective widths of the upper surface of the first gate structure120and the upper surface of the second gate structure220, but this is provided only for convenience of explanation and example embodiments are not limited thereto. That is, the first width W1of the first contact170may be based on the width of the upper surface of the third interlayer insulating film190.

Further, the first width W1of the first contact170may be a width in the first direction X1.

Referring toFIG.5A, the boundary surface between the first contact170and the first source/drain140may be a facet of an epitaxial layer included in the first source/drain140.

Alternatively, referring toFIG.5B, the boundary surface between the first contact170and the first source/drain140may be a curved surface. The boundary surface between the first contact170and the first source/drain140may depend on which etch process is used for the contact hole forming process to form the first contact170.

Although not illustrated inFIGS.5A and5B, a silicide layer may be additionally formed between the first contact170and the first source/drain140.

The second contact370may be formed between the third gate structure320and the fourth gate structure420. The second contact370may be formed adjacent to the first sidewall320aof the third gate structure.

The second contact370may be formed within the third interlayer insulating film190and the second interlayer insulating film380. The second contact370may not contact the third gate structure320and the fourth gate structure420. The second contact370may be connected with the third source/drain340.

The second contact370may have a second width W2. For example, the second width W2of the second contact370may be based on the upper surface of the third gate structure320and the upper surface of the fourth gate structure420. Further, the second width W2of the second contact370may be a width in the third direction X2.

The boundary surface between the second contact370and the third source/drain340may be similar or the same as the one illustrated inFIGS.5A and5B.

The first contact170and the second contact370may include at least one of, for example, tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), ruthenium (Ru), cobalt (Co), nickel (Ni), nickel boride (NiB), tungsten nitride (WN), aluminum (Al), tungsten (W), copper (Cu), cobalt (Co) or doped polysilicon.

While the first contact170and the second contact370are illustrated to be a single pattern, this is only for convenience of explanation and the example embodiments are not limited thereto. The first contact170and the second contact370may each include a barrier film, and a filling film formed on the barrier film.

The first distance L1of spacing between the first gate structure120and the second gate structure220may be different from the second distance L2of spacing between the third gate structure320and the fourth gate structure420. Further, the first width W1of the first contact170may be different from the second width W2of the second contact370.

For example, the first distance L1of spacing between the first gate structure120and the second gate structure220may be lower than the second distance L2of spacing between the third gate structure320and the fourth gate structure420. Further, the first width W1of the first contact170may be lower than the second width W2of the second contact370.

In other words, in a semiconductor device according to some example embodiments, the width of the contacts formed between gate structures may increase as the distances between adjacent gate structures increase.

In a semiconductor device according to an example embodiment, the stress characteristic of the first lower interlayer insulating film181may be different from the stress characteristic of the first upper interlayer insulating film182. Further, the stress characteristic of the second lower interlayer insulating film381may be different from the stress characteristic of the second upper interlayer insulating film382.

More specifically, for example, when the first lower interlayer insulating film181has a tensile stress characteristic, the first upper interlayer insulating film182may have a compressive stress characteristic. On the contrary, when the first lower interlayer insulating film181has a compressive stress characteristic, the first upper interlayer insulating film182may have a tensile stress characteristic.

The expression “tensile stress characteristic” as used herein refers to the interlayer insulating film having a tension that pulls the gate electrode or the gate spacers toward the interlayer insulating film.

More specifically, by the interlayer insulating film having the tensile stress characteristic, the gate spacers are subject to a force that acts in a direction from the gate electrode to the interlayer insulating film.

On the contrary, by the interlayer insulating film having the compressive stress characteristic, the gate spacers are subject to a force that acts in a direction from the interlayer insulating film to the gate electrode.

Because the first interlayer insulating film180may include the first lower interlayer insulating film181and the first upper interlayer insulating film182having different stress characteristics from each other, the overall stress characteristic of the first interlayer insulating film180may vary according to differences in thickness, volume, and so on between the first lower interlayer insulating film181and the first upper interlayer insulating film182.

Additionally, the first lower interlayer insulating film181and the first upper interlayer insulating film182may include different materials from each other, or alternatively, may include the same material as each other.

When the first lower interlayer insulating film181and the first upper interlayer insulating film182include a material same as each other, the conditions for forming the first lower interlayer insulating film181, including heat treatment condition, and the conditions for forming the first upper interlayer insulating film182, including heat treatment condition, may be different from each other. Accordingly, the first lower interlayer insulating film181and the first upper interlayer insulating film can have different stress characteristics from each other.

The example in which the first lower interlayer insulating film181and the first upper interlayer insulating film182include the same material will be described with reference toFIG.13and others.

The second lower interlayer insulating film381may have the same material and may be subject to the same post-processing as the first lower interlayer insulating film181. Accordingly, the second lower interlayer insulating film381may have the same stress characteristic as the first lower interlayer insulating film181.

For convenience of explanation, it is assumed hereinbelow that the first lower interlayer insulating film181and the second lower interlayer insulating film381have tensile stress characteristic, and the first upper interlayer insulating film182and the second upper interlayer insulating film382have compressive stress characteristic.

Referring toFIG.3, the first gate electrode130includes a sidewall130sand a bottom surface130b. The third gate electrode330includes a sidewall330sand a bottom surface330b.

The sidewall130sof the first gate electrode may make a first angle α with respect to the bottom surface130bof the first gate electrode. The sidewall330sof the third gate electrode may make a second angle β with respect to the bottom surface330bof the third gate electrode.

In this case, the first angle α of the sidewall130sof the first gate electrode with respect to the bottom surface130bof the first gate electrode may be a right angle, and the second angle β of the sidewall330sof the third gate electrode with respect to the bottom surface330bof the third gate electrode may be a right angle.

In other words, the width of the first gate electrode130and the width of the third gate electrode330may be constant as the distance from the upper surface of the substrate100increases. The width of the first gate electrode130may be constant as the distance from the bottom surface130bof the first gate electrode increases, and the width of the third gate electrode330may be constant as the distance from the bottom surface330bof the third gate electrode increases.

Additionally, the slope of the sidewall130sof the first gate electrode and the slope of the sidewall330sof the third gate electrode may have the same sign.

As an alternative embodiment, the point where the sidewall130sof the first gate electrode and the bottom surface130bof the first gate electrode meet, and the point where the sidewall330sof the third gate electrode and the bottom surface330bof the third gate electrode meet, may be rounded. However, even in such examples, it is apparent that those skilled in the art will be able to obtain the slope of the sidewall130sof the first gate electrode and the slope of the sidewall330sof the third gate electrode.

Meanwhile, as an alternative to the illustration inFIG.3, the first angle α of the sidewall130sof the first gate electrode with respect to the bottom surface130bof the first gate electrode, and the second angle β of the sidewall330sof the third gate electrode with respect to the bottom surface330bof the third gate electrode may both be obtuse angles or acute angles. Even in the above example, the sign of the slope of the sidewall130sof the first gate electrode, and the sign of the slope of the sidewall330sof the third gate electrode may still be identical.

When both the first angle α of the sidewall130sof the first gate electrode with respect to the bottom surface130bof the first gate electrode, and the second angle β of the sidewall330sof the third gate electrode with respect to the bottom surface330bof the third gate electrode are obtuse angles, it is defined herein that both the sign of the slope of the sidewall130sof the first gate electrode and the sign of the slope of the sidewall330sof the third gate electrode are positive signs.

If the situation is opposite the example described above, then it is defined herein that the sign of the slope of the sidewall130sof the first gate electrode and the sign of the slope of the sidewall330sof the third gate electrode are negative signs.

When both the slope of the sidewall130sof the first gate electrode and the slope of the sidewall330sof the third gate electrode have positive signs, the width of the first gate electrode130and the width of the third gate electrode330may increase as the distance from the upper surface of the substrate100increases.

On the contrary, when both the slope of the sidewall130sof the first gate electrode and the slope of the sidewall330sof the third gate electrode have negative signs, the width of the first gate electrode130and the width of the third gate electrode330may decrease as the distance from the upper surface of the substrate100increases.

When both the slope of the sidewall130sof the first gate electrode and the slope of the sidewall330sof the third gate electrode have the same sign, the stress characteristic of the first interlayer insulating film180and the stress characteristic of the second interlayer insulating film380may be identical.

The first distance L1between the first gate structure120and the second gate structure220may be lower than the second distance L2between the third gate structure320and the fourth gate structure420. In this case, when the thickness t12of the first upper interlayer insulating film182and the thickness t22of the second upper interlayer insulating film382are substantially equal, because the second upper interlayer insulating film382has a greater volume than the volume of the first upper interlayer insulating film182, the compressive stress of the second upper interlayer insulating film382becomes greater than the compressive stress of the first upper interlayer insulating film182.

In such example, the compressive stress exerted by the second interlayer insulating film380to the third gate structure320becomes greater than the compressive stress exerted by the first interlayer insulating film180to the first gate structure120. Accordingly, the stress characteristic of the first interlayer insulating film180and the stress characteristic of the second interlayer insulating film380cannot be identical.

Accordingly, when both the slope of the sidewall130sof the first gate electrode and the slope of the sidewall330sof the third gate electrode have the same sign, the thickness t12of the first upper interlayer insulating film182and the thickness t22of the second upper interlayer insulating film382may be different. For example, the thickness t12of the first upper interlayer insulating film182may be thicker than the thickness t22of the second upper interlayer insulating film382.

As a result, the stress characteristic of the first interlayer insulating film180and the stress characteristic of the second interlayer insulating film380may be equally obtained.

In other words, the ratio of the thickness t12of the first upper interlayer insulating film182to the thickness (t11+t12) of the first interlayer insulating film180, and the ratio of the thickness t22of the second upper interlayer insulating film382to the thickness (t21+t22) of the second interlayer insulating film380may be varied from each other, so that the stress characteristic of the first interlayer insulating film180and the stress characteristic of the second interlayer insulating film380may be equally obtained.

That is, by varying the ratio of the thickness t12of the first upper interlayer insulating film182to the thickness (t11+t12) of the first interlayer insulating film180, and the ratio of the thickness t22of the second upper interlayer insulating film382to the thickness (t21+t22) of the second interlayer insulating film380from each other, it is possible to equalize the sign of the slope of the sidewall130sof the first gate electrode and the sign of the slope of the sidewall330sof the third gate electrode.

FIG.6is a view provided to explain a semiconductor device according to some example embodiments.FIG.7is a view provided to explain a semiconductor device according to some example embodiments. For convenience of explanation, differences that are not explained above with reference toFIGS.1to5Bwill be mainly explained below.

For reference,FIGS.6and7are views illustrating the first gate structure portion and the third gate structure portion ofFIG.2in enlargement.

Referring toFIGS.6and7, in a semiconductor device according to some example embodiments, the thickness t12of the first upper interlayer insulating film182and the thickness t22of the second upper interlayer insulating film382may be substantially equal.

That is, the ratio of the thickness t12of the first upper interlayer insulating film182to the thickness (t11+t12) of the first interlayer insulating film180, and the ratio of the thickness t22of the second upper interlayer insulating film382to the thickness (t21+t22) of the second interlayer insulating film380may be substantially equal.

In this case, the first distance L1between the first gate structure120and the second gate structure220may be lower than the second distance L2between the third gate structure320and the fourth gate structure420.

Accordingly, the volume of the second upper interlayer insulating film382becomes greater than the volume of the first upper interlayer insulating film182.

Because the first upper interlayer insulating film182and the second upper interlayer insulating film382may each have the compressive stress characteristic, the compressive stress of the second upper interlayer insulating film382becomes greater than the compressive stress of the first upper interlayer insulating film182.

First, in a semiconductor device according to some example embodiments, when the sidewall of the gate electrode makes a right angle with respect to the bottom surface of the gate electrode, it is defined herein that the sign of the slope of the gate sidewall is different from a positive sign as well as a negative sign.

As illustrated inFIG.6, the width of the first gate electrode130may increase as the distance from the bottom surface130bof the first gate electrode increases.

Because the sidewall130sof the first gate electrode may make an obtuse angle with respect to the bottom surface130bof the first gate electrode, the sidewall130sof the first gate electrode may have a positive slope.

In contrast, the width of the third gate electrode330may be constant as the distance from the bottom surface330bof the third gate electrode increases. The sidewall330sof the third gate electrode may make a right angle with respect to the bottom surface330bof the third gate electrode.

Accordingly, the sign of the slope of the sidewall130sof the first gate electrode and the sign of the slope of the sidewall330sof the third gate electrode may be different from each other.

As illustrated inFIG.7, the width of the first gate electrode130may be constant as the distance from the bottom surface130bof the first gate electrode increases. The sidewall130sof the first gate electrode may make a right angle with respect to the bottom surface130bof the first gate electrode.

In contrast, the width of the third gate electrode330may decrease as the distance from the bottom surface330bof the third gate electrode increases. Because the sidewall330sof the third gate electrode may make an acute angle with respect to the bottom surface330bof the third gate electrode, the sidewall330sof the third gate electrode may have a negative slope.

Accordingly, the sign of the slope of the sidewall130sof the first gate electrode and the sign of the slope of the sidewall330sof the third gate electrode may be different from each other.

If the first upper interlayer insulating film182and the second upper interlayer insulating film382have tensile stress, the sign of the slope of the sidewall130sof the first gate electrode ofFIG.6may be a negative sign, and the sign of the slope of the sidewall330sof the third gate electrode ofFIG.7may be a positive sign.

FIG.8is a view provided to explain a semiconductor device according to some example embodiments.FIG.9illustrates the first gate structure portion and the third gate structure portion ofFIG.8in enlargement.

For convenience of explanation, differences that are not explained above with reference toFIGS.1to5Bwill be mainly explained below.

Referring toFIGS.8and9, the semiconductor device according to some example embodiments may further include a first liner185and a second liner385.

The first liner185may be formed between the first interlayer insulating film180and the sidewalls120a,120bof the first gate structure, between the first interlayer insulating film180and the sidewall220aof the second gate structure, and between the first interlayer insulating film180and the substrate100.

The first liner185may be formed along the sidewalls120a,120bof the first gate structure, the upper surface of the substrate100, and the sidewall220aof the second gate structure. However, the first liner185is not formed on the upper surface of the first gate structure120and the upper surface of the second gate structure220.

More specifically, the first liner185may extend along a portion of the first sidewall120aof the first gate structure, the upper surface of the substrate100, and a portion of the sidewall220aof the second gate structure, and may extend along a portion of the second sidewall120bof the first gate structure.

The first liner185extending along the upper surface of the substrate100may extend along the upper surface of the first source/drain140and the upper surface of the second source/drain145.

Because the first liner185extends along a portion of the sidewalls120a,120bof the first gate structure, the height of the uppermost portion of the first liner185formed on the sidewalls120a,120bof the first gate structure may be lower than the upper surface of the first gate structure120.

Further, because the first liner185extends along a portion of the sidewall220aof the second gate structure, the height of the uppermost portion of the first liner185formed on the sidewall220aof the second gate structure may be lower than the upper surface of the second gate structure220.

In other words, the height from the upper surface of the substrate100to the uppermost portion of the first liner185formed on the sidewalls120a,120bof the first gate structure may be lower than the height from the upper surface of the substrate100to the upper surface of the first gate structure120.

For example, the first liner185may include one of silicon nitride, silicon oxynitride, silicon oxycarbonitride (SiOCN), silicon oxide, and a combination of silicon nitride, silicon oxynitride, silicon oxycarbonitride (SiOCN), and silicon oxide. Further, the first liner185may be a single film or multiple films.

The first interlayer insulating film180may be formed on the first liner185. The first interlayer insulating film180may surround the sidewalls120a,120bof the first gate structure and the sidewall220aof the second gate structure where the first liner185is formed.

The first lower interlayer insulating film181and the first upper interlayer insulating film182may be deposited in a sequential order on the first liner185.

After dry etching to form the first liner185and the first lower interlayer insulating film181, the first upper interlayer insulating film182may be formed on the first lower interlayer insulating film181. Accordingly, the first liner185may not extend between the first upper interlayer insulating film182and the sidewalls120a,120bof the first gate structure, but not limited thereto.

Additionally, the first upper interlayer insulating film182may cover the upper surface of the first liner185that is formed on the sidewalls120a,120bof the first gate structure and the sidewall220aof the second gate structure.

The thickness t12of the first upper interlayer insulating film182formed on the first lower interlayer insulating film181may correspond to a distance from the upper surface of the first gate structure120to the uppermost portion of the first liner185.

The first contact170may be passed through the first liner185formed on the upper surface of the first source/drain140and connected with the first source/drain140.

The second liner385may be formed between the second interlayer insulating film380and the sidewalls320a,320bof the third gate structure, between the second interlayer insulating film380and the sidewall420aof the fourth gate structure, and between the second interlayer insulating film380and the substrate100.

The second liner385may be formed along the sidewalls320a,320bof the third gate structure, the upper surface of the substrate100, and the sidewall420aof the fourth gate structure. However, the second liner385is not formed on the upper surface of the third gate structure320and the upper surface of the fourth gate structure420.

More specifically, the second liner385may extend along a portion of the first sidewall320aof the third gate structure, the upper surface of the substrate100, and a portion of the sidewall420aof the fourth gate structure, and may extend along a portion of the second sidewall320bof the third gate structure.

The second liner385extending along the upper surface of the substrate100may extend along the upper surface of the third source/drain340and the upper surface of the fourth source/drain345.

Since the second liner385extends along a portion of the sidewalls320a,320bof the third gate structure, the height of the uppermost portion of the second liner385formed on the sidewalls320a,320bof the third gate structure may be lower than the upper surface of the third gate structure320.

Further, because the second liner385extends along a portion of the sidewall420aof the fourth gate structure, the height of the uppermost portion of the second liner385formed on the sidewall420aof the fourth gate structure may be lower than the upper surface of the fourth gate structure420.

In other words, the height from the upper surface of the substrate100to the uppermost portion of the second liner385formed on the sidewalls320a,320bof the third gate structure may be lower than the height from the upper surface of the substrate100to the upper surface of the third gate structure320.

The second interlayer insulating film380may be formed on the second liner385. The second interlayer insulating film380may surround the sidewalls320a,320bof the third gate structure and the sidewall420aof the fourth gate structure where the second liner385is formed.

The second lower interlayer insulating film381and the second upper interlayer insulating film382may be deposited in a sequential order on the second liner385.

After dry etching to form the second liner385and the second lower interlayer insulating film381, the second upper interlayer insulating film382may be formed on the second lower interlayer insulating film381.

The second upper interlayer insulating film382may cover the upper surface of the second liner385that is formed on the sidewalls320a,320bof the third gate structure and the sidewall420aof the fourth gate structure.

The thickness t22of the second upper interlayer insulating film382formed on the second lower interlayer insulating film381may correspond to a distance from the upper surface of the third gate structure320to the uppermost portion of the second liner385.

The second contact370may be passed through the second liner385formed on the upper surface of the third source/drain340and connected with the third source/drain340.

As illustrated inFIG.9, the slope of the sidewall130sof the first gate electrode and the slope of the sidewall330sof the third gate electrode may have the same sign. For example, the sidewall130sof the first gate electrode and the sidewall330sof the third gate electrode may be orthogonal to the upper surface of the substrate100.

The first distance L1between the first gate structure120and the second gate structure220may be lower than the second distance L2between the third gate structure320and the fourth gate structure420.

In order to adjust the magnitude of the compressive stress applied by the first upper interlayer insulating film182to the first gate structure120and the magnitude of the compressive stress applied by the second upper interlayer insulating film382to the third gate structure320, the distance t12from the upper surface of the first gate structure120to the uppermost portion of the first liner185may be greater than the distance t22from the upper surface of the third gate structure320to the uppermost portion of the second liner385.

FIG.10is a view provided to explain a semiconductor device according to some example embodiments.FIG.11is a view provided to explain a semiconductor device according to some example embodiments. For convenience of explanation, differences that are not explained above with reference toFIGS.8and9will be mainly explained below.

For reference,FIGS.10and11are views illustrating the first gate structure portion and the third gate structure portion ofFIG.8in enlargement.

Referring toFIGS.10and11, in a semiconductor device according to some example embodiments, the thickness t12of the first upper interlayer insulating film182and the thickness t22of the second upper interlayer insulating film382may be substantially equal.

The distance t12from the upper surface of the first gate structure120to the uppermost portion of the first liner185and the distance t12from the upper surface of the third gate structure320to the uppermost portion of the second liner385may be substantially equal.

Because the first distance L1between the first gate structure120and the second gate structure220is lower than the second distance L2between the third gate structure320and the fourth gate structure420, the volume of the second upper interlayer insulating film382becomes greater than the volume of the first upper interlayer insulating film182.

Because the compressive stress of the second upper interlayer insulating film382becomes greater than the compressive stress of the first upper interlayer insulating film182, the sign of the slope of the sidewall130sof the first gate electrode and the sign of the slope of the sidewall330sof the third gate electrode may be different from each other.

As illustrated inFIG.10, the sidewall130sof the first gate electrode may make a positive slope and the sidewall330sof the third gate electrode may make a right angle.

As illustrated inFIG.11, the sidewall130sof the first gate electrode may have a slope at a right angle, and the sidewall330sof the third gate electrode may have a negative slope.

FIG.12is a view provided to explain a semiconductor device according to some example embodiments.FIG.13is a view provided to explain a semiconductor device according to some example embodiments.FIG.14is a view provided to explain a semiconductor device according to some example embodiments. For convenience of explanation, differences that are not explained above with reference toFIGS.8and9will be mainly explained below.

Referring toFIG.12, in a semiconductor device according to some example embodiments, the first liner185may be formed along the entirety of the sidewalls120a,120bof the first gate structure and the sidewall220aof the second gate structure.

Further, the second liner385may be formed along the entirety of the sidewalls320a,320bof the third gate structure and the sidewall420aof the fourth gate structure.

In other words, the height from the upper surface of the substrate100to the uppermost portion of the first liner185may be substantially equal to the height from the upper surface of the substrate100to the upper surface of the first gate structure120.

Further, the height from the upper surface of the substrate100to the uppermost portion of the second liner385may be substantially equal to the height from the upper surface of the substrate100to the upper surface of the third gate structure320.

WhileFIG.12illustrates boundary surfaces between the first lower interlayer insulating film181and the first upper interlayer insulating film182, and between the second lower interlayer insulating film381and the second upper interlayer insulating film382as the planes, example embodiments are not limited thereto.

Referring toFIG.13, in a semiconductor device according to some example embodiments, the first interlayer insulating film180formed on the first liner185may be a single film. Further, the second interlayer insulating film380formed on the second liner385may be a single film.

By the statement that the first interlayer insulating film180and the second interlayer insulating film380are ‘single film’, it simply means that each, or at least one, of the first interlayer insulating film180and the second interlayer insulating film380is formed of or include a single material.

Accordingly, while each, or at least one, of the first interlayer insulating film180and the second interlayer insulating film380may be formed of or include a single material, each, or at least one, of the first interlayer insulating film180and the second interlayer insulating film380may include a material of different stress characteristic from the other. This is because, as described above, even the same material can have different stress characteristic under different forming conditions including heat treatment condition, and so on.

Even when the first interlayer insulating film180is a single film, the height from the upper surface of the substrate100to the uppermost portion of the first liner185formed on the sidewalls120a,120bof the first gate structure may be lower than the height from the upper surface of the substrate100to the upper surface of the first gate structure120.

Further, even when the second interlayer insulating film380is a single film, the height from the upper surface of the substrate100to the uppermost portion of the second liner385formed on the sidewalls320a,320bof the third gate structure may be lower than the height from the upper surface of the substrate100to the upper surface of the third gate structure320.

Further, the height from the upper surface of the substrate100to the uppermost portion of the first liner185formed on the sidewalls120a,120bof the first gate structure may be different from the height from the upper surface of the substrate100to the uppermost portion of the second liner385formed on the sidewalls320a,320bof the third gate structure.

Referring toFIG.14, in a semiconductor device according to some example embodiments, the first interlayer insulating film180formed on the first liner185may be a single film. Further, the first liner185may be formed along the entirety of the sidewalls120a,120bof the first gate structure and the sidewall220aof the second gate structure.

The height from the upper surface of the substrate100to the uppermost portion of the first liner185may be substantially equal to the height from the upper surface of the substrate100to the upper surface of the first gate structure120.

For example, the first interlayer insulating film180may include a same material as the second lower interlayer insulating film381and have the same stress characteristic.

In contrast, the second interlayer insulating film380on the second liner385may include the second lower interlayer insulating film381and the second upper interlayer insulating film382.

The height from the upper surface of the substrate100to the uppermost portion of the second liner385formed on the sidewalls320a,320bof the third gate structure may be lower than the height from the upper surface of the substrate100to the upper surface of the third gate structure320.

FIG.15Ais a view provided to explain a semiconductor device according to some example embodiments.FIG.15Bis an enlarged, example view of the squared area P ofFIG.15A. For convenience of explanation, differences that are not explained above with reference toFIGS.1to5Bwill be mainly explained below.

For reference,FIG.15Bmay be a view exemplifying an example in which the gate spacer is a multi-film. That is, when the gate spacer is a single film, it may be in an I-shape as illustrated inFIG.15A.

Referring toFIGS.15A and15B, in a semiconductor device according to some example embodiments, the first contact170may contact the first gate structure120and the second gate structure220.

The first contact170may be aligned by the first sidewall120aof the first gate structure and the sidewall220aof the second gate structure. The first contact170may be connected with the first source/drain140.

However, a contact that contacts the second sidewall120bof the first gate structure and is connected with the second source/drain145may not be formed.

The second contact370may contact the third gate structure320and the fourth gate structure420.

The second contact370may be aligned by the first sidewall320aof the third gate structure and the sidewall420aof the fourth gate structure. The second contact370may be connected with the third source/drain340.

However, a contact that contacts the second sidewall320bof the third gate structure and is connected with the fourth source/drain345may not be formed.

For example, the width of the first contact170and the width of the second contact370may increase as the distance from the upper surface of the substrate100increases.

As illustrated inFIG.15B, the first gate spacer135may be a triple film that includes a first portion135a, a second portion135band a third portion135c, although example embodiments are not limited thereto.

For example, when the first gate spacer135is formed as a triple layer, at least one of the first to third portions135a,135b,135cof the first gate spacer135may have an L-shape.

As illustrated inFIG.15B, the first portion135aof the first gate spacer and the second portion135bof the first gate spacer may each have an L-shape. However, this is provided only for convenience of explanation, and example embodiments are not limited thereto.

That is, it is of course possible that one of the first portion135aof the first gate spacer and the second portion135bof the first gate spacer may have an L-shape.

Further, at least one of the first portion135aof the first gate spacer, the second portion135bof the first gate spacer, or the third portion135cof the first gate spacer may include a low-k material such as silicon oxycarbon nitride (SiOCN) layer.

FIG.16is a view provided to explain a semiconductor device according to some example embodiments. For convenience of explanation, differences that are not explained above with reference toFIG.15Awill be mainly explained below.

Referring toFIG.16, in a semiconductor device according to some example embodiments, the first gate structure120may include a first capping pattern150, and the second gate structure220may include a second capping pattern250.

Further, the third gate structure320may include a third capping pattern350, and the fourth gate structure420may include a fourth capping pattern450.

For example, the first gate electrode130may fill a portion of the first trench135t. The first capping pattern150may be formed on the first gate electrode130. The first capping pattern150may fill rest of the first trench135tleft after the first gate electrode130is formed.

WhileFIG.16illustrates that the first gate insulating film125is not formed between the first gate spacer135and the first capping pattern150, this is provided only for convenience of explanation and example embodiments are not limited thereto.

The upper surface of the first capping pattern150may be the upper surface of the first gate structure120. The upper surface of the first capping pattern150may be in the same plane as the upper surface of the first interlayer insulating film180.

The first capping pattern150may include, for example, a material having etch selectivity with respect to the first interlayer insulating film180.

The first capping pattern150may include at least one of, for example, silicon nitride (SiN), silicon oxynitride (SiON), silicon dioxide (SiO2), silicon carbon nitride (SiCN), silicon oxycarbon nitride (SiOCN), and a combination of silicon nitride (SiN), silicon oxynitride (SiON), silicon dioxide (SiO2), silicon carbon nitride (SiCN) and silicon oxycarbon nitride (SiOCN).

Description about the second capping pattern250, the third capping pattern350, and the fourth capping pattern450will be omitted, as this is similar to or the same as that of the first capping pattern150.

FIG.17is a view provided to explain a semiconductor device according to some example embodiments.FIG.18illustrates the first gate structure portion and the third gate structure portion ofFIG.17in enlargement. For convenience of explanation, differences that are not explained above with reference toFIGS.8and9will be mainly explained below.

Referring toFIGS.17and18, the first contact170may contact the first gate structure120and the second gate structure220.

The first contact170may be aligned by the first sidewall120aof the first gate structure and the sidewall220aof the second gate structure. The first contact170may be connected with the first source/drain140.

However, a contact that contacts the second sidewall120bof the first gate structure and is connected with the second source/drain145may not be formed.

Further, the first liner185may be positioned between the first contact170and the first sidewall120aof the first gate structure.

The first liner185extending along the upper surface of the first source/drain140may be removed during process of forming the first contact170, but the first liner185on a portion of the first sidewall120aof the first gate structure may not be removed but remain.

During process of forming the first contact170, a portion of the first liner185on the first sidewall120aof the first gate structure may be removed.

However, because a contact that contacts the second sidewall120bof the first gate structure is not formed, the first liner185on the portion of the second sidewall120bof the first gate structure may not be removed.

Accordingly, the height h11of the first liner185on the first sidewall120aof the first gate structure may be different from the height h12of the first liner185on the second sidewall120bof the first gate structure.

For example, the height h12of the first liner185on the second sidewall120bof the first gate structure may be greater than the height h11of the first liner185on the first sidewall120aof the first gate structure by a first height h13.

The second contact370may contact the third gate structure320and the fourth gate structure420.

The second contact370may be aligned by the first sidewall320aof the third gate structure and the sidewall420aof the fourth gate structure. The second contact370may be connected with the third source/drain340.

However, a contact that contacts the second sidewall320bof the third gate structure and is connected with the fourth source/drain345may not be formed.

The second liner385may be positioned between the second contact370and the first sidewall320aof the third gate structure.

The second liner385extending along the upper surface of the third source/drain340may be removed during process of forming the second contact370, but the second liner385on a portion of the first sidewall320aof the third gate structure may not be removed but remain.

During process of forming the second contact370, a portion of the second liner385on the first sidewall320aof the third gate structure may be removed.

However, because a contact that contacts the second sidewall320bof the third gate structure is not formed, the second liner385on the portion of the second sidewall320bof the third gate structure may not be removed.

Accordingly, the height h21of the second liner385on the first sidewall320aof the third gate structure may be different from the height h22of the second liner385on the second sidewall320bof the third gate structure.

For example, the height h22of the second liner385on the second sidewall320bof the third gate structure may be greater than the height h21of the second liner385on the first sidewall320aof the third gate structure by a second height h23.

For example, the width of the first contact170and the width of the second contact370may increase as the distance from the upper surface of the substrate100increases.

FIG.19is a view provided to explain a semiconductor device according to some example embodiments.FIG.20is a view provided to explain a semiconductor device according to some example embodiments.FIG.21is a view provided to explain a semiconductor device according to some example embodiments.

For convenience of explanation, differences that are not explained above with reference toFIGS.17and18will be mainly explained below.

For reference,FIGS.19to21are views illustrating the first gate structure portion and the third gate structure portion ofFIG.17in enlargement.

Referring toFIG.19, in a semiconductor device according to some example embodiments, the sidewall130sof the first gate electrode may have a positive slope, and the sidewall330sof the third gate electrode may have a slope at a right angle.

The width of the first gate electrode130may increase as the distance from the upper surface of the first fin-type pattern110increases. Further, the width of the third gate electrode330may be substantially constant as the distance from the upper surface of the second fin-type pattern310increases.

When the sidewall130sof the first gate electrode has a positive slope, the sidewall of the first contact170contacting the first sidewall120aof the first gate structure may have a negative slope.

That is, the width of the first contact170decreases from W11to W12, along a direction from the upper surface of the first source/drain140toward the uppermost portion of the first liner185on the first sidewall120aof the first gate structure. After that, the width of the first contact170may increase along the direction from the uppermost portion of the first liner185toward the upper surface of the first gate structure120.

In other words, the width of the first contact170may decrease and then increase, as the distance from the upper surface of the first fin-type pattern110, i.e., as the distance from the upper surface of the substrate100increases.

In contrast, the width of the second contact370may increase, as the distance from the upper surface of the second fin-type pattern310, i.e., as the distance from the upper surface of the substrate100increases.

Referring toFIG.20, in a semiconductor device according to some example embodiments, the sidewall130sof the first gate electrode may have a slope at a right angle, and the sidewall330sof the third gate electrode may have a negative slope.

The width of the third gate electrode330may decrease as the distance from the upper surface of the second fin-type pattern310increases. Further, the width of the first gate electrode130may be substantially constant as the distance from the upper surface of the first fin-type pattern110increases.

The width of the first contact170may increase as the distance from the upper surface of the first fin-type pattern110, i.e., as the distance from the upper surface of the substrate100increases. The width of the second contact370may increase as the distance from the upper surface of the second fin-type pattern310, i.e., as the distance from the upper surface of the substrate100increases.

Referring toFIG.21, in a semiconductor device according to some example embodiments, the first interlayer insulating film180surrounding the second sidewall120bof the first gate structure, and the second interlayer insulating film380surrounding the second sidewall320bof the third gate structure may be single films.

While the first interlayer insulating film180and the second interlayer insulating film380may each be formed of or include a single material, each may include a material of different stress characteristic from the other.

FIG.22is layout diagrams provided to explain a semiconductor device according to some example embodiments.FIG.23is cross sectional views taken on lines A-A, B-B, and E-E ofFIG.22.

For convenience of explanation, differences that are not explained above with reference toFIGS.1to5Bwill be mainly explained below.

Referring toFIGS.22and23, a semiconductor device according to some example embodiments may additionally include a third fin-type pattern510, a fifth gate structure520, a sixth gate structure620, and a third contact570.

The substrate100may include a first region I, a second region II, and a third region III. The third region III, and the first region I and/or the second region II may be the regions that are spaced apart from one another, or connected with one another.

In the third region III, the third fin-type pattern510, the fifth gate structure520, the sixth gate structure620, and the third contact570may be formed.

The third fin-type pattern510may extend longitudinally on the substrate100in a fifth direction X3. The third fin-type pattern510may protrude from the substrate100.

The fifth gate structure520may extend in a sixth direction Y3. The fifth gate structure520may be formed to intersect the third fin-type pattern510.

The sixth gate structure620may extend in the sixth direction Y3. The sixth gate structure620may be formed to intersect the third fin-type pattern510. The sixth gate structure620may be spaced apart from the fifth gate structure520by a third distance L3.

The distance L3of spacing between the fifth gate structure520and the sixth gate structure620may be greater than the distance L1of spacing between the first gate structure120and the second gate structure220, and the distance L2of spacing between the third gate structure320and the fourth gate structure420.

Further, the fifth gate structure520may include a fifth gate electrode, a fifth gate insulating film, and a fifth gate spacer, and the sixth gate structure620may include a sixth gate electrode, a sixth gate insulating film, and a sixth gate spacer.

Description of the structures of the fifth gate structure520and the sixth gate structure620may be substantially identical to that of the first gate structure120, and therefore, will not be redundantly described below.

The fifth source/drain540may be formed between the fifth gate structure520and the sixth gate structure620. As illustrated, the fifth source/drain540may include an epitaxial layer formed within the third fin-type pattern510, although example embodiments are not limited thereto.

Depending on whether the semiconductor device formed in the third region III is a PMOS or an NMOS, the fifth source/drain540may include a tensile stress material, or a compressive stress material, or a material same as the third fin-type pattern510.

The fourth interlayer insulating film580may be formed on the substrate100of the third region III. The fourth interlayer insulating film580may cover the third fin-type pattern510, and the fifth source/drain540.

The upper surface of the fourth interlayer insulating film580may be in the same plane as, for example, the upper surface of the fifth gate structure520and the upper surface of the sixth gate structure620.

Description of the fourth interlayer insulating film580may be substantially identical to that of the first interlayer insulating film180, and will not be redundantly described below.

The third contact570may be formed between the fifth gate structure520and the sixth gate structure620.

The third contact570may be formed within the third interlayer insulating film190and the fourth interlayer insulating film580. The third contact570may not contact the fifth gate structure520and the sixth gate structure620. The third contact570may be connected with the fifth source/drain540.

The third contact570may have a third width W3. For example, the third width W3of the third contact570may be based on the upper surface of the fifth gate structure520and the upper surface of the sixth gate structure620, but this is provided only for convenience of explanation and example embodiments are not limited thereto. That is, the third width W3of the third contact570may be based on the upper surface of the third interlayer insulating film590.

Further, the third width W3of the third contact570may be a width in the fifth direction X3.

As illustrated inFIG.23, the third width W3of the third contact570may be greater than the first width W1of the first contact170and the second width W2of the second contact370.

That is, the width of the contacts formed between the gate structures may increase as the distance between the gate structures increases.

FIG.24is a view provided to explain a semiconductor device according to some example embodiments. For convenience of explanation, differences that are not explained above with reference toFIGS.22and23will be mainly explained below.

Referring toFIG.24, in a semiconductor device according to some example embodiments, the third width W3of the third contact570may be greater than the first width W1of the first contact170, but substantially equal to the second width W2of the second contact370.

The distance L3of spacing between the fifth gate structure520and the sixth gate structure620may be greater than the distance L2of spacing between the third gate structure320and the fourth gate structure420, but the third width W3of the third contact570may be substantially equal to the second width W2of the second contact370.

FIG.25is a view provided to explain a semiconductor device according to some example embodiments. For convenience of explanation, differences that are not explained above with reference toFIG.24will be mainly explained below.

Referring toFIG.25, in a semiconductor device according to some example embodiments, the first contact170may contact the first gate structure120and the second gate structure220, and the second contact370may contact the third gate structure320and the fourth gate structure420.

However, while the distance L3of spacing between the fifth gate structure520and the sixth gate structure620may be greater than the distance L2of spacing between the third gate structure320and the fourth gate structure420, because the third width W3of the third contact570is substantially equal to the second width W2of the second contact370, the third contact570does not contact at least one of the fifth gate structure520and the sixth gate structure620.

FIG.26is a layout diagram provided to explain a semiconductor device according to some example embodiments.FIG.27is a cross sectional view taken on line D-D ofFIG.26.

For convenience of explanation, differences that are not explained above with reference toFIGS.1to5Bwill be mainly explained below.

Referring toFIGS.26and27, a semiconductor device according to some example embodiments may additionally include a fourth fin-type pattern210formed in the first region I.

The fourth fin-type pattern210may extend in the first direction X and abreast of the first fin-type pattern110.

The first gate structure120and the second gate structure220may each intersect the first fin-type pattern110and the fourth fin-type pattern210.

The first source/drain140may be formed on the first fin-type pattern110. The sixth source/drain240may be formed on the fourth fin-type pattern210.

The first source/drain140and the sixth source/drain240formed on the first fin-type pattern110and the adjacent fourth fin-type pattern210may contact each other.

The first contact170may be connected with the first source/drain140and the sixth source/drain240that contact each other.

The first contact170may include, for example, a shared contact.

FIG.28is a block diagram of a SoC system comprising a semiconductor device according to example embodiments.

Referring toFIG.28, a SoC system1000includes an application processor1001and a dynamic random-access memory (DRAM)1060.

The application processor1001may include a central processing unit (CPU)1010, a multimedia system1020, a bus1030, a memory system1040and a peripheral circuit1050.

The CPU1010may perform arithmetic operation necessary for driving of the SoC system1000. In some example embodiments, the CPU1010may be configured on a multi-core environment which includes a plurality of cores.

The multimedia system1020may be used for performing a variety of multimedia functions on the SoC system1000. Such multimedia system1020may include a three-dimensional (3D) engine module, a video codec, a display system, a camera system, a post-processor, and so on.

The bus1030may be used for exchanging data communication among the CPU1010, the multimedia system1020, the memory system1040and the peripheral circuit1050. In some example embodiments, the bus1030may have a multi-layer structure. Specifically, an example of the bus1030may be a multi-layer advanced high-performance bus (AHB), or a multi-layer advanced eXtensible interface (AXI), although example embodiments are not limited herein.

The memory system1040may provide environments necessary for the application processor1001to connect to an external memory (e.g., DRAM1060) and perform high-speed operation. In some example embodiments, the memory system1040may include a separate controller (e.g., DRAM controller) to control an external memory (e.g., DRAM1060).

The peripheral circuit1050may provide environments necessary for the SoC system1000to have a seamless connection to an external device (e.g., main board). Accordingly, the peripheral circuit1050may include a variety of interfaces to allow compatible operation with the external device connected to the SoC system1000.

The DRAM1060may function as an operation memory necessary for the operation of the application processor1001. In some example embodiments, the DRAM1060may be arranged externally to the application processor1001, as illustrated. Specifically, the DRAM1060may be packaged into a package on package (PoP) type with the application processor1001.

At least one of the above-mentioned components of the SoC system1000may include at least one of the semiconductor devices according to the example embodiments explained above.

In concluding the detailed description, those skilled in the art will appreciate that many variations and modifications can be made to the example embodiments without substantially departing from the principles of the inventive concepts. Therefore, the disclosed example embodiments are used in a generic and descriptive sense only and not for purposes of limitation.