Patent ID: 12199149

Other features of the present embodiments will be apparent from the accompanying drawings and from the detailed description that follows.

DETAILED DESCRIPTION

Definitions and General Techniques

Unless otherwise defined herein, scientific and technical terms used herein shall have the meanings that are commonly understood by those of ordinary skill in the art. Further, unless otherwise required by context, singular terms shall include pluralities and plural terms shall include the singular. Generally, nomenclatures used in connection with, and techniques of, semiconductor processing described herein are those well-known and commonly used in the art.

The methods and techniques described herein are generally performed according to conventional methods well known in the art and as described in various general and more specific references that are cited and discussed throughout the present specification unless otherwise indicated. The nomenclatures used in connection with, and the procedures and techniques of semiconductor device technology, semiconductor processing, and other related fields described herein are those well-known and commonly used in the art.

For simplicity and clarity of illustration, the drawing figures illustrate the general manner of construction, and descriptions and details of well-known features and techniques may be omitted to avoid unnecessarily obscuring the present disclosure. Additionally, elements in the drawing figures are not necessarily drawn to scale. For example, the dimensions of some of the elements in the figures may be exaggerated relative to other elements to help improve understanding of embodiments of the present disclosure. The same reference numerals in different figures denotes the same elements.

The terms “first,” “second,” “third,” “fourth,” and the like in the description and in the claims, if any, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments described herein are, for example, capable of operation in sequences other than those illustrated or otherwise described herein. Furthermore, the terms “include,” and “have,” and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, device, or apparatus that comprises a list of elements is not necessarily limited to those elements, but may include other elements not expressly listed or inherent to such process, method, system, article, device, or apparatus.

The terms “left,” “right,” “front,” “back,” “top,” “bottom,” “over,” “under,” and the like in the description and in the claims, if any, are used for descriptive purposes and not necessarily for describing permanent relative positions. It is to be understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments of the apparatus, methods, and/or articles of manufacture described herein are, for example, capable of operation in other orientations than those illustrated or otherwise described herein.

The following terms and phrases, unless otherwise indicated, shall be understood to have the following meanings.

The term “unit cell” as used herein refers to a piece of a pattern in a semiconductor which is repeated in the semiconductor.

The term “SiC” as used herein refers to silicon carbide which is a compound semiconductor and is a mixture of silicon and carbon with the chemical formula SiC. Silicon is covalently bonded with carbon. In 4H—SiC, 4H is written in the Ramsdell classification scheme where the number indicates the layer and the letter indicates the Bravais lattice. That means in a 4H—SiC structure four hexagonal layers of SiC are present. SiC exists in a kind of polymorphic crystalline building known as a polytype, e.g. 3C—SiC, 4H—SiC, 6H—SiC. Presently 4H—SiC is used in power device manufacturing.

The term “substrate” as used herein refers to the supporting material on or in which the components of an integrated circuit are fabricated or attached.

The term “JFET” as used herein refers to junction gate field-effect transistor which is a three-terminal semiconductor device that can be used as electronically-controlled switches, amplifiers, or voltage-controlled resistors. A FET (field-effect transistor) is a unipolar transistor in which current carriers are injected at a source terminal and pass to a drain terminal through a channel of semiconductor material whose conductivity depends largely on an electric field applied to the semiconductor from a control electrode. There are two main types of FETs, a junction FET and an insulated-gate FET. In the junction FET, the gate is isolated from the channel by a p-n junction. In an insulated-gate FET, the gate is isolated from the channel by an insulating layer so that the gate and channel form a capacitor with the insulating layer as the capacitor dielectric.

The term “MOSFET” as used herein refers to metal oxide semiconductor field-effect transistor. which is a four-terminal device with source (S), gate (G), drain (D) and body (B) terminals. The body of the MOSFET is frequently connected to the source terminal so making it a three-terminal device like field effect transistor.

The term “DMOSFET” as used herein refers to double-implantation metal oxide semiconductor field-effect transistor. A common physical structure of SiC MOSFETs is the planar double-implanted MOSFET in 4H—SiC (SiC-DMOSFET).

The term “dopant” as used herein refers to an impurity added from an external source to a material by diffusion, coating, or implanting into a substrate, and changing the properties thereof. In semiconductor technology, an impurity may be added to a semiconductor to modify its electrical properties or to a material to produce a semiconductor having desired electrical properties. N-type (negative) dopants (e.g., such as phosphorus for a group IV semiconductor) typically come from group V of the periodic table. When added to a semiconductor, n-type dopants create a material that contains conduction electrons. P-type (positive) dopants (e.g., such as boron for a group IV semiconductor) typically come from group III and result in conduction holes (i.e., vacancies in the electron shells).

The term “drain” as used herein refers to the electrode of a field effect transistor which receives charge carriers which pass through the transistor channel from the source electrode.

The term “source” as used herein refers to the active region/electrode to which the source of charge carriers is connected in a field effect transistor.

The term “gate” as used herein refers to the control electrode or control region that exerts an effect on a semiconductor region directly associated therewith, such that the conductivity characteristic of the semiconductor region is altered in a temporary manner, often resulting in an on-off type switching action. The control electrode or control region of a field effect transistor is located between the source and drain electrodes, and regions thereof.

The term “topside” as used herein refers to outer side/top of the DMOSFET. The topside of the vertical SiC DMOSFET may comprise a source terminal.

The term “bottom side” as used herein refers to underside/base of the DMOSFET. The bottom side of the vertical SiC DMOSFET may comprise a drain terminal.

The term “front side” as used herein refers to a side of the DMOSFET which is visible in front.

The term “back side” as used herein refers to rear side of the DMOSFET. The back side of the vertical SiC DMOSFET may comprise the drain terminal.

The term “impurity” as used herein refers to a foreign material present in a semiconductor crystal, such as boron or arsenic in silicon, which is added to the semiconductor to produce either p-type or n-type semiconductor material, or to otherwise result in material whose electrical characteristics depend on the impurity dopant atoms.

The term “PN junction” as used herein refers to the interface and region of transition between p-type and n-type semiconductors.

The term “polysilicon” as used herein refers to a polycrystalline form of silicon.

The term “p-type” as used herein refers to extrinsic semiconductor in which the hole density exceeds the conduction electron density.

The term “bandgap” as used herein refers to the difference between the energy levels of electrons bound to their nuclei (valence electrons) and the energy levels that allow electrons to migrate freely (conduction electrons). The band gap depends on the particular semiconductor involved.

The term “channel” as used herein refers to a path for conducting current between a source and drain of a field effect transistor.

The term “chip” as used herein refers to a single crystal substrate of semiconductor material on which one or more active or passive solid-state electronic devices are formed. A chip may contain an integrated circuit. A chip is not normally ready for use until packaged and provided with external connectors.

The term “contact” as used herein refers to the point or part of a conductor which touches another electrical conductor or electrical component to carry electrical current to or from the conductor or electrical component.

The term “drift layer” as used herein refers to lightly doped region to support the high voltage in power DMOSFET.

The term “well” used herein refers certain regions in a metal-oxide-semiconductor (MOS) transistor. MOS transistors are always created in a “well” region. A PMOS (positive-channel MOS) transistor is made in an N-doped region, called “n-well” region. Similarly, an NMOS transistor (negative-channel MOS) is made in a “p-type” region called “p-well”. This ensures that the leakage between two transistors, through the bottom side, is low due to the reverse bias between the transistor areas and the well region.

The term “plus” used herein refers certain regions in a metal-oxide-semiconductor (MOS) transistor where doping concentration is excessive.

The term “source interconnect metallization” as used herein refers to interconnection metallization that interconnects many DMOSFETs using fine-line metal patterns.

The term “device” as used herein refers to the physical realization of an individual electrical element in a physically independent body which cannot be further divided without destroying its stated function.

The term “surface” as used herein refers to the outer or exterior boundary of a thing.

The term “trench” as used herein refers to electrical isolation of electronic components in a monolithic integrated circuit by the use of grooves or other indentations in the surface of the substrate, which may or may not be filled with electrically insulative (i.e., dielectric) material.

The term “dielectric” as used herein refers to a non-conductor of electricity, otherwise known as an insulator.

The term “ILD” as used herein refers to interlayer dielectric material used to electrically separate closely spaced interconnect lines arranged in several levels (multilevel metallization) in an advanced integrated circuit.

The term “active region” as used herein refers to a region of the DMOSFET where the current conduction happens.

The term “depletion region” as used herein refers to a region where flow of charged carriers decreases over a given time.

The term “thermal budget” as used herein refers to total amount of thermal energy transferred to a wafer during the given elevated temperature operation.

The term “work function” as used herein refers to minimum quantity of energy required to remove an electron to infinity from the surface of a given metal.

The terms “first conductivity type region” and “second conductivity type region” as used herein, are used to describe n-type and p-type regions respectively for a N type device. For a P type device “first conductivity type region” and “second conductivity type region” are used to describe p-type and n-type regions respectively

Embodiments relate to silicon carbide (SiC) DMOSFET power devices having increased third quadrant cross over current.

An embodiment relates to tuning turn-on voltage of one or more body diode regions of the DMOSFET.

An embodiment relates to reducing injection of minority carriers during conduction of the one or more body diode regions.

An embodiment relates to tuning source contact resistance of the one or more body diode regions of the DMOSFET.

An embodiment relates to improved device reliability.

An embodiment relates to reducing differential ON resistance for a given chip size.

An embodiment relates to mitigate basal plane dislocation (BPD).

An embodiment relates to formation of a first conductivity type second source region between a silicide layer and a second conductivity type well region of the DMOSFET.

An embodiment relates to formation of a first metal region in direct contact with a second conductivity type well contact region.

An embodiment relates to connecting one or more Schottky diode regions in series with the one or more body diode regions of the DMOSFET.

An embodiment relates to formation of the second conductivity type well contact region that meanders and comprise a periodic spacing between the first conductivity type source region and the second conductivity type well contact region.

An embodiment relates to formation of the second conductivity type well contact region that meanders and enables the second conductivity type well region to be contact in with a source metal only through the second conductivity type well contact region.

An embodiment relates to a power DMOSFET device structure designed to handle significant power level includes an intrinsic anti-parallel p-n junction diode, formed between the body and well regions, respectively. The anti-parallel p-n junction diode within the power DMOSFET structure conducts during third quadrant operation of the power DMOSFET. The third quadrant operation occurs when source terminal is biased positively with respect to drain terminal, a situation that is commonly encountered when power MOSFETs are utilized in motor control related power conversion applications. To circumvent performance and reliability issues related to slower switching speed of the p-n diode and conversion of the basal plane dislocations into stacking faults, respectively, a Schottky diode is either externally or internally connected in an anti-parallel with the intrinsic p-n body diode of the DMOSFET. In this scenario, there exists a specific cross-over current, above which the current still flows mainly through the p-n diode, despite the connection of the Schottky diode.

An embodiment relates to a Silicon Carbide (SiC) double-implantation metal oxide semiconductor field effect transistor (DMOSFET) with increased cross over current. The magnitude of the cross over current of the DMOSFET is increased by at least one of increasing built-in potential (e.g. turn-on voltage) of the one or more body diode regions of the DMOSFET and reducing injection of minority carriers during conduction of the one or more body diode regions. In an embodiment, the SiC DMOSFET is a n-type planar gate DMOSFET. In another embodiment, the SiC DMOSFET is a p-type planar gate DMOSFET. In yet another embodiment, the SiC DMOSFET is a n-type trench gate DMOSFET. In yet another embodiment, the SiC DMOSFET is a p-type trench gate DMOSFET. The magnitude of the cross over current is increased by performing below embodiments. The below embodiments are described specifically with respect to the n-type planar gate DMOSFET.

In one embodiment, each unit cell of the DMOSFET comprises a second N+ source region between a silicide layer and a p-well region to impact the turn-on voltage of the one or more body diode regions of the DMOSFET.

In another embodiment, each unit cell of the DMOSFET comprises a first metal region in direct contact with a P+ region to connect one or more Schottky diode regions in series with the one or more body diode regions of the DMOSFET to impact the turn-on voltage of the one or more body diode regions of the DMOSFET.

In yet another embodiment, each unit cell of the DMOSFET comprises the P+ region that meanders and comprises a periodic spacing between a N+ source region and the P+ region to form periodic contacts to a first pad metal (e.g. a source metal) via the silicide layer between interlayer dielectric bumps (ILD) to impact the differential on-resistance of the one or more body diode regions of the DMOSFET.

In yet another embodiment, each unit cell of the DMOSFET comprises the P+ region that meanders and enables the P-well region to be in contact with the silicide layer (i.e. the first pad metal) only through the meandering P+ region to impact the differential on-resistance of the one or more body diode regions of the DMOSFET.

FIG.1aillustrates an embodiment of a cross sectional structure of a unit cell of a double-implantation metal oxide semiconductor field-effect transistor (DMOSFET) comprising a first conductivity type second source region within a first conductivity type first source region. The DMOSFET (shown inFIG.1a) is a n-type planar gate DMOSFET. In an embodiment, the DMOSFET is a p-type planar gate DMOSFET. The DMOSFET (shown inFIG.1a) comprises a silicon carbide (SiC) substrate. The SiC substrate comprises a N+ substrate102and a N− drift layer104. The DMOSFET also comprises a P-well region106, a first N+ source region108(i.e. the first conductivity type first source region) and a second N+ source region110(i.e. the first conductivity type second source region). The first N+ source region108is formed within the P-well region106. The second N+ source region110is formed within each first N+ source region108by etching the SiC substrate to remove a portion of the SiC substrate and form a recessed SiC trench112. In an embodiment, the second N+ source region110is a depletion region when the DMOSFET is operated in the third quadrant. The recessed SiC trench112leaves the remnant thin first N+ source region108as the second N+ source region110. The second N+ source region110comprises a thickness less than a thickness of the first N+ source region108which enables the second N+ source region110to get depleted easily compared to the first N+ source region108. The second N+ source region110may comprise the thickness ranging from 1% to 90% lower than the thickness of the first N+ source region108. In an embodiment, the second N+ source region110comprises a doping concentration less than a doping concentration of the first N+ source region108. The second N+ source region110may comprise the doping concentration ranging from 1% to 90% lower than the doping concentration of the first N+ source region108.

The DMOSFET also comprises a gate insulator114, a polysilicon layer116and an interlayer dielectric (ILD)118on both sides of top surface of the SiC substrate. The DMOSFET further comprises a first silicide layer120on top of the recessed SiC trench112and a second silicide layer122on bottom side/back side of the SiC substrate to form ohmic contacts for a source terminal and a drain terminal respectively. The DMOSFET further comprises a first pad metal124(e.g. a source metal) and a second pad metal126(e.g. a drain metal) on top of the first silicide layer120and bottom of the second silicide layer122respectively.

During third quadrant operation of the n-type planar gate DMOSFET (i.e. when the source terminal is positively biased with respect to the drain terminal), an intrinsic p-n junction between the second N+ source region110and the p-well region106is reverse biased as electric potential of the first pad metal124is low when compared to electric potential of the second pad metal126. The second N+ source region110starts depleting during the third quadrant operation. The first pad metal124(e.g. the source metal) is directly short circuited (e.g. connected) with the P-well region106, when the second N+ source region110is completely depleted. The second N+ source region110enables one or more body diode regions of the DMOSFET to have an increased turn-on voltage and the one or more body diode regions turn on only when the second N+ source region110is completely depleted. The increased turn-on voltage is due to intrinsic bandgap of the SiC. As the complete depletion of the second N+ source region110depends on at least one of the thickness and the doping concentration of the second N+ source region110, the turn-on voltage of the second N+ source region110also depends on the thickness and the doping concentration of the second N+ source region110. The turn-on voltage of the one or more body diode regions is tuned by controlling/adjusting the thickness and the doping concentration of the second N+ source region110to a target thickness and a target doping concentration respectively. In an embodiment, the target thickness ranges from 1 nm to 1 μm. In another embodiment, the target doping concentration ranges from 1015cm−3to 1021cm−3. The target thickness and the target doping concentration of the second N+ source region110is achieved by monitoring and controlling precisely the etching performed onto the SiC substrate.

FIG.1billustrates an embodiment of a cross sectional structure of one or more unit cells of the DMOSFET, comprising one or more unit cells of an integrated Schottky diode, each DMOSFET unit cell comprising the first conductivity type second source region within the first conductivity type first source region. The DMOSFET (shown inFIG.1b) is a n-type planar gate SiC DMOSFET. The DMOSFET shown inFIG.1boperates in a similar way toFIG.1a. In addition toFIG.1a, the DMOSFET (shown inFIG.1b) comprises a metal region128(e.g. a Schottky metal region128) in direct contact with the N− drift layer104and bridges adjacent P-well regions106(i.e. bridges the adjacent unit cells) of the one or more P-well regions106. The DMOSFET comprises each second N+ source region110between the respective silicide SiC trench112and the respective P-well region106.

FIG.1cillustrates an embodiment of a cross sectional structure of one or more unit cells of a trench gate MOSFET, comprising one or more unit cells of the integrated Schottky diode, each MOSFET unit cell comprising the first conductivity type second source region within the first conductivity type first source region. The trench gate MOSFET shown inFIG.1cis a n-type trench gate SiC MOSFET. In an embodiment, the trench gate MOSFET is a p-type trench gate SiC MOSFET. The trench gate MOSFET shown inFIG.1coperates in a similar way to planar gate DMOSFET shown inFIG.1aandFIG.1b. The main difference between the trench gate MOSFET and the planar gate DMOSFET is that the trench gate MOSFET comprises one or more trench gate structures instead of one or more planar gate structures. The one or more trench gate structures of the trench gate MOSFET comprises sidewalls that are exposing to the first N+ source region108and the one or more P-well regions106. The bottom of the one or more trench gate structures is in vicinity of the bottom of the one or more P-well regions106. In an embodiment, the bottom of the one or more trench gate structures is adjusted appropriately depending on electrical properties of the MOSFET device. Each trench gate structure of the trench gate MOSFET comprises the gate insulator114as liner along the sidewall and the bottom of the respective trench gate structure. Each trench gate structure comprises the polysilicon layer116that fills the gate-insulator lined trenches and serves as gate electrode. The trench gate MOSFET further comprises the interlayer dielectric (ILD)118over each polysilicon layer116to open short circuitry between the first pad metal124(e.g. the source metal) and the gate electrode.

FIG.2a-2tillustrate an embodiment of a process of manufacturing the DMOSFET structure shown inFIG.1a. The process of manufacturing the DMOSFET structure (shown inFIG.1a) comprises preparing a Silicon Carbide (SiC) substrate having a N+ substrate202and a N− drift layer204as shown inFIG.2a. The N− drift layer204of the SiC substrate is epi-grown and prepared such that a doping concentration and a thickness of the N− drift layer204are selected primarily based on blocking voltage and forward conduction loss. The N+ substrate202is highly conductive when compared to the N− drift layer204and the N+ substrate202is in direct contact with the N-drift layer204. A first patterned hard mask layer205is formed on top of the SiC substrate as shown inFIG.2b. The first patterned hard mask layer205is thick enough for completely blocking high energy impurities during implantation. In an embodiment, the first patterned hard mask layer205is a hard mask of at least one of oxide, nitride and a polysilicon.

A first p-type ion implantation is formed inFIG.2cthrough the first patterned hard mask layer205to form a p-well region206. In an embodiment, the first p-type ion implantation is performed with one or more p-type impurities (e.g. aluminum, boron, etc.). In another embodiment, first p-type ion implantation may comprise a screen oxide layer. The first patterned hard mask layer205is then removed, after the first p-type ion implantation, by at least one of dry etching and wet etching process as shown inFIG.2d. A second patterned hard mask layer207is then formed on the top of the SiC substrate as shown inFIG.2efor subsequent ion implantation. The second patterned hard mask layer207is a photoresist based material and thick enough for preventing any unwanted high energy impurity particles penetrating the second patterned hard mask layer207. A first n-type ion implantation is performed through the second patterned hard mask layer207to form a first N+ source region208within the p-well region206as shown inFIG.2f. In an embodiment, the first n-type ion implantation is performed with one or more n-type impurities (e.g. nitrogen, phosphorous etc.). The second patterned hard mask layer207is then removed after the first n-type ion implantation by at least one of dry etching and wet etching process as shown inFIG.2g.

A third patterned hard mask layer209is formed on top of the SiC substrate as shown inFIG.2h. An etching is performed onto the SiC substrate through the third patterned hard mask layer209. The SiC etching performed consumes a central portion of each first N+ source region208and forms a recessed SiC trench region212per each first N+ source region208. The recessed SiC trench region212does not fully penetrates the first N+ source region208in vertical direction and leaves a remnant of the first N+ source region208to form a second N+ source region210under the bottom of the recessed SiC trench region212as shown inFIG.2i. The SiC etching is controlled accurately and precisely considering plausible loss of the Sic Substrate, during at least one of thermal activation annealing, sacrificial oxidation and dry oxidation for one of a gate oxide formation and a silicide layer formation for ohmic contacts, when target SiC trench depth is reached. The target SiC trench depth leaves at least one of a target thickness and a target doping concentration of the second N+ source region210under the bottom of the recessed SiC trench region212. In an embodiment, the target thickness ranges from 1 nm to 1 μm. In another embodiment, the target doping concentration ranges from 1015cm−3to 1021cm−3.

The third patterned hard mask layer209is then removed as shown inFIG.2jby at least one of a dry etching and a wet etching process once the target SiC trench depth is reached. The SiC substrate undergoes thermal activation annealing with a carbon-based protection coating at a predefined temperature. In an embodiment, the predefined temperature is 1700-degree Celsius. The SiC substrate then may undergo an additional ion implantation for forming a current spreading layer to improve on-state resistance. Ion implantations (e.g. the first p-type implantation, the first n-type impanation, the second p-type implantation, edge termination implantation, current spreading layer implantation etc.) undergone by the SiC substrate is performed prior to the thermal activation annealing step. The carbon-based protection coating is then removed from the SiC substrate once the thermal activation annealing is completed. The SiC substrate then undergoes a sacrificial oxide growth and subsequently the sacrificial oxide removal. An active region of the DMOSFET is then patterned by forming and patterning field oxide layer on the SiC substrate.

A gate insulator214is then deposited/formed on top of the SiC substrate as shown inFIG.2k. The gate insulator214is then patterned as shown inFIG.2l. A polysilicon layer216is then formed on top of the SiC substrate as shown inFIG.2m. The polysilicon layer216is then patterned as shown inFIG.2n. The contacts for the polysilicon layer are kept open before pad metal deposition for forming a gate pad region and the gate bus region(s). An interlayer dielectric (ILD)218is then formed on top of the SiC substrate as shown inFIG.2o. The interlayer dielectric (ILD)218is then patterned for exposing the portions of the SiC substrate via the openings of the ILD218as shown inFIG.2p. A first silicide layer220is then formed on the exposed portions on top of the SiC substrate for forming a first Ohmic contact (e.g. a source terminal contact) as shown inFIG.2q. In an embodiment, the first silicide layer220is a nickel-based silicide layer. In another embodiment, the nickel-based silicide is formed by Nickel deposition on the top of the SiC substrate, thermal activation annealing of the deposited Nickel for silicide formation, and removal of any un-reacted Nickel from the SiC substrate. A first pad metal224is then formed on top of the first silicide layer220of the SiC substrate as shown inFIG.2r.

A second silicide layer222is then formed on bottom of the SiC substrate for forming a second Ohmic contact as shown inFIG.2s. In an embodiment, the second silicide layer222is then formed on back of the SiC substrate for forming the second Ohmic contact (e.g. a drain terminal contact). In an embodiment, the second silicide layer222is also the nickel-based silicide layer. A second pad metal226is then formed on bottom of the second silicide layer222of the SiC substrate as shown inFIG.2t. In an embodiment, the second pad metal formation is performed by at least one of e-beam and sputtering.

A fourth patterned hard mask layer211is then formed on the SiC substrate once the first Ohmic contact and the second Ohmic contact are formed on topside and bottom side/back side of the SiC substrate respectively. The fourth patterned hard mask layer211is formed for selectively removing the exposed portions of the ILD layer218and forming a metal region (i.e. a Schottky metal region228) shown inFIG.1b. The fourth patterned hard mask layer211is used for both etching the portion of the ILD layer218and lifting off the Schottky metal region228when Schottky metal is deposited. The Schottky metal region228is in direct contact with the N− drift layer204and bridge two adjacent P-well regions206(i.e. bridges the adjacent unit cells). The Schottky metal region228is then annealed with a predefined thermal budget for forming a Schottky metal contact between the Schottky metal region228and the portion of the N− drift layer204exposed at the top surface of the SiC substrate. In an embodiment, the predefined thermal budget ranges from 55° C. to 1100° C. InFIG.1bthe first pad metal and the second pad metal formation are performed once the Schottky metal region228formation is completed.

FIG.3aillustrates an embodiment of a voltage-current characteristic of a SiC DMOSFET with conventional p-n junction vs the SiC DMOSFET with deactivated p-n junction (i.e. the first conductivity type second source region). The voltage-current characteristic shown inFIG.3adepicts that at a drain current −16A, the SiC planar DMOSFET with conventional p-n junction shows a voltage drop of ≈−4 v and the SiC DMOSFET with deactivated p-n junction (i.e. the first conductivity type second source region) shows a voltage drop of ˜−7V. The SiC DMOSFET comprise the p-n junction with increased built-in potential and increased differential on-resistance when the SiC DMOSFET comprises the first conductivity type second source region110.

FIG.3bis a perspective view that illustrates an embodiment of sides of the DMOSFET in relation to a dice. The DMOSFET may comprise a structure similar to the dice as shown inFIG.3b. The DMOSFET comprises at least the topside340, the bottom side342, a front side344, the back side346, a left side348and a right side350. The topside340of the DMOSFET refers to an outer side/top of the DMOSFET. The topside340comprises the source terminal. The bottom side342refers to a base of the DMOSFET. In an embodiment, the bottom side342of the DMOSFET comprises the drain terminal. The back side346of the DMOSFET is hidden in theFIG.3band is located in adjacent to the topside340and the bottom side342. In another embodiment, the back side346of the DMOSFET comprises the drain terminal. The front side344and the right side350of the DMOSFET is visible in theFIG.3b, whereas the left side348and the back side346of the DMOSFET is hidden in theFIG.3b.

FIG.3c-3dshows the operation of the anti-parallel diode in a half-bridge inverter feeding an inductive load. The left picture (i.e.FIG.3c) shows the state when the upper switch feeds the inductor. However, when that switch turns off, inductor's current continues its path through the anti-parallel diode of the bottom switch (right picture i.e.FIG.3d).” [source: Re: Why are diodes connected anti-parallel across the MOSFET or IGBT in Inverter Module? Heydari, Gholamali, published on Research gate, Jul. 25, 2013].

FIG.4aillustrates an embodiment of a cross sectional structure of a unit cell of a double-implantation metal oxide semiconductor field-effect transistor (DMOSFET) comprising a first conductivity type second source region within a first conductivity type first source region. The DMOSFET (shown inFIG.4a) is a n-type planar gate DMOSFET. In an embodiment, the DMOSFET is a p-type planar gate DMOSFET. In another embodiment, the DMOSFET is one of a n-type trench gate DMOSFET and a p-type trench gate DMOSFET. The DMOSFET (shown inFIG.4a) comprises a Silicon Carbide (SiC) substrate. The SiC substrate comprises a N+ substrate402and a N− drift layer404. The DMOSFET also comprises a P-well region406, a first N+ source region408(i.e. the first conductivity type first source region) and a second N+ source region410(i.e. the first conductivity type second source region). The first N+ source region408is formed within the P-well region406. The second N+ source region410is formed within the first N+ source region408by performing a n-type implantation with controlled dosage and energy level. In an embodiment, the second N+ source region410is a depletion region during third quadrant MOSFET operation. The second N+ source region410comprises a thickness and a doping concentration which is significantly less than a thickness and a doping concentration of the first N+ source region408respectively which enables the second N+ source region410to get depleted easily compared to the first N+ source region408. In an embodiment, the second N+ source region410comprises the thickness ranging from 1% to 90% lower than the thickness of the first N+ source region408. In another embodiment, the second N+ source region410comprises the doping concentration ranging from 1% to 90% lower than the doping concentration of the first N+ source region408.

The DMOSFET also comprises a gate insulator414, a polysilicon layer416and an interlayer dielectric (ILD)418on both sides of top surface of the SiC substrate. The DMOSFET further comprises a first silicide layer420on top of the SiC substrate and a second silicide layer422on bottom side/back side of the SiC substrate to form ohmic contacts for a source terminal and a drain terminal respectively. The DMOSFET further comprises a first pad metal424(e.g. a source metal) and a second pad metal426(e.g. a drain metal) on top of the first silicide layer420and bottom of the second silicide layer422respectively.

During third quadrant operation of the DMOSFET (i.e. when the source terminal is positively biased with respect to the drain terminal), an intrinsic p-n junction between the second N+ source region410and the p-well region406is reverse biased as electric potential of the first pad metal424is low when compared to electric potential of the second pad metal426. The second N+ source region410starts depleting during the third quadrant operation. The first pad metal424(e.g. the source metal) is directly short circuited (i.e. connected) with the P-well region406, when the second N+ source region410is completely depleted. The second N+ source region410enables one or more body diode regions of the DMOSFET to have an increased turn-on voltage and the one or more body diode regions turn on only when the second N+ source region410is completely depleted. The increased turn-on voltage is due to intrinsic bandgap of the SiC. As the complete depletion of the second N+ source region410depends on at least one of a thickness and a doping concentration of the second N+ source region410, the turn-on voltage of the one or more body diode regions also depends on the thickness and the doping concentration of the second N+ source region410. The turn-on voltage of the one or more body diode regions is tuned by controlling/adjusting the thickness and the doping concentration of the second N+ source region410to a target thickness and a target doping concentration respectively. In an embodiment, the target thickness ranges from 1 nm to 1 μm. In another embodiment, the target doping concentration ranges from 1015cm−3to 1021cm−3. The target thickness and the target doping concentration of the second N+ source region410is achieved by monitoring and controlling the dosage and the energy level of the n-type implantation.

FIG.4billustrates an embodiment of a cross sectional structure of one or more unit cells of the DMOSFET, comprising one or more unit cells of an integrated Schottky diode, each DMOSFET unit cell comprising the first conductivity type second source region within the first conductivity type first source region. The DMOSFET (shown inFIG.4b) is a n-type planar gate DMOSFET. The DMOSFET shown inFIG.4boperates in a similar way toFIG.4a. In addition toFIG.4a, the DMOSFET (shown inFIG.4b) comprises a metal region (i.e. a Schottky metal region428) and one or more P-well regions406. The Schottky metal region428is in direct contact with the N− drift layer404and bridges the adjacent P-well regions406(i.e. bridges the adjacent unit cells) of the one or more P-well regions406. The DMOSFET comprises each second N+ source region410between the first silicide layer420and the respective P-well region406.

FIG.5a-5tillustrate an embodiment of a process of manufacturing the DMOSFET structure shown inFIG.4a. The process of manufacturing the DMOSFET structure (shown inFIG.5a) comprises preparing a Silicon Carbide (SiC) substrate having a N+ substrate502and a N− drift layer504as shown inFIG.5a. The N− drift layer504of the SiC substrate is epi-grown and prepared such that a doping concentration and a thickness of the N− drift layer504are selected primarily based on blocking voltage and forward conduction loss. The N+ substrate502is highly conductive when compared to the N− drift layer504and the N+ substrate502is in direct contact with the N-drift layer504. A first patterned hard mask layer505is formed on top of the SiC substrate as shown inFIG.5b. The first patterned hard mask layer505is thick enough for completely blocking high energy impurities during implantation. In an embodiment, the first patterned hard mask layer505is a hard mask of at least one of oxide, nitride and a polysilicon.

A first p-type ion implantation is formed inFIG.5cthrough the first patterned hard mask layer505to form a p-well region506. In an embodiment, the first p-type ion implantation is performed with one or more p-type impurities (e.g. aluminum, boron, etc.). In another embodiment, first p-type ion implantation may comprise a screen oxide layer. The first patterned hard mask layer505is then removed, after the first p-type ion implantation, by at least one of dry etching process and wet etching process as shown inFIG.5d. A second patterned hard mask layer507is then formed on the top of the SiC substrate as shown inFIG.5efor subsequent ion implantation. The second patterned hard mask layer507is a photoresist based material and thick enough for preventing any unwanted high energy impurities particles penetrating the second patterned hard mask layer507. A first n-type ion implantation is formed through the second patterned hard mask layer507to form a first N+ source region508(i.e. the first conductivity type first source region) within the p-well region506as shown inFIG.5f. In an embodiment, the first n-type ion implantation is performed with one or more n-type impurities (e.g. nitrogen, phosphorous etc.). The second patterned hard mask layer507is then removed after the first n-type ion implantation by at least one of dry etching and wet etching process as shown inFIG.5g.

A third patterned hard mask layer509is then formed on top of the SiC substrate as shown inFIG.5h. A second n-type implantation is performed through the third patterned hard mask layer509to form a second N+ source region510within the first N+ source region508within each p-well region506as shown inFIG.5i. The dosage and energy level of the second n-type implantation is controlled accurately and precisely to form the second N+ source region510having a target thickness and a target doping concentration. The target thickness may range from 1 nm to 1 μm. The target doping concentration may range from 1015cm−3to 1021cm−3. In an embodiment, a doping concentration and a thickness of the second N+ source region510is less than a doping concentration and a thickness of the first N+ source region508respectively. In one embodiment, the doping concentration of the second N+ source region510is 1% to 90% lower than the doping concentration of the first N+ source region508. In another embodiment, the thickness of the second N+ source region510is 1% to 90% lower than the thickness of the first N+ source region508.

The third patterned hard mask layer509is then removed as shown inFIG.5jby at least one of a dry etching and a wet etching process once the second N+ source region510having the target thickness and the target doping concentration is achieved. The SiC substrate undergoes thermal activation annealing with a carbon-based protection coating at a predefined temperature. In an embodiment, the predefined temperature for performing the thermal activation annealing is 1700-degree Celsius. The SiC substrate then may undergo an additional ion implantation for forming a current spreading layer to improve on-state resistance. Ion implantations (e.g. the first p-type implantation, the first n-type impanation, the second p-type implantation, edge termination implantation, current spreading layer implantation etc.) undergone by the SiC substrate is performed prior to the thermal activation annealing step. The carbon-based protection coating is then removed from the SiC substrate. The SiC substrate then undergoes a sacrificial oxide growth and subsequently the sacrificial oxide removal. An active region of the SiC DMOSFET is then patterned by forming and patterning field oxide layer on the SiC substrate.

A gate insulator514is then formed on top of the SiC substrate as shown inFIG.5k. The gate insulator is then patterned as shown inFIG.5l. A polysilicon layer516is then formed on top of the SiC substrate as shown inFIG.5m. The polysilicon layer516is then patterned as shown inFIG.5n. Contacts for the polysilicon layer is kept open for pad metal deposition for forming a gate pad region and one or more gate bus regions. An interlayer dielectric (ILD)518is then formed on top of the SiC substrate as shown inFIG.5o. The interlayer dielectric (ILD)518is then patterned for exposing the portions of the SiC substrate via the openings of the ILD518as shown inFIG.5p. A first silicide layer520is then formed on the exposed portions of top of the SiC substrate for forming a first Ohmic contact (e.g. a source terminal contact) as shown inFIG.5q. In an embodiment, the first silicide layer520is a nickel-based silicide layer. In another embodiment, the nickel-based silicide is formed by Nickel deposition on the top of the SiC substrate, thermal activation annealing of the deposited Nickel for silicide formation, and removal of any un-reacted Nickel from the SiC substrate. A first pad metal524is then formed on top of the first silicide layer520of the SiC substrate as shown inFIG.5r.

A second silicide layer522is then formed on bottom of the SiC substrate for forming a second Ohmic contact (e.g. a drain terminal contact) as shown inFIG.5s. In an embodiment, the second silicide layer522is then formed on back of the SiC substrate for forming the second Ohmic contact (e.g. the drain terminal contact). In an embodiment, the second silicide layer522is also the nickel-based silicide layer. A second pad metal526is then formed on bottom of the second silicide layer522of the SiC substrate as shown in5t. In an embodiment, the second pad metal formation is performed by at least one of e-beam and sputtering.

A fourth patterned hard mask layer511is then formed on the SiC substrate once the first Ohmic contact and the second Ohmic contact are formed on top and bottom side/back side of the SiC substrate respectively. The fourth patterned hard mask layer511is formed for selectively removing the exposed portions of the ILD layer518and forming a metal region528(i.e. a Schottky metal region528) shown inFIG.4b. The fourth patterned hard mask layer511is used for both etching the portion of the ILD layer518and lifting off the Schottky metal region528when Schottky metal is deposited. The Schottky metal region528is in direct contact with the top of the N− drift layer504and bridge two adjacent P-well regions506(e.g. bridges the adjacent unit cells). The Schottky metal region528is then annealed with a predefined thermal budget for forming a Schottky metal contact between the second Schottky metal region528and the portion of the N-drift layer504exposed at the top surface of the SiC substrate. In an embodiment, the predefined thermal budget ranges from 55° C. to 1100° C. InFIG.4bthe first pad metal and the second pad metal formation are performed once the Schottky metal region528formation is completed.

FIG.6aillustrates an embodiment of a cross sectional structure of a unit cell of a double-implantation metal oxide semiconductor field effect transistor (DMOSFET) comprising a first metal region in direct contact with a second conductivity type well contact region. The DMOSFET (shown inFIG.6a) is a n-type planar gate SiC DMOSFET. In an embodiment, the DMOSFET is a p-type planar gate DMOSFET. In another embodiment, the DMOSFET is a p-type trench gate DMOSFET. In yet another embodiment, the DMOSFET is a n-type trench gate DMOSFET. The DMOSFET (shown inFIG.6a) comprises a Silicon Carbide (SiC) substrate. The SiC substrate comprises a N+ substrate602and a N− drift layer604. The DMOSFET also comprises a P-well region606, a first N+ source region608and a P+ region603(i.e. the second conductivity type well contact region). The first N+ source region608is formed within the P-well region606. The P+ region603(i.e. the second conductivity type well contact region) is formed within the P-well region606by performing a p-type implantation. The second conductivity type well contact region specifically refers to the P+ region603. The first metal region613(e.g. a first Schottky metal region613) is then formed in direct contact with the P+ region603to connect one or more Schottky diode regions in series with one or more body diode regions of the DMOSFET. The first Schottky metal region613comprises a target work function. In an embodiment, the target work function of the first Schottky metal region613ranges from 3.5 electron volts to 6 electron volts. The work function of the first Schottky metal region613and the series connection of the Schottky diode regions with the body diode regions allows the one or more body diode regions to turn-on only when significant number of carriers from the first Schottky metal region613is thermionically injected over Schottky barrier during third quadrant operation of the DMOSFET. Since the one or more Schottky diode regions are connected in series with the one or more body diode regions, the one or more Schottky diode regions consumes the voltage of the one or more body diode regions and the one or more Schottky diode regions turn on first before the one or more body diode regions. Any additional applied voltage that is greater than turn-on voltage of the one or more Schottky diode regions contributes to turn-on the one or more body diode regions. Due to the series connection of the one or more Schottky diode regions with the body diode regions, the body diode regions consume additional turn-on voltage compared to typical turn-on voltage. The one or more body diode regions get turn-on only when the first Schottky metal region613turn on with a forward voltage which corresponds at least to the barrier height of a first Schottky contact region for starting the on-set of the carrier injection over the Schottky barrier (i.e. when the first Schottky metal region613comprises the target work function). The forward voltage initiates the carrier injection to turn-on the Schottky diode regions. Any additional forward voltage that is greater than the turn-on voltage of the Schottky diode regions contributes to turn-on the body diode regions. The turn-on voltage of the body diode regions is tuned by at least one of controlling a Schottky barrier height and selecting a Schottky metal with an appropriate work function utilized in forming the first Schottky metal region613. The turn-on voltage of the body diode regions is also tuned by adjusting thermal budget for annealing the first Schottky contact region once the first Schottky metal region613is formed on top of the SiC substrate. The predefined thermal budget may range from 55° C. to 1100° C. In an embodiment, the DMOSFET comprises a second metal region628(e.g. a second Schottky metal region628) directly on top of the N− drift layer604and bridge adjacent P-well regions606of the one or more P-well regions606(i.e. bridges the adjacent unit cells) shown inFIG.6b. The work function of the first Schottky metal region613is less than a work function of the second Schottky metal region628.

FIG.6billustrates an embodiment of a cross sectional structure of one or more unit cells of the DMOSFET, comprising one or more unit cells of an integrated Schottky diode, each DMOSFET unit cell comprising the first metal region in direct contact with the respective second conductivity type well contact region. The DMOSFET (shown inFIG.6b) is a n-type planar gate SiC DMOSFET. The DMOSFET shown inFIG.6boperates in a similar way toFIG.6a. In addition toFIG.6a, the DMOSFET (shown inFIG.6b) comprises the second Schottky metal region628and one or more P-well regions606. The second Schottky metal region628is in direct contact with the N− drift layer604and bridges the adjacent P-well regions606(i.e. the adjacent unit cells) of the one or more P-well regions606. The work function of the first Schottky metal region613is less than the work function of the second Schottky metal region628.

FIG.6cillustrates an embodiment of a third quadrant current conduction through an intrinsic p-n junction diode region vs a Schottky diode region connected in parallel to DMOSFET. The third quadrant current of the body diode region is indicated as630in theFIG.6c. The third quadrant current of the anti-parallel Schottky diode region is indicated as632in theFIG.6c. At a certain point, the third quadrant current passing through the body diode region intersects with the third quadrant current passing through the Schottky diode region which is indicated as634inFIG.6c. Above this point, the third quadrant current is bipolar in nature which results in performance and reliability issues.

FIG.6dillustrates an embodiment of a third quadrant current conduction through the DMOSFET after connecting the one or more Schottky diode regions in series with the one or more body diode regions of the DMOSFET. The third quadrant current of the body diode region is indicated as636in theFIG.6d. Due to the existence of the one or more Schottky diode regions in series connection with the one or more body diode regions, the magnitude of the third quadrant current is shifted by the additional current required for the one or more Schottky diode regions to turn-on first. The shift in the magnitude of the third quadrant current ((i.e.) the increased third quadrant current), after connecting the one or more Schottky diode regions in series with the one or more body diode regions, is indicated as638inFIG.6d. It is evident fromFIG.6candFIG.6d, the magnitude of the third quadrant current is increased when the one or more Schottky Diode regions is connected in series with the one or more body diode regions of the DMOSFET.

FIG.7a-7xillustrate an embodiment of a process of manufacturing the DMOSFET structure shown inFIG.6a. The process of manufacturing the DMOSFET structure (shown inFIG.7a) comprises preparing a Silicon Carbide (SiC) substrate having a N+ substrate702and a N− drift layer704as shown inFIG.7a. The N− drift layer704of the SiC substrate is epi-grown and prepared such that a doping concentration and a thickness of the N− drift layer704are selected primarily based on blocking voltage and forward conduction loss. The N+ substrate702is highly conductive when compared to the N− drift layer704and the N+ substrate702is in direct contact with the N-drift layer704. A first patterned hard mask layer705is formed on top of the SiC substrate as shown inFIG.7b. The first patterned hard mask layer705is thick enough for completely blocking high energy impurities during implantation. In an embodiment, the first patterned hard mask layer705is a hard mask of at least one of oxide, nitride and polysilicon.

A first p-type ion implantation is formed inFIG.7cthrough the first patterned hard mask layer705to form a p-well region706. In an embodiment, the first p-type ion implantation is performed with one or more p-type impurities (e.g. aluminum, boron, etc.). In another embodiment, first p-type ion implantation may comprise a screen oxide layer. The first patterned hard mask layer705is then removed, after the first p-type ion implantation, by at least one of dry etching process and wet etching process as shown inFIG.7d. A second patterned hard mask layer707is then formed on the top of the SiC substrate as shown inFIG.7efor subsequent ion implantation. The second patterned hard mask layer707is a photoresist based material and thick enough for preventing any unwanted high energy impurities particles penetrating the second patterned hard mask layer707. A first n-type ion implantation is formed through the second patterned hard mask layer707to form a N+ source region708within the p-well region706as shown inFIG.7f. In an embodiment, the first n-type ion implantation is performed with one or more n-type impurities (e.g. nitrogen, phosphorous etc.). The second patterned hard mask layer707is then removed after the first n-type ion implantation by at least one of dry etching and wet etching process as shown inFIG.7g.

A third patterned hard mask layer709is then formed on top of the SiC substrate as shown inFIG.7h. A second p-type implantation is performed through the third patterned hard mask layer709to form a P+ region703within the p-well region706as shown inFIG.7i.

The third patterned hard mask layer709is then removed as shown inFIG.7jby at least one of a dry etching and a wet etching process once the P+ region703is formed. The SiC substrate undergoes thermal activation annealing with a carbon-based protection coating at a predefined temperature. In an embodiment, the predefined temperature for performing the thermal activation annealing is 1700-degree Celsius. The SiC substrate then may undergo an additional ion implantation for forming a current spreading layer to improve on-state resistance. Ion implantations (e.g. the first p-type implantation, the first n-type impanation, the second p-type implantation, edge termination implantation, current spreading layer implantation etc.) undergone by the SiC substrate is performed prior to the thermal activation annealing step. The carbon-based protection coating is then removed from the SiC substrate. The SiC substrate then undergoes a sacrificial oxide growth and subsequently the sacrificial oxide removal. An active region of the SiC DMOSFET is then patterned by forming and patterning field oxide layer on the SiC substrate.

A gate insulator714is then formed on top of the SiC substrate as shown inFIG.7k. The gate insulator is then patterned as shown inFIG.7l. A polysilicon layer716is then formed on top of the SiC substrate as shown inFIG.7m. The polysilicon layer716is then patterned as shown inFIG.7n. Contacts for the polysilicon layer is kept open for pad metal deposition for forming a gate pad region and one or more gate bus regions. An interlayer dielectric (ILD)718is then formed on top of the SiC substrate as shown inFIG.7o. The interlayer dielectric (ILD)718is then patterned for exposing the portions of the SiC substrate via the openings of the ILD718as shown inFIG.7p. A first silicide layer720is then formed on the exposed portions of top of the SiC substrate for forming a first Ohmic contact as shown inFIG.7q. In an embodiment, the first silicide layer720is a nickel-based silicide layer. In another embodiment, the nickel-based silicide is formed by Nickel deposition on the top of the SiC substrate, thermal activation annealing of the deposited Nickel for silicide formation, and removal of any un-reacted Nickel from the SiC substrate. A fourth patterned hard mask layer711is formed on top of the SiC substrate as shown inFIG.7r.

An ILD etching is formed on the SiC substrate through the fourth patterned hard mask layer711to selectively remove the exposed portions of the ILD layer718as shown inFIG.7s. A first metal is deposited on top of the SiC substrate through the fourth patterned hard mask layer711as shown inFIG.7t. The first metal is lifted off and annealed to form a first metal region713(e.g. the first Schottky metal region713) to be in direct contact with the P+ region703as shown inFIG.7u. The first Schottky metal region713comprises a target work function. In an embodiment, the target work function may range from 3.5 electron volts to 6 electron volts. The first Schottky metal region713is then annealed with a predefined thermal budget for forming a first Schottky contact region between the first Schottky metal region713and the top of each P+ region703. In an embodiment, the predefined thermal budget ranges from 55° C. to 1100° C. The thermal budget for forming the first Schottky contact region is precisely designed and controlled as it directly impacts electrical properties of the first Schottky contact regions. A first pad metal724is formed on top of the SiC substrate as shown inFIG.7v.

A second silicide layer722is then formed on bottom of the SiC substrate for forming a second Ohmic contact as shown inFIG.7w. In an embodiment, the second silicide layer722is then formed on back of the SiC substrate for forming the second Ohmic contact (e.g. a drain terminal contact). In an embodiment, the second silicide layer722is the nickel-based silicide layer. A second pad metal726is then formed on bottom of the second silicide layer722of the SiC substrate. In an embodiment, the second pad metal formation is performed by at least one of e-beam and sputtering.

A fifth patterned hard mask layer715is then formed on the SiC substrate once the first Ohmic contact and the second Ohmic contact are formed on topside and bottom side/back side of the SiC substrate respectively. The fifth patterned hard mask layer715is formed for selectively removing the exposed portions of the ILD layer718and depositing a second metal region728(i.e. a second Schottky metal region728) (shown inFIG.5b) on top of the SiC substrate. The fifth patterned hard mask layer715is used for both etching the portion of the ILD layer718and lifting off the second Schottky metal region728when second Schottky metal is deposited. The second Schottky metal region728is in direct contact with the N− drift layer704and bridge two adjacent P-well regions706(i.e. bridges the adjacent unit cells). The second Schottky metal region728is then annealed with a predefined thermal budget for forming a second Schottky metal contact between the second Schottky metal region728and the portion of the N− drift layer704exposed at the top surface of the SiC substrate. In an embodiment, the predefined thermal budget ranges from 55° C. to 1100° C. InFIG.6bthe first pad metal and the second pad metal formation are performed once the second Schottky metal region728formation is completed.

FIG.8a-8cillustrate an embodiment of cross-sectional structures of a unit cell of a DMOSFET comprising a second conductivity type well contact region that meanders at three different locations respectively. The DMOSFET shown inFIGS.8a,8band8cis a n-type planar gate SiC DMOSFET. In an embodiment, the DMOSFET is a p-type planar gate DMOSFET. In another embodiment, the DMOSFET is a n-type trench gate DMOSFET. In yet another embodiment, the DMOSFET is a p-type trench gate DMOSFET. The DMOSFET (shown inFIGS.8a,8band8c) comprises a Silicon Carbide (SiC) substrate. The SiC substrate comprises a N+ substrate802and a N− drift layer804. The DMOSFET also comprises a P-well region806, a N+ source region808and a P+ region803(i.e. the second conductivity type well contact region). The N+ source region808(i.e. a first conductivity type source region) is formed within the P-well region806. The P+ region803is meandering within the P-well region806by performing a p-type implantation at respective locations. The P+ region803comprise a periodic spacing with the successive P+ region803(i.e. non-contiguous). Further the lateral extent of the P+ region803varies with a non-zero value in a direction orthogonal to the unit cell. The meandering P+ region803periodically forms ohmic contacts to a first pad metal824(e.g. a source metal) via a first silicide layer820between two interlayer dielectric (ILD) bumps817located between metal oxide semiconductor gate stack and the first pad metal824. The meandering P+ region803follows Zigzag path, where corners of the zigzag path is right angled. The Zigzag path of the meandering P+ region803comprises dimensions α, β, and γ. The meandering P+ region803comprise a target size and are a target spacing between adjacent junction points located between the meandering P+ region803. Contact resistance to the first pad metal824(e.g. the source metal) varies when the P+ region803under the ILD bumps817do not have direct contact with the first pad metal824and when the P+ region803have direct contact with the first pad metal824through the first silicide layer820. The portions of the meandering P+ region803which are directly under the ILD bumps817functions as networks of distributed ballast resistors and provides an additional source resistance to the source contact resistance. The additional contact resistance provided directly impacts the differential on-resistance of one or more body diode regions of the DMOSFET. The impacted differential-on resistance of the body diode regions suppresses increase of forward conduction current of the one or more body diode regions. The limited forward conduction current mitigates basal plane dislocation (BPD). Since the source contact resistance is dependent on the sizing, the spacing between adjacent junction points located between the meandering P+ region803, and the silicide region between the adjacent ILD bumps817, the source contact resistance is tuned by sizing the P+ region803to a target size and controlling the spacing to a target spacing. In an embodiment, the target size ranges from 10 nm to 10 μm. In another embodiment, the target spacing ranges from 10 nm to 10 μm. Say for a first instance, when width (u) of the meandering P+ region803is reduced, the resistance of each ballast resistor network is increased which degrades the differential on-resistance of the one or more body diode regions. The reduction of the width (α), also shrinks the area where the Ohmic contacts are formed, degrades the differential on-resistance of the one or more body diode regions. Say for a second instance, when the periodic spacing (γ) between the meandering P+ region803is increased, the resistance of each ballast resistor network is increased which degrades the differential on-resistance of the one or more body diode regions. Say for a third instance, when spacing (β) between two adjacent junction points between the meandering featured P+ region803, and the straight silicide region between two adjacent ILD bumps817is increased, the resistance of each ballast resistor network is increased which degrades the differential on-resistance of the one or more body diode regions.

FIG.8d-8fillustrate an embodiment of cross-sectional structures of one or more unit cells of a diode integrated DMOSFET, each DMOSFET unit cell comprising the second conductivity type well contact region that meanders at three different locations respectively. The DMOSFET (shown inFIGS.8d,8e&8f) is a n-type planar gate SiC DMOSFET. The DMOSFET shown inFIGS.8d,8e&8foperates in a similar way toFIGS.8a,8b&8c. In addition toFIGS.8a,8b&8c, the DMOSFET (shown inFIGS.8d,8e&8f) comprises a metal region (i.e. a Schottky metal region828) in direct contact with the N− drift layer804and bridges adjacent P-well regions806of the one or more P-well regions806(i.e. bridges the adjacent unit cells). The DMOSFET comprises the P+ region803that meanders within each P-well region806.

FIG.9a-9tillustrate an embodiment of a process of manufacturing the DMOSFET structure shown inFIG.8a. The process of manufacturing the DMOSFET structure (shown inFIG.9a) comprises preparing a Silicon Carbide (SiC) substrate having a N+ substrate902and a N− drift layer904as shown inFIG.9a. The N− drift layer904of the SiC substrate is epi-grown and prepared such that a doping concentration and a thickness of the N− drift layer904are selected primarily based on blocking voltage and forward conduction loss. The N+ substrate902is highly conductive when compared to the N− drift layer904and the N+ substrate902is directly located under the N-drift layer904. A first patterned hard mask layer905is formed on top of the SiC substrate as shown inFIG.9b. The first patterned hard mask layer905is thick enough for completely blocking high energy impurities during implantation. In an embodiment, the first patterned hard mask layer905is a hard mask of at least one of oxide, nitride and a polysilicon layer.

A first p-type ion implantation is formed inFIG.9cthrough the first patterned hard mask layer905to form a p-well region906. In an embodiment, the first p-type ion implantation is performed with one or more p-type impurities (e.g. aluminum, boron, etc.). In another embodiment, first p-type ion implantation may comprise a screen oxide layer. The first patterned hard mask layer905is then removed, after the first p-type ion implantation, by at least one of dry etching process and wet etching process as shown inFIG.9d. A second patterned hard mask layer907is then formed on the top of the SiC substrate as shown inFIG.9efor subsequent ion implantation. The second patterned hard mask layer907is a photoresist based material and thick enough for preventing any unwanted high energy impurities particles penetrating the second patterned hard mask layer907. A first n-type ion implantation is formed through the second patterned hard mask layer907to form a N+ source region908within the p-well region906as shown inFIG.9f. In an embodiment, the first n-type ion implantation is performed with one or more n-type impurities (e.g. nitrogen, phosphorous etc.). The second patterned hard mask layer907is then removed after the first n-type ion implantation by at least one of dry etching and wet etching process as shown inFIG.9g.

A third patterned hard mask layer909is then formed on top of the SiC substrate as shown inFIG.9h. A second p-type implantation is performed through the third patterned hard mask layer909to form a P+ region903, at a first location within the p-well region906as shown inFIG.9i.

The third patterned hard mask layer909is then removed as shown inFIG.9jby at least one of a dry etching and a wet etching process once the P+ region903is formed. The SiC substrate undergoes thermal activation annealing with a carbon-based protection coating at a predefined temperature. In an embodiment, the predefined temperature for performing the thermal activation annealing is 1700-degree Celsius. The SiC substrate then may undergo an additional ion implantation for forming a current spreading layer to improve on-state resistance. Ion implantations (e.g. the first p-type implantation, the first n-type impanation, the second p-type implantation, edge termination implantation, current spreading layer implantation etc.) undergone by the SiC substrate is performed prior to the thermal activation annealing step. The carbon-based protection coating is then removed from the SiC substrate. The SiC substrate then undergoes a sacrificial oxide growth and subsequently the sacrificial oxide removal. An active region of the SiC DMOSFET is then patterned by forming and patterning field oxide layer on the SiC substrate.

A gate insulator914is then formed on top of the SiC substrate as shown inFIG.9k. The gate insulator914is then patterned as shown inFIG.9l. A polysilicon layer916is then formed on top of the SiC substrate as shown inFIG.9m. The polysilicon layer916is then patterned as shown inFIG.9n. Contacts for the polysilicon layer is kept open for pad metal deposition for forming a gate pad region and one or more gate bus regions. An interlayer dielectric (ILD)918is then formed on top of the SiC substrate as shown inFIG.9o. The interlayer dielectric (ILD)918is then patterned for exposing the portions of the SiC substrate via the openings of the ILD918and leaving one or more ILD bumps917as shown inFIG.9p. A first silicide layer920is then formed between the one or more ILD bumps917on the exposed portions of top of the SiC substrate for forming a first Ohmic contact as shown inFIG.9q. In an embodiment, the first silicide layer920is a nickel-based silicide layer. In another embodiment, the nickel-based silicide is formed by Nickel deposition on the top of the SiC substrate, thermal activation annealing of the deposited Nickel for silicide formation, and removal of any un-reacted Nickel from the SiC substrate. A first pad metal924is formed on top of the SiC substrate as shown inFIG.9r. The P+ region903, formed at the first location, covers both portions of the first silicide layer920between the adjacent ILD bumps917and the portions under the ILD bumps917.

A second silicide layer922is then formed on bottom of the SiC substrate for forming a second Ohmic contact as shown inFIG.9s. In an embodiment, the second silicide layer922is then formed on back of the SiC substrate for forming the second Ohmic contact. In an embodiment, the second silicide layer922is also the nickel-based silicide layer. A second pad metal926is then formed on bottom of the second silicide layer922of the SiC substrate as shown inFIG.9t. In an embodiment, the second pad metal formation is performed by at least one of e-beam and sputtering.

A fourth patterned hard mask layer911is then formed on the SiC substrate once the first Ohmic contact and the second Ohmic contact are formed on topside and bottom side/back side of the SiC substrate respectively. The fourth patterned hard mask layer911is formed for selectively removing the exposed portions of the ILD layer918and depositing a metal region (i.e. a Schottky metal region928) (shown inFIGS.8d,8e&8f) on top of the SiC substrate. The fourth patterned hard mask layer911is used for both etching the portion of the ILD layer918and lifting off the Schottky metal region928when Schottky metal is deposited. The Schottky metal region928is in direct contact with the N− drift layer904and bridge two adjacent P-well regions906(i.e. bridges the adjacent unit cells). The Schottky metal region928is then annealed with a predefined thermal budget for forming a Schottky metal contact between the Schottky metal region928and the portion of the N− drift layer904exposed at the top surface of the SiC substrate. In an embodiment, the predefined thermal budget ranges from 55° C. to 1100° C. InFIGS.8d,8e&8f, the first pad metal and the second pad metal formation are performed once the Schottky metal region928formation is completed.

FIG.10a-10tillustrate an embodiment of a process of manufacturing the DMOSFET structure shown inFIG.8b. The process of manufacturing the DMOSFET structure (shown inFIG.10a) comprises preparing a silicon carbide (SiC) substrate having a N+ substrate1002and a N-drift layer1004as shown inFIG.10a. The N− drift layer1004of the SiC substrate is epi-grown and prepared such that a doping concentration and a thickness of the N− drift layer1004are selected primarily based on blocking voltage and forward conduction loss. The N+ substrate1002is highly conductive when compared to the N− drift layer1004and the N+ substrate1002is in direct contact with the N− drift layer1004. A first patterned hard mask layer1005is formed on top of the SiC substrate as shown inFIG.10b. The first patterned hard mask layer1005is thick enough for completely blocking high energy impurities during implantation. In an embodiment, the first patterned hard mask layer1005is a hard mask of at least one of oxide, nitride and a polysilicon layer.

A first p-type ion implantation is formed inFIG.10cthrough the first patterned hard mask layer1005to form a p-well region1006. In an embodiment, the first p-type ion implantation is performed with one or more p-type impurities (e.g. aluminum, boron, etc.). In another embodiment, first p-type ion implantation may comprise a screen oxide layer. The first patterned hard mask layer1005is then removed, after the first p-type ion implantation, by at least one of dry etching process and wet etching process as shown inFIG.10d. A second patterned hard mask layer1007is then formed on the top of the SiC substrate as shown inFIG.10efor subsequent ion implantation. The second patterned hard mask layer1007is a photoresist based material and thick enough for preventing any unwanted high energy impurities particles penetrating the second patterned hard mask layer1007. A first n-type ion implantation is formed through the second patterned hard mask layer1007to form a N+ source region1008within the p-well region1006as shown inFIG.10f. In an embodiment, the first n-type ion implantation is performed with one or more n-type impurities (e.g. nitrogen, phosphorous etc.). The second patterned hard mask layer1007is then removed after the first n-type ion implantation by at least one of dry etching and wet etching process as shown inFIG.10g.

A third patterned hard mask layer1009is then formed on top of the SiC substrate as shown inFIG.10h. A second p-type implantation is performed through the third patterned hard mask layer1009to form a P+ region1003, at a second location, within the p-well region1006as shown inFIG.10i.

The third patterned hard mask layer1009is then removed as shown inFIG.10jby at least one of a dry etching and a wet etching process once the P+ region1003is formed at the second location. The SiC substrate undergoes thermal activation annealing with a carbon-based protection coating at a predefined temperature. In an embodiment, the predefined temperature for performing the thermal activation annealing is 1700-degree Celsius. The SiC substrate then may undergo an additional ion implantation for forming a current spreading layer to improve on-state resistance. Ion implantations (e.g. the first p-type implantation, the first n-type impanation, the second p-type implantation, edge termination implantation, current spreading layer implantation etc.) undergone by the SiC substrate is performed prior to the thermal activation annealing step. The carbon-based protection coating is then removed from the SiC substrate. The SiC substrate then undergoes a sacrificial oxide growth and subsequently the sacrificial oxide removal. An active region of the SiC DMOSFET is then patterned by forming and patterning field oxide layer on the SiC substrate.

A gate insulator1014is then formed on top of the SiC substrate as shown inFIG.10k. The gate insulator1014is then patterned as shown inFIG.10l. A polysilicon layer1016is then formed on top of the SiC substrate as shown inFIG.10m. The polysilicon layer1016is then patterned as shown inFIG.10n. Contacts for the polysilicon layer is kept open for pad metal deposition for forming a gate pad region and one or more gate bus regions. An interlayer dielectric (ILD)1018is then formed on top of the SiC substrate as shown inFIG.10o. The interlayer dielectric (ILD)1018is then patterned for exposing the portions of the SiC substrate via the openings of the ILD1018and leaving one or more ILD bumps1017on top of the SiC substrate as shown inFIG.10p. A first silicide layer1020is then formed between the one or more ILD bumps1017on the exposed portions of top of the SiC substrate for forming a first Ohmic contact as shown inFIG.10q. In an embodiment, the first silicide layer1020is a nickel-based silicide layer. In another embodiment, the nickel-based silicide is formed by Nickel deposition on the top of the SiC substrate, thermal activation annealing of the deposited Nickel for silicide formation, and removal of any un-reacted Nickel from the SiC substrate. A first pad metal1024is formed on top of the SiC substrate as shown inFIG.10r. The P+ region1003, formed at the second location, is under the one or more ILD bumps1017and do not form any direct contact with the first silicide layer1020.

A second silicide layer1022is then formed on bottom of the SiC substrate for forming a second Ohmic contact as shown inFIG.10s. In an embodiment, the second silicide layer1022is then formed on back of the SiC substrate for forming the second Ohmic contact. In an embodiment, the second silicide layer1022is also the nickel-based silicide layer. A second pad metal1026is then formed on bottom of the second silicide layer1022of the SiC substrate as shown inFIG.10t. In an embodiment, the second pad metal formation is performed by at least one of e-beam and sputtering.

A fourth patterned hard mask layer1011is then formed on the SiC substrate once the first Ohmic contact and the second Ohmic contact are formed on topside and bottom side/back side of the SiC substrate respectively. The fourth patterned hard mask layer1011is formed for selectively removing the exposed portions of the ILD layer1018and depositing a metal region1028(e.g. a Schottky metal region1028) (shown inFIGS.8d,8e&8f) on top of the SiC substrate. The fourth patterned hard mask layer1011is used for both etching the portion of the ILD layer1018and lifting off the Schottky metal region1028when Schottky metal is deposited. The Schottky metal region1028is in direct contact with the N− drift layer1004and bridge two adjacent P-well regions1006(i.e. bridges the adjacent unit cells). The Schottky metal region1028is then annealed with a predefined thermal budget for forming a Schottky metal contact between the Schottky metal region1028and the portion of the N− drift layer1004exposed at the top surface of the SiC substrate. In an embodiment, the predefined thermal budget ranges from 55° C. to 1100° C. InFIGS.8d,8e&8f, the first pad metal and the second pad metal formation are performed once the Schottky metal region1028formation is completed.

FIG.11a-11tillustrate an embodiment of a process of manufacturing the DMOSFET structure shown inFIG.8c. The process of manufacturing the DMOSFET structure (shown inFIG.11a) comprises preparing a silicon carbide (SiC) substrate having a N+ substrate1102and a N− drift layer1104as shown inFIG.11a. The N− drift layer1104of the SiC substrate is epi-grown and prepared such that a doping concentration and a thickness of the N− drift layer1104are selected primarily based on blocking voltage and forward conduction loss. The N+ substrate1102is highly conductive when compared to the N− drift layer1104and the N+ substrate1102is in direct contact with the N− drift layer1104. A first patterned hard mask layer1105is formed on top of the SiC substrate as shown inFIG.11b. The first patterned hard mask layer1105is thick enough for completely blocking high energy impurities during implantation. In an embodiment, the first patterned hard mask layer1105is a hard mask of at least one of oxide, nitride and a polysilicon layer.

A first p-type ion implantation is formed inFIG.11cthrough the first patterned hard mask layer1105to form a p-well region1106. In an embodiment, the first p-type ion implantation is performed with one or more p-type impurities (e.g. aluminum, boron, etc.). In another embodiment, first p-type ion implantation may comprise a screen oxide layer. The first patterned hard mask layer1105is then removed, after the first p-type ion implantation, by at least one of dry etching process and wet etching process as shown inFIG.11d. A second patterned hard mask layer1107is then formed on the top of the SiC substrate as shown inFIG.11efor subsequent ion implantation. The second patterned hard mask layer1107is a photoresist based material and thick enough for preventing any unwanted high energy impurities particles penetrating the second patterned hard mask layer1107. A first n-type ion implantation is formed through the second patterned hard mask layer1107to form a first N+ source region1108within the p-well region1106as shown inFIG.11f. In an embodiment, the first n-type ion implantation is performed with one or more n-type impurities (e.g. nitrogen, phosphorous etc.). The second patterned hard mask layer1107is then removed after the first n-type ion implantation by at least one of dry etching and wet etching process as shown inFIG.11g.

A third patterned hard mask layer1109is then formed on top of the SiC substrate as shown inFIG.11h. A second p-type implantation is performed through the third patterned hard mask layer1109to form a P+ region1103, at a third location, within the p-well region1106as shown inFIG.11i.

The third patterned hard mask layer1109is then removed as shown inFIG.11jby at least one of a dry etching and a wet etching process once the P+ region1103is formed at the second location. The SiC substrate undergoes thermal activation annealing with a carbon-based protection coating at a predefined temperature. In an embodiment, the predefined temperature for performing the thermal activation annealing is 1700-degree Celsius. The SiC substrate then may undergo an additional ion implantation for forming a current spreading layer to improve on-state resistance. Ion implantations (e.g. the first p-type implantation, the first n-type impanation, the second p-type implantation, edge termination implantation, current spreading layer implantation etc.) undergone by the SiC substrate is performed prior to the thermal activation annealing step. The carbon-based protection coating is then removed from the SiC substrate. The SiC substrate then undergoes a sacrificial oxide growth and subsequently the sacrificial oxide removal. An active region of the SiC DMOSFET is then patterned by forming and patterning field oxide layer on the SiC substrate.

A gate insulator1114is then formed on top of the SiC substrate as shown inFIG.11k. The gate insulator1114is then patterned as shown inFIG.11l. A polysilicon layer1116is then formed on top of the SiC substrate as shown inFIG.11m. The polysilicon layer1116is then patterned as shown inFIG.11n. Contacts for the polysilicon layer is kept open for pad metal deposition for forming a gate pad region and one or more gate bus regions. An interlayer dielectric (ILD)1118is then formed on top of the SiC substrate as shown inFIG.11o. The interlayer dielectric (ILD)1118is then patterned for exposing the portions of the SiC substrate via the openings of the ILD1118and leaving one or more ILD bumps1117on top of the SiC substrate as shown inFIG.11p. A first silicide layer1120is then formed between the one or more ILD bumps1117on the exposed portions of top of the SiC substrate for forming one or more first Ohmic contacts as shown inFIG.11q. In an embodiment, the first silicide layer1120is a nickel-based silicide layer. In another embodiment, the nickel-based silicide is formed by Nickel deposition on the top of the SiC substrate, thermal activation annealing of the deposited Nickel for silicide formation, and removal of any un-reacted Nickel from the SiC substrate. A first pad metal1124is formed on top of the SiC substrate as shown inFIG.11r. The P+ region1103, formed at the third location, is under the one or more ILD bumps1117and do not form any direct contact with the first silicide layer1120.

A second silicide layer1122is then formed on bottom of the SiC substrate for forming a second Ohmic contact as shown inFIG.11s. In an embodiment, the second silicide layer1122is then formed on back of the SiC substrate for forming the second Ohmic contact. In an embodiment, the second silicide layer1122is also the nickel-based silicide layer. A second pad metal1126is then formed on bottom of the second silicide layer1122of the SiC substrate. In an embodiment, the second pad metal formation is performed by at least one of e-beam and sputtering.

A fourth patterned hard mask layer1111is then formed on the SiC substrate once the first Ohmic contact and the second Ohmic contact are formed on topside and bottom side/back side of the SiC substrate respectively. The fourth patterned hard mask layer1111is formed for selectively removing the exposed portions of the ILD layer1118and depositing a metal region1128(i.e. a Schottky metal region1128) shown inFIGS.8d,8e&8fon top of the SiC substrate. The fourth patterned hard mask layer1111is used for both etching the portion of the ILD layer1118and lifting off the Schottky metal region1128when Schottky metal is deposited. The Schottky metal region1128is in direct contact with the top of the N− drift layer1104and bridge two adjacent P-well regions1106(i.e. bridges the adjacent unit cells). The Schottky metal region1128is then annealed with a predefined thermal budget for forming a Schottky metal contact between the Schottky metal region1128and the portion of the N− drift layer1104exposed at the top surface of the SiC substrate. In an embodiment, the predefined thermal budget ranges from 55° C. to 1100° C. InFIGS.8d,8e&8f, the first pad metal and the second pad metal formation are performed once the Schottky metal region1128formation is completed.

FIG.12a-12cillustrate an embodiment of cross sectional structures of a unit cell of a double-implantation metal oxide semiconductor field effect transistor (DMOSFET) comprising a second conductivity type well contact region that meanders at three different locations respectively, allowing a second conductivity type well region to be in contact with a source metal only through the second conductivity type well contact region. The DMOSFET shown inFIGS.12a,12band12cis a n-type planar gate SiC DMOSFET. In an embodiment, the DMOSFET is a p-type planar gate DMOSFET. The DMOSFET (shown inFIGS.12a,12band12c) comprises a Silicon Carbide (SiC) substrate. The SiC substrate comprises a N+ substrate1202and a N− drift layer1204. The DMOSFET also comprises a P-well region1206, a N+ source region1208and a P+ region1203(i.e. the second conductivity type well contact region). The N+ source regions1208is formed within the P-well region1206. The P+ region1203is meandering within the P-well region1206by performing a p-type implantation. The P+ region1203comprise a periodic spacing with the successive P+ region1203(i.e. non-contiguous). Further the lateral extent of the P+ region1203varies with a non-zero value in a direction orthogonal to the unit cell. The meandering P+ region1203periodically forms ohmic contacts to a first pad metal1224(e.g. the source metal) via a first silicide layer1220between two interlayer dielectric (ILD) bumps1217located between metal oxide semiconductor gate stack and the first pad metal1224. The P-well region1206contacts with the first pad metal1224(e.g. the source metal) only through the meandering P+ region1203. The P-well region1206do not have a direct contact with the first pad metal1224. The meandering P+ region1203follows Zigzag path, where corners of the zigzag path is right angled. The Zigzag path of the meandering P+ region1203comprises dimensions α, β, and γ. The meandering P+ region1203comprise a target size and a target spacing between adjacent junction points located between the meandering P+ region803. Contact resistance to the first pad metal1224(e.g. the source metal) varies when the P+ region1203under the ILD bumps1217do not have direct contact with the first pad metal1224and when the P+ region1203have direct contact with the first pad metal1224through the first silicide layer1220. The portions of the meandering P+ region1203which are directly under the ILD bumps1217functions as networks of distributed ballast resistors and provides an additional source resistance to the source contact resistance. The additional contact resistance provided directly impacts the differential on-resistance of one or more body diode regions of the DMOSFET. Since, the p-well region1206contacts the first pad metal1224only through the meandering P+ region1203, flow of carriers is confined within the meandering P+ region1203. The confined flow of carriers increases source contact resistance of each ballast resistor network and further impacts differential on-resistance of the one or more body diode regions of the DMOSFET. Since the source contact resistance is dependent on the sizing, the spacing between adjacent junction points located between the meandering P+ region1203, and the silicide region between the adjacent ILD bumps1217, the source contact resistance is tuned by sizing the P+ region1203to a target size and controlling the spacing to a target spacing. In an embodiment, the target size ranges from 10 nm to 10 μm. In another embodiment, the target spacing ranges from 10 nm to 10 μm. Say for a first instance, when width (u) of the meandering P+ region is reduced, the resistance of each ballast resistor network is increased which degrades the differential on-resistance of the body diode regions. The reduction of the width (u) also shrinks the area where the Ohmic contacts are formed so degrades the differential on-resistance of the body diode regions. Say for a second instance, when spacing (γ) between the meandering P+ region is increased, the resistance of each ballast resistor network is increased which degrades the differential on-resistance of the body diode regions. Say for a third instance, when spacing (0) between two adjacent junction points between the meandering featured P+ region1203, and the straight silicide region between two adjacent ILD bumps1217is increased, the resistance of each ballast resistor network is increased which degrades the differential on-resistance of the one or more body diode regions.

FIG.12d-12fillustrate an embodiment of cross sectional structures of one or more unit cells of a diode integrated DMOSFET, each DMOSFET unit cell comprising the second conductivity type well contact region that meanders at three different locations respectively, allowing the second conductivity type well region to be in contact with the source metal only through the second conductivity type well contact region. The DMOSFET (shown inFIGS.12d,12e&12f) is a n-type planar gate SiC DMOSFET. The DMOSFET shown inFIGS.12d,12e&12foperates in a similar way toFIGS.12a,12b&12c. In addition toFIGS.12a,12b&12c, the DMOSFET (shown inFIGS.12d,12e&12f) comprises a metal region1228(e.g. a Schottky metal region1228) in direct contact with the N− drift layer1204and bridges adjacent P-well regions1206of the one or more P-well regions1206(i.e. bridges the adjacent unit cells).

FIG.12gillustrate an embodiment of a cross sectional structure of one or more unit cells of a diode integrated trench gate MOSFET, comprising one or more unit cells of an integrated Schottky diode, each MOSFET unit cell comprising the second conductivity type well contact region at the first location, allowing the second conductivity type well region to be in contact with the source metal only through the second conductivity type well contact region. The trench gate MOSFET shown inFIG.12gis a n-type trench gate SiC MOSFET. In an embodiment, the trench gate MOSFET is a p-type trench gate SiC MOSFET. The trench gate MOSFET shown inFIG.12goperates in a similar way to planar gate MOSFET shown inFIG.12aandFIG.12d. The main difference between the trench gate MOSFET and the planar gate DMOSFET is that the trench gate MOSFET comprises one or more trench gate structures instead of one or more planar gate structures. The one or more trench gate structures of the trench gate MOSFET comprises sidewalls that are exposing to the first N+ source region1208and the one or more P-well regions1206. The bottom of the one or more trench gate structures is in vicinity of the bottom of the one or more P-well regions1206. In an embodiment, the bottom of the one or more trench gate structures is adjusted appropriately depending on electrical properties of the MOSFET device. Each trench gate structure of the trench gate MOSFET comprises a gate insulator as liner along the sidewall and the bottom of the respective trench gate structure. The trench gate MOSFET also comprises the polysilicon layer that fills each gate-insulator lined trenches and serves as gate electrode. The trench gate MOSFET further comprises the interlayer dielectric (ILD)1218over each polysilicon layer to open short circuitry between the first pad metal1224(e.g. the source metal) and the gate electrode.

FIG.13a-13tillustrate an embodiment of a process of manufacturing the DMOSFET structure shown inFIG.12a. The process of manufacturing the DMOSFET structure (shown inFIG.13a) comprises preparing a silicon carbide (SiC) substrate having a N+ substrate1302and a N− drift layer1304as shown inFIG.13a. The N− drift layer1304of the SiC substrate is epi-grown and prepared such that a doping concentration and a thickness of the N− drift layer1304are selected primarily based on blocking voltage and forward conduction loss. The N+ substrate1302is highly conductive when compared to the N− drift layer1304and the N+ substrate1302is directly located under the N− drift layer1304. A first patterned hard mask layer1305is formed on top of the SiC substrate as shown inFIG.13b. The first patterned hard mask layer1305is thick enough for completely blocking high energy impurities during implantation. In an embodiment, the first patterned hard mask layer1305is a hard mask of at least one of oxide, nitride and a polysilicon layer.

A first p-type ion implantation is formed inFIG.13cthrough the first patterned hard mask layer1305to form a p-well region1306. In an embodiment, the first p-type ion implantation is performed with one or more p-type impurities (e.g. aluminum, boron, etc.). In another embodiment, first p-type ion implantation may comprise a screen oxide layer. The first patterned hard mask layer1305is then removed, after the first p-type ion implantation, by at least one of dry etching process and wet etching process as shown inFIG.13d. A second patterned hard mask layer1307is then formed on the top of the SiC substrate as shown inFIG.13efor subsequent ion implantation. The second patterned hard mask layer1307is a photoresist based material and thick enough for preventing any unwanted high energy impurities particles penetrating the second patterned hard mask layer1307. A first n-type ion implantation is formed through the second patterned hard mask layer1307to form a N+ source region1308within the p-well region1306as shown inFIG.13f. In an embodiment, the first n-type ion implantation is performed with one or more n-type impurities (e.g. nitrogen, phosphorous etc.). The second patterned hard mask layer1307is then removed after the first n-type ion implantation by at least one of dry etching and wet etching process as shown inFIG.13g.

A third patterned hard mask layer1309is then formed on top of the SiC substrate as shown inFIG.13h. A second p-type implantation is performed through the third patterned hard mask layer1309to form a P+ region1303, at a first location, within the p-well region1306as shown inFIG.13i. The P+ region1303formed at the first location allows the P-well region1306to be in contact with a first pad metal1324(e.g. a source metal) only through the P+ region1303formed at the first location.

The third patterned hard mask layer1309is then removed as shown inFIG.13jby at least one of a dry etching and a wet etching process once the P+ region1303is formed. The SiC substrate undergoes thermal activation annealing with a carbon-based protection coating at a predefined temperature. In an embodiment, the predefined temperature for performing the thermal activation annealing is 1700-degree Celsius. The SiC substrate then may undergo an additional ion implantation for forming a current spreading layer to improve on-state resistance. Ion implantations (e.g. the first p-type implantation, the first n-type impanation, the second p-type implantation, edge termination implantation, current spreading layer implantation etc.) undergone by the SiC substrate is performed prior to the thermal activation annealing step. The carbon-based protection coating is then removed from the SiC substrate. The SiC substrate then undergoes a sacrificial oxide growth and subsequently the sacrificial oxide removal. An active region of the SiC DMOSFET is then patterned by forming and patterning field oxide layer on the SiC substrate.

A gate insulator1314is then formed on top of the SiC substrate as shown inFIG.13k. The gate insulator1314is then patterned as shown inFIG.13l. A polysilicon layer1316is then formed on top of the SiC substrate as shown inFIG.13m. The polysilicon layer1316is then patterned as shown inFIG.13n. Contacts for the polysilicon layer1316is kept open for pad metal deposition for forming a gate pad region and one or more gate bus regions. An interlayer dielectric (ILD)1318is then formed on top of the SiC substrate as shown inFIG.13o. The interlayer dielectric (ILD)1318is then patterned for exposing the portions of the SiC substrate via the openings of the ILD1318and leaving one or more ILD bumps1317as shown inFIG.13p. A first silicide layer1320is then formed between the one or more ILD bumps1317on the exposed portions of top of the SiC substrate for forming a first Ohmic contact as shown inFIG.13q. In an embodiment, the first silicide layer1320is a nickel-based silicide layer. In another embodiment, the nickel-based silicide is formed by Nickel deposition on the top of the SiC substrate, thermal activation annealing of the deposited Nickel for silicide formation, and removal of any un-reacted Nickel from the SiC substrate. The first pad metal1324is formed on top of the SiC substrate as shown inFIG.13r. The P+ region1303, formed at the first location, covers both portions of the first silicide layer1320between the adjacent ILD bumps1317and the portions under the ILD bumps1317. The p-well region1306contacts with the first pad metal1324only through the P+ region1303formed at the first location.

A second silicide layer1322is then formed on bottom of the SiC substrate for forming a second Ohmic contact as shown inFIG.13s. In an embodiment, the second silicide layer1322is then formed on back of the SiC substrate for forming the second Ohmic contact. In an embodiment, the second silicide layer1322is also the nickel-based silicide layer. A second pad metal1326is then formed on bottom of the second silicide layer1322of the SiC substrate as shown inFIG.13t. In an embodiment, the second pad metal formation is performed by at least one of e-beam and sputtering.

A fourth patterned hard mask layer1311is then formed on the SiC substrate once the first Ohmic contact and the second Ohmic contact are formed on topside and bottom side/back side of the SiC substrate respectively. The fourth patterned hard mask layer1311is formed for selectively removing the exposed portions of the ILD layer1318and depositing a metal region (e.g. the Schottky metal region1328) shown inFIGS.13d,13e&13fon top of the SiC substrate. The fourth patterned hard mask layer1311is used for both etching the portion of the ILD layer1318and lifting off the Schottky metal region1328when Schottky metal is deposited. The Schottky metal region1328is in direct contact with the top of the N− drift layer1304and bridge two adjacent P-well regions1306(i.e. bridges the adjacent unit cells). The Schottky metal region1328is then annealed with a predefined thermal budget for forming a Schottky metal contact between the Schottky metal region1328and the portion of the N− drift layer1304exposed at the top surface of the SiC substrate. In an embodiment, the predefined thermal budget ranges from 55° C. to 1100° C. InFIGS.12d,12e&12f, the first pad metal and the second pad metal formation are performed once the Schottky metal region1328formation is completed.

FIG.14a-14tillustrate an embodiment of a process of manufacturing the DMOSFET structure shown inFIG.12b. The process of manufacturing the DMOSFET structure (shown inFIG.14a) comprises preparing a silicon carbide (SiC) substrate having a N+ substrate1402and a N− drift layer1404as shown inFIG.14a. The N− drift layer1404of the SiC substrate is epi-grown and prepared such that a doping concentration and a thickness of the N− drift layer1404are selected primarily based on blocking voltage and forward conduction loss. The N+ substrate1402is highly conductive when compared to the N− drift layer1404and the N+ substrate1402is directly located under the N− drift layer1404. A first patterned hard mask layer1405is formed on top of the SiC substrate as shown inFIG.14b. The first patterned hard mask layer1405is thick enough for completely blocking high energy impurities during implantation. In an embodiment, the first patterned hard mask layer1405is a hard mask of at least one of oxide, nitride and a polysilicon layer.

A first p-type ion implantation is formed inFIG.14cthrough the first patterned hard mask layer1405to form a p-well region1406. In an embodiment, the first p-type ion implantation is performed with one or more p-type impurities (e.g. aluminum, boron, etc.). In another embodiment, first p-type ion implantation may comprise a screen oxide layer. The first patterned hard mask layer1405is then removed, after the first p-type ion implantation, by at least one of dry etching process and wet etching process as shown inFIG.14d. A second patterned hard mask layer1407is then formed on the top of the SiC substrate as shown inFIG.14efor subsequent ion implantation. The second patterned hard mask layer1407is a photoresist based material and thick enough for preventing any unwanted high energy impurities particles penetrating the second patterned hard mask layer1407. A first n-type ion implantation is formed through the second patterned hard mask layer1407to form a N+ source region1408within the p-well region1406as shown inFIG.14f. In an embodiment, the first n-type ion implantation is performed with one or more n-type impurities (e.g. nitrogen, phosphorous etc.). The second patterned hard mask layer1407is then removed after the first n-type ion implantation by at least one of dry etching and wet etching process as shown inFIG.14g.

A third patterned hard mask layer1409is then formed on top of the SiC substrate as shown inFIG.14h. A second p-type implantation is performed through the third patterned hard mask layer1409to form a P+ region1403, at a second location, within the p-well region1406as shown inFIG.14i.

The third patterned hard mask layer1409is then removed as shown inFIG.14jby at least one of a dry etching and a wet etching process once the P+ region1403is formed at the second location. The SiC substrate undergoes thermal activation annealing with a carbon-based protection coating at a predefined temperature. In an embodiment, the predefined temperature for performing the thermal activation annealing is 1700-degree Celsius. The SiC substrate then may undergo an additional ion implantation for forming a current spreading layer to improve on-state resistance. Ion implantations (e.g. the first p-type implantation, the first n-type impanation, the second p-type implantation, edge termination implantation, current spreading layer implantation etc.) undergone by the SiC substrate is performed prior to the thermal activation annealing step. The carbon-based protection coating is then removed from the SiC substrate. The SiC substrate then undergoes a sacrificial oxide growth and subsequently the sacrificial oxide removal. An active region of the SiC DMOSFET is then patterned by forming and patterning field oxide layer on the SiC substrate.

A gate insulator1414is then formed on top of the SiC substrate as shown inFIG.14k. The gate insulator1414is then patterned as shown inFIG.14l. A polysilicon layer1416is then formed on top of the SiC substrate as shown inFIG.14m. The polysilicon layer1416is then patterned as shown inFIG.14n. Contacts for the polysilicon layer is kept open for pad metal deposition for forming a gate pad region and one or more gate bus regions. An interlayer dielectric (ILD)1418is then formed on top of the SiC substrate as shown inFIG.14o. The interlayer dielectric (ILD)1418is then patterned for exposing the portions of the SiC substrate via the openings of the ILD1418and leaving one or more ILD bumps1417on top of the SiC substrate as shown inFIG.14p. A first silicide layer1420is then formed between the one or more ILD bumps1417on the exposed portions of top of the SiC substrate for forming a first Ohmic contacts as shown inFIG.14q. In an embodiment, the first silicide layer1420is a nickel-based silicide layer. In another embodiment, the nickel-based silicide is formed by Nickel deposition on the top of the SiC substrate, thermal activation annealing of the deposited Nickel for silicide formation, and removal of any un-reacted Nickel from the SiC substrate. A first pad metal1424is formed on top of the SiC substrate as shown inFIG.14r. The P+ region1403, formed at the second location, is under the one or more ILD bumps1417and do not form any direct contact with the first silicide layer1420.

A second silicide layer1422is then formed on bottom of the SiC substrate for forming a second Ohmic contact as shown inFIG.14s. In an embodiment, the second silicide layer1422is then formed on back of the SiC substrate for forming the second Ohmic contact. In an embodiment, the second silicide layer1422is also the nickel-based silicide layer. A second pad metal is then formed on bottom of the second silicide layer1422of the SiC substrate as shown inFIG.14t. In an embodiment, the second pad metal formation is performed by at least one of e-beam and sputtering.

A fourth patterned hard mask layer1411is then formed on the SiC substrate once the first Ohmic contact and the second Ohmic contact are formed on topside and bottom side/back side of the SiC substrate respectively. The fourth patterned hard mask layer1411is formed for selectively removing the exposed portions of the ILD layer1418and depositing a metal region (i.e. a Schottky metal region1428) shown inFIGS.12d,12e&12fon top of the SiC substrate. The fourth patterned hard mask layer1411is used for both etching the portion of the ILD layer1418and lifting off the Schottky metal region1428when Schottky metal is deposited. The Schottky metal region1428is in direct contact with the N− drift layer1404and bridge two adjacent P-well regions1406(i.e. bridges the adjacent unit cells). The Schottky metal region1428is then annealed with a predefined thermal budget for forming a Schottky metal contact between the Schottky metal region1428and the portion of the N− drift layer1404exposed at the top surface of the SiC substrate. In an embodiment, the predefined thermal budget ranges from 55° C. to 1100° C. InFIGS.12d,12e&12f, the first pad metal and the second pad metal formation are performed once the Schottky metal region1428formation is completed.

FIG.15a-15tillustrate an embodiment of a process of manufacturing the DMOSFET structure shown inFIG.12c. The process of manufacturing the DMOSFET structure (shown inFIG.15a) comprises preparing a silicon carbide (SiC) substrate having a N+ substrate1502and a N− drift layer1504as shown inFIG.15a. The N− drift layer1504of the SiC substrate is epi-grown and prepared such that a doping concentration and a thickness of the N− drift layer1504are selected primarily based on blocking voltage and forward conduction loss. The N+ substrate1502is highly conductive when compared to the N− drift layer1504and the N+ substrate1502is directly located under the N− drift layer1504. A first patterned hard mask layer1505is formed on top of the SiC substrate as shown inFIG.15b. The first patterned hard mask layer1505is thick enough for completely blocking high energy impurities during implantation. In an embodiment, the first patterned hard mask layer1505is a hard mask of at least one of oxide, nitride and a polysilicon layer.

A first p-type ion implantation is formed inFIG.15cthrough the first patterned hard mask layer1505to form a p-well region1506. In an embodiment, the first p-type ion implantation is performed with one or more p-type impurities (e.g. aluminum, boron, etc.). In another embodiment, first p-type ion implantation may comprise a screen oxide layer. The first patterned hard mask layer1505is then removed, after the first p-type ion implantation, by at least one of dry etching process and wet etching process as shown inFIG.15d. A second patterned hard mask layer1507is then formed on the top of the SiC substrate as shown inFIG.15efor subsequent ion implantation. The second patterned hard mask layer1507is a photoresist based material and thick enough for preventing any unwanted high energy impurities particles penetrating the second patterned hard mask layer1507. A first n-type ion implantation is formed through the second patterned hard mask layer1507to form a N+ source region1508within the p-well region1506as shown inFIG.15f. In an embodiment, the first n-type ion implantation is performed with one or more n-type impurities (e.g. nitrogen, phosphorous etc.). The second patterned hard mask layer1507is then removed after the first n-type ion implantation by at least one of dry etching and wet etching process as shown inFIG.15g.

A third patterned hard mask layer1509is then formed on top of the SiC substrate as shown inFIG.15h. A second p-type implantation is performed through the third patterned hard mask layer1509to form a P+ region1503, at a third location, within the p-well region1506as shown inFIG.15i.

The third patterned hard mask layer1509is then removed as shown inFIG.15jby at least one of a dry etching and a wet etching process once the P+ region1503is formed at the second location. The SiC substrate undergoes thermal activation annealing with a carbon-based protection coating at a predefined temperature. In an embodiment, the predefined temperature for performing the thermal activation annealing is 1700-degree Celsius. The SiC substrate then may undergo an additional ion implantation for forming a current spreading layer to improve on-state resistance. Ion implantations (e.g. the first p-type implantation, the first n-type impanation, the second p-type implantation, edge termination implantation, current spreading layer implantation etc.) undergone by the SiC substrate is performed prior to the thermal activation annealing step. The carbon-based protection coating is then removed from the SiC substrate. The SiC substrate then undergoes a sacrificial oxide growth and subsequently the sacrificial oxide removal. An active region of the SiC DMOSFET is then patterned by forming and patterning field oxide layer on the SiC substrate.

A gate insulator1514is then formed on top of the SiC substrate as shown inFIG.15k. The gate insulator1514is then patterned as shown inFIG.15l. A polysilicon layer1516is then formed on top of the SiC substrate as shown inFIG.15m. The polysilicon layer1516is then patterned as shown inFIG.15n. Contacts for the polysilicon layer is kept open for pad metal deposition for forming a gate pad region and one or more gate bus regions. An interlayer dielectric (ILD)1518is then formed on top of the SiC substrate as shown inFIG.15o. The interlayer dielectric (ILD)1518is then patterned for exposing the portions of the SiC substrate via the openings of the ILD1518and leaving one or more ILD bumps1517on top of the SiC substrate as shown inFIG.15p. A first silicide layer1520is then formed between the one or more ILD bumps1517on the exposed portions on top of the SiC substrate for forming a first Ohmic contact as shown inFIG.15q. In an embodiment, the first silicide layer1520is a nickel-based silicide layer. In another embodiment, the nickel-based silicide is formed by Nickel deposition on the top of the SiC substrate, thermal activation annealing of the deposited Nickel for silicide formation, and removal of any un-reacted Nickel from the SiC substrate. A first pad metal1524is formed on top of the SiC substrate as shown inFIG.15r. The P+ region1503, formed at the third location, is under the one or more ILD bumps1517and do not form any direct contact with the first silicide layer1520.

A second silicide layer1522is then formed on bottom of the SiC substrate for forming a second Ohmic contact as shown inFIG.15s. In an embodiment, the second silicide layer1522is then formed on back of the SiC substrate for forming the second Ohmic contact. In an embodiment, the second silicide layer1522is also the nickel-based silicide layer. A second pad metal1526is then formed on bottom of the second silicide layer1522of the SiC substrate as shown inFIG.15t. In an embodiment, the second pad metal formation is performed by at least one of e-beam and sputtering.

A fourth patterned hard mask layer1511is then formed on the SiC substrate once the first Ohmic contact and the second Ohmic contact are formed on topside and bottom side/back side of the SiC substrate respectively. The fourth patterned hard mask layer1511is formed for selectively removing the exposed portions of the ILD layer1518and depositing a metal region (e.g. a Schottky metal region1528) shown inFIGS.12d,12e&12fon top of the SiC substrate. The fourth patterned hard mask layer1511is used for both etching the portion of the ILD layer1518and lifting off the Schottky metal region1528when Schottky metal is deposited. The Schottky metal region1528is in direct contact with the N− drift layer1504and bridge two adjacent P-well regions1506(i.e. bridges the adjacent unit cells). The Schottky metal region1528is then annealed with a predefined thermal budget for forming a Schottky metal contact between the Schottky metal region1528and the portion of the N− drift layer1504exposed at the top surface of the SiC substrate. In an embodiment, the predefined thermal budget ranges from 55° C. to 1100° C. InFIGS.12d,12e&12f, the first pad metal and the second pad metal formation are performed once the Schottky metal region1528formation is completed.

The present disclosure may be embodied in other specific forms without departing from its spirit or characteristics. The described embodiments are to be considered in all respects only as illustrative and not restrictive. The scope is, therefore, indicated by the appended claims rather than by the foregoing description. All changes which come within the meaning and range of equivalency of the claims are to be embraced within their scope.

Other embodiments are also within the scope of the following claims.

Although, various embodiments which incorporate the teachings described in detail herein, those skilled in the art can readily devise many other varied embodiments that still incorporate these teachings. For example, a complementary SiC DMOSFET device with a P+ substrate, P− drift layer and P+ source can be created in a N-well region. The embodiments described are all applicable to the complementary DMOSFET as well.

All documents (patents, patent publications or other publications) mentioned in the specification are incorporated herein in their entirety by reference.

INCORPORATION BY REFERENCE

All publications, patents, and patent applications cited in this Specification are hereby incorporated by reference in their entirety, including:WO2011013042A1 entitled “Germanium n-MOSFET Devices and production methods”;EP0899791B1 entitled “Trench-gated MOSFET with bidirectional voltage clamping”;JP2008541459A entitled “Silicon carbide junction barrier Schottky diode with suppressed minority carrier injection”;U.S. Pat. No. 9,875,332 entitled “Contact Resistance Mitigation”;U.S. Pat. No. 5,731,605A entitled “Turn-off power semiconductor component with a particular ballast resistor structure”;U.S. Pat. No. 5,461,250 entitled “SiGe thin film or SOI MOSFET and method for making the same”;U.S. Pat. No. 9,899,512B2 entitled “Silicon Carbide device and method of making thereof”;U.S. Pat. No. 9,876,104B2 entitled “High voltage semiconductor devices and methods of making the devices”;US20190013312A1 entitled “MOSFET device of silicon carbide having an integrated diode and manufacturing process thereof”;U.S. Pat. No. 9,318,597B2 entitled “Layout configurations for integrating Schottky contacts into a power transistor device”; andU.S. Pat. No. 8,436,367B1 entitled “SiC power vertical DMOS with increased safe operating area”.