Patent ID: 12210187

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

Other features and processes may also be included. For example, testing structures may be included to aid in the verification testing of the 3D packaging or 3DIC devices. The testing structures may include, for example, test pads formed in a redistribution layer or on a substrate that allows the testing of the 3D packaging or 3DIC, the use of probes and/or probe cards, and the like. The verification testing may be performed on intermediate structures as well as the final structure. Additionally, the structures and methods disclosed herein may be used in conjunction with testing methodologies that incorporate intermediate verification of known good dies to increase the yield and decrease costs.

FIGS.1A through1Gare various views schematically illustrating a process flow for fabricating waveguide dies100A in accordance with some embodiments of the present disclosure. Referring toFIG.1A, a semiconductor substrate110ais provided. For example, the semiconductor substrate110amay be or may include a bulk silicon substrate, a silicon germanium substrate, or a substrate formed of other semiconductor materials.

Referring toFIG.1AandFIG.1B, the semiconductor substrate110ais patterned to form a plurality of semiconductor pillar portions112ain the semiconductor substrate110a. In some embodiments, the semiconductor substrate110ais patterned by photolithograph/etching process or other suitable patterning processes. As illustrated inFIG.1B, a plurality of trenches TH having a predetermined depth are formed in semiconductor substrate110a, such that a semiconductor base portion114aand the semiconductor pillar portions112aprotruding from the semiconductor base portion114aare formed.

Referring toFIG.1BandFIG.1C, a dielectric layer120ais formed over the semiconductor substrate110ato fill the trenches TH between the semiconductor pillar portions112a. The formation process of the dielectric layer120amay be attained by the following steps. First, a dielectric material (not shown) is formed on the semiconductor substrate110ato cover the semiconductor pillar portions112a. In some embodiments, the dielectric material may entirely cover a top surface of the semiconductor substrate110aand entirely fill the trenches TH. In some embodiments, the dielectric material may be formed by spin coating, chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), lamination or the like. Thereafter, portions of the dielectric material outside the trenches TH are ground to reveal the semiconductor pillar portions112a, so as to form the dielectric layer120a. In some embodiments, the portions of the dielectric material outside the trenches TH are removed by a mechanical grinding process, a chemical mechanical polishing (CMP) process, or other suitable processes. In some embodiments, portions of the semiconductor pillar portions112aare ground as well. After the grinding process, a first surface120S1of the dielectric layer120afacing upward is substantially leveled with the first surfaces112S1of the semiconductor pillar portions112afacing upward. In some embodiments, a material of the dielectric layer120amay include silicon oxide (SiOx, where x>0), silicon nitride (SiNx, where x>0), silicon oxynitride (SiOxNy, where x>0 and y>0) or other suitable dielectric materials.

Referring toFIG.1CandFIG.1D, a bonding layer130ais formed on the semiconductor pillar portions112aand the dielectric layer120ato cover the first surfaces112S1of the semiconductor pillar portions112aand the first surface120S1of the dielectric layer120a. In some embodiments, the bonding layer130amay be formed by spin coating, chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), lamination or the like. In some embodiments, a planarization process, such as a chemical mechanical polishing (CMP) process, is optionally performed on the bonding layer130a. In some embodiments, a material of the bonding layer130amay include silicon oxide, silicon nitride, silicon oxynitride or other suitable dielectric materials.

FIG.1Eis a cross-sectional view of the structure inFIG.1Dalong cross-section A-A in accordance with some embodiments of the present disclosure.FIG.1Dis a cross-sectional view of the structure inFIG.1Ealong the cross-section B-B.FIG.1Gis a cross-sectional view of the waveguide die inFIG.1Falong cross-section C-C in accordance with some embodiments of the present disclosure.FIG.1Fis a cross-sectional view of the waveguide die inFIG.1Galong the cross-section D-D.

Referring toFIG.1DthroughFIG.1G, a sawing process is performed along a scribe line SL1to singulate the semiconductor substrate110a, the dielectric layer120aand the bonding layer130a. The semiconductor substrate110a, the dielectric layer120aand the bonding layer130aare singulated into a plurality of waveguide dies100A. As illustrated inFIG.1F, each singulated waveguide die100A includes a plurality of the semiconductor pillar portions112, a semiconductor base portion114, a dielectric layer120and a bonding layer130. The semiconductor pillar portions112protrude from the semiconductor base portion114and are embedded in the dielectric layer120. The bonding layer130covers the first surfaces11251of the semiconductor pillar portions112and the first surface120S1of the dielectric layer120. As shown inFIG.1DandFIG.1F, the materials and the characteristics of the semiconductor pillar portions112, the semiconductor base portion114, the dielectric layer120and the bonding layer130inFIG.1Fare the same as those of the semiconductor pillar portions112a, the semiconductor base portion114a, the dielectric layer120aand the bonding layer130ainFIG.1D, and the detailed descriptions are omitted therein.

In some embodiments, the dielectric layer120includes a material having a refractive index lower than that of the semiconductor pillar portions112. For example, in an embodiment where the material of the dielectric layer120includes silicon oxide and the material of the semiconductor pillar portions112includes silicon, the refractive index of the dielectric layer120is about 1.4 and the refractive index of the semiconductor pillar portions112is about 3.5. When a radiation is incident into the semiconductor pillar portions112, the incident radiation may be totally internally reflected at the sidewalls of the semiconductor pillar portions112, such that the semiconductor pillar portions112of the waveguide die100A may be used to guide a light from one end of the semiconductor pillar portions112toward another end of the semiconductor pillar portions112. The details will be discussed later.

As illustrated inFIG.1DandFIG.1E, portions of the dielectric layer120aand portions of the semiconductor base portion114aare located in the scribe line regions (the regions of the scribe line SL1). Therefore, as illustrated inFIG.1FandFIG.1G, a sidewall120SW of the dielectric layer120is substantially aligned with a sidewall114SW of the semiconductor base portion114after the sawing process is performed along the scribe line SL1.

Referring toFIG.1FandFIG.1Gagain, the semiconductor pillar portions112may be arranged in array. In some embodiments, the semiconductor pillar portions112from the top view may be respectively shaped as square patterns. In some alternative embodiments, the semiconductor pillar portions of the waveguide die from the top view may be respectively shaped as rectangular patterns or circular patterns. The disclosure does not construe the shape of the semiconductor pillar portions of the waveguide die. As illustrated inFIG.1G, the dielectric layer120may include a mesh portion122and a ring portion124. The semiconductor pillar portions112may be spaced apart from each other by the mesh portion122of the dielectric layer120, and the semiconductor pillar portions112may be encircled by the ring portion124of the dielectric layer120.

In some embodiments, the semiconductor pillar portion112may have a width D1and a length D2. In some embodiments, the width D1and the length D2of the semiconductor pillar portion112may be the same. In some embodiments, the width D1and the length D2of the semiconductor pillar portion112may be different. For example, the length D2of the semiconductor pillar portion112may be about 2 times the width D1of the semiconductor pillar portion112. In some embodiments, the width D1and/or the length D2of the semiconductor pillar portion112may range from about 0.1 micrometer to about 0.2 micrometer, for example. In some embodiments, the semiconductor pillar portions112are spaced apart from one another by a distance D3ranging from about 0.5 micrometer to about 2 micrometers, for example.

FIGS.2A through2Eare various views schematically illustrating a process flow for fabricating waveguide dies100B in accordance with some other embodiments of the present disclosure.FIG.2Cis a cross-sectional view of the structure inFIG.2Balong cross-section A-A in accordance with some embodiments of the present disclosure.FIG.2Bis a cross-sectional view of structure inFIG.2Calong the cross-section B-B.FIG.2Eis a cross-sectional view of the waveguide die inFIG.2Dalong cross-section C-C in accordance with some embodiments of the present disclosure.FIG.2Dis a cross-sectional view of the waveguide die inFIG.2Ealong the cross-section D-D.

The process flow shown inFIGS.2A-2Eis similar to the process flow shown inFIGS.1A-1F, and the waveguide dies100B shown inFIGS.2D and2Eare similar to the waveguide dies100A shown inFIGS.1F and1G, and the detailed descriptions are omitted for the sake of brevity. In some embodiments, the semiconductor pillar portions112of the waveguide dies100B include a plurality of first semiconductor pillar portions112-1arranged in array and a second semiconductor pillar portion112-2encircling the first semiconductor pillar portions112-1, wherein the first semiconductor pillar portions112-1are embedded in the dielectric layer120and are spaced apart from the second semiconductor pillar portion112-2by the dielectric layer120.

Referring toFIG.2A, a semiconductor substrate100ais provided, and the semiconductor substrate110ais patterned to form a plurality of semiconductor pillar portions112ain the semiconductor substrate110a. The semiconductor pillar portions112ainclude a plurality of first semiconductor pillar portions112a-1arranged in array and a second semiconductor pillar portion112a-2encircling the first semiconductor pillar portions112a-1.

Referring toFIG.2AandFIG.2B, a dielectric layer120ais formed over the semiconductor substrate110ato fill the trenches TH between the semiconductor pillar portions112a. Thereafter, a bonding layer130ais formed on the semiconductor pillar portions112aand the dielectric layer120ato cover the first surfaces112S1of the semiconductor pillar portions112aand the first surface120S1of the dielectric layer120a.

Referring toFIG.2BthroughFIG.2D, a sawing process is performed along a scribe line SL2to singulate the semiconductor substrate110a, the dielectric layer120aand the bonding layer130a. The semiconductor substrate110a, the dielectric layer120aand the bonding layer130aare singulated into a plurality of waveguide dies100B. As illustrated inFIG.2D, each singulated waveguide die100B includes the plurality of first semiconductor pillar portions112-1, the second semiconductor pillar portions112-2, the semiconductor base portion114, the dielectric layer120and the bonding layer130. The first semiconductor pillar portions112-1, the second semiconductor pillar portions112-2protrude from the semiconductor base portion114. The bonding layer130covers the first surfaces112S1of the semiconductor pillar portions112and the first surface120S1of the dielectric layer120.

As illustrated inFIG.2BandFIG.2C, portions of the second semiconductor pillar portion112a-2and portions of the semiconductor base portion114aare located in the scribe line regions (the regions of the scribe line SL2). Therefore, as illustrated inFIG.2DandFIG.2E, a sidewall112SW of the second semiconductor pillar portion112-2is substantially aligned with a sidewall114SW of the semiconductor base portion114after the sawing process is performed along the scribe line SL2. As illustrated inFIG.2C, prior to the sawing process, the second semiconductor pillar portion112a-2from the top view may be shaped as a mesh pattern.

Referring toFIG.2DandFIG.2Eagain, the first semiconductor pillar portions112-1may be arranged in array. In some embodiments, the first semiconductor pillar portions112-1from the top view may be respectively shaped as square patterns. In some alternative embodiments, the first semiconductor pillar portions of the waveguide die from the top view may be respectively shaped as rectangular patterns or circular patterns. In some embodiments, the second semiconductor pillar portion112-2from the top view may be shaped as a square-frame pattern. In some alternative embodiments, the second semiconductor pillar portion of the waveguide die from the top view may be shaped as a rectangular-frame pattern or a circular-ring pattern. The disclosure does not construe the shape of the semiconductor pillar portions of the waveguide die. As illustrated inFIG.2E, the dielectric layer120may include a mesh portion122and a ring portion124. The first semiconductor pillar portions112-1may be spaced apart from each other by the mesh portion122of the dielectric layer120, and the first semiconductor pillar portions112-1may be encircled by the ring portion124of the dielectric layer120and spaced apart from the second semiconductor pillar portions112-2by the ring portion124of the dielectric layer120.

FIGS.3A,4A,5A,6through12are cross-sectional views schematically illustrating a process flow for fabricating a package in accordance with some embodiments of the present disclosure.FIGS.3B,4B and5Bare enlarged views of the region X illustrated inFIGS.3A,4A and5A, respectively, in accordance with some embodiments of the present disclosure. In some embodiments, one integrated circuit die is shown to represent plural integrated circuit die of the semiconductor wafer.

Referring toFIG.3AandFIG.3B, a semiconductor wafer200aincluding a plurality of photoelectric integrated circuit dies200is provided. Before a wafer dicing process is performed on the semiconductor wafer200a, the photoelectric integrated circuit dies200are connected to one another. In some embodiments, the semiconductor wafer200aincludes a semiconductor substrate210a, a dielectric layer220aand a waveguide layer230a. In some embodiments, the semiconductor substrate210amay be or may include a bulk silicon substrate, a silicon germanium substrate, or a substrate formed of other semiconductor materials. In some embodiments, the dielectric layer220ais formed over the semiconductor substrate210a, and a material of the dielectric layer220amay include silicon oxide, silicon nitride, silicon oxynitride or other suitable dielectric materials. In some embodiments, the waveguide layer230ais formed over the dielectric layer220a, and is configured for the internal transmission of optical signals. In some embodiments, the waveguide layer230aincludes waveguides (not individually illustrated) and a grating coupler232optically coupled to the waveguides. The grating coupler232may be configured to receive radiation from the overlying light source or optical signal source (such as the optical fiber OF as shown inFIG.12), and transmit the radiation to waveguides. In some embodiments, materials of the waveguides and grating coupler232of the waveguide layer230amay be or may include silicon, or other suitable semiconductor materials. In some embodiments, the photoelectric integrated circuit dies200in the semiconductor wafer200amay include various devices and circuits (not shown) that may be used for processing and transmitting optical signals and/or electrical signals.

In some embodiments, the semiconductor wafer200afurther includes an interconnect structure240aover the waveguide layer230aand through semiconductor vias (TSVs)250electrically connected to the interconnect structure240a. In some embodiments, the interconnect structure240aincludes a dielectric layer241a, an etching stop layer242aover the dielectric layer241a, a dielectric layer243aover the etching stop layer242a, and interconnect wirings244embedded in the dielectric layer243a. In some embodiments, the TSVs250may be formed in the semiconductor substrate210a, the dielectric layer220a, the waveguide layer230aand the interconnect structure240a. In some embodiments, a material of the dielectric layer241aand/or the dielectric layer243amay include silicon oxide, silicon nitride, silicon oxynitride or other suitable dielectric materials. In some embodiments, the dielectric layer243aand the etching stop layer242aare made of different materials. For example, a material of the etching stop layer242amay include silicon carbide, silicon nitride, SiCN, and SiOCN or other suitable dielectric materials. In some embodiments, the interconnect wirings244and/or the TSVs250may be formed of copper, copper alloys or other suitable conductive material.

As illustrated inFIG.3A, the semiconductor wafer200aincludes a front surface (active surface)20051and a rear surface20052opposite to the front surface20051.

Referring toFIG.4AandFIG.4B, a patterned photoresist layer PR including an opening OP may be formed over the interconnect structure240ato partially cover a top surface24351of the dielectric layer243a, wherein the top surface24351of the dielectric layer243ais partially exposed by the opening OP defined in the patterned photoresist layer PR. In some embodiments, the opening OP corresponds to the locations of the grating coupler232of the waveguide layer230a. For example, vertical projections of the openings OP along a direction perpendicular to the front surface (active surface)20051of the f semiconductor wafer200aoverlap with the grating coupler232of the waveguide layer230a. Subsequently, an etching process may be performed by using the patterned photoresist layer PR as a mask, such that an optical window OW directly over the grating coupler232is formed in the dielectric layer243aof the interconnect structure240a. In some embodiments, the optical window OW may extend into the etching stop layer242a. In some embodiments, the optical window OW may allow optical transmission between the photoelectric integrated circuit die200in the semiconductor wafer200aand the external element (e.g., the waveguide die100A/100B).

Referring toFIG.5AandFIG.5B, the patterned photoresist layer PR is removed/stripped through, for example, etching, ashing, or other suitable removal processes. Thereafter, a bonding material (not shown) is formed on the dielectric layer243ato cover the dielectric layer243a. In some embodiments, the bonding material may entirely cover a top surface243S1of the dielectric layer243aand entirely fill the optical window OW. In some embodiments, the bonding material may be formed by spin coating, chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), lamination or the like. Thereafter, portions of the bonding material outside the optical window OW are ground, so as to form a bonding layer260. In some embodiments, the portions of the bonding material outside the optical window OW are removed by a mechanical grinding process, a chemical mechanical polishing (CMP) process, or other suitable processes. After the grinding process, a top surface260S1of the bonding layer260is substantially leveled with the top surface243S1of the dielectric layer243aof the interconnect structure240a. In some embodiments, a material of the bonding layer260may include silicon oxide, silicon nitride, silicon oxynitride or other suitable dielectric materials.

Referring toFIG.5AandFIG.6, the waveguide die100A illustrated inFIGS.1F and1Gis flipped over and pressed onto the bonding layer260of the semiconductor wafer200a, such that the first surfaces112S1of the semiconductor pillar portions112and the first surface120S1of the dielectric layer120faces the front surface200S1of the semiconductor wafer200a, and the bonding layer130of the waveguide die100A is in contact with the bonding layer260of the semiconductor wafer200a. In other words, the semiconductor pillar portions112are between the semiconductor base portion114and the semiconductor wafer200a. A bonding process is performed to bond the waveguide die100A to the semiconductor wafer200athrough fusion bonding, wherein the bonding layer130of the waveguide die100A is bonded with the bonding layer260of the semiconductor wafer200a. In other words, the waveguide die100A are bonded to the semiconductor wafer200athrough the bonding layer130and the bonding layer260. In some embodiments, a width of the waveguide die100A is wider than a width of the bonding layer260of the semiconductor wafer200a. In some alternative embodiments, a width of the waveguide die100A is substantially equal to or less than a width of the bonding layer260of the semiconductor wafer200a.

Referring toFIG.6andFIG.7, an electric integrated circuit die300is provided over the semiconductor wafer200athrough a pick and place process. In some embodiments, the electric integrated circuit die300may be or may include logic dies (e.g., central processing unit, microcontroller, etc.), memory dies (e.g., dynamic random access memory (DRAM) dies, static random access memory (SRAM) dies, etc.), power management dies (e.g., power management integrated circuit (PMIC) dies), radio frequency (RF) dies, micro-electro-mechanical-system (MEMS) dies, signal processing dies (e.g., digital signal processing (DSP) dies), front-end dies (e.g., analog front-end (AFE) dies), system-on-chip (SoC) dies, or combinations thereof. The electric integrated circuit die300may include a semiconductor substrate310and an interconnect structure320over the semiconductor substrate310. In some embodiments, the semiconductor substrate310may be or may include bulk silicon substrate, a silicon germanium substrate, or a substrate formed of other semiconductor materials. In some embodiments, the semiconductor substrate310may include other conductive layers or other semiconductor elements, such as transistors, diodes, resistors, capacitors or the like. In some embodiments, the interconnect structure320is electrically connected to the conductive layers or other semiconductor elements formed in the semiconductor substrate310. The interconnect structure320formed on the semiconductor substrate310may include a dielectric layer322and interconnect wirings324embedded in the dielectric layer322. In some embodiments, a material of the dielectric layer322may include silicon oxide, silicon nitride, silicon oxynitride or other suitable dielectric materials. In some embodiments, the interconnect wirings324may be formed of copper, copper alloys or other suitable conductive material.

As illustrated inFIG.7, the electric integrated circuit die300includes a front surface (active surface)300S1and a rear surface300S2opposite to the front surface200S1. The front surface (active surface)300S1of the electric integrated circuit die300faces the front surface (active surface)200S1of the semiconductor wafer200a, and the rear surface300S2of the electric integrated circuit die300faces up.

In some embodiments, the electric integrated circuit die300is mounted onto and electrically connected to the semiconductor wafer200athrough a plurality of electrical terminals330. The electrical terminals330may be or may include micro bumps, ball grid array (BGA) connectors, solder balls, metal pillars, controlled collapse chip connection (C4) bumps, electroless nickel-electroless palladium-immersion gold (ENEPIG) formed bumps, or the like. Other possible forms and shapes of the electrical terminals330may be utilized according to design requirements. Besides, in some embodiments, an underfill UF may be formed between the electric integrated circuit die300and the semiconductor wafer200aso as to laterally encapsulate the electrical terminals330. The underfill UF may protect the electrical terminals330from fatigue and may enhance bonding reliability between the electric integrated circuit die300and the semiconductor wafer200a. In some alternative embodiments, the formation of the underfill UF may be omitted.

As illustrated inFIG.7, after the electric integrated circuit die300are provided over the semiconductor wafer200a, an encapsulation material410is formed over the semiconductor wafer200ato encapsulate the waveguide die100A and the electric integrated circuit die300. In some embodiments, the encapsulation material410is formed by a molding process to cover the waveguide die100A and the electric integrated circuit die300. For example, the encapsulation material410may be formed by a compression molding process, a transfer molding process, or the like. A curing process is optionally performed to harden the encapsulation material410for optimum protection. In some embodiments, the encapsulation material410includes a base material and filler particles distributed in the base material. In some embodiments, the material of the base material includes epoxy resins, phenolic resins or silicon-containing resins, or the like, and the material of the filler particles includes silica, alumina, zinc oxide, titanium dioxide, or the like. However, in some alternative embodiments, the encapsulation material410is formed by a deposition process, and the encapsulation material410includes silicon oxide, silicon nitride, silicon oxynitride or other suitable dielectric materials.

Referring toFIG.7andFIG.8, the encapsulation material410is then ground to remove the semiconductor base portion144of the waveguide die100A until the semiconductor pillar portions112are revealed, such that an insulating encapsulant400laterally encapsulating the electric integrated circuit die300and the waveguide die100A is formed. In some embodiments, a portion of the encapsulation material410and the semiconductor base portion144of the waveguide die100A are removed by a mechanical grinding process, a chemical mechanical polishing (CMP) process, or other suitable processes. In some embodiments, a portion of the semiconductor substrate310of the electric integrated circuit die300is ground as well. After the grinding process, a top surface100S of the waveguide die100A is substantially leveled with a rear surface300S3of the electric integrated circuit die300and a top surface400S1of the insulating encapsulant400. In some embodiments, a second surface120S2of the dielectric layer120opposite to the first surface120S1and/or a second surface112S2of the semiconductor pillar portions112opposite to the first surface112S1are the top surface100S1of the waveguide die100A may constitute the top surface100S1of the waveguide die100A.

Referring toFIG.8andFIG.9, after the insulating encapsulant400is formed, a recessing process is performed to remove a portion of the insulating encapsulant400, such that a top surface400S2of the recessed insulating encapsulant400is lower than the rear surface300S3of the electric integrated circuit die300and the top surface100S1of the waveguide die100A. In an embodiment where the insulating encapsulant400includes filler particles, a level height offset OS is between the top surface100S1of the waveguide die100A and the top surface400S2of the recessed insulating encapsulant400, such that the incident radiation may not be easily scattered by the filler particles of the insulating encapsulant400, so as to reduce optical noise. In some embodiments, the level height offset OS may be greater than about 10 micrometers.

Referring toFIG.9andFIG.10, the wafer-level package including the semiconductor wafer200a, waveguide die100A, the electric integrated circuit die300and the insulating encapsulant400is flipped over, and a back side grinding process is performed on the rear surface200S2of the semiconductor wafer200ato remove a portion of the semiconductor substrate210aof the semiconductor wafer200auntil bottom surfaces of the TSVs250are revealed. In some alternative embodiments, the semiconductor substrate210aof the semiconductor wafer200amay be ground by a mechanical grinding process, a chemical mechanical polishing (CMP) process, or other suitable processes. After the back side grinding process, bottom surfaces of the TSVs250may be substantially leveled with the rear surface200S3of the semiconductor wafer200a.

After the bottom surfaces of the TSVs250are revealed, a plurality of electrical terminals500may be formed over the rear surface200S3of the semiconductor wafer200ato be electrically connected to the TSVs250of the semiconductor wafer200a. The electrical terminals500may be or may include micro bumps, ball grid array (BGA) connectors, solder balls, metal pillars, controlled collapse chip connection (C4) bumps, electroless nickel-electroless palladium-immersion gold (ENEPIG) formed bumps, or the like. Other possible forms and shapes of the electrical terminals500may be utilized according to design requirements. In some alternative embodiments, the electrical terminals500may be electrically connected to the TSVs250of the semiconductor wafer200athrough a redistribution circuit layer (not shown) between the semiconductor wafer200aand the electrical terminals500. The redistribution circuit layer (not shown) may include a plurality of dielectric layers and a plurality of redistribution layers stacked alternately. The number of the dielectric layers or the redistribution layers is not limited by the disclosure.

Referring toFIG.10andFIG.11, after the electrical terminals500are formed, the wafer-level package including the semiconductor wafer200a, waveguide die100A, the electric integrated circuit die300, the insulating encapsulant400and the electrical terminals500is flipped upside down and is placed on a tape TP.

Referring toFIG.11andFIG.12, a wafer dicing process is performed along a scribe line SL3to singulate the structure mounted on the tape TP. Thereafter, the diced structure is removed from the tape TP to form multiple singulated package structures10. In some embodiments, the wafer dicing process is, for example, a laser cutting process, a mechanical cutting process, or other suitable processes. As illustrated inFIG.12, each singulated package structure10includes the photoelectric integrated circuit die200, the electric integrated circuit die300, the waveguide die100A and an insulating encapsulant400. The electric integrated circuit die300is over and electrically connected to the photoelectric integrated circuit die200. The waveguide die100A is over and optically coupled to the photoelectric integrated circuit die200. The insulating encapsulant400laterally encapsulates the electric integrated circuit die300and the waveguide die100A. In some embodiments, the waveguide die100A includes semiconductor pillar portions112and the dielectric layer114. In some embodiments, the semiconductor pillar portions112are embedded in the dielectric layer114. In some embodiments, the dielectric layer114is in contact with the insulating encapsulant400. As shown inFIG.11andFIG.12, the materials and the characteristics of a semiconductor substrate210, a dielectric layer220, a waveguide layer230and a redistribution structure240of the photoelectric integrated circuit die200inFIG.12are the same as those of the semiconductor substrate210a, the dielectric layer220a, the waveguide layer230aand the redistribution structure240aof the semiconductor wafer200ainFIG.11, and the detailed descriptions are omitted therein.

In some embodiments, the package structure10may be mounted on and electrically coupled to a package component20. The package component20may be or may include a package substrate, a printed circuit board (PCB), a printed wiring board, an interposer, and/or other circuit carrier that is capable of carrying integrated circuits.

In some embodiments, the optical fiber OF optical coupled to the photoelectric integrated circuit die200of the package structure10is disposed over the top surface100S1of the waveguide die100A. The optical fiber OF may be optical coupled to the grating coupler232of the photoelectric integrated circuit die200through the waveguide die100A. As illustrated inFIG.12, the semiconductor pillar portions112of the waveguide die100A extend from the optical fiber OF to the photoelectric integrated circuit die200, such that the semiconductor pillar portions112may guide the light from the optical fiber OF to the grating couplers232of the photoelectric integrated circuit die200and/or the light emitted out of the grating couplers232to the optical fiber OF. It is appreciated that the configuration of the optical fiber OF shown inFIG.12is schematic, and in some embodiments, a coupler (not shown) may be used to secure the optical fiber OF on the waveguide die100A, and the coupler and the optical fiber OF may be attached to the waveguide die100A through adhesive films, such as optical clear adhesive or other suitable optical glue/grease.

FIG.13is a cross-sectional view schematically illustrating a package in accordance with some other embodiments of the present disclosure. InFIG.13, a package structure30is similar to the package structure20shown inFIG.12, and the processes for forming the package structure30are similar to the processes for forming the package structure20, so the detailed descriptions are omitted for the sake of brevity. In some embodiments, the electric integrated circuit die300is bonded to the photoelectric integrated circuit die200through hybrid bonding, wherein the dielectric layer322of the electric integrated circuit die300are bonded with the dielectric layer243of the photoelectric integrated circuit die200, and metallic bonding pads326of the electric integrated circuit die300are bonded with metallic bonding pads245of the photoelectric integrated circuit die200. The metallic bonding pads326of the electric integrated circuit die300are embedded in the dielectric layer322of the interconnect structure320, and the metallic bonding pads245of the photoelectric integrated circuit die200are embedded in the dielectric layer243of the interconnect structure240. In detail, the dielectric layer322of the electric integrated circuit die300and the dielectric layer243of the photoelectric integrated circuit die200are bonded by dielectric-to-dielectric bonding, while the metallic bonding pads326of the electric integrated circuit die300and the metallic bonding pads245of the photoelectric integrated circuit die200are bonded by metal-to-metal bonding.

Besides, in an embodiment where the insulating encapsulant400includes oxide-based materials and does not includes filler particles, the top surface400S1of the insulating encapsulant400may be substantially leveled with the top surface100S of the waveguide die100A and the rear surface30053of the electric integrated circuit die300. For example, the recessing process of the insulating encapsulant400may be omitted.

FIG.14is a cross-sectional view schematically illustrating a package in accordance with some other embodiments of the present disclosure. InFIG.14, a package structure40is similar to the package structure30shown inFIG.13, and the processes for forming the package structure40are similar to the processes for forming the package structure30, so the detailed descriptions are omitted for the sake of brevity. In some embodiments, the waveguide die100A may be replaced by the waveguide die100B illustrated inFIGS.2D and2E. In some embodiments, the waveguide die100B includes the plurality of semiconductor pillar portions112and a dielectric layer114. In some embodiments, the semiconductor pillar portions112include the plurality of first semiconductor pillar portions112-1arranged in array and the second semiconductor pillar portion112-2encircling the first semiconductor pillar portions112-1, wherein the first semiconductor pillar portions112-1are embedded in the dielectric layer120and are spaced apart from the second semiconductor pillar portion112-2by the dielectric layer120. In some embodiments, the second semiconductor pillar portion112-2is in contact with the insulating encapsulant400.

FIGS.15through18are cross-sectional views schematically illustrating a process flow for fabricating a package in accordance with some other embodiments of the present disclosure. In some embodiments, one integrated circuit die is shown to represent plural integrated circuit die of the semiconductor wafer.

In some embodiments, a package structure50inFIG.18may be manufactured by performing processes similar to the steps illustrated inFIG.3AtoFIG.12except the alteration of the steps of forming the waveguide die. That is, the steps illustrated inFIG.6toFIG.12may be replaced by the steps illustrated inFIG.15toFIG.18.

Referring toFIG.15, the steps illustrated inFIGS.3A,4B and5Amay be performed. Thereafter, the electric integrated circuit die300and a semiconductor substrate110are provided over the semiconductor wafer200a. In some embodiments, the semiconductor substrate110is bonded to the semiconductor wafer200athrough the bonding layer130which is formed on the semiconductor substrate110. In some embodiments, the semiconductor substrate110may be or may include a bulk silicon substrate, a silicon germanium substrate, or a substrate formed of other semiconductor materials. In some embodiments, the electric integrated circuit die300is bonded to the semiconductor wafer200athrough hybrid bonding, wherein the dielectric layer322of the electric integrated circuit die300are bonded with the dielectric layer243aof the semiconductor wafer200a, and metallic bonding pads326of the electric integrated circuit die300are bonded with metallic bonding pads245of the semiconductor wafer200a.

Referring toFIG.15andFIG.16, after the electric integrated circuit die300and the semiconductor substrate110are provided over the semiconductor wafer200a, an encapsulation material is formed over the semiconductor wafer200ato encapsulate the semiconductor substrate110and the electric integrated circuit die300. Thereafter, the encapsulation material is then ground until the electric integrated circuit die300and the semiconductor substrate110are revealed, such that an insulating encapsulant400laterally encapsulating the electric integrated circuit die300and the semiconductor substrate110is formed. In some embodiments, a portion of the encapsulation material is removed by a mechanical grinding process, a chemical mechanical polishing (CMP) process, or other suitable processes. In some embodiments, a portion of the semiconductor substrate310of the electric integrated circuit die300and a portion of the semiconductor substrate110are ground as well. After the grinding process, a top surface1101S of the semiconductor substrate110is substantially leveled with a rear surface300S3of the electric integrated circuit die300and a top surface400S1of the insulating encapsulant400.

Referring toFIG.16andFIG.17, after the insulating encapsulant400is formed over the semiconductor wafer200a, the semiconductor substrate110is patterned to form a waveguide die100C including a plurality of semiconductor pillar portions112. The semiconductor pillar portions112include a plurality of first semiconductor pillar portions112-1arranged in array and a second semiconductor pillar portion112-2encircling the first semiconductor pillar portions112-1. In some embodiments, the waveguide die100C inFIG.17is similar to the waveguide die100B inFIGS.2D and2E, except that the dielectric layer120of the waveguide die100B inFIGS.2D and2Eis replaced by, for example, air gaps AG. That is, the first semiconductor pillar portions112-1may be spaced apart from each other by the air gaps AG, and the first semiconductor pillar portions112-1may be spaced apart from the second semiconductor pillar portions112-2by the air gaps AG. In some embodiments, the semiconductor substrate110is patterned by photolithograph/etching process or other suitable patterning processes.

Referring toFIG.17andFIG.18, after the semiconductor pillar portions112of the waveguide die100C are formed, the process similar to the steps illustrated inFIGS.10to12may be repeated to obtain a package structure50mounted on the package component20. In some embodiments, the package structure50inFIG.18is similar to the package structure40inFIG.14, except that the dielectric layer120of the waveguide die100B inFIG.14is replaced by, for example, air gaps AG, so the detailed descriptions are omitted therein.

In view of the above, in some embodiments of the disclosure, by disposing the waveguide die in the insulating encapsulant to guide the light transmitted between the photoelectric integrated circuit die and the overlying light source or optical signal source (e.g., optical fiber), lower optical loss may be achieved. The optical performance is accordingly improved.

In accordance with some embodiments of the disclosure, a structure adapted to optical coupled to an optical fiber includes a photoelectric integrated circuit die, an electric integrated circuit die, a waveguide die and an insulating encapsulant. The electric integrated circuit die is over and electrically connected to the photoelectric integrated circuit die. The waveguide die is over and optically coupled to the photoelectric integrated circuit die, wherein the waveguide die includes a plurality of semiconductor pillar portions extending from the optical fiber to the photoelectric integrated circuit die. The insulating encapsulant laterally encapsulates the electric integrated circuit die and the waveguide die.

In accordance with some embodiments of the disclosure, a method includes the following steps. An electric integrated circuit die and a waveguide die are provided over a photoelectric integrated circuit die, wherein the waveguide die includes a semiconductor base portion and a plurality of semiconductor pillar portions protruding from the semiconductor base portion, and the plurality of semiconductor pillar portions are between the semiconductor base portion and the photoelectric integrated circuit die. An encapsulation material is formed over the photoelectric integrated circuit die to encapsulate the electric integrated circuit die and the waveguide die. The encapsulation material and the waveguide die are ground to remove the semiconductor base portion until the plurality of semiconductor pillar portions are revealed, such that an insulating encapsulant laterally encapsulating the electric integrated circuit die and the waveguide die is formed.

In accordance with some embodiments of the disclosure, a method includes the following steps. An electric integrated circuit die and a semiconductor substrate are provided over a photoelectric integrated circuit die. An encapsulation material is formed over the photoelectric integrated circuit die to encapsulate the electric integrated circuit die and the semiconductor substrate. The semiconductor substrate is patterned to form a waveguide die including a plurality of semiconductor pillar portions.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.