Patent ID: 12191861

DETAILED DESCRIPTION

This description relates to delay correction for on-time generator circuitry, such as can be implemented in power converters.

As an example, a circuit includes a voltage-to-current converter configured to provide a current responsive to an input voltage, and the current is used to charge a capacitor and provide a capacitor voltage. The capacitor can be discharged by a discharge switch to rapidly decrease the capacitor voltage responsive to a comparator signal. Thus, the capacitor voltage provides a ramp signal responsive to charging and discharging the capacitor. The circuit includes a comparator configured to provide the comparator output signal to control the discharge switch responsive to the capacitor voltage and a reference voltage (e.g., proportional to an output voltage). The comparator can introduce a propagation delay that adds time to the on-time, which can result in significant error in the operating frequency of associated circuitry that uses the on-time provided by the comparator output signal.

To compensate for the delay introduced by the comparator, the on-time generator circuit includes a delay correction circuit. The delay correction circuit can be implemented as a feedback loop within the on-time generator configured to adjust the capacitor voltage to cause the ramp signal to cross the reference voltage at a time that is aligned with when the comparator trips (e.g., a state change in the comparator output signal). For example, the delay correction circuit includes a sample-hold circuit configured to sample a voltage across the capacitor responsive to the comparator output signal and provide a voltage signal representative of the sampled capacitor voltage. By sampling when the comparator triggers, the voltage across the capacitor is representative of a voltage adapted to trigger the comparator based on the reference voltage. An amplifier is configured to provide an amplifier output signal responsive to the sampled voltage signal and the reference voltage. The delay correction circuit also includes a variable resistor (e.g., a transistor) configured to provide a resistance between the capacitor and a ground terminal that is responsive to the amplifier output signal. The voltage across the variable resistor is thus configured to adjust (e.g., introduce a voltage shift in) the capacitor voltage to compensate for the turn-on delay, which the comparator introduces into the comparator output signal.

As a result, associated circuitry (e.g., power converter or other circuits) using the comparator output as an on-time generator can exhibit improved operation over a range of voltages and frequencies. Also, because the delay correction circuit can neutralize the delay of the comparator, less complicated circuitry (e.g., smaller and less expensive) can be used to implement the comparator. Additionally, because the delay correction circuit is self-adjusting during operation, additional trimming of the circuitry is not required.

FIG.1is a block diagram of a circuit100that includes on-time generator circuitry (also referred to as an on-time generator)102. For example, the on-time generator102has an output104coupled to an input of modulation logic106. The on-time generator102is configured to provide an output signal, which the modulation logic106uses to control the on-time of a modulated output signal provided by the modulation logic. As described herein, the circuit100also includes a delay correction circuit108configured (e.g., as a feedback loop) to compensate for (e.g., neutralize) a time delay introduced by the on-time generator in producing the output signal at104. The delay correction circuit108can be considered as part of the on-time generator102.

In the example ofFIG.1, the on-time generator102includes a voltage-to-current converter110having a converter input coupled to an input voltage terminal112. The voltage-to-current converter110also has a converter output114and is configured to provide a current (I) proportional to an input voltage VIN received at112. Thus, the current can vary responsive to changes in the input voltage VIN. A capacitor C1has first and second capacitor terminals116and118, in which the first capacitor terminal116is coupled to converter output114. A variable resistor120of the delay correction circuit108is coupled between the second capacitor terminal118and a ground terminal122. A discharge switch124is coupled between the converter output114and the ground terminal122in parallel with the circuit path provided by the capacitor C1and resistor120. The path through the switch and the path through the capacitor C1and the resistor120thus provide alternative current paths for the current I. The switch124can be implemented as a semiconductor or other type of switching device, such as a transistor (e.g., field effect transistor (FET), bipolar junction transistor (BJT)), a thyristor or the like.

A comparator125has first and second comparator inputs126and128and a comparator output130. The first comparator input126is coupled to the converter output114(also coupled to the first capacitor terminal116) and receives a ramp voltage signal VRAMP provided responsive to charging and discharging the capacitor C1. The second comparator input128is coupled to a reference voltage terminal adapted to receive a reference voltage VREF. For example, VREF is proportional to an output voltage VOUT provided by the circuit100at an output132of the circuit (e.g., VREF=αVOUT, where α is a proportionality constant). The comparator125is configured to provide a comparator output signal COMP_OUT at the comparator output130responsive to the signals VRAMP and VREF at the comparator inputs126and128.

The on-time generator102also includes capacitor discharge logic134configured to control discharging of the capacitor C1. The capacitor discharge logic134has inputs136and138and an output140. The input136is coupled to the comparator output130and the input138is coupled to an output of a control loop142, which is configured to provide a TRIGGER signal. The comparator output130is also coupled to the output104of the on-time generator102, which is also coupled to the input of the modulation logic106. The capacitor discharge logic134is configured to provide a control signal at140to a control input of the switch124responsive to the COMP_OUT and TRIGGER signals at136and138. For example, charging and discharging of the capacitor C1provides the ramp signal VRAMP at the comparator input126. As described herein, the comparator125introduces a delay

The delay correction circuit108includes a sample-hold circuit144having first and second sample inputs146and148, a control input149and a hold output150. The first sample input146is coupled to the first capacitor terminal116and the second sample input148is coupled to the second capacitor terminal118. The control input149is coupled to the comparator output130. The sample-hold circuit144is configured to control sampling a voltage across the capacitor C1responsive to the COMP_OUT signal and provide an output signal at150representative of the sampled voltage across C1.

An amplifier152has first and second amplifier inputs154and156and an amplifier output158. The first amplifier input154is coupled to the hold output150and the second amplifier input156is coupled to the reference voltage terminal to receive the reference voltage VREF (e.g., also coupled the second comparator input128). The amplifier152is configured to provide an amplifier output signal at the amplifier output158responsive to the sampled voltage signal at150and the reference voltage VREF. The variable resistor120is configured to provide a resistance (between the second capacitor terminal and ground) responsive to the amplifier output signal at158. The variable resistor120is configured to adjust the voltage at the first capacitor terminal116to enable the comparator125to provide COMP_OUT to trip (e.g., change states) more precisely at a time when the voltage across C1(e.g., between terminals116and118) crosses VREF. The delay correction circuit108thus can provide a feedback loop for the on-time generator102to compensate for the propagation time delay of the comparator125. Advantageously, as a result of using the delay correction circuit, less complicated comparator designs having a smaller area can be used in the circuit100to achieve comparable or better performance than existing approaches. The area overhead by adding the delay correction circuit is small compared to the area saved by using a smaller, less complicated instance of the comparator125.

The modulation logic106is configured to provide a modulated output signal at an output160responsive to the COMP_OUT and TRIGGER signals. Because the on-time in the COMP_OUT signal is adjusted to remove the time delay of the comparator125, the modulated signal at160likewise can be free of the effects of the comparator time delay. A drive circuit162has an input coupled to the output160configured to provide one or more drive signals to respective input(s) of an output circuit164responsive to the modulated signal. In an example, the modulation logic is pulse-width-modulation (PWM) logic configured to provide a PWM output to the drive circuit162. The drive circuit162is configured to provide drive signals to respective power transistors of the output circuit164, which provides the output voltage VOUT at132. As a result of implementing the delay correction circuit108, the output voltage VOUT exhibits significantly less switching frequency variation over a range of output voltages compared to circuits using existing on-time generator circuitry. The circuit100(or at least a portion thereof) can be implemented as an integrated circuit (IC). In one example, the IC includes the components of the on-time generator102and the delay correction circuit108. Additionally, or as an alternative, the IC can include the control loop142, the modulation logic106, and the drive circuit162. As yet another alternative, the IC can include the output circuit164, such as power transistors.

FIG.2is a circuit diagram showing an example on-time generator circuit200. The circuit200provides a useful example of circuitry102,106and108shown inFIG.1. Accordingly, the description ofFIG.2also refers toFIG.1. The circuit200includes a voltage-to-current converter110configured to provide current I2, which is proportional to input voltage VIN, for charging a capacitor C1. In the example ofFIG.2, the voltage-to-current converter110includes a divider circuit that includes resistors R1and R2coupled in series between an input voltage terminal112and a ground terminal122. The divider circuit is configured to provide a voltage at a non-inverting input202of an operational amplifier204proportional to VIN, such as β*VIN, where

β=R⁢1R⁢1+R⁢2.
The op-amp204has an output206coupled to a gate of a transistor M1, which is coupled between the drain of a diode-connected transistor M2and a resistor R3. An inverting input208of op-amp204is coupled to the source of M1(e.g., at a node interconnecting R3and M1).

The op-amp204is configured to control M1to provide current I1through a path that includes R3responsive to the voltages at inputs202and208. The current I1is proportional to VIN

(e.g.,I⁢1=β*VINR⁢3).
The gate and source of M2are coupled to the gate and source, respectively, of transistor M3to provide a current mirror, in which the sources of M2and M3are coupled to a voltage terminal210. The current mirror is configured to provide current I2at the drain of M3, which is coupled to a first terminal of capacitor C1. The current I2can be proportional or equal to the current I1depending on a current mirror ratio between M2and M3. As described herein, the terminal116of C1is coupled to the inverting input of comparator125and thus configured to provide a ramp voltage responsive to charging and discharging of C1.

The comparator125is configured to provide a comparator output signal COMP_OUT at the comparator output130responsive to VRAMP and a reference voltage VREF. Capacitor discharge logic134has inputs configured to receive the COMP_OUT and TRIGGER signals. The capacitor discharge logic134includes a delay circuit (RST DELAY)212having an input coupled to the comparator output130. The delay circuit212is configured to impose a time delay on COMP_OUT and provide the delayed COMP_OUT to an input of an inverter214, which is coupled to a set input of an SR flip-flop216. An input of another inverter218receives the TRIGGER signal and is configured to provide an inverted trigger to a reset input of the flip-flop216. A Q output of the flip-flop216is coupled to a control input of switch124, which is coupled between capacitor terminal116and ground terminal122. The capacitor discharge logic134is thus configured to control the switch124to discharge capacitor C1responsive to the COMP_OUT and TRIGGER signals.

In the example ofFIG.2, the modulation circuit106is a PWM modulator. The PWM modulator includes an inverter219having an input coupled to the comparator output130. The PWM modulator also includes an SR flip-flop221having a reset input coupled to an output of the inverter219and a reset input configured to receive a TRIGGER signal (e.g., from control loop circuitry142). The flip flop221is configured to provide a PWM output signal at the output160(e.g., the Q output of the flip flop) responsive to the TRIGGER signal and an inverted version of the COMP_OUT signal.

The sample-hold circuit144configured to sample the voltage across C1(e.g., between capacitor terminals116and118) responsive to COMP_OUT and provide a voltage signal at the hold output representative of the sampled voltage. InFIG.2, the sample-hold circuit144includes a sample-hold control circuit220configured to control the sampling and holding functions of the sample-hold circuit responsive to the COMP_OUT signal. For example, the sample-hold control circuit220is configured to provide a clock signal, shown as CLK_SAMP, to activate the sampling function and another clock signal, shown as CLK_HOLD, to activate the holding function. The sample-hold control circuit220provides the CLK_SAMP and CLK_HOLD signals so the sampling and holding functions of the sample-hold circuit144do not overlap.

In the example ofFIG.2, the sample-hold circuit144includes a sample capacitor C_SAMP having third and fourth capacitor terminals222and224, and a hold capacitor C_HOLD having fifth and sixth capacitor terminals226and228. A switch230is coupled between capacitor terminals116and222, and another switch232is coupled between capacitor terminals118and224. The switches230and232are thus configured to couple C_SAMP across C1to sample the capacitor voltage responsive to the CLK_SAMP signal. A switch234is coupled between capacitor terminals226and222, and another switch236is coupled between capacitor terminals switches224and228. The switches234and236are configured to couple C_HOLD across C_SAMP to transfer the sampled voltage to C_HOLD responsive to the CLK_HOLD signal. The switches230,232,234and236can be implemented as a semiconductor or other type of switching device, such as a transistor (e.g., FET or BJT), a thyristor or the like.

The amplifier152has an inverting input154coupled to the capacitor terminal226and configured to receive the sampled voltage across C_HOLD. The inverting input156of the amplifier152is configured to receive VREF. As described herein VREF can be proportional to an output voltage VOUT, such as responsive a proportionality constant depending on a ratio of components in a divider circuit used to provide VREF. The amplifier is configured to provide an amplifier output signal at the amplifier output158responsive to the sampled voltage at226and VREF. In the example ofFIG.2, a compensation capacitor C_COMP is coupled between the amplifier output158and ground.

Also, inFIG.2, the variable resistor is implemented as a field transistor M4. M4is shown as a FET. In other examples, M4could be implemented using another transistor technology (e.g., BJT) or another type of variable resistor. The amplifier is configured to provide the amplifier output signal at158to control M4in its linear mode responsive to the voltage signal at154and VREF. The delay correction circuit108provides a feedback loop configured to cooperate with a main control loop (e.g., control loop142) and adjust VRAMP so the comparator125trips when the voltage across C1crosses VREF. As a result, the propagation time delay of the comparator125is effectively compensated or neutralized.

FIG.3is signal diagram300showing examples of signals302,304,306,308and310provided in the on-time generator circuit ofFIG.2. The signal302is representative of the TRIGGER signal, such as a periodic pulse signal provided by the control loop142. The signal304is representative of VREF, which can be provided as a feedback signal representative of an output voltage. The signal306is representative of VRAMP provided responsive to charging and discharging of C1as adjusted by the delay correction circuit108over time. The signal308is representative of COMP_OUT provided by the comparator125, and the signal310is representative of the PWM signal generated by the modulation logic106responsive to COMP_OUT and TRIGGER signals302and308, respectively. As shown inFIG.3a time delay TD is representative of a propagation time delay between VRAMP signal306crossing VREF304and the COMP_OUT going low. As described herein, the delay correction circuit108is configured to adjust the resistance of the variable resistor120(over a number of cycles) to provide corresponding adjustments in VRAMP306to align the crossing VRAMP with when the comparator is activated (e.g., to change from high to low voltage states), as shown by dotted lines312. As a result of removing the time delay TD from COMP_OUT signal308, the on-time TON of the PWM signal310is likewise adjusted and thus omits the propagation time delay.

FIG.4is a time-domain plot400showing examples of signals in the circuit ofFIG.2over a number of cycles. The plot400includes signal402representative of the voltage at158applied to the gate of M4, showing an initial large value, which decreases over time to control the resistance of M4. Signal404is representative of the voltage at118(e.g., also representative of the drain voltage of M4) remains near 0 V. The plot also includes signals406and408representative of sampled voltage at154and VREF, respectively, showing how the delay correction circuit108forces the sampled voltage at154(representative of the voltage across C1) to VREF over a number of cycles and remain at VREF during operation.FIG.5is a plot500of voltage over time showing zoomed-in portion of waveforms, shown at410, fromFIG.4.

FIG.6is a time-domain plot600showing examples waveforms for signals for circuit ofFIG.2responsive to tripping the comparator125in the circuit ofFIG.2. The plot includes a signal602representative of VRAMP (at input126of comparator125) and a signal604representative of the voltage across C1. The plot also includes a signal606representative of VREF and a signal608representative of COMP_OUT. The plot600shows the respective signals for a time interval after the delay correction circuit108has operated over a number of cycles to neutralize the propagation time delay of the comparator125. As shown inFIG.6, the comparator trips (e.g., changes from high to low voltage states) at time when the signal604crosses the signal606.

FIG.7is a schematic block diagram of an example power converter circuit700. For example, the circuit700can be implemented as a buck, boost, buck-boost or other converter topology. The power converter circuit700provides an example of the circuit100ofFIG.1. Accordingly, the description ofFIG.7also refers toFIG.1. The converter circuit includes a control loop142configured to control operation of the converter circuit. The control loop142includes an amplifier702having inputs704and706and configured to receive a reference input voltage VRI and a feedback voltage VFB. For example, VRI is set to a voltage to enable the circuit700to provide a desired output voltage VOUT at the power converter output132. VFB can be a scaled (e.g., divided down) voltage representative of VOUT at132, such as provided by a divider circuit of resistors R4and R5coupled between the output132and ground terminal122. The amplifier702is configured to provide an amplified error signal at an amplifier output708based on a difference between VRI and VFB.

A controller710is configured to maintain the voltage VOUT and/or current at the output at132, which can be under varying load and input conditions. For example, the controller710is configured as a proportional compensator, a proportional-integral (PI) compensator or a proportional-integral-derivative (PID) compensator, such as to tune the gain and/or phase of the converter circuit700. The controller710is configured to provide a control signal at an output712thereof to a non-inverting input of a summing comparator714. The comparator714also receives a filtered ramp signal at an inverting input716. For example, the control loop142includes a ramp generator718configured to provide a ramp signal and a filter (e.g., a high-pass filter)720is configured to remove low-frequency components and provide the filter ramp signal at716. The comparator is configured to provide a TRIGGER pulse signal at722responsive to the control signal at712and the ramp signal at716.

An on-time generator102has an input coupled to the output of the comparator714to receive the TRIGGER signal. The on-time generator102also has an output130coupled to an input of modulation logic106, which is implemented as PWM logic in the example ofFIG.7. The logic106also has another input coupled to the output of the comparator714to receive the TRIGGER signal. As described herein, the on-time generator102includes a comparator configured to provide a COMP_OUT signal at130, which includes a propagation time delay associated with operation of timing circuitry of the on-time generator. The on-time generator thus can include a delay correction circuit108configured to compensate for error introduced by such time delay, such as described herein. As a result, the modulation logic106is configured to provide a PWM output signal to driver circuit162responsive to the corrected COMP_OUT signal and the TRIGGER signal. Advantageously, the on-time of the PWM signal can be provided without effect (e.g., due to compensation) of the propagation time delay variation that otherwise can occur in existing circuits.

The driver circuit162has outputs724and726coupled to inputs of an output circuit164. For example, the output circuit164includes transistors (e.g., power FETs) M5and M6coupled between input voltage terminal112and the ground terminal122, and outputs724and726are coupled to respective gates of M5and M6. The source of M5and drain of M6are coupled to a switching output728of the output circuit164. M5and M6are configured to provide a switching voltage signal VSW at728responsive to the drive signals at724and726. An inductor L1is coupled between the switching output728and the output132, and an output capacitor COUT is coupled between the output132and the ground terminal122. A load, shown as resistor RLOAD, can also be coupled to the output132. The converter is configured to provide the output voltage VOUT at132for providing power to the load (RLOAD).

FIG.8is a diagram800showing plots802and804switching frequency as a function of output voltage (VOUT) showing frequency variation for simulation results of different power converter circuits. The frequency plot802shows frequency variation over a range of output voltages for a power converter implemented using an existing on-time generator circuit. The frequency plot804shows frequency variation over the range of output voltages for a power converter700implemented using the on-time generator102and delay correction circuit108, as described herein. The plot802for the existing approach has switching frequency variation of about 13% compared to about 4% for the plot804. Thus, using an on-time generator with delay correction, as described herein can reduce switching frequency variation over a range of output voltages. As an example, referring toFIGS.2and7, switching frequency (FSW) can be expressed as follows:

FSW=VOUT/VINTON=1α*R⁢3*C⁢1β+VINVOUT*(TD-RM⁢4*C⁢1)where: α is a proportionality constant for VREF (e.g., VREF=α*VOUT);β is a proportionality constant for the voltage at202ofFIG.2(e.g., voltage at 200=β*VIN); andRM4is the resistance of variable resistor120.
Thus, by dynamically setting the resistance of RM4so TD=RM4*C1, the propagation time delay TD that manifests in the on-time of the PWM signal can be neutralized.

While the examples herein focus on reducing timing errors in power converter circuits, the approach described here is equally applicable to any current-charging capacitor-based timing circuits, such as oscillators (e.g., relaxation oscillators). Additionally, the approach described herein can enable opportunities for making small-area comparators (e.g., comparator125) with large delay variations (as well as delay variations due to any following circuits), as the delay correction circuit described here can be configured to correct for such combination of delays. Because the delay correction circuit can operate dynamically to compensate for delay errors according to operating conditions, the approach can afford immunity from process variations and temperature variations that might affect operation. Because the delay correction circuit is self-adjusting in the approach described herein, setting trim resistors and testing can be eliminated unlike many existing designs.

In this description, the term “based on” means based at least in part on.

In this description, the term “couple” may cover connections, communications, or signal paths that enable a functional relationship consistent with this description. For example, if device A generates a signal to control device B to perform an action: (a) in a first example, device A is coupled to device B by direct connection; or (b) in a second example, device A is coupled to device B through intervening component C if intervening component C does not alter the functional relationship between device A and device B, such that device B is controlled by device A via the control signal generated by device A.

Also, in this description, a device that is “configured to” perform a task or function may be configured (e.g., programmed and/or hardwired) at a time of manufacturing by a manufacturer to perform the function and/or may be configurable (or reconfigurable) by a user after manufacturing to perform the function and/or other additional or alternative functions. The configuring may be through firmware and/or software programming of the device, through a construction and/or layout of hardware components and interconnections of the device, or a combination thereof. Furthermore, a circuit or device described herein as including certain components may instead be configured to couple to those components to form the described circuitry or device. For example, a structure described as including one or more semiconductor elements (such as transistors), one or more passive elements (such as resistors, capacitors, and/or inductors), and/or one or more sources (such as voltage and/or current sources) may instead include only the semiconductor elements within a single physical device (e.g., a semiconductor die and/or integrated circuit (IC) package) and may be configured to couple to at least some of the passive elements and/or the sources to form the described structure, either at a time of manufacture or after a time of manufacture, such as by an end user and/or a third party.

Modifications are possible in the described embodiments, and other embodiments are possible, within the scope of the claims.