Patent ID: 12216602

The same reference numbers or other reference designators are used in the drawings to designate the same or similar (functionally and/or structurally) features.

DETAILED DESCRIPTION

The drawings are not necessarily to scale.

Universal serial bus (USB) communication is configured to communicate serial data between a primary USB device and a secondary USB device across a differential data BUS using a USB communication protocol. The speed of the USB transmission is determined based on an operation mode, such that each operation mode corresponds to a different transmission speed. A USB device may include circuitry capable of low-speed (LS) mode, full speed (FS) mode, and/or high-speed (HS) mode. In some example applications, the USB device may transition from one mode to another mode as a result of determining another USB device is capable of a different USB communication mode. For example, the primary device may transition from full speed mode to high-speed mode as a result of determining the secondary device is capable of high-speed mode.

Typically, USB devices are configured to begin USB communication operations in full speed mode. The USB device may enter a state (e.g., a reset state, a suspend state, etc.) to indicate a transition to a different operation mode as a result of the primary device determining that the secondary device includes circuitry to support a different operation mode. For example, the primary device can enter a reset state, wherein the primary device enables circuitry to pulldown the differential data BUS and/or by driving the differential data BUS to a logic low, to indicate to the secondary device that the primary device is capable of high-speed mode. In some such examples, the secondary device can determine whether or not the primary device has enabled circuitry to pulldown the differential BUS as a result of determining the voltage of the differential data BUS is approximately equal to a first chirp voltage after enabling circuitry to supply a test current to the differential data BUS. The USB communication between the primary device and secondary device finishes the reset state and begins to operate in high-speed mode as a result of the primary device determining the differential data BUS is approximately equal to a second chirp voltage. Alternatively, the secondary device may determine that the voltage of the differential data BUS is approximately equal to a voltage supply to indicate that the primary device is not attempting to enter high-speed.

A USB repeater is an example USB device configured to be placed between a primary device and a secondary device without adversely affecting the speed or quality of the data transmission of the USB communication system. In some applications, USB repeaters are configured to replicate the operation of both the primary device and the secondary device, such that the USB repeater must be able to indicate the operation mode of the primary device to the secondary device. USB repeaters operable in LS mode, FS mode, and/or HS mode, are designed to determine the state of the primary device based on the differential data BUS. The USB repeater replicates the operation mode of the primary device by enabling or disabling circuitry to pulldown the differential data BUS coupled between the USB repeater and the secondary device before the secondary device enables circuitry to pullup the differential data BUS to determine the operation mode of the primary device.

A USB repeater can be configured to replicate the operation mode of the primary device by determining whether or not the primary device has enabled or disabled pulldown circuitry. The USB repeater replicates the state of the primary device pulldown circuitry before the secondary device attempts to determine the mode of the primary device. For example, the USB repeater can determine the difference between a high-speed reset and a full speed suspend state before the secondary device measures the differential data BUS for a chirp voltage. A USB repeater may determine and replicate the mode of the primary device by including a precision clock of an accuracy greater than what is required for USB repeaters. In such an example, the precision clock is configured to provide a precise time reference for the detection of a change of the operation mode by accurately detecting a duration that has passed without USB communication. For example, a secondary device, which is transitioning from high-speed to full speed, enables its pullup circuitry after 3 milliseconds (mS) wherein there is no USB communication, before measuring the voltage of the differential data BUS at 3.1 mS in order to determine the operation mode of the primary device. In such an example, the USB repeater would only have 3.1 mS to disable pulldown circuitry and enable pullup circuitry, which is coupled to the differential data BUS, to determine whether the primary device has pulldown circuitry enabled. A USB repeater determines whether to enable or disable the pulldown circuitry on the differential data BUS coupled to the primary device and the USB repeater based on the voltage of the differential data BUS.

A USB repeater example described herein includes example high-speed termination detection circuitry to determine whether or not a primary device has transitioned from one operation mode to another operation mode. The USB repeater may include a clock of a lower precision than what has been conventionally used in USB repeaters as a result of including the high-speed termination detection circuitry, such that the cost of the clock included in the USB repeater is reduced. The high-speed termination detector circuitry is configured to determine whether or not the primary device has pulldown circuitry enabled. The high-speed termination detection circuitry may determine the primary device has entered a reset state or a suspend state (L2), such that the reset state indicates the primary device is not transitioning operation modes while the suspend state indicates a transition from high-speed mode to full speed mode.

FIG.1is a schematic diagram of an example USB communication system100including an example primary device102, an example secondary device104, and an example USB repeater circuitry106. In the example ofFIG.1, the USB communications system100is configured for USB communication between the primary device102and the secondary device104through the USB repeater circuitry106, situated between the primary device102and the secondary device104. The USB repeater circuitry106includes circuitry to determine an operation mode of the primary device102and circuitry to replicate the determined operation mode. Such circuitry enables the secondary device104to determine the operation mode of the primary device102based on the replicated circuitry, as if the primary device102and the secondary device104were coupled directly to the same differential data BUS.

In the example ofFIG.1, the primary device102includes an example first USB terminal (UDP)108, a second USB terminal (UDM)110, a first resistor112, a first switch114, a second resistor116, a second switch118, and a first controller120. The primary device102is configured to operate in full-speed mode by opening the switches114and118, such that the USB terminals108and110are not coupled to a common potential (e.g., ground). The primary device102is configured to operate in high-speed mode as a result of closing the switches114and118, such that the USB terminals108and110are coupled to the common potential through the resistors112and116.

The USB terminals108and110are configured to be coupled to the secondary device104, such that the USB terminals108and110comprise a first differential data BUS of the USB communication system100. The USB terminals108and110are coupled to the first controller120, such that the first controller120may set and/or determine the value of the USB terminals108and110. The USB terminals108and110are configured to represent the USB communications between the primary device102and the secondary device104as a differential signal. The differential signal represented by the USB terminals108and110is configured to represent a value as the difference in voltage between the first USB terminal108and the second USB terminal110, such that a logic high is determined as a result of a voltage difference between the USB terminals108and110above a threshold value. For example, the logic high signal is a signal (e.g., a voltage, a current, etc.) representative of a digital one (e.g., a digital ‘1,’ a logic ‘1,’ or a digital high), such as a voltage of 2.2V, 3.3V, 5V, etc. In some examples, a logic low signal is a signal representative of a digital zero (e.g., a digital ‘0,’ a logic ‘0,’ or a digital low), such as a common potential or ground.

The first resistor112is coupled between the first USB terminal108and the first switch114. The first resistor112is configured to pulldown the first USB terminal108as a result of the first switch114being closed. The first resistor112is configured to be of a resistance large enough to set the voltage of the first USB terminal108based on a current supplied to the first USB terminal108by the USB repeater circuitry106. For example, the first USB terminal108represents a logic high as a result of the first resistor112, having a resistance approximately equal to 45 ohms (Ω), being supplied a current approximately equal to 40 milliamps (mA) to set the voltage of the first USB terminal108to 1.8 volts (V). The first resistor112is configured to pulldown the first USB terminal108as a result of the primary device operating in high-speed mode.

The first switch114is coupled between the first resistor112and the common potential. The first switch114is coupled to the first controller120, such that the first controller120may open and/or close the first switch114. The first switch114is configured to be closed to allow the first resistor112to pulldown the first USB terminal108, such that the primary device102may operate in high-speed mode. The state of the first switch114determines the operation mode of the primary device102on the first USB terminal108. For example, the primary device102operates in high-speed mode as a result of the switches114and118being closed by the first controller120. Alternatively, the primary device102operates in full-speed mode as a result of the first switch114being opened by the first controller120. In the example ofFIG.1, the first switch114is illustrated as a switch controlled by the first controller120through a control input. Alternatively, the first switch114may be a transistor controlled by the first controller120.

The second resistor116is coupled between the second USB terminal110and the second switch118. The second resistor116is configured to pulldown the second USB terminal110as a result of the second switch118being closed. The second resistor116is configured to be of a resistance large enough to set the voltage of the second USB terminal110based on a current supplied to the second USB terminal110by the USB repeater circuitry106. For example, the second USB terminal110represents a logic high as a result of the second resistor116, having a resistance approximately equal to 45 ohms (Ω), being supplied a current approximately equal to 40 Milliamps (mA) to set the voltage of the second USB terminal110to 1.8 volts (V). The second resistor116is configured to pulldown the second USB terminal110as a result of the primary device operating in high-speed mode.

The second switch118is coupled between the second resistor116and the common potential. The second switch118is coupled to the first controller120, such that the first controller120may open and/or close the second switch118. The second switch118is configured to be closed to allow the second resistor116to pulldown the second USB terminal110, such that the primary device102may operate in high-speed mode. The state of the switches114and118determine the operation mode of the primary device102on the second USB terminal110. For example, the primary device102operates in high-speed mode as a result of the switches114and118being closed by the first controller120. Alternatively, the primary device102operates in full-speed mode as a result of the second switch118being opened by the first controller120. In the example ofFIG.1, the second switch118is illustrated as a switch controlled by the first controller120through a control input. Alternatively, the second switch118may be a transistor controlled by the first controller120.

In the example ofFIG.1, the secondary device104includes a third USB terminal (DDP)122, a fourth USB terminal (DDM)124, a third resistor126, a third switch128, a fourth resistor130, a fourth switch132, a fifth switch134, a fifth resistor136, a first voltage supply138, and a second controller140. The secondary device104is configured to operate in full-speed mode as a result of opening the switches128and132and closing the fifth switch134, such that the USB terminals122and124are coupled to a voltage supply. The secondary device104is configured to operate in high-speed mode as a result of closing the switches128and132, such that the USB terminals122and124are coupled to the common potential through the resistors126and130.

The USB terminals122and124are configured to be coupled to the primary device102, such that the USB terminals122and124comprise a second differential data BUS of the USB communication system100. The USB terminals122and124are coupled to the second controller140, such that the second controller140may set and/or determine the value of the USB terminals122and124. The USB terminals122and124are configured to represent the USB communications between the primary device102and the secondary device104as a differential signal. The differential signal represented by the USB terminals122and124are configured to represent a value as the difference in voltage between the third USB terminal122and the fourth USB terminal124, such that a logic high is determined as a result of a voltage difference between the USB terminals122and124above a threshold value. For example, the logic high signal is a signal (e.g., a voltage, a current, etc.) representative of a digital one (e.g., a digital ‘1’ or a logic ‘1’), such as a voltage of 2.2V, 3.3V, 5V, etc. In some examples, a logic low signal is a signal representative of a digital zero (e.g., a digital ‘0’ or a logic ‘0’), such as a common potential. The common potential or ground for secondary device104may be the same or different than the common potential or ground for the primary device. The difference is potentials for the primary device102and the secondary device104may be due to the isolation circuitry146in the USB repeater circuitry106.

The third resistor126is coupled between the third USB terminal122and the third switch128. The third resistor126is configured to pulldown the third USB terminal122as a result of the third switch128being closed. The third resistor126is configured to be of a resistance large enough to set the voltage of the third USB terminal122based on a current supplied to the third USB terminal122by the USB repeater circuitry106. For example, the third USB terminal122represents a high-speed mode as a result of determining the voltage of the third USB terminal122is approximately equal to 400 millivolts (mV) after the third resistor126, having a resistance approximately equal to 45 ohms (Ω), is supplied current prior to the secondary device104supplying a test current to the third USB terminal122. In such an example, the third USB terminal122is approximately equal to 400 mV in response to the test current having a magnitude of 17.78 milliamps (mA), which indicates that the third resistor126is coupled in parallel with another resistor of approximately the same magnitude. The third resistor126is configured to pulldown the third USB terminal122as a result of the primary device102operating in high-speed mode and/or high-speed reset.

The third switch128is coupled between the third resistor126and the common potential. The third switch128is coupled to the second controller140, such that the second controller140may open and/or close the third switch128. The third switch128is configured to allow the third resistor126to pulldown the third USB terminal122, such that the primary device102may operate in high-speed mode. The state of the switches128,132, and134determine the operation mode of the primary device102on the third USB terminal122. For example, the primary device102operates in high-speed mode as a result of the switches128and132being closed by the second controller140. Alternatively, the primary device102operates in full-speed mode as a result of the third switch128being opened by the second controller140. In the example ofFIG.1, the third switch128is illustrated as a switch controlled by the second controller140through a control input. Alternatively, the third switch128may be a transistor controlled by the second controller140.

The fourth resistor130is coupled between the fourth USB terminal124and the fourth switch132. The fourth resistor130is configured to pulldown the fourth USB terminal124as a result of the fourth switch132being closed. The fourth resistor130is configured to be of a resistance large enough to set the voltage of the fourth USB terminal124based on a current supplied to the fourth USB terminal124by the USB repeater circuitry106. For example, the fourth USB terminal124represents a high-speed mode as a result of determining the voltage of the fourth USB terminal124is approximately equal to 400 millivolts (mV) after the fourth resistor130, having a resistance approximately equal to 45 ohms (Ω), is supplied a current prior to the secondary device104supplying a test current to the fourth USB terminal124. In such an example, the fourth USB terminal124is approximately equal to 400 mV in response to the test current having a magnitude of 17.78 milliamps (mA), which indicates that the fourth resistor130is coupled in parallel with another resistor of approximately the same magnitude. The fourth resistor130is configured to pulldown the fourth USB terminal124as a result of the secondary device104operating in high-speed mode and/or high-speed reset.

The fourth switch132is coupled between the fourth resistor130and the common potential. The fourth switch132is coupled to the second controller140, such that the second controller140may open and/or close the fourth switch132. The fourth switch132is configured to allow the fourth resistor130to pulldown the fourth USB terminal124, such that the secondary device104may operate in high-speed mode. The state of the switches128,132, and134determine the operation mode of the secondary device104on the fourth USB terminal124. For example, the secondary device104operates in high-speed mode as a result of the switches128and132being closed by the second controller140. Alternatively, the secondary device104operates in full-speed mode as a result of the fourth switch132being opened by the second controller140. In the example ofFIG.1, the fourth switch132is illustrated as a switch controlled by the second controller140through a control input. Alternatively, the fourth switch132may be a transistor controlled by the second controller140.

The fifth switch134is coupled between the third USB terminal122and the fifth resistor136. The fifth switch134is coupled to the second controller140, such that the second controller140may open and/or close the fifth switch134. The fifth switch134is configured to allow the fifth resistor136to pullup the third USB terminal122, such that the secondary device104may operate in full-speed mode or determine whether or not the USB terminals122and124are being pulled down. The state of the switches128,132, and134determine the operation mode of the secondary device104on the third USB terminal122. For example, the secondary device104operates in full-speed mode as a result of the fifth switch134being closed by the second controller140. Alternatively, the secondary device104operates in high-speed mode as a result of the fifth switch134being opened and the switches128and132being closed by the second controller140. In the example ofFIG.1, the fifth switch134is illustrated as a switch controlled by the second controller140through a control input. Alternatively, the fifth switch134may be a transistor controlled by the second controller140.

The fifth resistor136is coupled between the fifth switch134and the first voltage supply138(which is shown to be approximately 3.3 volts inFIG.1but may any voltage that can be used in USB applications). The fifth resistor136is configured to pullup the third USB terminal122as a result of the fifth switch134being closed. The fifth resistor136is configured to be of a resistance large enough to set the voltage of the third USB terminal122to a value approximately equal to a chirp voltage as a result of the first resistor112pulling down the first USB terminal108and the fifth resistor136pulling up the third USB terminal122. For example, the third USB terminal122is approximately equal to common potential as a result of the first resistor112being equal to 45 ohms (Ω) and the fifth resistor136being equal to 1.5 kilohms (kΩ). The fifth resistor136is configured to pullup the third USB terminal122as a result of the secondary device104operating in full-speed mode or determining whether or not the USB terminals122and124are being pulled down.

In the example ofFIG.1, the USB repeater circuitry106includes upstream circuitry142, downstream circuitry144, logic isolation circuitry146, and a third controller148. The USB repeater circuitry106is coupled between the primary device102and the secondary device104, such that all USB communications pass through the USB repeater circuitry106. The logic isolation circuitry146(e.g., any type of galvanic isolation, inductive isolation and/or capacitive isolation) is coupled between the upstream circuitry142and the downstream circuitry144. Due to the isolation circuitry146, the upstream circuitry142and downstream circuitry144may operate at different voltages and/or different common potentials. The USB repeater circuitry106is configured to replicate the operation of the secondary device104using the upstream circuitry142and the third controller148. The upstream circuitry142is configured to determine the operation mode of the primary device102, such that the operation mode may be replicated using the downstream circuitry144. The USB repeater circuitry106is configured to replicate the operation of the primary device102using the downstream circuitry144and the third controller148. The logic isolation circuitry146is configured to buffer the transmissions of the upstream circuitry142and the downstream circuitry144, such that the primary device102and the secondary device104may communicate as if the devices102and104were directly coupled. Transmissions across isolation circuitry146may need to be converted (such as, modulated) to transverse the isolation barrier and then de-converted (such as, demodulated and converted back to digital).

The upstream circuitry142includes a fifth USB terminal (UDP)150, a sixth USB terminal (UDM)152, a sixth resistor154, a sixth switch156, a seventh resistor158, a seventh switch160, an eighth switch162, an eighth resistor164, a second voltage supply166, and an example high-speed termination detection circuitry168. The upstream circuitry142is coupled between the primary device102and the logic isolation circuitry146. The upstream circuitry142includes circuitry to replicate the full-speed mode and high-speed mode of the secondary device104.

The USB terminals150and152are configured to be coupled to USB terminals108and110, such that the USB terminals108,110,150, and152comprise the first differential data BUS of the USB communication system100. The USB terminals150and152are configured to represent the USB communications between the primary device102and the secondary device104as a differential signal. The differential signal represented by the USB terminals150and152is configured to represent a value as the difference in voltage between the fifth USB terminal150and the sixth USB terminal152, such that a logic high is determined as a result of a voltage difference between the USB terminals150and152above a threshold value.

The sixth resistor154is coupled between the fifth USB terminal150and the sixth switch156. The sixth resistor154is configured to pulldown the fifth USB terminal150as a result of the sixth switch156being closed. The sixth resistor154is configured to be of a resistance large enough to set the voltage of the fifth USB terminal150based on a current supplied to the fifth USB terminal150by the USB repeater circuitry106. For example, the fifth USB terminal150represents a high-speed mode as a result of determining the voltage of the fifth USB terminal150is approximately equal to 400 millivolts (mV) after the sixth resistor154, having a resistance approximately equal to 45 ohms (Ω), is supplied current prior to the primary device102supplying a test current to the first USB terminal108. In such an example, the fifth USB terminal150is approximately equal to 400 mV in response to the test current having a magnitude of 17.78 milliamps (mA), which indicates that the sixth resistor154is coupled in parallel with another resistor of approximately the same magnitude. The sixth resistor154is configured to pulldown the fifth USB terminal150as a result of the USB communication system100operating in high-speed mode and/or high-speed reset.

The sixth switch156is coupled between the sixth resistor154and the common potential. The sixth switch156is coupled to the third controller148, such that the third controller148may open and/or close the sixth switch156. The sixth switch156is configured to allow the sixth resistor154to pulldown the fifth USB terminal150, such that the USB communication system100may operate in high-speed mode. The state of the sixth switch156represents the operation mode of the secondary device104on the fifth USB terminal150. For example, the sixth switch156is closed by the third controller148as a result of determining the USB communication system100is operating in high-speed mode. Alternatively, the sixth switch156may be opened as a result of determining the USB communication system100is operating in full-speed mode. In the example ofFIG.1, the sixth switch156is illustrated as a switch controlled by the third controller148through a control input. Alternatively, the sixth switch156may be a transistor controlled by the third controller148.

The seventh resistor158is coupled between the sixth USB terminal152and the seventh switch160. The seventh resistor158is configured to pulldown the sixth USB terminal152as a result of the seventh switch160being closed. The seventh resistor158is configured to be of a resistance large enough to set the voltage of the sixth USB terminal152based on a current supplied to the sixth USB terminal152by the USB repeater circuitry106. For example, the sixth USB terminal152represents a high-speed mode as a result of determining the voltage of the sixth USB terminal152is approximately equal to 400 millivolts (mV) after the seventh resistor158, having a resistance approximately equal to 45 ohms (Ω), is supplied current prior to the primary device102supplying a test current to the second USB terminal110. In such an example, the sixth USB terminal152is approximately equal to 400 mV in response to the test current having a magnitude of 17.78 milliamps (mA), which indicates that the seventh resistor158is coupled in parallel with another resistor of approximately the same magnitude. The seventh resistor158is configured to pulldown the sixth USB terminal152as a result of the USB communication system100operating in high-speed mode and/or high-speed reset.

The seventh switch160is coupled between the seventh resistor158and the common potential. The seventh switch160is coupled to the third controller148, such that the third controller148may open and/or close the seventh switch160. The seventh switch160is configured to allow the seventh resistor158to pulldown the sixth USB terminal152, such that the USB communication system100may operate in high-speed mode. The state of the seventh switch160represents the operation mode of the secondary device104on the sixth USB terminal152. For example, the seventh switch160is closed by the third controller148as a result of determining the USB communication system100is operating in high-speed mode. Alternatively, the seventh switch160may be opened as a result of determining the USB communication system100is operating in full-speed mode. In the example ofFIG.1, the seventh switch160is illustrated as a switch controlled by the third controller148through a control input. Alternatively, the seventh switch160may be a transistor controlled by the third controller148.

The eighth switch162is coupled between the fifth USB terminal150and the eighth resistor164. The eighth switch162is coupled to the third controller148, such that the third controller148may open and/or close the eighth switch162. The eighth switch162is configured to allow the eighth resistor164to pullup the fifth USB terminal150, such that the USB repeater circuitry106may replicate the secondary device104operations in full-speed mode and determine whether or not the USB terminals150and152are being pulled down. The state of the eighth switch162represents the operation mode of the secondary device104on the fifth USB terminal150. For example, the eighth switch162is closed by the third controller148as a result of the USB repeater circuitry106determining the secondary device104is operating in full-speed mode. Alternatively, the USB repeater circuitry106may replicate the secondary device104operating in high-speed mode as a result of the eighth switch162being opened by the third controller148. In the example ofFIG.1, the eighth switch162is illustrated as a switch controlled by the third controller148through a control input. Alternatively, the eighth switch162may be a transistor controlled by the third controller148.

The eighth resistor164is coupled between the eighth switch162and the second voltage supply166. The eighth resistor164is configured to pullup the fifth USB terminal150as a result of the eighth switch162being closed. The eighth resistor164is configured to be of a resistance large enough to set the voltage of the fifth USB terminal150to a value approximately equal to the common potential as a result of the first resistor112pulling down the first USB terminal108and the eighth resistor164pulling up the sixth USB terminal152. For example, the fifth USB terminal150is approximately equal to common potential as a result of the first resistor112being equal to 45 ohms (Ω) and the eighth resistor164being equal to 1.5 kilohms (kΩ). The eighth resistor164is configured to pullup the fifth USB terminal150as a result of the USB repeater circuitry106determining the secondary device104is operating in full-speed mode or in the process of determining whether or not the USB terminals150and152are being pulled down.

The high-speed termination detection circuitry168is coupled to the third controller148and the USB terminals150and152. The high-speed termination detection circuitry168is configured to determine the operation mode of the primary device102. For example, the high-speed termination detection circuitry168may supply a current to the USB terminals150and152to determine whether the voltage is representative of the switches114and118being opened or closed. The high-speed termination detection circuitry168is configured to indicate to the third controller148the operation mode of the primary device102as a result of determining the operation mode of the primary device102. For example, the high-speed termination detection circuitry168may assert a pin coupled between the third controller148and the high-speed termination detection circuitry168to indicate high-speed mode. The high-speed termination detection circuitry168is additionally illustrated byFIG.2.

In the example ofFIG.1, the high-speed termination detection circuitry168is coupled individually to the USB terminals150and152, such that the high-speed termination detection circuitry168may interact with each terminal individually. Additionally, the high-speed termination detection circuitry168is coupled to the third controller148(there may be more connections between the high-speed termination detection circuitry168and the third controller148than depicted byFIG.1). The high-speed termination detection circuitry168is configured to be controlled by the third controller148, such that different circuitry included in the high-speed termination detection circuitry168may be individually enabled and/or disabled. The high-speed termination detection circuitry168is configured to supply power to the USB terminals150and152to determine whether or not the USB terminals150and152are coupled to a device which is pulling down the USB terminals150and152. For example, the high-speed termination detection circuitry168may supply a current to USB terminals150and152before monitoring for a change in voltage of the USB terminals150and152. In such an example, the voltage of the USB terminals150and152would increase as a result of circuitry, configured to pulldown the USB terminals150and152, being coupled to the USB terminals150and152. Advantageously, the magnitude of power supplied to the USB terminals150and152may be increased to reduce settling times of components coupled to the USB terminals150and152, such that the time to determine the operation mode of the primary device102is decreased. Advantageously, the high-speed termination detection circuitry168is configured to implement circuitry to determine the mode of the primary device102, such that no analog to digital conversion is required to determine the voltage of the USB terminals150and152.

The downstream circuitry144includes a seventh USB terminal (DDP)170, an eighth USB terminal (DDM)172, a ninth resistor174, a ninth switch176, a tenth resistor178, and a tenth switch180. The downstream circuitry144is coupled between the secondary device104and the logic isolation circuitry146. The downstream circuitry144includes circuitry to replicate the full-speed mode and high-speed operation mode of the primary device102.

The USB terminals170and172are configured to be coupled to USB terminals122and124, such that the USB terminals122,124,170, and172(and the conductors connected therebetween) comprise the second differential data BUS of the USB communication system100. The USB terminals170and172are configured to represent the USB communications between the primary device102and the secondary device104as a differential signal. The differential signal represented by the USB terminals170and172are configured to represent a value as the difference in voltage between the seventh USB terminal170and the eighth USB terminal172, such that a logic high is determined as a result of a voltage difference between the USB terminals170and172above a threshold value.

The ninth resistor174is coupled between the seventh USB terminal170and the ninth switch176. The ninth resistor174is configured to pulldown the seventh USB terminal170as a result of the ninth switch176being closed. The ninth resistor174is configured to be of a resistance large enough to set the voltage of the seventh USB terminal170based on a current supplied to the seventh USB terminal170by the USB repeater circuitry106. For example, the seventh USB terminal170represents a high-speed mode as a result of determining the voltage of the seventh USB terminal170is approximately equal to 400 millivolts (mV) after the ninth resistor174, having a resistance approximately equal to 45 ohms (Ω), is supplied current prior to the secondary device104supplying a test current to the third USB terminal122. In such an example, the seventh USB terminal170is approximately equal to 400 mV in response to the test current having a magnitude of 17.78 milliamps (mA), which indicates that the ninth resistor174is coupled in parallel with another resistor of approximately the same magnitude. The ninth resistor174is configured to pulldown the seventh USB terminal170as a result of the USB communication system100operating in high-speed mode and/or high-speed reset.

The ninth switch176is coupled between the ninth resistor174and the common potential. The ninth switch176is coupled to the third controller148, such that the third controller148may open and/or close the ninth switch176. The ninth switch176is configured to allow the ninth resistor174to pulldown the seventh USB terminal170, such that the USB communication system100may operate in high-speed mode. The state of the ninth switch176represents the operation mode of the secondary device104on the seventh USB terminal170. For example, the ninth switch176is closed by the third controller148as a result of determining the USB communication system100is operating in high-speed mode. Alternatively, the ninth switch176may be opened as a result of determining the USB communication system100is operating in full-speed mode. In the example ofFIG.1, the ninth switch176is illustrated as a switch controlled by the third controller148through a control input. Alternatively, the ninth switch176may be a transistor controlled by the third controller148.

The tenth resistor178is coupled between the eighth USB terminal172and the tenth switch180. The tenth resistor178is configured to pulldown the eighth USB terminal172as a result of the tenth switch180being closed. The tenth resistor178is configured to be of a resistance large enough to set the voltage of the eighth USB terminal172based on a current supplied to the eighth USB terminal172by the USB repeater circuitry106. For example, the eighth USB terminal172represents a high-speed mode as a result of determining the voltage of the eighth USB terminal172is approximately equal to 400 millivolts (mV) after the tenth resistor178, having a resistance approximately equal to 45 ohms (Ω), is supplied current prior to the secondary device104supplying a test current to the third USB terminal122. In such an example, the eighth USB terminal172is approximately equal to 400 mV in response to the test current having a magnitude of 17.78 milliamps (mA), which indicates that the tenth resistor178is coupled in parallel with another resistor of approximately the same magnitude. The tenth resistor178is configured to pulldown the eighth USB terminal172as a result of the USB communication system100operating in high-speed mode and/or high-speed reset.

The tenth switch180is coupled between the tenth resistor178and the common potential. The tenth switch180is coupled to the third controller148, such that the third controller148may open and/or close the tenth switch180. The tenth switch180is configured to allow the tenth resistor178to pulldown the eighth USB terminal172, such that the USB communication system100may operate in high-speed mode. The state of the tenth switch180represents the operation mode of the secondary device104on the eighth USB terminal172. For example, the tenth switch180is closed by the third controller148as a result of determining the USB communication system100is operating in high-speed mode. Alternatively, the tenth switch180may be opened as a result of determining the USB communication system100is operating in full-speed mode. In the example ofFIG.1, the tenth switch180is illustrated as a switch controlled by the third controller148through a control input. Alternatively, the tenth switch180may be a transistor controlled by the third controller148.

In example operation, the primary device102is configured to begin USB communication in full speed mode, such that the first controller120is configured to open the switches114and118. The USB repeater circuitry106is configured to open the switches176and180to replicate the full speed mode of the primary device102. The secondary device104is configured to begin USB communication in full speed mode, such that the second controller140is configured to open the switches128and132before closing the fifth switch134. The USB repeater circuitry106is configured to open the switches156and160before closing the eighth switch162to replicate the full speed operation mode of the secondary device104.

In example operation, the primary device102is configured to determine if the secondary device104is capable of high-speed mode by entering a reset state and closing the switches114and118, such that the USB terminals108,110,150, and152are pulled towards common potential and/or by enabling the first controller120to drive the USB terminals108and110to a logic low. The USB repeater circuitry106may determine that the primary device102has pulled down the USB terminals108and110using the high-speed termination detection circuitry168to determine the voltage of the USB terminals150and152. The USB repeater circuitry106is configured to close the switches176and180and/or configure the logic isolation circuitry146to drive the USB terminals170and172to a logic low to replicate the primary device102, such that the secondary device104may determine the operation mode of the primary device102. The secondary device104is configured to open the fifth switch134before closing the switches128and132and configuring the second controller140to supply a test current to the USB terminals150and152. The secondary device104determines the operation mode of the primary device102based on the second controller140determining that the voltage of the USB terminals122and124are approximately equal to a chirp voltage as a result of being pulled down and/or driven low. The primary device102is configured to wait for a logic low on the USB terminals108and110before supplying the test current to determine whether the secondary device104enabled circuitry for high-speed mode. The USB communication system100is configured to begin USB communications, by having the primary device102communicate to the secondary device104through the USB repeater circuitry106, upon finishing a reset state, which configures the operation mode of the primary device102and the secondary device104.

In example operation, the primary device102is configured to leave high-speed mode and return to full-speed mode as a result of the first controller120disabling the switches114and118following preventing USB communications for a set duration. The logic isolation circuitry146is configured to determine whether or not a USB communication has occurred within the set duration. The USB repeater circuitry106is configured to determine whether the USB terminals150and152are being pulled down by opening the switches156and160before enabling the high-speed termination detection circuitry168. The high-speed termination detection circuitry168is configured to indicate to the third controller148whether or not the primary device102opened the switches114and118. The third controller148is configured to open the switches176and180as a result of the high-speed termination detection circuitry168indicating the USB terminals150and152are no longer being pulled down. The secondary device104is configured to determine whether or not the USB terminals122and124are being pulled down by opening the switches128and132before closing the fifth switch134and determining the voltage of the USB terminals122and124. The primary device102may indicate an entry into a suspend state by opening the switches114and118. Alternatively, the primary device102may indicate entry into a reset state by having the switches114and118remain closed during the set duration wherein no USB communication occurs. Advantageously, the USB repeater circuitry106is configured to determine whether the primary device102has entered the suspend state or the reset state using the high-speed termination detection circuitry168. Advantageously, the USB repeater circuitry106requires a clock of a precision equivalent to the set duration in order for the high-speed termination detection circuitry168to determine the state of the primary device102in time to replicate the primary device102state in the downstream circuitry144.

FIG.2is a schematic diagram of an example of the high-speed termination detection circuitry168ofFIG.1. In the example ofFIG.2, the high-speed termination detection circuitry168includes the fifth USB terminal150, the sixth USB terminal152, a first source control terminal202, a second source control terminal204, a first current mode driver206, a third source control terminal208, a fourth source control terminal210, a second current mode driver212, a first reference input terminal214, a second reference input terminal216, a reference control terminal218, a multiplexer220, a first comparator222, a second comparator224, a first supply terminal226, a first termination indication terminal228, a second supply terminal230, and a second termination indication terminal232. In the example ofFIG.2, the high-speed termination detection circuitry168is configured to assert (e.g., bring to a logic “1” or a logic “high”) the termination indication terminals228and232based on the operation mode of the primary device102ofFIG.1.

In the example ofFIG.2, the source control terminals202and204are coupled to the first current mode driver206. The source control terminals202and204are configured to enable and/or disable an output of the first current mode driver206. For example, the first source control terminal202is configured to enable the first current mode driver206to supply a current to the fifth USB terminal150whereas the second source control terminal204is configured to enable the first current mode driver206to supply a current to the sixth USB terminal152. The source control terminals202and204may be coupled to the third controller148ofFIG.1, such that the first current mode driver206may be enabled by the third controller148.

The first current mode driver206is configured to receive an input on the source control terminals202and204and to output to the USB terminals150and152. The first current mode driver206is configured to supply a current and/or voltage of a first magnitude to the fifth USB terminal150as a result of the first source control terminal202being set to a logic high or a voltage above a threshold based on the properties of the first current mode driver206. Additionally, the first current mode driver206is configured to supply a current and/or voltage to the sixth USB terminal152as a result of the second source control terminal204being set to a logic high or a voltage above the threshold. Advantageously, the first current mode driver206may be enabled to supply a current to the USB terminals150and152to determine if the USB terminals150and152are coupled to enabled pulldown circuitry (e.g., the resistors112and116coupled to the switches114and118). The first current mode driver206may be referred to as a current supply.

The source control terminals208and210are coupled to the second current mode driver212. The source control terminals208and210are configured to enable and/or disable an output of the second current mode driver212. For example, the third source control terminal208is configured to enable the second current mode driver212to supply a current to the fifth USB terminal150whereas the fourth source control terminal210is configured to enable the second current mode driver212to supply a current to the sixth USB terminal152. The source control terminals208and210may be coupled to the third controller148, such that the second current mode driver212may be enabled by the third controller148.

The second current mode driver212is configured to receive an input on the source control terminals208and210and to output to the USB terminals150and152. The second current mode driver212is configured to supply a current and/or voltage of a second magnitude to the fifth USB terminal150as a result of the third source control terminal208being set to a logic high or a voltage above a threshold based on the properties of the second current driver mode212. Additionally, the second current mode driver212is configured to supply a current and/or voltage to the sixth USB terminal152as a result of the fourth source control terminal210being set to a logic high or a voltage above the threshold. Alternatively, the high-speed termination detection circuitry168may include either of the current mode drivers206or212. Advantageously, the second current mode driver212may be enabled to supply a current to the USB terminals150and152to determine whether or not the USB terminals150and152are coupled to pulldown circuitry (e.g., the resistors112and116ofFIG.1coupled to the switches114and118ofFIG.1). The second current mode driver212may be referred to as a current supply.

The reference input terminals214and216are coupled to the multiplexer220. The reference input terminals214and216may be configured to be coupled to the third controller148. The reference input terminals214and216are configured to supply a reference current to the multiplexer220. The first reference input terminal214is configured to supply a first current (Isrc1 ref) to the multiplexer220. The first current is configured to be of a magnitude approximately equal to the current of the first magnitude, which may be supplied by the first current mode driver206to the USB terminals150and152. The second reference input terminal216is configured to supply a second current (Isrc2 ref) to the multiplexer220. The second current is configured to be of a magnitude approximately equal to the current of the second magnitude, which may be supplied by the second current mode driver212to the USB terminals150and152.

The reference control terminal218is coupled to the multiplexer220. The reference control terminal218may be configured to be coupled to the third controller148. The reference control terminal218is configured to control the multiplexer220. For example, the multiplexer220outputs a current approximately (preferably exactly) equal to the current supplied to the first reference input terminal214as a result of the reference control terminal218being set to a logic high. In such an example, the multiplexer220outputs a current approximately (preferably exactly) equal to current supplied to the second reference input terminal216as a result of the reference control terminal218being set to a digital zero. Advantageously, the current supplied by the output of the multiplexer220is controlled by the reference control terminal218.

The multiplexer220is configured to supply the current supplied to either of the reference input terminals214or216to the comparators222and224based on the reference control terminal218. For example, the multiplexer220supplies a current approximately (preferably exactly) equal to the current supplied to the first reference input terminal214to the comparators222and224, as a result of the reference control terminal218being set to a logic high. Advantageously, the current supplied to the comparators is determined based on the reference control terminal218.

A first comparator terminal (e.g., the non-inverting input) of the first comparator222is coupled to the fifth USB terminal150. A second comparator terminal (e.g., the inverting input) of the first comparator222is coupled to the multiplexer220. A third comparator terminal of the first comparator222is coupled to the first supply terminal226. A fourth comparator terminal of the first comparator222is coupled to the first termination indication terminal228. The first comparator222is configured to receive a non-inverting (+) input from the fifth USB terminal150and an inverting (−) input from the multiplexer220. The first comparator222is configured to output to the first termination indication terminal228. The first comparator222is configured to be supplied power by the first supply terminal226. The first comparator222is configured to set the value of the first termination indication terminal228based on a comparison of the fifth USB terminal150and the output of the multiplexer220. For example, the first termination indication terminal228is set to a logic high as a result of the current of the fifth USB terminal150being greater than the current supplied by the multiplexer220. In some such examples, the first comparator222compares the comparator terminals to determine if pulldown circuitry (e.g., the resistors112and116ofFIG.1coupled to the switches114and118ofFIG.1) is coupled to the non-inverting by determining the current of the fifth USB terminal is less than the current supplied to the inverting input by the multiplexer220. For example, the first termination indication terminal228is equal to a logic low as a result of the current supplied by the fifth USB terminal150being less than the current supplied by the multiplexer220. Advantageously, the first termination indication terminal228represents whether or not the USB terminals150and152are coupled to pulldown circuitry.

A first comparator terminal of the second comparator224is coupled to the sixth USB terminal152. A second comparator terminal of the second comparator224is coupled to the multiplexer220. A third comparator terminal of the second comparator224is coupled to the second supply terminal230. A fourth comparator terminal of the second comparator224is coupled to the second termination indication terminal232. The second comparator224is configured to receive a non-inverting (+) input from the sixth USB terminal152and an inverting (−) input from the multiplexer220. The second comparator224is configured to output to the second termination indication terminal232. The second comparator224is configured to be supplied power by the second supply terminal230. The second comparator224is configured to set the value of the second termination indication terminal232based on a comparison of the sixth USB terminal152and the output of the multiplexer220. For example, the second termination indication terminal232is set to a logic high as a result of the current of the sixth USB terminal152being greater than the current supplied by the multiplexer220. In some such examples, the second comparator224is configured to determine if pulldown circuitry is coupled to the non-inverting by determining the current of the sixth USB terminal152is less than the current supplied to the inverting input by the multiplexer220. For example, the second termination indication terminal232is equal to a digital low as a result of the current supplied by the fifth USB terminal being less than the current supplied by the multiplexer220. Advantageously, the second termination indication terminal232represents whether or not the USB terminals150and152are coupled to pulldown circuitry.

In the example ofFIG.2, the second termination indication terminals228and232may be coupled to the third controller148, such that the third controller148may open and/or close the switches176and180to replicate the operation mode of the primary device102within the downstream circuitry144. Advantageously, the high-speed termination detection circuitry168is able to determine whether or not pulldown circuitry is coupled to and enabled on the USB terminals150and152without determining the voltage of the USB terminals150and152.

In example operation, the current mode drivers206and212supply a current of the first magnitude or the second magnitude individually to each of the USB terminals150and152based on the source control terminals202,204,208, and210. The reference control terminal218configures the multiplexer220to supply a current equal to the reference input terminal214or216based on whether the current is being supplied by first current mode driver206or the second current mode driver212. The first comparator222sets the first termination indication terminal228as a result of determining that the current supplied by the fifth USB terminal150is greater than the current supplied by the multiplexer220. The second comparator224sets the second termination indication terminal232as a result of determining that the current supplied by the sixth USB terminal152is greater than the current supplied by the multiplexer220.

Advantageously, the operation mode of the primary device102may be determined based on the controller148being coupled to the high-speed termination detection circuitry168. Advantageously, the high-speed termination detection circuitry168determines whether or not the USB terminals150and152without the need for a precise clock. Advantageously, the high-speed termination detection circuitry168includes a plurality of current mode drivers to supply currents of different magnitudes to the USB terminals150and152.

FIG.3Ais an example first timing diagram300of an example operation to detect a reset state using the USB repeater circuitry106ofFIG.1including the high-speed termination detection circuitry168ofFIGS.1and2. In the example ofFIG.3A, the first timing diagram300includes a first host high-speed termination302, a first repeater upstream high-speed termination304, a first upstream termination detection enable306, a first upstream termination detection output308, a first repeater downstream high-speed termination310, a first secondary device high-speed termination312, a first secondary device pullup314, and a first USB terminal voltage (DP/DM)316. The first timing diagram300represents the operations of the USB communications system100ofFIG.1during an example transition of the primary device102ofFIG.1into a reset state, such that the operation mode of the primary device102remains in a high-speed mode.

In the example ofFIG.3A, the first host high-speed termination302is configured to represent whether or not the switches114and118ofFIG.1of the primary device102are closed by the first controller120ofFIG.1. The first host high-speed termination302represents the switches114and118being closed as a logic high (HI) and open as a logic low (LO). The first host high-speed termination302represents the mode of the primary device102. For example, the primary device102is operating in high-speed mode during the duration wherein the first host high-speed termination302is a logic high, or the primary device102is operating in full-speed mode during the duration wherein the first host high-speed termination302is a logic low.

The first repeater upstream high-speed termination304is configured to represent whether or not the switches156and160of the upstream circuitry142ofFIG.1are closed by the third controller148ofFIG.1. The first repeater upstream high-speed termination304represents the switches156and160being closed as a logic high and open as a logic low. The first repeater upstream high-speed termination304represents the state of the upstream circuitry142. A transition of the first repeater upstream high-speed termination304indicates that either the USB repeater circuitry106is determining the state of the primary device102or the operation mode of the secondary device104has transitioned from one mode to another.

The first upstream termination detection enable306is configured to represent whether or not the high-speed termination detection circuitry168is enabled. The first upstream termination detection enable306represents the high-speed termination detection circuitry168being closed as a logic high and open as a logic low. The first upstream termination detection enable306represents the duration in which the termination indication terminals228and232may be used to indicate whether or not the switches114and118are closed by the primary device102.

The first upstream termination detection output308is configured to represent the termination indication terminals228and232. The first upstream termination detection output308represents the termination indication terminals228and232indicating enabled pulldown circuitry on the USB terminals150and152ofFIGS.1and2as a logic low and no pulldown circuitry on the USB terminals150and152as a logic high. The first upstream termination detection output308indicates determining the operation of the primary device102being high-speed mode as a logic high and another mode as logic low.

The first repeater downstream high-speed termination310is configured to represent whether or not the switches176and180ofFIG.1of the downstream circuitry144are closed by the third controller148. The first repeater downstream high-speed termination310represents the switches176and180being closed as a logic high and open as a logic low. The first repeater downstream high-speed termination310is configured to replicate the mode of the primary device102. For example, the first repeater downstream high-speed termination310is a logic high to replicate the primary device102operating in high-speed mode. A transition in the first repeater downstream high-speed termination310indicates that the high-speed termination detection circuitry168determined the primary device102has opened or closed the switches114and118.

The first secondary device high-speed termination312is configured to represent whether or not the switches128and132of the secondary device104are closed by the second controller140ofFIG.1. The first secondary device high-speed termination312represents the switches128and132being closed as a logic high and opened as a logic low. The first secondary device high-speed termination312represents the state of the secondary device104. A transition of the first secondary device high-speed termination312indicates that either the secondary device104is determining the state of the downstream circuitry144or the operation mode of the secondary device104has transitioned from one mode to another.

The first secondary device pullup314is configured to represent whether or not the fifth switch134of the secondary device104is closed by the second controller140. The first secondary device pullup314represents the fifth switch134being closed as a logic high and open as a logic low. A transition of the first secondary device pullup314indicates that either the secondary device104is determining the state of the downstream circuitry144or the operation mode of the secondary device104has transitioned into full speed mode.

The first USB terminal voltage316is configured to represent the voltage of the USB terminals108and110. The first USB terminal voltage316is configured to indicate that the operation mode of the primary device102, such that a voltage approximately equal to a common potential (e.g., ground) represents high-speed mode and the voltage approximately equal to the first voltage supply138ofFIG.1represents full speed mode.

At an example first time318, the USB communication system100completes a data transmission in high-speed mode. At a second time320, the USB repeater circuitry106configures the upstream circuitry142to determine the state of the primary device102as a result of determining that there has not been a data transmission in approximately 1.5-2.5 milliseconds (mS). At the second time320, the first repeater upstream high-speed termination304transitions from a logic high to a logic low to indicate that the third controller148opened the switches156and160. At the second time320, the first upstream termination detection enable306transitions from a logic low to a logic high to indicate that the third controller148has enabled the high-speed termination detection circuitry168to determine whether the first host high-speed termination302is a logic high or logic low.

At a third time322, the first secondary device high-speed termination312transitions from a logic high to a logic low to indicate that the second controller140opened the switches128and132. At the third time322, the first secondary device pullup314transitions from a logic low to a logic high to indicate that the second controller140closed the fifth switch134to pullup the third USB terminal122. At the third time322the secondary device104transitions its circuitry to determine whether or not the first repeater downstream high-speed termination310is a logic low. The secondary device104is configured to perform the operations of the third time322as a result of determining that there has not been a data transmission in approximately 3-3.125 milliseconds (mS).

At a fourth time324, the secondary device104is configured to determine whether the first USB terminal voltage316is approximately equal to the voltage of the first voltage supply138or the common potential. At the fourth time324the secondary device104determines whether the primary device102is in a reset state or in a suspend state. Advantageously, the USB repeater circuitry106replicated the state of the primary device102using the downstream circuitry144before the fourth time324.

FIG.3Bis a second timing diagram326of an example operation to detect and replicate a suspend state using the USB repeater circuitry106ofFIG.1including the high-speed termination detection circuitry168ofFIGS.1and2. In the example ofFIG.3B, the second timing diagram326includes a second host high-speed termination328, a second repeater upstream high-speed termination330, a second upstream termination detection enable332, a second upstream termination detection output334, a second repeater downstream high-speed termination336, a second secondary device high-speed termination338, a second secondary device pullup340, and a second USB terminal voltage (DP/DM)342. The second timing diagram326represents the operations of the USB communications system100during an example transition of the primary device102into a suspend state, such that the operation mode of the primary device102transitions high-speed mode to full speed mode.

In the example ofFIG.3B, the second host high-speed termination328is configured in a similar manner as the first host high-speed termination302. The second repeater upstream high-speed termination330is configured in a similar manner as the first repeater upstream high-speed termination304. The second upstream termination detection enable332is configured in a similar manner as the first upstream termination detection enable306. The second upstream termination detection output334is configured in a similar manner as the first upstream termination detection output308. The second repeater downstream high-speed termination336is configured in a similar manner as the first repeater downstream high-speed termination310. The second secondary device high-speed termination338is configured in a similar manner as the first secondary device high-speed termination312. The second secondary device pullup340is configured in a similar manner as the first secondary device pullup314. The second USB terminal voltage342is configured in a similar manner as the first USB terminal voltage316.

At a fifth time344, the USB communication system100completes a data transmission in high-speed mode before the USB communication system100transitions to full speed mode. At a sixth time346, the second host high-speed termination328transitions from a logic high to a logic low to indicate that the first controller120ofFIG.1opens the switches114and118. At the sixth time346, the primary device102enters suspend state which indicates a transition from high-speed mode to full speed mode.

At a seventh time348, the USB repeater circuitry106configures the upstream circuitry142to determine the state of the primary device102as a result of determining that there has not been a data transmission in approximately 1.5-2.5 milliseconds (mS). At the seventh time348, the second repeater upstream high-speed termination330transitions from a logic high to a logic low to indicate that the third controller148opened the switches156and160. At the seventh time348, the second upstream termination detection enable332transitions from a logic low to a logic high to indicate that the third controller148has enabled the high-speed termination detection circuitry168to determine whether the second host high-speed termination328is a logic high or logic low. Immediately following the seventh time348, the second upstream termination detection output334transitions from a logic high to a logic low to indicate that the high-speed termination detection circuitry168determined that the second host high-speed termination328is a logic low.

At an eighth time350, the second repeater downstream high-speed termination336transitions from a logic high to a logic low. At the eighth time350, the third controller148opens the switches176and180to replicate the primary device102opening the switches114and118. Immediately following the eighth time350, the secondary device104may accurately determine whether the primary device102is in reset or suspend state.

At a ninth time352, the second secondary device high-speed termination338transitions from a logic high to a logic low to indicate that the second controller140disabled the switches128and132. At the ninth time352, the second secondary device pullup340transitions from a logic low to a logic high to indicate that the second controller140closed the fifth switch134to pullup the third USB terminal122. At the ninth time352the secondary device104transitions its circuitry to determine whether or not the second repeater downstream high-speed termination336is a logic low. The secondary device104is configured to perform the operations of the ninth time352as a result of determining that there has not been a data transmission in approximately 3-3.125 milliseconds (mS).

At a tenth time354, the secondary device104is configured to determine whether the second USB terminal voltage342is approximately equal to the voltage of the first voltage supply138or the common potential. At the tenth time354the secondary device104determines whether the primary device102is in a reset state or in a suspend state. Advantageously, the USB repeater circuitry106replicated the state of the primary device102using the downstream circuitry144before the tenth time354.

FIG.4is a flowchart representative of an example process that may be performed using machine readable instructions that can be executed and/or hardware configured to implement the USB repeater circuitry106ofFIG.1, and/or, more generally, the high-speed termination detection circuitry168ofFIGS.1and2to determine and/or replicate the state of the primary device102ofFIG.1. The machine-readable instructions and/or the operations400ofFIG.4begin at block405, at which the USB repeater circuitry106determines if the primary device is idle.

At block405, the USB repeater circuitry106determines, based on the third controller148ofFIG.1and the logic isolation circuitry146, whether or not there has been any USB communication within a set duration, such as to determine whether or not the primary device102is idle. For example, the logic isolation circuitry146is configured to reset a timer in the third controller148every time there is a USB communication. In such an example, the third controller148is configured to determine the primary device102is idle as a result of the timer reaching 1.5 to 2.5 milliseconds (mS). The block405corresponds to the times320and348ofFIGS.3A and3B, respectively. The duration used to determine whether the primary device102is idle may depend on a USB protocol (e.g., USB 2.0 protocol which is incorporated herein in its entirety). For example, the third controller148may determine that the primary device102is idle as a result of a duration greater than 125 microseconds (μS) since the last USB communication.

If at block405, the third controller148determines that the primary device102is not idle, then the third controller148is configured to wait for the primary device102to be idle. If at block405, the third controller148determines that the primary device102is idle, then the process continues to block410.

At block410, the third controller148disables the upstream high-speed (HS) termination. At block410, the third controller148opens the switches156and160of the upstream circuitry142ofFIG.1, such that the USB terminals150and152are not pulled down by the upstream circuitry142. At block410, the upstream circuitry142is transitioning from high-speed mode to determine whether or not the USB terminals150and152are being pulled down by the primary device102. The block410corresponds to the times320and348ofFIGS.3A and3B, respectively. At block410, the USB repeater circuitry106may no longer be able to determine whether or not there is high-speed USB communications as a result of the high-speed circuitry being removed in the upstream circuitry142. The process proceeds to block415.

At block415, the third controller148enables the high-speed termination detection circuitry168. At block415, the third controller148enables either the first current mode driver206and/or the second current mode driver212to supply a current to the USB terminals150and152. The block415corresponds to the times320and348ofFIGS.3A and3B, respectively. The process proceeds to block420.

At block420, the high-speed termination detection circuitry168determines whether or not the primary device high-speed termination is enabled. At block420, the third controller148determines whether the termination indication terminals228and232ofFIG.2are equal to a logic high or a logic low. For example, the third controller148determines that the high-speed termination is enabled as a result of the termination indication terminals228and232being a logic high. The block420corresponds to a time immediately following the times320and348.

If at block420, the third controller148determines that the primary device102has the high-speed termination enabled, then the third controller148determines that the primary device102is in a reset state and ends the process. Alternatively, the third controller148may be configured to end the process after determining a chirp voltage on the USB terminals170and172as a result of the secondary device104supplying a test current to the USB terminals122and124. If at block420the third controller148determines that the primary device102has the high-speed termination disabled, then the process proceeds to block425.

At block425, the third controller148disables the downstream high-speed termination. At block425, the third controller148opens the switches176and180of the downstream circuitry144ofFIG.1, such that the USB terminals170and172are not pulled down by the downstream circuitry144. At block425, the downstream circuitry144is transitioning from high-speed mode to full speed mode to replicate the transition of the primary device102to suspend state. The block425corresponds to the eighth time350ofFIG.3B. The process proceeds to block430.

At block430, the third controller148waits for a downstream pullup to be enabled. At block430, the third controller148is configured to wait for the second controller140to close the fifth switch134ofFIG.1, such that the third USB terminal122ofFIG.1is pulled up by the fifth resistor136ofFIG.1. The logic isolation circuitry146ofFIG.1may be configured to determine that the secondary device104was disconnected from the USB repeater circuitry106as a result of waiting for the downstream pullup for a duration greater than a threshold. The process proceeds to block435.

At block435, the third controller148enables the upstream pullup. At block435, the third controller148closes the eighth switch162, such that the eighth resistor164pulls up the fifth USB terminal150. At block435, the third controller148is configuring the upstream circuitry142for full speed mode as a result of determining that the primary device102entered suspend state. At block435, the USB communication system100is configured to operate in full speed mode. The process proceeds to end.

Although example methods are described with reference to the flowchart illustrated inFIG.4, many other methods of high-speed termination detection may alternatively be used in accordance with the in accordance with this description. For example, the order of execution of the blocks may be changed, and/or some of the blocks described may be changed, eliminated, or combined. Similarly, additional operations may be included in the manufacturing process before, in between, or after the blocks shown in the illustrated examples.

FIG.5is a schematic diagram of a conventional USB communication system500. The conventional USB communication system500includes a primary device502and a secondary device504. The conventional USB communication system500is configured for USB communication between the primary device502and the secondary device504.

The primary device502includes a first USB terminal506, a second USB terminal508, a first resistor510, a first switch512, a second resistor514, and a second switch516. The primary device502is configured to transmit data to the secondary device504through the USB terminals506and508. Alternatively, the primary device502is configured to receive data from the secondary device504through the USB terminals506and508.

The first resistor510is coupled between the first USB terminal506and the first switch512. The first switch512is coupled between the first resistor510and a common potential (e.g., ground). The first resistor510and the first switch512are configured to pulldown the first USB terminal506. The second resistor514is coupled between the second USB terminal508and the second switch516. The second switch516is coupled between the second resistor514and common potential. The second resistor514and the second switch516are configured to pulldown the second USB terminal508.

The secondary device504includes a third USB terminal518, a fourth USB terminal520, a third resistor522, a third switch524, a fourth resistor526, a fourth switch528, a fifth switch530, a fifth resistor532, and a voltage supply534. The secondary device504is configured to transmit data to the primary device502through the USB terminals518and520. Alternatively, the secondary device504is configured to receive data from the primary device502through the USB terminals518and520.

The third resistor522is coupled between the third USB terminal518and the third switch524. The third switch524is coupled between the third resistor522and common potential. The third resistor522and the third switch524are configured to pulldown the third USB terminal518. The fourth resistor526is coupled between the fourth USB terminal520and the fourth switch528. The fourth switch528is coupled between the fourth resistor526and common potential. The fourth resistor526and the fourth switch528are configured to pulldown the fourth USB terminal520.

The fifth switch530is coupled between the third USB terminal518and the fifth resistor532. The fifth resistor532is coupled between the fifth switch530and the voltage supply534. The fifth switch530and the fifth resistor532are configured to pullup the third USB terminal518based on the value of the voltage supply534.

In example operation, the primary device502begins operation in full speed mode, such that the switches512and516are opened. The secondary device504begins operation in full speed mode, such that the switches524and528are opened and the fifth switch530is closed.

In example operation, the primary device502determines if the secondary device504is high-speed capable by ending data transmissions before closing the switches512and516. The secondary device504determines that the primary device502closed the switches512and516as a result of determining the voltage of the USB terminals518and520changed. The secondary device504opens the fifth switch530and closes the switches524and528as a result of the USB terminals518and520being pulled down by the primary device502. The USB communication system500is configured to high-speed mode as a result of the fifth switch530being opened and the switches512,516,524, and528being closed.

In example operation, the primary device502stops transmitting data in high-speed mode before opening the switches512and516. The secondary device504opens the switches524and528and closes the fifth switch530as a response to determining a duration of time passed since the primary device502has transmitted data. The secondary device504determines the voltage of the USB terminals518and520to determine whether the primary device is pulling down the USB terminals518and520. The secondary device504may open the fifth switch530and close the switches524and528as a result of determining the primary device502is pulling down the USB terminals518and520. The secondary device504may begin to communicate with the primary device502as a result of determining the primary device502is not pulling down the USB terminals518and520.

FIG.6Ais a first timing diagram600of an operation to detect a reset using the conventional USB communication system500ofFIG.5. The first timing diagram600includes a first host high-speed termination602, a first secondary device high-speed termination604, a first secondary device pullup606, and a first USB terminal voltage (DP/DM)608. The first timing diagram600is configured to represent the operation of the conventional USB communication system500during an example operation to determine whether the first host high-speed termination602is a logic high or a logic low. The operation of the first timing diagram600is configured to determine whether the state of the primary device502ofFIG.5is a suspend state or a reset state. The first timing diagram600represents the operations of the USB communication system500to remain in high-speed mode, such that the secondary device504ofFIG.5determines that the primary device502ofFIG.5is in the reset state.

The first host high-speed termination602is configured to represent whether the switches512and516ofFIG.5are opened or closed, such that the first host high-speed termination602represents whether or not the USB terminals506and508ofFIG.5are being pulled down. The first host high-speed termination602is configured to represent the switches512and516being closed as a logical high (HI) and being open as a logical low (LO).

The first secondary device high-speed termination604is configured to represent whether the switches524and528ofFIG.5are opened or closed, such that the first secondary device high-speed termination604represents whether or not the USB terminals518and520ofFIG.5are being pulled down. The first secondary device high-speed termination604is configured to represent the switches524and528being closed as a logical high and being open as a logical low.

The first secondary device pullup606is configured to represent whether the fifth switch530ofFIG.5is open or closed, such that the first secondary device pullup606represents whether or not the third USB terminal518is being pulled up towards the value of the voltage supply534ofFIG.5. The first secondary device pullup606is configured to represent the fifth switch530being closed as a logical high and being open as a logical low.

The first USB terminal voltage608is configured to represent a voltage of the USB terminals506,508,518, and520. The first USB terminal voltage608is approximately equal to common potential (e.g., ground) as a result of the USB terminals506,508,518, and520being pulled down. The first USB terminal voltage608is approximately equal to the voltage of the voltage supply534as a result of the USB terminals506,508,518, and520being pulled up by the secondary device504.

At a first time610, the primary device502finishes a high-speed USB communication with the secondary device504. At a second time612, the first secondary device high-speed termination604transitions from a logical high to a logical low as a result of the secondary device504determining that there has been no USB communication in approximately 3-3.125 milliseconds (mS). The transition of the first secondary device high-speed termination604at the second time612represents the secondary device504disabling the circuitry to pulldown the USB terminals518and520. At the second time612, the first secondary device pullup606transitions from a logical low to a logical high to represent the secondary device504attempting to determine whether the first host high-speed termination602is a logical high or a logical low.

At a third time614, the secondary device504determines whether the first host high-speed termination602is a logical high or a logical low, such that the secondary device504may determine the state of the primary device502. At the third time614, the secondary device504measures the voltage of the first USB terminal voltage608, such the secondary device504determines that the primary device502is in the reset state.

FIG.6Bis a second timing diagram616of an operation to detect a high-speed termination using the conventional USB communication system500ofFIG.5. The second timing diagram616includes a second host high-speed termination618, a second secondary device high-speed termination620, a second secondary device pullup622, and a second USB terminal voltage (DP/DM)624. The second timing diagram616is configured to represent the operation of the conventional USB communication system500during an example operation to determine whether the second host high-speed termination618is a logic high or a logic low. The operation of the second timing diagram616is configured to determine whether the state of the primary device502ofFIG.5is a suspend state (L2) or a reset state. The second timing diagram616represents the operations of the USB communication system500to remain in high-speed mode, such that the secondary device504ofFIG.5determines that the primary device502ofFIG.5is in the suspend state.

The second host high-speed termination618is configured to represent whether the switches512and516ofFIG.5are open or closed, such that the second host high-speed termination618represents whether or not the USB terminals506and508ofFIG.5are being pulled down. The second host high-speed termination618is configured to represent the switches512and516being enabled as a logical high (HI) and being disabled as a logical low (LO).

The second secondary device high-speed termination620is configured to represent whether the switches524and528ofFIG.5are open or closed, such that the second secondary device high-speed termination620represents whether or not the USB terminals518and520ofFIG.5are being pulled down. The second secondary device high-speed termination620is configured to represent the switches524and528being closed as a logical high and being open as a logical low.

The second secondary device pullup622is configured to represent whether the fifth switch530ofFIG.5is enabled or disabled, such that the second secondary device pullup622represents whether or not the third USB terminal518is being pulled up towards the value of the voltage supply534ofFIG.5. The second secondary device pullup622is configured to represent the fifth switch530being closed as a logical high and being open as a logical low.

The second USB terminal voltage624is configured to represent a voltage of the USB terminals506,508,518, and520. The second USB terminal voltage624is approximately equal to common potential (e.g., ground) as a result of the USB terminals506,508,518, and520being pulled down. The second USB terminal voltage624is approximately equal to the voltage of the voltage supply534as a result of the USB terminals506,508,518, and520being pulled up by the secondary device504.

At a fourth time626, the primary device502finishes a high-speed USB communication with the secondary device504. At a fifth time628, the second host high-speed termination618transitions from a logical high to a logical low to represent a change in state of the primary device502to the suspend state.

At a sixth time630, the second secondary device high-speed termination620transitions from a logical high to a logical low as a result of the secondary device504determining that there has been no USB communication in approximately 3-3.125 milliseconds (mS). The transition of the second secondary device high-speed termination620at the sixth time630represents the secondary device504disabling the circuitry to pulldown the USB terminals518and520. At the sixth time630, the second secondary device pullup622transitions from a logical low to a logical high to represent the secondary device504attempting to determine whether the second host high-speed termination618is a logical high or a logical low.

At a seventh time632, the secondary device504determines whether the second host high-speed termination618is a logical high or a logical low, such that the secondary device504may determine the state of the primary device502. At the seventh time632, the secondary device504measures the voltage of the second USB terminal voltage624, such the secondary device504determines that the primary device502is in the suspend state.

FIG.7is a block diagram of an example processing platform including processor circuitry structured to execute the example machine readable instructions and/or the example operations ofFIG.4to implement the USB repeater circuitry106ofFIG.1. The processor platform700can be, for example, a server, a personal computer, a workstation, a self-learning machine (e.g., a neural network), a mobile device (e.g., a cell phone, a smart phone, a tablet such as an iPad™), a personal digital assistant (PDA), an Internet appliance, a DVD player, a CD player, a digital video recorder, a Blu-ray player, a gaming console, a personal video recorder, a set top box, a headset (e.g., an augmented reality (AR) headset, a virtual reality (VR) headset, etc.) or other wearable device, or any other type of computing device.

The processor platform700of the illustrated example includes processor circuitry712. The processor circuitry712of the illustrated example is hardware. For example, the processor circuitry712can be implemented by one or more integrated circuits, logic circuits, FPGAs, microprocessors, CPUs, GPUs, DSPs, and/or microcontrollers from any desired family or manufacturer. The processor circuitry712may be implemented by one or more semiconductor based (e.g., silicon based) devices. In this example, the processor circuitry712includes the logic isolation circuitry146ofFIG.1and the third controller148ofFIG.1. In this example, the processor circuitry712implements the blocks405-430ofFIG.4.

The processor circuitry712of the illustrated example includes a local memory713(e.g., a cache, registers, etc.). The processor circuitry712of the illustrated example is in communication with a main memory including a volatile memory714and a non-volatile memory716by a bus718. The volatile memory714may be implemented by Synchronous Dynamic Random-Access Memory (SDRAM), Dynamic Random-Access Memory (DRAM), RAMBUS® Dynamic Random Access Memory (RDRAM®), and/or any other type of RAM device. The non-volatile memory716may be implemented by flash memory and/or any other desired type of memory device. Access to the main memory714,716of the illustrated example is controlled by a memory controller717. The logic isolation circuitry146and the third controller148may be coupled to the bus718.

The processor platform700of the illustrated example also includes interface circuitry720. The interface circuitry720may be implemented by hardware in accordance with any type of interface standard, such as an Ethernet interface, a universal serial bus (USB) interface, a Bluetooth® interface, a near field communication (NFC) interface, a Peripheral Component Interconnect (PCI) interface, and/or a Peripheral Component Interconnect Express (PCIe) interface. The interface circuitry720may be configured to include the logic isolation circuitry146and/or the third controller148.

In the illustrated example, one or more input devices722are connected to the interface circuitry720. The input device(s)722permit(s) a user to enter data and/or commands into the processor circuitry712. The input device(s)722can be implemented by, for example, an audio sensor, a microphone, a camera (still or video), a keyboard, a button, a mouse, a touchscreen, a track-pad, a trackball, an isopoint device, and/or a voice recognition system.

One or more output devices724are also connected to the interface circuitry720of the illustrated example. The output device(s)724can be implemented, for example, by display devices (e.g., a light emitting diode (LED), an organic light emitting diode (OLED), a liquid crystal display (LCD), a cathode ray tube (CRT) display, an in-place switching (IPS) display, a touchscreen, etc.), a tactile output device, a printer, and/or speaker. The interface circuitry720of the illustrated example, thus, typically includes a graphics driver card, a graphics driver chip, and/or graphics processor circuitry such as a GPU.

The interface circuitry720of the illustrated example also includes a communication device such as a transmitter, a receiver, a transceiver, a modem, a residential gateway, a wireless access point, and/or a network interface to facilitate exchange of data with external machines (e.g., computing devices of any kind) by a network726. The communication can be by, for example, an Ethernet connection, a digital subscriber line (DSL) connection, a telephone line connection, a coaxial cable system, a satellite system, a line-of-site wireless system, a cellular telephone system, an optical connection, etc.

The processor platform700of the illustrated example also includes one or more mass storage devices728to store software and/or data. Examples of such mass storage devices728include magnetic storage devices, optical storage devices, floppy disk drives, HDDs, CDs, Blu-ray disk drives, redundant array of independent disks (RAID) systems, solid state storage devices such as flash memory devices and/or SSDs, and DVD drives.

The machine executable instructions732, which may be implemented by the machine-readable instructions ofFIG.4may be stored in the mass storage device728, in the volatile memory714, in the non-volatile memory716, and/or on a removable non-transitory computer readable storage medium such as a CD or DVD.

In this description, the term “and/or” (when used in a form such as A, B and/or C) refers to any combination or subset of A, B, C, such as: (a) A alone; (b) B alone; (c) C alone; (d) A with B; (e) A with C; (f) B with C; and (g) A with B and with C. Also, as used herein, the phrase “at least one of A or B” (or “at least one of A and B”) refers to implementations including any of: (a) at least one A; (b) at least one B; and (c) at least one A and at least one B.

The term “couple” is used throughout the specification. The term may cover connections, communications, or signal paths that enable a functional relationship consistent with this description. For example, if device A provides a signal to control device B to perform an action, in a first example device A is coupled to device B, or in a second example device A is coupled to device B through intervening component C if intervening component C does not substantially alter the functional relationship between device A and device B such that device B is controlled by device A via the control signal provided by device A.

A device that is “configured to” perform a task or function may be configured (e.g., programmed and/or hardwired) at a time of manufacturing by a manufacturer to perform the function and/or may be configurable (or re-configurable) by a user after manufacturing to perform the function and/or other additional or alternative functions. The configuring may be through firmware and/or software programming of the device, through a construction and/or layout of hardware components and interconnections of the device, or a combination thereof

As used herein, the terms “terminal”, “node”, “interconnection”, “pin” and “lead” are used interchangeably. Unless specifically stated to the contrary, these terms are generally used to mean an interconnection between or a terminus of a device element, a circuit element, an integrated circuit, a device or other electronics or semiconductor component.

A circuit or device that is described herein as including certain components may instead be adapted to be coupled to those components to form the described circuitry or device. For example, a structure described as including one or more semiconductor elements (such as transistors), one or more passive elements (such as resistors, capacitors, and/or inductors), and/or one or more sources (such as voltage and/or current sources) may instead include only the semiconductor elements within a single physical device (e.g., a semiconductor die and/or integrated circuit (IC) package) and may be adapted to be coupled to at least some of the passive elements and/or the sources to form the described structure either at a time of manufacture or after a time of manufacture, for example, by an end-user and/or a third-party.

While the use of particular transistors are described herein, other transistors (or equivalent devices) may be used instead with little or no change to the remaining circuitry. For example, a metal-oxide-silicon FET (“MOSFET”) (such as an n-channel MOSFET, nMOSFET, or a p-channel MOSFET, pMOSFET), a bipolar junction transistor (BJT—e.g. NPN or PNP), insulated gate bipolar transistors (IGBTs), and/or junction field effect transistor (JFET) may be used in place of or in conjunction with the devices disclosed herein. The transistors may be depletion mode devices, drain-extended devices, enhancement mode devices, natural transistors or other type of device structure transistors. Furthermore, the devices may be implemented in/over a silicon substrate (Si), a silicon carbide substrate (SiC), a gallium nitride substrate (GaN) or a gallium arsenide substrate (GaAs). While some example embodiments may implement certain elements/circuits in an integrated circuit while other elements are external to the integrated circuit, in other example embodiments, additional or fewer features may be incorporated into the integrated circuit. In addition, some or all of the features that are external to the integrated circuit may be included in the integrated circuit and/or some features illustrated as being internal to the integrated circuit may be incorporated outside of the integrated. As used herein, the term “integrated circuit” means one or more circuits that are: (i) incorporated in/over a semiconductor substrate; (ii) incorporated in a single semiconductor package; (iii) incorporated into the same module; and/or (iv) incorporated in/on the same printed circuit board

Circuits described herein are reconfigurable to include the replaced components to provide functionality at least partially similar to functionality available prior to the component replacement. Components shown as resistors, unless otherwise stated, are generally representative of any one or more elements coupled in series and/or parallel to provide an amount of impedance represented by the shown resistor. For example, a resistor or capacitor shown and described herein as a single component may instead be multiple resistors or capacitors, respectively, coupled in parallel between the same nodes. For example, a resistor or capacitor shown and described herein as a single component may instead be multiple resistors or capacitors, respectively, coupled in series between the same two nodes as the single resistor or capacitor.

Uses of the phrase “ground” in the foregoing description include a chassis ground, an Earth ground, a floating ground, a virtual ground, a digital ground, a common ground, and/or any other form of ground connection applicable to, or suitable for, the teachings of this description. Unless otherwise stated, “about,” “approximately,” or “substantially” preceding a value means +/−10 percent of the stated value.

Modifications are possible in the described embodiments, and other embodiments are possible, within the scope of the claims.