mhurhangee/patent-ind-claim-en huggingface dataset:
A bus node comprising - a first logic unit , comprising a bus connection , - a second logic unit , - a monitoring circuit , - a transmission unit , - a first test line , and - a media access controller , wherein the bus node is designed such that in a communication phase the first logic unit communicates via the transmission unit and the media access controller with a bus , wherein the bus node is designed such that, in the event of a fault, the monitoring circuit sends a monitoring signal (SU) to the transmission unit such that the transmission unit blocks communication, wherein the bus node comprises a first test line , wherein the first and/or the second logic unit is/are coupled via the first test line to the monitoring circuit for outputting a first test signal (ST1) to the monitoring circuit , wherein the bus connection is coupled via the transmission unit to the media access controller , and wherein the media access controller is connected to the bus . - a first logic unit , comprising a bus connection , - a second logic unit , - a monitoring circuit , - a transmission unit , - a first test line , and - a media access controller , wherein the bus node is designed such that in a communication phase the first logic unit communicates via the transmission unit and the media access controller with a bus , wherein the bus node is designed such that, in the event of a fault, the monitoring circuit sends a monitoring signal (SU) to the transmission unit such that the transmission unit blocks communication, wherein the bus node comprises a first test line , wherein the first and/or the second logic unit is/are coupled via the first test line to the monitoring circuit for outputting a first test signal (ST1) to the monitoring circuit , wherein the bus connection is coupled via the transmission unit to the media access controller , and wherein the media access controller is connected to the bus . wherein the bus node is designed such that in a communication phase the first logic unit communicates via the transmission unit and the media access controller with a bus , wherein the bus node is designed such that, in the event of a fault, the monitoring circuit sends a monitoring signal (SU) to the transmission unit such that the transmission unit blocks communication, wherein the bus node comprises a first test line , wherein the first and/or the second logic unit is/are coupled via the first test line to the monitoring circuit for outputting a first test signal (ST1) to the monitoring circuit , wherein the bus connection is coupled via the transmission unit to the media access controller , and wherein the media access controller is connected to the bus .
A belt for suspending and/or driving an elevator car , comprising: a plurality of tension elements extending longitudinally along a length of the belt , at least one tension element of the plurality of tension elements having multiple tension element coating layers applied thereto; a plurality of fibers interlaced with the plurality of tension elements forming a composite belt structure; and a belt coating at least partially encapsulating the composite belt structure, characterized in that the multiple tension element coating layers include an adhesive layer to promote adhesion of the tension element coating layers to the tension element. a plurality of tension elements extending longitudinally along a length of the belt , at least one tension element of the plurality of tension elements having multiple tension element coating layers applied thereto; a plurality of fibers interlaced with the plurality of tension elements forming a composite belt structure; and a belt coating at least partially encapsulating the composite belt structure, characterized in that the multiple tension element coating layers include an adhesive layer to promote adhesion of the tension element coating layers to the tension element.
A lithium air battery comprising an air electrode, a negative electrode containing a lithium metal, and a non-aqueous electrolyte interposed between the air electrode and the negative electrode, wherein: the non-aqueous electrolyte contains an organic solvent and a lithium salt, wherein: the lithium salt contains at least LiX (where X stands for Br and/or I) and lithium nitrate, a molar concentration (mol/L) of the LiX in the non-aqueous electrolyte satisfies a range of no less than 0.005 to no greater than 2.0, and a molar concentration (mol/L) of the lithium nitrate in the non-aqueous electrolyte satisfies a range of greater than 0.1 to no greater than 2.0. the lithium salt contains at least LiX (where X stands for Br and/or I) and lithium nitrate, a molar concentration (mol/L) of the LiX in the non-aqueous electrolyte satisfies a range of no less than 0.005 to no greater than 2.0, and a molar concentration (mol/L) of the lithium nitrate in the non-aqueous electrolyte satisfies a range of greater than 0.1 to no greater than 2.0.
A computer implemented data processing method of using a dynamic anatomic atlas for matching a patient image and an atlas image or for matching two patient images, comprising the following step: • an information on a dynamic property of at least one atlas segment is used as a constraint for the matching, wherein the dynamic anatomic atlas comprises • static atlas data describing atlas segments ; and • dynamic atlas data comprising the information on the dynamic property which information is respectively linked to the atlas segments . • an information on a dynamic property of at least one atlas segment is used as a constraint for the matching, wherein the dynamic anatomic atlas comprises • static atlas data describing atlas segments ; and • dynamic atlas data comprising the information on the dynamic property which information is respectively linked to the atlas segments .
A method of hiding at least one logical processor in a computer having a plurality of logical processors , the logical processor including a CPU IC, a CPU IC core, or a thread on core, the method comprising: initializing the plurality of logical processors by executing a pre-boot routine in system firmware ; identifying at least one logical processor of the plurality of logical processors to be hidden from an operating system, OS, of the computer to provide at least one hidden logical processor and at least one visible logical processor; placing each of the at least one hidden logical processor into a system management mode, SMM, by executing a park routine in the system firmware wherein the park routine ensures that each of the at least one hidden logical processor stays in system management mode after executing the park routine; and booting the OS of the computer to use the at least one visible logical processor, wherein, once the OS is booted, the at least one hidden logical processor will not be visible to the OS and cannot be interrupted; the method further comprising: the OS signaling a global system management interrupt, SMI, to cause the plurality of logical processors to be placed into SMM; handling the global SMI using an SMI handler routine in the system firmware ; and returning the at least one visible logical processor for use by the OS . initializing the plurality of logical processors by executing a pre-boot routine in system firmware ; identifying at least one logical processor of the plurality of logical processors to be hidden from an operating system, OS, of the computer to provide at least one hidden logical processor and at least one visible logical processor; placing each of the at least one hidden logical processor into a system management mode, SMM, by executing a park routine in the system firmware wherein the park routine ensures that each of the at least one hidden logical processor stays in system management mode after executing the park routine; and booting the OS of the computer to use the at least one visible logical processor, wherein, once the OS is booted, the at least one hidden logical processor will not be visible to the OS and cannot be interrupted; the method further comprising: the OS signaling a global system management interrupt, SMI, to cause the plurality of logical processors to be placed into SMM; handling the global SMI using an SMI handler routine in the system firmware ; and returning the at least one visible logical processor for use by the OS . the OS signaling a global system management interrupt, SMI, to cause the plurality of logical processors to be placed into SMM; handling the global SMI using an SMI handler routine in the system firmware ; and returning the at least one visible logical processor for use by the OS .
A remote controlled demolition robot comprising a controller and at least one control switch for providing a control signal that is received by the controller , wherein the controller is configured to control the operation of a corresponding robot part , wherein the controller is further configured to: receive a pressure sensor reading from a pressure sensor for a proportional hydraulic valve , said pressure sensor reading indicating a standby pressure; provide the control signal to the valve ; increase a signal level of the control signal provided to the valve until a change in the pressure is detected; and determine a starting offset for the valve , said starting offset corresponding to the current signal level of the control signal, characterized in that the controller further is configured to determine a real-life offset line (A) for opening the valve , by aligning the starting offset with a top signal level, wherein the offset also is dependent on the actual valve position. receive a pressure sensor reading from a pressure sensor for a proportional hydraulic valve , said pressure sensor reading indicating a standby pressure; provide the control signal to the valve ; increase a signal level of the control signal provided to the valve until a change in the pressure is detected; and determine a starting offset for the valve , said starting offset corresponding to the current signal level of the control signal, characterized in that the controller further is configured to determine a real-life offset line (A) for opening the valve , by aligning the starting offset with a top signal level, wherein the offset also is dependent on the actual valve position.
A workpiece transfer apparatus for transferring workpieces (W) to or from a machine, comprising a crossbar member on which a workpiece holding member is provided, the workpiece holding member being configured to hold the workpieces (W), wherein the apparatus further comprises: a frame ; a member supported by the frame and configured to move relative to the frame ; and an arm supported by the member and configured to move relative to the member and back and forth in a transferring direction; wherein the crossbar member comprises first and second crossbars respectively coupled to the arm which extend in opposite directions from the arm ; and wherein the workpiece holding member includes first and second workpiece holding devices , each being configured to hold a workpiece (W); characterised in that the arm is provided with first and second tilt drive devices configured to independently rotate respective first and second crossbars and respective workpiece holding devices around longitudinal axes of the respective first and second crossbars . a frame ; a member supported by the frame and configured to move relative to the frame ; and an arm supported by the member and configured to move relative to the member and back and forth in a transferring direction; wherein the crossbar member comprises first and second crossbars respectively coupled to the arm which extend in opposite directions from the arm ; and wherein the workpiece holding member includes first and second workpiece holding devices , each being configured to hold a workpiece (W); characterised in that the arm is provided with first and second tilt drive devices configured to independently rotate respective first and second crossbars and respective workpiece holding devices around longitudinal axes of the respective first and second crossbars .
An exercise assist device for providing movement of a sacroiliac joint by extending a hip joint transitively, which exercise assist device comprises: a member onto which a thigh is placed in a lateral decubitus position, wherein the member is a stand , and wherein the thigh is an upper thigh of a human subject in a lateral decubitus position, wherein the stand is adapted to move toward a back of the human subject without exercise of voluntary muscles of the human subject, the exercise assist device further comprising a pad , wherein the stand is connected to a movable arm extending from a strut , the strut extending in a direction substantially orthogonal to a longitudinal axis of the human subject, wherein the pad is a sacrum support pad being adapted to support an area corresponding to the sacrum of the human subject behind a back of the human subject, and the member is adapted to support the thigh at a front part of the thigh, characterized in that the sacrum support pad is configured to support the sacrum so that the upper thigh, an upper iliac bone and the sacrum of the human subject are moved in the lateral decubitus position toward the back of the human subject. a member onto which a thigh is placed in a lateral decubitus position, wherein the member is a stand , and wherein the thigh is an upper thigh of a human subject in a lateral decubitus position, wherein the stand is adapted to move toward a back of the human subject without exercise of voluntary muscles of the human subject, the exercise assist device further comprising a pad , wherein the stand is connected to a movable arm extending from a strut , the strut extending in a direction substantially orthogonal to a longitudinal axis of the human subject, wherein the pad is a sacrum support pad being adapted to support an area corresponding to the sacrum of the human subject behind a back of the human subject, and the member is adapted to support the thigh at a front part of the thigh, characterized in that the sacrum support pad is configured to support the sacrum so that the upper thigh, an upper iliac bone and the sacrum of the human subject are moved in the lateral decubitus position toward the back of the human subject.
A method of making a compound of Formula (II): or a pharmaceutically acceptable salt thereof, wherein: each X 1 is independently selected from H, halo, NO 2 , CN, N 3 , C 1-6 alkyl, C 1-6 alkoxy, C 2-6 alkenyl, C 2-6 alkynyl, C 6-10 aryl, and 5-14 membered heteroaryl, wherein said C 1-6 alkyl, C 2-6 alkenyl, C 2-6 alkynyl, C 6-10 aryl, and 5-14 membered heteroaryl are each optionally substituted with 1, 2, or 3 substituents independently selected from halo, OH, SH, NH 2 , C 1-3 alkylamino, di(C 1-3 alkyl)amino, NO 2 , CN, C(O)OH, C 1-3 alkoxy, C 1-3 haloalkoxy, and N 3 ; and each R 1 is independently selected from H, C 1-6 alkyl, C 2-6 alkenyl, and C 2-6 alkynyl, each of which is optionally substituted with 1, 2, or 3 substituents independently selected from halo, OH, SH, NH 2 , C 1-3 alkylamino, di(C 1-3 alkyl)amino, NO 2 , CN, C(O)OH, C 1-3 alkoxy, C 1-3 haloalkoxy, and N 3 , the method comprising deprotecting a compound of Formula (IIa): or a salt thereof, wherein each P 1 is independently a protecting group, and R 1 is at each occurrence the same as R 1 for Formula (II), to obtain the compound of Formula (II), and the method further comprising preparing the compound of Formula (IIa) by a method comprising coupling a compound of Formula (IIb): or a salt thereof, with a compound of formula : or a salt thereof, to obtain the compound of Formula (IIa). each X 1 is independently selected from H, halo, NO 2 , CN, N 3 , C 1-6 alkyl, C 1-6 alkoxy, C 2-6 alkenyl, C 2-6 alkynyl, C 6-10 aryl, and 5-14 membered heteroaryl, wherein said C 1-6 alkyl, C 2-6 alkenyl, C 2-6 alkynyl, C 6-10 aryl, and 5-14 membered heteroaryl are each optionally substituted with 1, 2, or 3 substituents independently selected from halo, OH, SH, NH 2 , C 1-3 alkylamino, di(C 1-3 alkyl)amino, NO 2 , CN, C(O)OH, C 1-3 alkoxy, C 1-3 haloalkoxy, and N 3 ; and each R 1 is independently selected from H, C 1-6 alkyl, C 2-6 alkenyl, and C 2-6 alkynyl, each of which is optionally substituted with 1, 2, or 3 substituents independently selected from halo, OH, SH, NH 2 , C 1-3 alkylamino, di(C 1-3 alkyl)amino, NO 2 , CN, C(O)OH, C 1-3 alkoxy, C 1-3 haloalkoxy, and N 3 , the method comprising deprotecting a compound of Formula (IIa): or a salt thereof, wherein each P 1 is independently a protecting group, and R 1 is at each occurrence the same as R 1 for Formula (II), to obtain the compound of Formula (II), and coupling a compound of Formula (IIb): or a salt thereof, with a compound of formula : or a salt thereof, to obtain the compound of Formula (IIa).
Functional bar for arrangement on interior load compartment areas of a motor vehicle, with a - profile beam , with a connecting section and a rear side formed in sections for support on the interior load compartment area, wherein - the connecting section is designed for the arrangement of blocking means for securing the load, and - the profile beam additionally has connecting means for connection to an illuminant carrier , characterized in that - the functional bar has at least one illuminant carrier for the arrangement of illuminants , with an illuminant section for receiving at least one illuminant , and a connecting section with at least one coupling element and a support, wherein - the support of the illuminant carrier bears against at least one part of the profile beam , and the corresponding coupling element arranged on the connecting section is operatively connected to the profile beam in such a way that the coupling element with the connecting means detachably secures the illuminant carrier to the profile beam . - profile beam , with a connecting section and a rear side formed in sections for support on the interior load compartment area, wherein - the connecting section is designed for the arrangement of blocking means for securing the load, and - the profile beam additionally has connecting means for connection to an illuminant carrier , - the functional bar has at least one illuminant carrier for the arrangement of illuminants , with an illuminant section for receiving at least one illuminant , and a connecting section with at least one coupling element and a support, wherein - the support of the illuminant carrier bears against at least one part of the profile beam , and the corresponding coupling element arranged on the connecting section is operatively connected to the profile beam in such a way that the coupling element with the connecting means detachably secures the illuminant carrier to the profile beam .
Method for transferring electronic coin data sets (C i , C j , C k , C m , C l ) between terminals (M1, M2, M3) for payment in a payment system, wherein a first terminal (M1) has at least one electronic coin data set (C i , C j , C k ), wherein the at least one electronic coin data set (C i , C j , C k ) has a monetary amount (υ i , υ j , υ k ) and an obfuscation amount (r i , r j , r k ) as coin data set elements, comprising the following steps: - masking a first coin data set element of the electronic coin data set (C i , C j , C k ), preferably in the first terminal (M1), by applying a one-way function, which is homomorphic, for example, to the first coin data set element of the electronic coin data set (C i , C j , C k ) in order to obtain a masked first electronic coin data set element; characterized by - adding a second, unmasked coin data set element of the electronic coin data set (C i , C j , C k ) to the masked first electronic coin data set element in the first terminal (M1) in order to obtain a quasi-masked electronic coin data set (Z i , Z j , Z k ) ; - transmitting the quasi-masked electronic coin data set (Z i , Z j , Z k ) to a monitoring entity for registering the electronic coin data set (C i , C j , C k ); and - directly transferring the electronic coin data set (C i , C j , C k ) from the first terminal (M1) to a second terminal (M2, M3). - masking a first coin data set element of the electronic coin data set (C i , C j , C k ), preferably in the first terminal (M1), by applying a one-way function, which is homomorphic, for example, to the first coin data set element of the electronic coin data set (C i , C j , C k ) in order to obtain a masked first electronic coin data set element; - adding a second, unmasked coin data set element of the electronic coin data set (C i , C j , C k ) to the masked first electronic coin data set element in the first terminal (M1) in order to obtain a quasi-masked electronic coin data set (Z i , Z j , Z k ) ; - transmitting the quasi-masked electronic coin data set (Z i , Z j , Z k ) to a monitoring entity for registering the electronic coin data set (C i , C j , C k ); and - directly transferring the electronic coin data set (C i , C j , C k ) from the first terminal (M1) to a second terminal (M2, M3).
A delay circuit, comprising: a first, a second, a third and a fourth transistor ; a first inverter coupled to the first transistor and the second transistor , wherein the first transistor is connected to the second transistor in parallel, the first inverter is configured to receive a first intermediate delayed clock signal from the parallel first and second transistors and generate a positive delayed clock signal to be received by a first negative-AND NAND gate of a comparator; a second inverter coupled to the third transistor and the fourth transistor , wherein the third transistor is connected to the fourth transistor in parallel, the second inverter configured to receive a second intermediate delayed clock signal from the parallel third and fourth transistors and generate a negative delayed clock signal to be received by a second NAND gate of the comparator; wherein the delay circuit is arranged such that the resistance of the first transistor in parallel with the second transistor determines a delay in the positive delayed clock signal ; and the resistance of the third transistor in parallel with the fourth transistor determines a delay in the negative delayed clock signal; characterized by a pair of cross-coupled capacitors cross coupling the first and second inverters . a first, a second, a third and a fourth transistor ; a first inverter coupled to the first transistor and the second transistor , wherein the first transistor is connected to the second transistor in parallel, the first inverter is configured to receive a first intermediate delayed clock signal from the parallel first and second transistors and generate a positive delayed clock signal to be received by a first negative-AND NAND gate of a comparator; a second inverter coupled to the third transistor and the fourth transistor , wherein the third transistor is connected to the fourth transistor in parallel, the second inverter configured to receive a second intermediate delayed clock signal from the parallel third and fourth transistors and generate a negative delayed clock signal to be received by a second NAND gate of the comparator; wherein the delay circuit is arranged such that the resistance of the first transistor in parallel with the second transistor determines a delay in the positive delayed clock signal ; and the resistance of the third transistor in parallel with the fourth transistor determines a delay in the negative delayed clock signal; characterized by a pair of cross-coupled capacitors cross coupling the first and second inverters .