A microstrip DC block comprising: a first signal line having a first signal line end and a first centreline ( C 1 ); a second signal line having a second signal line end and a second centreline ( C 2 ); a first spur-line electrically connected to and extending from the first signal line end towards the second signal line end; a first stepped impedance line electrically connected to and extending from the first signal line end towards the second signal line end, wherein the first stepped impedance line is parallel to the first spur line; a second spur-line electrically connected to and extending from the second signal line end towards the first signal line end; and a second stepped impedance line electrically connected to and extending from the second signal line end towards the first signal line end, wherein the second stepped impedance line is parallel to the second spur line, and wherein the second stepped impedance line is coupled to the first stepped impedance line , wherein the first spur-line extends from a portion of the first signal line end that is proximate to a side of the first signal line , and wherein the first stepped impedance line extends from a portion of the first signal line end that is adjacent to the first spur-line and is proximate to the first centreline ( C 1 ); wherein the second spur-line extends from a portion of the second signal line end that is proximate to a side of the second signal line , and wherein the second stepped impedance line extends from a portion of the second signal line end that is adjacent to the second spur-line and is proximate to the second centreline ( C 2 ), and wherein the first and second spur-lines and the first and second stepped impedance lines are parallel to one another. a first signal line having a first signal line end and a first centreline ( C 1 ); a second signal line having a second signal line end and a second centreline ( C 2 ); a first spur-line electrically connected to and extending from the first signal line end towards the second signal line end; a first stepped impedance line electrically connected to and extending from the first signal line end towards the second signal line end, wherein the first stepped impedance line is parallel to the first spur line; a second spur-line electrically connected to and extending from the second signal line end towards the first signal line end; and a second stepped impedance line electrically connected to and extending from the second signal line end towards the first signal line end, wherein the second stepped impedance line is parallel to the second spur line, and wherein the second stepped impedance line is coupled to the first stepped impedance line , wherein the first spur-line extends from a portion of the first signal line end that is proximate to a side of the first signal line , and wherein the first stepped impedance line extends from a portion of the first signal line end that is adjacent to the first spur-line and is proximate to the first centreline ( C 1 ); wherein the second spur-line extends from a portion of the second signal line end that is proximate to a side of the second signal line , and wherein the second stepped impedance line extends from a portion of the second signal line end that is adjacent to the second spur-line and is proximate to the second centreline ( C 2 ), and wherein the first and second spur-lines and the first and second stepped impedance lines are parallel to one another. <EOS>