A stacking embedded dynamic random access memory SEDRAM-based stacked Cache system, integrated in multiple layers of wafers bonded together, and comprising a Cache, a Cache controller and a SEDRAM controller; wherein the multiple layers of wafers comprise a SEDRAM wafer structure and a processor wafer structure; the SEDRAM wafer structure comprises at least one layer of SEDRAM wafer, and a SEDRAM unit is integrated in each layer of SEDRAM wafer in the SEDRAM wafer structure and configured as a storage space of the Cache; the processor wafer structure comprises at least one layer of processor wafer; and a CPU, the Cache controller, the SEDRAM controller and a memory controller are integrated in the processor wafer structure; data is transferred between wafers through a bonding structure in pin-to-pin data direct transmission, comprising: pin-to-pin data direct transmission between the SEDRAM wafer of the SEDRAM wafer structure and the processor wafer of the processor wafer structure through a bonding structure; pin-to-pin data direct transmission between the SEDRAM wafers of the SEDRAM wafer structure through a bonding structure; pin-to-pin data direct transmission between the processor wafers of the processor wafer structure through a bonding structure, wherein the Cache controller is configured to determine whether the Cache hits, and send corresponding command operation and data interaction request to the CPU, the SEDRAM controller and the memory controller; and the SEDRAM controller is configured to control reading or writing content in the SEDRAM unit. the multiple layers of wafers comprise a SEDRAM wafer structure and a processor wafer structure; the SEDRAM wafer structure comprises at least one layer of SEDRAM wafer, and a SEDRAM unit is integrated in each layer of SEDRAM wafer in the SEDRAM wafer structure and configured as a storage space of the Cache; the processor wafer structure comprises at least one layer of processor wafer; and a CPU, the Cache controller, the SEDRAM controller and a memory controller are integrated in the processor wafer structure; data is transferred between wafers through a bonding structure in pin-to-pin data direct transmission, comprising: pin-to-pin data direct transmission between the SEDRAM wafer of the SEDRAM wafer structure and the processor wafer of the processor wafer structure through a bonding structure; pin-to-pin data direct transmission between the SEDRAM wafers of the SEDRAM wafer structure through a bonding structure; pin-to-pin data direct transmission between the processor wafers of the processor wafer structure through a bonding structure, wherein the Cache controller is configured to determine whether the Cache hits, and send corresponding command operation and data interaction request to the CPU, the SEDRAM controller and the memory controller; and the SEDRAM controller is configured to control reading or writing content in the SEDRAM unit. pin-to-pin data direct transmission between the SEDRAM wafer of the SEDRAM wafer structure and the processor wafer of the processor wafer structure through a bonding structure; pin-to-pin data direct transmission between the SEDRAM wafers of the SEDRAM wafer structure through a bonding structure; pin-to-pin data direct transmission between the processor wafers of the processor wafer structure through a bonding structure, wherein the Cache controller is configured to determine whether the Cache hits, and send corresponding command operation and data interaction request to the CPU, the SEDRAM controller and the memory controller; and the SEDRAM controller is configured to control reading or writing content in the SEDRAM unit. <EOS>