A static converter with parallel architecture, designed to be powered by a voltage source Vin and to provide an output current lout, comprising a first power supply input terminal , a second power supply input terminal , an output terminal , a total number q of electronic switching cells arranged in parallel, a total number q of output branches connected in common along first ends to the output terminal , a same total number q of control modules (52, 54, 56, 58, 60; 252, 254, 256, 258, 260; 522, 524, 526, 528, 530; 722, 724, 726, 728, 730), a chain of q communication links connecting the control modules in a closed loop, each electronic switching cell being associated with a single and different control module (52, 54, 56, 58, 60; 252, 254, 256, 258, 260; 522, 524, 526, 528, 530; 722, 724, 726, 728, 730) and with a single and different output branch , the associated module , switching cell and output branch being identified by a same single and different integer rank, comprised between 1 and q, for positioning i within the communication chain , any two control modules , adjacent within the communication chain and with respective rank i, i+1, being connected by a single and different communication link L i,i +1 , the switching cells each comprising a single and different pair of two electronic switches (80; 82, 84; 86, 88; 90, 92; 94, 96; 98) connected in series, a first cell power supply terminal , a second cell power terminal supply and a single and different intermediate output terminal , shared by the two electronic switches (80; 82, 84; 86, 88; 90, 92; 94, 96; 98) connected in series and connected to a second end of the associated output branch , the first cell power supply terminals and the second cell power supply terminals being connected to the first power supply input terminal and the second power supply input terminal , respectively, each control module (52, 54, 56, 58, 60; 252, 254, 256, 258, 260; 522, 524, 526, 528, 530; 722, 724, 726, 728, 730) respectively comprising a single and different local unit for generating a unique triangular voltage carrier , the local unit for generating the triangular carrier of any control module (56; 256; 526; 726) with rank i being configured to control the positioning of its interleaving phase within all of the interleaved triangular carriers based solely on the signals of the triangular carriers of the two modules (54, 58; 254, 258; 524, 528; 724, 728) with respective rank i-1, i+1 adjacent to the any module (56; 256; 526; 726) with rank i, provided by the two modules (54, 58; 254, 258; 524, 528; 724, 728) adjacent to the any module (56; 256; 526; 726) through two corresponding communication links , i being comprised between 1 and q, with i-1 equal to q when i is equal to 1, and i+1 equal to 1 when i is equal to q, characterized in that each control module (52, 54, 56, 58, 60 ; 252, 254, 256, 258, 260 ; 522, 524, 526, 528, 530 ; 722, 724, 726, 728, 730) respectively comprises a single and different unit for internal regulation of the output voltage of the AVP type (532, 534, 536, 538, 540 ; 732, 734, 736, 738, 740), the internal unit regulating the output voltage of the AVP type (536; 736) of any module (56; 526; 726) with rank i being configured by implementing a unique internal voltage and/or current loop to determine a unique cyclic ratio Di, the determination of Di depending on a product of the value of the current li passing through the branch connected to the switching cell associated with the any module (56; 526; 726) with rank i and a slope factor αi depending on the rank i of the module (56; 526). <EOS>