A macro scheduler, comprising: a resource tracking module configured to: update a database enumerating a plurality of macro components in a set of field programmable gate array, FPGA, devices (121-123), each of the plurality of macro components representing a plurality of circuit components in the set of FPGA devices; and for each macro component of the plurality of macro components, record in the database a location of the macro component in the set of FPGA devices; a communication interface configured to receive from a first client device a first design definition indicating one or more specified macro components for a design; resource allocation logic configured to allocate a first set of macro components for the design by performing an allocation of one of the plurality of macro components in the set of FPGA devices (121-123) enumerated in the database that is indicated as available during a time period for each of the one or more specified macro components indicated in the first design definition, wherein the database stores schedule information indicating the availability of at least one of the plurality of macro components; the resource tracking module being further configured to update the schedule information to indicate that the first set of macro components is not available for the time period; and configuration logic configured to implement the design in the set of FPGA devices by configuring the first set of allocated macro components according to the first design definition. a resource tracking module configured to: update a database enumerating a plurality of macro components in a set of field programmable gate array, FPGA, devices (121-123), each of the plurality of macro components representing a plurality of circuit components in the set of FPGA devices; and for each macro component of the plurality of macro components, record in the database a location of the macro component in the set of FPGA devices; update a database enumerating a plurality of macro components in a set of field programmable gate array, FPGA, devices (121-123), each of the plurality of macro components representing a plurality of circuit components in the set of FPGA devices; and for each macro component of the plurality of macro components, record in the database a location of the macro component in the set of FPGA devices; a communication interface configured to receive from a first client device a first design definition indicating one or more specified macro components for a design; resource allocation logic configured to allocate a first set of macro components for the design by performing an allocation of one of the plurality of macro components in the set of FPGA devices (121-123) enumerated in the database that is indicated as available during a time period for each of the one or more specified macro components indicated in the first design definition, wherein the database stores schedule information indicating the availability of at least one of the plurality of macro components; the resource tracking module being further configured to update the schedule information to indicate that the first set of macro components is not available for the time period; and configuration logic configured to implement the design in the set of FPGA devices by configuring the first set of allocated macro components according to the first design definition. <EOS>