A processor comprising: decode circuitry to decode a single instruction into a decoded single instruction, the single instruction having a first field to specify a source matrix, a second field to specify a destination matrix, and an opcode to indicate execution circuitry is to cause a store of a first element and a second element from a first column of the source matrix respectively into a first element and a second element in a first row of the destination matrix, a first element and a second element from a second column of the source matrix respectively into a third element and a fourth element in the first row of the destination matrix, a third element and a fourth element from the first column of the source matrix respectively into a first element and a second element in a second row of the destination matrix, and a third element and a fourth element from the second column of the source matrix respectively into a third element and a fourth element in the second row of the destination matrix; and the execution circuitry to execute the decoded single instruction according to the opcode, wherein the single instruction further comprises a field to specify a hint that indicates the source matrix is prioritized for eviction from a first level cache of the processor . decode circuitry to decode a single instruction into a decoded single instruction, the single instruction having a first field to specify a source matrix, a second field to specify a destination matrix, and an opcode to indicate execution circuitry is to cause a store of a first element and a second element from a first column of the source matrix respectively into a first element and a second element in a first row of the destination matrix, a first element and a second element from a second column of the source matrix respectively into a third element and a fourth element in the first row of the destination matrix, a third element and a fourth element from the first column of the source matrix respectively into a first element and a second element in a second row of the destination matrix, and a third element and a fourth element from the second column of the source matrix respectively into a third element and a fourth element in the second row of the destination matrix; and the execution circuitry to execute the decoded single instruction according to the opcode, a first element and a second element from a first column of the source matrix respectively into a first element and a second element in a first row of the destination matrix, a first element and a second element from a second column of the source matrix respectively into a third element and a fourth element in the first row of the destination matrix, a third element and a fourth element from the first column of the source matrix respectively into a first element and a second element in a second row of the destination matrix, and a third element and a fourth element from the second column of the source matrix respectively into a third element and a fourth element in the second row of the destination matrix; and the execution circuitry to execute the decoded single instruction according to the opcode, wherein the single instruction further comprises a field to specify a hint that indicates the source matrix is prioritized for eviction from a first level cache of the processor . <EOS>