An apparatus, comprising: a first select line configured to provide a first voltage; a second select line configured to provide a second voltage; a third select line; a fourth select line; a polarity line configured to provide a polarity signal; a first set of access lines ; a second set of access lines; at least one memory cell coupled between an access line of the first set of access lines and an access line of the second set of access lines; a first address decoder circuit coupled to the first and second select lines, the polarity line, and the access line, the address decoder circuit configured to receive address information and further configured to couple the access line of the first set of access lines to the first select line responsive to the address information having a combination of logic levels and the polarity signal having a first logic level and further configured to couple the access line to the second select line responsive to the address information having the combination of logic levels and the polarity signal having a second logic level; and a second address decoder circuit coupled to the third select line, the fourth select line, and the polarity line, wherein the second address decoder circuit is configured to receive second address information and further configured to couple the access line of the second set of access lines to the third select line responsive to second address information and further configured to switch the coupling of the access line from the third select line to the fourth select line for the second address information responsive to switching the logic level of the polarity signal, wherein the first and second address decoders are configured to switch the coupling of the access lines of the first and second sets of access lines to cause current to flow in different directions through the memory cell. a first select line configured to provide a first voltage; a second select line configured to provide a second voltage; a third select line; a fourth select line; a polarity line configured to provide a polarity signal; a first set of access lines ; a second set of access lines; at least one memory cell coupled between an access line of the first set of access lines and an access line of the second set of access lines; a first address decoder circuit coupled to the first and second select lines, the polarity line, and the access line, the address decoder circuit configured to receive address information and further configured to couple the access line of the first set of access lines to the first select line responsive to the address information having a combination of logic levels and the polarity signal having a first logic level and further configured to couple the access line to the second select line responsive to the address information having the combination of logic levels and the polarity signal having a second logic level; and a second address decoder circuit coupled to the third select line, the fourth select line, and the polarity line, wherein the second address decoder circuit is configured to receive second address information and further configured to couple the access line of the second set of access lines to the third select line responsive to second address information and further configured to switch the coupling of the access line from the third select line to the fourth select line for the second address information responsive to switching the logic level of the polarity signal, wherein the first and second address decoders are configured to switch the coupling of the access lines of the first and second sets of access lines to cause current to flow in different directions through the memory cell. <EOS>