Method for calibrating a Successive Approximation Register analog-to-digital converter, ADC, converting an input voltage signal into a digital output signal representing said input voltage signal, the method comprising : - sampling said input voltage signal applied to said analog-to-digital converter, - comparing with a comparator said sampled input voltage signal with an output signal of a feedback digital-to-analogue converter, DAC, comprising an array of capacitors, - determining in a search logic block of said ADC a digital code representation for the comparison result, characterised by - performing a calibration by : performing an additional comparator cycle wherein the last comparison carried out for determining the least significant bit of said digital code representation is repeated with a second comparator resolution mode different from a first comparator resolution mode used in at least said last comparison, so obtaining an additional comparison, determining from a difference between the results of said additional comparison and said last comparison a sign of a comparator offset error between said first and said second comparator resolution mode, tuning, in accordance with said sign of said comparator offset error, a programmable capacitor (C cal1 ) connected between capacitors of said DAC and the input of said comparator, thereby inducing a voltage step to counteract said comparator offset error, when switching between said first and said second comparator resolution mode. - sampling said input voltage signal applied to said analog-to-digital converter, - comparing with a comparator said sampled input voltage signal with an output signal of a feedback digital-to-analogue converter, DAC, comprising an array of capacitors, - determining in a search logic block of said ADC a digital code representation for the comparison result, characterised by - performing a calibration by : performing an additional comparator cycle wherein the last comparison carried out for determining the least significant bit of said digital code representation is repeated with a second comparator resolution mode different from a first comparator resolution mode used in at least said last comparison, so obtaining an additional comparison, determining from a difference between the results of said additional comparison and said last comparison a sign of a comparator offset error between said first and said second comparator resolution mode, tuning, in accordance with said sign of said comparator offset error, a programmable capacitor (C cal1 ) connected between capacitors of said DAC and the input of said comparator, thereby inducing a voltage step to counteract said comparator offset error, when switching between said first and said second comparator resolution mode. performing an additional comparator cycle wherein the last comparison carried out for determining the least significant bit of said digital code representation is repeated with a second comparator resolution mode different from a first comparator resolution mode used in at least said last comparison, so obtaining an additional comparison, determining from a difference between the results of said additional comparison and said last comparison a sign of a comparator offset error between said first and said second comparator resolution mode, tuning, in accordance with said sign of said comparator offset error, a programmable capacitor (C cal1 ) connected between capacitors of said DAC and the input of said comparator, thereby inducing a voltage step to counteract said comparator offset error, when switching between said first and said second comparator resolution mode. <EOS>