An optical head tracking system comprising: at least one helmet which carries a light emitting diode, LED, array as a part of the optical head tracking system ; a plurality of LEDs on the helmet which have an infrared, IR, characteristic; at least one camera which is adapted to capture a video of the LEDs on the helmet ; at least one camera holder which is adapted to hold the camera ; at least one field programmable gate array, FPGA, which is adapted to calculate LED center coordinates by using double floating point operators; at least one video processing board which contains the FPGA and video capturing components; and at least one camera lens adapted to accept only the specific IR from the LEDs , wherein the FPGA is adapted to: process an incoming video frame by Camera Lens Distortion Correction, CLDC; filter the incoming video frame using a Pixel Intensity Filter, PIF, to clean up all the noisy pixels on the video frame by using adjustable pixel thresholds; use Connected Component Labeling, CCL, to extract a relation between the incoming pixels and label LED pixels in terms of their neighborhood; for every label, store and update information by LED Center Calculation, LCC, according to incoming label information; and check and filter the incoming information using an LED Validity Filter, LVF, by checking whether the number of pixels for a related label value is in a defined range or not and discarding the incoming information if the number of pixels for the related label value is not in the defined range. at least one helmet which carries a light emitting diode, LED, array as a part of the optical head tracking system ; a plurality of LEDs on the helmet which have an infrared, IR, characteristic; at least one camera which is adapted to capture a video of the LEDs on the helmet ; at least one camera holder which is adapted to hold the camera ; at least one field programmable gate array, FPGA, which is adapted to calculate LED center coordinates by using double floating point operators; at least one video processing board which contains the FPGA and video capturing components; and at least one camera lens adapted to accept only the specific IR from the LEDs , wherein the FPGA is adapted to: process an incoming video frame by Camera Lens Distortion Correction, CLDC; filter the incoming video frame using a Pixel Intensity Filter, PIF, to clean up all the noisy pixels on the video frame by using adjustable pixel thresholds; use Connected Component Labeling, CCL, to extract a relation between the incoming pixels and label LED pixels in terms of their neighborhood; for every label, store and update information by LED Center Calculation, LCC, according to incoming label information; and check and filter the incoming information using an LED Validity Filter, LVF, by checking whether the number of pixels for a related label value is in a defined range or not and discarding the incoming information if the number of pixels for the related label value is not in the defined range. process an incoming video frame by Camera Lens Distortion Correction, CLDC; filter the incoming video frame using a Pixel Intensity Filter, PIF, to clean up all the noisy pixels on the video frame by using adjustable pixel thresholds; use Connected Component Labeling, CCL, to extract a relation between the incoming pixels and label LED pixels in terms of their neighborhood; for every label, store and update information by LED Center Calculation, LCC, according to incoming label information; and check and filter the incoming information using an LED Validity Filter, LVF, by checking whether the number of pixels for a related label value is in a defined range or not and discarding the incoming information if the number of pixels for the related label value is not in the defined range. <EOS>