A semiconductor package comprising: a package structure comprising a base connection member comprising a redistribution layer , a first semiconductor chip comprising a plurality of first connection pads connected to the redistribution layer, an encapsulant disposed on the base connection member and covering at least a portion of the first semiconductor chip, a backside connection member disposed on the encapsulant and comprising a backside wiring layer electrically connected to the redistribution layer, a through-via connecting the redistribution layer to the backside wiring layer by penetrating through the first semiconductor chip, and an electronic component disposed inside of the first semiconductor chip and electrically connected to the through-via; a second semiconductor chip disposed on the base connection member or the backside connection member, the second semiconductor chip comprising a plurality of second connection pads connected to the redistribution layer or the backside wiring layer; and, a plurality of connection bumps disposed between the package structure and the second semiconductor chip and directly connecting the plurality of second connection pads to at least one of the redistribution layer and the backside wiring layer, wherein the second semiconductor chip comprises a logic circuit, wherein the logic circuit comprises a central processing unit, a graphics processing unit, a neural processing unit, a digital signal processor unit, or an image signal processing unit, and the first semiconductor chip comprises a logic input terminal and a logic output terminal that are respectively connected to the logic circuit through at least one of the redistribution layer and the backside wiring layer. a package structure comprising a base connection member comprising a redistribution layer , a first semiconductor chip comprising a plurality of first connection pads connected to the redistribution layer, an encapsulant disposed on the base connection member and covering at least a portion of the first semiconductor chip, a backside connection member disposed on the encapsulant and comprising a backside wiring layer electrically connected to the redistribution layer, a through-via connecting the redistribution layer to the backside wiring layer by penetrating through the first semiconductor chip, and an electronic component disposed inside of the first semiconductor chip and electrically connected to the through-via; a second semiconductor chip disposed on the base connection member or the backside connection member, the second semiconductor chip comprising a plurality of second connection pads connected to the redistribution layer or the backside wiring layer; and, a plurality of connection bumps disposed between the package structure and the second semiconductor chip and directly connecting the plurality of second connection pads to at least one of the redistribution layer and the backside wiring layer, wherein the second semiconductor chip comprises a logic circuit, wherein the logic circuit comprises a central processing unit, a graphics processing unit, a neural processing unit, a digital signal processor unit, or an image signal processing unit, and the first semiconductor chip comprises a logic input terminal and a logic output terminal that are respectively connected to the logic circuit through at least one of the redistribution layer and the backside wiring layer. <EOS>