An apparatus comprising hardware logic arranged to normalise an n-bit input number, the hardware logic comprising: a first hardware logic stage comprising a left shifting logic element and a plurality of OR-reduction logic elements (204-208, 604-607), wherein each OR-reduction logic element is arranged to perform OR-reduction on a different subset of bits from the input number and the left shifting logic element is arranged to perform left shifting on the input number dependent upon a value output by a first of the OR-reduction logic elements and output an updated binary number; one or more intermediate hardware logic stages, each comprising a left shifting logic element, a plurality of OR-reduction logic elements and one or more multiplexers, wherein each OR-reduction logic element in an intermediate stage is arranged to perform OR-reduction on a different subset of bits from an updated binary number received from an immediately previous hardware logic stage, a first of the multiplexers is arranged to select one of a plurality of OR-reduction results received from a previous hardware logic stage and the left shifting logic element is arranged to perform left shifting on the updated binary number received from an immediately previous hardware logic stage dependent upon the selected OR-reduction result and output an updated binary number; and one or more final hardware logic stages, each comprising a left shifting logic element and one or more multiplexers, wherein a first of the multiplexers is arranged to select one of a plurality of OR-reduction results received from a previous hardware logic stage and the left shifting logic element is arranged to perform left shifting on the updated binary number received from an immediately previous hardware logic stage dependent upon the selected OR-reduction result and output an updated binary number and wherein, for a last of the final hardware logic stages, the updated binary number is the normalised input number. a first hardware logic stage comprising a left shifting logic element and a plurality of OR-reduction logic elements (204-208, 604-607), wherein each OR-reduction logic element is arranged to perform OR-reduction on a different subset of bits from the input number and the left shifting logic element is arranged to perform left shifting on the input number dependent upon a value output by a first of the OR-reduction logic elements and output an updated binary number; one or more intermediate hardware logic stages, each comprising a left shifting logic element, a plurality of OR-reduction logic elements and one or more multiplexers, wherein each OR-reduction logic element in an intermediate stage is arranged to perform OR-reduction on a different subset of bits from an updated binary number received from an immediately previous hardware logic stage, a first of the multiplexers is arranged to select one of a plurality of OR-reduction results received from a previous hardware logic stage and the left shifting logic element is arranged to perform left shifting on the updated binary number received from an immediately previous hardware logic stage dependent upon the selected OR-reduction result and output an updated binary number; and one or more final hardware logic stages, each comprising a left shifting logic element and one or more multiplexers, wherein a first of the multiplexers is arranged to select one of a plurality of OR-reduction results received from a previous hardware logic stage and the left shifting logic element is arranged to perform left shifting on the updated binary number received from an immediately previous hardware logic stage dependent upon the selected OR-reduction result and output an updated binary number and wherein, for a last of the final hardware logic stages, the updated binary number is the normalised input number. <EOS>