A method of forming memory cells, comprising: forming a conductive layer over and insulated from a substrate that has a first conductivity type; forming a second conductive layer over and insulated from the conductive layer; forming an insulation layer on the second conductive layer; performing an etch of the insulation layer and the second conductive layer to form a pair of spaced apart conductive control gates over and insulated from the conductive layer and blocks of insulation over the control gates , wherein each of the control gates and blocks of insulation includes opposing inner and outer sidewalls, and wherein the inner sidewalls face each other; forming silicon dioxide and silicon nitride on the inner and outer sidewalls of the control gates and the blocks of insulation ; forming a pair of first oxide spacers of insulation material along the inner sidewalls of the control gates and the blocks of insulation and on the conductive layer ; performing an etch of the conductive layer to form a pair of floating gates of the conductive layer and using the first oxide spacers to define inner sidewalls of the floating gates that face each other; forming a pair of second spacers of insulation material each extending along one of the first spacers and along the inner sidewall of one of the floating gates; performing etches that partially etch down the blocks of insulation , spacers , silicon nitride , and silicon dioxide , and form a trench into the substrate, wherein the trench has sidewalls aligned with side surfaces of the pair of second spacers ; forming silicon carbon in the trench until the trench is full of the silicon carbon; and implanting a material into the silicon carbon to form a first region therein having a second conductivity type. forming a conductive layer over and insulated from a substrate that has a first conductivity type; forming a second conductive layer over and insulated from the conductive layer; forming an insulation layer on the second conductive layer; performing an etch of the insulation layer and the second conductive layer to form a pair of spaced apart conductive control gates over and insulated from the conductive layer and blocks of insulation over the control gates , wherein each of the control gates and blocks of insulation includes opposing inner and outer sidewalls, and wherein the inner sidewalls face each other; forming silicon dioxide and silicon nitride on the inner and outer sidewalls of the control gates and the blocks of insulation ; forming a pair of first oxide spacers of insulation material along the inner sidewalls of the control gates and the blocks of insulation and on the conductive layer ; performing an etch of the conductive layer to form a pair of floating gates of the conductive layer and using the first oxide spacers to define inner sidewalls of the floating gates that face each other; forming a pair of second spacers of insulation material each extending along one of the first spacers and along the inner sidewall of one of the floating gates; performing etches that partially etch down the blocks of insulation , spacers , silicon nitride , and silicon dioxide , and form a trench into the substrate, wherein the trench has sidewalls aligned with side surfaces of the pair of second spacers ; forming silicon carbon in the trench until the trench is full of the silicon carbon; and implanting a material into the silicon carbon to form a first region therein having a second conductivity type. <EOS>