A method implemented in an Artificial Neural Network (ANN), the ANN comprising a plurality of neurons arranged in layers, the layers comprising at least one upstream neuron layer and at least one downstream neuron layer, the output of the at least one upstream neuron layer connected to the input of the at least one downstream neuron layer, wherein a plurality of analog signals are transmitted on a plurality of transmission channels, all of the transmission channels sharing a common initialization trigger signal, by encoding each of the signals in the delay between the common initialization trigger signal and a subsequent unique termination trigger, the method comprising: (a) receiving an enable signal generated in the upstream neuron layer, thereby commencing discharging of a capacitor in the upstream neuron layer, the capacitor having an initial value representative of an output of the upstream neuron layer, wherein the capacitor is coupled to a comparator in the upstream neuron layer; (b) sharing the enable signal to an input of a digital counter located at the downstream neuron layer, where the counter, upon reception of the enable signal, starts counting using a clock that is local to the downstream neuron layer; (c) monitoring output analog voltage of the capacitor; and (d) when a voltage transition is detected in the monitored output analog voltage, (e) transmitting a voltage transition signal to a plurality of flip-flops at the downstream neuron layer, wherein the plurality of flip-flops are arranged in parallel with one another and each flip-flop is coupled to the counter such that each flip-flop receives a same counter value from the counter, wherein the downstream neuron layer latches a current value of the counter upon reception of the voltage transition signal, the latched current value being equal to the initial value representative of an output of the upstream neuron layer, and wherein the output value is communicated between the upstream neuron layer and the downstream neuron layer without global synchronization of clocks between the upstream neuron layer and the downstream neuron layer, and wherein the trigger signal, the enable signal and the voltage transition signal are conveyed on a bus between the upstream neuron layer and the downstream neuron layer as an encoded signal that includes an address of the capacitor and a delay to be imposed before latching the current value of the counter, wherein the address of the capacitor corresponds to the address of the particular flip-flop which should be latched at the instant of arrival of the voltage transition signal, and wherein the delays associated with encoding the capacitor address, and of decoding the address at the downstream neuron layer, need only be identical for each and every capacitor/flip-flop pair, and are added into the delay associated with the arrival of the trigger signal. (a) receiving an enable signal generated in the upstream neuron layer, thereby commencing discharging of a capacitor in the upstream neuron layer, the capacitor having an initial value representative of an output of the upstream neuron layer, wherein the capacitor is coupled to a comparator in the upstream neuron layer; (b) sharing the enable signal to an input of a digital counter located at the downstream neuron layer, where the counter, upon reception of the enable signal, starts counting using a clock that is local to the downstream neuron layer; (c) monitoring output analog voltage of the capacitor; and (d) when a voltage transition is detected in the monitored output analog voltage, (e) transmitting a voltage transition signal to a plurality of flip-flops at the downstream neuron layer, wherein the plurality of flip-flops are arranged in parallel with one another and each flip-flop is coupled to the counter such that each flip-flop receives a same counter value from the counter, <EOS>