A system comprising: a processor communicatively coupled with a first memory and a second memory used as system memory; input/output (I/O) circuitry coupled with the first memory and the second memory, the I/O circuitry to receive memory access requests; and logic communicatively coupled with the processor and with the first memory and the second memory to: determine if the memory access requests are to a first region of system memory or a second region of system memory, wherein data in the first region is cacheable in a cache comprised in the first memory; and in response to a determination that one of the memory access requests is to the first region and a second of the memory access requests is to the second region, access the data in the first region from the cache of the first memory and concurrently access second data in the second region from the second memory, wherein the first region comprises a cacheable portion of a page in the system memory, and the second region comprises a non-cacheable portion of the page in the system memory; wherein the logic is to only cache data located in cacheable portions of pages in the system memory, and the first memory has a first bandwidth and the second memory has a second bandwidth, characterized in that a ratio of the size of the first region to the size of the second region is proportional to a ratio of the first bandwidth to the second bandwidth. a processor communicatively coupled with a first memory and a second memory used as system memory; input/output (I/O) circuitry coupled with the first memory and the second memory, the I/O circuitry to receive memory access requests; and logic communicatively coupled with the processor and with the first memory and the second memory to: determine if the memory access requests are to a first region of system memory or a second region of system memory, wherein data in the first region is cacheable in a cache comprised in the first memory; and in response to a determination that one of the memory access requests is to the first region and a second of the memory access requests is to the second region, access the data in the first region from the cache of the first memory and concurrently access second data in the second region from the second memory, wherein determine if the memory access requests are to a first region of system memory or a second region of system memory, wherein data in the first region is cacheable in a cache comprised in the first memory; and in response to a determination that one of the memory access requests is to the first region and a second of the memory access requests is to the second region, access the data in the first region from the cache of the first memory and concurrently access second data in the second region from the second memory, wherein the first region comprises a cacheable portion of a page in the system memory, and the second region comprises a non-cacheable portion of the page in the system memory; wherein the logic is to only cache data located in cacheable portions of pages in the system memory, and the first memory has a first bandwidth and the second memory has a second bandwidth, characterized in that a ratio of the size of the first region to the size of the second region is proportional to a ratio of the first bandwidth to the second bandwidth. <EOS>