A system for synchronizing multiple arbitrary waveform generators comprising: a master arbitrary waveform generator, AWG, having a master AWG clock and a master digital to analog converter, DAC, ; one or more slave arbitrary waveform generators, AWGs, , each having a slave digital to analog converter, DAC, ; and a sync hub having a sync controller and sync phase detector ; wherein the master DAC is configured to generate a divided down master clock, SystemRefClock , from the master AWG clock and output said divided down master clock, SystemRefClock , to the sync hub ; wherein the slave DAC is configured to generate a divided down slave clock, SystemRefClock , from the master AWG clock and output the divided down slave clock, SystemRefClock , to the sync hub ; wherein the sync phase detector is configured to receive the divided down master clock, SystemRefClock , and the divided down slave clock, SystemRefClock , and determine a phase difference between the divided down master clock, SystemRefClock , and the divided down slave clock, SystemRefClock , wherein the slave DAC is further configured to adjust the phase of the divided down slave clock, SystemRefClock , until the phase difference reaches a desired target; and wherein the sync controller is configured to receive the divided down master clock, SystemRefClock , derive a system clock signal, SystemClock , from the divided down master clock, SystemRefClock , using a phase-locked loop, and output the system clock signal to the master AWG and to the slave AWGs , said system clock signal being used within the AWGs to clock a synchronous trigger to indicate when to start playing waveforms from the AWGs . a master arbitrary waveform generator, AWG, having a master AWG clock and a master digital to analog converter, DAC, ; one or more slave arbitrary waveform generators, AWGs, , each having a slave digital to analog converter, DAC, ; and a sync hub having a sync controller and sync phase detector ; wherein the master DAC is configured to generate a divided down master clock, SystemRefClock , from the master AWG clock and output said divided down master clock, SystemRefClock , to the sync hub ; wherein the slave DAC is configured to generate a divided down slave clock, SystemRefClock , from the master AWG clock and output the divided down slave clock, SystemRefClock , to the sync hub ; wherein the sync phase detector is configured to receive the divided down master clock, SystemRefClock , and the divided down slave clock, SystemRefClock , and determine a phase difference between the divided down master clock, SystemRefClock , and the divided down slave clock, SystemRefClock , wherein the slave DAC is further configured to adjust the phase of the divided down slave clock, SystemRefClock , until the phase difference reaches a desired target; and wherein the sync controller is configured to receive the divided down master clock, SystemRefClock , derive a system clock signal, SystemClock , from the divided down master clock, SystemRefClock , using a phase-locked loop, and output the system clock signal to the master AWG and to the slave AWGs , said system clock signal being used within the AWGs to clock a synchronous trigger to indicate when to start playing waveforms from the AWGs . <EOS>