A clock recovery circuit comprising: a first circuitry configured to receive a first signal (162, NX), wherein the first signal (162, NX) is a logical combination of second signals (158a-c) which each corresponds to a different respective differential data signal (152a-c); and a second circuitry coupled to the first circuitry and configured to receive a third signal (172, NX_gt) from the first circuitry during a closed-circuit state of the first circuitry, the third signal (172, NX_gt) based on the first signal (162, NX), wherein the second circuitry is further configured to generate a cyclical signal (142, CLKOUT) based on the third signal (172, NX_gt), wherein: the second circuitry is configured to generate, responsive to a first transition of the third signal (172, NX_gt), a second transition of the cyclical signal (142, CLKOUT), wherein the first circuitry is further to transition to an open-circuit state based on the second transition of the cyclical signal (142, CLKOUT), wherein the first circuitry is configured to not provide the third signal (172, NX_gt) to the second circuitry during the open-circuit state of the first circuitry; and the second circuitry is configured to generate a third transition of the cyclical signal (142, CLKOUT) responsive to an expiration of a threshold period of time after the first transition of the third signal (172, NX_gt), wherein the first circuitry is further configured to transition to the closed-circuit state based on the third transition of the cyclical signal. a first circuitry configured to receive a first signal (162, NX), wherein the first signal (162, NX) is a logical combination of second signals (158a-c) which each corresponds to a different respective differential data signal (152a-c); and a second circuitry coupled to the first circuitry and configured to receive a third signal (172, NX_gt) from the first circuitry during a closed-circuit state of the first circuitry, the third signal (172, NX_gt) based on the first signal (162, NX), wherein the second circuitry is further configured to generate a cyclical signal (142, CLKOUT) based on the third signal (172, NX_gt), wherein: the second circuitry is configured to generate, responsive to a first transition of the third signal (172, NX_gt), a second transition of the cyclical signal (142, CLKOUT), wherein the first circuitry is further to transition to an open-circuit state based on the second transition of the cyclical signal (142, CLKOUT), wherein the first circuitry is configured to not provide the third signal (172, NX_gt) to the second circuitry during the open-circuit state of the first circuitry; and the second circuitry is configured to generate a third transition of the cyclical signal (142, CLKOUT) responsive to an expiration of a threshold period of time after the first transition of the third signal (172, NX_gt), wherein the first circuitry is further configured to transition to the closed-circuit state based on the third transition of the cyclical signal. the second circuitry is configured to generate, responsive to a first transition of the third signal (172, NX_gt), a second transition of the cyclical signal (142, CLKOUT), wherein the first circuitry is further to transition to an open-circuit state based on the second transition of the cyclical signal (142, CLKOUT), wherein the first circuitry is configured to not provide the third signal (172, NX_gt) to the second circuitry during the open-circuit state of the first circuitry; and the second circuitry is configured to generate a third transition of the cyclical signal (142, CLKOUT) responsive to an expiration of a threshold period of time after the first transition of the third signal (172, NX_gt), wherein the first circuitry is further configured to transition to the closed-circuit state based on the third transition of the cyclical signal. <EOS>