A solar cell, wherein the solar cell comprising: a semiconductor substrate comprising a first surface and a second surface that are opposite to each other; a first dielectric layer located on the first surface ; a first N+ doped layer located on a surface of the first dielectric layer ; a first passivation layer located on a surface of the first N+ doped layer ; a first electrode located on a surface of the first passivation layer ; a second dielectric layer located on the second surface ; a first P+ doped layer located on a surface of the second dielectric layer ; a second passivation layer located on a surface of the first P+ doped layer ; and a second electrode located on a surface of the second passivation layer , wherein the semiconductor substrate is an N-type semiconductor substrate , the first surface is a front surface of the semiconductor substrate, and the second surface is a back surface of the semiconductor substrate, wherein at least one region on the surface of the first N+ doped layer is further provided with a third dielectric layer and a second N+ doped layer , and the first electrode penetrates through the first passivation layer to be in contact with the second N+ doped layer , wherein the at least one region on the surface of the first N+ doped layer corresponds to a region of the first electrode ; or wherein the semiconductor substrate is a P-type semiconductor substrate , the first surface is a back surface of the semiconductor substrate, and the second surface is a front surface of the semiconductor substrate, wherein at least one region on the surface of the first P+ doped layer is further provided with a fourth dielectric layer and a second P+ doped layer , and the second electrode penetrates through the second passivation layer to be in contact with the second P+ doped layer , wherein the at least one region on the surface of the first P+ doped layer corresponds to a region of the second electrode . a semiconductor substrate comprising a first surface and a second surface that are opposite to each other; a first dielectric layer located on the first surface ; a first N+ doped layer located on a surface of the first dielectric layer ; a first passivation layer located on a surface of the first N+ doped layer ; a first electrode located on a surface of the first passivation layer ; a second dielectric layer located on the second surface ; a first P+ doped layer located on a surface of the second dielectric layer ; a second passivation layer located on a surface of the first P+ doped layer ; and a second electrode located on a surface of the second passivation layer , wherein the semiconductor substrate is an N-type semiconductor substrate , the first surface is a front surface of the semiconductor substrate, and the second surface is a back surface of the semiconductor substrate, wherein at least one region on the surface of the first N+ doped layer is further provided with a third dielectric layer and a second N+ doped layer , and the first electrode penetrates through the first passivation layer to be in contact with the second N+ doped layer , wherein the at least one region on the surface of the first N+ doped layer corresponds to a region of the first electrode ; or wherein the semiconductor substrate is a P-type semiconductor substrate , the first surface is a back surface of the semiconductor substrate, and the second surface is a front surface of the semiconductor substrate, wherein at least one region on the surface of the first P+ doped layer is further provided with a fourth dielectric layer and a second P+ doped layer , and the second electrode penetrates through the second passivation layer to be in contact with the second P+ doped layer , wherein the at least one region on the surface of the first P+ doped layer corresponds to a region of the second electrode . <EOS>