A phase detector for use in a Clock Data Recovery CDR circuit, wherein the CDR circuit generates a clock signal (CK) according to a data signal (DA), comprising: a clock delay circuit , configured to receive the clock signal, a first control signal (SC1), and a second control signal (SC2), and to delay the clock signal by a delay time of the clock delay circuit so as to generate a first delay clock signal (CKD1), wherein the delay time of the clock delay circuit is adjustable according to the first control signal and the second control signal; a data delay circuit , configured to receive the data signal, the first control signal, and the second control signal, and to delay the data signal by a delay time of the data delay circuit so as to generate a first delay data signal (DAD1), wherein the delay time of the data delay circuit is adjustable according to the first control signal and the second control signal; a first control circuit , configured to receive the clock signal and the first delay clock signal, and to generate the first control signal and the second control signal according to the clock signal and the first delay clock signal so that each of the first control signal and the second control signal reaches a respective constant value when the delay time of the clock delay circuit is equal to half of a bit time of the clock signal; a main D flip-flop , configured to generate a register signal (SB) according to the data signal and the clock signal; and a logic circuit , configured to generate an up control signal (UP) and a down control signal (DOWN) according to the data signal, the first delay data signal, and the register signal so as to control a charge pump of the CDR circuit to adjust a time difference between a rising edge of the clock signal and a bit pulse central point of the data signal. a clock delay circuit , configured to receive the clock signal, a first control signal (SC1), and a second control signal (SC2), and to delay the clock signal by a delay time of the clock delay circuit so as to generate a first delay clock signal (CKD1), wherein the delay time of the clock delay circuit is adjustable according to the first control signal and the second control signal; a data delay circuit , configured to receive the data signal, the first control signal, and the second control signal, and to delay the data signal by a delay time of the data delay circuit so as to generate a first delay data signal (DAD1), wherein the delay time of the data delay circuit is adjustable according to the first control signal and the second control signal; a first control circuit , configured to receive the clock signal and the first delay clock signal, and to generate the first control signal and the second control signal according to the clock signal and the first delay clock signal so that each of the first control signal and the second control signal reaches a respective constant value when the delay time of the clock delay circuit is equal to half of a bit time of the clock signal; a main D flip-flop , configured to generate a register signal (SB) according to the data signal and the clock signal; and a logic circuit , configured to generate an up control signal (UP) and a down control signal (DOWN) according to the data signal, the first delay data signal, and the register signal so as to control a charge pump of the CDR circuit to adjust a time difference between a rising edge of the clock signal and a bit pulse central point of the data signal. <EOS>