An apparatus comprising: a memory controller comprising word line, WL, control circuitry and bit line, BL, control circuitry , the memory controller configured to apply a WL select bias voltage to a target WL and a BL select bias voltage to a target BL such that a selection voltage (VT_SEL) being the difference between the BL select bias voltage and the WL select bias voltage is applied across a corresponding target memory cell of a cross point memory array; the memory controller further comprising: sense circuitry configured to determine whether an impedance of the target memory cell transitions from a high impedance state to a low impedance state in response to the application of the selection voltage across the target memory cell, said transition occurring if the selection voltage is greater than or equal to a selection threshold voltage (Vt) of the target memory cell; wherein said memory controller is configured to increase the selection voltage if said sense circuitry determines that the impedance of the target memory cell does not transition from the high impedance state to the low impedance state in response to the application of the selection voltage across the target memory cell; the apparatus being characterized in that said memory controller includes a C-cell bias circuitry configured to, in response to the sense circuitry determining that the impedance of the target memory cell does not transition from a high impedance state to a low impedance state in response to the application of the selection voltage across the target memory cell, adjust at least one of a WL deselect bias voltage applied to a non-selected WL and a BL deselect bias voltage applied to a non-selected BL, such that non-selected memory cells of the cross point memory array corresponding to the non-selected WL and the target BL and/or non-selected memory cells corresponding to the target WL and the non-selected BL do not transition from a high impedance state to a low impedance state when the selection voltage is increased by said controller. sense circuitry configured to determine whether an impedance of the target memory cell transitions from a high impedance state to a low impedance state in response to the application of the selection voltage across the target memory cell, said transition occurring if the selection voltage is greater than or equal to a selection threshold voltage (Vt) of the target memory cell; wherein said memory controller is configured to increase the selection voltage if said sense circuitry determines that the impedance of the target memory cell does not transition from the high impedance state to the low impedance state in response to the application of the selection voltage across the target memory cell; the apparatus being characterized in that said memory controller includes a C-cell bias circuitry configured to, in response to the sense circuitry determining that the impedance of the target memory cell does not transition from a high impedance state to a low impedance state in response to the application of the selection voltage across the target memory cell, adjust at least one of a WL deselect bias voltage applied to a non-selected WL and a BL deselect bias voltage applied to a non-selected BL, such that non-selected memory cells of the cross point memory array corresponding to the non-selected WL and the target BL and/or non-selected memory cells corresponding to the target WL and the non-selected BL do not transition from a high impedance state to a low impedance state when the selection voltage is increased by said controller. <EOS>