An organic light emitting device, OLED, having a thin film transistor substrate comprising: a thin film transistor (T1) being a switching element for controlling an operation of a pixel of the OLED or being a driving element for driving a pixel of the OLED, the thin film transistor (T1) comprising a lower gate electrode on a substrate , an active layer on the lower gate electrode , wherein a gate insulation layer is interposed between the lower gate electrode and the active layer , source and drain electrodes on the active layer , and an upper gate electrode on the source electrode , drain electrode and active layer , the upper gate electrode covering a channel region defined by the source and drain electrodes , wherein a first passivation layer is interposed between the upper gate electrode and the source and drain electrodes , wherein the source electrode is connected with a data line of the pixel or with a power line of the pixel; and a contact portion formed at a predetermined interval from the drain electrode , the contact portion being formed in an island shape and electrically connecting the lower gate electrode exposed by a first contact hole (H1) formed in the gate insulation layer with the upper gate electrode being filled in a second contact hole (H2) formed in the first passivation layer , wherein the contact portion is exposed by the second contact hole (H2) and the contact portion is formed to interpose between the lower gate electrode and the upper gate electrode , characterized in that at least a portion of the contact portion is formed on the gate insulation layer at the periphery of the first contact hole (H1). a thin film transistor (T1) being a switching element for controlling an operation of a pixel of the OLED or being a driving element for driving a pixel of the OLED, the thin film transistor (T1) comprising a lower gate electrode on a substrate , an active layer on the lower gate electrode , wherein a gate insulation layer is interposed between the lower gate electrode and the active layer , source and drain electrodes on the active layer , and an upper gate electrode on the source electrode , drain electrode and active layer , the upper gate electrode covering a channel region defined by the source and drain electrodes , wherein a first passivation layer is interposed between the upper gate electrode and the source and drain electrodes , wherein the source electrode is connected with a data line of the pixel or with a power line of the pixel; and a contact portion formed at a predetermined interval from the drain electrode , the contact portion being formed in an island shape and electrically connecting the lower gate electrode exposed by a first contact hole (H1) formed in the gate insulation layer with the upper gate electrode being filled in a second contact hole (H2) formed in the first passivation layer , wherein the contact portion is exposed by the second contact hole (H2) and the contact portion is formed to interpose between the lower gate electrode and the upper gate electrode , characterized in that at least a portion of the contact portion is formed on the gate insulation layer at the periphery of the first contact hole (H1). <EOS>