A three-dimensional semiconductor memory device, comprising: a peripheral logic structure (PS) on a semiconductor substrate ; a horizontal semiconductor layer on the peripheral logic structure (PS) and including a cell array region (CAR) and a connection region (CNR); electrode structures (ST) extending in a first direction (D1) on the horizontal semiconductor layer and spaced apart in a second direction (D2) intersecting the first direction (D1), each of the electrode structure (ST) including gate electrodes vertically stacked on the horizontal semiconductor layer ; a through via structure (TVS) penetrating the electrode structures (ST) and the horizontal semiconductor layer , the through via structure (TVS) connecting the electrode structures (ST) to the peripheral logic structure (PS), first gate insulation regions (GIR1) extending in the first direction on the cell array region (CAR) and spaced apart from each other at a first interval; and second gate insulation regions (GIR2) extending in the first direction on the connection region (CNR) and spaced apart from each other at a second interval, wherein the first gate insulation regions (GIR1) vertically penetrate a first part of the each of the electrode structures (ST) and the second gate insulation regions (GIR2) are spaced apart from the first gate insulation regions (GIR1) and vertically penetrate a second part of the each of the electrode structures (ST), characterized in that , the second interval is less than the first interval. a peripheral logic structure (PS) on a semiconductor substrate ; a horizontal semiconductor layer on the peripheral logic structure (PS) and including a cell array region (CAR) and a connection region (CNR); electrode structures (ST) extending in a first direction (D1) on the horizontal semiconductor layer and spaced apart in a second direction (D2) intersecting the first direction (D1), each of the electrode structure (ST) including gate electrodes vertically stacked on the horizontal semiconductor layer ; a through via structure (TVS) penetrating the electrode structures (ST) and the horizontal semiconductor layer , the through via structure (TVS) connecting the electrode structures (ST) to the peripheral logic structure (PS), first gate insulation regions (GIR1) extending in the first direction on the cell array region (CAR) and spaced apart from each other at a first interval; and second gate insulation regions (GIR2) extending in the first direction on the connection region (CNR) and spaced apart from each other at a second interval, first gate insulation regions (GIR1) extending in the first direction on the cell array region (CAR) and spaced apart from each other at a first interval; and second gate insulation regions (GIR2) extending in the first direction on the connection region (CNR) and spaced apart from each other at a second interval, wherein the first gate insulation regions (GIR1) vertically penetrate a first part of the each of the electrode structures (ST) and the second gate insulation regions (GIR2) are spaced apart from the first gate insulation regions (GIR1) and vertically penetrate a second part of the each of the electrode structures (ST), characterized in that , the second interval is less than the first interval. <EOS>