A signal transmission circuit adapted to shift the level of and transmit a multiple of signals (OHE, OCE, UVE) between first and second circuits adapted to operate with mutually differing voltages (VS, GND) as reference potentials (VS, GND), wherein the first circuit on a signal transmission side includes first and second semiconductor switch elements adapted to transmit the reference potential (VS) or power supply voltage of the first circuit to the second circuit on a signal reception side by being alternatively driven so as to be turned on and off in accordance with the multiple of signals, and the second circuit on the signal reception side includes: a voltage conversion circuit , including an in-phase noise filter adapted to eliminate in-phase noise superimposed on the voltage transmitted from the first circuit via the first and second semiconductor switch elements , that is adapted to generate first and second pulse signals (ER1, ER2) in accordance with the voltage transmitted via the first and second semiconductor switch elements ; a latch circuit adapted to latch each of the first and second pulse signals (ER1, ER2) with the logical sum output of the first and second pulse signals (ER1, ER2) generated by the voltage conversion circuit as a clock, the logical sum output obtained via an OR circuit (OR), wherein the latch circuit includes in parallel a first shift register formed of multiple stages of D-type flip-flops connected in cascade and a second shift register formed of multiple stages of D-type flip-flops connected in cascade, wherein the first shift register of the latch circuit is adapted to latch the first pulse signal (ER1) and the second shift register of the latch circuit is adapted to latch the second pulse signal (ER2) ; and a signal analysis circuit adapted to determine the category of the multiple of signals (OHE, OCE, UVE) by analyzing the first and second pulse signals (ER1, ER2) latched by the latch circuit , and to generate an output signal (ERDET, OHER, OCER, UVER, RXER) in accordance with the determined signal category. a voltage conversion circuit , including an in-phase noise filter adapted to eliminate in-phase noise superimposed on the voltage transmitted from the first circuit via the first and second semiconductor switch elements , that is adapted to generate first and second pulse signals (ER1, ER2) in accordance with the voltage transmitted via the first and second semiconductor switch elements ; a latch circuit adapted to latch each of the first and second pulse signals (ER1, ER2) with the logical sum output of the first and second pulse signals (ER1, ER2) generated by the voltage conversion circuit as a clock, the logical sum output obtained via an OR circuit (OR), wherein the latch circuit includes in parallel a first shift register formed of multiple stages of D-type flip-flops connected in cascade and a second shift register formed of multiple stages of D-type flip-flops connected in cascade, wherein the first shift register of the latch circuit is adapted to latch the first pulse signal (ER1) and the second shift register of the latch circuit is adapted to latch the second pulse signal (ER2) ; and a signal analysis circuit adapted to determine the category of the multiple of signals (OHE, OCE, UVE) by analyzing the first and second pulse signals (ER1, ER2) latched by the latch circuit , and to generate an output signal (ERDET, OHER, OCER, UVER, RXER) in accordance with the determined signal category. <EOS>