A print head memory device , comprising: a number of memory EPROM banks (114-1, ..., 114-N), each comprising a memory array; and a number of serial-in parallel-out shift registers (112-1, ..., 112-N), wherein each of the registers is connected to each of the number of memory banks (114-1, ..., 114-N), and the registers are adapted to generate a three-dimensional memory address based on input signals, wherein generating the three-dimensional EPROM address comprises generating a number of outputs, the outputs comprising: a row select data signal specifying a row portion of the three-dimensional memory address, a column select data signal specifying a column portion of the three-dimensional memory address, and a bank select data signal specifying a memory bank (114-1, ..., 114-N) of the number of memory banks (114-1, ..., 114-N) associated with the row select data signal and the column select data signal , wherein: the number of rows of each memory bank is equal to a number of clock cycles associated with a shift register specifying the row select data signal; the number of columns of each memory bank is equal to a number of clock cycles associated with a shift register specifying the column data signal; and the number of EPROM banks is equal to a number of clock cycles associated with a shift register generating the bank select data signal. a number of memory EPROM banks (114-1, ..., 114-N), each comprising a memory array; and a number of serial-in parallel-out shift registers (112-1, ..., 112-N), wherein each of the registers is connected to each of the number of memory banks (114-1, ..., 114-N), and the registers are adapted to generate a three-dimensional memory address based on input signals, wherein generating the three-dimensional EPROM address comprises generating a number of outputs, the outputs comprising: a row select data signal specifying a row portion of the three-dimensional memory address, a column select data signal specifying a column portion of the three-dimensional memory address, and a bank select data signal specifying a memory bank (114-1, ..., 114-N) of the number of memory banks (114-1, ..., 114-N) associated with the row select data signal and the column select data signal , wherein: the number of rows of each memory bank is equal to a number of clock cycles associated with a shift register specifying the row select data signal; the number of columns of each memory bank is equal to a number of clock cycles associated with a shift register specifying the column data signal; and the number of EPROM banks is equal to a number of clock cycles associated with a shift register generating the bank select data signal. a row select data signal specifying a row portion of the three-dimensional memory address, a column select data signal specifying a column portion of the three-dimensional memory address, and a bank select data signal specifying a memory bank (114-1, ..., 114-N) of the number of memory banks (114-1, ..., 114-N) associated with the row select data signal and the column select data signal , wherein: the number of rows of each memory bank is equal to a number of clock cycles associated with a shift register specifying the row select data signal; the number of columns of each memory bank is equal to a number of clock cycles associated with a shift register specifying the column data signal; and the number of EPROM banks is equal to a number of clock cycles associated with a shift register generating the bank select data signal. <EOS>