A memory device comprising at least one memory cell comprising: a first transistor (102. 802) coupled between a first storage node and a first supply voltage (GND, V DD ): a second transistor coupled between a second storage node and said first supply voltage, a control terminal of said first transistor being coupled to said second storage node, and a control terminal of said second transistor being coupled to said first storage node; and a single resistance switching element , wherein said single resistive switching element is coupled in series with said first transistor and is programmable to have one of first and second resistances (R min , R max ), wherein sad first storage node is coupled to a first access line (BL) via a third transistor , and said second storage node is coupled to a second access line (BLB) via a fourth transistor , said single resistance switching element being coupled between said first transistor and said first supply voltage, a first branch of said memory cell comprising said element and said first transistor, and a second branch of said memory cell comprising said second transistor, said second branch being adapted to have a resistance R 2 such that: R 2 = R ON 1 + R min + R max / 2 , where R ON1 is the ON resistance of said transistor of said first branch , and R min and R max are said first and second resistances respectively, said second branch comprising a fixed value resistor coupled in series with said transistor of said second branch, said first transistor being the only transistor of a first inverter of said at least one memory cell, and said second transistor is the only transistor of a second inverter of said at least one memory cell. a first transistor (102. 802) coupled between a first storage node and a first supply voltage (GND, V DD ): a second transistor coupled between a second storage node and said first supply voltage, a control terminal of said first transistor being coupled to said second storage node, and a control terminal of said second transistor being coupled to said first storage node; and a single resistance switching element , wherein said single resistive switching element is coupled in series with said first transistor and is programmable to have one of first and second resistances (R min , R max ), wherein sad first storage node is coupled to a first access line (BL) via a third transistor , and said second storage node is coupled to a second access line (BLB) via a fourth transistor , said single resistance switching element being coupled between said first transistor and said first supply voltage, a first branch of said memory cell comprising said element and said first transistor, and a second branch of said memory cell comprising said second transistor, said second branch being adapted to have a resistance R 2 such that: R 2 = R ON 1 + R min + R max / 2 , where R ON1 is the ON resistance of said transistor of said first branch , and R min and R max are said first and second resistances respectively, said second branch comprising a fixed value resistor coupled in series with said transistor of said second branch, said first transistor being the only transistor of a first inverter of said at least one memory cell, and said second transistor is the only transistor of a second inverter of said at least one memory cell. where R ON1 is the ON resistance of said transistor of said first branch , and R min and R max are said first and second resistances respectively, said second branch comprising a fixed value resistor coupled in series with said transistor of said second branch, said first transistor being the only transistor of a first inverter of said at least one memory cell, and said second transistor is the only transistor of a second inverter of said at least one memory cell. <EOS>