A method for manufacturing a microelectronic device comprising at least two transistors each comprising a channel in the form of a wire extending mainly in a first direction x, a gate surrounding said channel , a source and a drain linked to the channel , said transistors being stacked in a third direction z and each occupying a level n z , n z = n 1 ...n 4 , of a given altitude in the third direction z, said method comprising the following steps: - Forming on a substrate a stack (E) in the third direction z comprising at least two layers made of a first semiconductor material separated by at least one sacrificial layer made of a second semiconductor material, - Forming from this stack (E) openings (201, 202, 301, 301 c , 401) defining transistor patterns , the transistor patterns each comprising a central portion extending particularly and preferably mainly in the first direction x and first and second peripheral portions extending on either side of the central portion , said central portion being intended to form the channels of the transistors and said first and second peripheral portions being intended to form the sources and drains of the transistors respectively, - Forming sacrificial gates partly in the openings , spanning the central portions of the transistor patterns and extending mainly in a second direction y normal to the first direction x, - Removing, from the openings , the second semiconductor material from the at least one sacrificial layer of the transistor patterns , - Filling with a second dielectric material a first space left by the removal, at the first and second peripheral portions of the transistor patterns , of the at least one sacrificial layer , - Removing the sacrificial gates , - Filling with a gate material a second space left by the removal, at the central portions of the transistor patterns , of the at least one sacrificial layer , so as to form so-called gate-all-around totally surrounding the channels of the transistors by at least one level n z of the given levels of altitude. - Forming on a substrate a stack (E) in the third direction z comprising at least two layers made of a first semiconductor material separated by at least one sacrificial layer made of a second semiconductor material, - Forming from this stack (E) openings (201, 202, 301, 301 c , 401) defining transistor patterns , the transistor patterns each comprising a central portion extending particularly and preferably mainly in the first direction x and first and second peripheral portions extending on either side of the central portion , said central portion being intended to form the channels of the transistors and said first and second peripheral portions being intended to form the sources and drains of the transistors respectively, - Forming sacrificial gates partly in the openings , spanning the central portions of the transistor patterns and extending mainly in a second direction y normal to the first direction x, - Removing, from the openings , the second semiconductor material from the at least one sacrificial layer of the transistor patterns , - Filling with a second dielectric material a first space left by the removal, at the first and second peripheral portions of the transistor patterns , of the at least one sacrificial layer , - Removing the sacrificial gates , - Filling with a gate material a second space left by the removal, at the central portions of the transistor patterns , of the at least one sacrificial layer , so as to form so-called gate-all-around totally surrounding the channels of the transistors by at least one level n z of the given levels of altitude. <EOS>