A programmable logic region for use on a programmable integrated circuit, the programmable logic region comprising: a first set of look-up tables (62A; 64, 66) adapted to receive programmable logic region input signals for the programmable logic region ; a second set of look-up tables adapted to provide programmable logic region output signals for the programmable logic region ; and multiplexer circuitry coupled between the first set of look-up tables (62A; 64, 66) and the second set of look-up tables , wherein at least one multiplexer in the multiplexer circuitry is adapted to receive the programmable logic region input signals (B, E) and to output signals (S1) from the first set of look-up tables (62A; 64, 66) and to provide corresponding selected signals to the second set of look-up tables ; wherein the multiplexer circuitry is adapted to receive output signals from at least two different look-up tables of the first set of look-up tables (62A; 64, 66) and is configured to route one of the output signals from the two different look-up tables to a given look-up table of the second set of look-up tables . characterized in that at least one look-up table of the first set of look-up tables (62A; 64, 66) is adapted to receive a carry input signal (C IN ) and produce a first carry output signal (COUT 1 ) and a first sum signal based at least partly on the carry input signal (C IN ), and wherein the programmable logic region further comprises a routing path between the at least one look-up table of the first set of look-up tables (62A; 64, 66) and the given look-up table of the second set of look-up tables , wherein the routing path bypasses the multiplexer circuitry and wherein the given look-up table of the second set of look-up tables receives the first carry output signal from the first set of look-up tables (62A; 64, 66) over the routing path and produces a second carry output signal and a second sum signal based at least partly on the first carry output signal. a first set of look-up tables (62A; 64, 66) adapted to receive programmable logic region input signals for the programmable logic region ; a second set of look-up tables adapted to provide programmable logic region output signals for the programmable logic region ; and multiplexer circuitry coupled between the first set of look-up tables (62A; 64, 66) and the second set of look-up tables , wherein at least one multiplexer in the multiplexer circuitry is adapted to receive the programmable logic region input signals (B, E) and to output signals (S1) from the first set of look-up tables (62A; 64, 66) and to provide corresponding selected signals to the second set of look-up tables ; wherein the multiplexer circuitry is adapted to receive output signals from at least two different look-up tables of the first set of look-up tables (62A; 64, 66) and is configured to route one of the output signals from the two different look-up tables to a given look-up table of the second set of look-up tables . characterized in that at least one look-up table of the first set of look-up tables (62A; 64, 66) is adapted to receive a carry input signal (C IN ) and produce a first carry output signal (COUT 1 ) and a first sum signal based at least partly on the carry input signal (C IN ), and wherein the programmable logic region further comprises a routing path between the at least one look-up table of the first set of look-up tables (62A; 64, 66) and the given look-up table of the second set of look-up tables , wherein the routing path bypasses the multiplexer circuitry and wherein the given look-up table of the second set of look-up tables receives the first carry output signal from the first set of look-up tables (62A; 64, 66) over the routing path and produces a second carry output signal and a second sum signal based at least partly on the first carry output signal. <EOS>