A differential Colpitts oscillator circuit (100; 200) comprising: a first transistor pair (M1, M3) having a first tap point (150; 250) between a source of one transistor (M1) and a drain of the other transistor (M3); a first power supply (VDD) connected to a first transistor (M1) of the first transistor pair (M1, M3); a first inductor (L a ) connected in a first line (170; 270) between a gate (aa) of the first transistor (M1) of the first transistor pair (M1, M3) and a connecting point (140; 240); a second transistor pair (M2, M4) having a second tap point (160; 260) between a source of one transistor (M2) and a drain of the other transistor (M4); a second power supply (VDD) connected to a first transistor (M2) of the second transistor pair (M2, M4); a second inductor (L b ) connected in a second line (190; 290) between a gate (bb) of the first transistor (M2) of the second transistor pair (M2, M4) and the connecting point (140; 240); a first variable capacitor (C2; C2') connected in a third line (180; 280) between the first and second tap points (150, 160; 250, 260); and a resistor (R) connected to a second transistor (M3) of the first transistor pair (M1, M3) and to a second transistor (M4) of the second transistor pair (M2, M4), the resistor also being connected to a ground point (130; 230); characterized in that a gate (a) of the second transistor (M4) of the second transistor pair (M2, M4) is connected to a first tap point (A) of the first inductor (L a ) and a gate (b) of the second transistor (M3) of the first transistor pair (M1, M3) is connected to a second tap point (B) of the second inductor (L b ). a first transistor pair (M1, M3) having a first tap point (150; 250) between a source of one transistor (M1) and a drain of the other transistor (M3); a first power supply (VDD) connected to a first transistor (M1) of the first transistor pair (M1, M3); a first inductor (L a ) connected in a first line (170; 270) between a gate (aa) of the first transistor (M1) of the first transistor pair (M1, M3) and a connecting point (140; 240); a second transistor pair (M2, M4) having a second tap point (160; 260) between a source of one transistor (M2) and a drain of the other transistor (M4); a second power supply (VDD) connected to a first transistor (M2) of the second transistor pair (M2, M4); a second inductor (L b ) connected in a second line (190; 290) between a gate (bb) of the first transistor (M2) of the second transistor pair (M2, M4) and the connecting point (140; 240); a first variable capacitor (C2; C2') connected in a third line (180; 280) between the first and second tap points (150, 160; 250, 260); and a resistor (R) connected to a second transistor (M3) of the first transistor pair (M1, M3) and to a second transistor (M4) of the second transistor pair (M2, M4), the resistor also being connected to a ground point (130; 230); characterized in that a gate (a) of the second transistor (M4) of the second transistor pair (M2, M4) is connected to a first tap point (A) of the first inductor (L a ) and a gate (b) of the second transistor (M3) of the first transistor pair (M1, M3) is connected to a second tap point (B) of the second inductor (L b ). <EOS>