A method implemented by a system comprising a direct memory access circuit , a central processing unit , and a memory , the method comprising: a) initializing a register bank of a channel (channel-1) of the direct memory access circuit; b) executing transfer cycles over said channel (channel-1), each of said cycles comprising at least one data transfer configured by a content of the register bank, and an update of the content of the register bank from an item recorded into memory, at an address indicated by a second field (C-@) of the register bank; c) at each of said cycles, according to at least one first field (C-sig1) of the register bank, c1) when the first field indicates that no first signal has to be generated carrying on the execution of the transfer cycles over said channels and c2) when the first field indicates that the first signal has to be generated generating the first signal (sig1) and suspending the execution of the transfer cycles over said channel; d) at each reception of the first signal (sig1) by the central processing unit , according to a state of the system, d1) when the system is in a first state generating a second signal (sig2), and d2) when the system is in a second state different from the first state recording into the memory a first item (LLI'(N+1); LLI'(N); LLI' ) representative of a next update of the register bank, and then generating the second signal (sig2); and e) at each reception of the second signal by the direct memory access circuit, carrying on the execution of said transfer cycles over said channel, wherein, at step d2), the central processing unit programs another channel (channel-2) of the direct memory access circuit so that said other channel records into the memory said first item (LLI' ) and generates the second signal (sig2) after the recording of said first item (LLI' ) into the memory . a) initializing a register bank of a channel (channel-1) of the direct memory access circuit; b) executing transfer cycles over said channel (channel-1), each of said cycles comprising at least one data transfer configured by a content of the register bank, and an update of the content of the register bank from an item recorded into memory, at an address indicated by a second field (C-@) of the register bank; c) at each of said cycles, according to at least one first field (C-sig1) of the register bank, c1) when the first field indicates that no first signal has to be generated carrying on the execution of the transfer cycles over said channels and c2) when the first field indicates that the first signal has to be generated generating the first signal (sig1) and suspending the execution of the transfer cycles over said channel; d) at each reception of the first signal (sig1) by the central processing unit , according to a state of the system, d1) when the system is in a first state generating a second signal (sig2), and d2) when the system is in a second state different from the first state recording into the memory a first item (LLI'(N+1); LLI'(N); LLI' ) representative of a next update of the register bank, and then generating the second signal (sig2); and e) at each reception of the second signal by the direct memory access circuit, carrying on the execution of said transfer cycles over said channel, <EOS>