A power-on-reset circuit comprising: an execution circuit comprising a first input terminal , a second input terminal , and a first output terminal , the first input terminal connected to a power supply voltage, a voltage at the second input terminal having a low level at an initial state, and a voltage at the first output terminal having a low level, wherein the voltage at the first output terminal transitions from the low level to a high level when the power supply voltage at the first input terminal and the voltage at the second input terminal are not less than the high threshold voltage of the execution circuit ; and a control circuit comprising a third input terminal connected to the first output terminal , a fourth input terminal connected to the first input terminal , and a second output terminal connected to the second input terminal , wherein the voltage at the second input terminal transitions from the low level to the high level when a difference between the power supply voltage at the first input terminal and the voltage at the first output terminal is greater than a predetermined voltage difference, wherein a voltage difference detection circuit of the control circuit comprises a PMOS transistor having a substrate connected to the power supply voltage, the first output terminal being connected to the gate of the PMOS transistor so that when the power supply voltage rises to the turn-on voltage of the PMOS transistor, then the predetermined voltage difference is reached, and wherein the execution circuit comprises a NAND gate and an inverter , the NAND gate having a first input terminal connected to the first input terminal of the execution circuit , a second input terminal connected to the second input terminal of the execution circuit , and an output terminal connected to an input terminal of the inverter , and the inverter having an output terminal connected to the first output terminal of the execution circuit . an execution circuit comprising a first input terminal , a second input terminal , and a first output terminal , the first input terminal connected to a power supply voltage, a voltage at the second input terminal having a low level at an initial state, and a voltage at the first output terminal having a low level, wherein the voltage at the first output terminal transitions from the low level to a high level when the power supply voltage at the first input terminal and the voltage at the second input terminal are not less than the high threshold voltage of the execution circuit ; and a control circuit comprising a third input terminal connected to the first output terminal , a fourth input terminal connected to the first input terminal , and a second output terminal connected to the second input terminal , wherein the voltage at the second input terminal transitions from the low level to the high level when a difference between the power supply voltage at the first input terminal and the voltage at the first output terminal is greater than a predetermined voltage difference, wherein a voltage difference detection circuit of the control circuit comprises a PMOS transistor having a substrate connected to the power supply voltage, the first output terminal being connected to the gate of the PMOS transistor so that when the power supply voltage rises to the turn-on voltage of the PMOS transistor, then the predetermined voltage difference is reached, and <EOS>