A delay circuit which is reconfigurable and is included in a delay monitor circuit for measuring a delay in a signal transmission time in an integrated circuit, comprising: an input node (In) for inputting an input signal; an output node (Out) for outputting an output signal; a first inversion circuit including a serial circuit which comprises a pull-up circuit adapted to connect a power supply potential to the output node when being turned on based on the input signal, and a pull-down circuit adapted to connect a ground potential to the output node when being turned on based on the input signal; a second inversion circuit including a serial circuit which comprises a pull-up circuit adapted to connect the power supply potential to the output node when being turned on based on the input signal, and a pull-down circuit adapted to connect the ground potential to the output node when being turned on based on the input signal; a first pass transistor connected in series to the pull-up circuit in the first inversion circuit, between the power supply potential and the output node; a second pass transistor connected in series to the pull-down circuit in the first inversion logic circuit, between the ground potential and the output node; a third pass transistor connected in series between the input node and an input of the pull-up circuit in the second inversion circuit; and a fourth pass transistor connected in series between the input node and an input of the pull-down circuit in the second inversion circuit, wherein the first to fourth pass transistors (6-9) are controlled independently of each other by respective control signals (C1-C4), and wherein a delay characteristic of the reconfigurable delay circuit is changed by a combination of control signals (C1-C4) applied to gates of the first to fourth pass transistors (6-9). an input node (In) for inputting an input signal; an output node (Out) for outputting an output signal; a first inversion circuit including a serial circuit which comprises a pull-up circuit adapted to connect a power supply potential to the output node when being turned on based on the input signal, and a pull-down circuit adapted to connect a ground potential to the output node when being turned on based on the input signal; a second inversion circuit including a serial circuit which comprises a pull-up circuit adapted to connect the power supply potential to the output node when being turned on based on the input signal, and a pull-down circuit adapted to connect the ground potential to the output node when being turned on based on the input signal; a first pass transistor connected in series to the pull-up circuit in the first inversion circuit, between the power supply potential and the output node; a second pass transistor connected in series to the pull-down circuit in the first inversion logic circuit, between the ground potential and the output node; a third pass transistor connected in series between the input node and an input of the pull-up circuit in the second inversion circuit; and a fourth pass transistor connected in series between the input node and an input of the pull-down circuit in the second inversion circuit, wherein the first to fourth pass transistors (6-9) are controlled independently of each other by respective control signals (C1-C4), and wherein a delay characteristic of the reconfigurable delay circuit is changed by a combination of control signals (C1-C4) applied to gates of the first to fourth pass transistors (6-9). <EOS>