An image processor comprising: a coding circuit for dividing a target image (DVin) into a plurality of tiles, and coding the tiles in units of tile to generate a coding stream (BSout) and a local decoding image (LDI); a compression circuit for compressing the local decoding image (LDI) in units of image block; and a determination circuit for determining whether a tile boundary is included in each of the image blocks of the local decoding image (LDI), characterized in that : the compression by the compression circuit is configured to be performed in parallel with the coding by the coding circuit , and the compression circuit is configured to: if the determination circuit determines that a tile boundary is not included in an image block, compress the image block, and write the compressed image block into a memory , and if the determination circuit determines that a tile boundary is included in an image block, not compress the image block, and write one of two areas of the non-compressed image block that is separated by the tile boundary and belongs to a firstly coded tile into the memory , and then write the other area of the non-compressed image block that is separated by the tile boundary and belongs to a secondly coded tile into the memory . a coding circuit for dividing a target image (DVin) into a plurality of tiles, and coding the tiles in units of tile to generate a coding stream (BSout) and a local decoding image (LDI); a compression circuit for compressing the local decoding image (LDI) in units of image block; and a determination circuit for determining whether a tile boundary is included in each of the image blocks of the local decoding image (LDI), characterized in that : the compression by the compression circuit is configured to be performed in parallel with the coding by the coding circuit , and the compression circuit is configured to: if the determination circuit determines that a tile boundary is not included in an image block, compress the image block, and write the compressed image block into a memory , and if the determination circuit determines that a tile boundary is included in an image block, not compress the image block, and write one of two areas of the non-compressed image block that is separated by the tile boundary and belongs to a firstly coded tile into the memory , and then write the other area of the non-compressed image block that is separated by the tile boundary and belongs to a secondly coded tile into the memory . the compression by the compression circuit is configured to be performed in parallel with the coding by the coding circuit , and the compression circuit is configured to: if the determination circuit determines that a tile boundary is not included in an image block, compress the image block, and write the compressed image block into a memory , and if the determination circuit determines that a tile boundary is included in an image block, not compress the image block, and write one of two areas of the non-compressed image block that is separated by the tile boundary and belongs to a firstly coded tile into the memory , and then write the other area of the non-compressed image block that is separated by the tile boundary and belongs to a secondly coded tile into the memory . if the determination circuit determines that a tile boundary is not included in an image block, compress the image block, and write the compressed image block into a memory , and if the determination circuit determines that a tile boundary is included in an image block, not compress the image block, and write one of two areas of the non-compressed image block that is separated by the tile boundary and belongs to a firstly coded tile into the memory , and then write the other area of the non-compressed image block that is separated by the tile boundary and belongs to a secondly coded tile into the memory . <EOS>