A pair of memory cells, comprising: a semiconductor substrate having an upper surface; first and second trenches formed into the upper surface and spaced apart from each other; a first floating gate of conductive material disposed in the first trench and insulated from the substrate; a second floating gate of conductive material disposed in the second trench and insulated from the substrate; an erase gate of conductive material, and disposed laterally between and insulated from the first and second floating gates; a first word line gate of conductive material disposed over and insulated from a portion of the upper surface that is adjacent to the first floating gate; a second word line gate of conductive material disposed over and insulated from a portion of the upper surface that is adjacent to the second floating gate; a source region formed in the substrate laterally between the first and second trenches, laterally between the first and second floating gates, and vertically under the first portion of the erase gate; a first drain region formed in a portion of the upper surface adjacent to the first word line gate; a second drain region formed in a portion of the upper surface adjacent to the second word line gate; wherein a first channel region of the substrate extends from the source region to the first drain region, including extending at least under the first trench, along a side wall of the first trench, and along a portion of the upper surface disposed under the first word line gate; and wherein a second channel region of the substrate extends from the source region to the second drain region, including extending at least under the second trench, along a side wall of the second trench, and along a portion of the upper surface disposed under the second word line gate, characterised in that the erase gate has a first portion which extends into the upper surface of the substrate. a semiconductor substrate having an upper surface; first and second trenches formed into the upper surface and spaced apart from each other; a first floating gate of conductive material disposed in the first trench and insulated from the substrate; a second floating gate of conductive material disposed in the second trench and insulated from the substrate; an erase gate of conductive material, and disposed laterally between and insulated from the first and second floating gates; a first word line gate of conductive material disposed over and insulated from a portion of the upper surface that is adjacent to the first floating gate; a second word line gate of conductive material disposed over and insulated from a portion of the upper surface that is adjacent to the second floating gate; a source region formed in the substrate laterally between the first and second trenches, laterally between the first and second floating gates, and vertically under the first portion of the erase gate; a first drain region formed in a portion of the upper surface adjacent to the first word line gate; a second drain region formed in a portion of the upper surface adjacent to the second word line gate; wherein a first channel region of the substrate extends from the source region to the first drain region, including extending at least under the first trench, along a side wall of the first trench, and along a portion of the upper surface disposed under the first word line gate; and wherein a second channel region of the substrate extends from the source region to the second drain region, including extending at least under the second trench, along a side wall of the second trench, and along a portion of the upper surface disposed under the second word line gate, characterised in that the erase gate has a first portion which extends into the upper surface of the substrate. <EOS>