A power management unit , comprising: a digital control circuit operative to generate first and second voltage values (logic_vsel, mem_vsel) that are configured to gradually ramp during a transition from a first Operating Performance Point "OPP" to a second OPP, each OPP specifying target values for corresponding first and second supply voltages (V logic , V memory ), in response to a selection of the second OPP communicated to the power management unit ; and first and second voltage regulators operative to convert the first and second voltage values (logic_vsel, mem_vsel) to the first and second supply voltages (V logic , V memory ) having corresponding voltage levels; wherein the digital control circuit comprises: a plurality of registers storing at least one trigger point voltage value (TRIGGER1-3), the trigger points dividing a permissible range of values of the first supply voltage (V logic ) into two or more zones and OPP target values for the first and second supply voltages (V logic , V memory ) for each selectable OPP; and a regulator control circuit operative to generate the first and second voltage values (logic_vsel, mem_vsel) according to the OPP target values for the first OPP and the second OPP read from the registers, whereby the second voltage value (mem_vsel) is constrained, both in the voltage value and in the difference between the second voltage value (mem_vsel) and the first voltage value (logic_vsel), the constraints being unique to each zone. a digital control circuit operative to generate first and second voltage values (logic_vsel, mem_vsel) that are configured to gradually ramp during a transition from a first Operating Performance Point "OPP" to a second OPP, each OPP specifying target values for corresponding first and second supply voltages (V logic , V memory ), in response to a selection of the second OPP communicated to the power management unit ; and first and second voltage regulators operative to convert the first and second voltage values (logic_vsel, mem_vsel) to the first and second supply voltages (V logic , V memory ) having corresponding voltage levels; wherein the digital control circuit comprises: a plurality of registers storing at least one trigger point voltage value (TRIGGER1-3), the trigger points dividing a permissible range of values of the first supply voltage (V logic ) into two or more zones and OPP target values for the first and second supply voltages (V logic , V memory ) for each selectable OPP; and a regulator control circuit operative to generate the first and second voltage values (logic_vsel, mem_vsel) according to the OPP target values for the first OPP and the second OPP read from the registers, whereby the second voltage value (mem_vsel) is constrained, both in the voltage value and in the difference between the second voltage value (mem_vsel) and the first voltage value (logic_vsel), the constraints being unique to each zone. a plurality of registers storing at least one trigger point voltage value (TRIGGER1-3), the trigger points dividing a permissible range of values of the first supply voltage (V logic ) into two or more zones and OPP target values for the first and second supply voltages (V logic , V memory ) for each selectable OPP; and a regulator control circuit operative to generate the first and second voltage values (logic_vsel, mem_vsel) according to the OPP target values for the first OPP and the second OPP read from the registers, whereby the second voltage value (mem_vsel) is constrained, both in the voltage value and in the difference between the second voltage value (mem_vsel) and the first voltage value (logic_vsel), the constraints being unique to each zone. <EOS>