A semiconductor device comprising: a substrate ; a first conductivity type source region formed on a main surface of the substrate ; a second conductivity type well region formed on the main surface of the substrate and in contact with the first conductivity type source region ; a first conductivity type drift region formed on the main surface of the substrate and in contact with the second conductivity type well region ; a first conductivity type drain region formed on the main surface of the substrate and in contact with the first conductivity type drift region ; a first electrode electrically connected to the first conductivity type source region ; a second electrode electrically connected to the first conductivity type drain region ; an insulating film formed on an inner surface of a gate groove formed in contact with the first conductivity type source region , the second conductivity type well region , and the first conductivity type drift region ; a third electrode formed in contact with the first conductivity type source region , the second conductivity type well region , and the first conductivity type drift region through the insulating film ; and a parasitic capacitance reduction region placed between the third electrode and the first electrode , and formed in contact with the first conductivity type source region and in contact with the third electrode through the insulating film , characterized in that the parasitic capacitance reduction region is formed from the same material as that of the substrate and has a lower impurity concentration than the first conductivity type source region . a substrate ; a first conductivity type source region formed on a main surface of the substrate ; a second conductivity type well region formed on the main surface of the substrate and in contact with the first conductivity type source region ; a first conductivity type drift region formed on the main surface of the substrate and in contact with the second conductivity type well region ; a first conductivity type drain region formed on the main surface of the substrate and in contact with the first conductivity type drift region ; a first electrode electrically connected to the first conductivity type source region ; a second electrode electrically connected to the first conductivity type drain region ; an insulating film formed on an inner surface of a gate groove formed in contact with the first conductivity type source region , the second conductivity type well region , and the first conductivity type drift region ; a third electrode formed in contact with the first conductivity type source region , the second conductivity type well region , and the first conductivity type drift region through the insulating film ; and a parasitic capacitance reduction region placed between the third electrode and the first electrode , and formed in contact with the first conductivity type source region and in contact with the third electrode through the insulating film , characterized in that the parasitic capacitance reduction region is formed from the same material as that of the substrate and has a lower impurity concentration than the first conductivity type source region . <EOS>