A display device comprising: a substrate including a display area (DP) having a plurality of subpixels (SP) and a bezel area (BP) around the display area (DP); a plurality of insulating layers (116, GI, ILD1, ILD2) sequentially disposed on the display area and the bezel area of the substrate , wherein the plurality of insulating layers (116, GI, ILD1, ILD2) includes a second buffer layer , a gate insulating layer (GI), a first interlayer dielectric layer (ILD1), and a second interlayer dielectric layer (ILD2); at least one via hole (VIA1, VIA2) passing through the plurality of insulating layers in the bezel area, wherein the via hole (VIA1, VIA2) passes through the second buffer layer , the gate insulating layer (GI), the first interlayer dielectric layer (ILD1), and the second interlayer dielectric layer (ILD2); a passivation layer (PAS) positioned on the second interlayer dielectric layer (ILD2), wherein the passivation layer (PAS) contacts a first buffer layer formed under the plurality of insulating layers through the via hole (VIA1, VIA2); and at least one opening (PAH1, PAH2) passing through the passivation layer (PAS) on the plurality of insulating layers (116, GI, ILD1, ILD2) in the bezel area, wherein the via hole (VIA1, VIA2) and the at least one opening (PAH1, PAH2) each surround the display area (DP) to form a respective closed loop, wherein the at least one via hole (VIA1, VIA2) and the at least one opening (PAH1, PAH2) are configured to suppress propagation of cracks in the bezel area (BP), and wherein the via hole (VIA1, VIA2) is further configured to block moisture penetration through the cracks. a substrate including a display area (DP) having a plurality of subpixels (SP) and a bezel area (BP) around the display area (DP); a plurality of insulating layers (116, GI, ILD1, ILD2) sequentially disposed on the display area and the bezel area of the substrate , wherein the plurality of insulating layers (116, GI, ILD1, ILD2) includes a second buffer layer , a gate insulating layer (GI), a first interlayer dielectric layer (ILD1), and a second interlayer dielectric layer (ILD2); at least one via hole (VIA1, VIA2) passing through the plurality of insulating layers in the bezel area, wherein the via hole (VIA1, VIA2) passes through the second buffer layer , the gate insulating layer (GI), the first interlayer dielectric layer (ILD1), and the second interlayer dielectric layer (ILD2); a passivation layer (PAS) positioned on the second interlayer dielectric layer (ILD2), wherein the passivation layer (PAS) contacts a first buffer layer formed under the plurality of insulating layers through the via hole (VIA1, VIA2); and at least one opening (PAH1, PAH2) passing through the passivation layer (PAS) on the plurality of insulating layers (116, GI, ILD1, ILD2) in the bezel area, wherein the via hole (VIA1, VIA2) and the at least one opening (PAH1, PAH2) each surround the display area (DP) to form a respective closed loop, wherein the at least one via hole (VIA1, VIA2) and the at least one opening (PAH1, PAH2) are configured to suppress propagation of cracks in the bezel area (BP), and wherein the via hole (VIA1, VIA2) is further configured to block moisture penetration through the cracks. <EOS>