A transmitter apparatus comprising: an encoder configured to encode information bits to generate parity bits based on a parity check matrix of a low density parity check, LDPC code according to a code rate of 12/15 and a code length of 64800; an interleaver comprising: a parity interleaver configured to interleave the parity bits, a group interleaver configured to split a codeword comprising the information bits and the interleaved parity bits into a plurality of bit groups and interleave the plurality of bit groups; and a block interleaver configured to interleave the interleaved plurality of bit groups using a plurality of columns to provide an interleaved codeword; and a modulator configured to map the bits of the interleaved codeword onto modulation symbols for 256-quadrature amplitude modulation, QAM, wherein the parity check matrix comprises an information submatrix corresponding to the information bits with quasi-cyclic structure and a parity submatrix corresponding to the parity bits with a dual diagonal structure, wherein the number of the plurality of columns is 8, and wherein the group interleaver is configured to interleave the plurality of bit groups based on the following equation: Y j = X π j for 0≤j<N group for where X j is a j th bit group among the plurality of bit groups, Y j is a j th bit group among the interleaved plurality of bit groups, N group is a total number of the plurality of bit groups, and π(j) denotes a permutation order for the interleaving of the plurality of bit groups, and wherein the π (j) is defined as the table below: an encoder configured to encode information bits to generate parity bits based on a parity check matrix of a low density parity check, LDPC code according to a code rate of 12/15 and a code length of 64800; an interleaver comprising: a parity interleaver configured to interleave the parity bits, a group interleaver configured to split a codeword comprising the information bits and the interleaved parity bits into a plurality of bit groups and interleave the plurality of bit groups; and a block interleaver configured to interleave the interleaved plurality of bit groups using a plurality of columns to provide an interleaved codeword; and a parity interleaver configured to interleave the parity bits, a group interleaver configured to split a codeword comprising the information bits and the interleaved parity bits into a plurality of bit groups and interleave the plurality of bit groups; and a block interleaver configured to interleave the interleaved plurality of bit groups using a plurality of columns to provide an interleaved codeword; and a modulator configured to map the bits of the interleaved codeword onto modulation symbols for 256-quadrature amplitude modulation, QAM, wherein the parity check matrix comprises an information submatrix corresponding to the information bits with quasi-cyclic structure and a parity submatrix corresponding to the parity bits with a dual diagonal structure, wherein the number of the plurality of columns is 8, and wherein the group interleaver is configured to interleave the plurality of bit groups based on the following equation: Y j = X π j for 0≤j<N group for where X j is a j th bit group among the plurality of bit groups, Y j is a j th bit group among the interleaved plurality of bit groups, N group is a total number of the plurality of bit groups, and π(j) denotes a permutation order for the interleaving of the plurality of bit groups, and wherein the π (j) is defined as the table below: <EOS>