A data processing apparatus comprising: processing circuitry configured to perform a sequence of speculative vector operations on vector operands, each vector operand comprising a plurality of vector elements; speculation control circuitry configured to maintain a speculation width indication indicating the number of vector elements of each vector operand to be subjected to said speculative vector operations, the speculation width indication being initialised to an initial value prior to performance of said sequence of speculative vector operations; said processing circuitry being configured to generate progress indications during performance of said sequence of speculative vector operations; the speculation control circuitry being further configured to detect, with reference to the progress indications and speculation reduction criteria , presence of a speculation reduction condition, the speculation reduction condition being a condition indicating that a reduction in the speculation width indication is expected to improve at least one performance characteristic of the data processing apparatus relative to continued operation without the reduction in the speculation width indication; the speculation control circuitry being further responsive to detection of said speculation reduction condition to reduce the speculation width indication; wherein the speculation control circuitry is responsive to execution of a start speculation instruction to trigger a speculative mode of operation, the processing circuitry being configured to perform said speculative vector operations in response to instructions executed during said speculative mode of operation. processing circuitry configured to perform a sequence of speculative vector operations on vector operands, each vector operand comprising a plurality of vector elements; speculation control circuitry configured to maintain a speculation width indication indicating the number of vector elements of each vector operand to be subjected to said speculative vector operations, the speculation width indication being initialised to an initial value prior to performance of said sequence of speculative vector operations; said processing circuitry being configured to generate progress indications during performance of said sequence of speculative vector operations; the speculation control circuitry being further configured to detect, with reference to the progress indications and speculation reduction criteria , presence of a speculation reduction condition, the speculation reduction condition being a condition indicating that a reduction in the speculation width indication is expected to improve at least one performance characteristic of the data processing apparatus relative to continued operation without the reduction in the speculation width indication; the speculation control circuitry being further responsive to detection of said speculation reduction condition to reduce the speculation width indication; wherein the speculation control circuitry is responsive to execution of a start speculation instruction to trigger a speculative mode of operation, the processing circuitry being configured to perform said speculative vector operations in response to instructions executed during said speculative mode of operation. <EOS>