A circuit, comprising: a resistor (RCON), a normal capacitor and a ferroelectric capacitor that are connected in series; an input terminal to provide an input voltage across the circuit; and an output terminal to deliver an output voltage taken across the normal capacitor , wherein the circuit is an integrated circuit formed on a substrate , the circuit comprises: a ferroelectric layer sandwiched between a first buffer layer and a second buffer layer , wherein the first buffer layer contacts a portion of a surface of a first metal layer and the first metal layer extends beyond the first buffer layer, wherein the first metal layer is arranged on the substrate ; and a dielectric layer sandwiched between a second metal layer and a third metal layer , such that the second metal layer extends beyond the dielectric layer and in contact with the second buffer layer , wherein the ferroelectric capacitor is formed by the first metal layer, the ferroelectric layer sandwiched between the first buffer layer and the second buffer layer , and the second metal layer , and wherein the normal capacitor is formed by the dielectric layer and the third metal layer ; wherein the first metal layer and the third metal layer serve as the input terminal, and the second metal layer and the third metal layer serve as the output terminal. a resistor (RCON), a normal capacitor and a ferroelectric capacitor that are connected in series; an input terminal to provide an input voltage across the circuit; and an output terminal to deliver an output voltage taken across the normal capacitor , wherein the circuit is an integrated circuit formed on a substrate , the circuit comprises: a ferroelectric layer sandwiched between a first buffer layer and a second buffer layer , wherein the first buffer layer contacts a portion of a surface of a first metal layer and the first metal layer extends beyond the first buffer layer, wherein the first metal layer is arranged on the substrate ; and a dielectric layer sandwiched between a second metal layer and a third metal layer , such that the second metal layer extends beyond the dielectric layer and in contact with the second buffer layer , wherein the ferroelectric capacitor is formed by the first metal layer, the ferroelectric layer sandwiched between the first buffer layer and the second buffer layer , and the second metal layer , and wherein the normal capacitor is formed by the dielectric layer and the third metal layer ; wherein the first metal layer and the third metal layer serve as the input terminal, and the second metal layer and the third metal layer serve as the output terminal. a ferroelectric layer sandwiched between a first buffer layer and a second buffer layer , wherein the first buffer layer contacts a portion of a surface of a first metal layer and the first metal layer extends beyond the first buffer layer, wherein the first metal layer is arranged on the substrate ; and a dielectric layer sandwiched between a second metal layer and a third metal layer , such that the second metal layer extends beyond the dielectric layer and in contact with the second buffer layer , wherein the ferroelectric capacitor is formed by the first metal layer, the ferroelectric layer sandwiched between the first buffer layer and the second buffer layer , and the second metal layer , and wherein the normal capacitor is formed by the dielectric layer and the third metal layer ; wherein the first metal layer and the third metal layer serve as the input terminal, and the second metal layer and the third metal layer serve as the output terminal. <EOS>