An asynchronous data capture device, comprising: an edge spread detector circuit configured to: use a first clock frequency, wherein the first clock frequency is a multiple of a second clock frequency; identify transitions in a data stream transmitted to the data capture device at the second clock frequency; determine a sampling point based on the identified transitions in the data stream; a clock generator coupled to the edge spread detector circuit and configured to: adjust a phase offset based on the sampling point, and generate a clock signal having the second clock frequency and the adjusted phase offset; and a data sampling circuit coupled to the clock generator and configured to: use the second clock frequency, and sample the data stream at the sampling point; wherein the edge spread detector circuit comprises: an edge detector sub-circuit configured to receive the data stream and identify transitions in the data stream; and a shift register coupled to the edge detector sub-circuit; wherein the edge detector sub-circuit comprises: a first flip flop having an input configured to receive the data stream; a second flip flop coupled to the first flip flop ; a first logic gate coupled to the first and the second flip flops ; and a second logic gate coupled to the first logic gate and to an output of the shift register . an edge spread detector circuit configured to: use a first clock frequency, wherein the first clock frequency is a multiple of a second clock frequency; identify transitions in a data stream transmitted to the data capture device at the second clock frequency; determine a sampling point based on the identified transitions in the data stream; use a first clock frequency, wherein the first clock frequency is a multiple of a second clock frequency; identify transitions in a data stream transmitted to the data capture device at the second clock frequency; determine a sampling point based on the identified transitions in the data stream; a clock generator coupled to the edge spread detector circuit and configured to: adjust a phase offset based on the sampling point, and generate a clock signal having the second clock frequency and the adjusted phase offset; and a data sampling circuit coupled to the clock generator and configured to: use the second clock frequency, and sample the data stream at the sampling point; adjust a phase offset based on the sampling point, and generate a clock signal having the second clock frequency and the adjusted phase offset; and a data sampling circuit coupled to the clock generator and configured to: use the second clock frequency, and sample the data stream at the sampling point; use the second clock frequency, and sample the data stream at the sampling point; wherein the edge spread detector circuit comprises: an edge detector sub-circuit configured to receive the data stream and identify transitions in the data stream; and a shift register coupled to the edge detector sub-circuit; wherein the edge detector sub-circuit comprises: a first flip flop having an input configured to receive the data stream; a second flip flop coupled to the first flip flop ; a first logic gate coupled to the first and the second flip flops ; and a second logic gate coupled to the first logic gate and to an output of the shift register . a first flip flop having an input configured to receive the data stream; a second flip flop coupled to the first flip flop ; a first logic gate coupled to the first and the second flip flops ; and a second logic gate coupled to the first logic gate and to an output of the shift register . <EOS>