A sensing method, comprising: providing a first input and a second input of a resistive memory sensing circuit ; in a first stage operation of the resistive memory sensing circuit, connecting the first input to a resistive memory data cell and, in order to generate a first load transistor gate voltage (V G_Load_1st ) based on a reference value (Rref) of a resistive memory reference cell, connecting the second input to the resistive memory reference cell; in the first stage operation of the resistive memory sensing circuit, applying said first load transistor gate voltage (V G_Load_1st ) to a first load transistor (PL D ,); in the first stage operation, applying a first sense current through the first load transistor (PL D ) to said resistive memory data cell based on the first load transistor gate voltage (V G_Load_1st ); in the first stage operation, sensing a data value (Rdata) of the resistive memory data cell based on the first sense current; in a second stage operation of the resistive memory sensing circuit after the first stage operation, connecting the first input to the resistive memory reference cell and, in order to generate a second load transistor gate voltage (V G_Load-_2nd ) based on the data value (Rdata) of the resistive memory data cell, connecting the second input to the resistive memory data cell; in the second stage operation, applying said second load transistor gate voltage (V G_Load_2nd ) to the first load transistor (PL D ,); in the second stage operation, applying a second sense current through the first load transistor (PL D ) to the resistive memory reference cell based on the second load transistor gate voltage (V G_Load_2nd ); in the second stage operation, sensing a reference value (R Ref ) of the resistive memory reference cell based on the second sense current; and reading the data value by comparing the sensed data value with the sensed referenced value. providing a first input and a second input of a resistive memory sensing circuit ; in a first stage operation of the resistive memory sensing circuit, connecting the first input to a resistive memory data cell and, in order to generate a first load transistor gate voltage (V G_Load_1st ) based on a reference value (Rref) of a resistive memory reference cell, connecting the second input to the resistive memory reference cell; in the first stage operation of the resistive memory sensing circuit, applying said first load transistor gate voltage (V G_Load_1st ) to a first load transistor (PL D ,); in the first stage operation, applying a first sense current through the first load transistor (PL D ) to said resistive memory data cell based on the first load transistor gate voltage (V G_Load_1st ); in the first stage operation, sensing a data value (Rdata) of the resistive memory data cell based on the first sense current; in a second stage operation of the resistive memory sensing circuit after the first stage operation, connecting the first input to the resistive memory reference cell and, in order to generate a second load transistor gate voltage (V G_Load-_2nd ) based on the data value (Rdata) of the resistive memory data cell, connecting the second input to the resistive memory data cell; in the second stage operation, applying said second load transistor gate voltage (V G_Load_2nd ) to the first load transistor (PL D ,); in the second stage operation, applying a second sense current through the first load transistor (PL D ) to the resistive memory reference cell based on the second load transistor gate voltage (V G_Load_2nd ); in the second stage operation, sensing a reference value (R Ref ) of the resistive memory reference cell based on the second sense current; and reading the data value by comparing the sensed data value with the sensed referenced value. <EOS>