A three-dimensional, 3D, memory device , comprising: a substrate ; (i) a memory deck comprising a plurality of interleaved conductor layers and dielectric layers on top of the substrate ; and a memory string extending vertically through the memory deck , or (ii) a memory stack comprising a plurality of memory decks each having a plurality of interleaved conductor layers and dielectric layers over the substrate ; and a memory string having a plurality of memory sub-strings (108-1, 108-2) extending vertically through the memory stack , each memory deck having a respective memory sub-string (108-1, 108-2), and wherein according to (i) or (ii): - a bottom conductor layer of the plurality of interleaved conductor layers and dielectric layers that is a layer of conductive material closest to the substrate intersects with and contacts the memory string and serves as a bottom select gate of the memory string ; - a semiconductor plug is connected to the substrate at a lower portion of the memory string , wherein the memory string comprises a semiconductor channel along a sidewall of the memory string and extending along the memory string to contact the semiconductor plug ; wherein a top surface of the semiconductor plug is lower than a top surface of the bottom conductor layer ; wherein the semiconductor plug is a deposited poly-silicon or amorphous silicon plug. a substrate ; (i) a memory deck comprising a plurality of interleaved conductor layers and dielectric layers on top of the substrate ; and a memory string extending vertically through the memory deck , or (ii) a memory stack comprising a plurality of memory decks each having a plurality of interleaved conductor layers and dielectric layers over the substrate ; and a memory string having a plurality of memory sub-strings (108-1, 108-2) extending vertically through the memory stack , each memory deck having a respective memory sub-string (108-1, 108-2), (i) a memory deck comprising a plurality of interleaved conductor layers and dielectric layers on top of the substrate ; and a memory string extending vertically through the memory deck , or (ii) a memory stack comprising a plurality of memory decks each having a plurality of interleaved conductor layers and dielectric layers over the substrate ; and a memory string having a plurality of memory sub-strings (108-1, 108-2) extending vertically through the memory stack , each memory deck having a respective memory sub-string (108-1, 108-2), and wherein according to (i) or (ii): - a bottom conductor layer of the plurality of interleaved conductor layers and dielectric layers that is a layer of conductive material closest to the substrate intersects with and contacts the memory string and serves as a bottom select gate of the memory string ; - a semiconductor plug is connected to the substrate at a lower portion of the memory string , wherein the memory string comprises a semiconductor channel along a sidewall of the memory string and extending along the memory string to contact the semiconductor plug ; - a bottom conductor layer of the plurality of interleaved conductor layers and dielectric layers that is a layer of conductive material closest to the substrate intersects with and contacts the memory string and serves as a bottom select gate of the memory string ; - a semiconductor plug is connected to the substrate at a lower portion of the memory string , wherein the memory string comprises a semiconductor channel along a sidewall of the memory string and extending along the memory string to contact the semiconductor plug ; wherein a top surface of the semiconductor plug is lower than a top surface of the bottom conductor layer ; wherein the semiconductor plug is a deposited poly-silicon or amorphous silicon plug. <EOS>