A memory device comprising: a memory comprising banks, wherein each bank comprises a respective plurality of bit-cells; and an in-memory computation, IMC, operator configured to perform an IMC operation between first data while the first data is in the bit-cells of the memory and second data received as input to the memory device , wherein the banks share the IMC operator ; wherein the memory device is configured to: generate a first test pattern and store it in the bit-cells of the memory , and generate a second test pattern and apply it to the IMC operator , wherein the IMC operator is further configured to receive the first test pattern from the memory and perform a test operation between the first test pattern and the second test pattern, obtain a result of the test operation from the IMC operator and determine based thereon whether an operation error of the result has occurred for each of the banks, based on determining that the operation error has occurred, based on a same type of error occurring in each of the banks, determine that a defect has occurred in the IMC operator , based on determining that the operation error has occurred, based on a same type of error not occurring in each of the banks, determine that a defect has occurred in the memory , and perform a repair based on the determination that the defect has occurred in either the memory or the IMC operator . a memory comprising banks, wherein each bank comprises a respective plurality of bit-cells; and an in-memory computation, IMC, operator configured to perform an IMC operation between first data while the first data is in the bit-cells of the memory and second data received as input to the memory device , wherein the banks share the IMC operator ; wherein the memory device is configured to: generate a first test pattern and store it in the bit-cells of the memory , and generate a second test pattern and apply it to the IMC operator , wherein the IMC operator is further configured to receive the first test pattern from the memory and perform a test operation between the first test pattern and the second test pattern, obtain a result of the test operation from the IMC operator and determine based thereon whether an operation error of the result has occurred for each of the banks, based on determining that the operation error has occurred, based on a same type of error occurring in each of the banks, determine that a defect has occurred in the IMC operator , based on determining that the operation error has occurred, based on a same type of error not occurring in each of the banks, determine that a defect has occurred in the memory , and perform a repair based on the determination that the defect has occurred in either the memory or the IMC operator . generate a first test pattern and store it in the bit-cells of the memory , and generate a second test pattern and apply it to the IMC operator , wherein the IMC operator is further configured to receive the first test pattern from the memory and perform a test operation between the first test pattern and the second test pattern, obtain a result of the test operation from the IMC operator and determine based thereon whether an operation error of the result has occurred for each of the banks, based on determining that the operation error has occurred, based on a same type of error occurring in each of the banks, determine that a defect has occurred in the IMC operator , based on determining that the operation error has occurred, based on a same type of error not occurring in each of the banks, determine that a defect has occurred in the memory , and perform a repair based on the determination that the defect has occurred in either the memory or the IMC operator . <EOS>