A solar cell, comprising: a semiconductor substrate , wherein a rear surface of the semiconductor substrate includes a first texture structure , the first texture structure has a non-pyramid-shaped microstructure and includes two or more first substructures at least partially stacked on one another, and a one-dimensional size of a top surface of the outermost first substructure is less than or equal to 45 μm; and wherein a front surface of the semiconductor substrate includes a second texture structure , the second texture structure has a pyramid-shaped microstructure, the pyramid-shaped microstructure includes a top portion away from the front surface of the semiconductor substrate and a bottom portion close to the front surface of the semiconductor substrate , and in a direction away from the front surface and perpendicular to the front surface, a distance between the top portion and the bottom portion of the pyramid-shaped microstructure is less than or equal to 5 μm, wherein the top surface of the first substructure is a polygonal plane; a first passivation layer located on the second texture structure of the front surface of the semiconductor substrate ; a tunnel oxide layer located on the first texture structure of the rear surface of the semiconductor substrate ; a doped conductive layer located on a surface of the tunnel oxide layer ; and a second passivation layer located on a surface of the doped conductive layer , wherein for the two or more first substructures at least partially stacked on one another, in a direction away from the rear surface and perpendicular to the rear surface, a distance between the top surface of the outermost first substructure and the top surface of an adjacent first substructure is less than or equal to 2 μm. a semiconductor substrate , wherein a rear surface of the semiconductor substrate includes a first texture structure , the first texture structure has a non-pyramid-shaped microstructure and includes two or more first substructures at least partially stacked on one another, and a one-dimensional size of a top surface of the outermost first substructure is less than or equal to 45 μm; and wherein a front surface of the semiconductor substrate includes a second texture structure , the second texture structure has a pyramid-shaped microstructure, the pyramid-shaped microstructure includes a top portion away from the front surface of the semiconductor substrate and a bottom portion close to the front surface of the semiconductor substrate , and in a direction away from the front surface and perpendicular to the front surface, a distance between the top portion and the bottom portion of the pyramid-shaped microstructure is less than or equal to 5 μm, wherein the top surface of the first substructure is a polygonal plane; a first passivation layer located on the second texture structure of the front surface of the semiconductor substrate ; a tunnel oxide layer located on the first texture structure of the rear surface of the semiconductor substrate ; a doped conductive layer located on a surface of the tunnel oxide layer ; and a second passivation layer located on a surface of the doped conductive layer , wherein for the two or more first substructures at least partially stacked on one another, in a direction away from the rear surface and perpendicular to the rear surface, a distance between the top surface of the outermost first substructure and the top surface of an adjacent first substructure is less than or equal to 2 μm. <EOS>