A memory device, comprising: a crosspoint array of conductors, including rows and columns; and a decoder to select or deselect one of the conductors, the decoder including a driver circuit to apply a bias voltage to select or deselect the conductor; and a select device to selectively provide both high voltage bias and low voltage bias to the driver circuit to enable the driver circuit to apply the bias voltage; characterised in that the decoder further includes : a multiplexer to select between the high voltage bias and the low voltage bias, wherein the driver circuit includes a first transistor (M1) and a second transistor (M2) that together provide a driver for a local wordline or a local bitline, wherein the first transistor (M1) is configured to be driven by a local deselect signal and the second transistor (M2) is configured to be driven by a local select signal, wherein deselection will drive the local wordline or the local bitline to a midrange voltage through the first transistor (M1), and selection will drive the local wordline or the local bitline to the bias of a global wordline or a local bitline, respectively, through the second transistor (M2); and the select device includes a third transistor (M3) and a fourth transistor (M4) for global selection, wherein the third transistor (M3) is configured to be driven by a global deselect signal and the fourth transistor (M4) is configured to be driven by a global select signal, wherein deselection will drive the global wordline or the global bitline to the midrange voltage and selection will drive the global wordline or the global bitline to the output of the multiplexer, wherein the second transistor (M2) and the fourth transistor (M4) are each N-type transistors, and the first transistor (M1) and the third transistor (M3) are both P-type transistors or N-type transistors. a crosspoint array of conductors, including rows and columns; and a decoder to select or deselect one of the conductors, the decoder including a driver circuit to apply a bias voltage to select or deselect the conductor; and a select device to selectively provide both high voltage bias and low voltage bias to the driver circuit to enable the driver circuit to apply the bias voltage; a driver circuit to apply a bias voltage to select or deselect the conductor; and a select device to selectively provide both high voltage bias and low voltage bias to the driver circuit to enable the driver circuit to apply the bias voltage; characterised in that the decoder further includes : a multiplexer to select between the high voltage bias and the low voltage bias, wherein the driver circuit includes a first transistor (M1) and a second transistor (M2) that together provide a driver for a local wordline or a local bitline, wherein the first transistor (M1) is configured to be driven by a local deselect signal and the second transistor (M2) is configured to be driven by a local select signal, wherein deselection will drive the local wordline or the local bitline to a midrange voltage through the first transistor (M1), and selection will drive the local wordline or the local bitline to the bias of a global wordline or a local bitline, respectively, through the second transistor (M2); and the select device includes a third transistor (M3) and a fourth transistor (M4) for global selection, wherein the third transistor (M3) is configured to be driven by a global deselect signal and the fourth transistor (M4) is configured to be driven by a global select signal, wherein deselection will drive the global wordline or the global bitline to the midrange voltage and selection will drive the global wordline or the global bitline to the output of the multiplexer, wherein the second transistor (M2) and the fourth transistor (M4) are each N-type transistors, and the first transistor (M1) and the third transistor (M3) are both P-type transistors or N-type transistors. <EOS>