A memory storage device comprising: a memory controller ; and a status indicating circuit , wherein the memory controller is configured to perform a first and a second initialization operation in response to turning-on of the memory storage device , to generate a first status parameter regarding a status of the memory storage device in which the first initialization operation has been performed, and to generate a second status parameter regarding the status of the memory storage device in which the second initialization operation has been performed, the status indicating circuit includes, a first transistor (TR1) which is configured to operate on the basis of the first status parameter, a first resistor (R1) connected to the first transistor (TR1), a second transistor (TR2) which is configured to operate on the basis of the second status parameter, and a second resistor (R2) connected to the second transistor (TR2), wherein a gate of the first transistor (TR1)receives the first status parameter, a first source/drain of the first transistor (TR1) is connected to a terminal voltage (Vterm), a second source/drain of the first transistor (TR1) is connected to one end of the first resistor (R1), and the other end of the first resistor (R1) is connected to a node (ND), and wherein a gate of the second transistor (TR2)receives the second status parameter, a first source/drain of the second transistor (TR2) is connected to the terminal voltage (Vterm), a second source/drain of the second transistor (TR2) is connected to one end of the second resistor (R2), and the other end of the second resistor (R2) is connected to the node (ND). a memory controller ; and a status indicating circuit , wherein the memory controller is configured to perform a first and a second initialization operation in response to turning-on of the memory storage device , to generate a first status parameter regarding a status of the memory storage device in which the first initialization operation has been performed, and to generate a second status parameter regarding the status of the memory storage device in which the second initialization operation has been performed, the status indicating circuit includes, a first transistor (TR1) which is configured to operate on the basis of the first status parameter, a first resistor (R1) connected to the first transistor (TR1), a second transistor (TR2) which is configured to operate on the basis of the second status parameter, and a second resistor (R2) connected to the second transistor (TR2), wherein a gate of the first transistor (TR1)receives the first status parameter, a first source/drain of the first transistor (TR1) is connected to a terminal voltage (Vterm), a second source/drain of the first transistor (TR1) is connected to one end of the first resistor (R1), and the other end of the first resistor (R1) is connected to a node (ND), and wherein a gate of the second transistor (TR2)receives the second status parameter, a first source/drain of the second transistor (TR2) is connected to the terminal voltage (Vterm), a second source/drain of the second transistor (TR2) is connected to one end of the second resistor (R2), and the other end of the second resistor (R2) is connected to the node (ND). <EOS>