A processor comprising: a two-dimensional shift register array , wherein each array location of the shift register array has a first shift register (R0) and a second shift register (R1) and the two-dimensional shift register array is configured to wrap data from an edge of the shift register array to an opposite edge of the shift register array; and a two-dimensional array of processing elements , wherein each processing element of the array of processing elements can select between content in the first and second shift registers at the same array location as the processing element, wherein the processor is configured to execute instructions to perform an accumulation operation that sums all values stored in a row or a column of the two-dimensional shift register array, wherein the instructions cause the processor to repeatedly perform multiple iterations from 0 to M on values (A0-A7) stored in respective first and second shift registers of each array location in the row or in the column of data in the shift register array, each iteration N including operations comprising: simultaneously shifting data in the second shift registers of the shift register array in a particular direction along the rows or the columns by a shift amount of 2 N that doubles relative to a previous iteration, simultaneously summing the contents of the first and second shift registers in each array location to generate a resultant; and writing the resultant to the first and second shift registers in each array location to produce an accumulated partial sum; until all data in the row or the column has been added to the accumulated partial sum. a two-dimensional shift register array , wherein each array location of the shift register array has a first shift register (R0) and a second shift register (R1) and the two-dimensional shift register array is configured to wrap data from an edge of the shift register array to an opposite edge of the shift register array; and a two-dimensional array of processing elements , wherein each processing element of the array of processing elements can select between content in the first and second shift registers at the same array location as the processing element, wherein the processor is configured to execute instructions to perform an accumulation operation that sums all values stored in a row or a column of the two-dimensional shift register array, wherein the instructions cause the processor to repeatedly perform multiple iterations from 0 to M on values (A0-A7) stored in respective first and second shift registers of each array location in the row or in the column of data in the shift register array, each iteration N including operations comprising: simultaneously shifting data in the second shift registers of the shift register array in a particular direction along the rows or the columns by a shift amount of 2 N that doubles relative to a previous iteration, simultaneously summing the contents of the first and second shift registers in each array location to generate a resultant; and writing the resultant to the first and second shift registers in each array location to produce an accumulated partial sum; simultaneously shifting data in the second shift registers of the shift register array in a particular direction along the rows or the columns by a shift amount of 2 N that doubles relative to a previous iteration, simultaneously summing the contents of the first and second shift registers in each array location to generate a resultant; and writing the resultant to the first and second shift registers in each array location to produce an accumulated partial sum; until all data in the row or the column has been added to the accumulated partial sum. <EOS>