A display device , comprising: a substrate; a plurality of first sub-pixels (SP1) disposed on the substrate in first columns and a plurality of second sub-pixels (SP2) disposed on the substrate in second columns, wherein the first and second columns are arranged alternately with one another on the substrate such that each of the second columns of second sub-pixels (SP2) is disposed adjacent to a first column of first sub-pixels (SP1); a plurality of data lines (DL) comprising a plurality of first data lines (DL1) electrically connected to the first sub-pixels (SP1), and a plurality of second data lines (DL2) electrically connected to the second sub-pixels (SP2); wherein the first data lines (DL1) are each disposed on a right side of a respective first column of the plurality of first sub-pixels (SP1) and the second data lines (DL2) are each disposed on the left side of a respective second column of the plurality of second sub-pixels (SP2); a plurality of parking voltage lines (PKL) each disposed between the left side of a respective first column of the plurality of first sub-pixels (SP1) and the right side of a respective second column of the plurality of second sub-pixels (SP2); a plurality of connection transistors (Ten) each configured to electrically connect a respective parking voltage line of the plurality of parking voltage lines (PKL) to a respective first data line of the plurality of first data lines (DL1); and an enable line (ENL) electrically connected to gate electrodes of the connection transistors (Ten); wherein the second data lines (DL2) are insulated from the plurality of parking voltage lines (PKL), and wherein the plurality of first sub-pixels (SP1) includes a plurality of green sub-pixels (SPG) and the plurality of second sub-pixels (SP2) includes a plurality of red subpixels (SPR) and a plurality of blue sub-pixels (SPB). a substrate; a plurality of first sub-pixels (SP1) disposed on the substrate in first columns and a plurality of second sub-pixels (SP2) disposed on the substrate in second columns, wherein the first and second columns are arranged alternately with one another on the substrate such that each of the second columns of second sub-pixels (SP2) is disposed adjacent to a first column of first sub-pixels (SP1); a plurality of data lines (DL) comprising a plurality of first data lines (DL1) electrically connected to the first sub-pixels (SP1), and a plurality of second data lines (DL2) electrically connected to the second sub-pixels (SP2); wherein the first data lines (DL1) are each disposed on a right side of a respective first column of the plurality of first sub-pixels (SP1) and the second data lines (DL2) are each disposed on the left side of a respective second column of the plurality of second sub-pixels (SP2); a plurality of parking voltage lines (PKL) each disposed between the left side of a respective first column of the plurality of first sub-pixels (SP1) and the right side of a respective second column of the plurality of second sub-pixels (SP2); a plurality of connection transistors (Ten) each configured to electrically connect a respective parking voltage line of the plurality of parking voltage lines (PKL) to a respective first data line of the plurality of first data lines (DL1); and an enable line (ENL) electrically connected to gate electrodes of the connection transistors (Ten); wherein the second data lines (DL2) are insulated from the plurality of parking voltage lines (PKL), and wherein the plurality of first sub-pixels (SP1) includes a plurality of green sub-pixels (SPG) and the plurality of second sub-pixels (SP2) includes a plurality of red subpixels (SPR) and a plurality of blue sub-pixels (SPB). <EOS>