A method for scheduling a neural network , the method comprising: using one or more computing processors : receiving a model defining a sequential order, in a pipeline , of a plurality of functions defined in and performed when executing at least one layer (Layer 1-7) in the neural network , wherein the model represents the neural network comprising a plurality of layers; generating a systolic array including interconnected processing elements, PEs, (PE 00, 01, 01, 03), generating the systolic array being based on the model and by connecting identical processes in the at least one layer of the neural network , wherein the processes relate to operations that are performed by the PEs, the systolic array being for executing the identical processes for executing the plurality of functions, the interconnected processing elements of the systolic array being for executing concurrently; and compiling source code corresponding to the model and the systolic array into a hardware level design that provides a static schedule when executing the neural network in a hardware system , wherein compiling the source code of the systolic array comprises: converting the source code corresponding to the systolic array into a two- dimensional array of interconnected processing elements using register transfer level code for configuring programmable logic; identifying a plurality of operations performed by each of the interconnected processing elements, wherein each of the interconnected processing elements perform the same plurality of operations; and assigning the plurality of operations to different hardware elements in the hardware system such that the plurality of operations are able to perform concurrently. receiving a model defining a sequential order, in a pipeline , of a plurality of functions defined in and performed when executing at least one layer (Layer 1-7) in the neural network , wherein the model represents the neural network comprising a plurality of layers; generating a systolic array including interconnected processing elements, PEs, (PE 00, 01, 01, 03), generating the systolic array being based on the model and by connecting identical processes in the at least one layer of the neural network , wherein the processes relate to operations that are performed by the PEs, the systolic array being for executing the identical processes for executing the plurality of functions, the interconnected processing elements of the systolic array being for executing concurrently; and compiling source code corresponding to the model and the systolic array into a hardware level design that provides a static schedule when executing the neural network in a hardware system , wherein compiling the source code of the systolic array comprises: converting the source code corresponding to the systolic array into a two- dimensional array of interconnected processing elements using register transfer level code for configuring programmable logic; identifying a plurality of operations performed by each of the interconnected processing elements, wherein each of the interconnected processing elements perform the same plurality of operations; and assigning the plurality of operations to different hardware elements in the hardware system such that the plurality of operations are able to perform concurrently. converting the source code corresponding to the systolic array into a two- dimensional array of interconnected processing elements using register transfer level code for configuring programmable logic; identifying a plurality of operations performed by each of the interconnected processing elements, wherein each of the interconnected processing elements perform the same plurality of operations; and assigning the plurality of operations to different hardware elements in the hardware system such that the plurality of operations are able to perform concurrently. <EOS>