A system comprising: a memory device configured to include a command and address, CA, interface and a DQ interface ; a command bus configured to couple with the CA interface; a data bus configured to couple with the DQ interface; a memory controller configured to couple with the command bus and the data bus, the memory controller to include: a controller logic configured to generate a first command to trigger the memory device to enter one of a first command bus training mode or a second command bus training mode to train the CA interface; and input/output, I/O, circuitry configured to: cause a CA pattern to be output via the command bus; receive a sampled CA pattern from the memory device via the data bus, compress the sampled CA pattern to generate a first compressed value, if the memory device is in the first command bus training mode, and forward the first compressed value to the controller logic; and forward a second compressed value received from the memory device via the data bus, the second compressed value to represent the sampled CA pattern compressed at the memory device, if the memory device is in the second command bus training mode. a memory device configured to include a command and address, CA, interface and a DQ interface ; a command bus configured to couple with the CA interface; a data bus configured to couple with the DQ interface; a memory controller configured to couple with the command bus and the data bus, the memory controller to include: a controller logic configured to generate a first command to trigger the memory device to enter one of a first command bus training mode or a second command bus training mode to train the CA interface; and input/output, I/O, circuitry configured to: cause a CA pattern to be output via the command bus; receive a sampled CA pattern from the memory device via the data bus, compress the sampled CA pattern to generate a first compressed value, if the memory device is in the first command bus training mode, and forward the first compressed value to the controller logic; and forward a second compressed value received from the memory device via the data bus, the second compressed value to represent the sampled CA pattern compressed at the memory device, if the memory device is in the second command bus training mode. a controller logic configured to generate a first command to trigger the memory device to enter one of a first command bus training mode or a second command bus training mode to train the CA interface; and input/output, I/O, circuitry configured to: cause a CA pattern to be output via the command bus; receive a sampled CA pattern from the memory device via the data bus, compress the sampled CA pattern to generate a first compressed value, if the memory device is in the first command bus training mode, and forward the first compressed value to the controller logic; and forward a second compressed value received from the memory device via the data bus, the second compressed value to represent the sampled CA pattern compressed at the memory device, if the memory device is in the second command bus training mode. cause a CA pattern to be output via the command bus; receive a sampled CA pattern from the memory device via the data bus, compress the sampled CA pattern to generate a first compressed value, if the memory device is in the first command bus training mode, and forward the first compressed value to the controller logic; and forward a second compressed value received from the memory device via the data bus, the second compressed value to represent the sampled CA pattern compressed at the memory device, if the memory device is in the second command bus training mode. <EOS>