An All-Digital-Phase-Locked-Loop , ADPLL, comprising a Digitally Controlled Oscillator , DCO, arranged for generating a DCO output signal from a Frequency Code Word, FCW, and a feedback loop comprising a set of components for controlling the DCO , the ADPLL being arranged to receive a reference frequency signal (FREF), the components comprising: a Time-to-Digital Converter , TDC, provided for performing phase detection within a predetermined observation window, the TDC being arranged for receiving at least a delayed reference signal (FREF dly ) having a first offset delay and an enable signal (CKVD2 S ) having a second offset delay and defining the predetermined observation window, the TDC being arranged for generating a TDC output code (TDC out ) indicative of the phase difference between the delayed reference signal (FREFdly) and the enable signal (CKVD2 S ) measured within the predetermined observation window; and a subset of components arranged for generating the enable signal (CKVDS2s) from the DCO output signal, such that the enable signal (CKVDS2s) contains a transition edge derived from the DCO output signal and is arranged for activating the TDC so as to measure the phase difference between the delayed reference signal (FREFdly) and the enable signal (CKVDS2s) within the predetermined observation window; characterised in that the set of components of the feedback loop comprises an offset calibration system , connected to the TDC output (TDCout), which when activated is arranged for evaluating the difference between the first and second offset delay values by monitoring the TDC output code (TDCout) generated over a predetermined period of time and for adjusting said difference to position the predetermined observation window with respect to the delayed reference signal (FREFdly). a Time-to-Digital Converter , TDC, provided for performing phase detection within a predetermined observation window, the TDC being arranged for receiving at least a delayed reference signal (FREF dly ) having a first offset delay and an enable signal (CKVD2 S ) having a second offset delay and defining the predetermined observation window, the TDC being arranged for generating a TDC output code (TDC out ) indicative of the phase difference between the delayed reference signal (FREFdly) and the enable signal (CKVD2 S ) measured within the predetermined observation window; and a subset of components arranged for generating the enable signal (CKVDS2s) from the DCO output signal, such that the enable signal (CKVDS2s) contains a transition edge derived from the DCO output signal and is arranged for activating the TDC so as to measure the phase difference between the delayed reference signal (FREFdly) and the enable signal (CKVDS2s) within the predetermined observation window; characterised in that the set of components of the feedback loop comprises an offset calibration system , connected to the TDC output (TDCout), which when activated is arranged for evaluating the difference between the first and second offset delay values by monitoring the TDC output code (TDCout) generated over a predetermined period of time and for adjusting said difference to position the predetermined observation window with respect to the delayed reference signal (FREFdly). <EOS>