A method of forming a gate-all-around semiconductor device, the method comprising: forming a stack of alternating epitaxial silicon-germanium layers and epitaxial silicon layers on a bulk crystalline silicon substrate ; forming a plurality of fin structures from said stack, the plurality of fin structures being adjacent to each other and separated by a trench ; forming a sacrificial gate electrode over the plurality of fin structures, defining on opposing sides of the sacrificial gate electrode a pair of source/drain regions for each of the plurality of fin structures; forming dielectric spacers directly adjacent to both sidewalls of the sacrificial gate electrode and over and orthogonally to the plurality of fin structures; removing the portions of the fin structures on the pair of source/drain regions for each of the plurality of fin structures, to expose the source/drain regions ; forming epitaxial silicon source/drain structures in the pair of source/drain regions for each of the plurality of fin structures, the epitaxial silicon source/drain structures being adjacent to the dielectric spacers; removing the sacrificial gate electrode from between the dielectric spacers to expose a portion of each of the plurality of fin structures between the dielectric spacers; removing the epitaxial silicon-germanium layers from each of the portions of the plurality of fin structures between the dielectric spacers to form epitaxial silicon nanowires in each of the portions of the plurality of fin structures between the dielectric spacers; forming a high-k gate dielectric layer around each of the epitaxial silicon nanowires; and forming a metal gate electrode around the high-k gate dielectric layers, around each of the epitaxial silicon nanowires and filling the gaps between the epitaxial silicon nanowires. forming a stack of alternating epitaxial silicon-germanium layers and epitaxial silicon layers on a bulk crystalline silicon substrate ; forming a plurality of fin structures from said stack, the plurality of fin structures being adjacent to each other and separated by a trench ; forming a sacrificial gate electrode over the plurality of fin structures, defining on opposing sides of the sacrificial gate electrode a pair of source/drain regions for each of the plurality of fin structures; forming dielectric spacers directly adjacent to both sidewalls of the sacrificial gate electrode and over and orthogonally to the plurality of fin structures; removing the portions of the fin structures on the pair of source/drain regions for each of the plurality of fin structures, to expose the source/drain regions ; forming epitaxial silicon source/drain structures in the pair of source/drain regions for each of the plurality of fin structures, the epitaxial silicon source/drain structures being adjacent to the dielectric spacers; removing the sacrificial gate electrode from between the dielectric spacers to expose a portion of each of the plurality of fin structures between the dielectric spacers; removing the epitaxial silicon-germanium layers from each of the portions of the plurality of fin structures between the dielectric spacers to form epitaxial silicon nanowires in each of the portions of the plurality of fin structures between the dielectric spacers; forming a high-k gate dielectric layer around each of the epitaxial silicon nanowires; and forming a metal gate electrode around the high-k gate dielectric layers, around each of the epitaxial silicon nanowires and filling the gaps between the epitaxial silicon nanowires. <EOS>