An inter-chip timing synchronization method comprising: for each pair of chips of a plurality of chips of a semiconductor device, said plurality of chips having at least three chips: (i) determining a first one-way latency for transmissions from a first chip in the pair to a second chip in the pair of chips, and (ii) determining a second one-way latency for transmissions from the second chip in the pair to the first chip in the pair of chips; (iii) receiving, at a semiconductor device driver, the first one-way latency and the second one-way latency for each pair of chips; (iv) determining , by the semiconductor device driver and from the respective first one-way latency and the respective second one-way latency for each pair of chips, a loop latency between chips in each pair of chips by summing the respective first one-way latency and the respective second one-way latency; (v) determining , by the semiconductor device driver, whether each loop latency is less than or equal to a characteristic inter-chip latency of the semiconductor device, the characteristic inter-chip latency representing the longest time that it would take for data to be transferred from one chip of the plurality of chips to an adjacent chip of said plurality of chips; (vi) in response to each loop latency being less than or equal to the characteristic inter-chip latency of the semiconductor device, adjusting , by the semiconductor device driver and for at least one pair of chips, a local counter of the second chip in the at least one pair of chips based on the characteristic inter-chip latency of the semiconductor device and the first one-way latency of the at least one pair of chips; and (vii) in response to at least one determined loop latency being more than the characteristic inter-chip latency, repeating operations i) to iv) or generating an error signal by the semiconductor device driver. (i) determining a first one-way latency for transmissions from a first chip in the pair to a second chip in the pair of chips, and (ii) determining a second one-way latency for transmissions from the second chip in the pair to the first chip in the pair of chips; (iii) receiving, at a semiconductor device driver, the first one-way latency and the second one-way latency for each pair of chips; (iv) determining , by the semiconductor device driver and from the respective first one-way latency and the respective second one-way latency for each pair of chips, a loop latency between chips in each pair of chips by summing the respective first one-way latency and the respective second one-way latency; (v) determining , by the semiconductor device driver, whether each loop latency is less than or equal to a characteristic inter-chip latency of the semiconductor device, the characteristic inter-chip latency representing the longest time that it would take for data to be transferred from one chip of the plurality of chips to an adjacent chip of said plurality of chips; (vi) in response to each loop latency being less than or equal to the characteristic inter-chip latency of the semiconductor device, adjusting , by the semiconductor device driver and for at least one pair of chips, a local counter of the second chip in the at least one pair of chips based on the characteristic inter-chip latency of the semiconductor device and the first one-way latency of the at least one pair of chips; and (vii) in response to at least one determined loop latency being more than the characteristic inter-chip latency, repeating operations i) to iv) or generating an error signal by the semiconductor device driver. <EOS>