A method for preparing a thin-film transistor (TFT), the TFT comprising a source electrode , a drain electrode , a semiconductor layer , a gate electrode , a gate insulating layer and a source conductive layer and a drain conductive layer disposed on an upper surface of the semiconductor layer and spaced from each other, the source conductive layer connected with the source electrode , the drain conductive layer connected with the drain electrode , a minimum distance between the source conductive layer and the drain conductive layer being less than a minimum distance between the source electrode and the drain electrode , the method comprising: forming a pattern of the semiconductor layer by a first patterning process; forming patterns of the gate insulating layer disposed on the semiconductor layer and the gate electrode disposed on the gate insulating layer by a second patterning process; forming patterns of the source conductive layer and the drain conductive layer ; forming a protection layer covering the semiconductor layer , the source conductive layer , the drain conductive layer , the gate electrode and the gate insulating layer , and forming through holes in the protection layer by a third patterning process; and forming patterns of the source electrode and the drain electrode by a fourth patterning process, in which the source electrode and the drain electrode are respectively connected with the source conductive layer and the drain conductive layer via the through holes in the protection layer ; wherein a portion on the upper surface of the semiconductor layer , not covered by the gate insulating layer , is divided into a source region and a drain region, which are independent of each other, by the gate insulating layer ; and the source region and the drain region are respectively covered by the source conductive layer and the drain conductive layer ; wherein the semiconductor layer is a metal oxide semiconductor layer; characterized in that forming of the source conductive layer and the drain conductive layer in the source region and the drain region on the upper surface of the semiconductor layer respectively is conducted by a chemical plating process, and a metal layer is simultaneously formed on the gate electrode by the chemical plating process. forming a pattern of the semiconductor layer by a first patterning process; forming patterns of the gate insulating layer disposed on the semiconductor layer and the gate electrode disposed on the gate insulating layer by a second patterning process; forming patterns of the source conductive layer and the drain conductive layer ; forming a protection layer covering the semiconductor layer , the source conductive layer , the drain conductive layer , the gate electrode and the gate insulating layer , and forming through holes in the protection layer by a third patterning process; and forming patterns of the source electrode and the drain electrode by a fourth patterning process, in which the source electrode and the drain electrode are respectively connected with the source conductive layer and the drain conductive layer via the through holes in the protection layer ; wherein a portion on the upper surface of the semiconductor layer , not covered by the gate insulating layer , is divided into a source region and a drain region, which are independent of each other, by the gate insulating layer ; and the source region and the drain region are respectively covered by the source conductive layer and the drain conductive layer ; wherein the semiconductor layer is a metal oxide semiconductor layer; characterized in that forming of the source conductive layer and the drain conductive layer in the source region and the drain region on the upper surface of the semiconductor layer respectively is conducted by a chemical plating process, and a metal layer is simultaneously formed on the gate electrode by the chemical plating process. <EOS>