A data synchronization unit comprising: first flip-flops having an input for receiving data (D_REG) from a first clock domain , a reset coupled to a reset signal (POR-B) of a second clock domain , and an output for providing sampled data (D_SRC), characterized in that the first flip-flops are enabled by a request enable signal (REQ _PULSE) and in that the data synchronization unit comprises: a second flip-flop having an input coupled to an inverted output of the second flip-flop , an output for providing a request signal (REQ), and a reset coupled to a reset signal (RST_B) of the first clock domain , the second flip-flop being enabled by the request enable signal (REQ_PULSE); a request signal path having an input coupled to the request signal (REQ), and an output for providing an enable signal (ENP) synchronized to the second clock domain , the request signal path being configured to synchronize and delay the request signal (REQ) by a first delay and to generate the enable signal (ENP) in accordance with the synchronized request signal; a synchronized reset signal path having an input coupled to the reset signal (RST_B) of the first clock domain , and an output for providing a synchronized reset signal (RST_B_SRC_2_DEST), the synchronized reset signal path being configured to synchronize and delay the reset signal (RST_B) of the first clock domain by a second delay, wherein the second delay is shorter than the first delay; and multiplexers having first inputs for receiving outputs of recirculation multiplexers , second inputs for receiving a reset value (RST_VAL) of a programmable register, a select input for receiving the synchronized reset signal (RST_B_SRC_2_DEST), the multiplexers being configured to selectively output signals at inputs of the multiplexers to outputs of the multiplexers. a second flip-flop having an input coupled to an inverted output of the second flip-flop , an output for providing a request signal (REQ), and a reset coupled to a reset signal (RST_B) of the first clock domain , the second flip-flop being enabled by the request enable signal (REQ_PULSE); a request signal path having an input coupled to the request signal (REQ), and an output for providing an enable signal (ENP) synchronized to the second clock domain , the request signal path being configured to synchronize and delay the request signal (REQ) by a first delay and to generate the enable signal (ENP) in accordance with the synchronized request signal; a synchronized reset signal path having an input coupled to the reset signal (RST_B) of the first clock domain , and an output for providing a synchronized reset signal (RST_B_SRC_2_DEST), the synchronized reset signal path being configured to synchronize and delay the reset signal (RST_B) of the first clock domain by a second delay, wherein the second delay is shorter than the first delay; and multiplexers having first inputs for receiving outputs of recirculation multiplexers , second inputs for receiving a reset value (RST_VAL) of a programmable register, a select input for receiving the synchronized reset signal (RST_B_SRC_2_DEST), the multiplexers being configured to selectively output signals at inputs of the multiplexers to outputs of the multiplexers. <EOS>