An antenna comprising a splitter circuit and n antenna elements , wherein the splitter circuit comprises: an input terminal configured to receive a signal; n output terminals connected to the n respective antenna elements where n is an integer of 2 or more, and configured to output signals input from the input terminal; a first line having a first end connected to the input terminal; a second line having a first end connected to a second end of the first line; a third line having a first end which is connected to the second end of the first line in parallel with the second line, and configured to transmit a signal with a delay time different from a delay time in the second line; n fourth lines having first ends connected in parallel to a second end of the second line; n fifth lines having first ends connected in parallel to a second end of the third line; and n switching circuits (5m to 5p) connected to respective second ends of the n fourth lines, respective second ends of the n fifth lines, and the respective n output terminals, and configured to perform switching to connect the n output terminals to either the second ends of the fourth lines or the second ends of the fifth lines, wherein when m switching circuits are arbitrarily selected from among the n switching circuits and switched to connect with the second ends of the fourth lines where m is an integer ranging from 1 to n-1 while n-m switching circuits are switched to connect with the second ends of the fifth lines, characteristic impedances of the n fourth lines are set to a product between a characteristic impedance of the second line and the integer m denoting a number of the fourth lines connected to the output terminal, and characteristic impedances of the n fifth lines are set to a product between a characteristic impedance of the third line and the integer n-m denoting a number of the fifth lines connected to the output terminal. an input terminal configured to receive a signal; n output terminals connected to the n respective antenna elements where n is an integer of 2 or more, and configured to output signals input from the input terminal; a first line having a first end connected to the input terminal; a second line having a first end connected to a second end of the first line; a third line having a first end which is connected to the second end of the first line in parallel with the second line, and configured to transmit a signal with a delay time different from a delay time in the second line; n fourth lines having first ends connected in parallel to a second end of the second line; n fifth lines having first ends connected in parallel to a second end of the third line; and n switching circuits (5m to 5p) connected to respective second ends of the n fourth lines, respective second ends of the n fifth lines, and the respective n output terminals, and configured to perform switching to connect the n output terminals to either the second ends of the fourth lines or the second ends of the fifth lines, wherein when m switching circuits are arbitrarily selected from among the n switching circuits and switched to connect with the second ends of the fourth lines where m is an integer ranging from 1 to n-1 while n-m switching circuits are switched to connect with the second ends of the fifth lines, characteristic impedances of the n fourth lines are set to a product between a characteristic impedance of the second line and the integer m denoting a number of the fourth lines connected to the output terminal, and characteristic impedances of the n fifth lines are set to a product between a characteristic impedance of the third line and the integer n-m denoting a number of the fifth lines connected to the output terminal. <EOS>