A circuit for capacitive touch applications comprising - a charge integrator (CSA), followed by a low pass-filter (LPF), - said low pass-filter (LPF), followed by a correlated double sampler (CDS), - said correlated double sampler (CDS) comprising an input capacitor (Cin, C CDS ), followed by a sampler and holder (S/H), - said sampler and holder (S/H), followed by an analog to digital converter (ADC) - said analog to digital converter (ADC), said low pass-filter (LPF) having a cut-off frequency lower than the Nyquist frequency of the sampler and holder (S/H), said low pass filter comprising said input capacitor (Cin, C CDS ) and a serial resistor (R LPF+CDS ),wherein said low-pass filter (LPF) and said correlated double sampler (CDS) are integrated in a first single block (2, LPF+CDS), wherein said analog to digital converter (ADC) is a switched capacitor analog to digital converter, wherein said analog to digital converter (ADC) is a multistage analog to digital converter comprising a first stage and further stages, wherein said first stage comprises a successive approximation register (SAR) and a feedback digital to analog converter (DAC) and wherein an amplifier is shared between said sampler and holder (S/H) and said first stage of said analog-to-digital converter, wherein said low pass filter (LPF), said correlated double sampler (CDS), said sampler and holder (S/H) and said first stage of said analog to digital converter (ADC) are integrated in a second single block , wherein a capacitor (Cfb) is shared between said sampler and holder (S/H) integrated in said first stage of said analog-to-digital converter, and said first single block (2, LPF+CDS) integrating said low-pass filter (LPF) and said correlated double sampler (CDS). - a charge integrator (CSA), followed by a low pass-filter (LPF), - said low pass-filter (LPF), followed by a correlated double sampler (CDS), - said correlated double sampler (CDS) comprising an input capacitor (Cin, C CDS ), followed by a sampler and holder (S/H), - said sampler and holder (S/H), followed by an analog to digital converter (ADC) - said analog to digital converter (ADC), said low pass-filter (LPF) having a cut-off frequency lower than the Nyquist frequency of the sampler and holder (S/H), said low pass filter comprising said input capacitor (Cin, C CDS ) and a serial resistor (R LPF+CDS ),wherein said low-pass filter (LPF) and said correlated double sampler (CDS) are integrated in a first single block (2, LPF+CDS), wherein said analog to digital converter (ADC) is a switched capacitor analog to digital converter, wherein said analog to digital converter (ADC) is a multistage analog to digital converter comprising a first stage and further stages, wherein said first stage comprises a successive approximation register (SAR) and a feedback digital to analog converter (DAC) and wherein an amplifier is shared between said sampler and holder (S/H) and said first stage of said analog-to-digital converter, wherein said low pass filter (LPF), said correlated double sampler (CDS), said sampler and holder (S/H) and said first stage of said analog to digital converter (ADC) are integrated in a second single block , wherein a capacitor (Cfb) is shared between said sampler and holder (S/H) integrated in said first stage of said analog-to-digital converter, and said first single block (2, LPF+CDS) integrating said low-pass filter (LPF) and said correlated double sampler (CDS). <EOS>