A display panel, comprising: an array substrate (AS) and an opposing substrate (PS) facing the array substrate (AS); a data line layer comprising a plurality of data lines on the array substrate (AS); a passivation layer on a side of the data line layer proximal to the opposing substrate (PS); a sealant layer on a side of the passivation layer distal to the data line layer , sealing the array substrate (AS) and the opposing substrate (PS) together; the display panel comprising a first area (A) enclosed by the sealant layer and a second area (B) outside of the first area (A) and the sealant layer ; the plurality of data lines extending from the first area (A) into the second area (B); and a common electrode layer on a side of the sealant layer distal to the passivation layer ; wherein the common electrode layer comprises a portion having a plurality of connections (C), and a plurality of slits (S) spaced apart from each other by the plurality of connections (C); each of the plurality of slits (S) and each of the plurality of connections (C) extending from the first area (A) into the second area (B), each of the plurality of connections (C) is between two adjacent slits (S); each of the plurality of connections (C) has a first portion in the first area (A) and a second portion in the second area (B), the plurality of connections (C) are electrically connected to each other; each of the plurality of connections (C) corresponds to one of the plurality of data lines ; and a projection of each of the plurality of connections (C) on the array substrate (AS) overlaps a projection of one of the plurality of data lines in plan view of the display panel. an array substrate (AS) and an opposing substrate (PS) facing the array substrate (AS); a data line layer comprising a plurality of data lines on the array substrate (AS); a passivation layer on a side of the data line layer proximal to the opposing substrate (PS); a sealant layer on a side of the passivation layer distal to the data line layer , sealing the array substrate (AS) and the opposing substrate (PS) together; the display panel comprising a first area (A) enclosed by the sealant layer and a second area (B) outside of the first area (A) and the sealant layer ; the plurality of data lines extending from the first area (A) into the second area (B); and a common electrode layer on a side of the sealant layer distal to the passivation layer ; wherein the common electrode layer comprises a portion having a plurality of connections (C), and a plurality of slits (S) spaced apart from each other by the plurality of connections (C); each of the plurality of slits (S) and each of the plurality of connections (C) extending from the first area (A) into the second area (B), each of the plurality of connections (C) is between two adjacent slits (S); each of the plurality of connections (C) has a first portion in the first area (A) and a second portion in the second area (B), the plurality of connections (C) are electrically connected to each other; each of the plurality of connections (C) corresponds to one of the plurality of data lines ; and a projection of each of the plurality of connections (C) on the array substrate (AS) overlaps a projection of one of the plurality of data lines in plan view of the display panel. <EOS>