A method for forming a three-dimensional, 3D, memory device , comprising: forming a peripheral circuit on a first substrate; subsequently forming a sacrificial layer on a substrate , a P-type doped semiconductor layer having an N-well on the sacrificial layer , and a dielectric stack on the P-type doped semiconductor layer , wherein the dielectric stack comprises interleaved a stack of dielectric layers and a stack of sacrificial layers ; forming a channel structure extending vertically through the dielectric stack and the P-type doped semiconductor layer , wherein forming the channel structure comprises: etching a channel hole extending vertically through the dielectric stack and the P-type doped semiconductor layer , stopping at the sacrificial layer ; and subsequently depositing a memory film and a semiconductor channel along a sidewall of the channel hole; replacing the sacrificial layers of the dielectric stack to obtain a memory stack , wherein the memory stack comprises interleaved a stack dielectric layers and a stack conductive layers , such that the channel structure extends vertically through the memory stack and the P-type doped semiconductor layer ; and bonding the first substrate and the substrate in a face-to-face manner, such that the memory stack is above the peripheral circuit ; removing the substrate and the sacrificial layer to expose an end of the channel structure ; and replacing part of the channel structure abutting the P-type doped semiconductor layer with a semiconductor plug . forming a peripheral circuit on a first substrate; subsequently forming a sacrificial layer on a substrate , a P-type doped semiconductor layer having an N-well on the sacrificial layer , and a dielectric stack on the P-type doped semiconductor layer , wherein the dielectric stack comprises interleaved a stack of dielectric layers and a stack of sacrificial layers ; forming a channel structure extending vertically through the dielectric stack and the P-type doped semiconductor layer , wherein forming the channel structure comprises: etching a channel hole extending vertically through the dielectric stack and the P-type doped semiconductor layer , stopping at the sacrificial layer ; and subsequently depositing a memory film and a semiconductor channel along a sidewall of the channel hole; replacing the sacrificial layers of the dielectric stack to obtain a memory stack , wherein the memory stack comprises interleaved a stack dielectric layers and a stack conductive layers , such that the channel structure extends vertically through the memory stack and the P-type doped semiconductor layer ; and bonding the first substrate and the substrate in a face-to-face manner, such that the memory stack is above the peripheral circuit ; removing the substrate and the sacrificial layer to expose an end of the channel structure ; and replacing part of the channel structure abutting the P-type doped semiconductor layer with a semiconductor plug . etching a channel hole extending vertically through the dielectric stack and the P-type doped semiconductor layer , stopping at the sacrificial layer ; and subsequently depositing a memory film and a semiconductor channel along a sidewall of the channel hole; replacing the sacrificial layers of the dielectric stack to obtain a memory stack , wherein the memory stack comprises interleaved a stack dielectric layers and a stack conductive layers , such that the channel structure extends vertically through the memory stack and the P-type doped semiconductor layer ; and bonding the first substrate and the substrate in a face-to-face manner, such that the memory stack is above the peripheral circuit ; removing the substrate and the sacrificial layer to expose an end of the channel structure ; and replacing part of the channel structure abutting the P-type doped semiconductor layer with a semiconductor plug . <EOS>