An integrated circuit , comprising: a memory manager having a plurality of memory ports , each memory port configured to communicate with a corresponding floating memory block of a plurality of floating memory blocks configured to be allocated in different configurations to a first domain or a second domain; a first interconnect for the first domain , the first interconnect having a first set of fixed ports configured to communicate with one or more memory blocks dedicated to the first domain and a first set of floating ports configured to communicate with the memory manager ; a second interconnect for the second domain , the second interconnect having a second set of fixed ports configured to communicate with one or more memory blocks dedicated to the second domain and a second set of floating ports configured to communicate with the memory manager, wherein the memory manager is configured to allocate, based upon a mode indicator , a first portion of the plurality of memory ports to the first set of floating ports for the first domain and a second, non-overlapping, portion of the plurality of memory ports to the second set of floating ports for the second domain; each fixed port of the first set of fixed ports is configured to communicate with a memory block of the one or more memory blocks dedicated to the first domain via a corresponding memory controller , and each floating port of the first set of floating ports is configured to communicate with the memory manager via a corresponding memory controller ; and each fixed port of the second set of fixed ports is configured to communicate with a memory block of the one or more memory blocks dedicated to the second domain via a corresponding memory controller , and each floating port of the second set of floating ports is configured to communicate with the memory manager via a corresponding memory controller . a memory manager having a plurality of memory ports , each memory port configured to communicate with a corresponding floating memory block of a plurality of floating memory blocks configured to be allocated in different configurations to a first domain or a second domain; a first interconnect for the first domain , the first interconnect having a first set of fixed ports configured to communicate with one or more memory blocks dedicated to the first domain and a first set of floating ports configured to communicate with the memory manager ; a second interconnect for the second domain , the second interconnect having a second set of fixed ports configured to communicate with one or more memory blocks dedicated to the second domain and a second set of floating ports configured to communicate with the memory manager, wherein the memory manager is configured to allocate, based upon a mode indicator , a first portion of the plurality of memory ports to the first set of floating ports for the first domain and a second, non-overlapping, portion of the plurality of memory ports to the second set of floating ports for the second domain; each fixed port of the first set of fixed ports is configured to communicate with a memory block of the one or more memory blocks dedicated to the first domain via a corresponding memory controller , and each floating port of the first set of floating ports is configured to communicate with the memory manager via a corresponding memory controller ; and each fixed port of the second set of fixed ports is configured to communicate with a memory block of the one or more memory blocks dedicated to the second domain via a corresponding memory controller , and each floating port of the second set of floating ports is configured to communicate with the memory manager via a corresponding memory controller . <EOS>