An integrated circuit device, comprising: an input for receiving an initial data argument (D[31:0]) comprising a plurality of bits; circuitry for providing a first shift argument (L[4:0]) indicating a number of shift positions in a first direction, the first shift argument (L[4:0]) comprising a plurality of bits; circuitry for providing a second shift argument (R[4:0]) indicating a number of shift positions in a second direction, the second shift argument (R[4:0]) comprising a plurality of bits; a plurality of rotate stages (ROTATE STAGE 1-N), each comprising an input and an output; wherein a first rotate stage (ROTATE STAGE 1), in the plurality of rotate stages, is coupled to receive the initial data argument (D[31:0]); wherein each rotate stage, in the plurality of rotate stages, other than the first rotate stage (ROTATE STAGE 1), is coupled to receive a data argument from an output of another one of the rotate stages in the plurality of rotate stages; characterized in that the first rotate stage (ROTATE STAGE 1), in the plurality of rotate stages, is operable to rotate the data argument input into the corresponding rotate stage, in response to a least significant bit (L ) in the first shift argument (L[4:0]); a second rotate stage (ROTATE STAGE 2), in the plurality of rotate stages, is operable to rotate the data argument input into the corresponding rotate stage, in response to a least significant bit (R ) in the second shift argument (R[4:0]); and wherein each rotate stage (ROTATE STAGE 3-N), in the plurality of rotate stages, other than the first (ROTATE STAGE 1) and second (ROTATE STAGE 2) rotate stages, is operable to rotate the data argument input thereto, in response to a sum of respective bit positions (L[2:1], (L[4:3] (R[2:1]) (R[4:3])) of the first (L[4:0]) and second (R[4:0]) shift arguments. an input for receiving an initial data argument (D[31:0]) comprising a plurality of bits; circuitry for providing a first shift argument (L[4:0]) indicating a number of shift positions in a first direction, the first shift argument (L[4:0]) comprising a plurality of bits; circuitry for providing a second shift argument (R[4:0]) indicating a number of shift positions in a second direction, the second shift argument (R[4:0]) comprising a plurality of bits; a plurality of rotate stages (ROTATE STAGE 1-N), each comprising an input and an output; wherein a first rotate stage (ROTATE STAGE 1), in the plurality of rotate stages, is coupled to receive the initial data argument (D[31:0]); wherein each rotate stage, in the plurality of rotate stages, other than the first rotate stage (ROTATE STAGE 1), is coupled to receive a data argument from an output of another one of the rotate stages in the plurality of rotate stages; the first rotate stage (ROTATE STAGE 1), in the plurality of rotate stages, is operable to rotate the data argument input into the corresponding rotate stage, in response to a least significant bit (L ) in the first shift argument (L[4:0]); a second rotate stage (ROTATE STAGE 2), in the plurality of rotate stages, is operable to rotate the data argument input into the corresponding rotate stage, in response to a least significant bit (R ) in the second shift argument (R[4:0]); and wherein each rotate stage (ROTATE STAGE 3-N), in the plurality of rotate stages, other than the first (ROTATE STAGE 1) and second (ROTATE STAGE 2) rotate stages, is operable to rotate the data argument input thereto, in response to a sum of respective bit positions (L[2:1], (L[4:3] (R[2:1]) (R[4:3])) of the first (L[4:0]) and second (R[4:0]) shift arguments. <EOS>