A processing device comprising: a memory controller ; and a memory paging circuit , operatively coupled to the memory controller , to: insert a transportable page into a memory location associated with a trust domain, TD, executed by the processing device , wherein the transportable page comprises encrypted contents of a first memory page of the TD , the encrypted contents comprise at least one of a physical address of the first memory page or a virtual address of a second memory page where the encrypted contents of the transportable page are stored, and is encrypted using a key associated with the TD , wherein the TD is cryptographically isolated in memory using the key for encrypting the memory associated with the TD ; create a third memory page associated with the TD by binding the transportable page to the TD , wherein binding the transportable page to the TD comprises decrypting contents of the transportable page using the TD specific encryption key , and re-encrypting contents of the transportable page based on an ephemeral key associated with the TD and a physical address of the memory location, wherein the ephemeral key is generated for each execution of the TD; and access contents of the third memory page by decrypting the contents of the third memory page using the ephemeral key associated with the TD and the physical address of the memory location. a memory controller ; and a memory paging circuit , operatively coupled to the memory controller , to: insert a transportable page into a memory location associated with a trust domain, TD, executed by the processing device , wherein the transportable page comprises encrypted contents of a first memory page of the TD , the encrypted contents comprise at least one of a physical address of the first memory page or a virtual address of a second memory page where the encrypted contents of the transportable page are stored, and is encrypted using a key associated with the TD , wherein the TD is cryptographically isolated in memory using the key for encrypting the memory associated with the TD ; create a third memory page associated with the TD by binding the transportable page to the TD , wherein binding the transportable page to the TD comprises decrypting contents of the transportable page using the TD specific encryption key , and re-encrypting contents of the transportable page based on an ephemeral key associated with the TD and a physical address of the memory location, wherein the ephemeral key is generated for each execution of the TD; and access contents of the third memory page by decrypting the contents of the third memory page using the ephemeral key associated with the TD and the physical address of the memory location. insert a transportable page into a memory location associated with a trust domain, TD, executed by the processing device , wherein the transportable page comprises encrypted contents of a first memory page of the TD , the encrypted contents comprise at least one of a physical address of the first memory page or a virtual address of a second memory page where the encrypted contents of the transportable page are stored, and is encrypted using a key associated with the TD , wherein the TD is cryptographically isolated in memory using the key for encrypting the memory associated with the TD ; create a third memory page associated with the TD by binding the transportable page to the TD , wherein binding the transportable page to the TD comprises decrypting contents of the transportable page using the TD specific encryption key , and re-encrypting contents of the transportable page based on an ephemeral key associated with the TD and a physical address of the memory location, wherein the ephemeral key is generated for each execution of the TD; and access contents of the third memory page by decrypting the contents of the third memory page using the ephemeral key associated with the TD and the physical address of the memory location. <EOS>