A computer implemented method for designing a circuit, comprising: specifying a circuit including a first transistor , a second transistor , and an interconnect connecting a terminal of the first transistor to a terminal of the second transistor , the interconnect comprising nanowires or 2D material strips arranged in parallel, to form a machine readable specification of circuit structures; executing a process utilizing the machine readable specification of circuit structures to identify entries of a cell library specifying parameters used to simulate timing characteristics of a physical implementation of the circuit when placed with other circuits or components, wherein the entries identify a number of nanowires or 2D material strips in the set of nanowires or 2D material strips in the interconnect ; creating a machine readable specification of a cell including said parameters of the circuit; storing the machine readable specification of the cell in computer readable memory ; and running a placement process utilizing the machine readable specification of the cell to control physical placement of the circuit with other circuits or components by preparing and changing lithographic mask data affecting the number of nanowires or 2D material strips; wherein said nanowires or 2D material strips of the interconnect include a set of parallel nanowires or 2D material strips disposed in a plurality of stacks , and all of the parallel nanowires or 2D material strips in each of the plurality of stacks are disposed at planes horizontally relative to a surface of a substrate , the plurality of stacks being disposed on the substrate , wherein the 2D material strips include layers of doped or undoped materials. specifying a circuit including a first transistor , a second transistor , and an interconnect connecting a terminal of the first transistor to a terminal of the second transistor , the interconnect comprising nanowires or 2D material strips arranged in parallel, to form a machine readable specification of circuit structures; executing a process utilizing the machine readable specification of circuit structures to identify entries of a cell library specifying parameters used to simulate timing characteristics of a physical implementation of the circuit when placed with other circuits or components, wherein the entries identify a number of nanowires or 2D material strips in the set of nanowires or 2D material strips in the interconnect ; creating a machine readable specification of a cell including said parameters of the circuit; storing the machine readable specification of the cell in computer readable memory ; and running a placement process utilizing the machine readable specification of the cell to control physical placement of the circuit with other circuits or components by preparing and changing lithographic mask data affecting the number of nanowires or 2D material strips; wherein said nanowires or 2D material strips of the interconnect include a set of parallel nanowires or 2D material strips disposed in a plurality of stacks , and all of the parallel nanowires or 2D material strips in each of the plurality of stacks are disposed at planes horizontally relative to a surface of a substrate , the plurality of stacks being disposed on the substrate , wherein the 2D material strips include layers of doped or undoped materials. <EOS>