An electrical-converter system , comprising: a printed circuit board including at least a first layer and a second layer ; a switching node disposed on the second layer; a first transistor (Q1), a second transistor (Q2), a third transistor (Q3), and a fourth transistor (Q4), disposed on the first layer, the first transistor and the third transistor each having a source coupled to the switching node, and the second transistor and the fourth transistor each having a drain coupled to the switching node; a first conduction path from the source of the first transistor, through the switching node, to the drain of the fourth transistor, the first conduction path having a first inductance ; and a second conduction path from the source of the first transistor, through the switching node, to the drain of the second transistor, the second conduction path having a second inductance ; a third conduction path from the source of the third transistor, through the switching node, to the drain of the second transistor, the third conduction path having a third inductance ; a fourth conduction path from the source of the third transistor, through the switching node, to the drain of the fourth transistor, the fourth conduction path having a fourth inductance , wherein the transistors are positioned on the first layer symmetrically such that a first distance (D1) between the first and second transistors is substantially the same as a second distance (D2) between the third and fourth transistors, and a third distance (D3) between the first and third transistors is substantially the same as a fourth distance (D4) between the second and fourth transistors, wherein the first and third inductance of the first and third conduction path are substantially equal and greater than the second and fourth inductance of the second and fourth conduction path, with the second and fourth inductance being substantially equal. a printed circuit board including at least a first layer and a second layer ; a switching node disposed on the second layer; a first transistor (Q1), a second transistor (Q2), a third transistor (Q3), and a fourth transistor (Q4), disposed on the first layer, the first transistor and the third transistor each having a source coupled to the switching node, and the second transistor and the fourth transistor each having a drain coupled to the switching node; a first conduction path from the source of the first transistor, through the switching node, to the drain of the fourth transistor, the first conduction path having a first inductance ; and a second conduction path from the source of the first transistor, through the switching node, to the drain of the second transistor, the second conduction path having a second inductance ; a third conduction path from the source of the third transistor, through the switching node, to the drain of the second transistor, the third conduction path having a third inductance ; a fourth conduction path from the source of the third transistor, through the switching node, to the drain of the fourth transistor, the fourth conduction path having a fourth inductance , wherein the transistors are positioned on the first layer symmetrically such that a first distance (D1) between the first and second transistors is substantially the same as a second distance (D2) between the third and fourth transistors, and a third distance (D3) between the first and third transistors is substantially the same as a fourth distance (D4) between the second and fourth transistors, wherein the first and third inductance of the first and third conduction path are substantially equal and greater than the second and fourth inductance of the second and fourth conduction path, with the second and fourth inductance being substantially equal. <EOS>