A system comprising: at least one processor ; and memory storing instructions that, when executed by the at least one processor, causes the system to perform a set of operations, the set of operations comprising: initializing content of a memory unit; activating , using a susceptibility test sequence, a first memory row of the memory unit; evaluating the memory unit based on the content to identify one or more rows of the memory unit where bits changed; and generating , based on an evaluation of the one or more rows and the first memory row, a physical adjacency map indicating at least one row of the one or more rows is adjacent to the first memory row; accessing, for the memory unit, the physical adjacency map; determining , based on the physical adjacency map, a first set of adjacent memory rows for a first target row of the memory unit; activating , using the susceptibility test sequence, each memory row of the first set of adjacent memory rows; evaluating the first target row to determine if one or more bits of the first target row changed; and based on determining that one or more bits of the first target row did not change, generating an indication that the memory unit is not susceptible to induced charge leakage. at least one processor ; and memory storing instructions that, when executed by the at least one processor, causes the system to perform a set of operations, the set of operations comprising: initializing content of a memory unit; activating , using a susceptibility test sequence, a first memory row of the memory unit; evaluating the memory unit based on the content to identify one or more rows of the memory unit where bits changed; and generating , based on an evaluation of the one or more rows and the first memory row, a physical adjacency map indicating at least one row of the one or more rows is adjacent to the first memory row; accessing, for the memory unit, the physical adjacency map; determining , based on the physical adjacency map, a first set of adjacent memory rows for a first target row of the memory unit; activating , using the susceptibility test sequence, each memory row of the first set of adjacent memory rows; evaluating the first target row to determine if one or more bits of the first target row changed; and based on determining that one or more bits of the first target row did not change, generating an indication that the memory unit is not susceptible to induced charge leakage. initializing content of a memory unit; activating , using a susceptibility test sequence, a first memory row of the memory unit; evaluating the memory unit based on the content to identify one or more rows of the memory unit where bits changed; and generating , based on an evaluation of the one or more rows and the first memory row, a physical adjacency map indicating at least one row of the one or more rows is adjacent to the first memory row; accessing, for the memory unit, the physical adjacency map; determining , based on the physical adjacency map, a first set of adjacent memory rows for a first target row of the memory unit; activating , using the susceptibility test sequence, each memory row of the first set of adjacent memory rows; evaluating the first target row to determine if one or more bits of the first target row changed; and based on determining that one or more bits of the first target row did not change, generating an indication that the memory unit is not susceptible to induced charge leakage. <EOS>