A display device, comprising: pixels (PXL) each comprising at least one transistor (T) disposed on a substrate (SUB), a protective layer (PSV) configured to cover the transistor (T), and a light-emitting element disposed over the protective layer (PSV) and coupled to the transistor (T); scan lines (S) and data lines (D) coupled to the pixels (PXL); a power line (IL) configured to supply driving power to the light-emitting elements of the pixels (PXL), and extending in one direction; and an initialization power line (IPL) disposed over the protective layer (PSV) and configured to supply initialization power to the light-emitting elements, wherein the transistor comprises an active pattern (ACT) disposed on the substrate, a source electrode (SE) and a drain electrode (DE) coupled to the active pattern (ACT), a gate electrode (GE) disposed over the active pattern (ACT) with a gate insulating layer (GI) interposed therebetween, and an interlayer insulating layer comprising a first interlayer insulating layer (IL1) and a second interlayer insulating layer (IL2) successively stacked and configured to cover the gate electrode (GE),wherein the power line (IL) is disposed over the second interlayer insulating layer (IL2), and wherein the initialization power line (IPL) comprises a plurality of first conductive lines (CP1) and a plurality of second conductive lines (CP2) intersecting the first conductive lines (CP1), and the first conductive lines (CP1) and the second conductive lines (CP2) are spaced apart from the light-emitting elements, wherein the initialization power line (IPL) is configured to apply an initialization power supply (Vint); characterized in that the plurality of first conductive lines (CP1) extends in a direction oblique to the scan lines (S) and the data lines (D); and wherein the plurality of second conductive lines (CP2) is electrically connected to the first conductive lines (CP1) thereby forming a mesh structure. pixels (PXL) each comprising at least one transistor (T) disposed on a substrate (SUB), a protective layer (PSV) configured to cover the transistor (T), and a light-emitting element disposed over the protective layer (PSV) and coupled to the transistor (T); scan lines (S) and data lines (D) coupled to the pixels (PXL); a power line (IL) configured to supply driving power to the light-emitting elements of the pixels (PXL), and extending in one direction; and an initialization power line (IPL) disposed over the protective layer (PSV) and configured to supply initialization power to the light-emitting elements, wherein the transistor comprises an active pattern (ACT) disposed on the substrate, a source electrode (SE) and a drain electrode (DE) coupled to the active pattern (ACT), a gate electrode (GE) disposed over the active pattern (ACT) with a gate insulating layer (GI) interposed therebetween, and an interlayer insulating layer comprising a first interlayer insulating layer (IL1) and a second interlayer insulating layer (IL2) successively stacked and configured to cover the gate electrode (GE),wherein the power line (IL) is disposed over the second interlayer insulating layer (IL2), and wherein the initialization power line (IPL) comprises a plurality of first conductive lines (CP1) and a plurality of second conductive lines (CP2) intersecting the first conductive lines (CP1), and the first conductive lines (CP1) and the second conductive lines (CP2) are spaced apart from the light-emitting elements, wherein the initialization power line (IPL) is configured to apply an initialization power supply (Vint); characterized in that the plurality of first conductive lines (CP1) extends in a direction oblique to the scan lines (S) and the data lines (D); and wherein the plurality of second conductive lines (CP2) is electrically connected to the first conductive lines (CP1) thereby forming a mesh structure. <EOS>