A writing method of a filament-based resistive memory apparatus , comprising: receiving (S510) logic data (DATA), and selecting a corresponding resistive memory cell ; determining (S520) a logic level of the logic data (DATA) 1 to be written into the resistive memory apparatus ; when the logic data (DATA) is in a first logic level, where a first reading current (IR1) of the corresponding resistive memory cell is greater than a first reference current, providing (S542, S544) a set pulse (SET) and a reset pulse (RESET) to the resistive memory cell during a writing period which comprises: providing (S542) the set pulse (SET) to the resistive memory cell ; and providing (S544) the reset pulse (RESET) to the resistive memory cell after providing the set pulse (SET) to the resistive memory cell if the first reading current (IR1) is smaller than the first reference current (S546), wherein polarities of the reset pulse (RESET) and the set pulse (SET) are opposite, and when the logic data (DATA) is in a second logic level, where a second reading current (IR2) of the resistive memory cell is smaller than a second reference current, providing (S532) the reset pulse (RESET) to the resistive memory cell during the writing period, wherein the first reference current and the second reference current are different, wherein the set pulse (SET) decreases an electrical resistance of the resistive memory cell and the reset pulse (RESET) increases the electrical resistance of the resistive memory cell . receiving (S510) logic data (DATA), and selecting a corresponding resistive memory cell ; determining (S520) a logic level of the logic data (DATA) 1 to be written into the resistive memory apparatus ; when the logic data (DATA) is in a first logic level, where a first reading current (IR1) of the corresponding resistive memory cell is greater than a first reference current, providing (S542, S544) a set pulse (SET) and a reset pulse (RESET) to the resistive memory cell during a writing period which comprises: providing (S542) the set pulse (SET) to the resistive memory cell ; and providing (S544) the reset pulse (RESET) to the resistive memory cell after providing the set pulse (SET) to the resistive memory cell if the first reading current (IR1) is smaller than the first reference current (S546), wherein polarities of the reset pulse (RESET) and the set pulse (SET) are opposite, and providing (S542) the set pulse (SET) to the resistive memory cell ; and providing (S544) the reset pulse (RESET) to the resistive memory cell after providing the set pulse (SET) to the resistive memory cell if the first reading current (IR1) is smaller than the first reference current (S546), wherein polarities of the reset pulse (RESET) and the set pulse (SET) are opposite, and when the logic data (DATA) is in a second logic level, where a second reading current (IR2) of the resistive memory cell is smaller than a second reference current, providing (S532) the reset pulse (RESET) to the resistive memory cell during the writing period, wherein the first reference current and the second reference current are different, wherein the set pulse (SET) decreases an electrical resistance of the resistive memory cell and the reset pulse (RESET) increases the electrical resistance of the resistive memory cell . <EOS>