A semiconductor device comprising: a ceramic substrate (CS1) having a first surface (CSt), and a second surface (CSb) located on an opposite side of the first surface (CSt); a plurality of metal patterns (MP) each having a third surface (MPb) facing and contacting the first surface (CSt) of the ceramic substrate (CS1), and a fourth surface (MPm) located on an opposite side of the third surface (MPb); and a plurality of semiconductor chips (CP) mounted on one or some of the plurality of metal patterns (MP) through a solder (SD), wherein the plurality of metal patterns (MP) includes: a first metal pattern (MPU/MPV/MPW) which has a first side (MUs1/MVs1/MWs1) and on which a first semiconductor chip (CTL) among the plurality of semiconductor chips (CP) is mounted; and a second metal pattern (MPL/MPT) which has a second side (MLs2) facing the first side (MUs1/MVs1/MWs1) of the first metal pattern (MPU/MPV/MPW) and which is separated from the first metal pattern (MPU/MPV/MPW), a first electrode (PDE/PDG) of the first semiconductor chip (CTL) and the second metal pattern (MPL/MPT) are electrically connected to each other through a first conductive member (BWL/BWG) extending so as to intersect with the first side (MUs1/MVs1/MWs1) and the second side (MLs2), and a plurality of hollow portions (DP) which are recessed in a direction from the fourth surface (MPm) to the third surface (MPb) is formed in peripheral portions of the fourth surfaces (MPm) of the plurality of metal patterns (MP), but is not provided in both a region overlapping with the plurality of semiconductor chips (CP) and a region between the first semiconductor chip (CTL) and the first side (MUs1/MVs1/MWs1) of the first metal pattern (MPU/MPV/MPW) in plan view. a ceramic substrate (CS1) having a first surface (CSt), and a second surface (CSb) located on an opposite side of the first surface (CSt); a plurality of metal patterns (MP) each having a third surface (MPb) facing and contacting the first surface (CSt) of the ceramic substrate (CS1), and a fourth surface (MPm) located on an opposite side of the third surface (MPb); and a plurality of semiconductor chips (CP) mounted on one or some of the plurality of metal patterns (MP) through a solder (SD), wherein the plurality of metal patterns (MP) includes: a first metal pattern (MPU/MPV/MPW) which has a first side (MUs1/MVs1/MWs1) and on which a first semiconductor chip (CTL) among the plurality of semiconductor chips (CP) is mounted; and a second metal pattern (MPL/MPT) which has a second side (MLs2) facing the first side (MUs1/MVs1/MWs1) of the first metal pattern (MPU/MPV/MPW) and which is separated from the first metal pattern (MPU/MPV/MPW), a first metal pattern (MPU/MPV/MPW) which has a first side (MUs1/MVs1/MWs1) and on which a first semiconductor chip (CTL) among the plurality of semiconductor chips (CP) is mounted; and a second metal pattern (MPL/MPT) which has a second side (MLs2) facing the first side (MUs1/MVs1/MWs1) of the first metal pattern (MPU/MPV/MPW) and which is separated from the first metal pattern (MPU/MPV/MPW), a first electrode (PDE/PDG) of the first semiconductor chip (CTL) and the second metal pattern (MPL/MPT) are electrically connected to each other through a first conductive member (BWL/BWG) extending so as to intersect with the first side (MUs1/MVs1/MWs1) and the second side (MLs2), and a plurality of hollow portions (DP) which are recessed in a direction from the fourth surface (MPm) to the third surface (MPb) is formed in peripheral portions of the fourth surfaces (MPm) of the plurality of metal patterns (MP), but is not provided in both a region overlapping with the plurality of semiconductor chips (CP) and a region between the first semiconductor chip (CTL) and the first side (MUs1/MVs1/MWs1) of the first metal pattern (MPU/MPV/MPW) in plan view. <EOS>