A processor comprising: a storage to store a source vector having a first portion with a first plurality of packed data fields, wherein each of the first plurality of packed data fields has a second plurality of bits comprising four or more bits; a destination register, comprising a first portion that corresponds in position to the first portion of the source vector; a decode stage to decode a first instruction that is to specify a vector population count operation and a packed data field size indicating the second plurality of bits; and one or more single instruction, multiple data, SIMD, execution units comprising comparison logic and counting logic, responsive to the decode of the first instruction, to: read a value of each of the first plurality of packed data fields in the first portion of the source vector; compare the value from each of the first plurality of packed data fields in the first portion of the source vector for equality with each of one or more predetermined binary values that are to be fixed for the first instruction or the first instruction is to specify; for each predetermined binary value, count occurrences of the values from the first plurality of packed data fields equal to said predetermined binary value; and store, in the first portion of the destination register corresponding in position to the first portion of the source vector, a count of the occurrences for each of the corresponding one or more predetermined binary values. a storage to store a source vector having a first portion with a first plurality of packed data fields, wherein each of the first plurality of packed data fields has a second plurality of bits comprising four or more bits; a destination register, comprising a first portion that corresponds in position to the first portion of the source vector; a decode stage to decode a first instruction that is to specify a vector population count operation and a packed data field size indicating the second plurality of bits; and one or more single instruction, multiple data, SIMD, execution units comprising comparison logic and counting logic, responsive to the decode of the first instruction, to: read a value of each of the first plurality of packed data fields in the first portion of the source vector; compare the value from each of the first plurality of packed data fields in the first portion of the source vector for equality with each of one or more predetermined binary values that are to be fixed for the first instruction or the first instruction is to specify; for each predetermined binary value, count occurrences of the values from the first plurality of packed data fields equal to said predetermined binary value; and store, in the first portion of the destination register corresponding in position to the first portion of the source vector, a count of the occurrences for each of the corresponding one or more predetermined binary values. read a value of each of the first plurality of packed data fields in the first portion of the source vector; compare the value from each of the first plurality of packed data fields in the first portion of the source vector for equality with each of one or more predetermined binary values that are to be fixed for the first instruction or the first instruction is to specify; for each predetermined binary value, count occurrences of the values from the first plurality of packed data fields equal to said predetermined binary value; and store, in the first portion of the destination register corresponding in position to the first portion of the source vector, a count of the occurrences for each of the corresponding one or more predetermined binary values. <EOS>