A lateral field effect transistor device having: a plurality of source cells and a plurality of drain cells , each source cell having a central semiconductor source region , and each drain cell having a central semiconductor drain region , a first metallic conductive path (3a-3b) which extends from a source electrode (S) to join the source regions of the source cells, thereby connecting the source cells in series to the source electrode, the first metallic conductive path (3a-3b) comprising a main branch extending from the source electrode (S) toward a gate electrode (G), and a plurality of side branches extending from the main branch , a second metallic conductive path (4a-4b) which extends from a drain electrode (D) to join the drain regions of the drain cells, thereby connecting the drain cells in series to the drain electrode, the second metallic conductive path (4a-4b) comprising a main branch extending from the drain electrode (D) toward the gate electrode (G), and a plurality of side branches extending from the main branch , wherein the side-branches of the first and second metal conductive paths travel across the cells to connect the semiconductor regions of neighbouring source cells and the semiconductor regions of neighbouring drain cells in respective series rows and plural gate paths which extend from a gate electrode (G) around the edges of the cells to form boundaries between neighbouring source and drain cells, thereby forming respective field effect transistors between the source and drain regions of neighbouring cells; wherein the source cells and drain cells tessellate to cover an area of the device, the source and drain electrodes are spaced and alternate around the boundary of the tessellated area, and the gate electrode is centrally positioned in the tessellated area. a plurality of source cells and a plurality of drain cells , each source cell having a central semiconductor source region , and each drain cell having a central semiconductor drain region , a first metallic conductive path (3a-3b) which extends from a source electrode (S) to join the source regions of the source cells, thereby connecting the source cells in series to the source electrode, the first metallic conductive path (3a-3b) comprising a main branch extending from the source electrode (S) toward a gate electrode (G), and a plurality of side branches extending from the main branch , a second metallic conductive path (4a-4b) which extends from a drain electrode (D) to join the drain regions of the drain cells, thereby connecting the drain cells in series to the drain electrode, the second metallic conductive path (4a-4b) comprising a main branch extending from the drain electrode (D) toward the gate electrode (G), and a plurality of side branches extending from the main branch , wherein the side-branches of the first and second metal conductive paths travel across the cells to connect the semiconductor regions of neighbouring source cells and the semiconductor regions of neighbouring drain cells in respective series rows and plural gate paths which extend from a gate electrode (G) around the edges of the cells to form boundaries between neighbouring source and drain cells, thereby forming respective field effect transistors between the source and drain regions of neighbouring cells; wherein the source cells and drain cells tessellate to cover an area of the device, the source and drain electrodes are spaced and alternate around the boundary of the tessellated area, and the gate electrode is centrally positioned in the tessellated area. <EOS>