An electronic voltage divider circuit comprising at least two FDSOI transistors on insulating thin film (TP1, TP2) of a first type connected to a first supply potential and arranged in a current mirror structure and two FDSOI transistors on thin film (TN1, TN2) of a second type and an electrical load of non-zero impedance (R), the transistors each having a front-face main gate (G top ) and a back-face control gate (G back ), a drain of a first transistor (TN1) of the second type being connected to the drain of a first transistor (TP1) of the first type, a drain of a second transistor (TN2) of the second type being connected to the drain of a second transistor (TP2) of the first type, the drain of the first transistor of the second type being connected to the front-face gate of this same transistor, the front-face gates of the first and second transistors of the second type being connected to one another, the source of the first transistor of the second type being connected to a second supply potential and said load of non-zero impedance being placed between the source of the second transistor of the second type and said second supply potential, the drain of the second transistor (TP2) of the first type being connected to a front-face gate of the first and second transistors (TP1, TP2) of the first type, wherein the back-face gates of the first and second transistors of the second type (TN2) are connected to an external circuit (CPGA) applying a non-zero input voltage between these two back-face gates, such that the back-face gate of the first transistor of the second type is brought to a potential (V BBN1 ) lower than that (V BBN2 ) of the back-face gate of the second transistor of the second type if these two transistors are of nMOS type, and that the back-face gate of the first transistor of the second type is brought to a potential (V BBP1 ) greater than that (V BBP2 ) of the back-face gate of the second transistor of the second type if these two transistors are of pMOS type; whereby the voltage across the terminals of said load (V R ) is an output voltage equal to the sum of a first component A and a second component B; the first component A being dependent on the difference between the geometric ratios of gate width to gate length of said transistors; the second component B being proportional to said non-zero input voltage with a proportionality factor strictly less than 1; the second component B being preponderant with respect to the first component A. wherein the back-face gates of the first and second transistors of the second type (TN2) are connected to an external circuit (CPGA) applying a non-zero input voltage between these two back-face gates, such that the back-face gate of the first transistor of the second type is brought to a potential (V BBN1 ) lower than that (V BBN2 ) of the back-face gate of the second transistor of the second type if these two transistors are of nMOS type, and that the back-face gate of the first transistor of the second type is brought to a potential (V BBP1 ) greater than that (V BBP2 ) of the back-face gate of the second transistor of the second type if these two transistors are of pMOS type; whereby the voltage across the terminals of said load (V R ) is an output voltage equal to the sum of a first component A and a second component B; the first component A being dependent on the difference between the geometric ratios of gate width to gate length of said transistors; the second component B being proportional to said non-zero input voltage with a proportionality factor strictly less than 1; the second component B being preponderant with respect to the first component A. <EOS>