A method for manufacturing a Silicon Carbide, SiC, switch device, comprising the following steps of: epitaxially growing a drift layer of a first conduction type on the front side of a substrate of a first conduction type; forming a doped P well region of a second conduction type on the drift layer by ion implantation; forming an N+ region of a first conduction type on the doped P well region by ion implantation; forming a doped P+ region of a second conduction type on the doped P well region by ion implantation, wherein the P+ region is connected with both the N+ region and the doped P well region; forming a first epitaxial region of a first conduction type and a second epitaxial N+ region in an epitaxial growth sequence on a surface of the device; etching the first epitaxial region and the second epitaxial N+ region to form a SiC step, leaving the N+ region partially and the doped P+ region completely exposed; forming a lateral implantation P well region of a second conduction type on the surface of the device by lateral ion implantation; forming an oxide gate dielectric layer on the lateral implantation P well region by high-temperature oxidation; manufacturing a gate electrode on one side of the surface of the device by growth; growing an isolation dielectric on the surface of the device; opening a dielectric hole in the isolation dielectric and the gate dielectric layer by etching; and manufacturing an ohmic contact drain electrode on a back surface of the substrate by a metallization process, and forming an ohmic contact region on one side of the lateral implantation P well region on an upper surface of the device by high-temperature annealing; wherein a doping concentration of the second epitaxial N+ region is higher than that of the implantation P well region and a doping concentration of the implantation N+ region is higher than that of the implantation P well region . epitaxially growing a drift layer of a first conduction type on the front side of a substrate of a first conduction type; forming a doped P well region of a second conduction type on the drift layer by ion implantation; forming an N+ region of a first conduction type on the doped P well region by ion implantation; forming a doped P+ region of a second conduction type on the doped P well region by ion implantation, wherein the P+ region is connected with both the N+ region and the doped P well region; forming a first epitaxial region of a first conduction type and a second epitaxial N+ region in an epitaxial growth sequence on a surface of the device; etching the first epitaxial region and the second epitaxial N+ region to form a SiC step, leaving the N+ region partially and the doped P+ region completely exposed; forming a lateral implantation P well region of a second conduction type on the surface of the device by lateral ion implantation; forming an oxide gate dielectric layer on the lateral implantation P well region by high-temperature oxidation; manufacturing a gate electrode on one side of the surface of the device by growth; growing an isolation dielectric on the surface of the device; opening a dielectric hole in the isolation dielectric and the gate dielectric layer by etching; and manufacturing an ohmic contact drain electrode on a back surface of the substrate by a metallization process, and forming an ohmic contact region on one side of the lateral implantation P well region on an upper surface of the device by high-temperature annealing; <EOS>