A process for manufacturing MEMS devices , comprising the step of forming a first assembly , which includes: - a dielectric coating region , which is delimited by a first surface (S 1 ') and a second surface (S 2 '); - a dielectric redistribution region , which is delimited by the first surface (S 1 ') and by a third surface (S 3 '); and - a plurality of unit portions laterally staggered with respect to one another, each of which comprises: - at least one respective die , arranged in the dielectric coating region and including a corresponding electronic circuit (10, 12; 14, 16); - a plurality of corresponding first conductive connection elements , which give out onto the first surface (S 1 ') and are electrically coupled to said respective die ; - a plurality of corresponding second conductive connection elements , which give out onto the third surface (S 3 '); and - a plurality of conductive redistribution paths , which extend in the dielectric redistribution region and connect the second conductive connection elements to the first conductive connection elements ; said process further comprising the steps of: - forming a second assembly (80; 110), which includes a plurality of respective unit portions (84; 284), each of which comprises a respective semiconductor portion (82; 282) and a number of respective third conductive connection elements ; - mechanically coupling the first and second assemblies (74, 80; 74, 110) so that the third conductive connection elements of each unit portion (84; 284) of the second assembly (80; 110) are in electrical contact with the second conductive connection elements of a corresponding unit portion of the first assembly ; and then - removing at least part of the semiconductor portion (82; 282) of each unit portion (84; 284) of the second assembly (80; 110) so as to form, starting from each unit portion (84; 284) of the second assembly (80; 110), a plurality of corresponding membranes . - a dielectric coating region , which is delimited by a first surface (S 1 ') and a second surface (S 2 '); - a dielectric redistribution region , which is delimited by the first surface (S 1 ') and by a third surface (S 3 '); and - a plurality of unit portions laterally staggered with respect to one another, each of which comprises: - at least one respective die , arranged in the dielectric coating region and including a corresponding electronic circuit (10, 12; 14, 16); - a plurality of corresponding first conductive connection elements , which give out onto the first surface (S 1 ') and are electrically coupled to said respective die ; - a plurality of corresponding second conductive connection elements , which give out onto the third surface (S 3 '); and - a plurality of conductive redistribution paths , which extend in the dielectric redistribution region and connect the second conductive connection elements to the first conductive connection elements ; - forming a second assembly (80; 110), which includes a plurality of respective unit portions (84; 284), each of which comprises a respective semiconductor portion (82; 282) and a number of respective third conductive connection elements ; - mechanically coupling the first and second assemblies (74, 80; 74, 110) so that the third conductive connection elements of each unit portion (84; 284) of the second assembly (80; 110) are in electrical contact with the second conductive connection elements of a corresponding unit portion of the first assembly ; and then - removing at least part of the semiconductor portion (82; 282) of each unit portion (84; 284) of the second assembly (80; 110) so as to form, starting from each unit portion (84; 284) of the second assembly (80; 110), a plurality of corresponding membranes . <EOS>