A circuit comprising: a continuous diffusion region ; a first gate layer for a blocking transistor arranged according to a gate layer pitch between an adjacent second gate layer for a first adjacent transistor and an adjacent third gate layer for a second adjacent transistor , wherein the blocking transistor , the first ajacent transistor , and the second adjacent transistor are arranged in the continuous diffusion region such that the first and second adjacent transistors are electrically isolated by the blocking transistor being configured to be always turned off; a first level 2 gate-directed local interconnect arranged between the first gate layer and the second gate layer , wherein the first level 2 gate-directed local interconnect is coupled to a first source/drain terminal for the first adjacent transistor via a first level 1 gate-directed local interconnect arranged between the first level 2 gate-directed local interconnect and the first source/drain terminal; a second level 2 gate-directed local interconnect arranged between the first gate layer and the third gate layer , wherein the second level 2 gate-directed local interconnect is coupled to a second drain/source terminal for the second adjacent transistor via a second level 1 gate-directed local interconnect arranged between the second level 2 gate-directed local interconnect and the second drain/source terminal, wherein the first and second level 1 gate-directed local interconnects are arranged at the level of the first, second and third gate layers ; a level 2 diffusion-directed local interconnect coupling the first gate layer to the first level 2 gate-directed local interconnect; and a level 3 via (V0) coupled and arranged between a metal 1 layer (Ml) and the first level 2 gate-directed local interconnect layer to couple the first gate layer for the blocking transistor to a power supply node, the metal 1 layer (Ml) being above the level 3 via (V0). a continuous diffusion region ; a first gate layer for a blocking transistor arranged according to a gate layer pitch between an adjacent second gate layer for a first adjacent transistor and an adjacent third gate layer for a second adjacent transistor , wherein the blocking transistor , the first ajacent transistor , and the second adjacent transistor are arranged in the continuous diffusion region such that the first and second adjacent transistors are electrically isolated by the blocking transistor being configured to be always turned off; a first level 2 gate-directed local interconnect arranged between the first gate layer and the second gate layer , wherein the first level 2 gate-directed local interconnect is coupled to a first source/drain terminal for the first adjacent transistor via a first level 1 gate-directed local interconnect arranged between the first level 2 gate-directed local interconnect and the first source/drain terminal; a second level 2 gate-directed local interconnect arranged between the first gate layer and the third gate layer , wherein the second level 2 gate-directed local interconnect is coupled to a second drain/source terminal for the second adjacent transistor via a second level 1 gate-directed local interconnect arranged between the second level 2 gate-directed local interconnect and the second drain/source terminal, wherein the first and second level 1 gate-directed local interconnects are arranged at the level of the first, second and third gate layers ; a level 2 diffusion-directed local interconnect coupling the first gate layer to the first level 2 gate-directed local interconnect; and a level 3 via (V0) coupled and arranged between a metal 1 layer (Ml) and the first level 2 gate-directed local interconnect layer to couple the first gate layer for the blocking transistor to a power supply node, the metal 1 layer (Ml) being above the level 3 via (V0). <EOS>