An apparatus comprising: a hardware processor core ; and an accelerator circuit (106-0) coupled to the hardware processor core , the accelerator circuit (106-0) comprising a decompressor circuit and a direct memory access circuit to: in response to a first descriptor sent from the hardware processor core , cause the decompressor circuit to decompress compressed data from the direct memory access circuit into decompressed data and store the decompressed data in a buffer in the accelerator circuit (106-0), and in response to a second descriptor sent from the hardware processor core separately from the first descriptor , cause the decompressed data to be written from the buffer to memory external to the accelerator circuit (106-0) by the direct memory access circuit ; wherein the accelerator circuit (106-0) is to write the decompressed data to a destination address in the memory specified by the second descriptor and not the first descriptor wherein the second descriptor comprises at least one value that indicates the second descriptor provides the destination address for the decompressed data generated in response to the first desciptor , the at least one value is a same source address of the compressed data in the first descriptor and the second descriptor . a hardware processor core ; and an accelerator circuit (106-0) coupled to the hardware processor core , the accelerator circuit (106-0) comprising a decompressor circuit and a direct memory access circuit to: in response to a first descriptor sent from the hardware processor core , cause the decompressor circuit to decompress compressed data from the direct memory access circuit into decompressed data and store the decompressed data in a buffer in the accelerator circuit (106-0), and in response to a second descriptor sent from the hardware processor core separately from the first descriptor , cause the decompressed data to be written from the buffer to memory external to the accelerator circuit (106-0) by the direct memory access circuit ; wherein the accelerator circuit (106-0) is to write the decompressed data to a destination address in the memory specified by the second descriptor and not the first descriptor wherein the second descriptor comprises at least one value that indicates the second descriptor provides the destination address for the decompressed data generated in response to the first desciptor , the at least one value is a same source address of the compressed data in the first descriptor and the second descriptor . in response to a first descriptor sent from the hardware processor core , cause the decompressor circuit to decompress compressed data from the direct memory access circuit into decompressed data and store the decompressed data in a buffer in the accelerator circuit (106-0), and in response to a second descriptor sent from the hardware processor core separately from the first descriptor , cause the decompressed data to be written from the buffer to memory external to the accelerator circuit (106-0) by the direct memory access circuit ; wherein the accelerator circuit (106-0) is to write the decompressed data to a destination address in the memory specified by the second descriptor and not the first descriptor wherein the second descriptor comprises at least one value that indicates the second descriptor provides the destination address for the decompressed data generated in response to the first desciptor , the at least one value is a same source address of the compressed data in the first descriptor and the second descriptor . <EOS>