A device comprising: a first chip having a front side and a back side; a second chip stacked with the first chip and located on the back side of the first chip; and a first loop comprising: - first and second through vias located in the first chip and each having a first end on the front side of the first chip and a second end on the back side of the first chip; - a first track connecting the first ends of the first and second through vias and located in the first chip on the front side thereof; and - a second track connecting the second ends of the first and second through vias and located in the second chip; and at least a second loop comprising: - third and fourth through vias located in the first chip and each having a first end on the front side of the first chip and a second end on the back side of the first chip; - a third track connecting the first ends of the third and fourth through vias and located in the first chip on the front side thereof; and - a fourth track (38C; 38E) connecting the second ends of the third and fourth through vias and located in the second chip , the first chip comprising a first circuit for detecting an electrical characteristic of the first loop, the first circuit being adapted for detecting a least one of the following electrical characteristics of the first and second loops: an electric continuity between the first loop and the second loop; and a difference between the electric resistance of the first loop and of the second loop. a first chip having a front side and a back side; a second chip stacked with the first chip and located on the back side of the first chip; and a first loop comprising: - first and second through vias located in the first chip and each having a first end on the front side of the first chip and a second end on the back side of the first chip; - a first track connecting the first ends of the first and second through vias and located in the first chip on the front side thereof; and - a second track connecting the second ends of the first and second through vias and located in the second chip; and - first and second through vias located in the first chip and each having a first end on the front side of the first chip and a second end on the back side of the first chip; - a first track connecting the first ends of the first and second through vias and located in the first chip on the front side thereof; and - a second track connecting the second ends of the first and second through vias and located in the second chip; and at least a second loop comprising: - third and fourth through vias located in the first chip and each having a first end on the front side of the first chip and a second end on the back side of the first chip; - a third track connecting the first ends of the third and fourth through vias and located in the first chip on the front side thereof; and - a fourth track (38C; 38E) connecting the second ends of the third and fourth through vias and located in the second chip , - third and fourth through vias located in the first chip and each having a first end on the front side of the first chip and a second end on the back side of the first chip; - a third track connecting the first ends of the third and fourth through vias and located in the first chip on the front side thereof; and - a fourth track (38C; 38E) connecting the second ends of the third and fourth through vias and located in the second chip , the first chip comprising a first circuit for detecting an electrical characteristic of the first loop, the first circuit being adapted for detecting a least one of the following electrical characteristics of the first and second loops: an electric continuity between the first loop and the second loop; and a difference between the electric resistance of the first loop and of the second loop. an electric continuity between the first loop and the second loop; and a difference between the electric resistance of the first loop and of the second loop. <EOS>