An apparatus , comprising: a differential pair of input transistors (M1, M2); and a cascode circuit including a first pair of transistors (M13, M14) coupled to a first transistor (M1) of the differential pair and a second pair of transistors (M15, M16) coupled to a second transistor (M2) of the differential pair, said first pair of transistors and said second pair of transistors configured to receive a common gate bias voltage (VB1); another cascode circuit including a first transistor (M17) coupled to the first pair of transistors of (M13, M14) the cascode circuit and a second transistor (M18) coupled to the second pair of transistors (M15, M16) of the cascode circuit, the first transistor of the another cascode circuit and the second transistor of the another cascode circuit configured to receive a common gate voltage (VB2); wherein a first transistor (M13) of the first pair of transistors of the cascode circuit includes a drain coupled to a drain of the first transistor (M17) of the another cascode circuit and a second transistor (M14) of the first pair of transistors of the cascode circuit includes a drain coupled to a source of the first transistor (M17) of the another cascode circuit; wherein a first transistor (M16) of the second pair of transistors of the cascode circuit includes a drain coupled to a drain of the second transistor (M18) of the another cascode circuit and a second transistor (M15) of the second pair of transistors of the cascode circuit includes a drain coupled to a source of the second transistor (M18) of the another cascode circuit, wherein each transistor of the first pair of transistors (M13, M14) of the cascode circuit includes a source coupled to a drain of the first transistor (M1) of the differential pair of input transistors and each transistor of the second pair of transistors (M15, M16) of the cascode circuit includes a source coupled to a drain of the second transistor (M2) of the differential pair of input transistors. a differential pair of input transistors (M1, M2); and a cascode circuit including a first pair of transistors (M13, M14) coupled to a first transistor (M1) of the differential pair and a second pair of transistors (M15, M16) coupled to a second transistor (M2) of the differential pair, said first pair of transistors and said second pair of transistors configured to receive a common gate bias voltage (VB1); another cascode circuit including a first transistor (M17) coupled to the first pair of transistors of (M13, M14) the cascode circuit and a second transistor (M18) coupled to the second pair of transistors (M15, M16) of the cascode circuit, the first transistor of the another cascode circuit and the second transistor of the another cascode circuit configured to receive a common gate voltage (VB2); wherein a first transistor (M13) of the first pair of transistors of the cascode circuit includes a drain coupled to a drain of the first transistor (M17) of the another cascode circuit and a second transistor (M14) of the first pair of transistors of the cascode circuit includes a drain coupled to a source of the first transistor (M17) of the another cascode circuit; wherein a first transistor (M16) of the second pair of transistors of the cascode circuit includes a drain coupled to a drain of the second transistor (M18) of the another cascode circuit and a second transistor (M15) of the second pair of transistors of the cascode circuit includes a drain coupled to a source of the second transistor (M18) of the another cascode circuit, wherein each transistor of the first pair of transistors (M13, M14) of the cascode circuit includes a source coupled to a drain of the first transistor (M1) of the differential pair of input transistors and each transistor of the second pair of transistors (M15, M16) of the cascode circuit includes a source coupled to a drain of the second transistor (M2) of the differential pair of input transistors. <EOS>