An integrated current reference circuit , comprising a first voltage source (Vcc); a voltage offset circuit having a first end and a second end; a reference current (Iref) having one end coupled to the second end of the voltage offset circuit and another end coupled to a ground potential; a first p-channel transistor (MP1) having a source (S1) coupled to the first voltage source (Vcc), a gate (G1) coupled to the first end of the voltage offset circuit, and a drain (D1) coupled to the reference current (Iref); a second p-channel transistor (MP2) having a source (S2) coupled to the first voltage source (Vcc), a gate (G2) coupled to the first end of the voltage offset circuit, and a drain (D2) configured to provide an output current (lout); characterised in that the voltage offset circuit comprises: a second voltage source (Vd); an n-channel transistor (MN1) having a drain (D3) coupled to the second voltage source (Vd), a gate (G3) coupled to the drain (D1) of the first p-channel transistor (MP1), and a source (S3) coupled to the gate (G1) of the first p-channel transistor (MP1); and a first resistor (R1) coupled between the source (S3) of the n-channel transistor (MN1) and the ground potential; wherein the first voltage source (Vcc) is about 0.9V to 1.0V, and the second voltage source (Vd) is about 0.6V; wherein the gate (G3) of the n-channel transistor (MN1) has a voltage about 0.4V, and the gate (G1) of the first p-channel transistor (MP1) has a voltage about 0.1V. a first voltage source (Vcc); a voltage offset circuit having a first end and a second end; a reference current (Iref) having one end coupled to the second end of the voltage offset circuit and another end coupled to a ground potential; a first p-channel transistor (MP1) having a source (S1) coupled to the first voltage source (Vcc), a gate (G1) coupled to the first end of the voltage offset circuit, and a drain (D1) coupled to the reference current (Iref); a second p-channel transistor (MP2) having a source (S2) coupled to the first voltage source (Vcc), a gate (G2) coupled to the first end of the voltage offset circuit, and a drain (D2) configured to provide an output current (lout); characterised in that the voltage offset circuit comprises: a second voltage source (Vd); an n-channel transistor (MN1) having a drain (D3) coupled to the second voltage source (Vd), a gate (G3) coupled to the drain (D1) of the first p-channel transistor (MP1), and a source (S3) coupled to the gate (G1) of the first p-channel transistor (MP1); and a first resistor (R1) coupled between the source (S3) of the n-channel transistor (MN1) and the ground potential; wherein the first voltage source (Vcc) is about 0.9V to 1.0V, and the second voltage source (Vd) is about 0.6V; wherein the gate (G3) of the n-channel transistor (MN1) has a voltage about 0.4V, and the gate (G1) of the first p-channel transistor (MP1) has a voltage about 0.1V. a second voltage source (Vd); an n-channel transistor (MN1) having a drain (D3) coupled to the second voltage source (Vd), a gate (G3) coupled to the drain (D1) of the first p-channel transistor (MP1), and a source (S3) coupled to the gate (G1) of the first p-channel transistor (MP1); and a first resistor (R1) coupled between the source (S3) of the n-channel transistor (MN1) and the ground potential; wherein the first voltage source (Vcc) is about 0.9V to 1.0V, and the second voltage source (Vd) is about 0.6V; wherein the gate (G3) of the n-channel transistor (MN1) has a voltage about 0.4V, and the gate (G1) of the first p-channel transistor (MP1) has a voltage about 0.1V. <EOS>