An integrated circuit ferroelectric random access memory, FRAM, system, comprising: (a) an FRAM ; (b) a digital circuit coupled to the FRAM for controlling read and write operations in the FRAM; (c) a first supply voltage conductor coupled to the digital circuit for applying a first supply voltage (V CORE ) to the digital circuit and also coupled to a conductive pin (5-1) that conducts a second supply voltage (V LDO ) and is coupled to an external capacitor (C EXT ) so that a DC value of the first supply voltage is substantially equal to a DC value of the second supply voltage; (d) a second supply voltage conductor (4-4) coupled to the FRAM for applying a third supply voltage (V FRAM ) to the FRAM; (e) a switch circuit (SW1) having a first terminal coupled by the second supply voltage conductor to an internal capacitor (C INT ) and a second terminal coupled to the conductive pin so that a DC value of the third supply voltage is substantially equal to the DC value of the second supply voltage when the switch circuit is closed, and at least one inductance (L WIRE ) coupled between the external capacitor and the internal capacitor for preventing transmission of fast supply voltage transients; (f) a power interrupt detection circuit for detecting an interruption of the first supply voltage to produce an interruption signal and turning the switch circuit off and for causing the digital circuit to operate in response to the interruption signal (nBORdet) to prevent initiating of new read and write operations and to allow completion of ongoing read and write operations in the FRAM in response to the detecting of the interruption, wherein the internal capacitor maintains the third supply voltage above a predetermined level during the completing of ongoing read and write operations; and (g) delay circuitry for producing a delayed signal (nBOR(RCdelay)) for resetting the FRAM after the ongoing read and write operations have been completed. (a) an FRAM ; (b) a digital circuit coupled to the FRAM for controlling read and write operations in the FRAM; (c) a first supply voltage conductor coupled to the digital circuit for applying a first supply voltage (V CORE ) to the digital circuit and also coupled to a conductive pin (5-1) that conducts a second supply voltage (V LDO ) and is coupled to an external capacitor (C EXT ) so that a DC value of the first supply voltage is substantially equal to a DC value of the second supply voltage; (d) a second supply voltage conductor (4-4) coupled to the FRAM for applying a third supply voltage (V FRAM ) to the FRAM; (e) a switch circuit (SW1) having a first terminal coupled by the second supply voltage conductor to an internal capacitor (C INT ) and a second terminal coupled to the conductive pin so that a DC value of the third supply voltage is substantially equal to the DC value of the second supply voltage when the switch circuit is closed, and at least one inductance (L WIRE ) coupled between the external capacitor and the internal capacitor for preventing transmission of fast supply voltage transients; (f) a power interrupt detection circuit for detecting an interruption of the first supply voltage to produce an interruption signal and turning the switch circuit off and for causing the digital circuit to operate in response to the interruption signal (nBORdet) to prevent initiating of new read and write operations and to allow completion of ongoing read and write operations in the FRAM in response to the detecting of the interruption, wherein the internal capacitor maintains the third supply voltage above a predetermined level during the completing of ongoing read and write operations; and (g) delay circuitry for producing a delayed signal (nBOR(RCdelay)) for resetting the FRAM after the ongoing read and write operations have been completed. <EOS>