A single gate stack quantum dot semiconductor device for use in a quantum computer, the device comprising: a semiconductor substrate ; a reservoir accumulation gate (511; 611; 711; 811a; 911a; 1011a) placed on top of the semiconductor substrate and defining an electric charge reservoir in the semiconductor substrate; a quantum dot accumulation gate (501; 601; 701; 801a; 901a; 1001a) placed on top of the semiconductor substrate and defining a quantum dot well (QD) in the semiconductor substrate; a spatial gap (S) between said reservoir accumulation gate and said quantum dot accumulation gate on top of the semiconductor substrate; wherein a tunnel barrier (T) is created between said electric charge reservoir and said quantum dot well in the semiconductor substrate underneath said spatial gap when a common polarity electrical potential is applied to said reservoir accumulation gate and said quantum dot accumulation gate, said common polarity electrical potential defining a tunnel barrier height, width and charge tunneling rate between said quantum dot well and said electric charge reservoir without relying on any barrier gate to control the charge tunneling rate, the device further comprising: control circuitry connected to said reservoir accumulation gate and said quantum dot accumulation gate for applying to said reservoir accumulation gate and said quantum dot accumulation gate the common polarity electrical potential to define said tunnel barrier height, width and charge tunneling rate between said quantum dot well and said electric charge reservoir without relying on any barrier gate to control the charge tunneling rate. a semiconductor substrate ; a reservoir accumulation gate (511; 611; 711; 811a; 911a; 1011a) placed on top of the semiconductor substrate and defining an electric charge reservoir in the semiconductor substrate; a quantum dot accumulation gate (501; 601; 701; 801a; 901a; 1001a) placed on top of the semiconductor substrate and defining a quantum dot well (QD) in the semiconductor substrate; a spatial gap (S) between said reservoir accumulation gate and said quantum dot accumulation gate on top of the semiconductor substrate; wherein a tunnel barrier (T) is created between said electric charge reservoir and said quantum dot well in the semiconductor substrate underneath said spatial gap when a common polarity electrical potential is applied to said reservoir accumulation gate and said quantum dot accumulation gate, said common polarity electrical potential defining a tunnel barrier height, width and charge tunneling rate between said quantum dot well and said electric charge reservoir without relying on any barrier gate to control the charge tunneling rate, the device further comprising: control circuitry connected to said reservoir accumulation gate and said quantum dot accumulation gate for applying to said reservoir accumulation gate and said quantum dot accumulation gate the common polarity electrical potential to define said tunnel barrier height, width and charge tunneling rate between said quantum dot well and said electric charge reservoir without relying on any barrier gate to control the charge tunneling rate. <EOS>