A memory controller coupled to a cross-point non-volatile phase change memory , the memory controller being configured to refresh voltage values of a plurality of memory cells of the cross-point non-volatile phase change memory having voltage values respectively set to a first threshold voltage or a second threshold voltage, the memory controller comprising: read logic configured to refresh a voltage value of a first one or more of the plurality of memory cells set to the first threshold voltage by reading the plurality of memory cells ; and write logic coupled with the read logic and configured to refresh a voltage value of a second one or more of the plurality of memory cells set to the second threshold voltage without altering the voltage value of the first one or more of the plurality of memory cells set to the first threshold voltage; error correction logic coupled with the read logic and the write logic configured to: identify a number of third one or more memory cells of the plurality of memory cells that produce an error upon a read of the voltage value of the third one or more memory cells by the read logic; and detect whether the number of the third one or more memory cells of the plurality of memory cells exceeds an error threshold; wherein the write logic is configured to perform a write operation, in response to a detection by the error correction logic that the number of the third one or more memory cells of the plurality of memory cells exceeds the error threshold, to reset the respective voltage values of each memory cell in the third one or more memory cells to the first threshold voltage if the memory cell is set to the first threshold voltage and to reset the respective voltage values of each memory cell in the third one or more memory cells to the second threshold voltage if the memory cell is set to the second threshold voltage . read logic configured to refresh a voltage value of a first one or more of the plurality of memory cells set to the first threshold voltage by reading the plurality of memory cells ; and write logic coupled with the read logic and configured to refresh a voltage value of a second one or more of the plurality of memory cells set to the second threshold voltage without altering the voltage value of the first one or more of the plurality of memory cells set to the first threshold voltage; error correction logic coupled with the read logic and the write logic configured to: identify a number of third one or more memory cells of the plurality of memory cells that produce an error upon a read of the voltage value of the third one or more memory cells by the read logic; and detect whether the number of the third one or more memory cells of the plurality of memory cells exceeds an error threshold; identify a number of third one or more memory cells of the plurality of memory cells that produce an error upon a read of the voltage value of the third one or more memory cells by the read logic; and detect whether the number of the third one or more memory cells of the plurality of memory cells exceeds an error threshold; wherein the write logic is configured to perform a write operation, in response to a detection by the error correction logic that the number of the third one or more memory cells of the plurality of memory cells exceeds the error threshold, to reset the respective voltage values of each memory cell in the third one or more memory cells to the first threshold voltage if the memory cell is set to the first threshold voltage and to reset the respective voltage values of each memory cell in the third one or more memory cells to the second threshold voltage if the memory cell is set to the second threshold voltage . <EOS>