An organic light-emitting diode display device comprising an organic light-emitting diode (OLE) having an anode electrode (ANO), an organic emission layer (OL), and a cathode electrode (CAT), the organic light-emitting diode display device comprising: a low potential source line (VSL) configured to supply a low potential source voltage; at least one auxiliary cathode electrode (ACAT) configured to connect the low potential source line (VSL) to the cathode electrode (CAT); and pixel regions partitioned by gate lines (GL) and data lines (DL) crossing each other, wherein the at least one auxiliary cathode (ACAT) electrode includes a first electrode layer (M1) connected to the low potential source line (VSL), and a second electrode layer (M2) connected to the first electrode layer (M1) at a plurality of first positions and connected to the cathode electrode (CAT) at a plurality of second positions different from the plurality of first positions, wherein, in a region in which the cathode electrode (CAT) and the auxiliary cathode electrode (ACAT) are connected, the first electrode layer (M1) of the auxiliary cathode electrode (ACAT) is disposed on a gate insulating film (GI) covering the gate line (GL), a planarization layer (PL) having a plurality of opening portions exposing the first electrode layer (M1) at the plurality of first positions is disposed on the first electrode layer (M1), the first positions corresponding to concave portions of the planarization layer (PL), the second electrode layer (M2) is disposed on the planarization layer (PL) and connected to the first electrode layer (M1) at the plurality of first positions, a residual organic emission layer (ROL) is disposed at positions of the second electrode layer (M2) corresponding to the plurality of first positions, characterized in that the cathode electrode (CAT) is disposed on the residual organic emission layer (ROL) and the second electrode layer (M2), and connected to the second electrode layer (M2) at the plurality of second positions corresponding to convex portions of the planarization layer (PL). a low potential source line (VSL) configured to supply a low potential source voltage; at least one auxiliary cathode electrode (ACAT) configured to connect the low potential source line (VSL) to the cathode electrode (CAT); and pixel regions partitioned by gate lines (GL) and data lines (DL) crossing each other, wherein the at least one auxiliary cathode (ACAT) electrode includes a first electrode layer (M1) connected to the low potential source line (VSL), and a second electrode layer (M2) connected to the first electrode layer (M1) at a plurality of first positions and connected to the cathode electrode (CAT) at a plurality of second positions different from the plurality of first positions, wherein, in a region in which the cathode electrode (CAT) and the auxiliary cathode electrode (ACAT) are connected, the first electrode layer (M1) of the auxiliary cathode electrode (ACAT) is disposed on a gate insulating film (GI) covering the gate line (GL), a planarization layer (PL) having a plurality of opening portions exposing the first electrode layer (M1) at the plurality of first positions is disposed on the first electrode layer (M1), the first positions corresponding to concave portions of the planarization layer (PL), the second electrode layer (M2) is disposed on the planarization layer (PL) and connected to the first electrode layer (M1) at the plurality of first positions, a residual organic emission layer (ROL) is disposed at positions of the second electrode layer (M2) corresponding to the plurality of first positions, characterized in that the cathode electrode (CAT) is disposed on the residual organic emission layer (ROL) and the second electrode layer (M2), and connected to the second electrode layer (M2) at the plurality of second positions corresponding to convex portions of the planarization layer (PL). <EOS>