An apparatus comprising: a processor circuit (122; 520); a receive module (230; 522-1) for execution on the processor circuit to receive one or more configuration commands ; a configuration module (240; 522-2) for execution on the processor circuit (122; 520) to cause a solid state drive, SSD, to be configured to operate in one of a storage mode, a memory mode or a combination thereof based on the received one or more configuration commands ; a storage module (210; 522-3) for execution on the processor circuit (122; 520) to operate the SSD in the storage mode, the storage module (210; 522-3) having direct memory access, DMA, capabilities to access one or more non-volatile memory arrays for the SSD and a device programming interface to coordinate storage of data to at least a portion of the one or more non-volatile memory arrays via use of the DMA capabilities; and a memory module (220; 522-4) for execution on the processor circuit (122; 520) to operate the SSD in the memory mode, the memory module (220; 522-4) to cause at least a portion of the one or more non-volatile memory arrays to be addressable via a memory mapping configuration command included in the received one or more configuration commands, the memory mapping configuration command included in the received one or more configuration commands including a Peripheral Component Interconnect, PCI, Express, PCIe, or Non-Volatile Memory Express, NVMe, memory mapping configuration command, the memory module to cause the portion of the one or more non-volatile memory arrays to be addressable to the host system for use as system memory based on the PCIe or NVMe mapping configuration command. a processor circuit (122; 520); a receive module (230; 522-1) for execution on the processor circuit to receive one or more configuration commands ; a configuration module (240; 522-2) for execution on the processor circuit (122; 520) to cause a solid state drive, SSD, to be configured to operate in one of a storage mode, a memory mode or a combination thereof based on the received one or more configuration commands ; a storage module (210; 522-3) for execution on the processor circuit (122; 520) to operate the SSD in the storage mode, the storage module (210; 522-3) having direct memory access, DMA, capabilities to access one or more non-volatile memory arrays for the SSD and a device programming interface to coordinate storage of data to at least a portion of the one or more non-volatile memory arrays via use of the DMA capabilities; and a memory module (220; 522-4) for execution on the processor circuit (122; 520) to operate the SSD in the memory mode, the memory module (220; 522-4) to cause at least a portion of the one or more non-volatile memory arrays to be addressable via a memory mapping configuration command included in the received one or more configuration commands, the memory mapping configuration command included in the received one or more configuration commands including a Peripheral Component Interconnect, PCI, Express, PCIe, or Non-Volatile Memory Express, NVMe, memory mapping configuration command, the memory module to cause the portion of the one or more non-volatile memory arrays to be addressable to the host system for use as system memory based on the PCIe or NVMe mapping configuration command. <EOS>