An integrated circuit system comprising: a digital signal processing, DSP, block comprising: a plurality of columns (102, 102A-C, 102E-H, 102J-L) of weight registers ; a plurality of inputs configured to receive a first plurality of values and a second plurality of values, wherein the first plurality of values is stored in the plurality of columns (102, 102A-C, 102E-H, 102J-L) of weight registers after being received, wherein: in a first mode of operation, the first and second pluralities of values are received via a first portion of the plurality of inputs; and in a second mode of operation: the first plurality of values is received via a second portion of the plurality of inputs different than the first plurality of inputs; and the second plurality of values is received via the first portion of the plurality of inputs; and a plurality of multipliers configured to simultaneously multiply each value of the first plurality of values by each value of the second plurality of values, wherein the first plurality of values are weights and the second plurality of values are data input, characterized in that when operating in the second mode, the weights are taken from pins normally used for the data input of the multipliers not being used in the second mode. a plurality of columns (102, 102A-C, 102E-H, 102J-L) of weight registers ; a plurality of inputs configured to receive a first plurality of values and a second plurality of values, wherein the first plurality of values is stored in the plurality of columns (102, 102A-C, 102E-H, 102J-L) of weight registers after being received, wherein: in a first mode of operation, the first and second pluralities of values are received via a first portion of the plurality of inputs; and in a second mode of operation: the first plurality of values is received via a second portion of the plurality of inputs different than the first plurality of inputs; and the second plurality of values is received via the first portion of the plurality of inputs; and a plurality of multipliers configured to simultaneously multiply each value of the first plurality of values by each value of the second plurality of values, wherein the first plurality of values are weights and the second plurality of values are data input, characterized in that when operating in the second mode, the weights are taken from pins normally used for the data input of the multipliers not being used in the second mode. in a first mode of operation, the first and second pluralities of values are received via a first portion of the plurality of inputs; and in a second mode of operation: the first plurality of values is received via a second portion of the plurality of inputs different than the first plurality of inputs; and the second plurality of values is received via the first portion of the plurality of inputs; and a plurality of multipliers configured to simultaneously multiply each value of the first plurality of values by each value of the second plurality of values, wherein the first plurality of values are weights and the second plurality of values are data input, characterized in that when operating in the second mode, the weights are taken from pins normally used for the data input of the multipliers not being used in the second mode. the first plurality of values is received via a second portion of the plurality of inputs different than the first plurality of inputs; and the second plurality of values is received via the first portion of the plurality of inputs; and a plurality of multipliers configured to simultaneously multiply each value of the first plurality of values by each value of the second plurality of values, wherein the first plurality of values are weights and the second plurality of values are data input, characterized in that when operating in the second mode, the weights are taken from pins normally used for the data input of the multipliers not being used in the second mode. <EOS>