A MOS device comprising: - a substrate including a first well of a first conductivity type defined within the substrate, - the well having a top surface and having, defined within the first well: a region of the second conductivity type forming a bottom gate ,a first source of the first conductivity type, a first drain of the first conductivity type, a second drain of the first conductivity type between the first drain and the first source, a region of the second conductivity type forming a first gate disposed at the top surface and between the first drain and the second drain, a first channel of the first conductivity type defined between the bottom gate and the first gate, wherein the bottom gate is disposed below the first channel, the first channel providing in use conduction between the first drain and the second drain , a gap between the first source and the second drain, and a second channel of the second conductivity type disposed within the first well , the first and second channels having opposite doping types, the second channel providing in use conduction between the first source and the second drain ; - wherein the MOS device further comprises a dielectric layer disposed above the top surface of the first well and aligned with the gap; and a second gate disposed above the dielectric layer and aligned with the gap , - wherein the MOS device further comprises a first sidewall and a second sidewall both of the second conductivity type and defined within the first well and both joined to an opposing end of the bottom gate , the bottom gate and the two sidewalls defining a second well within the first well and - wherein the first source , first and second drains , and first gate are all disposed within the second well, - wherein at least one sidewall extends to the top surface and - wherein the first gate and the bottom gate form a dual gate of a JFET. - a substrate including a first well of a first conductivity type defined within the substrate, - the well having a top surface and having, defined within the first well: a region of the second conductivity type forming a bottom gate ,a first source of the first conductivity type, a first drain of the first conductivity type, a second drain of the first conductivity type between the first drain and the first source, a region of the second conductivity type forming a first gate disposed at the top surface and between the first drain and the second drain, a first channel of the first conductivity type defined between the bottom gate and the first gate, wherein the bottom gate is disposed below the first channel, the first channel providing in use conduction between the first drain and the second drain , a gap between the first source and the second drain, and a second channel of the second conductivity type disposed within the first well , the first and second channels having opposite doping types, the second channel providing in use conduction between the first source and the second drain ; - wherein the MOS device further comprises a dielectric layer disposed above the top surface of the first well and aligned with the gap; and a second gate disposed above the dielectric layer and aligned with the gap , - wherein the MOS device further comprises a first sidewall and a second sidewall both of the second conductivity type and defined within the first well and both joined to an opposing end of the bottom gate , the bottom gate and the two sidewalls defining a second well within the first well and - wherein the first source , first and second drains , and first gate are all disposed within the second well, - wherein at least one sidewall extends to the top surface and - wherein the first gate and the bottom gate form a dual gate of a JFET. <EOS>