An integrated circuit which includes at least one transistor, called nano-ridge transistor, said circuit comprising: - a crystal silicon substrate having a silicon surface (S); - the nano-ridge transistor, which comprises at least three III-V semiconducting crystal portions (4-7) superposed so that at least part of one of the III-V portions is intermediate between respective parts of two other ones of said III-V portions along a superposition direction, and a first one of said III-V portions is connected to the silicon surface (S) of the substrate through an epitaxial material transition between silicon and a material of the first III-V portion, and those of the III-V portions which are next to one another have epitaxial interfaces in-between; - at least three electrical connections (14-16) which are arranged so that three parts of the III-V portions (4-7) of the nano-ridge transistor are each electrically contacted by at least one of said electrical connections; and - an electrically insulating portion which is supported by the silicon substrate and abuts laterally against at least one of the III-V portions (4-7), wherein the first III-V portion of the nano-ridge transistor is connected to the silicon surface (S) through an intermediate portion which contains the epitaxial material transition between silicon and the material of the first III-V portion, said intermediate portion being also abutted laterally by the electrically insulating portion , and less in thickness than said electrically insulating portion, or equal, along a direction (D1) perpendicular to the silicon surface, and having an aspect ratio greater than unity, said aspect ratio being equal to a thickness (t) of said intermediate portion divided by a width (w) of said intermediate portion which is measured parallel to the silicon surface. - a crystal silicon substrate having a silicon surface (S); - the nano-ridge transistor, which comprises at least three III-V semiconducting crystal portions (4-7) superposed so that at least part of one of the III-V portions is intermediate between respective parts of two other ones of said III-V portions along a superposition direction, and a first one of said III-V portions is connected to the silicon surface (S) of the substrate through an epitaxial material transition between silicon and a material of the first III-V portion, and those of the III-V portions which are next to one another have epitaxial interfaces in-between; - at least three electrical connections (14-16) which are arranged so that three parts of the III-V portions (4-7) of the nano-ridge transistor are each electrically contacted by at least one of said electrical connections; and - an electrically insulating portion which is supported by the silicon substrate and abuts laterally against at least one of the III-V portions (4-7), wherein the first III-V portion of the nano-ridge transistor is connected to the silicon surface (S) through an intermediate portion which contains the epitaxial material transition between silicon and the material of the first III-V portion, said intermediate portion being also abutted laterally by the electrically insulating portion , and less in thickness than said electrically insulating portion, or equal, along a direction (D1) perpendicular to the silicon surface, and having an aspect ratio greater than unity, said aspect ratio being equal to a thickness (t) of said intermediate portion divided by a width (w) of said intermediate portion which is measured parallel to the silicon surface. <EOS>