A multilayer structure comprising: a single crystal semiconductor handle substrate , wherein the single crystal semiconductor handle substrate comprises two major, generally parallel surfaces, one of which is a front surface of the single crystal semiconductor handle substrate and the other of which is a back surface of the single crystal semiconductor handle substrate , a circumferential edge joining the front surface and the back surface of the single crystal semiconductor handle substrate , a central plane between the front surface and the back surface of the single crystal semiconductor handle substrate, and a bulk region between the front and back surfaces of the single crystal semiconductor handle substrate, wherein the single crystal semiconductor handle substrate has a minimum bulk region resistivity of at least 500 Ohm-cm, wherein the single crystal semiconductor handle substrate has a handle crystal orientation, and wherein the single crystal semiconductor handle substrate comprises an electrically active p-type dopant selected from the group consisting of boron, aluminum, gallium, indium, and any combination thereof; an epitaxial layer in interfacial contact with the front surface of the single crystal semiconductor handle substrate , wherein the epitaxial layer has a resistivity between 100 Ohm-cm and 5000 Ohm-cm, wherein the epitaxial layer has a crystal orientation that is the same as the handle crystal orientation, and wherein the epitaxial layer comprises silicon and an electrically active n-type dopant selected from the group consisting of arsenic, phosphorus, antimony, and any combination thereof; a charge trapping layer in interfacial contact with the epitaxial layer , the charge trapping layer comprising polycrystalline silicon and having a resistivity of at least 3000 Ohm-cm; a dielectric layer in interfacial contact with the charge trapping layer ; and a single crystal semiconductor device layer in interfacial contact with the dielectric layer. a single crystal semiconductor handle substrate , wherein the single crystal semiconductor handle substrate comprises two major, generally parallel surfaces, one of which is a front surface of the single crystal semiconductor handle substrate and the other of which is a back surface of the single crystal semiconductor handle substrate , a circumferential edge joining the front surface and the back surface of the single crystal semiconductor handle substrate , a central plane between the front surface and the back surface of the single crystal semiconductor handle substrate, and a bulk region between the front and back surfaces of the single crystal semiconductor handle substrate, wherein the single crystal semiconductor handle substrate has a minimum bulk region resistivity of at least 500 Ohm-cm, wherein the single crystal semiconductor handle substrate has a handle crystal orientation, and wherein the single crystal semiconductor handle substrate comprises an electrically active p-type dopant selected from the group consisting of boron, aluminum, gallium, indium, and any combination thereof; an epitaxial layer in interfacial contact with the front surface of the single crystal semiconductor handle substrate , wherein the epitaxial layer has a resistivity between 100 Ohm-cm and 5000 Ohm-cm, wherein the epitaxial layer has a crystal orientation that is the same as the handle crystal orientation, and wherein the epitaxial layer comprises silicon and an electrically active n-type dopant selected from the group consisting of arsenic, phosphorus, antimony, and any combination thereof; a charge trapping layer in interfacial contact with the epitaxial layer , the charge trapping layer comprising polycrystalline silicon and having a resistivity of at least 3000 Ohm-cm; a dielectric layer in interfacial contact with the charge trapping layer ; and a single crystal semiconductor device layer in interfacial contact with the dielectric layer. <EOS>