Apparatus, comprising a clock (CLK, CLK0, CLK1, 71, 74) adapted to provide a clock signal, wherein the clock signal alternates with a cycle between a first level and a second level different from the first level; a first combinational logic adapted to output a first signal; a first latch (LL1, 72, LL91) adapted to be clocked such that it passes the first signal when the clock signal is at the first level; a second combinational logic (F2, 73, F92) adapted to output a second signal based on the first signal passed through the first latch; a second latch (LL2, 75, 78, LL93) adapted to be clocked such that it passes the second signal when the clock signal is at the second level; a detecting means (TED, 76) adapted to detect a timing violation of at least one of the first signal at the first latch when the clock signal is at the first level and of the second signal at the second latch when the clock signal is at the second level, said detecting means being adapted to detect the timing violation at the respective latch as the respective preceding combinational logic not having finished its operation when the clock signal transits into the respective level; a time stretching means (TED, 76) adapted to stretch, in response to the detecting means detecting the timing violation, the clock such that the clock alternates between the first level and the second level with a delay compared to a time of alternating between the first level and the second level according to the cycle characterized in that the first latch is adapted to be clocked such that it is closed for the first signal when the clock is at the second level; and the second latch is adapted to be clocked such that it is closed for the second signal when the clock is at the first level. a clock (CLK, CLK0, CLK1, 71, 74) adapted to provide a clock signal, wherein the clock signal alternates with a cycle between a first level and a second level different from the first level; a first combinational logic adapted to output a first signal; a first latch (LL1, 72, LL91) adapted to be clocked such that it passes the first signal when the clock signal is at the first level; a second combinational logic (F2, 73, F92) adapted to output a second signal based on the first signal passed through the first latch; a second latch (LL2, 75, 78, LL93) adapted to be clocked such that it passes the second signal when the clock signal is at the second level; a detecting means (TED, 76) adapted to detect a timing violation of at least one of the first signal at the first latch when the clock signal is at the first level and of the second signal at the second latch when the clock signal is at the second level, said detecting means being adapted to detect the timing violation at the respective latch as the respective preceding combinational logic not having finished its operation when the clock signal transits into the respective level; a time stretching means (TED, 76) adapted to stretch, in response to the detecting means detecting the timing violation, the clock such that the clock alternates between the first level and the second level with a delay compared to a time of alternating between the first level and the second level according to the cycle characterized in that the first latch is adapted to be clocked such that it is closed for the first signal when the clock is at the second level; and the second latch is adapted to be clocked such that it is closed for the second signal when the clock is at the first level. <EOS>