Safety controller , comprising: a) a first controller suitable for controlling a facility or a process having a first clock generator suitable for generating a first clock signal ; b) a separate second controller suitable for controlling the facility or the process having a second clock generator suitable for generating a second clock signal ; wherein c) the first clock signal is output to a first input of the first controller and to a first input of the second controller for allowing a synchronous processing of programs on the first and second controller ; characterized in that , d) the second clock signal is output to a second input of the first controller and to a second input of the second controller ; e) the frequency of the second clock signal is higher than the frequency of the first clock signal ; f) the first controller comprises a first counter and the second controller comprises a second counter , and the second clock signal is routed to the first counter and to the second counter and the clocks of the second clock signal are counted by means of the first and the second counter for determining an integer number of clocks of the second clock signal, that appears during a clock interval of the first clock signal; g) the first clock signal triggers an interrupt simultaneously in the first and second controllers ; h) the first counter and the second counter are suitable for determining the number of clocks of the second clock signal since a previous interrupt ; i) the first controller and/or the second controller are suitable for correlating the counter readings of the respective first or second counter with the time interval between two interrupts ; and j) the first controller and/or the second controller are suitable for providing an error output when the controller determines that the counter reading of the respective first or second counter is outside its reference range . a) a first controller suitable for controlling a facility or a process having a first clock generator suitable for generating a first clock signal ; b) a separate second controller suitable for controlling the facility or the process having a second clock generator suitable for generating a second clock signal ; wherein c) the first clock signal is output to a first input of the first controller and to a first input of the second controller for allowing a synchronous processing of programs on the first and second controller ; characterized in that , d) the second clock signal is output to a second input of the first controller and to a second input of the second controller ; e) the frequency of the second clock signal is higher than the frequency of the first clock signal ; f) the first controller comprises a first counter and the second controller comprises a second counter , and the second clock signal is routed to the first counter and to the second counter and the clocks of the second clock signal are counted by means of the first and the second counter for determining an integer number of clocks of the second clock signal, that appears during a clock interval of the first clock signal; g) the first clock signal triggers an interrupt simultaneously in the first and second controllers ; h) the first counter and the second counter are suitable for determining the number of clocks of the second clock signal since a previous interrupt ; i) the first controller and/or the second controller are suitable for correlating the counter readings of the respective first or second counter with the time interval between two interrupts ; and j) the first controller and/or the second controller are suitable for providing an error output when the controller determines that the counter reading of the respective first or second counter is outside its reference range . <EOS>