An apparatus comprising: a detector circuit (220; 620; 820) configured to determine whether or not an atypical amount of phase error exists in a phase-locked loop (PLL); and a holdover circuit configured to enter a holdover state in response to a logic comparator output signal (PHE), wherein the holdover state is initiated asynchronously by the logic comparator output signal (PHE) when the detector circuit has determined that the atypical amount of phase error exists, wherein the detector circuit (220; 620; 820) comprises: an OR gate having a first input (UP), a second input (DN) and an output, wherein the first input is coupled to a first output of a phase frequency detector wherein the second input is coupled to a second output of the phase frequency detector and the OR gate is configured to generate a trigger pulse signal (UOD) at the output; and a logic time detection circuit configured to delay the trigger pulse signal (UOD) by a threshold delay time to generate a delayed pulse signal (UODT) and AND the trigger pulse signal (UOD) and the delayed pulse signal (UODT) to generate the logic comparator output signal (PHE) configured to initiate the holdover state; wherein the apparatus further comprises a training circuit configured to receive the trigger pulse signal (UOD) and the delayed pulse signal (UODT) and to calculate the threshold time delay such that the logic comparator output signal (PHE) only transitions when the PLL transitions out of phase lock. a detector circuit (220; 620; 820) configured to determine whether or not an atypical amount of phase error exists in a phase-locked loop (PLL); and a holdover circuit configured to enter a holdover state in response to a logic comparator output signal (PHE), wherein the holdover state is initiated asynchronously by the logic comparator output signal (PHE) when the detector circuit has determined that the atypical amount of phase error exists, wherein the detector circuit (220; 620; 820) comprises: an OR gate having a first input (UP), a second input (DN) and an output, wherein the first input is coupled to a first output of a phase frequency detector wherein the second input is coupled to a second output of the phase frequency detector and the OR gate is configured to generate a trigger pulse signal (UOD) at the output; and a logic time detection circuit configured to delay the trigger pulse signal (UOD) by a threshold delay time to generate a delayed pulse signal (UODT) and AND the trigger pulse signal (UOD) and the delayed pulse signal (UODT) to generate the logic comparator output signal (PHE) configured to initiate the holdover state; wherein the apparatus further comprises a training circuit configured to receive the trigger pulse signal (UOD) and the delayed pulse signal (UODT) and to calculate the threshold time delay such that the logic comparator output signal (PHE) only transitions when the PLL transitions out of phase lock. an OR gate having a first input (UP), a second input (DN) and an output, wherein the first input is coupled to a first output of a phase frequency detector wherein the second input is coupled to a second output of the phase frequency detector and the OR gate is configured to generate a trigger pulse signal (UOD) at the output; and a logic time detection circuit configured to delay the trigger pulse signal (UOD) by a threshold delay time to generate a delayed pulse signal (UODT) and AND the trigger pulse signal (UOD) and the delayed pulse signal (UODT) to generate the logic comparator output signal (PHE) configured to initiate the holdover state; wherein the apparatus further comprises a training circuit configured to receive the trigger pulse signal (UOD) and the delayed pulse signal (UODT) and to calculate the threshold time delay such that the logic comparator output signal (PHE) only transitions when the PLL transitions out of phase lock. <EOS>