A PLL circuit adapted to generate a chirp signal for a frequency modulated continuous wave (FMCW) radar, said PLL circuit comprising: a voltage-controlled oscillator for outputting a signal with a frequency depending on a frequency control voltage provided to the voltage-controlled oscillator; a variable frequency divider for frequency-dividing the output signal from the voltage-controlled oscillator on a basis of a signal representing a division ratio provided to the variable frequency divider; a phase-frequency comparator for comparing a reference signal with an output signal from the variable frequency divider, and outputting an up signal of frequency and a down signal of frequency depending on results of the comparison; a charge pump for outputting a current corresponding to each of the up signal and the down signal; a loop filter for outputting a signal obtained by performing current-voltage conversion and smoothing on the output from the charge pump, as the frequency control voltage, to the voltage-controlled oscillator; a frequency control circuit for operating using the reference signal as a clock, and outputting a signal corresponding to an output frequency of the voltage-controlled oscillator; characterised by an AND circuit for outputting a result of an AND operation between the up signal and the down signal; a flip-flop circuit for holding the output signal from the frequency control circuit at timing of an output signal from the AND circuit, and outputting the held output signal; and a ΔΣ modulator for operating using the output from the variable frequency divider as a clock, and determining a division ratio for the variable frequency divider on a basis of the output from the flip-flop circuit. a voltage-controlled oscillator for outputting a signal with a frequency depending on a frequency control voltage provided to the voltage-controlled oscillator; a variable frequency divider for frequency-dividing the output signal from the voltage-controlled oscillator on a basis of a signal representing a division ratio provided to the variable frequency divider; a phase-frequency comparator for comparing a reference signal with an output signal from the variable frequency divider, and outputting an up signal of frequency and a down signal of frequency depending on results of the comparison; a charge pump for outputting a current corresponding to each of the up signal and the down signal; a loop filter for outputting a signal obtained by performing current-voltage conversion and smoothing on the output from the charge pump, as the frequency control voltage, to the voltage-controlled oscillator; a frequency control circuit for operating using the reference signal as a clock, and outputting a signal corresponding to an output frequency of the voltage-controlled oscillator; characterised by an AND circuit for outputting a result of an AND operation between the up signal and the down signal; a flip-flop circuit for holding the output signal from the frequency control circuit at timing of an output signal from the AND circuit, and outputting the held output signal; and a ΔΣ modulator for operating using the output from the variable frequency divider as a clock, and determining a division ratio for the variable frequency divider on a basis of the output from the flip-flop circuit. <EOS>