A nonvolatile memory device comprising: a memory cell array including memory blocks, wherein each of the memory blocks includes pages each including memory cells, each memory cell comprising a respective transistor including a control gate and a floating gate; a row decoder circuit configured to select one of the pages from a selected memory block of the memory blocks in a write operation and to select memory cells of a close unit from the selected memory block in a close operation; and a page buffer circuit configured to write data into memory cells of a page selected by the row decoder circuit in the write operation and to write dummy data into the memory cells of the close unit selected by the row decoder circuit in the close operation, wherein the close unit includes one or more pages, and wherein, in the close operation: dummy data is written in memory cells, into which data has not previously been written, from among memory cells of the selected memory block, such that data or dummy data is stored in each of the cells of the memory block; and the row decoder circuit is further configured to adjust a size of the close unit such that the close unit has a first size when writing dummy data into first memory cells of the selected memory block and a second size upon writing dummy data into second memory cells of the selected memory block, the second size being different to the first size, wherein the first and second sizes depend on whether the first and second memory cells used for the writing of the dummy data are adjacent to memory cells into which data has previously been written, and wherein after the close operation is completed no additional data may be written in the selected memory block. a memory cell array including memory blocks, wherein each of the memory blocks includes pages each including memory cells, each memory cell comprising a respective transistor including a control gate and a floating gate; a row decoder circuit configured to select one of the pages from a selected memory block of the memory blocks in a write operation and to select memory cells of a close unit from the selected memory block in a close operation; and a page buffer circuit configured to write data into memory cells of a page selected by the row decoder circuit in the write operation and to write dummy data into the memory cells of the close unit selected by the row decoder circuit in the close operation, wherein the close unit includes one or more pages, and wherein, in the close operation: dummy data is written in memory cells, into which data has not previously been written, from among memory cells of the selected memory block, such that data or dummy data is stored in each of the cells of the memory block; and the row decoder circuit is further configured to adjust a size of the close unit such that the close unit has a first size when writing dummy data into first memory cells of the selected memory block and a second size upon writing dummy data into second memory cells of the selected memory block, the second size being different to the first size, dummy data is written in memory cells, into which data has not previously been written, from among memory cells of the selected memory block, such that data or dummy data is stored in each of the cells of the memory block; and the row decoder circuit is further configured to adjust a size of the close unit such that the close unit has a first size when writing dummy data into first memory cells of the selected memory block and a second size upon writing dummy data into second memory cells of the selected memory block, the second size being different to the first size, wherein the first and second sizes depend on whether the first and second memory cells used for the writing of the dummy data are adjacent to memory cells into which data has previously been written, and wherein after the close operation is completed no additional data may be written in the selected memory block. <EOS>