A memory device comprising: a non-volatile memory ; and circuitry, configured to: initialize and prepare the non-volatile memory for executing memory-access operations for a processor ; and ascertain that no memory-access operations are received from the processor before the non-volatile memory is ready, by preventing the processor from bootstrapping during initialization of the non-volatile memory , wherein the non-volatile memory is configured to store a boot code of the processor , wherein the circuitry is configured to prevent the processor from bootstrapping, and wherein the circuitry includes an initialization circuit configured to signal that the memory device is ready when a initialization sequence is completed, a stall-code unit configured to output a computer instruction that will cause the processor to stall, a bus over which the memory device communicates with the processor , and a multiplexor coupled to the non-volatile memory , the initialization circuit , the stall-code unit and the bus , the multiplexor being configured to route to bus data that the stall-code unit outputs when the initialization circuit indicates that the memory device is not ready, or data that the non-volatile memory outputs when the initialization circuit indicates that the memory device is ready, wherein during the initialization of the non-volatile memory , responding to a request from the processor for the boot code by providing an alternative code that prevents the processor from bootstrapping; and after the initialization of the non-volatile memory , responding to a subsequent request from the processor for the boot code by providing the boot code, characterized by the alternative code causing the processor to repeatedly loop by causing the processor to continue reading an instruction from a same location indefinitely until the initialization of the non-volatile memory is complete. a non-volatile memory ; and circuitry, configured to: initialize and prepare the non-volatile memory for executing memory-access operations for a processor ; and ascertain that no memory-access operations are received from the processor before the non-volatile memory is ready, by preventing the processor from bootstrapping during initialization of the non-volatile memory , initialize and prepare the non-volatile memory for executing memory-access operations for a processor ; and ascertain that no memory-access operations are received from the processor before the non-volatile memory is ready, by preventing the processor from bootstrapping during initialization of the non-volatile memory , wherein the non-volatile memory is configured to store a boot code of the processor , wherein the circuitry is configured to prevent the processor from bootstrapping, and wherein the circuitry includes an initialization circuit configured to signal that the memory device is ready when a initialization sequence is completed, a stall-code unit configured to output a computer instruction that will cause the processor to stall, a bus over which the memory device communicates with the processor , and a multiplexor coupled to the non-volatile memory , the initialization circuit , the stall-code unit and the bus , the multiplexor being configured to route to bus data that the stall-code unit outputs when the initialization circuit indicates that the memory device is not ready, or data that the non-volatile memory outputs when the initialization circuit indicates that the memory device is ready, wherein during the initialization of the non-volatile memory , responding to a request from the processor for the boot code by providing an alternative code that prevents the processor from bootstrapping; and after the initialization of the non-volatile memory , responding to a subsequent request from the processor for the boot code by providing the boot code, <EOS>