A method for caching memory, comprising: caching, in a cache line of a cache memory for accessing a physical memory area connected to at least one hardware processor , the cache memory comprising a plurality of cache lines (150-0, 150-i and 150-m) each having a cache line amount of bits, at least two data values, where each data value is of one of at least two ranges of application memory addresses, wherein each range of application memory addresses is associated with one of a set of execution threads having an identified order of threads and executed by the at least one hardware processor, by: organizing a plurality of sequences of consecutive address sub-ranges (110, 111, 112 and 113), each sequence associated with one of the set of execution threads and consisting of a consecutive sequence of application memory address sub-ranges (110A, 110B, 110C and 110D) of the respective range of application memory addresses associated with the execution thread, each application memory address sub-range having an identified amount of memory bits less than the amount of cache line bits, in an interleaved sequence of address sub-ranges by alternately selecting, for each execution thread in the identified order of threads, a next address sub-range in the respective sequence of address sub-ranges associated therewith; generating a mapping of the interleaved sequence of address sub-ranges to a range of physical memory addresses in order of the interleaved sequence of address sub-ranges; and when an execution thread of the set of execution threads accesses an application memory address of the respective range of application memory addresses associated thereof: computing a target memory address according to the mapping using the application memory address; and storing the at least two data values in one cache line of the plurality of cache lines by accessing the physical memory area using the target memory address. organizing a plurality of sequences of consecutive address sub-ranges (110, 111, 112 and 113), each sequence associated with one of the set of execution threads and consisting of a consecutive sequence of application memory address sub-ranges (110A, 110B, 110C and 110D) of the respective range of application memory addresses associated with the execution thread, each application memory address sub-range having an identified amount of memory bits less than the amount of cache line bits, in an interleaved sequence of address sub-ranges by alternately selecting, for each execution thread in the identified order of threads, a next address sub-range in the respective sequence of address sub-ranges associated therewith; generating a mapping of the interleaved sequence of address sub-ranges to a range of physical memory addresses in order of the interleaved sequence of address sub-ranges; and when an execution thread of the set of execution threads accesses an application memory address of the respective range of application memory addresses associated thereof: computing a target memory address according to the mapping using the application memory address; and storing the at least two data values in one cache line of the plurality of cache lines by accessing the physical memory area using the target memory address. computing a target memory address according to the mapping using the application memory address; and storing the at least two data values in one cache line of the plurality of cache lines by accessing the physical memory area using the target memory address. <EOS>