A method for a power efficient generation of supply voltages and currents in an integrated circuit comprising core analog circuit blocks by reducing the power consumption of all said core analog circuit blocks, comprising the following steps: providing an integrated circuit comprising analog blocks generating one or more internal reference voltages wherein the analog blocks comprise a low drop-out (LDO) regulator, one or more internal supply voltages, and one or more biasing currents, a pulsed mode control logic block , and one or more external capacitors (CF1, CF2); operating all analog blocks of the circuit in pulsed mode; characterized in that it further comprises : accelerate recharge of internal nodes and the external capacitors by a top-up buffer , which is connected to an output of a band gap buffer, in order to reduce an ON-time of the analog blocks wherein the band gap buffer is isolated from an external capacitance (CF2) during ON-time by a switch (S3); introducing dynamic control of commutating components ensuring least disturbances of the voltage potentials of the circuit in order to minimize the ON-time of the analog blocks, wherein dynamic control comprises limiting the ON-time of the analog blocks to the time required for re-charging and settling of the internal voltages of the analog blocks to their nominal values; bypassing the LDO regulator in regard of said dynamic control by permanently disabling the LDO during pulsed mode operation and maintaining the voltage level of an internal VLDO supply rail by a faster combination comprising a comparator (BPC) and a drive transistor (M BP ); and maintaining voltage levels in the circuit by charge holding capacitors (C1, C2, C3, C4) during OFF periods of the pulsed mode. providing an integrated circuit comprising analog blocks generating one or more internal reference voltages wherein the analog blocks comprise a low drop-out (LDO) regulator, one or more internal supply voltages, and one or more biasing currents, a pulsed mode control logic block , and one or more external capacitors (CF1, CF2); operating all analog blocks of the circuit in pulsed mode; accelerate recharge of internal nodes and the external capacitors by a top-up buffer , which is connected to an output of a band gap buffer, in order to reduce an ON-time of the analog blocks wherein the band gap buffer is isolated from an external capacitance (CF2) during ON-time by a switch (S3); introducing dynamic control of commutating components ensuring least disturbances of the voltage potentials of the circuit in order to minimize the ON-time of the analog blocks, wherein dynamic control comprises limiting the ON-time of the analog blocks to the time required for re-charging and settling of the internal voltages of the analog blocks to their nominal values; bypassing the LDO regulator in regard of said dynamic control by permanently disabling the LDO during pulsed mode operation and maintaining the voltage level of an internal VLDO supply rail by a faster combination comprising a comparator (BPC) and a drive transistor (M BP ); and maintaining voltage levels in the circuit by charge holding capacitors (C1, C2, C3, C4) during OFF periods of the pulsed mode. <EOS>