A frequency determination device for determining a frequency relationship between a reference signal (109; 309) and a clock signal (110; 310), the frequency determination device comprising: a plurality of constituent time-to-digital converters, TDC:s, (101, 102, 103; 200; 301, 302, 303, 304, 308), wherein each constituent TDC is configured to provide a digitally represented constituent output signal (131, 132, 133; 232; 331, 332, 333, 334, 338) in response to receiving a constituent reference signal (181, 182, 183; 282; 381, 382, 383, 384, 388) and a constituent clock signal (171, 172, 173; 210; 371, 372, 373, 374, 378), and wherein the frequency determination device is configured to successively provide respectively delayed versions of the constituent clock signal (171; 210; 378) of a first constituent TDC as respective constituent clock signals (172, 173; 210; 374, 373, 372, 371) to the other constituent TDC:s (102, 103; 304, 303, 302, 301); a reference signal provider (120; 320) configured to provide the respective constituent reference signals (181, 182, 183; 282; 381, 382, 383, 384, 388) to each of the constituent TDC:s (101, 102, 103; 200; 301, 302, 303, 304, 308), wherein each respective constituent reference signal comprises a delayed version of the reference signal (109; 309); switching circuitry (191, 156; 398, 356) configured to provide the reference signal (109; 309) as the constituent clock signal (171; 378) to the first constituent TDC (101; 308) during a first stage, and to provide the clock signal (110; 310) as the constituent clock signal (171; 378) to the first constituent TDC (101; 308) during a second stage; and determination circuitry (150; 350) configured to determine a number of consecutively same-valued symbols in a concatenation of the digitally represented constituent output signals (131, 132, 133; 232; 331, 332, 333, 334, 338) of the constituent TDC:s, and to determine the frequency relationship (199; 399) based on the number determined during the first stage and the number determined during the second stage. a plurality of constituent time-to-digital converters, TDC:s, (101, 102, 103; 200; 301, 302, 303, 304, 308), wherein each constituent TDC is configured to provide a digitally represented constituent output signal (131, 132, 133; 232; 331, 332, 333, 334, 338) in response to receiving a constituent reference signal (181, 182, 183; 282; 381, 382, 383, 384, 388) and a constituent clock signal (171, 172, 173; 210; 371, 372, 373, 374, 378), and wherein the frequency determination device is configured to successively provide respectively delayed versions of the constituent clock signal (171; 210; 378) of a first constituent TDC as respective constituent clock signals (172, 173; 210; 374, 373, 372, 371) to the other constituent TDC:s (102, 103; 304, 303, 302, 301); a reference signal provider (120; 320) configured to provide the respective constituent reference signals (181, 182, 183; 282; 381, 382, 383, 384, 388) to each of the constituent TDC:s (101, 102, 103; 200; 301, 302, 303, 304, 308), wherein each respective constituent reference signal comprises a delayed version of the reference signal (109; 309); switching circuitry (191, 156; 398, 356) configured to provide the reference signal (109; 309) as the constituent clock signal (171; 378) to the first constituent TDC (101; 308) during a first stage, and to provide the clock signal (110; 310) as the constituent clock signal (171; 378) to the first constituent TDC (101; 308) during a second stage; and determination circuitry (150; 350) configured to determine a number of consecutively same-valued symbols in a concatenation of the digitally represented constituent output signals (131, 132, 133; 232; 331, 332, 333, 334, 338) of the constituent TDC:s, and to determine the frequency relationship (199; 399) based on the number determined during the first stage and the number determined during the second stage. <EOS>