A system configured to facilitate operation of a processor with any of multiple memory devices each corresponding to a different respective set of signal, the system comprising: a printed circuit board, PCB, ; a first hardware, HW, interface disposed in or on the PCB , the first HW interface to couple to any of memory devices each corresponding to a different respective set of signals of multiple sets of signals; a second HW interface disposed in or on the PCB ; a processor device coupled to the PCB via the second HW interface , the processor device to detect connectivity of a memory device (130-136) to the first HW interface and to configure, based on a memory type of the memory device, a first interface mode of interface modes each corresponding to a different respective one of the multiple sets of signals; a voltage regulator, VR, coupled to the first HW interface , the VR to be programmed, based on the memory type, to a first VR mode of VR modes each corresponding to a different respective one of the memory devices, and to provide one or more voltages to the first interface based on the first VR mode; and an interconnect , disposed in or on the PCB , including x signal lines each coupling a respective input/output, I/O, contact of the first HW interface to a respective I/O contact of the second HW interface , wherein x is an integer equal to a total number of signals of a superset of the multiple sets of signals characterized in that the processor device includes signal MUX circuitry to provide mappings of I/O contacts to a respective signal or voltage of an interface at the connection to HW interface ; wherein the MUX circuitry is configured at different times to any of different interface modes each corresponding to a different respective memory technology, where an interface mode provides a respective mapping to accommodate the corresponding memory technology. a printed circuit board, PCB, ; a first hardware, HW, interface disposed in or on the PCB , the first HW interface to couple to any of memory devices each corresponding to a different respective set of signals of multiple sets of signals; a second HW interface disposed in or on the PCB ; a processor device coupled to the PCB via the second HW interface , the processor device to detect connectivity of a memory device (130-136) to the first HW interface and to configure, based on a memory type of the memory device, a first interface mode of interface modes each corresponding to a different respective one of the multiple sets of signals; a voltage regulator, VR, coupled to the first HW interface , the VR to be programmed, based on the memory type, to a first VR mode of VR modes each corresponding to a different respective one of the memory devices, and to provide one or more voltages to the first interface based on the first VR mode; and an interconnect , disposed in or on the PCB , including x signal lines each coupling a respective input/output, I/O, contact of the first HW interface to a respective I/O contact of the second HW interface , wherein x is an integer equal to a total number of signals of a superset of the multiple sets of signals characterized in that the processor device includes signal MUX circuitry to provide mappings of I/O contacts to a respective signal or voltage of an interface at the connection to HW interface ; wherein the MUX circuitry is configured at different times to any of different interface modes each corresponding to a different respective memory technology, where an interface mode provides a respective mapping to accommodate the corresponding memory technology. <EOS>