A flip chip , comprising: a first set of pads , each pad of the first set of pads comprising: a first pad portion configured for only contact with one or more tips of a probe device during a testing before bumping on the pad of the first set of pads , and a second pad portion configured for only the bumping on the pad of the first set of pads without contact with the one or more tips during the testing; a second set of pads , each pad of the second set of pads configured for only bumping on the pad of the second set of pads after the testing; and a third set of pads , each pad of the third set of pads configured for only contact with one or more tips of the probe device during the testing, wherein the first pad portions and the pads of the third set of pads have probe marks but no solder bumps thereon, and the second pad portions and the pads of the second set of pads have solder bumps but no probe marks thereon, wherein the first set of pads are formed in first and second rows and a part of a third row in a first area of the flip chip that is proximate to an edge of the flip chip , the second set of pads are formed in a fourth row in a second area of the flip chip that is further from the edge than the first area, and the third set of pads are formed in a fifth row and another part of the third row in a third area of the flip chip between the first and second areas, wherein the first and second rows are proximate to the edge, wherein the fourth row is further from the edge than the first and second rows , and wherein the third row is disposed between the second row and the fifth row , and the fifth row is disposed between the third row and the fourth row . a first set of pads , each pad of the first set of pads comprising: a first pad portion configured for only contact with one or more tips of a probe device during a testing before bumping on the pad of the first set of pads , and a second pad portion configured for only the bumping on the pad of the first set of pads without contact with the one or more tips during the testing; a first pad portion configured for only contact with one or more tips of a probe device during a testing before bumping on the pad of the first set of pads , and a second pad portion configured for only the bumping on the pad of the first set of pads without contact with the one or more tips during the testing; a second set of pads , each pad of the second set of pads configured for only bumping on the pad of the second set of pads after the testing; and a third set of pads , each pad of the third set of pads configured for only contact with one or more tips of the probe device during the testing, wherein the first pad portions and the pads of the third set of pads have probe marks but no solder bumps thereon, and the second pad portions and the pads of the second set of pads have solder bumps but no probe marks thereon, wherein the first set of pads are formed in first and second rows and a part of a third row in a first area of the flip chip that is proximate to an edge of the flip chip , the second set of pads are formed in a fourth row in a second area of the flip chip that is further from the edge than the first area, and the third set of pads are formed in a fifth row and another part of the third row in a third area of the flip chip between the first and second areas, wherein the first and second rows are proximate to the edge, wherein the fourth row is further from the edge than the first and second rows , and wherein the third row is disposed between the second row and the fifth row , and the fifth row is disposed between the third row and the fourth row . <EOS>