An impedance circuit (BigR) for a charge pump arrangement comprising: - a first current mirror circuit (CM1) with a first bias (pbias) serving as a current input terminal, a first output (out1) serving as a current output terminal and a first input (in1) for coupling with a pre-selected potential, - a first charge pump (CP1) for biasing the first current mirror circuit (CM1) with a first reference current, wherein the first charge pump (CP1) comprises a first biasing output (bias1) coupled with the first bias (pbias) of the first current mirror circuit (CM1). - a second current mirror circuit (CM2) with a second bias (nbias) serving as a current input terminal, a second output (out2) serving as a current output terminal and a second input (in2) for coupling with the pre-selected potential, - a second charge pump (CP2) for biasing the second current mirror circuit (CM2) with a second reference current, wherein the second charge pump (CP2) comprises a second biasing output (bias2) coupled with the second bias (nbias) of the second current mirror circuit (CM2), wherein the impedance circuit (BigR) comprises a device input and a device output, the first output (out1) of the first current mirror circuit (CM1) and the second output (out2) of the second current mirror circuit (CM2) being coupled with the device output, and the first input (in1) of the first current mirror circuit (CM1) and the second input (in2) of the second current mirror circuit (CM2) being coupled with the device input and wherein the first current mirror (CM1) and the second current mirror (CM2) are coupled anti-parallel and provide two sub-paths. - a first current mirror circuit (CM1) with a first bias (pbias) serving as a current input terminal, a first output (out1) serving as a current output terminal and a first input (in1) for coupling with a pre-selected potential, - a first charge pump (CP1) for biasing the first current mirror circuit (CM1) with a first reference current, wherein the first charge pump (CP1) comprises a first biasing output (bias1) coupled with the first bias (pbias) of the first current mirror circuit (CM1). - a second current mirror circuit (CM2) with a second bias (nbias) serving as a current input terminal, a second output (out2) serving as a current output terminal and a second input (in2) for coupling with the pre-selected potential, - a second charge pump (CP2) for biasing the second current mirror circuit (CM2) with a second reference current, wherein the second charge pump (CP2) comprises a second biasing output (bias2) coupled with the second bias (nbias) of the second current mirror circuit (CM2), wherein the impedance circuit (BigR) comprises a device input and a device output, the first output (out1) of the first current mirror circuit (CM1) and the second output (out2) of the second current mirror circuit (CM2) being coupled with the device output, and the first input (in1) of the first current mirror circuit (CM1) and the second input (in2) of the second current mirror circuit (CM2) being coupled with the device input and wherein the first current mirror (CM1) and the second current mirror (CM2) are coupled anti-parallel and provide two sub-paths. <EOS>