An electronic system , comprising: a processing sub-system configured to execute a program using a set of virtual memory addresses to reference memory locations for storage of variables of the program ; a programmable logic sub-system configured to implement a set of circuits specified in a configuration data stream, the set of circuits including a plurality of input/output circuits , each input/output circuit having a respective identifier (ID) and configured to access a respective one of the variables; a memory ; a memory management circuit configured to: map the set of virtual memory addresses to physical memory addresses of the memory ; and for each of the plurality of input/output circuits that accesses the respective one of the variables of the program , map the respective ID of the input/output circuit to the physical memory address that corresponds to the respective one of the variables; at least one translation look-aside buffer, TLB , coupled to at least one input/output circuit of the plurality of input/output circuits , the at least one translation look-aside buffer configured to determine, in response to receiving a memory access request indicating an ID, a physical memory address that is mapped to the ID indicated in the memory access request and to provide to the memory a memory access request indicating the physical memory address that is mapped to the ID; and wherein the set of circuits implemented by the programmable logic sub-system includes the at least one TLB . a processing sub-system configured to execute a program using a set of virtual memory addresses to reference memory locations for storage of variables of the program ; a programmable logic sub-system configured to implement a set of circuits specified in a configuration data stream, the set of circuits including a plurality of input/output circuits , each input/output circuit having a respective identifier (ID) and configured to access a respective one of the variables; a memory ; a memory management circuit configured to: map the set of virtual memory addresses to physical memory addresses of the memory ; and for each of the plurality of input/output circuits that accesses the respective one of the variables of the program , map the respective ID of the input/output circuit to the physical memory address that corresponds to the respective one of the variables; map the set of virtual memory addresses to physical memory addresses of the memory ; and for each of the plurality of input/output circuits that accesses the respective one of the variables of the program , map the respective ID of the input/output circuit to the physical memory address that corresponds to the respective one of the variables; at least one translation look-aside buffer, TLB , coupled to at least one input/output circuit of the plurality of input/output circuits , the at least one translation look-aside buffer configured to determine, in response to receiving a memory access request indicating an ID, a physical memory address that is mapped to the ID indicated in the memory access request and to provide to the memory a memory access request indicating the physical memory address that is mapped to the ID; and wherein the set of circuits implemented by the programmable logic sub-system includes the at least one TLB . <EOS>