An electronic cryptographic device arranged to perform a cryptographic operation on input data obtaining output data , the cryptographic device comprising - an input interface arranged to receive the input data, - a memory arranged to store an internal state , the internal state comprising one or more data elements , each data element being represented in the memory as a corresponding set of shares , a set of shares in the memory having a corresponding set of Fourier coefficients according to a discrete Fourier transform in a finite field, a predetermined relationship being satisfied among the sets of Fourier coefficients corresponding to the sets of shares in the memory, - a processor circuit configured to - perform the cryptographic operation by repeatedly updating the internal state, an initial internal state being derived from the input data, the output data being derived from a final internal state, wherein, if the predetermined relationship is satisfied among the set of Fourier coefficients corresponding to the share sets of the internal state, then the predetermined relationship is satisfied among an updated set of Fourier coefficients corresponding to the share sets of the updated internal state, - apply an output operator to the final internal state to derive the output data, the output operator mapping a set of shares to the data element it represents plus a distortion, wherein the distortion is zero if the Fourier coefficients of the set of shares satisfy the predetermined relationship, and said distortion depends on the Fourier coefficients of the set of shares. - an input interface arranged to receive the input data, - a memory arranged to store an internal state , the internal state comprising one or more data elements , each data element being represented in the memory as a corresponding set of shares , a set of shares in the memory having a corresponding set of Fourier coefficients according to a discrete Fourier transform in a finite field, a predetermined relationship being satisfied among the sets of Fourier coefficients corresponding to the sets of shares in the memory, - a processor circuit configured to - perform the cryptographic operation by repeatedly updating the internal state, an initial internal state being derived from the input data, the output data being derived from a final internal state, wherein, if the predetermined relationship is satisfied among the set of Fourier coefficients corresponding to the share sets of the internal state, then the predetermined relationship is satisfied among an updated set of Fourier coefficients corresponding to the share sets of the updated internal state, - apply an output operator to the final internal state to derive the output data, the output operator mapping a set of shares to the data element it represents plus a distortion, wherein the distortion is zero if the Fourier coefficients of the set of shares satisfy the predetermined relationship, and said distortion depends on the Fourier coefficients of the set of shares. - perform the cryptographic operation by repeatedly updating the internal state, an initial internal state being derived from the input data, the output data being derived from a final internal state, wherein, if the predetermined relationship is satisfied among the set of Fourier coefficients corresponding to the share sets of the internal state, then the predetermined relationship is satisfied among an updated set of Fourier coefficients corresponding to the share sets of the updated internal state, - apply an output operator to the final internal state to derive the output data, the output operator mapping a set of shares to the data element it represents plus a distortion, wherein the distortion is zero if the Fourier coefficients of the set of shares satisfy the predetermined relationship, and said distortion depends on the Fourier coefficients of the set of shares. <EOS>