An ink-jet head driving circuit comprising: a first PMOS transistor (31 ) including a first drain terminal, a first source terminal and a first Nwell area, the first drain terminal being connected to a piezoelectric element for jetting ink from a nozzle; a second PMOS transistor (31(n-1)) including a second drain terminal, a second source terminal and a second Nwell area, the second drain terminal being connected to the piezoelectric element ; a third PMOS transistor (31(n)) including a third drain terminal, a third source terminal and a third Nwell area, the third drain terminal being connected to the piezoelectric element ; and an NMOS transistor including a drain terminal and a source terminal, the drain terminal being connected to the first drain terminal of the first PMOS transistor, the second drain terminal of the second PMOS transistor and the third drain terminal of the third PMOS transistor, wherein the first source terminal of the first PMOS transistor is connected to a first power source, the second source terminal of the second PMOS transistor is connected to a second power source, the voltage of a second power source (VDD2-n-1) being higher than voltage of the first power source (VDD 2-1), the third source terminal of the third PMOS transistor is connected to a third power source, the voltage of the third power source (VDD2-n) being higher than voltage of the second power source (VDD2-n-1), the first Nwell area of the first PMOS transistor, the second Nwell area of the second PMOS transistor and the third Nwell area of the third PMOS transistor are connected to the third power source, and voltage difference between the voltages of the third and second power sources is larger than voltage difference between the voltages of the second and first power sources. a first PMOS transistor (31 ) including a first drain terminal, a first source terminal and a first Nwell area, the first drain terminal being connected to a piezoelectric element for jetting ink from a nozzle; a second PMOS transistor (31(n-1)) including a second drain terminal, a second source terminal and a second Nwell area, the second drain terminal being connected to the piezoelectric element ; a third PMOS transistor (31(n)) including a third drain terminal, a third source terminal and a third Nwell area, the third drain terminal being connected to the piezoelectric element ; and an NMOS transistor including a drain terminal and a source terminal, the drain terminal being connected to the first drain terminal of the first PMOS transistor, the second drain terminal of the second PMOS transistor and the third drain terminal of the third PMOS transistor, wherein the first source terminal of the first PMOS transistor is connected to a first power source, the second source terminal of the second PMOS transistor is connected to a second power source, the voltage of a second power source (VDD2-n-1) being higher than voltage of the first power source (VDD 2-1), the third source terminal of the third PMOS transistor is connected to a third power source, the voltage of the third power source (VDD2-n) being higher than voltage of the second power source (VDD2-n-1), the first Nwell area of the first PMOS transistor, the second Nwell area of the second PMOS transistor and the third Nwell area of the third PMOS transistor are connected to the third power source, and voltage difference between the voltages of the third and second power sources is larger than voltage difference between the voltages of the second and first power sources. <EOS>