A method to provide a vertical device patterning, comprising: forming a grid comprising a first set of grid lines and a second set of grid lines crossing each other in a regular pattern on a substrate using a first deep ultraviolet, DUV, lithography process; depositing a spacer adjacent to sidewalls of the first and second set of grid lines ; depositing a device hard mask through openings adjacent to the sidewalls of the spacer on exposed portions of the substrate ; selectively removing the spacer ; depositing a first sacrificial hard mask layer ; patterning the first sacrificial hard mask layer to expose a portion of the device hard mask; removing the exposed portions of the device hard mask and first sacrificial hard mask layer ; depositing a second sacrificial hard mask layer over the first and second set of grid lines and the device hard mask ; patterning the second sacrificial hard mask layer to expose portions of the grid lines ; removing the exposed portions of the first grid lines and the second sacrificial hard mark layer ;forming trenches in the substrate by using portions of the device hard mask and remaining grid lines as a mask; depositing a gate stack in the trenches; removing the remaining grid lines ; depositing a gate barrier into spaces of removed grid lines ; removing the remaining device hard mask ; depositing a third sacrificial hard mask layer ; patterning the third sacrificial hard mask layer to form openings to expose vertical features formed on the substrate; removing the third sacrificial hard mask layer ; removing the vertical features with adjacent gate dielectric portions; and filling the openings with conductive layers to form vias. forming a grid comprising a first set of grid lines and a second set of grid lines crossing each other in a regular pattern on a substrate using a first deep ultraviolet, DUV, lithography process; depositing a spacer adjacent to sidewalls of the first and second set of grid lines ; depositing a device hard mask through openings adjacent to the sidewalls of the spacer on exposed portions of the substrate ; selectively removing the spacer ; depositing a first sacrificial hard mask layer ; patterning the first sacrificial hard mask layer to expose a portion of the device hard mask; removing the exposed portions of the device hard mask and first sacrificial hard mask layer ; depositing a second sacrificial hard mask layer over the first and second set of grid lines and the device hard mask ; patterning the second sacrificial hard mask layer to expose portions of the grid lines ; removing the exposed portions of the first grid lines and the second sacrificial hard mark layer ;forming trenches in the substrate by using portions of the device hard mask and remaining grid lines as a mask; depositing a gate stack in the trenches; removing the remaining grid lines ; depositing a gate barrier into spaces of removed grid lines ; removing the remaining device hard mask ; depositing a third sacrificial hard mask layer ; patterning the third sacrificial hard mask layer to form openings to expose vertical features formed on the substrate; removing the third sacrificial hard mask layer ; removing the vertical features with adjacent gate dielectric portions; and filling the openings with conductive layers to form vias. <EOS>