A display device comprising: a base layer (BSL); a pixel circuit layer (PCL) located over the base layer (BSL); the pixel circuit layer (PCL) comprises: a transistor (T1) located over the base layer (BSL), the transistor (T1) comprising: an active layer (ACT); a gate electrode (GAT); a first electrode (TE1); and a second electrode (TE2); and a passivation layer (PSV) covering the transistor (T1); a first electrode (EL1) located over the passivation layer (PSV) of the pixel circuit layer (PCL), the first electrode (EL1) is electrically connected to the second electrode (TE2) of the transistor (T1) through a contact hole (CH1) of the passivation layer (PSV); a bank (BNK) located over the passivation layer (PSV) of the pixel circuit layer (PCL); a light emitting element (LD) comprising a coupling electrode layer located over the first electrode (EL1); an insulating layer (INS) disposed between the light emitting element (LD) and the bank (BNK) and exposing an upper surface of the light emitting element (LD); the insulating layer (INS) located over the passivation layer (PSV) and the first electrode (EL1); and the insulating layer (INS) overlaps at least a portion of the passivation layer (PSV) and the first electrode (EL1); and a second electrode (EL2) located over the light emitting element (LD), wherein the first electrode (EL1) and the bank (BNK) are spaced apart from each other and characterized in that the second electrode (EL2) entirely overlaps the insulating layer (INS) and also directly contacts and entirely overlaps in a cross-sectional view the upper surface of the light emitting element (LD). a base layer (BSL); a pixel circuit layer (PCL) located over the base layer (BSL); the pixel circuit layer (PCL) comprises: a transistor (T1) located over the base layer (BSL), the transistor (T1) comprising: an active layer (ACT); a gate electrode (GAT); a first electrode (TE1); and a second electrode (TE2); and a passivation layer (PSV) covering the transistor (T1); a transistor (T1) located over the base layer (BSL), the transistor (T1) comprising: an active layer (ACT); a gate electrode (GAT); a first electrode (TE1); and a second electrode (TE2); and an active layer (ACT); a gate electrode (GAT); a first electrode (TE1); and a second electrode (TE2); and a passivation layer (PSV) covering the transistor (T1); a first electrode (EL1) located over the passivation layer (PSV) of the pixel circuit layer (PCL), the first electrode (EL1) is electrically connected to the second electrode (TE2) of the transistor (T1) through a contact hole (CH1) of the passivation layer (PSV); a bank (BNK) located over the passivation layer (PSV) of the pixel circuit layer (PCL); a light emitting element (LD) comprising a coupling electrode layer located over the first electrode (EL1); an insulating layer (INS) disposed between the light emitting element (LD) and the bank (BNK) and exposing an upper surface of the light emitting element (LD); the insulating layer (INS) located over the passivation layer (PSV) and the first electrode (EL1); and the insulating layer (INS) overlaps at least a portion of the passivation layer (PSV) and the first electrode (EL1); and a second electrode (EL2) located over the light emitting element (LD), wherein the first electrode (EL1) and the bank (BNK) are spaced apart from each other and characterized in that the second electrode (EL2) entirely overlaps the insulating layer (INS) and also directly contacts and entirely overlaps in a cross-sectional view the upper surface of the light emitting element (LD). <EOS>