A current limiting control method for a three-level inverter which comprises an I-type three-level inverter or a T-type three-level inverter, wherein the three-level inverter at least comprises a bridge arm including four switch transistors, the four switch transistors comprising main switch transistors (Q1, Q4) and auxiliary switch transistors (Q2, Q3), wherein each main switch transistor (Q1, Q4) is configured to connect an output of the three-level inverter to a positive bus or to a negative bus, and each auxiliary switch transistor (Q2, Q3) is configured to connect the output of the three-level inverter to a neutral point between the positive bus and the negative bus, wherein the method comprises the following steps: S1. when a current output from the bridge arm is greater than or equal to a current limiting threshold and a received overcurrent signal is enabled, first turning off the main switch transistors (Q1, Q4) and then turning off the auxiliary switch transistors (Q2, Q3); S2. when the current output from the bridge arm drops to lower than the current limiting threshold and the received overcurrent signal is disabled, turning on the auxiliary switch transistors (Q2, Q3); S3. when the received overcurrent signal is disabled and a next PWM effective edge of the main switch transistors (Q1, Q4) arrives, turning on the main switch transistors (Q1, Q4), characterized in that the step S2 further comprises: S21. when the current output from the bridge arm drops to lower than the current limiting threshold and the received overcurrent signal is disabled, turning on the auxiliary switch transistors (Q2, Q3) after elapse of a first delay time; S22. when the current output from the bridge arms rises to greater than or equal to the current limiting threshold and the received overcurrent signal is enabled, again turning off the auxiliary switch transistors (Q2, Q3) and no longer turning on the auxiliary switch transistors (Q2, Q3) within this switching cycle. S1. when a current output from the bridge arm is greater than or equal to a current limiting threshold and a received overcurrent signal is enabled, first turning off the main switch transistors (Q1, Q4) and then turning off the auxiliary switch transistors (Q2, Q3); S2. when the current output from the bridge arm drops to lower than the current limiting threshold and the received overcurrent signal is disabled, turning on the auxiliary switch transistors (Q2, Q3); S3. when the received overcurrent signal is disabled and a next PWM effective edge of the main switch transistors (Q1, Q4) arrives, turning on the main switch transistors (Q1, Q4), characterized in that the step S2 further comprises: S21. when the current output from the bridge arm drops to lower than the current limiting threshold and the received overcurrent signal is disabled, turning on the auxiliary switch transistors (Q2, Q3) after elapse of a first delay time; S22. when the current output from the bridge arms rises to greater than or equal to the current limiting threshold and the received overcurrent signal is enabled, again turning off the auxiliary switch transistors (Q2, Q3) and no longer turning on the auxiliary switch transistors (Q2, Q3) within this switching cycle. S21. when the current output from the bridge arm drops to lower than the current limiting threshold and the received overcurrent signal is disabled, turning on the auxiliary switch transistors (Q2, Q3) after elapse of a first delay time; S22. when the current output from the bridge arms rises to greater than or equal to the current limiting threshold and the received overcurrent signal is enabled, again turning off the auxiliary switch transistors (Q2, Q3) and no longer turning on the auxiliary switch transistors (Q2, Q3) within this switching cycle. <EOS>