A processor comprising: a decode unit to decode an instruction, wherein the instruction is an SM3 two round state word update instruction , the SM3 two round state word update instruction to indicate one or more source packed data operands and a round number, the one or more source packed data operands to have eight 32-bit state words A j , B j , C j , D j , E j , F j , G j , and H j that are to correspond to a round, j, of an SM3 hash algorithm, and the one or more source packed data operands to have a set of messages that are sufficient to evaluate two rounds of the SM3 hash algorithm; and an execution unit coupled with the decode unit, the execution unit operable, in response to the SM3 two round state word update instruction, to: generate one or more result packed data operands ; and store the one or more result packed data operands, in one or more destination storage locations that are to be indicated by the SM3 two round state word update instruction, the one or more result packed data operands to have at least four two-round updated 32-bit state words A j+2 , B j+2 , E j+2 , and F j+2 that are to correspond to a round, j+2, of the SM3 hash algorithm, wherein the SM3 two round state word update instruction has a source/destination operand that is initially to store a source packed data operand having the C j , D j , G j , and H j but not the A j , B j , E j , and F j and where a result packed data operand having the A j+2 , B j+2 , E j+2 , and F j+2 is to be stored. a decode unit to decode an instruction, wherein the instruction is an SM3 two round state word update instruction , the SM3 two round state word update instruction to indicate one or more source packed data operands and a round number, the one or more source packed data operands to have eight 32-bit state words A j , B j , C j , D j , E j , F j , G j , and H j that are to correspond to a round, j, of an SM3 hash algorithm, and the one or more source packed data operands to have a set of messages that are sufficient to evaluate two rounds of the SM3 hash algorithm; and an execution unit coupled with the decode unit, the execution unit operable, in response to the SM3 two round state word update instruction, to: generate one or more result packed data operands ; and store the one or more result packed data operands, in one or more destination storage locations that are to be indicated by the SM3 two round state word update instruction, the one or more result packed data operands to have at least four two-round updated 32-bit state words A j+2 , B j+2 , E j+2 , and F j+2 that are to correspond to a round, j+2, of the SM3 hash algorithm, wherein the SM3 two round state word update instruction has a source/destination operand that is initially to store a source packed data operand having the C j , D j , G j , and H j but not the A j , B j , E j , and F j and where a result packed data operand having the A j+2 , B j+2 , E j+2 , and F j+2 is to be stored. generate one or more result packed data operands ; and store the one or more result packed data operands, in one or more destination storage locations that are to be indicated by the SM3 two round state word update instruction, the one or more result packed data operands to have at least four two-round updated 32-bit state words A j+2 , B j+2 , E j+2 , and F j+2 that are to correspond to a round, j+2, of the SM3 hash algorithm, wherein the SM3 two round state word update instruction has a source/destination operand that is initially to store a source packed data operand having the C j , D j , G j , and H j but not the A j , B j , E j , and F j and where a result packed data operand having the A j+2 , B j+2 , E j+2 , and F j+2 is to be stored. <EOS>