A method of forming a semiconductor device, comprising: providing a substrate that includes silicon , a first insulation layer directly over the silicon, and a silicon layer directly over the first insulation layer; epitaxially growing silicon on the silicon layer in a first area of the substrate and not in a second area of the substrate such that the silicon layer is thicker in the first area of the substrate relative to the second area of the substrate; forming memory cells in the first area of the substrate, wherein the forming of each of the memory cells includes: forming spaced apart first source and first drain regions in the silicon layer in the first area of the substrate, defining a channel region there between, forming a floating gate over and insulated from a first portion of the channel region, and forming a select gate over and insulated from a second portion of the channel region; forming logic devices in the second area of the substrate, wherein the forming of each of the logic devices includes: forming spaced apart second source and second drain regions in the silicon layer in the second area of the substrate, and forming a conductive gate over and insulated from a portion of the silicon layer between the second source and second drain regions; wherein the first source and first drain regions extend deeper into the silicon layer than do the second source and second drain regions, and wherein the first source and first drain regions each have a breakdown voltage in the silicon layer that is greater than that of each of the second source and second drain regions in the silicon layer. providing a substrate that includes silicon , a first insulation layer directly over the silicon, and a silicon layer directly over the first insulation layer; epitaxially growing silicon on the silicon layer in a first area of the substrate and not in a second area of the substrate such that the silicon layer is thicker in the first area of the substrate relative to the second area of the substrate; forming memory cells in the first area of the substrate, wherein the forming of each of the memory cells includes: forming spaced apart first source and first drain regions in the silicon layer in the first area of the substrate, defining a channel region there between, forming a floating gate over and insulated from a first portion of the channel region, and forming a select gate over and insulated from a second portion of the channel region; forming spaced apart first source and first drain regions in the silicon layer in the first area of the substrate, defining a channel region there between, forming a floating gate over and insulated from a first portion of the channel region, and forming a select gate over and insulated from a second portion of the channel region; forming logic devices in the second area of the substrate, wherein the forming of each of the logic devices includes: forming spaced apart second source and second drain regions in the silicon layer in the second area of the substrate, and forming a conductive gate over and insulated from a portion of the silicon layer between the second source and second drain regions; forming spaced apart second source and second drain regions in the silicon layer in the second area of the substrate, and forming a conductive gate over and insulated from a portion of the silicon layer between the second source and second drain regions; wherein the first source and first drain regions extend deeper into the silicon layer than do the second source and second drain regions, and wherein the first source and first drain regions each have a breakdown voltage in the silicon layer that is greater than that of each of the second source and second drain regions in the silicon layer. <EOS>