An input stage of a chip, comprising: a variable resistor (R1, R2), wherein the variable resistor (R1, R2) has a first electrode and a second electrode, the first electrode is connected to a pad (N1, N2) of the chip , and wherein the variable resistor (R1, R2) is configured to directly receive an input signal coupled by means of a capacitor to the pad (N1, N2) of the chip to generate a first signal; and an amplifier with a variable feedback resistor (RFB1, RFB2), wherein an input terminal of the amplifier is coupled to the second electrode of the variable resistor (R1, R2), and wherein the amplifier is configured to amplify the first signal to generate an output signal (Von, Vop); wherein the variable resistor (R1, R2) is implemented by a first resistor switchably connected in parallel with a second resistor, and the variable feedback resistor (RFB1, RFB2) is implemented by a third resistor switchably connected in parallel with a fourth resistor wherein, in a first mode, the input stage is configured to switch the variable resistor (R1, R2) to have a first resistance, and to switch the variable feedback resistor (RFB1, RFB2) to have a second resistance, using a first control signal (Vc1, Vc2), wherein, in a second mode, the input stage is configured to switch the variable resistor (R1, R2) to have a third resistance greater than the first resistance, and to switch the variable feedback (RFB, RFB2) resistor to have a fourth resistance greater than the second resistance, using a second control signal (Vc1, Vc2), wherein the input stage of the chip is configured to initially operate in the first mode, when the input stage starts to process the input signal, and then operate in the second mode, and wherein the input stage is configured to detect glitches in the output signal (Von, Vop), and the input stage is configured to operate in the second mode when the glitches are reduced to a predetermined level. a variable resistor (R1, R2), wherein the variable resistor (R1, R2) has a first electrode and a second electrode, the first electrode is connected to a pad (N1, N2) of the chip , and wherein the variable resistor (R1, R2) is configured to directly receive an input signal coupled by means of a capacitor to the pad (N1, N2) of the chip to generate a first signal; and an amplifier with a variable feedback resistor (RFB1, RFB2), wherein an input terminal of the amplifier is coupled to the second electrode of the variable resistor (R1, R2), and wherein the amplifier is configured to amplify the first signal to generate an output signal (Von, Vop); wherein the variable resistor (R1, R2) is implemented by a first resistor switchably connected in parallel with a second resistor, and the variable feedback resistor (RFB1, RFB2) is implemented by a third resistor switchably connected in parallel with a fourth resistor wherein, in a first mode, the input stage is configured to switch the variable resistor (R1, R2) to have a first resistance, and to switch the variable feedback resistor (RFB1, RFB2) to have a second resistance, using a first control signal (Vc1, Vc2), wherein, in a second mode, the input stage is configured to switch the variable resistor (R1, R2) to have a third resistance greater than the first resistance, and to switch the variable feedback (RFB, RFB2) resistor to have a fourth resistance greater than the second resistance, using a second control signal (Vc1, Vc2), wherein the input stage of the chip is configured to initially operate in the first mode, when the input stage starts to process the input signal, and then operate in the second mode, and wherein the input stage is configured to detect glitches in the output signal (Von, Vop), and the input stage is configured to operate in the second mode when the glitches are reduced to a predetermined level. <EOS>