A semiconductor electronic device comprising: - a semiconductor body , having a first conductivity, delimited by a first side and a second side opposite to one another along an axis (Z); - a body region , having a second conductivity opposite to the first conductivity, in the semiconductor body facing the first side ; - a source terminal , having the first conductivity, extending at least in part in the body region ; - a drain terminal , having the first conductivity, extending at the second side of the semiconductor body ; and - a trench gate , which extends in the semiconductor body from the first side towards the second side , through the body region and the source region , wherein said trench gate includes a dielectric region of porous silicon oxide buried in the semiconductor body , and a gate conductive region extending between the dielectric region of porous silicon oxide and said first side , wherein a gate dielectric extends between the gate conductive region and the semiconductor body , characterized in that said trench gate , in addition to the gate dielectric , further includes a protection region between the dielectric region of porous silicon oxide and the gate conductive region , designed for separating the dielectric region of porous silicon oxide from the gate conductive region , said protection region being of a dielectric material or of an electrically insulating material, and has a density higher than the density of the dielectric region . - a semiconductor body , having a first conductivity, delimited by a first side and a second side opposite to one another along an axis (Z); - a body region , having a second conductivity opposite to the first conductivity, in the semiconductor body facing the first side ; - a source terminal , having the first conductivity, extending at least in part in the body region ; - a drain terminal , having the first conductivity, extending at the second side of the semiconductor body ; and - a trench gate , which extends in the semiconductor body from the first side towards the second side , through the body region and the source region , wherein said trench gate includes a dielectric region of porous silicon oxide buried in the semiconductor body , and a gate conductive region extending between the dielectric region of porous silicon oxide and said first side , wherein a gate dielectric extends between the gate conductive region and the semiconductor body , characterized in that said trench gate , in addition to the gate dielectric , further includes a protection region between the dielectric region of porous silicon oxide and the gate conductive region , designed for separating the dielectric region of porous silicon oxide from the gate conductive region , said protection region being of a dielectric material or of an electrically insulating material, and has a density higher than the density of the dielectric region . wherein said trench gate includes a dielectric region of porous silicon oxide buried in the semiconductor body , and a gate conductive region extending between the dielectric region of porous silicon oxide and said first side , wherein a gate dielectric extends between the gate conductive region and the semiconductor body , characterized in that said trench gate , in addition to the gate dielectric , further includes a protection region between the dielectric region of porous silicon oxide and the gate conductive region , designed for separating the dielectric region of porous silicon oxide from the gate conductive region , said protection region being of a dielectric material or of an electrically insulating material, and has a density higher than the density of the dielectric region . <EOS>