An integrated circuit comprising: a first fin and a second fin ; a first gate electrode, of a first n-type metal-oxide-semiconductor, NMOS, transistor (n2) having a first threshold voltage, on a top surface and sidewalls of the first fin, the first gate electrode including a first layer over the top surface and the sidewalls of the first fin, the first layer having a first thickness above the top surface of the first fin and a third layer having a third thickness over the first layer ; a second gate electrode, of a second NMOS transistor (n1) having a second threshold voltage, on a top surface and sidewalls of the second fin, wherein the second gate electrode includes a second layer of electrode material over the top surface and the sidewalls of the second fin, the second layer having a second thickness above the top surface of the second fin, and a fourth layer having a fourth thickness over the second layer wherein the first thickness is greater than the second thickness, the first layer and the second layer are a same first electrode material and the third layer and the fourth layer are a same second electrode material different from the first electrode material; and a first gate dielectric between the first gate electrode and the first fin and a second gate dielectric between the second gate electrode and the second fin, wherein the first threshold voltage is different from the second threshold voltage, wherein modulation of the first threshold voltage and the second threshold voltage is accomplished by varying the thickness of the first electrode material without implanting the first and second fin with n-type or p-type impurities, and wherein the thickness of the first gate electrode is equal to the thickness of the second gate electrode. a first fin and a second fin ; a first gate electrode, of a first n-type metal-oxide-semiconductor, NMOS, transistor (n2) having a first threshold voltage, on a top surface and sidewalls of the first fin, the first gate electrode including a first layer over the top surface and the sidewalls of the first fin, the first layer having a first thickness above the top surface of the first fin and a third layer having a third thickness over the first layer ; a second gate electrode, of a second NMOS transistor (n1) having a second threshold voltage, on a top surface and sidewalls of the second fin, wherein the second gate electrode includes a second layer of electrode material over the top surface and the sidewalls of the second fin, the second layer having a second thickness above the top surface of the second fin, and a fourth layer having a fourth thickness over the second layer wherein the first thickness is greater than the second thickness, the first layer and the second layer are a same first electrode material and the third layer and the fourth layer are a same second electrode material different from the first electrode material; and the first thickness is greater than the second thickness, the first layer and the second layer are a same first electrode material and the third layer and the fourth layer are a same second electrode material different from the first electrode material; and a first gate dielectric between the first gate electrode and the first fin and a second gate dielectric between the second gate electrode and the second fin, wherein the first threshold voltage is different from the second threshold voltage, wherein modulation of the first threshold voltage and the second threshold voltage is accomplished by varying the thickness of the first electrode material without implanting the first and second fin with n-type or p-type impurities, and wherein the thickness of the first gate electrode is equal to the thickness of the second gate electrode. <EOS>