A common mode logic (CML) buffer device comprising: a differential input signal pair that includes a first input and a second input; a differential output signal pair that includes a first output and a second output; a current source ; a reference voltage ; a first metal-oxide-semiconductor (MOS) transistor pair including: a first MOS transistor with a gate connected to the first input and connected in series between the current source and the first output, and a second MOS transistor with a gate connected to the second input and connected in series between the current source and the second output; a second MOS transistor pair including: a third MOS transistor connected in series between the reference voltage and the first output, and a fourth MOS transistor connected in series between the reference voltage and the second output; a first adjustment circuit configured to adjust, in response to a control signal, a first resistance value between the first output and a gate of the third MOS transistor; and a second adjustment circuit configured to adjust, in response to the control signal, a second resistance value between the second output and a gate of the fourth MOS transistor, wherein the first adjustment circuit is further configured to adjust, in response to the control signal, a first capacitance value between the gate of the third MOS transistor and the reference voltage, wherein the second adjustment circuit is further configured to adjust, in response to the control signal, a second capacitance value between the gate of the fourth MOS transistor and the reference voltage. a differential input signal pair that includes a first input and a second input; a differential output signal pair that includes a first output and a second output; a current source ; a reference voltage ; a first metal-oxide-semiconductor (MOS) transistor pair including: a first MOS transistor with a gate connected to the first input and connected in series between the current source and the first output, and a second MOS transistor with a gate connected to the second input and connected in series between the current source and the second output; a first MOS transistor with a gate connected to the first input and connected in series between the current source and the first output, and a second MOS transistor with a gate connected to the second input and connected in series between the current source and the second output; a second MOS transistor pair including: a third MOS transistor connected in series between the reference voltage and the first output, and a fourth MOS transistor connected in series between the reference voltage and the second output; a third MOS transistor connected in series between the reference voltage and the first output, and a fourth MOS transistor connected in series between the reference voltage and the second output; a first adjustment circuit configured to adjust, in response to a control signal, a first resistance value between the first output and a gate of the third MOS transistor; and a second adjustment circuit configured to adjust, in response to the control signal, a second resistance value between the second output and a gate of the fourth MOS transistor, wherein the first adjustment circuit is further configured to adjust, in response to the control signal, a first capacitance value between the gate of the third MOS transistor and the reference voltage, wherein the second adjustment circuit is further configured to adjust, in response to the control signal, a second capacitance value between the gate of the fourth MOS transistor and the reference voltage. <EOS>