An integrated circuit for accelerating memory access comprising an output latch , wherein the output latch includes: a data storage unit , wherein the data storage unit comprises: a first logic gate having a first input, a second input, and an output, with the first input coupled to a first input node configured to receive a first input voltage , the second input coupled to a second output node , and the output coupled to a first output node configured to provide a first output voltage ; and a second logic gate having a first input, a second input, and an output, with the first input coupled to the first output node , the second input coupled to a second input node configured to receive a second input voltage , and the output coupled to the second output node configured to provide a second output voltage ; wherein the first input voltage and the second input voltage comprise complementary data values; wherein the data storage unit is configured to store the complementary data values; and wherein the data storage unit is coupled to an output-enable line configured to receive an output-enable signal, OES; a first output transition circuitry having a first switch and a second switch coupled in series between the first output node and a voltage rail , including a first control node coupled to the first input node , including a second control node coupled to the output-enable line , and configured to accelerate a voltage level transition of the first output voltage responsive to the first input voltage ; and a second output transition circuitry having a first switch and a second switch coupled in series between the second output node and a voltage rail , including a first control node coupled to the second input node , including a second control node coupled to the output-enable line , and configured to accelerate a voltage level transition of the second output voltage responsive to the second input voltage . a first logic gate having a first input, a second input, and an output, with the first input coupled to a first input node configured to receive a first input voltage , the second input coupled to a second output node , and the output coupled to a first output node configured to provide a first output voltage ; and a second logic gate having a first input, a second input, and an output, with the first input coupled to the first output node , the second input coupled to a second input node configured to receive a second input voltage , and the output coupled to the second output node configured to provide a second output voltage ; wherein the first input voltage and the second input voltage comprise complementary data values; wherein the data storage unit is configured to store the complementary data values; and wherein the data storage unit is coupled to an output-enable line configured to receive an output-enable signal, OES; a first output transition circuitry having a first switch and a second switch coupled in series between the first output node and a voltage rail , including a first control node coupled to the first input node , including a second control node coupled to the output-enable line , and configured to accelerate a voltage level transition of the first output voltage responsive to the first input voltage ; and a second output transition circuitry having a first switch and a second switch coupled in series between the second output node and a voltage rail , including a first control node coupled to the second input node , including a second control node coupled to the output-enable line , and configured to accelerate a voltage level transition of the second output voltage responsive to the second input voltage . <EOS>