A jitter control circuit within a chip , comprising: an adaptive power delivery network (PDN) configured to provide a supply voltage, capable of being controlled/modulated to provide different impedances; a current generator , coupled to the adaptive PDN , configured to receive the supply voltage provided by the adaptive PDN and to generate currents with different patterns; and a jitter generator , coupled to the adaptive PDN , configured to generate a plurality of jitters corresponding to the currents with different patterns, respectively, according to the supply voltage provided by the adaptive PDN , characterized in that for a portion of the patterns of the currents whose corresponding jitters are greater than a threshold, the adaptive PDN is arranged to be controlled/modulated to have different frequencies to have the different impedances, respectively, and the jitter generator is configured to generate the plurality of jitters corresponding to the currents with the portion of the patterns and the different frequencies of the adaptive PDN , respectively, according to the supply voltage provided by the adaptive PDN , wherein a look-up table is generated based on the plurality of jitters corresponding to the currents with the portion of the patterns and the different frequencies of the adaptive PDN , respectively, during an off-line period, and the look-up table is stored in the chip , said look-up table comprises a plurality of combinations of the impedances of the adaptive PDN and the patterns of the current generated by the current generator , and a plurality of jitter levels corresponding to the combinations, respectively. an adaptive power delivery network (PDN) configured to provide a supply voltage, capable of being controlled/modulated to provide different impedances; a current generator , coupled to the adaptive PDN , configured to receive the supply voltage provided by the adaptive PDN and to generate currents with different patterns; and a jitter generator , coupled to the adaptive PDN , configured to generate a plurality of jitters corresponding to the currents with different patterns, respectively, according to the supply voltage provided by the adaptive PDN , characterized in that for a portion of the patterns of the currents whose corresponding jitters are greater than a threshold, the adaptive PDN is arranged to be controlled/modulated to have different frequencies to have the different impedances, respectively, and the jitter generator is configured to generate the plurality of jitters corresponding to the currents with the portion of the patterns and the different frequencies of the adaptive PDN , respectively, according to the supply voltage provided by the adaptive PDN , wherein a look-up table is generated based on the plurality of jitters corresponding to the currents with the portion of the patterns and the different frequencies of the adaptive PDN , respectively, during an off-line period, and the look-up table is stored in the chip , said look-up table comprises a plurality of combinations of the impedances of the adaptive PDN and the patterns of the current generated by the current generator , and a plurality of jitter levels corresponding to the combinations, respectively. <EOS>