A sorting circuit for sorting input data values, the sorting circuit comprising: a plurality of comparators, each comparator being operable to compare two comparator data values input at a first comparator input and a second comparator input, and produce a minimum of the two comparator data values at a first comparator output and a maximum of the two comparator data values at a second comparator output; a plurality of multiplexors, each multiplexor having: a plurality of multiplexor data inputs, wherein each multiplexor data input is coupled to one of the comparator outputs of one of the comparators or to one of the input data values of the sorting circuit, a single multiplexor output coupled to the first comparator input or the second comparator input of one of the comparators, so as to route one of the multiplexor inputs to the first comparator input or the second comparator input of said one of the comparators, and a multiplexor selection input operable to determine which of the multiplexor data inputs is routed to the multiplexor output; and a scheduling circuit configured to generate, for each of multiple sorting phases, control signals that are coupled to the multiplexor selection inputs of the plurality of multiplexors, so as to route the comparator outputs or the input data values during one sorting phase to the comparator inputs for a next sorting phase, to implement a known sorting algorithm and produce a median value corresponding to a window of the input data values. a plurality of comparators, each comparator being operable to compare two comparator data values input at a first comparator input and a second comparator input, and produce a minimum of the two comparator data values at a first comparator output and a maximum of the two comparator data values at a second comparator output; a plurality of multiplexors, each multiplexor having: a plurality of multiplexor data inputs, wherein each multiplexor data input is coupled to one of the comparator outputs of one of the comparators or to one of the input data values of the sorting circuit, a single multiplexor output coupled to the first comparator input or the second comparator input of one of the comparators, so as to route one of the multiplexor inputs to the first comparator input or the second comparator input of said one of the comparators, and a multiplexor selection input operable to determine which of the multiplexor data inputs is routed to the multiplexor output; and a plurality of multiplexor data inputs, wherein each multiplexor data input is coupled to one of the comparator outputs of one of the comparators or to one of the input data values of the sorting circuit, a single multiplexor output coupled to the first comparator input or the second comparator input of one of the comparators, so as to route one of the multiplexor inputs to the first comparator input or the second comparator input of said one of the comparators, and a multiplexor selection input operable to determine which of the multiplexor data inputs is routed to the multiplexor output; and a scheduling circuit configured to generate, for each of multiple sorting phases, control signals that are coupled to the multiplexor selection inputs of the plurality of multiplexors, so as to route the comparator outputs or the input data values during one sorting phase to the comparator inputs for a next sorting phase, to implement a known sorting algorithm and produce a median value corresponding to a window of the input data values. <EOS>