A memory system comprising: a memory device that outputs data in response to a read command; and a memory controller that provides the read command to the memory device in response to a read request received from a host , such that the data is output from the memory device , wherein: the memory device comprises a first function circuit that performs a first operation based on the data stored in the memory device to generate first processed data (mDAT), in response to the read command, the memory controller receives status information (STAT) associated with performing the first operation, the memory controller comprises a second function circuit that performs a second operation based on the first processed data (mDAT) to generate second processed data (pDAT), characterized in that a manner of the second operation varies based on the status information (STAT) indicating whether the memory device includes the first function circuit or whether performing the first operation is enabled, and wherein the first operation is a first error processing operation; and the second operation is a second error processing operation, and wherein: a maximum number of errors detectable by the second error processing operation with regard to the first processed data (mDAT) is greater than a maximum number of errors detectable by the first error processing operation with regard to the data stored in the memory device . a memory device that outputs data in response to a read command; and a memory controller that provides the read command to the memory device in response to a read request received from a host , such that the data is output from the memory device , wherein: the memory device comprises a first function circuit that performs a first operation based on the data stored in the memory device to generate first processed data (mDAT), in response to the read command, the memory controller receives status information (STAT) associated with performing the first operation, the memory controller comprises a second function circuit that performs a second operation based on the first processed data (mDAT) to generate second processed data (pDAT), characterized in that a manner of the second operation varies based on the status information (STAT) indicating whether the memory device includes the first function circuit or whether performing the first operation is enabled, and wherein the first operation is a first error processing operation; and the second operation is a second error processing operation, and wherein: a maximum number of errors detectable by the second error processing operation with regard to the first processed data (mDAT) is greater than a maximum number of errors detectable by the first error processing operation with regard to the data stored in the memory device . the memory device comprises a first function circuit that performs a first operation based on the data stored in the memory device to generate first processed data (mDAT), in response to the read command, the memory controller receives status information (STAT) associated with performing the first operation, the memory controller comprises a second function circuit that performs a second operation based on the first processed data (mDAT) to generate second processed data (pDAT), characterized in that a manner of the second operation varies based on the status information (STAT) indicating whether the memory device includes the first function circuit or whether performing the first operation is enabled, and wherein the first operation is a first error processing operation; and the second operation is a second error processing operation, and wherein: a maximum number of errors detectable by the second error processing operation with regard to the first processed data (mDAT) is greater than a maximum number of errors detectable by the first error processing operation with regard to the data stored in the memory device . <EOS>