An integrated circuit comprising N adjacent patterns, all identical, corresponding to N adjacent identical partial circuits (C1, C2, C3) of rank i=1 to i=N in the order of geographical succession of the partial circuits, each partial circuit comprising an upstream clock signal input (EH Ami ), a downstream clock signal output (SH AV ) and a main conducting line (LP) extending between the upstream clock signal input (EH Ami ) and the downstream clock signal output (SH AV ) and introducing a propagation delay of time T, the downstream clock signal output (SH AV ) of each partial circuit, except that of rank N, being directly linked to the upstream clock signal input (EH Ami ) of the partial circuit immediately following so that the main conducting lines (LP) of the partial circuits allow the cascade transmission of a master signal (CLK) received on the partial rank circuit of rank 1, characterized in that it comprises in each partial circuit of rank i: - a compensation conducting line (LS) with N successive outputs (S1, S2, S3) of rank i = 1 to N, linked to the main line (LP) of the partial circuit and establishing a propagation delay of duration T between the successive outputs, - a multiplexer (MUX) with N inputs linked respectively to each of the N outputs of the compensation conducting line, and - control lines (LC) of the multiplexer, which are designed to select the multiplexer's input of rank i, linked to the output of rank N-i+1 from among the N outputs of the compensation conducting line, the output of the multiplexer of the partial circuit of rank i thus providing a local signal (ClkL i ) for this partial circuit. and in that : - the control lines of the multiplexer of the partial circuit of rank 1 are configured to receive a signal for selecting the input of rank N of this multiplexer and to propagate this signal from one multiplexer to the following while modifying it each time so as to increment the rank of the selected input by one unit, so that the control lines ending at the multiplexer of the partial circuit of rank i select the output of rank N-i+1 of the compensation line and transmit to the multiplexer of the partial circuit of rank i+1 a command for selecting the output of rank N-i. - a compensation conducting line (LS) with N successive outputs (S1, S2, S3) of rank i = 1 to N, linked to the main line (LP) of the partial circuit and establishing a propagation delay of duration T between the successive outputs, - a multiplexer (MUX) with N inputs linked respectively to each of the N outputs of the compensation conducting line, and - control lines (LC) of the multiplexer, which are designed to select the multiplexer's input of rank i, linked to the output of rank N-i+1 from among the N outputs of the compensation conducting line, - the control lines of the multiplexer of the partial circuit of rank 1 are configured to receive a signal for selecting the input of rank N of this multiplexer and to propagate this signal from one multiplexer to the following while modifying it each time so as to increment the rank of the selected input by one unit, so that the control lines ending at the multiplexer of the partial circuit of rank i select the output of rank N-i+1 of the compensation line and transmit to the multiplexer of the partial circuit of rank i+1 a command for selecting the output of rank N-i. <EOS>