An array substrate for a liquid crystal display of the advanced super-dimensional switching type, the array substrate comprising: a base substrate ; a data line (DL) and a common electrode line (CL) on the base substrate; and a first gate line (GL1) and a second gate line (GL2) on the base substrate, both the first gate line and the second gate line being insulated from and crossing both the data line and the common electrode line to define a sub-pixel (P), wherein the sub-pixel comprises: a pixel electrode on the base substrate; a common electrode on a side of the pixel electrode distal to the base substrate; and an insulating layer between the pixel electrode and the common electrode, wherein the common electrode comprises a plurality of slits , and the plurality of slits extend in the same direction as the data line (DL); wherein the plurality of slits comprise a first slit close to the data line, the pixel electrode comprises a first side surface close to the data line, and an orthographic projection of the first side surface of the pixel electrode on the base substrate is located within an orthographic projection of the first slit on the base substrate; wherein the sub-pixel further comprises a light shielding portion , and an orthographic projection of the light shielding portion on the base substrate is located between an orthographic projection of the data line (DL) on the base substrate and an orthographic projection of the pixel electrode on the base substrate; and wherein the light shielding portion and the pixel electrode are located in the same layer. a base substrate ; a data line (DL) and a common electrode line (CL) on the base substrate; and a first gate line (GL1) and a second gate line (GL2) on the base substrate, both the first gate line and the second gate line being insulated from and crossing both the data line and the common electrode line to define a sub-pixel (P), wherein the sub-pixel comprises: a pixel electrode on the base substrate; a common electrode on a side of the pixel electrode distal to the base substrate; and an insulating layer between the pixel electrode and the common electrode, a pixel electrode on the base substrate; a common electrode on a side of the pixel electrode distal to the base substrate; and an insulating layer between the pixel electrode and the common electrode, wherein the common electrode comprises a plurality of slits , and the plurality of slits extend in the same direction as the data line (DL); wherein the plurality of slits comprise a first slit close to the data line, the pixel electrode comprises a first side surface close to the data line, and an orthographic projection of the first side surface of the pixel electrode on the base substrate is located within an orthographic projection of the first slit on the base substrate; wherein the sub-pixel further comprises a light shielding portion , and an orthographic projection of the light shielding portion on the base substrate is located between an orthographic projection of the data line (DL) on the base substrate and an orthographic projection of the pixel electrode on the base substrate; and wherein the light shielding portion and the pixel electrode are located in the same layer. <EOS>