A circuit, comprising: a first amplifier having a first input coupled to a first node , a second input coupled to a second node , a first output, and a second output; a second amplifier having a first input coupled to the first output of the first amplifier , a second input coupled to the second output of the first amplifier , a first output coupled to a third node , and a second output coupled to a fourth node ; a third amplifier having a first input coupled to the third node , a second input coupled to the fourth node , a first output coupled to a fifth node , a second output coupled to a sixth node , and a control input; a first resistor coupled between the first node and a seventh node ; a second resistor coupled between the seventh node and the second node ; a first comparator having a first input coupled to the seventh node , a second input coupled to an eighth node , and an output, wherein the eighth node is connected a) to ground potential, or b) between a third resistor and a fourth resistor , the third resistor coupled between the first node and the eighth node and the fourth resistor coupled between the eighth node and the second node ; a bus holder circuit having an input, a first output coupled to the third node , and a second output coupled to the fourth node ; and a logic circuit having a first input coupled to the output of the first comparator , a first output coupled to the input of the bus holder circuit , and a second output coupled to the control input of the third amplifier ; wherein the logic circuit is adapted to control the bus holder and/or the third amplifier to maintain a value of a last bit of data at the third node and the fourth node , respectively. a first amplifier having a first input coupled to a first node , a second input coupled to a second node , a first output, and a second output; a second amplifier having a first input coupled to the first output of the first amplifier , a second input coupled to the second output of the first amplifier , a first output coupled to a third node , and a second output coupled to a fourth node ; a third amplifier having a first input coupled to the third node , a second input coupled to the fourth node , a first output coupled to a fifth node , a second output coupled to a sixth node , and a control input; a first resistor coupled between the first node and a seventh node ; a second resistor coupled between the seventh node and the second node ; a first comparator having a first input coupled to the seventh node , a second input coupled to an eighth node , and an output, wherein the eighth node is connected a) to ground potential, or b) between a third resistor and a fourth resistor , the third resistor coupled between the first node and the eighth node and the fourth resistor coupled between the eighth node and the second node ; a bus holder circuit having an input, a first output coupled to the third node , and a second output coupled to the fourth node ; and a logic circuit having a first input coupled to the output of the first comparator , a first output coupled to the input of the bus holder circuit , and a second output coupled to the control input of the third amplifier ; wherein the logic circuit is adapted to control the bus holder and/or the third amplifier to maintain a value of a last bit of data at the third node and the fourth node , respectively. a bus holder circuit having an input, a first output coupled to the third node , and a second output coupled to the fourth node ; and a logic circuit having a first input coupled to the output of the first comparator , a first output coupled to the input of the bus holder circuit , and a second output coupled to the control input of the third amplifier ; wherein the logic circuit is adapted to control the bus holder and/or the third amplifier to maintain a value of a last bit of data at the third node and the fourth node , respectively. <EOS>