An apparatus comprising a memory system (14; 14A) configured to be communicatively coupled to a processor (12; 12A) via one or more data buses , wherein the memory system comprises: a main memory array (66; 66A) configured to store first data at a first storage location and second data at a second storage location; characterized in that the memory system (14; 14A) comprises: a first memory controller (26; 26B) configured to: receive a memory access request that requests return of the first data and the second data when the first data and the second data are targeted by the processor (12; 12A); determine a data access pattern resulting from the memory access request; determine an access pointer that identifies the first storage location of the first data in the main memory array (66; 66A) and the second storage location of the second data in the main memory (66; 66A), wherein the access pointer comprises a striding access pointer when the data access pattern is a striding access pattern and a sorted access pointer when the data access pattern is a sorted access pattern; and instruct the memory system (14; 14A) to use the access pointer to identify and output the first data and the second data via the one or more data buses to enable processing circuitry (16; 16A) implemented in the processor (12; 12A) to perform an operation based at least in part on the first data and the second data. a main memory array (66; 66A) configured to store first data at a first storage location and second data at a second storage location; a first memory controller (26; 26B) configured to: receive a memory access request that requests return of the first data and the second data when the first data and the second data are targeted by the processor (12; 12A); determine a data access pattern resulting from the memory access request; determine an access pointer that identifies the first storage location of the first data in the main memory array (66; 66A) and the second storage location of the second data in the main memory (66; 66A), wherein the access pointer comprises a striding access pointer when the data access pattern is a striding access pattern and a sorted access pointer when the data access pattern is a sorted access pattern; and instruct the memory system (14; 14A) to use the access pointer to identify and output the first data and the second data via the one or more data buses to enable processing circuitry (16; 16A) implemented in the processor (12; 12A) to perform an operation based at least in part on the first data and the second data. receive a memory access request that requests return of the first data and the second data when the first data and the second data are targeted by the processor (12; 12A); determine a data access pattern resulting from the memory access request; determine an access pointer that identifies the first storage location of the first data in the main memory array (66; 66A) and the second storage location of the second data in the main memory (66; 66A), wherein the access pointer comprises a striding access pointer when the data access pattern is a striding access pattern and a sorted access pointer when the data access pattern is a sorted access pattern; and instruct the memory system (14; 14A) to use the access pointer to identify and output the first data and the second data via the one or more data buses to enable processing circuitry (16; 16A) implemented in the processor (12; 12A) to perform an operation based at least in part on the first data and the second data. <EOS>