An apparatus for a digital-to-analog converter, DAC, the apparatus comprising: a logical circuit configured to perform an AND logical operation to bits of a digital code, a plurality of current cells comprising a first group of current cells and a second group of current cells, and a plurality of switches configured to operate the plurality of current cells to output currents, respectively, wherein the plurality of switches is divided into a first switching group configured to operate the first group of current cells based directly on the bits of the digital code and a second switching group configured to operate the second group of current cells based on a result of the AND logical operation of at least two bits of the digital code, wherein the plurality of current cells is configured to output an analog signal according to a total current that is a sum of the currents of the plurality of current cells, and wherein the plurality of current cells is configured to output the currents such that the total current is exponentially changed when the digital code is linearly changed, wherein the analog signal is generated based on a following equation: I = I 0 ⋅ 10 k 2 L − 1 C , wherein I 0 denotes a constant, L denotes a size of the digital code, k denotes a value corresponding to the bits of the digital code and is an integer ranging from 0 to 2 L , and C is a constant value indicating sensitivity to a weak signal, wherein the currents of the plurality of current cells are determined according to terms of a Taylor series corresponding to the equation.. a logical circuit configured to perform an AND logical operation to bits of a digital code, a plurality of current cells comprising a first group of current cells and a second group of current cells, and a plurality of switches configured to operate the plurality of current cells to output currents, respectively, wherein the plurality of switches is divided into a first switching group configured to operate the first group of current cells based directly on the bits of the digital code and a second switching group configured to operate the second group of current cells based on a result of the AND logical operation of at least two bits of the digital code, wherein the plurality of current cells is configured to output an analog signal according to a total current that is a sum of the currents of the plurality of current cells, and wherein the plurality of current cells is configured to output the currents such that the total current is exponentially changed when the digital code is linearly changed, wherein the analog signal is generated based on a following equation: I = I 0 ⋅ 10 k 2 L − 1 C , wherein I 0 denotes a constant, L denotes a size of the digital code, k denotes a value corresponding to the bits of the digital code and is an integer ranging from 0 to 2 L , and C is a constant value indicating sensitivity to a weak signal, wherein the currents of the plurality of current cells are determined according to terms of a Taylor series corresponding to the equation.. wherein I 0 denotes a constant, L denotes a size of the digital code, k denotes a value corresponding to the bits of the digital code and is an integer ranging from 0 to 2 L , and C is a constant value indicating sensitivity to a weak signal, wherein the currents of the plurality of current cells are determined according to terms of a Taylor series corresponding to the equation.. <EOS>