A three-dimensional memory device , comprising: a first semiconductor structure comprising: an array of NAND memory strings; and a first semiconductor layer in contact with sources of the array of NAND memory strings; a second semiconductor structure comprising: a first peripheral circuit of the array of NAND memory strings, the first peripheral circuit comprising a first transistor; and a second semiconductor layer in contact with the first transistor; a third semiconductor structure comprising: a second peripheral circuit of the array of NAND memory strings, the second peripheral circuit comprising a second transistor; and a third semiconductor layer in contact with the second transistor; a first bonding interface between the first semiconductor structure and the second semiconductor structure , wherein the first peripheral circuit is between the first bonding interface and the second semiconductor layer; and a second bonding interface between the second semiconductor structure and the third semiconductor structure , wherein the second peripheral circuit is between the second bonding interface and the third semiconductor layer, wherein the first peripheral circuit and the second peripheral circuit are control and sensing circuits, which include any suitable digital, analog, and/or mixed-signal circuits used for facilitating the operations of the memory cell array, wherein the first transistor comprises a first gate dielectric; the second transistor comprises a second gate dielectric; and a thickness of the second gate dielectric is greater than a thickness of the first gate dielectric. a first semiconductor structure comprising: an array of NAND memory strings; and a first semiconductor layer in contact with sources of the array of NAND memory strings; a second semiconductor structure comprising: a first peripheral circuit of the array of NAND memory strings, the first peripheral circuit comprising a first transistor; and a second semiconductor layer in contact with the first transistor; a first peripheral circuit of the array of NAND memory strings, the first peripheral circuit comprising a first transistor; and a second semiconductor layer in contact with the first transistor; a third semiconductor structure comprising: a second peripheral circuit of the array of NAND memory strings, the second peripheral circuit comprising a second transistor; and a third semiconductor layer in contact with the second transistor; a second peripheral circuit of the array of NAND memory strings, the second peripheral circuit comprising a second transistor; and a third semiconductor layer in contact with the second transistor; a first bonding interface between the first semiconductor structure and the second semiconductor structure , wherein the first peripheral circuit is between the first bonding interface and the second semiconductor layer; and a second bonding interface between the second semiconductor structure and the third semiconductor structure , wherein the second peripheral circuit is between the second bonding interface and the third semiconductor layer, wherein the first peripheral circuit and the second peripheral circuit are control and sensing circuits, which include any suitable digital, analog, and/or mixed-signal circuits used for facilitating the operations of the memory cell array, wherein the first transistor comprises a first gate dielectric; the second transistor comprises a second gate dielectric; and a thickness of the second gate dielectric is greater than a thickness of the first gate dielectric. <EOS>