A magnetoresistive random-access memory, MRAM device, the MRAM device comprising: a first cell connected to a first bit line ; a second cell connected to a second bit line ; a shared transistor connected to the first cell and connected to the second cell; a first selector device corresponding to the first cell, the first selector device configured to permit current to flow through the first cell to the shared transistor when a first voltage applied to the first selector device is larger than a threshold activation voltage; a second selector device corresponding to the second cell, the second selector device configured to permit current to flow through the second cell to the shared transistor when a second voltage applied to the second selector device is larger than the threshold activation voltage; a word line connected to a gate of the shared transistor; a first transistor connected to and associated with the first cell by way of the first bit line; a second transistor connected to and associated with the second cell by way of the second bit line; wherein the first cell comprises a first magnetic tunnel junction, MTJ , arranged between a first top electrode and a first bottom electrode ; the first MTJ comprising a first reference layer , a first tunnel barrier layer , and a first free layer ; wherein the second cell includes a second magnetic tunnel junction, MTJ , arranged between a second top electrode and a second bottom electrode ; the second MTJ comprising a second reference layer , a second tunnel barrier layer , and a second free layer ; and wherein both bottom electrodes are connected to a shared landing pad ; and at least one of the first selector device and the second selector device is arranged between the reference layer and the bottom electrode of the corresponding cell. a first cell connected to a first bit line ; a second cell connected to a second bit line ; a shared transistor connected to the first cell and connected to the second cell; a first selector device corresponding to the first cell, the first selector device configured to permit current to flow through the first cell to the shared transistor when a first voltage applied to the first selector device is larger than a threshold activation voltage; a second selector device corresponding to the second cell, the second selector device configured to permit current to flow through the second cell to the shared transistor when a second voltage applied to the second selector device is larger than the threshold activation voltage; a word line connected to a gate of the shared transistor; a first transistor connected to and associated with the first cell by way of the first bit line; a second transistor connected to and associated with the second cell by way of the second bit line; wherein the first cell comprises a first magnetic tunnel junction, MTJ , arranged between a first top electrode and a first bottom electrode ; the first MTJ comprising a first reference layer , a first tunnel barrier layer , and a first free layer ; wherein the second cell includes a second magnetic tunnel junction, MTJ , arranged between a second top electrode and a second bottom electrode ; the second MTJ comprising a second reference layer , a second tunnel barrier layer , and a second free layer ; and wherein both bottom electrodes are connected to a shared landing pad ; and at least one of the first selector device and the second selector device is arranged between the reference layer and the bottom electrode of the corresponding cell. <EOS>