A range sensor comprising: a semiconductor substrate ; a photogate electrode (PG) provided on a surface of the semiconductor substrate and having a planar shape with a first side (LS1) and a second side (LS2) opposed to each other; first and second semiconductor regions (FD1, FD2) arranged as spatially separated from each other on the side where the first side (LS1) of the photogate electrode (PG) exists and along the first side (LS1), having a conductivity type different from that of the semiconductor substrate , and configured to accumulate charge generated in a region immediately below the photogate electrode (PG); third and fourth semiconductor regions (FD3, FD4) arranged as spatially separated from each other on the side where the second side (LS2) of the photogate electrode (PG) exists and along the second side (LS2) and as opposed to the first and second semiconductor regions (FD1, FD2) with the photogate electrode (PG) in between in an opposed direction in which the first side (LS1) and the second side (LS2) are opposed, having the conductivity type different from that of the semiconductor substrate , and configured to accumulate charge generated in the region immediately below the photogate electrode (PG); well regions (W1-W4) having the same conductivity type as the semiconductor substrate and an impurity concentration higher than an impurity concentration of the semiconductor substrate , and provided so as to overlap with the first to fourth respective semiconductor regions(FD1-FD4); and first transfer electrodes (TX1) provided respectively between the first and third semiconductor regions (FD1, FD3) and the photogate electrode (PG) on the surface and second transfer electrodes (TX2) provided respectively between the second and fourth semiconductor regions (FD2, FD4) and the photogate electrode (PG) on the surface, to which charge transfer signals of different phases are supplied. a semiconductor substrate ; a photogate electrode (PG) provided on a surface of the semiconductor substrate and having a planar shape with a first side (LS1) and a second side (LS2) opposed to each other; first and second semiconductor regions (FD1, FD2) arranged as spatially separated from each other on the side where the first side (LS1) of the photogate electrode (PG) exists and along the first side (LS1), having a conductivity type different from that of the semiconductor substrate , and configured to accumulate charge generated in a region immediately below the photogate electrode (PG); third and fourth semiconductor regions (FD3, FD4) arranged as spatially separated from each other on the side where the second side (LS2) of the photogate electrode (PG) exists and along the second side (LS2) and as opposed to the first and second semiconductor regions (FD1, FD2) with the photogate electrode (PG) in between in an opposed direction in which the first side (LS1) and the second side (LS2) are opposed, having the conductivity type different from that of the semiconductor substrate , and configured to accumulate charge generated in the region immediately below the photogate electrode (PG); well regions (W1-W4) having the same conductivity type as the semiconductor substrate and an impurity concentration higher than an impurity concentration of the semiconductor substrate , and provided so as to overlap with the first to fourth respective semiconductor regions(FD1-FD4); and first transfer electrodes (TX1) provided respectively between the first and third semiconductor regions (FD1, FD3) and the photogate electrode (PG) on the surface and second transfer electrodes (TX2) provided respectively between the second and fourth semiconductor regions (FD2, FD4) and the photogate electrode (PG) on the surface, to which charge transfer signals of different phases are supplied. <EOS>