An electronic device comprising: a battery ; a power management module configured to control a power supplied from the battery of a first power signal and of a second power signal; a connector comprising a first sub-pin array and a second sub-pin array ; a device recognition circuit configured to detect whether an external device is connected to the connector; and a processor ; wherein the first sub-pin array comprises a first power pin , a first data pin , and a first recognition pin , wherein the second sub-pin array comprises a second power pin , a second data pin , and a second recognition pin ; wherein the first recognition pin and the second recognition pin are connected to the device recognition circuit ; wherein the processor is configured to: based on a first resistance value detected in the first recognition pin ,control the power management module to supply the first power signal to the first power pin and to supply the second power signal to the second recognition pin , receive first identification information of the external device via the first recognition pin or the first data pin , and based on the first identification information, control the power management module to cut off the supply of the first power signal and to maintain the supply of the second power signal, wherein a first voltage value of the first power signal is higher than a second voltage value of the second power signal, and wherein the first power signal is a signal obtained by boosting a power signal output via a terminal of the battery, and the second power signal is a power signal directly output via the terminal of the battery. a battery ; a power management module configured to control a power supplied from the battery of a first power signal and of a second power signal; a connector comprising a first sub-pin array and a second sub-pin array ; a device recognition circuit configured to detect whether an external device is connected to the connector; and a processor ; wherein the first sub-pin array comprises a first power pin , a first data pin , and a first recognition pin , wherein the second sub-pin array comprises a second power pin , a second data pin , and a second recognition pin ; wherein the first recognition pin and the second recognition pin are connected to the device recognition circuit ; wherein the processor is configured to: based on a first resistance value detected in the first recognition pin ,control the power management module to supply the first power signal to the first power pin and to supply the second power signal to the second recognition pin , receive first identification information of the external device via the first recognition pin or the first data pin , and based on the first identification information, control the power management module to cut off the supply of the first power signal and to maintain the supply of the second power signal, based on a first resistance value detected in the first recognition pin ,control the power management module to supply the first power signal to the first power pin and to supply the second power signal to the second recognition pin , receive first identification information of the external device via the first recognition pin or the first data pin , and based on the first identification information, control the power management module to cut off the supply of the first power signal and to maintain the supply of the second power signal, wherein a first voltage value of the first power signal is higher than a second voltage value of the second power signal, and wherein the first power signal is a signal obtained by boosting a power signal output via a terminal of the battery, and the second power signal is a power signal directly output via the terminal of the battery. <EOS>