A current sampling circuit comprising a proportional current output circuit and a negative feedback circuit , the proportional current output circuit being configured to calculate a current output from a power device (M 1 ) according to a pre-set proportion to obtain a first proportional current (I J1 ) and a second proportional current (I J2 ) and to output the first proportional current (I J1 ) and the second proportional current (I J2 ) to the negative feedback circuit , characterised in that : a) the negative feedback circuit is a full differential common mode negative feedback circuit which is configured to shunt respectively the first proportional current (I J1 ) and the second proportional current (I J2 ) using a full differential common mode negative feedback network and a bias current (I b ) in microamps to obtain a first sampling current (I sense+ ) and a second sampling current (I sense- ) and to output constantly the first sampling current (I sense+ ) and the second sampling current (I sense- ) according to the following formulae: I sense + = I J 1 − I b I sense − = I J 2 − I b , where I sense+ is the first sampling current, I sense- is the second sampling current, I J1 is the first proportional current, I J2 is the second proportional current and I b is the bias current in microamps provided by the full differential common mode negative feedback network; b) the power device (M 1 ) is implemented by a first Lateral Diffusion N-channel Metal-Oxide-Semiconductor LDNMOS (M 1 ) connected between a power supply (V in ) and a first reference power source (I 1 ), which is connected to ground; c) the proportional current output circuit comprises a second LDNMOS (M 2 ), a third LDNMOS (M 3 ), a fourth LDNMOS (M 4 ) and a fifth LDNMOS (M 5 ); and d) the full differential common mode negative feedback circuit comprises a first P-channel Metal-Oxide-Semiconductor PMOS (M 6 ), a second PMOS (M 7 ), a third PMOS (M 8 ), a fourth PMOS (M 9 ), a first resistor (R 1 ), a second resistor (R 2 ), a second reference current source (I 2 ), a third reference current source (I 3 ), a fourth reference current source (I 4 ) and a fifth reference current source (I 5 ). a) the negative feedback circuit is a full differential common mode negative feedback circuit which is configured to shunt respectively the first proportional current (I J1 ) and the second proportional current (I J2 ) using a full differential common mode negative feedback network and a bias current (I b ) in microamps to obtain a first sampling current (I sense+ ) and a second sampling current (I sense- ) and to output constantly the first sampling current (I sense+ ) and the second sampling current (I sense- ) according to the following formulae: I sense + = I J 1 − I b I sense − = I J 2 − I b , where I sense+ is the first sampling current, I sense- is the second sampling current, I J1 is the first proportional current, I J2 is the second proportional current and I b is the bias current in microamps provided by the full differential common mode negative feedback network; b) the power device (M 1 ) is implemented by a first Lateral Diffusion N-channel Metal-Oxide-Semiconductor LDNMOS (M 1 ) connected between a power supply (V in ) and a first reference power source (I 1 ), which is connected to ground; c) the proportional current output circuit comprises a second LDNMOS (M 2 ), a third LDNMOS (M 3 ), a fourth LDNMOS (M 4 ) and a fifth LDNMOS (M 5 ); and d) the full differential common mode negative feedback circuit comprises a first P-channel Metal-Oxide-Semiconductor PMOS (M 6 ), a second PMOS (M 7 ), a third PMOS (M 8 ), a fourth PMOS (M 9 ), a first resistor (R 1 ), a second resistor (R 2 ), a second reference current source (I 2 ), a third reference current source (I 3 ), a fourth reference current source (I 4 ) and a fifth reference current source (I 5 ). <EOS>