A circuit for pre-balancing a switched capacitor converter having a plurality of switches coupled in series, an input capacitor , an output capacitor , and a flying capacitor , comprising: a first comparator comprising: a positive input configured to receive a voltage across an output capacitor ; a negative input configured to receive a first hysteresis voltage ; an enable input operative to receive an enable signal ; and an output coupled to a first current source ; a second comparator comprising: a positive input configured to receive a voltage across an input capacitor of the switched capacitor converter; a negative input configured to receive a second hysteresis voltage ; an enable input operative to receive the enable signal ; and an output coupled to a second current source , wherein: the first current source is coupled between the output capacitor and GND and is configured to discharge the output capacitor upon determining that the voltage across the output capacitor is above a tolerance provided by the first hysteresis voltage , and the second current source is coupled between the input capacitor and GND and is configured to discharge the input capacitor upon determining that the voltage across the input capacitor is above a tolerance provided by the second hysteresis voltage , the circuit further comprising a switch coupled between the second current source and an input of the switched capacitor converter, wherein the switch is a transistor having a gate that is coupled to an enable signal , and is configured to operate as an input disconnect switch , being OFF during a pre-balance phase and ON after the pre-balancing; wherein the enable signal is asserted to create a ramp voltage at the input of the switched capacitor converter. a first comparator comprising: a positive input configured to receive a voltage across an output capacitor ; a negative input configured to receive a first hysteresis voltage ; an enable input operative to receive an enable signal ; and an output coupled to a first current source ; a positive input configured to receive a voltage across an output capacitor ; a negative input configured to receive a first hysteresis voltage ; an enable input operative to receive an enable signal ; and an output coupled to a first current source ; a second comparator comprising: a positive input configured to receive a voltage across an input capacitor of the switched capacitor converter; a negative input configured to receive a second hysteresis voltage ; an enable input operative to receive the enable signal ; and an output coupled to a second current source , wherein: a positive input configured to receive a voltage across an input capacitor of the switched capacitor converter; a negative input configured to receive a second hysteresis voltage ; an enable input operative to receive the enable signal ; and an output coupled to a second current source , wherein: the first current source is coupled between the output capacitor and GND and is configured to discharge the output capacitor upon determining that the voltage across the output capacitor is above a tolerance provided by the first hysteresis voltage , and the second current source is coupled between the input capacitor and GND and is configured to discharge the input capacitor upon determining that the voltage across the input capacitor is above a tolerance provided by the second hysteresis voltage , the circuit further comprising a switch coupled between the second current source and an input of the switched capacitor converter, wherein the switch is a transistor having a gate that is coupled to an enable signal , and is configured to operate as an input disconnect switch , being OFF during a pre-balance phase and ON after the pre-balancing; wherein the enable signal is asserted to create a ramp voltage at the input of the switched capacitor converter. <EOS>