(Currently amended) A display device comprising: a substrate comprising a display area and a peripheral area outside the display area (DA), the display area (DA) comprising a plurality of pixel circuits (PC) and a plurality of display elements respectively connected to the plurality of pixel circuits (PC) to display an image; an inorganic insulating layer arranged in the display area (DA), the inorganic insulating layer having a lower valley (VA1) as an opening or a groove in a region and arranged between a first pixel circuit (PC1) and a second pixel circuit (PC2) that are adjacent to each other; a first organic planarization layer arranged over entire regions of the first pixel circuit (PC1) and the second pixel circuit (PC2), the first organic planarization layer filling the lower valley (VA1); a connection wire arranged on the first organic planarization layer , the connection wire connecting the first pixel circuit (PC1) to the second pixel circuit (PC2); an interlayer insulating layer arranged on the connection wire , the interlayer insulating layer having an upper valley as an opening or a groove arranged in a region between at least two of the plurality of pixel circuits (PC); and a second organic planarization layer arranged on the interlayer insulating layer and over the entire regions of the first pixel circuit (PC1) and the second pixel circuit (PC2), the second organic planarization layer filling the upper valley (VA2), wherein the connection wire is connected to a first conductive layer in the first pixel circuit (PC1) through a first contact hole (CNT3a) passing through the first organic planarization layer and is connected to a second conductive layer in the second pixel circuit (PC2) through a second contact hole (CNT2b) passing through the first organic planarization layer , and wherein the interlayer insulating layer is disposed between the first organic planarization layer and the plurality of display elements. an inorganic insulating layer arranged in the display area (DA), the inorganic insulating layer having a lower valley (VA1) as an opening or a groove in a region and arranged between a first pixel circuit (PC1) and a second pixel circuit (PC2) that are adjacent to each other; a first organic planarization layer arranged over entire regions of the first pixel circuit (PC1) and the second pixel circuit (PC2), the first organic planarization layer filling the lower valley (VA1); a connection wire arranged on the first organic planarization layer , the connection wire connecting the first pixel circuit (PC1) to the second pixel circuit (PC2); an interlayer insulating layer arranged on the connection wire , the interlayer insulating layer having an upper valley as an opening or a groove arranged in a region between at least two of the plurality of pixel circuits (PC); and a second organic planarization layer arranged on the interlayer insulating layer and over the entire regions of the first pixel circuit (PC1) and the second pixel circuit (PC2), the second organic planarization layer filling the upper valley (VA2), wherein the connection wire is connected to a first conductive layer in the first pixel circuit (PC1) through a first contact hole (CNT3a) passing through the first organic planarization layer and is connected to a second conductive layer in the second pixel circuit (PC2) through a second contact hole (CNT2b) passing through the first organic planarization layer , and wherein the interlayer insulating layer is disposed between the first organic planarization layer and the plurality of display elements. <EOS>