An apparatus comprising: an integrator circuit comprising two integrator inputs and two integrator outputs; a first switch circuit configured to selectively couple one of a first apparatus input signal (V INP ) and a second apparatus input signal (V INM ) with one of a first integrator input and a second integrator input, the first switch circuit comprising: a first switch configured to couple the first integrator input with the first apparatus input signal (V INP ); a second switch configured to couple the second integrator input with the first apparatus input signal (V INP ); a third switch configured to couple the first integrator input with the second apparatus input signal (V INM ); and a fourth switch configured to couple the second integrator input with the second apparatus input signal (V INM ); a first comparator configured to: receive a first output (V INP_COMP ) of the integrator circuit and a first reference signal (V TH ); and generate a first comparator output signal (INC); and a second comparator configured to: receive a second output (V INM _ COMP ) of the integrator circuit and the first reference signal (V TH ); and generate a second comparator output signal (DEC), and a switch control generation circuit configured to receive the first and second comparator output signals (INC, DEC) and to generate control signals for the first switch circuit . an integrator circuit comprising two integrator inputs and two integrator outputs; a first switch circuit configured to selectively couple one of a first apparatus input signal (V INP ) and a second apparatus input signal (V INM ) with one of a first integrator input and a second integrator input, the first switch circuit comprising: a first switch configured to couple the first integrator input with the first apparatus input signal (V INP ); a second switch configured to couple the second integrator input with the first apparatus input signal (V INP ); a third switch configured to couple the first integrator input with the second apparatus input signal (V INM ); and a fourth switch configured to couple the second integrator input with the second apparatus input signal (V INM ); a first switch configured to couple the first integrator input with the first apparatus input signal (V INP ); a second switch configured to couple the second integrator input with the first apparatus input signal (V INP ); a third switch configured to couple the first integrator input with the second apparatus input signal (V INM ); and a fourth switch configured to couple the second integrator input with the second apparatus input signal (V INM ); a first comparator configured to: receive a first output (V INP_COMP ) of the integrator circuit and a first reference signal (V TH ); and generate a first comparator output signal (INC); and receive a first output (V INP_COMP ) of the integrator circuit and a first reference signal (V TH ); and generate a first comparator output signal (INC); and a second comparator configured to: receive a second output (V INM _ COMP ) of the integrator circuit and the first reference signal (V TH ); and generate a second comparator output signal (DEC), and receive a second output (V INM _ COMP ) of the integrator circuit and the first reference signal (V TH ); and generate a second comparator output signal (DEC), and a switch control generation circuit configured to receive the first and second comparator output signals (INC, DEC) and to generate control signals for the first switch circuit . <EOS>