A low dropout regulator, LDO, comprising: a reference voltage generating circuit and a source follower , the reference voltage generating circuit having a first terminal and a second terminal, the source follower having a first terminal and a second terminal, the first terminal of the reference voltage generating circuit being connected to the first terminal of the source follower , the second terminal of the reference voltage generating circuit being grounded, and the second terminal of the source follower being configured to be connected to a load circuit; wherein the reference voltage generating circuit is configured to generate a reference voltage (V ref ) that changes with temperature, to offset a voltage change caused by a voltage between the first terminal and the second terminal of the source follower changing with the temperature; the reference voltage generating circuit comprises: a first N-Metal-Oxide-Semiconductor (NMOS) transistor (M1) and an adjustable resistor (R0), the first NMOS transistor having a gate, a drain, a source, and a threshold voltage, resistance of the adjustable resistor (R0) being adjustable, and the gate (g) and the drain (d) of the first NMOS transistor (M1) are connected to the first terminal of the source follower , and the source (s) of the first NMOS transistor (M1) is grounded through the adjustable resistor (R0); the source follower comprises: a second NMOS transistor (M2), having a gate, a drain, a source, and a threshold voltage, wherein the gate (g) of the second NMOS transistor (M2) is connected to the drain (d) of the first NMOS transistor (M1), the source (s) of the second NMOS transistor (M2) is configured to be connected to the load circuit, and the drain (d) of the second NMOS transistor (M2) is connected to a power supply voltage (VDD); characterised in that the first NMOS transistor (M1) and the second NMOS transistor (M2) are of a same type, and a channel length of the first NMOS transistor (M1) is the same as a channel length of the second NMOS transistor (M2), and then the threshold voltage V thM1 of the first NMOS transistor (M1) is the same as the threshold voltage V thM2 of the second NMOS transistor (M2). wherein the reference voltage generating circuit is configured to generate a reference voltage (V ref ) that changes with temperature, to offset a voltage change caused by a voltage between the first terminal and the second terminal of the source follower changing with the temperature; the reference voltage generating circuit comprises: a first N-Metal-Oxide-Semiconductor (NMOS) transistor (M1) and an adjustable resistor (R0), the first NMOS transistor having a gate, a drain, a source, and a threshold voltage, resistance of the adjustable resistor (R0) being adjustable, and the gate (g) and the drain (d) of the first NMOS transistor (M1) are connected to the first terminal of the source follower , and the source (s) of the first NMOS transistor (M1) is grounded through the adjustable resistor (R0); the source follower comprises: a second NMOS transistor (M2), having a gate, a drain, a source, and a threshold voltage, wherein the gate (g) of the second NMOS transistor (M2) is connected to the drain (d) of the first NMOS transistor (M1), the source (s) of the second NMOS transistor (M2) is configured to be connected to the load circuit, and the drain (d) of the second NMOS transistor (M2) is connected to a power supply voltage (VDD); characterised in that the first NMOS transistor (M1) and the second NMOS transistor (M2) are of a same type, and a channel length of the first NMOS transistor (M1) is the same as a channel length of the second NMOS transistor (M2), and then the threshold voltage V thM1 of the first NMOS transistor (M1) is the same as the threshold voltage V thM2 of the second NMOS transistor (M2). <EOS>