A semiconductor die with clock control , the semiconductor die comprising: a plurality of pins comprising a supply pin configured, in use, to receive a supply voltage from a power supply, and a first clock interface pin ; and a clock interface circuit configured to output a clock signal, the clock interface circuit coupled to the supply pin and the first clock interface pin , wherein the clock interface circuit comprises: an oscillator configured to generate an oscillator signal; and a first comparator configured to control operation of the clock interface circuit in a selected clock control mode chosen from two or more clock control modes based on comparing an electrical characteristic of the first clock interface pin to a comparison threshold, the clock interface circuit being configured to generate the comparison threshold based on a voltage level of the supply voltage, VDD, wherein the two or more clock control modes includes a first clock control mode in which the clock interface circuit generates the clock signal based on an input clock signal received on the clock interface pin , and a second clock control mode in which the clock interface circuit generates the clock signal based on the oscillator signal. a plurality of pins comprising a supply pin configured, in use, to receive a supply voltage from a power supply, and a first clock interface pin ; and a clock interface circuit configured to output a clock signal, the clock interface circuit coupled to the supply pin and the first clock interface pin , wherein the clock interface circuit comprises: an oscillator configured to generate an oscillator signal; and a first comparator configured to control operation of the clock interface circuit in a selected clock control mode chosen from two or more clock control modes based on comparing an electrical characteristic of the first clock interface pin to a comparison threshold, the clock interface circuit being configured to generate the comparison threshold based on a voltage level of the supply voltage, VDD, wherein the two or more clock control modes includes a first clock control mode in which the clock interface circuit generates the clock signal based on an input clock signal received on the clock interface pin , and a second clock control mode in which the clock interface circuit generates the clock signal based on the oscillator signal. an oscillator configured to generate an oscillator signal; and a first comparator configured to control operation of the clock interface circuit in a selected clock control mode chosen from two or more clock control modes based on comparing an electrical characteristic of the first clock interface pin to a comparison threshold, the clock interface circuit being configured to generate the comparison threshold based on a voltage level of the supply voltage, VDD, wherein the two or more clock control modes includes a first clock control mode in which the clock interface circuit generates the clock signal based on an input clock signal received on the clock interface pin , and a second clock control mode in which the clock interface circuit generates the clock signal based on the oscillator signal. <EOS>