An anti-aliasing filter, AAF , for discretization at a sampling period (Ts), comprising: an operational amplifier having an input terminal (i1) and an output terminal (o1); a first capacitor (C1) coupled between the input terminal (i1) and the output terminal (o1); a second capacitor (C2) coupled between a first node (n1) and a second node (n2); and a first switch (sw1) coupled between the first node (n1) and the input terminal (i1); a second switch (sw2) coupled between the second node (n2) and the output terminal (o1); a first resistor (R1) coupled between a front node (a1) and the input terminal (i1); a third capacitor (C3); and a third switch (sw3) coupled between the third capacitor (C3) and the second capacitor (C2); wherein: during a first phase (p1), the first switch (sw1) and the second switch (sw2) are configured to connect the second capacitor (C2) to the first capacitor (C1); during a second phase (p2), the first switch (sw1) and second switch (sw2) are configured to insulate the second capacitor (C2) from the first capacitor (C1); the first phase (p1) lasts for one said sampling period (Ts), during a middle phase (p1m) between the first phase (p1) and the second phase (p2), the third switch (sw3) is configured to connect the third capacitor (C3) to the second capacitor (C2); and during the first phase (p1) and the second phase (p2), the third switch (sw3) is configured to insulate the third capacitor (C3) from the second capacitor (C2). an operational amplifier having an input terminal (i1) and an output terminal (o1); a first capacitor (C1) coupled between the input terminal (i1) and the output terminal (o1); a second capacitor (C2) coupled between a first node (n1) and a second node (n2); and a first switch (sw1) coupled between the first node (n1) and the input terminal (i1); a second switch (sw2) coupled between the second node (n2) and the output terminal (o1); a first resistor (R1) coupled between a front node (a1) and the input terminal (i1); a third capacitor (C3); and a third switch (sw3) coupled between the third capacitor (C3) and the second capacitor (C2); wherein: during a first phase (p1), the first switch (sw1) and the second switch (sw2) are configured to connect the second capacitor (C2) to the first capacitor (C1); during a second phase (p2), the first switch (sw1) and second switch (sw2) are configured to insulate the second capacitor (C2) from the first capacitor (C1); the first phase (p1) lasts for one said sampling period (Ts), during a middle phase (p1m) between the first phase (p1) and the second phase (p2), the third switch (sw3) is configured to connect the third capacitor (C3) to the second capacitor (C2); and during the first phase (p1) and the second phase (p2), the third switch (sw3) is configured to insulate the third capacitor (C3) from the second capacitor (C2). during a first phase (p1), the first switch (sw1) and the second switch (sw2) are configured to connect the second capacitor (C2) to the first capacitor (C1); during a second phase (p2), the first switch (sw1) and second switch (sw2) are configured to insulate the second capacitor (C2) from the first capacitor (C1); the first phase (p1) lasts for one said sampling period (Ts), during a middle phase (p1m) between the first phase (p1) and the second phase (p2), the third switch (sw3) is configured to connect the third capacitor (C3) to the second capacitor (C2); and during the first phase (p1) and the second phase (p2), the third switch (sw3) is configured to insulate the third capacitor (C3) from the second capacitor (C2). <EOS>