A method for manufacturing a CMOS device, said CMOS device comprising a first transistor structure of a first conductivity type in a first region (I) and a second transistor structure of a second conductivity type, different from the first conductivity type, in a second region (II), the method comprising the following sequence of subsequent steps: - providing a semiconductor base layer having a main upper surface; - epitaxially growing a germanium layer on said main upper surface of said semiconductor base layer , the germanium layer having thickness above a critical thickness such that an upper portion of said germanium layer is strain relaxed; - performing an anneal step at a temperature larger than 800°C; - thinning said germanium layer ; - patterning said germanium layer into germanium fin structures (2") having a longitudinal direction parallel to said main upper surface or into vertical germanium wire structures having a main direction perpendicular on said main upper surface; - laterally embedding said germanium fin structures or vertical germanium wire structures (2") in a dielectric layer ; - providing a masking layer covering said first region (I), leaving the second region (II) exposed; - selectively removing said germanium fin structure or vertical germanium wire structure (2") in said second region (II) up until said main upper surface, resulting in a trench ; - growing a protrusion in said trench by epitaxially growing one or more semiconductor layers in said trench ; wherein at least an upper portion of said protrusion is suitable for being used as a channel structure of said transistor structure of a second conductivity type and wherein at least an upper portion of said germanium fin structure or vertical germanium wire structure (2") is suitable for being used as a channel structure of said transistor structure of a first conductivity type. - providing a semiconductor base layer having a main upper surface; - epitaxially growing a germanium layer on said main upper surface of said semiconductor base layer , the germanium layer having thickness above a critical thickness such that an upper portion of said germanium layer is strain relaxed; - performing an anneal step at a temperature larger than 800°C; - thinning said germanium layer ; - patterning said germanium layer into germanium fin structures (2") having a longitudinal direction parallel to said main upper surface or into vertical germanium wire structures having a main direction perpendicular on said main upper surface; - laterally embedding said germanium fin structures or vertical germanium wire structures (2") in a dielectric layer ; - providing a masking layer covering said first region (I), leaving the second region (II) exposed; - selectively removing said germanium fin structure or vertical germanium wire structure (2") in said second region (II) up until said main upper surface, resulting in a trench ; - growing a protrusion in said trench by epitaxially growing one or more semiconductor layers in said trench ; wherein at least an upper portion of said protrusion is suitable for being used as a channel structure of said transistor structure of a second conductivity type and wherein at least an upper portion of said germanium fin structure or vertical germanium wire structure (2") is suitable for being used as a channel structure of said transistor structure of a first conductivity type. <EOS>