A memory device comprising: a magnetic random access memory, "MRAM", cell including a storage layer having a storage magnetization direction; a sense layer having a sense magnetization direction; and a spacer layer disposed between the storage layer and the sense layer; a bit line electrically coupled through a selection transistor to the MRAM cell; and a field line magnetically coupled to the MRAM cell extending in a direction orthogonal to the bit line and configured to induce a magnetic field along a magnetic field axis ; wherein the storage layer has a single magnetic anisotropy axis ; wherein the single magnetic anisotropy axis is tilted relative to the magnetic field axis; wherein the memory device is configured such that, during a write operation, the storage magnetization direction is switchable between m directions to store data corresponding to one of m logic states, wherein the MRAM cell is implemented as a multi-bit cell with m > 2, at least one of the m directions is aligned along the single magnetic anisotropy axis, and at least another one of the m directions is aligned relative to the magnetic field axis; and wherein the memory device is configured such that, during a read operation, the sense magnetization direction is varied, relative to the storage magnetization direction, to determine the data stored by the storage layer; wherein the memory device is configured such that, when a MRAM cell is to be written, the field line, the bit line and a control line coupled to the selection transistor of the MRAM cell to be written are activated to switch the MRAM cell selection transistor into a saturated on mode allowing a flow of current through the MRAM cell, the bit line thereby inducing a magnetic field, in addition to a magnetic field induced by the field line, in the vicinity of the MRAM cell, such that the MRAM cell is individually addressed and written. a magnetic random access memory, "MRAM", cell including a storage layer having a storage magnetization direction; a sense layer having a sense magnetization direction; and a spacer layer disposed between the storage layer and the sense layer; a storage layer having a storage magnetization direction; a sense layer having a sense magnetization direction; and a spacer layer disposed between the storage layer and the sense layer; a bit line electrically coupled through a selection transistor to the MRAM cell; and a field line magnetically coupled to the MRAM cell extending in a direction orthogonal to the bit line and configured to induce a magnetic field along a magnetic field axis ; wherein the storage layer has a single magnetic anisotropy axis ; wherein the single magnetic anisotropy axis is tilted relative to the magnetic field axis; wherein the memory device is configured such that, during a write operation, the storage magnetization direction is switchable between m directions to store data corresponding to one of m logic states, wherein the MRAM cell is implemented as a multi-bit cell with m > 2, at least one of the m directions is aligned along the single magnetic anisotropy axis, and at least another one of the m directions is aligned relative to the magnetic field axis; and wherein the memory device is configured such that, during a read operation, the sense magnetization direction is varied, relative to the storage magnetization direction, to determine the data stored by the storage layer; wherein the memory device is configured such that, when a MRAM cell is to be written, the field line, the bit line and a control line coupled to the selection transistor of the MRAM cell to be written are activated to switch the MRAM cell selection transistor into a saturated on mode allowing a flow of current through the MRAM cell, the bit line thereby inducing a magnetic field, in addition to a magnetic field induced by the field line, in the vicinity of the MRAM cell, such that the MRAM cell is individually addressed and written. <EOS>