A method of remotely validating memory content on one or more target circuits running at least one application, comprising: associating at least one JTAG scan instrument with one or more JTAG diagnostic ports of a local microcomputer system including at least one of the target circuits ; associating at least one non-JTAG scan instrument with one or more non-JTAG diagnostic ports of the local microcomputer system including at least one of the target circuits ; performing a scan process distinct from a boundary scan process, via the at least one JTAG scan instrument and the at least one non-JTAG scan instrument , via accessing at least one storage element associated with the at least one of the target circuits through the one or more JTAG diagnostic ports (360A, and the one or more non-JTAG diagnostic ports to obtain system data during operation of the application or applications, respectively, operating on the one or more target circuits , the scan process including: halting the running application or applications, respectively, operating on the one or more target circuits ; and reading content related to the running application or applications, respectively, from the at least one storage element in the scan process distinct from a boundary scan process to obtain test data while the application or applications, respectively, are halted; resuming operation of the running application or applications from the state at which the running application or applications, respectively, were halted; transmitting information describing the test data to a remote site; and comparing, at the remote site, the information to known information to confirm desired system configuration and/or operation. associating at least one JTAG scan instrument with one or more JTAG diagnostic ports of a local microcomputer system including at least one of the target circuits ; associating at least one non-JTAG scan instrument with one or more non-JTAG diagnostic ports of the local microcomputer system including at least one of the target circuits ; performing a scan process distinct from a boundary scan process, via the at least one JTAG scan instrument and the at least one non-JTAG scan instrument , via accessing at least one storage element associated with the at least one of the target circuits through the one or more JTAG diagnostic ports (360A, and the one or more non-JTAG diagnostic ports to obtain system data during operation of the application or applications, respectively, operating on the one or more target circuits , the scan process including: halting the running application or applications, respectively, operating on the one or more target circuits ; and reading content related to the running application or applications, respectively, from the at least one storage element in the scan process distinct from a boundary scan process to obtain test data while the application or applications, respectively, are halted; resuming operation of the running application or applications from the state at which the running application or applications, respectively, were halted; halting the running application or applications, respectively, operating on the one or more target circuits ; and reading content related to the running application or applications, respectively, from the at least one storage element in the scan process distinct from a boundary scan process to obtain test data while the application or applications, respectively, are halted; resuming operation of the running application or applications from the state at which the running application or applications, respectively, were halted; transmitting information describing the test data to a remote site; and comparing, at the remote site, the information to known information to confirm desired system configuration and/or operation. <EOS>