A protection circuit for use in a power amplifier said power amplifier comprising an input-stage amplifying circuit (ST1) biased with a first bias current (I B1 ) and supplied with a first supply current (I C1 ), an intermediate stage amplifying circuit (ST2) and an output-stage amplifying circuit (ST3) biased with a third bias current (I B3 ) and supplied with a third supply current (Ics), the protection circuit comprising: a signal strength detecting circuit (PD2) coupled to an RF input end of the output-stage amplifying circuit (ST3) of the power amplifier and configured to generate a first detecting signal (VPD2) according to a signal strength of a radio frequency signal (RF2) at said RF input end, wherein a value of the detecting signal (V PD2 ) is associated with a VSWR signal from the output-stage amplifying circuit (ST3); a current detecting circuit (CD) coupled to an output of a bias circuit (BC3) providing the third bias current (I B3 ) to the output-stage amplifying circuit (ST3) of the power amplifier and configured to detect the third bias current (I B3 ) and generate a corresponding second detecting signal (Vid) wherein a value of the second detecting signal (Vid) is associated with the VSWR signal from the output-stage amplifying circuit (ST3); a logic circuit (Comp2) configured to generate a first plurality of switch control signals (S 3A ,S 3B ,S 3C ) and a second plurality of switch control signals (S 2A ,S 2B ,S 2C ) based on a comparison of a detecting signal (Vs) and a reference signal (V REF2 ), wherein the detecting signal is generated based on the first detecting signal (V PD2 ) and the second detecting signal (Vid); and a switching unit (SW2) configured to lower the third bias current (I B3 ) or the third supply current (Ics) according to the first plurality of switch control signals (S 3A ,S 3B ,S 3C ) and to lower the first bias current (I B1 ) or the first supply current (I C1 ) according to the second plurality of switch control signals (S 2A , S 2B , S 2C ). a signal strength detecting circuit (PD2) coupled to an RF input end of the output-stage amplifying circuit (ST3) of the power amplifier and configured to generate a first detecting signal (VPD2) according to a signal strength of a radio frequency signal (RF2) at said RF input end, wherein a value of the detecting signal (V PD2 ) is associated with a VSWR signal from the output-stage amplifying circuit (ST3); a current detecting circuit (CD) coupled to an output of a bias circuit (BC3) providing the third bias current (I B3 ) to the output-stage amplifying circuit (ST3) of the power amplifier and configured to detect the third bias current (I B3 ) and generate a corresponding second detecting signal (Vid) wherein a value of the second detecting signal (Vid) is associated with the VSWR signal from the output-stage amplifying circuit (ST3); a logic circuit (Comp2) configured to generate a first plurality of switch control signals (S 3A ,S 3B ,S 3C ) and a second plurality of switch control signals (S 2A ,S 2B ,S 2C ) based on a comparison of a detecting signal (Vs) and a reference signal (V REF2 ), wherein the detecting signal is generated based on the first detecting signal (V PD2 ) and the second detecting signal (Vid); and a switching unit (SW2) configured to lower the third bias current (I B3 ) or the third supply current (Ics) according to the first plurality of switch control signals (S 3A ,S 3B ,S 3C ) and to lower the first bias current (I B1 ) or the first supply current (I C1 ) according to the second plurality of switch control signals (S 2A , S 2B , S 2C ). <EOS>