A control system for a double data rate synchronous dynamic random access memory, DDR SDRAM, system, wherein the control system is used in a device, the device comprises the control system, the DDR SDRAM system and functional systems, and the DDR SDRAM system comprises a DDR controller and a DDR PHY, the control system comprising: a monitoring unit , configured to: monitor a working status of each of the functional systems that shares a power domain with the DDR SDRAM system; and determine a target power parameter value and a target clock parameter value of the DDR SDRAM system according to the working status of each of the functional systems; and a control unit , configured to control a power parameter and a clock parameter of the DDR SDRAM system according to the target power parameter value and the target clock parameter value of the DDR SDRAM system, wherein in a process in which the control unit controls the power parameter and the clock parameter of the DDR SDRAM system to change, the DDR SDRAM system is in a self-refresh state; and the control system further comprises: a delay buffer unit , used as a data storage buffer of each of the functional systems when the DDR SDRAM system is in a self-refresh state; wherein the control unit is further configured to: before controlling the power parameter and the clock parameter of the DDR SDRAM system to change, determine whether a data volume of the delay buffer unit reaches a preset data volume; and wherein the control unit is further configured to control the power parameter and the clock parameter of the DDR SDRAM system to change only when it is determined that the data volume of the delay buffer unit reaches the preset data volume. a monitoring unit , configured to: monitor a working status of each of the functional systems that shares a power domain with the DDR SDRAM system; and determine a target power parameter value and a target clock parameter value of the DDR SDRAM system according to the working status of each of the functional systems; and a control unit , configured to control a power parameter and a clock parameter of the DDR SDRAM system according to the target power parameter value and the target clock parameter value of the DDR SDRAM system, wherein in a process in which the control unit controls the power parameter and the clock parameter of the DDR SDRAM system to change, the DDR SDRAM system is in a self-refresh state; and the control system further comprises: a delay buffer unit , used as a data storage buffer of each of the functional systems when the DDR SDRAM system is in a self-refresh state; wherein the control unit is further configured to: before controlling the power parameter and the clock parameter of the DDR SDRAM system to change, determine whether a data volume of the delay buffer unit reaches a preset data volume; and wherein the control unit is further configured to control the power parameter and the clock parameter of the DDR SDRAM system to change only when it is determined that the data volume of the delay buffer unit reaches the preset data volume. a delay buffer unit , used as a data storage buffer of each of the functional systems when the DDR SDRAM system is in a self-refresh state; wherein the control unit is further configured to: before controlling the power parameter and the clock parameter of the DDR SDRAM system to change, determine whether a data volume of the delay buffer unit reaches a preset data volume; and wherein the control unit is further configured to control the power parameter and the clock parameter of the DDR SDRAM system to change only when it is determined that the data volume of the delay buffer unit reaches the preset data volume. <EOS>