A fringe field switching mode liquid crystal display device, comprising: a substrate ; gate and data lines (101, 301; 103) arranged to cross each other on the substrate and define white (W), red (R), green (G) and blue (B) sub-pixels (SP); first through fourth thin film transistors (TFT1, TFT2, TFT3, TFT4) connected to the white (W), red (R), green (G) and blue (B) sub-pixels (SP), respectively; common electrodes disposed in the white (W), red (R), green (G) and blue (B) sub-pixels (SP); and white, red, green and blue pixel electrodes (WP, RP, GP, BP) disposed to overlap with the common electrodes within the white (W), red (R), green (G) and blue (B) sub-pixels (SP); wherein the areas of the red (R), green (G) and blue (B) sub-pixels (SP) are larger than that of the white (W) sub-pixel (SP); wherein the first and second thin film transistors (TFT1, TFT2) are disposed in an adjacent region to a bottom edge of the white (W) sub-pixel (SP), and the third and fourth thin film transistors (TFT3, TFT4) are disposed in another adjacent region to a top edge of the white (W) sub-pixel (SP); and wherein the white pixel electrode (WP) includes: two horizontal bars disposed parallel to the gate lines , including a first horizontal bar disposed in a bottom edge region of the white sub-pixel (WP) adjacent to one gate line and a second horizontal bar disposed in a top edge region of the white sub-pixel (WP) adjacent to another gate line ; vertical bars disposed between the horizontal bars in parallel with the data lines ; a first extensive portion configured to extend from the first horizontal bar along the downward direction of the white (W) sub-pixel (SP) parallel to the data lines , and a second extensive portion configured to extend from the second horizontal bar along the upward direction of the white (W) sub-pixel (SP) parallel to the data lines , wherein the white sub-pixel (W) includes a storage capacitor formed between the white pixel electrode (WP) and the common electrode disposed under the white pixel electrode (WP). a substrate ; gate and data lines (101, 301; 103) arranged to cross each other on the substrate and define white (W), red (R), green (G) and blue (B) sub-pixels (SP); first through fourth thin film transistors (TFT1, TFT2, TFT3, TFT4) connected to the white (W), red (R), green (G) and blue (B) sub-pixels (SP), respectively; common electrodes disposed in the white (W), red (R), green (G) and blue (B) sub-pixels (SP); and white, red, green and blue pixel electrodes (WP, RP, GP, BP) disposed to overlap with the common electrodes within the white (W), red (R), green (G) and blue (B) sub-pixels (SP); wherein the areas of the red (R), green (G) and blue (B) sub-pixels (SP) are larger than that of the white (W) sub-pixel (SP); wherein the first and second thin film transistors (TFT1, TFT2) are disposed in an adjacent region to a bottom edge of the white (W) sub-pixel (SP), and the third and fourth thin film transistors (TFT3, TFT4) are disposed in another adjacent region to a top edge of the white (W) sub-pixel (SP); two horizontal bars disposed parallel to the gate lines , including a first horizontal bar disposed in a bottom edge region of the white sub-pixel (WP) adjacent to one gate line and a second horizontal bar disposed in a top edge region of the white sub-pixel (WP) adjacent to another gate line ; vertical bars disposed between the horizontal bars in parallel with the data lines ; a first extensive portion configured to extend from the first horizontal bar along the downward direction of the white (W) sub-pixel (SP) parallel to the data lines , and a second extensive portion configured to extend from the second horizontal bar along the upward direction of the white (W) sub-pixel (SP) parallel to the data lines , wherein the white sub-pixel (W) includes a storage capacitor formed between the white pixel electrode (WP) and the common electrode disposed under the white pixel electrode (WP). <EOS>