A field effect transistor, wherein the field effect transistor comprises: a substrate layer , wherein a first gate structure and a second gate structure are disposed in respective grooves in an upper surface of the substrate layer ; a bottom gate insulation layer covering the upper surface of the substrate layer ; a channel layer covering an upper surface of the bottom gate insulation layer , wherein the channel layer uses one of graphene, molybdenum disulfide, black phosphorus, or another two-dimensional material; a top gate insulation layer covering an upper surface of the channel layer , wherein a first source structure , a second source structure , and a drain disposed between the first source structure and the second source structure , are disposed on a lower surface of the top gate insulation layer ; a third gate structure and a fourth gate structure ; the third gate structure is disposed in a first projection region, of the first gate structure , on the top gate insulation layer , and the first projection region is located between the first source structure and the drain ; and the fourth gate structure is disposed in a second projection region, of the second gate structure 1032B, on the top gate insulation layer , and the second projection region is located between the second source structure and the drain ; wherein the field effect transistor is characterized in that the third gate structure and the fourth gate structure are disposed in respective grooves in an upper surface of the top gate insulation layer , and in that two edges of the first projection region coincide with an edge of the first source structure and an edge of the drain , respectively, and two edges of the second projection region coincide with an edge of the second source structure and an edge of the drain , respectively. a substrate layer , wherein a first gate structure and a second gate structure are disposed in respective grooves in an upper surface of the substrate layer ; a bottom gate insulation layer covering the upper surface of the substrate layer ; a channel layer covering an upper surface of the bottom gate insulation layer , wherein the channel layer uses one of graphene, molybdenum disulfide, black phosphorus, or another two-dimensional material; a top gate insulation layer covering an upper surface of the channel layer , wherein a first source structure , a second source structure , and a drain disposed between the first source structure and the second source structure , are disposed on a lower surface of the top gate insulation layer ; a third gate structure and a fourth gate structure ; the third gate structure is disposed in a first projection region, of the first gate structure , on the top gate insulation layer , and the first projection region is located between the first source structure and the drain ; and the fourth gate structure is disposed in a second projection region, of the second gate structure 1032B, on the top gate insulation layer , and the second projection region is located between the second source structure and the drain ; wherein the field effect transistor is characterized in that the third gate structure and the fourth gate structure are disposed in respective grooves in an upper surface of the top gate insulation layer , and in that two edges of the first projection region coincide with an edge of the first source structure and an edge of the drain , respectively, and two edges of the second projection region coincide with an edge of the second source structure and an edge of the drain , respectively. <EOS>