An apparatus comprising: a plurality of multi-level drivers configured to receive a set of input bits and to responsively generate an ensemble of signals, each multi-level driver of the plurality of multi-level drivers connected to a respective wire of a multi-wire bus and configured to generate a respective signal of the ensemble of signals, characterized in that each multi-level driver comprising: a data buffer comprising inverting and non-inverting buffers configured to receive a subset of the set of input bits, the received subset of input bits corresponding to a respective group of sub-channels associated with the respective wire, the data buffer configured to apply each input bit of the subset of input bits to a respective inverting or non-inverting buffer as determined by a sign of a corresponding wire-specific sub-channel weight of a set of wire-specific sub-channel weights associated with the respective wire; a plurality of sub-channel driver element groups connected to an output of the data buffer , each sub-channel driver element group configured to generate a respective weighted analog signal component of a plurality of weighted analog signal components, each sub-channel driver element group having a number of enabled driver elements connected in parallel, the number predetermined in accordance with a magnitude of a corresponding wire-specific sub-channel weight of the set of wire-specific sub-channel weights associated with the respective wire; and a common node connected between the plurality of sub-channel driver element groups and the respective wire configured to generate the respective signal by forming an analog summation of the plurality of weighted analog signal components and to responsively transmit the respective signal over the respective wire of the multi-wire bus. a data buffer comprising inverting and non-inverting buffers configured to receive a subset of the set of input bits, the received subset of input bits corresponding to a respective group of sub-channels associated with the respective wire, the data buffer configured to apply each input bit of the subset of input bits to a respective inverting or non-inverting buffer as determined by a sign of a corresponding wire-specific sub-channel weight of a set of wire-specific sub-channel weights associated with the respective wire; a plurality of sub-channel driver element groups connected to an output of the data buffer , each sub-channel driver element group configured to generate a respective weighted analog signal component of a plurality of weighted analog signal components, each sub-channel driver element group having a number of enabled driver elements connected in parallel, the number predetermined in accordance with a magnitude of a corresponding wire-specific sub-channel weight of the set of wire-specific sub-channel weights associated with the respective wire; and a common node connected between the plurality of sub-channel driver element groups and the respective wire configured to generate the respective signal by forming an analog summation of the plurality of weighted analog signal components and to responsively transmit the respective signal over the respective wire of the multi-wire bus. <EOS>