An apparatus comprising: address translation circuitry configured to perform a translation of virtual addresses into physical addresses in dependence on stored page table mappings between the virtual addresses and the physical addresses , wherein the stored page table mappings comprise tag-guard control information ; and memory access circuitry configured to perform a tag-guarded memory access in response to a target physical address , the tag-guarded memory access comprising a guard-tag check of comparing an address tag associated with the target physical address with a guard tag stored in association with a block of one or more memory locations comprising an addressed location identified by the target physical address , wherein the memory access circuitry is arranged to perform a non-tag-guarded memory access to the addressed location in response to the target physical address without performing the guard-tag check in dependence on the tag-guard control information , wherein the stored page table mappings comprise plural tag-guard control bits for each page table entry and the memory access circuitry is responsive to at least one of the plural tag-guard control bits having a predetermined first value to perform the tag-guarded memory access to the addressed location and the memory access circuitry is responsive to the tag-guard control bit having a predetermined second value to perform the non-tag-guarded memory access to the addressed location without performing the guard-tag check, wherein the plural tag-guard control bits for each page table entry specify tag-check rules dependent on a type of the memory access. address translation circuitry configured to perform a translation of virtual addresses into physical addresses in dependence on stored page table mappings between the virtual addresses and the physical addresses , wherein the stored page table mappings comprise tag-guard control information ; and memory access circuitry configured to perform a tag-guarded memory access in response to a target physical address , the tag-guarded memory access comprising a guard-tag check of comparing an address tag associated with the target physical address with a guard tag stored in association with a block of one or more memory locations comprising an addressed location identified by the target physical address , wherein the memory access circuitry is arranged to perform a non-tag-guarded memory access to the addressed location in response to the target physical address without performing the guard-tag check in dependence on the tag-guard control information , wherein the stored page table mappings comprise plural tag-guard control bits for each page table entry and the memory access circuitry is responsive to at least one of the plural tag-guard control bits having a predetermined first value to perform the tag-guarded memory access to the addressed location and the memory access circuitry is responsive to the tag-guard control bit having a predetermined second value to perform the non-tag-guarded memory access to the addressed location without performing the guard-tag check, wherein the plural tag-guard control bits for each page table entry specify tag-check rules dependent on a type of the memory access. <EOS>