An amplifier, comprising: a Field Effect Transistor, FET (Q1); a Radio Frequency, RF, power level detector circuit with an output terminal for producing a control signal in accordance with a power level of an RF input signal fed to an input (RF IN ) of the amplifier, such control signal indicating whether the power level of the RF input signal is within a predetermined range of power levels greater than zero; and a bias circuit , configured to be fed by the control signal, for producing a fixed bias voltage at a gate electrode (G) of the FET (Q1) to establish a predetermined quiescent current for the FET (Q1) when the control signal indicates the power level of the RF input signal is within the predetermined range of power levels greater than zero and to reduce the bias voltage to reduce the predetermined quiescent current when the control signal indicates the power level of the RF input signal is below the predetermined range of power levels, wherein the RF power level detector circuit comprises a plurality of serially connected diodes (D a , D b , D c , D d ) connected between the input (RF IN ) of the amplifier and a terminal through a DC blocking capacitor (Ca), the terminal being connected to a voltage source (-V EE ) through a resistor (Ra), to a reference potential through a capacitor (Cb), and to the output terminal through a further resistor (Rb), so that the voltage of the control signal at the output terminal is the voltage source (-V EE ) when the RF input signal is below the predetermined range of power levels, and is more positive than the voltage source (-V EE ) when the RF input signal is within the predetermined range of power levels greater than zero and ranging from a power level established by the number of the plurality of the serially connected diodes (Da, Db, Dc, Dd) to a greater power level. a Field Effect Transistor, FET (Q1); a Radio Frequency, RF, power level detector circuit with an output terminal for producing a control signal in accordance with a power level of an RF input signal fed to an input (RF IN ) of the amplifier, such control signal indicating whether the power level of the RF input signal is within a predetermined range of power levels greater than zero; and a bias circuit , configured to be fed by the control signal, for producing a fixed bias voltage at a gate electrode (G) of the FET (Q1) to establish a predetermined quiescent current for the FET (Q1) when the control signal indicates the power level of the RF input signal is within the predetermined range of power levels greater than zero and to reduce the bias voltage to reduce the predetermined quiescent current when the control signal indicates the power level of the RF input signal is below the predetermined range of power levels, wherein the RF power level detector circuit comprises a plurality of serially connected diodes (D a , D b , D c , D d ) connected between the input (RF IN ) of the amplifier and a terminal through a DC blocking capacitor (Ca), the terminal being connected to a voltage source (-V EE ) through a resistor (Ra), to a reference potential through a capacitor (Cb), and to the output terminal through a further resistor (Rb), so that the voltage of the control signal at the output terminal is the voltage source (-V EE ) when the RF input signal is below the predetermined range of power levels, and is more positive than the voltage source (-V EE ) when the RF input signal is within the predetermined range of power levels greater than zero and ranging from a power level established by the number of the plurality of the serially connected diodes (Da, Db, Dc, Dd) to a greater power level. <EOS>