A nonvolatile memory device (400a-k) comprising: a memory cell array , wherein the memory cell array includes a plurality of word-lines (WL) stacked on a substrate (SUB), a plurality of memory cells (MC) provided in a plurality of channel holes (CH) extending in a vertical direction with respect to the substrate (SUB) and a word-line cut region (WLC) extending in a first horizontal direction and dividing the plurality of word-lines (WL) into a plurality of memory blocks (BLK); and a control circuit configured to control the memory cell array , wherein a plurality of target memory cells coupled to each of the plurality of word-lines (WL) are grouped into outer cells and inner cells based on a location index of each of the plurality of memory cells (MC), a distance (D11) between the outer cell and the word-line cut region (WLC) being smaller than a distance (D12) between the inner cell and the word-line cut region (WLC), and wherein the control circuit is configured to control performance of a program operation on target memory cells coupled to a target word-line of the plurality of word-lines (WL) such that each of the outer cells stores a first number of bits and each of the inner cells stores a second number of bits, the first number being a natural number greater than zero and the second number being a natural number greater than the first number, and wherein the control circuit is configured to adjust levels of read voltages associated with a read operation performed on the target memory cell such that at least one of first threshold voltage distributions of the outer cells and at least one of second threshold voltage distributions of the inner cells are discriminated by a same read voltage. a memory cell array , wherein the memory cell array includes a plurality of word-lines (WL) stacked on a substrate (SUB), a plurality of memory cells (MC) provided in a plurality of channel holes (CH) extending in a vertical direction with respect to the substrate (SUB) and a word-line cut region (WLC) extending in a first horizontal direction and dividing the plurality of word-lines (WL) into a plurality of memory blocks (BLK); and a control circuit configured to control the memory cell array , wherein a plurality of target memory cells coupled to each of the plurality of word-lines (WL) are grouped into outer cells and inner cells based on a location index of each of the plurality of memory cells (MC), a distance (D11) between the outer cell and the word-line cut region (WLC) being smaller than a distance (D12) between the inner cell and the word-line cut region (WLC), and wherein the control circuit is configured to control performance of a program operation on target memory cells coupled to a target word-line of the plurality of word-lines (WL) such that each of the outer cells stores a first number of bits and each of the inner cells stores a second number of bits, the first number being a natural number greater than zero and the second number being a natural number greater than the first number, and wherein the control circuit is configured to adjust levels of read voltages associated with a read operation performed on the target memory cell such that at least one of first threshold voltage distributions of the outer cells and at least one of second threshold voltage distributions of the inner cells are discriminated by a same read voltage. <EOS>