Microelectronic device comprising: • a first field effect transistor comprising a first active layer as well as a first drain , a first source , a first gate surmounting the first active layer , • a second field effect transistor comprising a second active layer as well as a second drain , a second source and a second gate surmounting the second active layer , the second source being electrically connected to the first drain , • a first rear electrode , underlying the first active layer in a stack direction (Z) perpendicular to a transverse plane (XY) defined by a first direction (X) and a second direction (Y), the first rear electrode being electrically connected to the first source , • a second rear electrode , underlying the second active layer in the stack direction (Z), the second rear electrode being separated from the first rear electrode , the second rear electrode being electrically connected to the second source , • a stack , where the stack comprises: • a continuous and GaN-based third active layer , underlying the first active layer , on the one hand, and underlying the second active layer , on the other hand, and • an insulating layer extending, in the stack direction (Z), between the first rear electrode and the first active layer , on the one hand, and the second rear electrode and the second active layer , on the other hand, the insulating layer being continuous and with the basis of a first dielectric, the insulating layer having, in the stack direction (Z), a critical field E c , the insulating layer having, in the stack direction (Z), a thickness called dielectric thickness e 1500 of between 2*e 1500,min and 10*e 1500,min , with e 1500,min =V target /E c , V target being a target breakdown voltage of the insulating layer , the first dielectric having a heat conductivity λ 1 greater than 1W.m -1 .K -1 . • a first field effect transistor comprising a first active layer as well as a first drain , a first source , a first gate surmounting the first active layer , • a second field effect transistor comprising a second active layer as well as a second drain , a second source and a second gate surmounting the second active layer , the second source being electrically connected to the first drain , • a first rear electrode , underlying the first active layer in a stack direction (Z) perpendicular to a transverse plane (XY) defined by a first direction (X) and a second direction (Y), the first rear electrode being electrically connected to the first source , • a second rear electrode , underlying the second active layer in the stack direction (Z), the second rear electrode being separated from the first rear electrode , the second rear electrode being electrically connected to the second source , • a stack , • a continuous and GaN-based third active layer , underlying the first active layer , on the one hand, and underlying the second active layer , on the other hand, and • an insulating layer extending, in the stack direction (Z), between the first rear electrode and the first active layer , on the one hand, and the second rear electrode and the second active layer , on the other hand, the insulating layer being continuous and with the basis of a first dielectric, the insulating layer having, in the stack direction (Z), a critical field E c , the insulating layer having, in the stack direction (Z), a thickness called dielectric thickness e 1500 of between 2*e 1500,min and 10*e 1500,min , with e 1500,min =V target /E c , V target being a target breakdown voltage of the insulating layer , the first dielectric having a heat conductivity λ 1 greater than 1W.m -1 .K -1 . <EOS>