An apparatus, comprising: a set of NAND strings (NS1, NS2, 700n-703n, 710n-713n, 720n-723n, 730n-733n), each NAND string of the set of NAND strings comprising a corresponding drain-end select gate transistor at a drain end of the NAND string; a set of word lines (WLLO-WLL31) connected to memory cells (680a, 681a, 682a, 683a, 684a and 685a, 703-716, 723-736, 743-756, 763-776) in the set of NAND strings; a set of bit lines (BL0-BL3) connected to the set of NAND strings; and a control circuit configured to, in a program loop for a selected word line (WL14) of the set of word lines: increase a voltage of the selected word line to a pass voltage (Vpass), increase the voltage of the selected word line from the pass voltage to a program voltage (Vpgm), increase a voltage of one drain-side word line (WL16-WL31) of the selected word line to the pass voltage, wherein a start of the increase of voltage of the selected word line to the pass voltage is after a start of the increase of the voltage of the one drain-side word line to the pass voltage, and wherein another drain-side word line (WL15) of the selected word line is between the one drain-side word line and the selected word line; the control circuit is further configured to, in the program loop, increase a voltage of the another drain-side side word line to the pass voltage; the apparatus characterised in that the control circuit is such that a start of the increase of the voltage of the another drain-side word line to the pass voltage is before the start of the increase of the voltage of the selected word line to the pass voltage and after the start of the increase of the voltage of the one drain-side word line to the pass voltage. a set of NAND strings (NS1, NS2, 700n-703n, 710n-713n, 720n-723n, 730n-733n), each NAND string of the set of NAND strings comprising a corresponding drain-end select gate transistor at a drain end of the NAND string; a set of word lines (WLLO-WLL31) connected to memory cells (680a, 681a, 682a, 683a, 684a and 685a, 703-716, 723-736, 743-756, 763-776) in the set of NAND strings; a set of bit lines (BL0-BL3) connected to the set of NAND strings; and a control circuit configured to, in a program loop for a selected word line (WL14) of the set of word lines: increase a voltage of the selected word line to a pass voltage (Vpass), increase the voltage of the selected word line from the pass voltage to a program voltage (Vpgm), increase a voltage of one drain-side word line (WL16-WL31) of the selected word line to the pass voltage, wherein a start of the increase of voltage of the selected word line to the pass voltage is after a start of the increase of the voltage of the one drain-side word line to the pass voltage, and wherein another drain-side word line (WL15) of the selected word line is between the one drain-side word line and the selected word line; the control circuit is further configured to, in the program loop, increase a voltage of the another drain-side side word line to the pass voltage; the apparatus characterised in that the control circuit is such that a start of the increase of the voltage of the another drain-side word line to the pass voltage is before the start of the increase of the voltage of the selected word line to the pass voltage and after the start of the increase of the voltage of the one drain-side word line to the pass voltage. <EOS>