A display substrate, comprising: a base substrate ; a plurality of pixel circuits on the base substrate ; and a plurality of pixels in an array and on a side of the plurality of pixel circuits away from the base substrate ; wherein each of the plurality of pixels comprises a first sub-pixel , a second sub-pixel and a third sub-pixel ; orthographic projections of the first sub-pixel , the second sub-pixel and the third sub-pixel on the base substrate do not overlap with each other; the first sub-pixel , the second sub-pixel and the third sub-pixel are electrically connected to corresponding ones of the plurality of pixel circuits in a one-to-one correspondence; the first sub-pixel and the second sub-pixel are separated from each other by a first distance in a first direction (Y), and a first via is arranged in the first distance; the first sub-pixel and the third sub-pixel are separated from each other by a second distance in the first direction (Y), and a first via is arranged in the second distance; and the second sub-pixel and the third sub-pixel are separated from each other by a third distance in the first direction (Y), wherein each of the plurality of pixel circuits comprises a driving transistor and an insulating layer ; each of the first sub-pixel , the second sub-pixel and the third sub-pixel comprises an anode ; the driving transistor , the insulating layer and the anode are sequentially arranged away from the base substrate ; wherein the first via is formed in the insulating layer , and configured to connect the anode of each of the first sub-pixel , the second sub-pixel and the third sub-pixel to the first electrode of the driving transistor in a respective one of plurality of pixel circuits, characterized in that the first vias corresponding to the first sub-pixel , the second sub-pixel and the third sub-pixel in a same pixel are on a same line extending in a second direction (X), wherein the first direction (Y) is perpendicular to the second direction (X). a base substrate ; a plurality of pixel circuits on the base substrate ; and a plurality of pixels in an array and on a side of the plurality of pixel circuits away from the base substrate ; wherein each of the plurality of pixels comprises a first sub-pixel , a second sub-pixel and a third sub-pixel ; orthographic projections of the first sub-pixel , the second sub-pixel and the third sub-pixel on the base substrate do not overlap with each other; the first sub-pixel , the second sub-pixel and the third sub-pixel are electrically connected to corresponding ones of the plurality of pixel circuits in a one-to-one correspondence; the first sub-pixel and the second sub-pixel are separated from each other by a first distance in a first direction (Y), and a first via is arranged in the first distance; the first sub-pixel and the third sub-pixel are separated from each other by a second distance in the first direction (Y), and a first via is arranged in the second distance; and the second sub-pixel and the third sub-pixel are separated from each other by a third distance in the first direction (Y), wherein each of the plurality of pixel circuits comprises a driving transistor and an insulating layer ; each of the first sub-pixel , the second sub-pixel and the third sub-pixel comprises an anode ; the driving transistor , the insulating layer and the anode are sequentially arranged away from the base substrate ; wherein the first via is formed in the insulating layer , and configured to connect the anode of each of the first sub-pixel , the second sub-pixel and the third sub-pixel to the first electrode of the driving transistor in a respective one of plurality of pixel circuits, characterized in that the first vias corresponding to the first sub-pixel , the second sub-pixel and the third sub-pixel in a same pixel are on a same line extending in a second direction (X), wherein the first direction (Y) is perpendicular to the second direction (X). <EOS>