A power testing device configured for testing power providing capabilities of a device under test , the power testing device comprising: a communication port including a plurality of pins, the communication port being configured for, in operation, receiving signals from the device under test via a cable that includes a plurality of wires (112a-h) electrically coupled to the pins of the communication port; first test circuitry electrically coupled to a first set of pairs of the pins of the communication port; second test circuitry electrically coupled to a second set of pairs of the pins of the communication port; a switch electrically coupled to at least one of the first test circuitry and the second test circuitry, wherein, while the switch is in a first state, the first test circuitry and the second test circuitry are electrically isolated from each other, and wherein, while the switch is in a second state, the first test circuitry and the second test circuitry are not electrically isolated from each other; a processor coupled to the first test circuitry, the second test circuitry, and the switch; and a memory coupled to the processor, the memory storing processor-readable instructions that, when executed by the processor, cause the processor to: control operation of the first test circuitry; control operation of the second test circuitry; and control the switch to be in one of the first state or the second state. a communication port including a plurality of pins, the communication port being configured for, in operation, receiving signals from the device under test via a cable that includes a plurality of wires (112a-h) electrically coupled to the pins of the communication port; first test circuitry electrically coupled to a first set of pairs of the pins of the communication port; second test circuitry electrically coupled to a second set of pairs of the pins of the communication port; a switch electrically coupled to at least one of the first test circuitry and the second test circuitry, wherein, while the switch is in a first state, the first test circuitry and the second test circuitry are electrically isolated from each other, and wherein, while the switch is in a second state, the first test circuitry and the second test circuitry are not electrically isolated from each other; wherein, while the switch is in a first state, the first test circuitry and the second test circuitry are electrically isolated from each other, and wherein, while the switch is in a second state, the first test circuitry and the second test circuitry are not electrically isolated from each other; a processor coupled to the first test circuitry, the second test circuitry, and the switch; and a memory coupled to the processor, the memory storing processor-readable instructions that, when executed by the processor, cause the processor to: control operation of the first test circuitry; control operation of the second test circuitry; and control the switch to be in one of the first state or the second state. control operation of the first test circuitry; control operation of the second test circuitry; and control the switch to be in one of the first state or the second state. <EOS>