An analog beamformer comprising: an input circuit configured to receive an input signal (Vin) to generate a first input signal (SI1) having the same phase as the input signal (Vin) and a second input signal (SI2) having a phase difference corresponding to a first phase with respect to the input signal (Vin); a first delay circuit configured to receive the first input signal (SI1) and delay the first input signal (SI1) by a beamforming delay time to output a first delayed signal (SD1); a second delay circuit configured to receive the second input signal (SI2) and delay the second input signal (SI2) by the beamforming delay time to output a second delayed signal (SD2); and an output circuit configured to output an output signal (Vout) by summing the first delayed signal (SD1) and the second delayed signal (SD2), wherein a first write signal (CW1) controlling an input of the first delay circuit has the phase difference corresponding to the first phase with respect to a second write signal (CW2) controlling an input of the second delay circuit , and a first read signal (CR1) controlling an output of the first delay circuit has the phase difference corresponding to the first phase with respect to a second read signal (CR2) controlling an output of the second delay circuit , wherein the first delay circuit is further configured to hold the first input signal (SI1) in response to the first write signal (CW1) and output the first delayed signal (SD1) in response to the first read signal (CR1) that is delayed by the beamforming delay time with respect to the first write signal (CW1), and wherein the second delay circuit is further configured to hold the second input signal (SI2) in response to the second write signal (CW2) and output the second delayed signal (SD2) in response to the second read signal (CR2) that is delayed by the beamforming delay time with respect to the second write signal (CW2). an input circuit configured to receive an input signal (Vin) to generate a first input signal (SI1) having the same phase as the input signal (Vin) and a second input signal (SI2) having a phase difference corresponding to a first phase with respect to the input signal (Vin); a first delay circuit configured to receive the first input signal (SI1) and delay the first input signal (SI1) by a beamforming delay time to output a first delayed signal (SD1); a second delay circuit configured to receive the second input signal (SI2) and delay the second input signal (SI2) by the beamforming delay time to output a second delayed signal (SD2); and an output circuit configured to output an output signal (Vout) by summing the first delayed signal (SD1) and the second delayed signal (SD2), wherein a first write signal (CW1) controlling an input of the first delay circuit has the phase difference corresponding to the first phase with respect to a second write signal (CW2) controlling an input of the second delay circuit , and a first read signal (CR1) controlling an output of the first delay circuit has the phase difference corresponding to the first phase with respect to a second read signal (CR2) controlling an output of the second delay circuit , wherein the first delay circuit is further configured to hold the first input signal (SI1) in response to the first write signal (CW1) and output the first delayed signal (SD1) in response to the first read signal (CR1) that is delayed by the beamforming delay time with respect to the first write signal (CW1), and wherein the second delay circuit is further configured to hold the second input signal (SI2) in response to the second write signal (CW2) and output the second delayed signal (SD2) in response to the second read signal (CR2) that is delayed by the beamforming delay time with respect to the second write signal (CW2). <EOS>