A III-nitride power semiconductor package comprising: a substrate ; a III-nitride power semiconductor device including a first high electron mobility transistor (HEMT) comprising: a first III-nitride layer ; a second III-nitride layer forming a heterojunction with said first III-nitride layer; a field nitride layer and a gate nitride on said second III-nitride layer ; a gate metal on said gate nitride ; a plurality of interconnect metal layers including a top metal layer and a bottom metal layer on said second III-nitride layer , said bottom metal layer including a source contact, a drain contact, and a gate contact on said gate metal ; a plurality of vias interconnecting said plurality of interconnect metal layers through a plurality of dielectric layers to connect said source contact, said drain contact, and said gate contact to said top metal layer , and, a solderable front metal on said top metal layer , said solderable front metal comprising spaced elongated digits; solder bars running substantially parallel with said solderable front metal , said spaced elongated digits being configured for external circuit connection through said solder bars, wherein said solderable front metal is coupled to said substrate through said solder bars . a substrate ; a III-nitride power semiconductor device including a first high electron mobility transistor (HEMT) comprising: a first III-nitride layer ; a second III-nitride layer forming a heterojunction with said first III-nitride layer; a field nitride layer and a gate nitride on said second III-nitride layer ; a gate metal on said gate nitride ; a plurality of interconnect metal layers including a top metal layer and a bottom metal layer on said second III-nitride layer , said bottom metal layer including a source contact, a drain contact, and a gate contact on said gate metal ; a plurality of vias interconnecting said plurality of interconnect metal layers through a plurality of dielectric layers to connect said source contact, said drain contact, and said gate contact to said top metal layer , and, a solderable front metal on said top metal layer , said solderable front metal comprising spaced elongated digits; a first III-nitride layer ; a second III-nitride layer forming a heterojunction with said first III-nitride layer; a field nitride layer and a gate nitride on said second III-nitride layer ; a gate metal on said gate nitride ; a plurality of interconnect metal layers including a top metal layer and a bottom metal layer on said second III-nitride layer , said bottom metal layer including a source contact, a drain contact, and a gate contact on said gate metal ; a plurality of vias interconnecting said plurality of interconnect metal layers through a plurality of dielectric layers to connect said source contact, said drain contact, and said gate contact to said top metal layer , and, a solderable front metal on said top metal layer , said solderable front metal comprising spaced elongated digits; solder bars running substantially parallel with said solderable front metal , said spaced elongated digits being configured for external circuit connection through said solder bars, wherein said solderable front metal is coupled to said substrate through said solder bars . <EOS>