An integrated circuit, comprising: i. a host substrate ; ii. optionally, a first layer overlaying the host substrate , the first layer optionally comprising a first transistor ; iii. a second layer overlaying the host substrate and the first layer , if present, the second layer comprising a second transistor ; and iv. an electromagnetic shielding structure shielding the second transistor from electromagnetic fields, comprising - a bottom underlying the second transistor and comprised in the host substrate , the first layer , if present, or the second layer , - one or more lateral sides laterally bordering the second transistor , and - optionally, a top overlaying the second transistor ; wherein the bottom , each of the one or more lateral sides and, if present, the top each comprise at least one shielding element independently made up of either an electrically conductive material or a trap-rich material selected from trap-rich polycrystalline silicon and trap-rich amorphous silicon, the trap rich material having a trap density of at least 10 22 cm -3 , characterized in that the bottom , each of the one or more lateral sides and, if present, the top do not each comprise at least one shielding element made up of an electrically conductive material. i. a host substrate ; ii. optionally, a first layer overlaying the host substrate , the first layer optionally comprising a first transistor ; iii. a second layer overlaying the host substrate and the first layer , if present, the second layer comprising a second transistor ; and iv. an electromagnetic shielding structure shielding the second transistor from electromagnetic fields, comprising - a bottom underlying the second transistor and comprised in the host substrate , the first layer , if present, or the second layer , - one or more lateral sides laterally bordering the second transistor , and - optionally, a top overlaying the second transistor ; wherein the bottom , each of the one or more lateral sides and, if present, the top each comprise at least one shielding element independently made up of either an electrically conductive material or a trap-rich material selected from trap-rich polycrystalline silicon and trap-rich amorphous silicon, the trap rich material having a trap density of at least 10 22 cm -3 , characterized in that the bottom , each of the one or more lateral sides and, if present, the top do not each comprise at least one shielding element made up of an electrically conductive material. - a bottom underlying the second transistor and comprised in the host substrate , the first layer , if present, or the second layer , - one or more lateral sides laterally bordering the second transistor , and - optionally, a top overlaying the second transistor ; wherein the bottom , each of the one or more lateral sides and, if present, the top each comprise at least one shielding element independently made up of either an electrically conductive material or a trap-rich material selected from trap-rich polycrystalline silicon and trap-rich amorphous silicon, the trap rich material having a trap density of at least 10 22 cm -3 , characterized in that the bottom , each of the one or more lateral sides and, if present, the top do not each comprise at least one shielding element made up of an electrically conductive material. wherein the bottom , each of the one or more lateral sides and, if present, the top each comprise at least one shielding element independently made up of either an electrically conductive material or a trap-rich material selected from trap-rich polycrystalline silicon and trap-rich amorphous silicon, the trap rich material having a trap density of at least 10 22 cm -3 , characterized in that the bottom , each of the one or more lateral sides and, if present, the top do not each comprise at least one shielding element made up of an electrically conductive material. <EOS>