A semiconductor device comprising: a voltage line to which a first voltage is applied; a first circuit configured to operate by using the first voltage; and a second circuit configured to control a connection between the voltage line and the first circuit; wherein the second circuit includes: at least one first switch circuit including a plurality of first switch cells (SC); and a second switch circuit including a plurality of switch sections (291-1 to 291-5), the plurality of first switch cells are configured to connect the first circuit and the voltage line based on a first control signal (PSW_ENa), the plurality of switch sections are configured to connect the first circuit and the voltage line based on a plurality of second control signals (PSW_ENb1 to PSW ENb5) different from the first control signal, each of the plurality of second control signals is asserted at different timings, the first switch circuit outputs a delayed signal (PSW_ACK) of the first control signal after the plurality of first switch cells are sequentially turned on, each of the plurality of switch sections is set to an on state at different timings based on the plurality of second control signals, and a first switch section (291-1) of the plurality of switch sections is turned on based on the delayed signal and a first signal (PSW_ENb1) of the plurality of second control signals, characterized in that the delayed signal indicates that the connection between the first circuit and the voltage line via the first switch circuit is complete having completed turn-on of the switching elements in the first switch circuit. a voltage line to which a first voltage is applied; a first circuit configured to operate by using the first voltage; and a second circuit configured to control a connection between the voltage line and the first circuit; wherein the second circuit includes: at least one first switch circuit including a plurality of first switch cells (SC); and a second switch circuit including a plurality of switch sections (291-1 to 291-5), at least one first switch circuit including a plurality of first switch cells (SC); and a second switch circuit including a plurality of switch sections (291-1 to 291-5), the plurality of first switch cells are configured to connect the first circuit and the voltage line based on a first control signal (PSW_ENa), the plurality of switch sections are configured to connect the first circuit and the voltage line based on a plurality of second control signals (PSW_ENb1 to PSW ENb5) different from the first control signal, each of the plurality of second control signals is asserted at different timings, the first switch circuit outputs a delayed signal (PSW_ACK) of the first control signal after the plurality of first switch cells are sequentially turned on, each of the plurality of switch sections is set to an on state at different timings based on the plurality of second control signals, and a first switch section (291-1) of the plurality of switch sections is turned on based on the delayed signal and a first signal (PSW_ENb1) of the plurality of second control signals, characterized in that the delayed signal indicates that the connection between the first circuit and the voltage line via the first switch circuit is complete having completed turn-on of the switching elements in the first switch circuit. <EOS>