A display device, comprising: a first transistor (T1) including: a first active layer disposed over a substrate ; and a gate electrode disposed over the first active layer ; a second transistor (T3) including: a lower gate electrode disposed over the substrate ; a second active layer disposed over the lower gate electrode, a first end portion of the second active layer being electrically connected to an end portion of the first active layer ; and an upper gate electrode disposed over the second active layer ; a lower gate signal line extending in a first direction (DR1), a portion of the lower gate signal line forming the lower gate electrode; an upper gate signal line disposed over the lower gate signal line and extending in the first direction, a portion of the upper gate signal line forming the upper gate electrode; and a first connection pattern disposed over the upper gate signal line , electrically connecting the gate electrode and a second end portion of the second active layer , and intersecting the lower gate signal line and the upper gate signal line , characterized in that an entire part of the upper gate signal line overlaps a part of the lower gate signal line in an overlapping area (OA) in which the lower gate signal line or the upper gate signal line overlaps the first connection pattern , a channel of the second active layer is disposed in the first direction (DR1) from the overlapping area (OA) in a plan view, and the lower gate electrode and the upper gate electrode overlap the channel of the second active layer . a first transistor (T1) including: a first active layer disposed over a substrate ; and a gate electrode disposed over the first active layer ; a first active layer disposed over a substrate ; and a gate electrode disposed over the first active layer ; a second transistor (T3) including: a lower gate electrode disposed over the substrate ; a second active layer disposed over the lower gate electrode, a first end portion of the second active layer being electrically connected to an end portion of the first active layer ; and an upper gate electrode disposed over the second active layer ; a lower gate electrode disposed over the substrate ; a second active layer disposed over the lower gate electrode, a first end portion of the second active layer being electrically connected to an end portion of the first active layer ; and an upper gate electrode disposed over the second active layer ; a lower gate signal line extending in a first direction (DR1), a portion of the lower gate signal line forming the lower gate electrode; an upper gate signal line disposed over the lower gate signal line and extending in the first direction, a portion of the upper gate signal line forming the upper gate electrode; and a first connection pattern disposed over the upper gate signal line , electrically connecting the gate electrode and a second end portion of the second active layer , and intersecting the lower gate signal line and the upper gate signal line , characterized in that an entire part of the upper gate signal line overlaps a part of the lower gate signal line in an overlapping area (OA) in which the lower gate signal line or the upper gate signal line overlaps the first connection pattern , a channel of the second active layer is disposed in the first direction (DR1) from the overlapping area (OA) in a plan view, and the lower gate electrode and the upper gate electrode overlap the channel of the second active layer . <EOS>