A processor comprising: a plurality of cores to execute instructions; a shared circuitry region to be shared by the plurality of cores ; cache management circuitry associated with the shared circuitry region ; and a delayed prefetch manager comprising storage for a plurality of delayed prefetch entries, each delayed prefetch entry to be associated with a delayed prefetch message identifying a cache line to be prefetched by one of the plurality of cores , wherein the processor is configured as: upon receiving a write modify request from a first core of the plurality of cores , the write modify request indicating that a first cache line is being modified by the first core, the cache management circuitry is to check the storage of the delay prefetch manager to determine whether there is a first delayed prefetch entry for the first cache line, the first delayed prefetch entry associated with a first delayed prefetch message from a second core of the plurality of cores , wherein the cache management circuitry is to transmit the first cache line to the second core as a response to the first delayed prefetch message, wherein the delayed prefetch manager comprises a table or buffer to store the delayed prefetch entries, and wherein each delayed prefetch entry includes a first field to identify a cache line and a second field to identify one or more of the plurality of cores , and wherein the second field comprises a bit vector with a bit associated with each core, wherein upon receipt of a delayed prefetch request message identifying the cache line from a core of the plurality of cores , the bit associated with the core is to be set to a first value. a plurality of cores to execute instructions; a shared circuitry region to be shared by the plurality of cores ; cache management circuitry associated with the shared circuitry region ; and a delayed prefetch manager comprising storage for a plurality of delayed prefetch entries, each delayed prefetch entry to be associated with a delayed prefetch message identifying a cache line to be prefetched by one of the plurality of cores , wherein the processor is configured as: upon receiving a write modify request from a first core of the plurality of cores , the write modify request indicating that a first cache line is being modified by the first core, the cache management circuitry is to check the storage of the delay prefetch manager to determine whether there is a first delayed prefetch entry for the first cache line, the first delayed prefetch entry associated with a first delayed prefetch message from a second core of the plurality of cores , wherein the cache management circuitry is to transmit the first cache line to the second core as a response to the first delayed prefetch message, wherein the delayed prefetch manager comprises a table or buffer to store the delayed prefetch entries, and wherein each delayed prefetch entry includes a first field to identify a cache line and a second field to identify one or more of the plurality of cores , and wherein the second field comprises a bit vector with a bit associated with each core, wherein upon receipt of a delayed prefetch request message identifying the cache line from a core of the plurality of cores , the bit associated with the core is to be set to a first value. <EOS>