A method for fabricating a semiconductor device including a logic device and an SRAM device, the method comprising: providing a base substrate including an N-type logic region, a P-type logic region, a first pull down, PD, transistor region, a second PD transistor region, and a pass gate, PG, transistor region, wherein the N-type logic region includes a first N-type threshold-voltage, TV, region used to form a first N-type device and a second N-type TV region used to form a second N-type device, the P-type logic region includes a first P-type TV region used to form a first P-type device and a second P-type TV region used to form a second P-type device; forming a gate dielectric layer on a portion of the base substrate in the N-type logic region, the P-type logic region, the first PD transistor region, the second PD transistor region, and the PG transistor region ; forming a first work function, WF, layer on the gate dielectric layer in the first N-type TV region , the P-type logic region, the second PD transistor region, and the PG transistor region; forming a second WF layer on the first WF layer in the first P-type TV region ; forming a third WF layer on the second WF layer in the first P-type TV region , the first WF layer in the second P-type TV region , and the gate dielectric layer in the second N-type TV region and the first PD transistor region, wherein a thickness of the third WF layer is smaller than a thickness of the first WF layer; and forming a fourth WF layer on the third WF layer in the P-type logic region, the second N-type TV region , and the first PD transistor region, and on the first WF layer in the first N-type TV region , the second PD transistor region, and the PG transistor region. providing a base substrate including an N-type logic region, a P-type logic region, a first pull down, PD, transistor region, a second PD transistor region, and a pass gate, PG, transistor region, wherein the N-type logic region includes a first N-type threshold-voltage, TV, region used to form a first N-type device and a second N-type TV region used to form a second N-type device, the P-type logic region includes a first P-type TV region used to form a first P-type device and a second P-type TV region used to form a second P-type device; forming a gate dielectric layer on a portion of the base substrate in the N-type logic region, the P-type logic region, the first PD transistor region, the second PD transistor region, and the PG transistor region ; forming a first work function, WF, layer on the gate dielectric layer in the first N-type TV region , the P-type logic region, the second PD transistor region, and the PG transistor region; forming a second WF layer on the first WF layer in the first P-type TV region ; forming a third WF layer on the second WF layer in the first P-type TV region , the first WF layer in the second P-type TV region , and the gate dielectric layer in the second N-type TV region and the first PD transistor region, wherein a thickness of the third WF layer is smaller than a thickness of the first WF layer; and forming a fourth WF layer on the third WF layer in the P-type logic region, the second N-type TV region , and the first PD transistor region, and on the first WF layer in the first N-type TV region , the second PD transistor region, and the PG transistor region. <EOS>