A microcontroller, in particular a battery operated microcontroller , comprising: - a central processing unit (CPU) ; - a plurality of peripherals ; and - a programmable scheduler unit comprising: - a timer being clocked by an independent clock signal (170; 210, 220); - a comparator coupled with a timer register of said timer and having an output generating an output signal; - an event register coupled with said comparator , wherein preferably the timer register and the event register are configured to store a UNIX time format; - a plurality of delta time register arranged as a sequence buffer ; and - an arithmetic logic unit controlled by the output signal of the comparator and comprising first and second inputs and an output, wherein the first input is coupled with the timer register or the event register and the second input is coupled with the sequence buffer and the output is coupled with the event register , and an event logic unit (154; 380) receiving the output signal of the comparator and an output signal of said sequence buffer and controlling said arithmetic logic unit and said event register and information form the sequence buffer is taken into consideration to process an event wherein said event logic unit is configured to generate a plurality of output signals depending on the output signal of the comparator and the output signal of said sequence buffer . - a central processing unit (CPU) ; - a plurality of peripherals ; and - a programmable scheduler unit comprising: - a timer being clocked by an independent clock signal (170; 210, 220); - a comparator coupled with a timer register of said timer and having an output generating an output signal; - an event register coupled with said comparator , wherein preferably the timer register and the event register are configured to store a UNIX time format; - a plurality of delta time register arranged as a sequence buffer ; and - an arithmetic logic unit controlled by the output signal of the comparator and comprising first and second inputs and an output, wherein the first input is coupled with the timer register or the event register and the second input is coupled with the sequence buffer and the output is coupled with the event register , and an event logic unit (154; 380) receiving the output signal of the comparator and an output signal of said sequence buffer and controlling said arithmetic logic unit and said event register and information form the sequence buffer is taken into consideration to process an event wherein said event logic unit is configured to generate a plurality of output signals depending on the output signal of the comparator and the output signal of said sequence buffer . - a timer being clocked by an independent clock signal (170; 210, 220); - a comparator coupled with a timer register of said timer and having an output generating an output signal; - an event register coupled with said comparator , wherein preferably the timer register and the event register are configured to store a UNIX time format; - a plurality of delta time register arranged as a sequence buffer ; and - an arithmetic logic unit controlled by the output signal of the comparator and comprising first and second inputs and an output, wherein the first input is coupled with the timer register or the event register and the second input is coupled with the sequence buffer and the output is coupled with the event register , and an event logic unit (154; 380) receiving the output signal of the comparator and an output signal of said sequence buffer and controlling said arithmetic logic unit and said event register and information form the sequence buffer is taken into consideration to process an event wherein said event logic unit is configured to generate a plurality of output signals depending on the output signal of the comparator and the output signal of said sequence buffer . <EOS>