A system for phase alignment of multiple phase adjustable Phase Locked Loops, PLLs, comprising: a plurality N of PLLs (PLL_1...PLL_N) wherein each PLL comprises: an oscillator (VCO; DCO) configured to generate a respective output signal (OUT_1,...OUT_N); a frequency divider (DIV) configured to generate a respective feedback signal (FB_1,...FB_N) by dividing the respective output signal; a phase comparator arrangement configured to output a respective control signal to control the oscillator in response to a detection of a phase deviation between a reference signal (REF) and the feedback signal (FB); the system further comprising: a plurality N of phase detectors (DET_1...DET_N), wherein the plurality N of phase detectors and the plurality N of PLLs are connected in a loop such that: an i-th phase detector (DET_i) is configured to receive the i-th feedback signal (FB_i) generated from the i-th PLL and the (i+1)-th feedback signal (FB_i+1) generated from the (i+1)-th PLL, wherein i=1, 2, 3,...N-1; and the N-th phase detector (DET_N) is configured to receive the first feedback signal (FB_1) generated from the first PLL and the N-th feedback signal (FB_N) generated from the N-th PLL; wherein the i-th phase detector (DET_i) is configured to generate an i-th adjustment signal indicating an i-th phase difference between the i-th and (i+1)-th feedback signals for adjusting a phase of the i-th or (i+1)-th PLL; and the N-th phase detector (DET_N) is configured to generate a N-th adjustment signal indicating a N-th phase difference between the first and N-th feedback signals. a plurality N of PLLs (PLL_1...PLL_N) wherein each PLL comprises: an oscillator (VCO; DCO) configured to generate a respective output signal (OUT_1,...OUT_N); a frequency divider (DIV) configured to generate a respective feedback signal (FB_1,...FB_N) by dividing the respective output signal; a phase comparator arrangement configured to output a respective control signal to control the oscillator in response to a detection of a phase an oscillator (VCO; DCO) configured to generate a respective output signal (OUT_1,...OUT_N); a frequency divider (DIV) configured to generate a respective feedback signal (FB_1,...FB_N) by dividing the respective output signal; a phase comparator arrangement configured to output a respective control signal to control the oscillator in response to a detection of a phase deviation between a reference signal (REF) and the feedback signal (FB); the system further comprising: a plurality N of phase detectors (DET_1...DET_N), wherein the plurality N of phase detectors and the plurality N of PLLs are connected in a loop such that: an i-th phase detector (DET_i) is configured to receive the i-th feedback signal (FB_i) generated from the i-th PLL and the (i+1)-th feedback signal (FB_i+1) generated from the (i+1)-th PLL, wherein i=1, 2, 3,...N-1; and the N-th phase detector (DET_N) is configured to receive the first feedback signal (FB_1) generated from the first PLL and the N-th feedback signal (FB_N) generated from the N-th PLL; wherein an i-th phase detector (DET_i) is configured to receive the i-th feedback signal (FB_i) generated from the i-th PLL and the (i+1)-th feedback signal (FB_i+1) generated from the (i+1)-th PLL, wherein i=1, 2, 3,...N-1; and the N-th phase detector (DET_N) is configured to receive the first feedback signal (FB_1) generated from the first PLL and the N-th feedback signal (FB_N) generated from the N-th PLL; wherein the i-th phase detector (DET_i) is configured to generate an i-th adjustment signal indicating an i-th phase difference between the i-th and (i+1)-th feedback signals for adjusting a phase of the i-th or (i+1)-th PLL; and the N-th phase detector (DET_N) is configured to generate a N-th adjustment signal indicating a N-th phase difference between the first and N-th feedback signals. <EOS>