A heterogeneous computer system comprising: a first processor (101-1) comprising a first work scheduler (103-1) and a first work stealer logic (105-1); a second processor (101-2) being a different type than the first processor (101-1), wherein the second processor (101-2) is a digital signal processor, DSP, comprising a second work scheduler (103-1) and a second work stealer logic (105-2); a plurality of work queues (104-1, 104-2) to store tasks to be processed at the first and second processors (101-1, 101-2), wherein the plurality of queues (104-1, 104-2) comprises a first work queue (104-1) to queue tasks for the first processor (101-1) and a second work queue (104-2) to queue tasks for the second processor (101-2), wherein the first work stealer logic (105-1) and the second work stealer logic (105-2) have access to both the first work queue (104-1) and the second work queue (104-2), wherein the first work stealer logic (105-1) is configured to steal a first task from the second work queue (104-2) designated to be processed at the second processor (101-2) and add the stolen first task to the first work queue (104-1) for processing at the first processor (101-1) in response to determining that the first work queue (104-1) is filled below a first threshold level and the second work queue (104-2) is filled above a second threshold level, and wherein the second work stealer logic (105-2) is configured to steal a second task from the first work queue (104-1) designated to be processed at the first processor (101-2) and add the stolen second task to the second work queue (104-2) for processing at the second processor (101-2) in response to determining that the second work queue (104-2) is filled below the second threshold level and the first work queue (104-1) is filled above the first threshold level. a first processor (101-1) comprising a first work scheduler (103-1) and a first work stealer logic (105-1); a second processor (101-2) being a different type than the first processor (101-1), wherein the second processor (101-2) is a digital signal processor, DSP, comprising a second work scheduler (103-1) and a second work stealer logic (105-2); a plurality of work queues (104-1, 104-2) to store tasks to be processed at the first and second processors (101-1, 101-2), wherein the plurality of queues (104-1, 104-2) comprises a first work queue (104-1) to queue tasks for the first processor (101-1) and a second work queue (104-2) to queue tasks for the second processor (101-2), wherein the first work stealer logic (105-1) and the second work stealer logic (105-2) have access to both the first work queue (104-1) and the second work queue (104-2), wherein the first work stealer logic (105-1) is configured to steal a first task from the second work queue (104-2) designated to be processed at the second processor (101-2) and add the stolen first task to the first work queue (104-1) for processing at the first processor (101-1) in response to determining that the first work queue (104-1) is filled below a first threshold level and the second work queue (104-2) is filled above a second threshold level, and wherein the second work stealer logic (105-2) is configured to steal a second task from the first work queue (104-1) designated to be processed at the first processor (101-2) and add the stolen second task to the second work queue (104-2) for processing at the second processor (101-2) in response to determining that the second work queue (104-2) is filled below the second threshold level and the first work queue (104-1) is filled above the first threshold level. <EOS>