A semiconductor device, comprising: a first semiconductor structure comprising a programmable logic device , wherein the programmable logic device includes one or more PLAs, PALs, GALs, CPLDs, FPGAs, an array of static random-access memory, SRAM, cells to function as the internal instruction memory and/or data memory of programmable logic device , a first bonding layer comprising a plurality of first bonding contacts , a first interconnect layer vertically between the first bonding layer and the programmable logic device and a device layer above a substrate ; a second semiconductor structure comprising the substrate , an array of 2D NAND memory cells , a second bonding layer comprising a plurality of second bonding contacts and a second interconnect layer vertically between the second bonding layer and the array of 2D NAND memory cells ; and a bonding interface between the first bonding layer and the second bonding layer , wherein the first bonding contacts are aligned and in contact with the second bonding contacts at the bonding interface , wherein the first semiconductor structure includes a peripheral circuit of the 2D NAND memory for controlling and sensing the 2D NAND memory cells , wherein the peripheral circuit includes one or more of word line drivers and page buffers , wherein the first interconnect layer includes a plurality of interconnects, including interconnect lines and via contacts, wherein the programmable logic device , the array of static random-access memory, SRAM, cells and the peripheral circuit of the 2D NAND memory in device layer are electrically connected to one another through the interconnects in the first interconnect layer , wherein the device layer includes the peripheral circuit above the first interconnect layer and the first bonding layer and outside of the programmable logic device , wherein the peripheral circuits and SRAM are formed in different regions on the same plane outside of the programmable logic device . a first semiconductor structure comprising a programmable logic device , wherein the programmable logic device includes one or more PLAs, PALs, GALs, CPLDs, FPGAs, an array of static random-access memory, SRAM, cells to function as the internal instruction memory and/or data memory of programmable logic device , a first bonding layer comprising a plurality of first bonding contacts , a first interconnect layer vertically between the first bonding layer and the programmable logic device and a device layer above a substrate ; a second semiconductor structure comprising the substrate , an array of 2D NAND memory cells , a second bonding layer comprising a plurality of second bonding contacts and a second interconnect layer vertically between the second bonding layer and the array of 2D NAND memory cells ; and a bonding interface between the first bonding layer and the second bonding layer , wherein the first bonding contacts are aligned and in contact with the second bonding contacts at the bonding interface , wherein the first semiconductor structure includes a peripheral circuit of the 2D NAND memory for controlling and sensing the 2D NAND memory cells , wherein the peripheral circuit includes one or more of word line drivers and page buffers , wherein the first interconnect layer includes a plurality of interconnects, including interconnect lines and via contacts, wherein the programmable logic device , the array of static random-access memory, SRAM, cells and the peripheral circuit of the 2D NAND memory in device layer are electrically connected to one another through the interconnects in the first interconnect layer , wherein the device layer includes the peripheral circuit above the first interconnect layer and the first bonding layer and outside of the programmable logic device , wherein the peripheral circuits and SRAM are formed in different regions on the same plane outside of the programmable logic device . <EOS>