A fully balanced differential difference amplifier, FBDDA, comprising: - a first differential input stage , configured to receive an input voltage signal (Vin), including an AC component and a DC component; and - a second differential input stage , configured to receive a DC common-mode voltage signal (V CM ), said DC component of the input signal being said common-mode voltage signal, - a first resistive-degeneration group , including a first degeneration resistor in series to a second degeneration resistor , coupled between a first input terminal and a second input terminal of the first differential input stage ; and - a second resistive-degeneration group , including a third degeneration resistor in series to a fourth degeneration resistor , coupled between a third input terminal and a fourth input terminal of the second differential input stage ; - a differential output stage, configured to supply an output voltage signal (Vout_n, Vout_p); - a first switch coupled in parallel to the first resistive-degeneration group between the first and second input terminals ; - a second switch coupled in parallel to the second resistive-degeneration group between the third and fourth input terminals , said first and second switches being configured in a closed state for bypassing the first and second resistive-degeneration groups , during a first operating condition where said input voltage signal (Vin) has a first value, and being further configured in an open state during a second operating condition where said input voltage signal (Vin) has a second value, higher than the first value, thus reducing a harmonic distortion of the output voltage signal. - a first differential input stage , configured to receive an input voltage signal (Vin), including an AC component and a DC component; and - a second differential input stage , configured to receive a DC common-mode voltage signal (V CM ), said DC component of the input signal being said common-mode voltage signal, - a first resistive-degeneration group , including a first degeneration resistor in series to a second degeneration resistor , coupled between a first input terminal and a second input terminal of the first differential input stage ; and - a second resistive-degeneration group , including a third degeneration resistor in series to a fourth degeneration resistor , coupled between a third input terminal and a fourth input terminal of the second differential input stage ; - a differential output stage, configured to supply an output voltage signal (Vout_n, Vout_p); - a first switch coupled in parallel to the first resistive-degeneration group between the first and second input terminals ; - a second switch coupled in parallel to the second resistive-degeneration group between the third and fourth input terminals , said first and second switches being configured in a closed state for bypassing the first and second resistive-degeneration groups , during a first operating condition where said input voltage signal (Vin) has a first value, and being further configured in an open state during a second operating condition where said input voltage signal (Vin) has a second value, higher than the first value, thus reducing a harmonic distortion of the output voltage signal. <EOS>