Circuit arrangement for monitoring alternating voltage signals (I_k), comprising: - one or more comparators , which can each be supplied at a first comparison input with an alternating voltage signal (I_k) to be monitored or a signal obtained therefrom for comparison with a defined amplitude threshold value (A) applied to a second comparison input, such that a first output signal (S1) can be generated at an output, - a zero crossing detector which can be supplied at a monitoring input with a reference signal or a signal obtained therefrom such that a second output signal (S2) can be generated at an output of the zero crossing detector , - a first timer connected downstream of the zero crossing detector for generating a first clock signal (S3a) on the basis of the second output signal (S2), - a second timer connected downstream of the zero crossing detector for generating a second clock signal (S3b) on the basis of the second output signal (S2) or on the basis of the first clock signal (S3a), wherein the second clock signal (S3b) is different from the first clock signal (S3a), - a first edge-triggered flip-flop , and - a second edge-triggered flip-flop , wherein the output of the comparator or the outputs of the comparators are each connected to a state-controlled input (D) of the first flip-flop or the second flip-flop , and wherein an output of the first timer is connected to an edge-triggered input of the first flip-flop and an output of the second timer is connected to an edge-triggered input of the second flip-flop such that a first state signal (S4a) can be generated at an output of the first flip-flop and a second state signal (S4b) can be generated at an output of the second flip-flop . - one or more comparators , which can each be supplied at a first comparison input with an alternating voltage signal (I_k) to be monitored or a signal obtained therefrom for comparison with a defined amplitude threshold value (A) applied to a second comparison input, such that a first output signal (S1) can be generated at an output, - a zero crossing detector which can be supplied at a monitoring input with a reference signal or a signal obtained therefrom such that a second output signal (S2) can be generated at an output of the zero crossing detector , - a first timer connected downstream of the zero crossing detector for generating a first clock signal (S3a) on the basis of the second output signal (S2), - a second timer connected downstream of the zero crossing detector for generating a second clock signal (S3b) on the basis of the second output signal (S2) or on the basis of the first clock signal (S3a), wherein the second clock signal (S3b) is different from the first clock signal (S3a), - a first edge-triggered flip-flop , and - a second edge-triggered flip-flop , wherein the output of the comparator or the outputs of the comparators are each connected to a state-controlled input (D) of the first flip-flop or the second flip-flop , and wherein an output of the first timer is connected to an edge-triggered input of the first flip-flop and an output of the second timer is connected to an edge-triggered input of the second flip-flop such that a first state signal (S4a) can be generated at an output of the first flip-flop and a second state signal (S4b) can be generated at an output of the second flip-flop . wherein the output of the comparator or the outputs of the comparators are each connected to a state-controlled input (D) of the first flip-flop or the second flip-flop , and wherein an output of the first timer is connected to an edge-triggered input of the first flip-flop and an output of the second timer is connected to an edge-triggered input of the second flip-flop such that a first state signal (S4a) can be generated at an output of the first flip-flop and a second state signal (S4b) can be generated at an output of the second flip-flop . <EOS>