A memory, comprising: a plurality of bitcells, each bitcell configured to store a stored bit, having a pair of switches (L, R) connected to an output node , and having a capacitor (C) coupled to the output node ; a first storage element configured to store a sign bit (S) for a signed input word and a plurality of additional storage elements (M6, M5, M4, M3, M2, M1, M0) configured to store a plurality of magnitude bits for the signed input word; and a controller configured to select a first bit from the first storage element to control the pair of switches (L, R) responsive to the first bit during a first phase of operation for the memory and configured to select a second bit from the plurality of additional storage elements (M6, M5, M4, M3, M2, M1, M0) to control the pair of switches (L, R) responsive to the second bit during a second phase of operation for the memory; wherein the controller is further configured during the first phase of operation to close a first switch (L) of the pair of switches (L, R) that is coupled between a first node for the stored bit and the output node and to open a second switch (R) of the pair of switches (L, R) that is coupled between a second node for a complement of the stored bit and the output node responsive to the first bit having a first binary value and to open the first switch (L) and to close the second switch (R) responsive to the first bit having a second binary value that is a complement of the first binary value; and wherein the controller is further configured during the second phase of operation to reverse a switching state of the first switch (L) and the second switch (R) responsive to the second bit having the first binary value and to maintain the switching state of the first switch (L) and the second switch (R) responsive to the second bit having the second binary value. a plurality of bitcells, each bitcell configured to store a stored bit, having a pair of switches (L, R) connected to an output node , and having a capacitor (C) coupled to the output node ; a first storage element configured to store a sign bit (S) for a signed input word and a plurality of additional storage elements (M6, M5, M4, M3, M2, M1, M0) configured to store a plurality of magnitude bits for the signed input word; and a controller configured to select a first bit from the first storage element to control the pair of switches (L, R) responsive to the first bit during a first phase of operation for the memory and configured to select a second bit from the plurality of additional storage elements (M6, M5, M4, M3, M2, M1, M0) to control the pair of switches (L, R) responsive to the second bit during a second phase of operation for the memory; wherein the controller is further configured during the first phase of operation to close a first switch (L) of the pair of switches (L, R) that is coupled between a first node for the stored bit and the output node and to open a second switch (R) of the pair of switches (L, R) that is coupled between a second node for a complement of the stored bit and the output node responsive to the first bit having a first binary value and to open the first switch (L) and to close the second switch (R) responsive to the first bit having a second binary value that is a complement of the first binary value; and wherein the controller is further configured during the second phase of operation to reverse a switching state of the first switch (L) and the second switch (R) responsive to the second bit having the first binary value and to maintain the switching state of the first switch (L) and the second switch (R) responsive to the second bit having the second binary value. <EOS>