A method for calibrating timing relationships between signals involved in performing write operations, wherein the signals are communicated between a memory controller and a memory chip in a set of memory chips (D110,...,D117), wherein the set of memory chips (D110,...,D117) is coupled to the memory controller such that the clock signal is routed from the memory controller to the set of memory chips (D110,...,D117) in a multi-drop fashion, and wherein the data-strobe signal is routed from the memory controller to the set of memory chips (D110,...,D117) through direct connections, and wherein a difference in delay between the clock signal and the data-strobe signal can exceed one clock period, the method comprising: calibrating a phase relationship of a data strobe signal sent by the memory controller to the memory chip , wherein the phase relationship is between the data-strobe signal and a clock signal received at the memory chip from the memory controller , wherein calibrating the phase relationship between the data-strobe signal and the clock signal includes: the memory controller asserting a pulse on the data-strobe signal at varying delays relative to the clock signal ; and receiving from the memory chip a transition that indicates a pulse of the strobe signal that is aligned with the clock signal at the memory chip ; and after receiving the transition, the memory controller calibrating a clock-cycle relationship between the data-strobe signal and the clock signal , wherein calibrating the clock-cycle relationship involves iteratively: varying a delay on the data-strobe signal relative to the clock signal by a multiple of a clock period; writing a first value to a specific location in the memory chip using the data-strobe signal; reading a second value from the specific location in the memory chip ; and determining whether the data-strobe signal and the clock signal are calibrated by validating that the second value read from the specific location matches the first value written to the specific location. the memory controller asserting a pulse on the data-strobe signal at varying delays relative to the clock signal ; and receiving from the memory chip a transition that indicates a pulse of the strobe signal that is aligned with the clock signal at the memory chip ; and after receiving the transition, the memory controller calibrating a clock-cycle relationship between the data-strobe signal and the clock signal , wherein calibrating the clock-cycle relationship involves iteratively: varying a delay on the data-strobe signal relative to the clock signal by a multiple of a clock period; writing a first value to a specific location in the memory chip using the data-strobe signal; reading a second value from the specific location in the memory chip ; and determining whether the data-strobe signal and the clock signal are calibrated by validating that the second value read from the specific location matches the first value written to the specific location. varying a delay on the data-strobe signal relative to the clock signal by a multiple of a clock period; writing a first value to a specific location in the memory chip using the data-strobe signal; reading a second value from the specific location in the memory chip ; and determining whether the data-strobe signal and the clock signal are calibrated by validating that the second value read from the specific location matches the first value written to the specific location. <EOS>