An artificial intelligence chip (100_1, 100_2, 100_3, 200), suitable for receiving a command carrying first data and address information, wherein the artificial intelligence chip (100_1, 100_2, 100_3, 200) is part of a node of a collective communication system, said node comprising also a network interface controller , and the artificial intelligence chip (100_1, 100_2, 100_3, 200) comprises: a chip memory ; a computing processor , coupled to the chip memory ; a base address register , configured to access an extended address space of the chip memory , wherein the extended address space is greater than a physical memory address space of the chip memory ; and an extended address processor , coupled between the computing processor and the base address register , configured to receive the command, wherein the base address register is coupled between the extended address processor and a bus connected to the network interface controller , the network interface controller being external to the artificial intelligence chip, the computing processor is coupled between the extended address processor and the chip memory , the address information points to a section among a plurality of sections comprised in the extended address space, and upon receiving the command via the network interface controller, the extended address processor determines an operation mode of the first data according to the section pointed to by the address information, wherein the extended address processor performs a first operation on the first data when the address information points to a first section of the extended address space, wherein the extended address processor notifies the computing processor of the operation mode and the computing processor performs a second operation on the first data when the address information points to a section other than the first section of the extended address space, wherein the first section corresponds to the physical memory address space. a chip memory ; a computing processor , coupled to the chip memory ; a base address register , configured to access an extended address space of the chip memory , wherein the extended address space is greater than a physical memory address space of the chip memory ; and an extended address processor , coupled between the computing processor and the base address register , configured to receive the command, wherein the base address register is coupled between the extended address processor and a bus connected to the network interface controller , the network interface controller being external to the artificial intelligence chip, the computing processor is coupled between the extended address processor and the chip memory , the address information points to a section among a plurality of sections comprised in the extended address space, and upon receiving the command via the network interface controller, the extended address processor determines an operation mode of the first data according to the section pointed to by the address information, wherein the extended address processor performs a first operation on the first data when the address information points to a first section of the extended address space, wherein the extended address processor notifies the computing processor of the operation mode and the computing processor performs a second operation on the first data when the address information points to a section other than the first section of the extended address space, wherein the first section corresponds to the physical memory address space. <EOS>