A semiconductor structure, comprising: a substrate, the substrate comprising a peripheral region and a chip region; a first dielectric layer positioned on the peripheral region and the chip region of the substrate; and a sealing ring structure and a functional structure respectively positioned in the first dielectric layer on the peripheral region and in the first dielectric layer on the chip region; wherein the sealing ring structure and the functional structure are formed by electrically conductive material; wherein the sealing ring structure comprises a first subportion , a second subportion and a third subportion stacked in sequence, the functional structure comprising a fourth subportion and a fifth subportion stacked in sequence, a total height of the first subportion , the second subportion and the third subportion being equal to a total height of the fourth subportion and the fifth subportion ; characterized in that , in a direction parallel to a surface of the substrate, a width of the second subportion is greater than a width of the first subportion ; and in a direction parallel to a surface of the substrate, a width of the third subportion is greater than the width of the second subportion ; in a direction parallel to a surface of the substrate, the width of the first subportion is equal to a width of the fourth subportion ; and in a direction parallel to a surface of the substrate, the width of the second subportion is equal to a width of the fifth subportion ; the first subportion , the second subportion and the third subportion are integrally formed; and the fourth subportion and the fifth subportion are integrally formed and the first dielectric layer is a single-layer structure. a substrate, the substrate comprising a peripheral region and a chip region; a first dielectric layer positioned on the peripheral region and the chip region of the substrate; and a sealing ring structure and a functional structure respectively positioned in the first dielectric layer on the peripheral region and in the first dielectric layer on the chip region; wherein the sealing ring structure and the functional structure are formed by electrically conductive material; wherein the sealing ring structure comprises a first subportion , a second subportion and a third subportion stacked in sequence, the functional structure comprising a fourth subportion and a fifth subportion stacked in sequence, a total height of the first subportion , the second subportion and the third subportion being equal to a total height of the fourth subportion and the fifth subportion ; characterized in that , in a direction parallel to a surface of the substrate, a width of the second subportion is greater than a width of the first subportion ; and in a direction parallel to a surface of the substrate, a width of the third subportion is greater than the width of the second subportion ; in a direction parallel to a surface of the substrate, the width of the first subportion is equal to a width of the fourth subportion ; and in a direction parallel to a surface of the substrate, the width of the second subportion is equal to a width of the fifth subportion ; the first subportion , the second subportion and the third subportion are integrally formed; and the fourth subportion and the fifth subportion are integrally formed and the first dielectric layer is a single-layer structure. <EOS>