A circuit for transferring a signal from a fast clock domain to a slow clock domain comprising: a fast clock domain configured to receive an input signal (F_IN; 604) from a data storage and enable circuit having received input data , and, to responsively, set a capture time period and transfer an intermediate signal (f_1) to the slow clock domain to notify the set capture time period, a slow clock domain configured to receive the transferred intermediate signal (f_1) from the fast clock domain and, responsively, generate an output signal (S_OUT), a first synchronizer disposed in the slow clock domain, and a second synchronizer disposed in the fast clock domain, wherein the first synchronizer , operating with a slow clock(CLKS), is configured to receive the intermediate signal and, responsively, provide the output signal as a transferred signal which is synchronized to the input signal, and the second synchronizer , operating with a fast clock(CLKF), is configured to receive a feedback signal (s_2) from the first synchronizer for acknowledging synchronization of the output signal to the input signal, the fast clock domain configured to reset the capture time period upon receipt of the feedback signal (s_2), in response to receiving the feedback signal (s_2) from the first synchronizer, the second synchronizer being configured to cause an acknowledge out signal (F_ACK_OUT; 606) to be sent to the data storage and enable circuit , the data storage and enable circuit being configured to disable the input signal (F_IN; 604) until the acknowledge out signal (F_ACK_OUT; 606) is received by the data storage and enable circuit , the data storage and enable circuit being configured to in response to receiving the acknowledge out signal (F_ACK_OUT; 606) generate a next input signal (F_IN; 604) to be sent to the fast clock domain . a fast clock domain configured to receive an input signal (F_IN; 604) from a data storage and enable circuit having received input data , and, to responsively, set a capture time period and transfer an intermediate signal (f_1) to the slow clock domain to notify the set capture time period, a slow clock domain configured to receive the transferred intermediate signal (f_1) from the fast clock domain and, responsively, generate an output signal (S_OUT), a first synchronizer disposed in the slow clock domain, and a second synchronizer disposed in the fast clock domain, wherein the first synchronizer , operating with a slow clock(CLKS), is configured to receive the intermediate signal and, responsively, provide the output signal as a transferred signal which is synchronized to the input signal, and the second synchronizer , operating with a fast clock(CLKF), is configured to receive a feedback signal (s_2) from the first synchronizer for acknowledging synchronization of the output signal to the input signal, the fast clock domain configured to reset the capture time period upon receipt of the feedback signal (s_2), in response to receiving the feedback signal (s_2) from the first synchronizer, the second synchronizer being configured to cause an acknowledge out signal (F_ACK_OUT; 606) to be sent to the data storage and enable circuit , the data storage and enable circuit being configured to disable the input signal (F_IN; 604) until the acknowledge out signal (F_ACK_OUT; 606) is received by the data storage and enable circuit , the data storage and enable circuit being configured to in response to receiving the acknowledge out signal (F_ACK_OUT; 606) generate a next input signal (F_IN; 604) to be sent to the fast clock domain . <EOS>