A transmission circuit, applicable to a Dynamic Random Access Memory, DRAM, and comprising: an upper-layer clock bonding pad , configured to transmit a clock signal; M upper-layer data bonding pads , configured to transmit data signals; a lower-layer clock bonding pad , electrically connected with the upper-layer clock bonding pad , wherein an area of the lower-layer clock bonding pad is smaller than that of the upper-layer clock bonding pad ; and M lower-layer data bonding pads , electrically connected with the M upper-layer data bonding pads in a one-to-one correspondence, wherein an area of each lower-layer data bonding pad is smaller than that of each upper-layer data bonding pad , and a distance between each lower-layer data bonding pad and the lower-layer clock bonding pad is less than a distance between an upper-layer data bonding pad corresponding to the lower-layer data bonding pad and the upper-layer clock bonding pad ; wherein the upper-layer clock bonding pad and the upper-layer data bonding pads are located on a first layer, the lower-layer clock bonding pad and the lower-layer data bonding pads are located on a second layer, a dielectric layer is arranged between the first layer and the second layer, and the first layer, the dielectric layer and the second layer are all located on a same substrate , M being an integer greater than or equal to 2; characterized in that the lower-layer data bonding pads are arranged in two parallel rows, and the lower-layer clock bonding pad is located in one of the two parallel rows, and has a same number of lower-layer data bonding pads on two sides thereof; and part of the upper-layer data bonding pads and the upper-layer clock bonding pad are arranged in a same row, and remaining upper-layer data bonding pads are arranged in a same column around two or more sides of the two parallel rows of the lower-layer data bonding pads and the lower-layer clock bonding pad. an upper-layer clock bonding pad , configured to transmit a clock signal; M upper-layer data bonding pads , configured to transmit data signals; a lower-layer clock bonding pad , electrically connected with the upper-layer clock bonding pad , wherein an area of the lower-layer clock bonding pad is smaller than that of the upper-layer clock bonding pad ; and M lower-layer data bonding pads , electrically connected with the M upper-layer data bonding pads in a one-to-one correspondence, wherein an area of each lower-layer data bonding pad is smaller than that of each upper-layer data bonding pad , and a distance between each lower-layer data bonding pad and the lower-layer clock bonding pad is less than a distance between an upper-layer data bonding pad corresponding to the lower-layer data bonding pad and the upper-layer clock bonding pad ; wherein the upper-layer clock bonding pad and the upper-layer data bonding pads are located on a first layer, the lower-layer clock bonding pad and the lower-layer data bonding pads are located on a second layer, a dielectric layer is arranged between the first layer and the second layer, and the first layer, the dielectric layer and the second layer are all located on a same substrate , M being an integer greater than or equal to 2; characterized in that the lower-layer data bonding pads are arranged in two parallel rows, and the lower-layer clock bonding pad is located in one of the two parallel rows, and has a same number of lower-layer data bonding pads on two sides thereof; and part of the upper-layer data bonding pads and the upper-layer clock bonding pad are arranged in a same row, and remaining upper-layer data bonding pads are arranged in a same column around two or more sides of the two parallel rows of the lower-layer data bonding pads and the lower-layer clock bonding pad. <EOS>