A communication apparatus for a beamforming system comprising a plurality of communication circuits (10a-c), each communication circuit of the plurality of communication circuits (10a-c) comprising a fractional-N frequency synthesizer circuit (20, 20a-c) configured to generate a local oscillator signal (LOa-c) of said communication circuit (10-c); wherein each fractional-N frequency synthesizer circuit (20, 20a-c) being driven by a common reference oscillator and comprising: a frequency divider circuit configured to receive a first oscillation signal having a first frequency, to receive a control word indicating a divisor, and to frequency divide the first oscillation signal with the divisor to generate a second oscillation signal having a second frequency, lower than the first frequency; and a modulator circuit configured to generate a sequence of control words to the frequency divider circuit; wherein the modulator circuit comprises a set of memory elements (M, Ml-M/V), configured to store an internal state of the modulator circuit in response to a first control signal and to restore the internal state of the modulator circuit in response to a second control signal, the internal state of the modulator circuit being restored to a value that the internal state had when the first control signal was applied to the modulator circuit, wherein the communication apparatus is further configured to initially synchronize the modulator circuits of each fractional-N frequency synthesizer circuit (20a-c) such that each modulator circuit has a same initial internal state; wherein the sequence of control words generated by each modulator circuit is the same; and wherein the communication apparatus is further configured to supply the first control signal and the second control signal, with a time delay between them, to the modulator circuit of each fractional-N frequency synthesizer circuit (20a-c) in each communication circuit (10-c) with different time delays for different communication circuits (10a-c), thereby enabling a time shift of the sequence of control words generated by each modulator. a frequency divider circuit configured to receive a first oscillation signal having a first frequency, to receive a control word indicating a divisor, and to frequency divide the first oscillation signal with the divisor to generate a second oscillation signal having a second frequency, lower than the first frequency; and a modulator circuit configured to generate a sequence of control words to the frequency divider circuit; wherein the modulator circuit comprises a set of memory elements (M, Ml-M/V), configured to store an internal state of the modulator circuit in response to a first control signal and to restore the internal state of the modulator circuit in response to a second control signal, the internal state of the modulator circuit being restored to a value that the internal state had when the first control signal was applied to the modulator circuit, wherein the communication apparatus is further configured to initially synchronize the modulator circuits of each fractional-N frequency synthesizer circuit (20a-c) such that each modulator circuit has a same initial internal state; wherein the sequence of control words generated by each modulator circuit is the same; and wherein the communication apparatus is further configured to supply the first control signal and the second control signal, with a time delay between them, to the modulator circuit of each fractional-N frequency synthesizer circuit (20a-c) in each communication circuit (10-c) with different time delays for different communication circuits (10a-c), thereby enabling a time shift of the sequence of control words generated by each modulator. <EOS>