A semiconductor structure comprising: a compound semiconductor growth support layer (16, 16'b, 16"e) for a compound semiconductor device, wherein the compound semiconductor growth support layer is silicon, SiC or sapphire; a first buried oxide layer of silicon dioxide disposed directly on an upper surface of the compound semiconductor growth support layer (16, 16'b, 16"e); a selective etch layer disposed directly on the first buried oxide layer , wherein the selective etch layer is aluminum oxide, Al 2 O 3 , or aluminum nitride, AlN, or a composite layer of a lower layer of Al 2 O 3 or AlN and an upper layer of silicon nitride, SiN x ; a second buried oxide layer of silicon dioxide disposed directly on the selective etch layer , wherein the etch rate of the second buried oxide layer is higher than the etch rate of the underlying portions of the selective etch layer in fluorine containing plasmas; an elemental semiconductor layer disposed directly on the second buried oxide layer , wherein the elemental semiconductor layer is silicon; a pair of silicon devices formed in the elemental semiconductor layer , wherein the silicon devices are CMOS transistors; a top silicon dioxide layer disposed directly on the elemental semiconductor layer ; a compound semiconductor disposed directly on the compound semiconductor growth support layer (16, 16'b, 16"e) in a window formed through the top silicon dioxide layer , the elemental semiconductor layer , the second buried oxide layer , the selective etch layer and the first buried oxide layer ; a compound semiconductor device formed in the compound semiconductor , wherein the compound semiconductor device is a III-V device. a compound semiconductor growth support layer (16, 16'b, 16"e) for a compound semiconductor device, wherein the compound semiconductor growth support layer is silicon, SiC or sapphire; a first buried oxide layer of silicon dioxide disposed directly on an upper surface of the compound semiconductor growth support layer (16, 16'b, 16"e); a selective etch layer disposed directly on the first buried oxide layer , wherein the selective etch layer is aluminum oxide, Al 2 O 3 , or aluminum nitride, AlN, or a composite layer of a lower layer of Al 2 O 3 or AlN and an upper layer of silicon nitride, SiN x ; a second buried oxide layer of silicon dioxide disposed directly on the selective etch layer , wherein the etch rate of the second buried oxide layer is higher than the etch rate of the underlying portions of the selective etch layer in fluorine containing plasmas; an elemental semiconductor layer disposed directly on the second buried oxide layer , wherein the elemental semiconductor layer is silicon; a pair of silicon devices formed in the elemental semiconductor layer , wherein the silicon devices are CMOS transistors; a top silicon dioxide layer disposed directly on the elemental semiconductor layer ; a compound semiconductor disposed directly on the compound semiconductor growth support layer (16, 16'b, 16"e) in a window formed through the top silicon dioxide layer , the elemental semiconductor layer , the second buried oxide layer , the selective etch layer and the first buried oxide layer ; a compound semiconductor device formed in the compound semiconductor , wherein the compound semiconductor device is a III-V device. <EOS>