An RF amplifier circuit , comprising: an output transistor (Q2), the output transistor having a control electrode for controlling a flow of carriers between a first electrode and a second electrode, the second electrode is connected to ground potential and the first electrode connected to a first voltage supply (+VDD); and a bias circuit , comprising: a pair (SF1, SF2) of source follower transistors circuits; a first one (SF1) of the pair of two source follower transistor circuits being coupled between the first voltage supply (+VDD) having a first polarity relative to the ground potential and a second voltage supply (-VSS) having a second polarity relative to ground potential, the first polarity being opposite to the second polarity, the first one of the pair of the source follower transistor circuits supplying a control signal to a second one (SF2) of the pair of source follower transistor circuits; wherein the second one (SF2) of the pair of source follower transistors circuits is coupled between the second voltage supply (-VSS) and the ground potential and wherein the second one of the pair of source follower transistor circuits is arranged to produce a bias signal for the control electrode of the output transistor . an output transistor (Q2), the output transistor having a control electrode for controlling a flow of carriers between a first electrode and a second electrode, the second electrode is connected to ground potential and the first electrode connected to a first voltage supply (+VDD); and a bias circuit , comprising: a pair (SF1, SF2) of source follower transistors circuits; a first one (SF1) of the pair of two source follower transistor circuits being coupled between the first voltage supply (+VDD) having a first polarity relative to the ground potential and a second voltage supply (-VSS) having a second polarity relative to ground potential, the first polarity being opposite to the second polarity, the first one of the pair of the source follower transistor circuits supplying a control signal to a second one (SF2) of the pair of source follower transistor circuits; wherein the second one (SF2) of the pair of source follower transistors circuits is coupled between the second voltage supply (-VSS) and the ground potential and wherein the second one of the pair of source follower transistor circuits is arranged to produce a bias signal for the control electrode of the output transistor . a pair (SF1, SF2) of source follower transistors circuits; a first one (SF1) of the pair of two source follower transistor circuits being coupled between the first voltage supply (+VDD) having a first polarity relative to the ground potential and a second voltage supply (-VSS) having a second polarity relative to ground potential, the first polarity being opposite to the second polarity, the first one of the pair of the source follower transistor circuits supplying a control signal to a second one (SF2) of the pair of source follower transistor circuits; wherein the second one (SF2) of the pair of source follower transistors circuits is coupled between the second voltage supply (-VSS) and the ground potential and wherein the second one of the pair of source follower transistor circuits is arranged to produce a bias signal for the control electrode of the output transistor . <EOS>