An imaging sensor device , comprising: an array of pixel sensors arranged in rows and columns, the array comprising: a plurality of stitching blocks , each stitching block comprising a plurality of pixel sensors disposed in at least one row group; and first and second groups of addressing lines for addressing the pixel sensors, the arrangement of pixel sensors and addressing lines in each of the stitching blocks being the same; row addressing circuitry external to the array, disposed along an edge of the array parallel to the rows of pixel sensors, coupled to the pixel sensors using the first group of addressing lines and configured to perform a row addressing action in which a single corresponding row in each of the row groups of each stitching block is simultaneously addressed; and group addressing circuitry external to the array, disposed along the same edge of the array as the row addressing circuitry, coupled to the pixel sensors using at least some of the second group of addressing lines and configured to perform a group addressing action in which all of the rows in a single row group of a single stitching block are simultaneously addressed; wherein each stitching block further comprises a logic gate provided within a respective pixel sensor for each respective row of pixel sensors of the stitching block, said logic gate being coupled to a respective one of the first addressing lines and a respective one of the second addressing lines, so as to combine a row addressing action and a group addressing action, such that only one row of one row group of one stitching block is selected simultaneously; and wherein respective logic gates are distributed randomly or pseudo-randomly such that the positions of each logic gate in relation to their associated pixel sensors of the respective row of pixel sensors of the stitching block are not the same. an array of pixel sensors arranged in rows and columns, the array comprising: a plurality of stitching blocks , each stitching block comprising a plurality of pixel sensors disposed in at least one row group; and first and second groups of addressing lines for addressing the pixel sensors, the arrangement of pixel sensors and addressing lines in each of the stitching blocks being the same; row addressing circuitry external to the array, disposed along an edge of the array parallel to the rows of pixel sensors, coupled to the pixel sensors using the first group of addressing lines and configured to perform a row addressing action in which a single corresponding row in each of the row groups of each stitching block is simultaneously addressed; and group addressing circuitry external to the array, disposed along the same edge of the array as the row addressing circuitry, coupled to the pixel sensors using at least some of the second group of addressing lines and configured to perform a group addressing action in which all of the rows in a single row group of a single stitching block are simultaneously addressed; wherein each stitching block further comprises a logic gate provided within a respective pixel sensor for each respective row of pixel sensors of the stitching block, said logic gate being coupled to a respective one of the first addressing lines and a respective one of the second addressing lines, so as to combine a row addressing action and a group addressing action, such that only one row of one row group of one stitching block is selected simultaneously; and wherein respective logic gates are distributed randomly or pseudo-randomly such that the positions of each logic gate in relation to their associated pixel sensors of the respective row of pixel sensors of the stitching block are not the same. <EOS>