A monolithic three-dimensional memory device comprising: at least one alternating stack of insulating layers and electrically conductive layers located over a semiconductor substrate ; memory openings extending through the at least one alternating stack , wherein each of the memory openings is filled with an epitaxial channel portion contacting a portion of the semiconductor substrate and a memory stack structure ; and support openings extending through the at least one alternating stack , wherein each of the support openings is filled with a support pillar structure , characterised in that : each of the memory stack structures and the support pillar structures comprise an instance of a layer stack including charge storage material portions, a tunneling dielectric layer, and at least one vertical semiconductor channel layer ; each instance of the layer stack in the memory stack structures is vertically spaced from the semiconductor substrate by the respective epitaxial channel portion ; and each instance of the layer stack in the support pillar structures is in physical contact with an impurity-doped semiconductor material portion of the semiconductor substrate , wherein the impurity-doped semiconductor material portion has a greater concentration of an impurity species than the portions of the semiconductor substrate that contact the epitaxial channel portions . at least one alternating stack of insulating layers and electrically conductive layers located over a semiconductor substrate ; memory openings extending through the at least one alternating stack , wherein each of the memory openings is filled with an epitaxial channel portion contacting a portion of the semiconductor substrate and a memory stack structure ; and support openings extending through the at least one alternating stack , wherein each of the support openings is filled with a support pillar structure , characterised in that : each of the memory stack structures and the support pillar structures comprise an instance of a layer stack including charge storage material portions, a tunneling dielectric layer, and at least one vertical semiconductor channel layer ; each instance of the layer stack in the memory stack structures is vertically spaced from the semiconductor substrate by the respective epitaxial channel portion ; and each instance of the layer stack in the support pillar structures is in physical contact with an impurity-doped semiconductor material portion of the semiconductor substrate , wherein the impurity-doped semiconductor material portion has a greater concentration of an impurity species than the portions of the semiconductor substrate that contact the epitaxial channel portions . each of the memory stack structures and the support pillar structures comprise an instance of a layer stack including charge storage material portions, a tunneling dielectric layer, and at least one vertical semiconductor channel layer ; each instance of the layer stack in the memory stack structures is vertically spaced from the semiconductor substrate by the respective epitaxial channel portion ; and each instance of the layer stack in the support pillar structures is in physical contact with an impurity-doped semiconductor material portion of the semiconductor substrate , wherein the impurity-doped semiconductor material portion has a greater concentration of an impurity species than the portions of the semiconductor substrate that contact the epitaxial channel portions . <EOS>