Method for forming at least one doped area intended to form a source or drain of a transistor , comprising the following steps: • Providing a stack comprising in a direction z at least one insulating layer , an active layer made of a semiconductor material overlying the insulating layer , and a transistor gate pattern overlying the active layer and having at least one lateral flank extending in a plane substantially perpendicular to an upper face of the active layer , • Removing a first portion of the active layer not overlaid by the gate pattern , said first portion extending up to vertically in line with the gate pattern directly at the rim of a second portion of the active layer , said second portion being located under the gate pattern , so as to expose an edge of said second portion , said edge extending in an extension of the lateral flank of the gate pattern , • Forming a first spacer in a first material on the lateral flank and on said edge , said first spacer having an L-shape and comprising a base portion in contact with the insulating layer and a lateral portion in contact with the lateral flank , said base portion having a thickness along the direction z substantially equal to the thickness of the active layer , • Forming a second spacer from a second material on the first spacer , said second spacer having a shape complementary to that of the first spacer , • Remove the base portion of the first spacer by selectively etching the first material with respect to the second material of the second spacer and the semiconductor material, so as to expose the edge of the second portion while at least partially retaining the side portion of the first spacer on the lateral flank of the gate pattern , • Forming the doped zone by epitaxy from said exposed edge . • Providing a stack comprising in a direction z at least one insulating layer , an active layer made of a semiconductor material overlying the insulating layer , and a transistor gate pattern overlying the active layer and having at least one lateral flank extending in a plane substantially perpendicular to an upper face of the active layer , • Removing a first portion of the active layer not overlaid by the gate pattern , said first portion extending up to vertically in line with the gate pattern directly at the rim of a second portion of the active layer , said second portion being located under the gate pattern , so as to expose an edge of said second portion , said edge extending in an extension of the lateral flank of the gate pattern , • Forming a first spacer in a first material on the lateral flank and on said edge , said first spacer having an L-shape and comprising a base portion in contact with the insulating layer and a lateral portion in contact with the lateral flank , said base portion having a thickness along the direction z substantially equal to the thickness of the active layer , • Forming a second spacer from a second material on the first spacer , said second spacer having a shape complementary to that of the first spacer , • Remove the base portion of the first spacer by selectively etching the first material with respect to the second material of the second spacer and the semiconductor material, so as to expose the edge of the second portion while at least partially retaining the side portion of the first spacer on the lateral flank of the gate pattern , • Forming the doped zone by epitaxy from said exposed edge . <EOS>