A Josephson memory array comprising a plurality of unit cells , each of the plurality of unit cells comprising: an internal sub-circuit comprising a plurality of π Josephson junctions , and first, second, third, and fourth quasi-long-Josephson-junction interconnects (E, Rm, D, B), each coupled to the internal sub-circuit at respective first, second, third, and fourth electrical nodes (e, r_m, d, b) of the sub-circuit , the interconnects including: a write enable line (E) configured to enable writing a binary memory state to the unit cell , a read enable line (Rm) configured to enable reading the binary memory state from the unit cell , a data input line (D) configured to provide the binary memory state to the unit cell , and a bit line (B) configured to read out the binary memory state from the unit cell , wherein each of the first, second, third, and fourth quasi-long-Josephson-junction interconnects (E, Rm, D, B) is adapted to connect together multiple ones of the plurality of unit cells in the memory array, wherein for each of the plurality of unit cells , the electrical node (e) of the sub-circuit to which the write enable line (E) is connected, the electrical node (d) of the sub-circuit to which the data input line (D) is connected, and the electrical node (r_m) of the sub-circuit to which the read enable line (Rm) is connected are each coupled to ground via a respective Josephson junction in the sub-circuit , and wherein each of the quasi-long-Josephson-junction interconnects is a Josephson transmission line having connecting inductors (L) of between about one picohenry and ten picrohenries. an internal sub-circuit comprising a plurality of π Josephson junctions , and first, second, third, and fourth quasi-long-Josephson-junction interconnects (E, Rm, D, B), each coupled to the internal sub-circuit at respective first, second, third, and fourth electrical nodes (e, r_m, d, b) of the sub-circuit , the interconnects including: a write enable line (E) configured to enable writing a binary memory state to the unit cell , a read enable line (Rm) configured to enable reading the binary memory state from the unit cell , a data input line (D) configured to provide the binary memory state to the unit cell , and a bit line (B) configured to read out the binary memory state from the unit cell , a write enable line (E) configured to enable writing a binary memory state to the unit cell , a read enable line (Rm) configured to enable reading the binary memory state from the unit cell , a data input line (D) configured to provide the binary memory state to the unit cell , and a bit line (B) configured to read out the binary memory state from the unit cell , wherein each of the first, second, third, and fourth quasi-long-Josephson-junction interconnects (E, Rm, D, B) is adapted to connect together multiple ones of the plurality of unit cells in the memory array, wherein for each of the plurality of unit cells , the electrical node (e) of the sub-circuit to which the write enable line (E) is connected, the electrical node (d) of the sub-circuit to which the data input line (D) is connected, and the electrical node (r_m) of the sub-circuit to which the read enable line (Rm) is connected are each coupled to ground via a respective Josephson junction in the sub-circuit , and wherein each of the quasi-long-Josephson-junction interconnects is a Josephson transmission line having connecting inductors (L) of between about one picohenry and ten picrohenries. <EOS>