A display device comprising: a first substrate ; a gate wiring on the first substrate , the gate wiring comprising a gate line and a gate electrode ; a data wiring which is disposed on the first substrate and insulated from the gate wiring , the data wiring comprising a data line , a source electrode , and a drain electrode , wherein the drain electrode comprises a first drain electrode portion partially overlapping the gate electrode and a second drain electrode portion ; a semiconductor layer overlapping the data wiring in a plan view and having a protrusion not overlapping the data wiring; a pixel electrode disposed on an insulating layer which is above the gate wiring and the data wiring so as to separate the pixel electrode from the data wiring , the pixel electrode being connected to the second drain electrode portion of the drain electrode through a contact hole ; a backlight shielding electrode at floating potential, disposed below the contact hole and shielding the semiconductor layer, wherein a second distance between the backlight shielding electrode and the gate line is provided, and wherein the gate electrode is spaced apart from the backlight shielding electrode at a third distance, characterised in that : the gate wiring further comprises a gate compensation portion protruding from the gate line to have a protrusion shape and spaced apart from the gate electrode at a first distance, which is different from the second distance; the drain electrode further comprises a third drain electrode portion , partially overlapping the gate compensation portion ; and the gate compensation portion is spaced apart from the backlight shielding electrode at a fourth distance, the second to fourth distances being equal. a first substrate ; a gate wiring on the first substrate , the gate wiring comprising a gate line and a gate electrode ; a data wiring which is disposed on the first substrate and insulated from the gate wiring , the data wiring comprising a data line , a source electrode , and a drain electrode , wherein the drain electrode comprises a first drain electrode portion partially overlapping the gate electrode and a second drain electrode portion ; a semiconductor layer overlapping the data wiring in a plan view and having a protrusion not overlapping the data wiring; a pixel electrode disposed on an insulating layer which is above the gate wiring and the data wiring so as to separate the pixel electrode from the data wiring , the pixel electrode being connected to the second drain electrode portion of the drain electrode through a contact hole ; a backlight shielding electrode at floating potential, disposed below the contact hole and shielding the semiconductor layer, wherein a second distance between the backlight shielding electrode and the gate line is provided, and wherein the gate electrode is spaced apart from the backlight shielding electrode at a third distance, characterised in that : the gate wiring further comprises a gate compensation portion protruding from the gate line to have a protrusion shape and spaced apart from the gate electrode at a first distance, which is different from the second distance; the drain electrode further comprises a third drain electrode portion , partially overlapping the gate compensation portion ; and the gate compensation portion is spaced apart from the backlight shielding electrode at a fourth distance, the second to fourth distances being equal. the gate wiring further comprises a gate compensation portion protruding from the gate line to have a protrusion shape and spaced apart from the gate electrode at a first distance, which is different from the second distance; the drain electrode further comprises a third drain electrode portion , partially overlapping the gate compensation portion ; and the gate compensation portion is spaced apart from the backlight shielding electrode at a fourth distance, the second to fourth distances being equal. <EOS>