A semiconductor structure for an electronic power switch, including: - a substrate of a first type of conductivity, having a lower face and an upper face , - a drain electrode (D) in contact with the lower face of the substrate , - a first semiconductor region of the first type of conductivity, having a lower surface arranged on the upper face of the substrate , and an upper surface provided with a contact area , - a source electrode (S) in contact with the contact area of the first semiconductor region , - a second semiconductor region , of a second type of conductivity, arranged inside the first semiconductor region , under the contact area , so as to delimit a first and a second conduction channels (C1, C2) of the first type of conductivity between the drain electrode (D) and the source electrode (S), the second conduction channel (C2) extending in a second substantially vertical direction and the first conduction channel (C1) extending in a first direction substantially perpendicular to the second direction, the semiconductor structure further including: - a first metal gate electrode (G1) independent of the source electrode and having at least a first portion in contact with the second semiconductor region , and at least a second portion in contact with the first semiconductor region so as to form a first Schottky-type junction, the first junction being surrounded by the second semiconductor region, and - a second metal gate electrode (G2) independent of the source electrode and having at least a first portion in contact with the upper surface of the first semiconductor region so as to form a second Schottky-type junction, the second gate electrode (G2) being arranged at a distance from the contact area . - a substrate of a first type of conductivity, having a lower face and an upper face , - a drain electrode (D) in contact with the lower face of the substrate , - a first semiconductor region of the first type of conductivity, having a lower surface arranged on the upper face of the substrate , and an upper surface provided with a contact area , - a source electrode (S) in contact with the contact area of the first semiconductor region , - a second semiconductor region , of a second type of conductivity, arranged inside the first semiconductor region , under the contact area , so as to delimit a first and a second conduction channels (C1, C2) of the first type of conductivity between the drain electrode (D) and the source electrode (S), the second conduction channel (C2) extending in a second substantially vertical direction and the first conduction channel (C1) extending in a first direction substantially perpendicular to the second direction, - a first metal gate electrode (G1) independent of the source electrode and having at least a first portion in contact with the second semiconductor region , and at least a second portion in contact with the first semiconductor region so as to form a first Schottky-type junction, the first junction being surrounded by the second semiconductor region, and - a second metal gate electrode (G2) independent of the source electrode and having at least a first portion in contact with the upper surface of the first semiconductor region so as to form a second Schottky-type junction, the second gate electrode (G2) being arranged at a distance from the contact area . <EOS>