A method of fabricating an erasable programmable single-poly nonvolatile memory, comprising the following sequence of steps: (S402) defining a first area (A) and a second area (B) in a first conductivity type substrate; (S404) forming a second conductivity type well region (NW) only in the first area (A); (S406) forming a first gate oxide layer and a second gate oxide layer on a surface of the first area (A), wherein the second gate oxide layer is extended over the second area (B); (S408) forming a second conductivity type double diffused drain region only in the second area (B); (S410) forming a first conductivity type well region (PW) only in the second area (B), wherein the first conductivity type well region (PW) is formed under the second conductivity type double diffused drain region ; (S412) processing the second gate oxide layer to form a first portion of the second gate oxide layer directly connected with a second portion of the second gate oxide layer , wherein a thickness of the first portion of the second gate oxide layer above the first area (A) is thicker than a thickness of the second portion of the second gate oxide layer above the second area (B); (S414) forming a first polysilicon gate and a second polysilicon gate , respectively on the first gate oxide layer and the second gate oxide layers for manufacturing a select transistor and a floating gate transistor in the first area (A), wherein the first polysilicon gate is a gate of said select transistor and the second polysilicon gate is a floating gate of said floating gate transistor; and (S416) forming a second conductivity type doped region in said second conductivity type double diffused drain region in the second area (B) and forming first conductivity type doped regions in the second conductivity type well region (NW) so as to manufacture said select transistor and said floating gate transistor connected in series when the formation of said first conductivity type doped regions is completed. (S402) defining a first area (A) and a second area (B) in a first conductivity type substrate; (S404) forming a second conductivity type well region (NW) only in the first area (A); (S406) forming a first gate oxide layer and a second gate oxide layer on a surface of the first area (A), wherein the second gate oxide layer is extended over the second area (B); (S408) forming a second conductivity type double diffused drain region only in the second area (B); (S410) forming a first conductivity type well region (PW) only in the second area (B), wherein the first conductivity type well region (PW) is formed under the second conductivity type double diffused drain region ; (S412) processing the second gate oxide layer to form a first portion of the second gate oxide layer directly connected with a second portion of the second gate oxide layer , wherein a thickness of the first portion of the second gate oxide layer above the first area (A) is thicker than a thickness of the second portion of the second gate oxide layer above the second area (B); (S414) forming a first polysilicon gate and a second polysilicon gate , respectively on the first gate oxide layer and the second gate oxide layers for manufacturing a select transistor and a floating gate transistor in the first area (A), wherein the first polysilicon gate is a gate of said select transistor and the second polysilicon gate is a floating gate of said floating gate transistor; and (S416) forming a second conductivity type doped region in said second conductivity type double diffused drain region in the second area (B) and forming first conductivity type doped regions in the second conductivity type well region (NW) so as to manufacture said select transistor and said floating gate transistor connected in series when the formation of said first conductivity type doped regions is completed. <EOS>