A method of operation within an integrated circuit device, the method comprising: shifting a first sequence of data bits into storage elements of a shift register during a first sequence of bit- time intervals; receiving a memory access command indicating that a second sequence of data bits is to be received within the integrated circuit device via an external data signaling path during a second sequence of bit- time intervals; receiving a data strobe signal via an external strobe signal line and shifting the second sequence of bits into the shift-register storage elements in response to transitions of the data strobe signal; determining, based at least in part on a temporal offset between the memory access command and a preceding memory access command, whether one or more bit-time intervals will transpire between the first and second sequences of bit time intervals; and overwriting contents of the shift-register storage elements with a predetermined set of seed bits if one or more bit-time intervals will transpire between the first and second sequences of bit-time intervals, wherein overwriting contents of the shift-register storage elements with the predetermined set of seed bits if one or more bit-time intervals will transpire between the first and second sequences of bits comprises loading the seed bits into the shift-register storage elements during the interval between first and second bit sequences; generating a plurality of equalization signals based, at least in part, on contents of the shift- register storage elements; and adjusting respective signal levels representative of one or more bits of the second sequence of data bits based on the plurality of equalization signals. shifting a first sequence of data bits into storage elements of a shift register during a first sequence of bit- time intervals; receiving a memory access command indicating that a second sequence of data bits is to be received within the integrated circuit device via an external data signaling path during a second sequence of bit- time intervals; receiving a data strobe signal via an external strobe signal line and shifting the second sequence of bits into the shift-register storage elements in response to transitions of the data strobe signal; determining, based at least in part on a temporal offset between the memory access command and a preceding memory access command, whether one or more bit-time intervals will transpire between the first and second sequences of bit time intervals; and overwriting contents of the shift-register storage elements with a predetermined set of seed bits if one or more bit-time intervals will transpire between the first and second sequences of bit-time intervals, wherein overwriting contents of the shift-register storage elements with the predetermined set of seed bits if one or more bit-time intervals will transpire between the first and second sequences of bits comprises loading the seed bits into the shift-register storage elements during the interval between first and second bit sequences; generating a plurality of equalization signals based, at least in part, on contents of the shift- register storage elements; and adjusting respective signal levels representative of one or more bits of the second sequence of data bits based on the plurality of equalization signals. <EOS>