A high electron mobility transistor (HEMT), comprising: a channel semiconductor structure including a stack of layers arranged on top of each other in an order of magnitudes of the polarization of materials of the layers to form multiple carrier channels at heterojunctions formed by each pair of layers in the stack, wherein the stack of layers includes a first layer and a second layer , wherein a magnitude of polarization of the first layer is greater than a magnitude of polarization of the second layer arranged in the stack below the first layer , and wherein the width of the first layer is less than the width of the second layer to form a staircase profile of the channel semiconductor structure; a source semiconductor structure including a heavily doped semiconductor material, the source semiconductor structure is electrically connected to the channel semiconductor structure to provide carriers to all carrier channels; a drain semiconductor structure including the heavily doped semiconductor material, the drain semiconductor structure is electrically connected to the channel semiconductor structure to receive the carriers on all carrier channels; and a source electrode arranged on the source semiconductor structure to make electrical contacts with each carrier channel; a drain electrode arranged on the drain semiconductor structure to make electrical contacts with each carrier channel; and a gate electrode arranged between the source electrode and the drain electrode along the length of the HEMT to modulate the conductivity of the carrier channels, wherein the gate electrode has a staircase shape having treads and risers tracking the staircase profile of the channel semiconductor structure, wherein the treads have different widths. a channel semiconductor structure including a stack of layers arranged on top of each other in an order of magnitudes of the polarization of materials of the layers to form multiple carrier channels at heterojunctions formed by each pair of layers in the stack, wherein the stack of layers includes a first layer and a second layer , wherein a magnitude of polarization of the first layer is greater than a magnitude of polarization of the second layer arranged in the stack below the first layer , and wherein the width of the first layer is less than the width of the second layer to form a staircase profile of the channel semiconductor structure; a source semiconductor structure including a heavily doped semiconductor material, the source semiconductor structure is electrically connected to the channel semiconductor structure to provide carriers to all carrier channels; a drain semiconductor structure including the heavily doped semiconductor material, the drain semiconductor structure is electrically connected to the channel semiconductor structure to receive the carriers on all carrier channels; and a source electrode arranged on the source semiconductor structure to make electrical contacts with each carrier channel; a drain electrode arranged on the drain semiconductor structure to make electrical contacts with each carrier channel; and a gate electrode arranged between the source electrode and the drain electrode along the length of the HEMT to modulate the conductivity of the carrier channels, wherein the gate electrode has a staircase shape having treads and risers tracking the staircase profile of the channel semiconductor structure, wherein the treads have different widths. <EOS>