A power amplification apparatus comprising: an inverse fast Fourier transform section configured to perform an inverse fast Fourier transformation on data allocated to a plurality of sub-carriers; a parallel/serial conversion section configured to convert time-domain data output in parallel from the inverse fast Fourier transform section into a time-domain analog signal, wherein the time-domain analog signal output from the parallel/serial conversion section includes a real-part time-domain analog signal and an imaginary-part time-domain analog signal; a power amplifier configured to perform a power amplification on the time-domain analog signal, wherein a saturation power output level of the power amplifier is adjustable in accordance with a switching signal; and a comparator configured to compare an amplitude in each time slot of the time-domain analog signal with a predetermined threshold; wherein the comparator includes: a real-part comparator configured to compare an amplitude in each time slot of the real-part time-domain analog signal with the predetermined threshold, and an imaginary-part comparator configured to compare an amplitude in each time slot of the imaginary-part time-domain analog signal with the predetermined threshold; wherein the power amplification apparatus further comprises a logical sum circuit configured to calculate a logical sum of outputs of the real-part comparator and the imaginary-part comparator; and wherein the saturation power output level of the power amplifier is switched based on an output of the logical sum circuit for each time slot of the time-domain analog signal. an inverse fast Fourier transform section configured to perform an inverse fast Fourier transformation on data allocated to a plurality of sub-carriers; a parallel/serial conversion section configured to convert time-domain data output in parallel from the inverse fast Fourier transform section into a time-domain analog signal, wherein the time-domain analog signal output from the parallel/serial conversion section includes a real-part time-domain analog signal and an imaginary-part time-domain analog signal; a power amplifier configured to perform a power amplification on the time-domain analog signal, wherein a saturation power output level of the power amplifier is adjustable in accordance with a switching signal; and a comparator configured to compare an amplitude in each time slot of the time-domain analog signal with a predetermined threshold; wherein the comparator includes: a real-part comparator configured to compare an amplitude in each time slot of the real-part time-domain analog signal with the predetermined threshold, and an imaginary-part comparator configured to compare an amplitude in each time slot of the imaginary-part time-domain analog signal with the predetermined threshold; wherein the power amplification apparatus further comprises a logical sum circuit configured to calculate a logical sum of outputs of the real-part comparator and the imaginary-part comparator; and wherein the saturation power output level of the power amplifier is switched based on an output of the logical sum circuit for each time slot of the time-domain analog signal. a real-part comparator configured to compare an amplitude in each time slot of the real-part time-domain analog signal with the predetermined threshold, and an imaginary-part comparator configured to compare an amplitude in each time slot of the imaginary-part time-domain analog signal with the predetermined threshold; wherein the power amplification apparatus further comprises a logical sum circuit configured to calculate a logical sum of outputs of the real-part comparator and the imaginary-part comparator; and wherein the saturation power output level of the power amplifier is switched based on an output of the logical sum circuit for each time slot of the time-domain analog signal. <EOS>