An array substrate, comprising: a substrate ; a plurality of data lines , formed on the substrate and extending in a first direction; a plurality of gate lines , formed on the substrate , crossing the plurality of data lines , and extending in a second direction perpendicular to the first direction; a plurality of pixel regions, defined by the plurality of gate lines and the plurality of data lines crossing each other and arranged in a matrix form, wherein each of the pixel regions is provided with a thin film transistor and a pixel electrode , wherein the thin film transistor comprises: a gate electrode connected with one of the plurality of gate lines ; a gate insulating layer provided above the gate line and the gate electrode ; an active layer formed on the gate insulating layer and disposed corresponding to the gate electrode ; a drain electrode and a source electrode disposed opposite to each other above the active layer and having a channel region of the thin film transistor therebetween; and a passivation layer provided on the source electrode , the drain electrode and the active layer , wherein at a position directly facing the gate line , the passivation layer is provided with a passivation layer through hole configured to perform a connection between the drain electrode and the pixel electrode ; characterized by a filling layer provided between the gate electrode and the gate line connected with the gate electrode , and the drain electrode and the source electrode ; and the channel region being in a U shape whose opening faces away from the corresponding data line. a substrate ; a plurality of data lines , formed on the substrate and extending in a first direction; a plurality of gate lines , formed on the substrate , crossing the plurality of data lines , and extending in a second direction perpendicular to the first direction; a plurality of pixel regions, defined by the plurality of gate lines and the plurality of data lines crossing each other and arranged in a matrix form, wherein each of the pixel regions is provided with a thin film transistor and a pixel electrode , wherein the thin film transistor comprises: a gate electrode connected with one of the plurality of gate lines ; a gate insulating layer provided above the gate line and the gate electrode ; an active layer formed on the gate insulating layer and disposed corresponding to the gate electrode ; a drain electrode and a source electrode disposed opposite to each other above the active layer and having a channel region of the thin film transistor therebetween; and a passivation layer provided on the source electrode , the drain electrode and the active layer , wherein at a position directly facing the gate line , the passivation layer is provided with a passivation layer through hole configured to perform a connection between the drain electrode and the pixel electrode ; a gate electrode connected with one of the plurality of gate lines ; a gate insulating layer provided above the gate line and the gate electrode ; an active layer formed on the gate insulating layer and disposed corresponding to the gate electrode ; a drain electrode and a source electrode disposed opposite to each other above the active layer and having a channel region of the thin film transistor therebetween; and a passivation layer provided on the source electrode , the drain electrode and the active layer , wherein at a position directly facing the gate line , the passivation layer is provided with a passivation layer through hole configured to perform a connection between the drain electrode and the pixel electrode ; characterized by a filling layer provided between the gate electrode and the gate line connected with the gate electrode , and the drain electrode and the source electrode ; and the channel region being in a U shape whose opening faces away from the corresponding data line. <EOS>