A memory circuit comprising: a memory area in which a plurality of memory cells are arranged in matrix fashion in a plurality of rows and columns, each of the plurality of memory cells including a bistable circuit configured to write data in a volatile manner, and a nonvolatile element (MTJ1, MTJ2) configured to store the data written in the bistable circuit in a nonvolatile manner and restore the data stored in a nonvolatile manner into the bistable circuit ; characterized in that the memory circuit further comprises: a control line (CTRL) directly connected to the nonvolatile element (MTJ1, MTJ2) of each of a plurality of memory cells arranged in one of a row and a column, wherein the nonvolatile element (MTJ1, MTJ2) has one end connected to a node (Q, QB) in the bistable circuit and has the other end directly connected to the control line (CTRL); a determining unit configured to determine that the data in the bistable circuit is the same as the data in the nonvolatile element (MTJ1, MTJ2) in each memory cell of the plurality of memory cells arranged in the one of the row and the column when a voltage of the control line (CTRL) is lower than a reference voltage, and to determine that the data in the bistable circuit is not the same as the data in the nonvolatile element (MTJ1, MTJ2) in each memory cell of the plurality of memory cells arranged in the one of the row and the column when the voltage of the control line (CTRL) is higher than the reference voltage; and a control unit located outside the memory area configured to apply, during a time period in which storing is performed in a memory cell, a low level voltage to the control line (CTRL) when the determining unit determines that the data in the bistable circuit is the same as the data in the nonvolatile element (MTJ1, MTJ2), and configured to apply, during the time period in which storing is performed in the memory cell, the low level voltage during part of said time period and a high level voltage during another part of said time period to the control line (CTRL) when the determining unit determines that the data in the bistable circuit is not the same as the data in the non-volatile element (MTJ1, MTJ2). a control line (CTRL) directly connected to the nonvolatile element (MTJ1, MTJ2) of each of a plurality of memory cells arranged in one of a row and a column, wherein the nonvolatile element (MTJ1, MTJ2) has one end connected to a node (Q, QB) in the bistable circuit and has the other end directly connected to the control line (CTRL); a determining unit configured to determine that the data in the bistable circuit is the same as the data in the nonvolatile element (MTJ1, MTJ2) in each memory cell of the plurality of memory cells arranged in the one of the row and the column when a voltage of the control line (CTRL) is lower than a reference voltage, and to determine that the data in the bistable circuit is not the same as the data in the nonvolatile element (MTJ1, MTJ2) in each memory cell of the plurality of memory cells arranged in the one of the row and the column when the voltage of the control line (CTRL) is higher than the reference voltage; and a control unit located outside the memory area configured to apply, during a time period in which storing is performed in a memory cell, a low level voltage to the control line (CTRL) when the determining unit determines that the data in the bistable circuit is the same as the data in the nonvolatile element (MTJ1, MTJ2), and configured to apply, during the time period in which storing is performed in the memory cell, the low level voltage during part of said time period and a high level voltage during another part of said time period to the control line (CTRL) when the determining unit determines that the data in the bistable circuit is not the same as the data in the non-volatile element (MTJ1, MTJ2). <EOS>