A power supply system comprising: a Quad Flat No-Lead (QFN)-type or Small Outline No-Lead (SON)-type leadframe having a plurality of leads and a pad with a first and a second pad surface, the first pad surface having a recessed portion and an un-recessed portion , the recessed portion having a depth and an outline suitable for attaching a plurality of semiconductor chips, the pad tie-able to a switch node terminal (V SW ) of the system; a first Field Effect Transistor (FET) chip having a drain terminal of the first FET chip attached to the recessed portion of the first pad surface , and further having a source terminal of the first FET chip and the gate terminal co-planar with the un-recessed portion of the first pad surface , the source terminal of the first FET chip tie-able to a board terminal (V OUT ) as a grounded output terminal (P GND ) of the system; a second FET chip having a source terminal of the second FET chip attached to the recessed portion of the first pad surface , and further having a drain terminal of the second FET chip and the gate terminal co-planar with the un-recessed portion of the first pad surface , the drain of the second FET chip tie-able to a board terminal as an input terminal (V IN ) of the system; and characterized by a driver-and-controller chip attached to the second pad surface , wherein the driver-and-controller chip has a plurality of terminals tied by bonding wires to respective leads of the leadframe; and a package encapsulating the driver-and-controller chip , the wires and the second surface of the pad and leads , but leaving the first pad surface and at least some of the plurality of leads un-encapsulated. a Quad Flat No-Lead (QFN)-type or Small Outline No-Lead (SON)-type leadframe having a plurality of leads and a pad with a first and a second pad surface, the first pad surface having a recessed portion and an un-recessed portion , the recessed portion having a depth and an outline suitable for attaching a plurality of semiconductor chips, the pad tie-able to a switch node terminal (V SW ) of the system; a first Field Effect Transistor (FET) chip having a drain terminal of the first FET chip attached to the recessed portion of the first pad surface , and further having a source terminal of the first FET chip and the gate terminal co-planar with the un-recessed portion of the first pad surface , the source terminal of the first FET chip tie-able to a board terminal (V OUT ) as a grounded output terminal (P GND ) of the system; a second FET chip having a source terminal of the second FET chip attached to the recessed portion of the first pad surface , and further having a drain terminal of the second FET chip and the gate terminal co-planar with the un-recessed portion of the first pad surface , the drain of the second FET chip tie-able to a board terminal as an input terminal (V IN ) of the system; and characterized by a driver-and-controller chip attached to the second pad surface , wherein the driver-and-controller chip has a plurality of terminals tied by bonding wires to respective leads of the leadframe; and a package encapsulating the driver-and-controller chip , the wires and the second surface of the pad and leads , but leaving the first pad surface and at least some of the plurality of leads un-encapsulated. <EOS>