A back contact structure of a solar cell, wherein the back contact structure comprises: a silicon substrate , the silicon substrate comprising a back surface comprising a plurality of recesses disposed at intervals; a first dielectric layer disposed on the back surface of the silicon substrate ; a plurality of first doped regions disposed only inside the plurality of recesses; wherein the plurality of first doped regions are disposed on the first dielectric layer inside the plurality of recesses; a plurality of second doped regions disposed on the first dielectric layer and disposed only at part of the regions outside the plurality of recesses, such that the first doped regions and the second doped regions are separated by portions of the silicon substrate not covered by the second doped regions; the plurality of first doped regions is a P-type doped region, and the plurality of second doped regions is an N-type doped region; or the plurality of first doped regions is an N-type doped region, and the plurality of second doped regions is a P-type doped region; a second dielectric layer disposed between the plurality of first doped regions and the plurality of second doped regions , wherein the second dielectric layer is at least one in number; and a conductive layer disposed on and contacting the plurality of first doped regions and the plurality of second doped regions ; the first dielectric layer is connected to the bottom walls of the recesses and the second dielectric layer is further connected to the sidewalls of the recesses; the portions of the silicon substrate located between the plurality of recesses and the plurality of second regions are covered only by the second dielectric layer; the second dielectric layer extends to partially cover the first and second doped regions. a silicon substrate , the silicon substrate comprising a back surface comprising a plurality of recesses disposed at intervals; a first dielectric layer disposed on the back surface of the silicon substrate ; a plurality of first doped regions disposed only inside the plurality of recesses; the plurality of first doped regions are disposed on the first dielectric layer inside the plurality of recesses; a plurality of second doped regions disposed on the first dielectric layer and disposed only at part of the regions outside the plurality of recesses, such that the first doped regions and the second doped regions are separated by portions of the silicon substrate not covered by the second doped regions; the plurality of first doped regions is a P-type doped region, and the plurality of second doped regions is an N-type doped region; or the plurality of first doped regions is an N-type doped region, and the plurality of second doped regions is a P-type doped region; a second dielectric layer disposed between the plurality of first doped regions and the plurality of second doped regions , wherein the second dielectric layer is at least one in number; and a conductive layer disposed on and contacting the plurality of first doped regions and the plurality of second doped regions ; the first dielectric layer is connected to the bottom walls of the recesses and the second dielectric layer is further connected to the sidewalls of the recesses; the portions of the silicon substrate located between the plurality of recesses and the plurality of second regions are covered only by the second dielectric layer; the second dielectric layer extends to partially cover the first and second doped regions. <EOS>