An integrated circuit chip device comprising a main processing circuit and a plurality of basic processing circuits, wherein the main processing circuit comprises a data type conversion circuit configured to convert data between a floating point data type and a fixed point data type; the plurality of basic processing circuits are arranged as an array, each basic processing circuit is connected to an adjacent basic processing circuit, the main processing circuit is connected to n basic processing circuits in a first row, n basic processing circuits in an m th row, and m basic processing circuits in a first column; the main processing circuit is configured to obtain an input data block, a weight data block, and a multiplication instruction, convert the input data block and the weight data block to an input data block of the fixed point type and a weight data block of the fixed point type through the data type conversion circuit, classify the input data block of the fixed point type into a distribution data block and the weight data block of the fixed point type into a broadcasting data block according to the multiplication instruction, partition the distribution data block to obtain a plurality of basic data blocks, distribute the plurality of basic data blocks to at least one of basic processing circuits connected to the main processing circuit, and broadcast the broadcasting data block to the basic processing circuits connected to the main processing circuit; the plurality of basic processing circuits are configured to perform computations of a neural network in parallel according to the broadcasting data block of the fixed point type and the basic data blocks of the fixed point type to obtain computation results, and transfer the computation results to the main processing circuit through the basic processing circuits connected to the main processing circuit; and the main processing circuit is configured to process the computation results to obtain an instruction result of the multiplication instruction. the plurality of basic processing circuits are arranged as an array, each basic processing circuit is connected to an adjacent basic processing circuit, the main processing circuit is connected to n basic processing circuits in a first row, n basic processing circuits in an m th row, and m basic processing circuits in a first column; the main processing circuit is configured to obtain an input data block, a weight data block, and a multiplication instruction, convert the input data block and the weight data block to an input data block of the fixed point type and a weight data block of the fixed point type through the data type conversion circuit, classify the input data block of the fixed point type into a distribution data block and the weight data block of the fixed point type into a broadcasting data block according to the multiplication instruction, partition the distribution data block to obtain a plurality of basic data blocks, distribute the plurality of basic data blocks to at least one of basic processing circuits connected to the main processing circuit, and broadcast the broadcasting data block to the basic processing circuits connected to the main processing circuit; the plurality of basic processing circuits are configured to perform computations of a neural network in parallel according to the broadcasting data block of the fixed point type and the basic data blocks of the fixed point type to obtain computation results, and transfer the computation results to the main processing circuit through the basic processing circuits connected to the main processing circuit; and the main processing circuit is configured to process the computation results to obtain an instruction result of the multiplication instruction. <EOS>