Method of semiconductor component manufacture, wherein - a semiconductor semi-finished product with an upper side and a lower side is provided, comprising a plurality of mutually adjacent semiconductor components in stack configuration, wherein the semiconductor components each comprise a substrate layer (SUB) with a III-V material or with germanium and the substrate layer (SUB) is arranged at or in the vicinity of the lower side , and on the substrate layer (SUB) a respective first semiconductor layer (HA1) of a first conductivity type is arranged and on the first semiconductor layer (HA1) at least one second semiconductor layer (HA2) of a second conductivity type is arranged, wherein the two semiconductor layers (HA1, HA2) comprise a III-V material or consist of a III-V material and the two conductivity types are different, and a scribe frame with a width (B1) is formed between two directly adjacent semiconductor components on the upper side of the semiconductor semifinished product , - prior to application of a masking layer the upper side of the semiconductor semi-finished product is coated by means of chemical gas phase deposition with a passivation layer (P) with a layer thickness of at least 100 nm and - prior to separation a masking layer (M) covering the semiconductor components and leaving free at least part of the scribe frame is applied to the upper side of the semiconductor semi-finished product and - after application of the masking layer (M) an ion implantation for at least partial amorphisation and/or insulation is carried out and the ion implantation comprises at least one implantation step with an energy of at least 500 keV and - after the ion implantation the masking layer (M) is removed and - after removal of the masking layer (M) semiconductor components are separated along the scribe frame. - a semiconductor semi-finished product with an upper side and a lower side is provided, comprising a plurality of mutually adjacent semiconductor components in stack configuration, wherein the semiconductor components each comprise a substrate layer (SUB) with a III-V material or with germanium and the substrate layer (SUB) is arranged at or in the vicinity of the lower side , and on the substrate layer (SUB) a respective first semiconductor layer (HA1) of a first conductivity type is arranged and on the first semiconductor layer (HA1) at least one second semiconductor layer (HA2) of a second conductivity type is arranged, wherein the two semiconductor layers (HA1, HA2) comprise a III-V material or consist of a III-V material and the two conductivity types are different, and a scribe frame with a width (B1) is formed between two directly adjacent semiconductor components on the upper side of the semiconductor semifinished product , - prior to application of a masking layer the upper side of the semiconductor semi-finished product is coated by means of chemical gas phase deposition with a passivation layer (P) with a layer thickness of at least 100 nm and - prior to separation a masking layer (M) covering the semiconductor components and leaving free at least part of the scribe frame is applied to the upper side of the semiconductor semi-finished product and - after application of the masking layer (M) an ion implantation for at least partial amorphisation and/or insulation is carried out and the ion implantation comprises at least one implantation step with an energy of at least 500 keV and - after the ion implantation the masking layer (M) is removed and - after removal of the masking layer (M) semiconductor components are separated along the scribe frame. <EOS>