A semiconductor device , comprising: a stack of layers comprising a common source layer , gate layers and insulating layers disposed on a substrate , the gate layers and insulating layers 154) being stacked alternatingly; an array of channel structures formed in an array region , each channel structure extending through the stack of layers forming a stack of transistors in a series configuration, each the channel structure comprising a channel layer that is conductively connected with the common source layer , the common source layer extending over the array region and a staircase region ; a contact structure disposed in the staircase region , the contact structure forming a conductive connection with the common source layer , wherein the common source layer comprises a source layer and a high conductive layer , wherein the high conductive layer is disposed between the source layer and the bottom most insulating layer , wherein the high conductive layer comprises at least one of metal, metal compound or metal silicide, wherein the source layer comprises a silicon layer; a gate line cut structure with a bottom high conductive layer in conductive connection and in direct contact with the high conductive layer , wherein the bottom high conductive layer comprises a different material than the high conductive layer , wherein the gate line cut structure comprises an upper insulating portion that is above the bottom high conductive layer ; and vertical memory cell strings formed as arrays in the respective channel structures in the array region , wherein the high conductive layer extends in the array region and forms an array common source, ACS. a stack of layers comprising a common source layer , gate layers and insulating layers disposed on a substrate , the gate layers and insulating layers 154) being stacked alternatingly; an array of channel structures formed in an array region , each channel structure extending through the stack of layers forming a stack of transistors in a series configuration, each the channel structure comprising a channel layer that is conductively connected with the common source layer , the common source layer extending over the array region and a staircase region ; a contact structure disposed in the staircase region , the contact structure forming a conductive connection with the common source layer , wherein the common source layer comprises a source layer and a high conductive layer , wherein the high conductive layer is disposed between the source layer and the bottom most insulating layer , wherein the high conductive layer comprises at least one of metal, metal compound or metal silicide, wherein the source layer comprises a silicon layer; a gate line cut structure with a bottom high conductive layer in conductive connection and in direct contact with the high conductive layer , wherein the bottom high conductive layer comprises a different material than the high conductive layer , wherein the gate line cut structure comprises an upper insulating portion that is above the bottom high conductive layer ; and vertical memory cell strings formed as arrays in the respective channel structures in the array region , wherein the high conductive layer extends in the array region and forms an array common source, ACS. <EOS>