A resistive random access memory apparatus comprising: a memory array comprising a plurality of bipolar resistive random access memory (RRAM) memory cells , each bipolar resistive random access memory (RRAM) memory cell comprising a selector element and a storage element electrically arranged in series and having a threshold voltage having a magnitude that is based at least in part on a time lapse from the bipolar resistive random access memory (RRAM) memory cell being released from a previous thresholding event; and a memory controller configured to cause an access operation, the access operation comprising application of a first voltage bias across at least one bipolar resistive random access memory (RRAM) memory cell of the plurality of bipolar resistive random access memory (RRAM) memory cells for a selection phase of the access operation and application of a second voltage bias, lower in magnitude than the first voltage bias, across the bipolar resistive random access memory (RRAM) memory cell for an access phase of the access operation, wherein the memory controller is further configured to cause a direction of current flowing through the bipolar resistive random access memory (RRAM) memory cell to be reversed between the selection phase and the access phase, and wherein the bipolar resistive random access memory (RRAM) memory cell is configured to threshold in response to application of the first voltage bias, and wherein the memory controller is further configured to remove the first voltage bias, and prior to application of the second voltage bias, cause a current flowing through the bipolar resistive random access memory (RRAM) memory cell to fall below a minimum hold current to release the bipolar resistive random access memory (RRAM) memory cell from a thresholded condition reverting back to an unthresholded state. a memory array comprising a plurality of bipolar resistive random access memory (RRAM) memory cells , each bipolar resistive random access memory (RRAM) memory cell comprising a selector element and a storage element electrically arranged in series and having a threshold voltage having a magnitude that is based at least in part on a time lapse from the bipolar resistive random access memory (RRAM) memory cell being released from a previous thresholding event; and a memory controller configured to cause an access operation, the access operation comprising application of a first voltage bias across at least one bipolar resistive random access memory (RRAM) memory cell of the plurality of bipolar resistive random access memory (RRAM) memory cells for a selection phase of the access operation and application of a second voltage bias, lower in magnitude than the first voltage bias, across the bipolar resistive random access memory (RRAM) memory cell for an access phase of the access operation, wherein the memory controller is further configured to cause a direction of current flowing through the bipolar resistive random access memory (RRAM) memory cell to be reversed between the selection phase and the access phase, and wherein the bipolar resistive random access memory (RRAM) memory cell is configured to threshold in response to application of the first voltage bias, and wherein the memory controller is further configured to remove the first voltage bias, and prior to application of the second voltage bias, cause a current flowing through the bipolar resistive random access memory (RRAM) memory cell to fall below a minimum hold current to release the bipolar resistive random access memory (RRAM) memory cell from a thresholded condition reverting back to an unthresholded state. <EOS>