A daisy-chain serial peripheral interface, SPI, integrated circuit, IC, , characterized by comprising: a first master input/slave output, MISO, interface circuit (MISO21); a second MISO interface circuit (MISO22); a first data enable interface circuit (DE21); a second data enable interface circuit (DE22); a routing circuit coupled to an input terminal of the first MISO interface circuit (MISO21), an output terminal of the second MISO interface circuit (MISO22), an input terminal of the first data enable interface circuit (DE21), and an output terminal of the second data enable interface circuit (DE22); and a core circuit coupled to the routing circuit , wherein when the daisy-chain SPI IC is a slave IC (S1, S2, S3, Sn) of a daisy-chain SPI architecture , and the daisy-chain SPI IC is a target slave circuit selected by a master IC (M1) of the daisy-chain SPI architecture for reading target data (Smiso21), the core circuit is configured to output a data enable signal (Sde21) to the master IC (M1) through the routing circuit and the first data enable interface circuit (DE21), and the core circuit is configured to send back the target data (Smiso21) to the master IC (M1) through the routing circuit and the first MISO interface circuit (MISO21) based on a timing of the data enable signal (Sde21); and when the daisy-chain SPI IC is the slave IC (S1, S2, S3, Sn) of the daisy-chain SPI architecture , and the daisy-chain SPI IC is not the target slave circuit, the routing circuit is configured to transmit a signal received by the second data enable interface circuit (DE22) to the first data enable interface circuit (DE21), and the routing circuit is configured to transmit data received by the second MISO interface circuit (MISO22) to the first MISO interface circuit (MISO21). a first master input/slave output, MISO, interface circuit (MISO21); a second MISO interface circuit (MISO22); a first data enable interface circuit (DE21); a second data enable interface circuit (DE22); a routing circuit coupled to an input terminal of the first MISO interface circuit (MISO21), an output terminal of the second MISO interface circuit (MISO22), an input terminal of the first data enable interface circuit (DE21), and an output terminal of the second data enable interface circuit (DE22); and a core circuit coupled to the routing circuit , wherein when the daisy-chain SPI IC is a slave IC (S1, S2, S3, Sn) of a daisy-chain SPI architecture , and the daisy-chain SPI IC is a target slave circuit selected by a master IC (M1) of the daisy-chain SPI architecture for reading target data (Smiso21), the core circuit is configured to output a data enable signal (Sde21) to the master IC (M1) through the routing circuit and the first data enable interface circuit (DE21), and the core circuit is configured to send back the target data (Smiso21) to the master IC (M1) through the routing circuit and the first MISO interface circuit (MISO21) based on a timing of the data enable signal (Sde21); and when the daisy-chain SPI IC is the slave IC (S1, S2, S3, Sn) of the daisy-chain SPI architecture , and the daisy-chain SPI IC is not the target slave circuit, the routing circuit is configured to transmit a signal received by the second data enable interface circuit (DE22) to the first data enable interface circuit (DE21), and the routing circuit is configured to transmit data received by the second MISO interface circuit (MISO22) to the first MISO interface circuit (MISO21). <EOS>