A method of authenticated encryption, comprising: generating , with an encryption circuit of a first processor component , a first digital signature of a plaintext message and a secure initialization vector, SIV, that is shared with a decryption circuit of a second processor component to be maintained at the decryption circuit as a local SIV; concatenating , with the encryption circuit , the first digital signature to the plaintext message to generate a concatenated message ; encrypting , with the encryption circuit , the concatenated message into a ciphertext ; extracting, with the encryption circuit , least significant bits of the SIV, IVC-LSB; concatenating the IVC-LSB to the ciphertext ; transmitting , with the first processor component and via a communications channel to the second processor component , the ciphertext and the concatenated IVC-LSB to enable a decryption circuit of the second processor component to authenticate plaintext messages ; incrementing, by the encryption circuit , the SIV after transmitting the ciphertext and the concatenated IVC-LSB; extracting, with the decryption circuit a portion of the local SIV; comparing the portion of the local SIV with the IVC-LSB concatenated to the ciphertext ; in response to the portion of the local SIV matching the IVC-LSB concatenated to the ciphertext , decrypting , with the decryption circuit , the ciphertext into a decrypted first digital signature and a decrypted plaintext message ; authenticating the decrypted plaintext message by comparing the decrypted first digital signature with a second digital signature of the decrypted plaintext message by the decryption circuit ; and after authenticating the decrypted plaintext message , incrementing, by the decryption circuit , the local SIV to match an increment by the encryption circuit of the SIV. generating , with an encryption circuit of a first processor component , a first digital signature of a plaintext message and a secure initialization vector, SIV, that is shared with a decryption circuit of a second processor component to be maintained at the decryption circuit as a local SIV; concatenating , with the encryption circuit , the first digital signature to the plaintext message to generate a concatenated message ; encrypting , with the encryption circuit , the concatenated message into a ciphertext ; extracting, with the encryption circuit , least significant bits of the SIV, IVC-LSB; concatenating the IVC-LSB to the ciphertext ; transmitting , with the first processor component and via a communications channel to the second processor component , the ciphertext and the concatenated IVC-LSB to enable a decryption circuit of the second processor component to authenticate plaintext messages ; incrementing, by the encryption circuit , the SIV after transmitting the ciphertext and the concatenated IVC-LSB; extracting, with the decryption circuit a portion of the local SIV; comparing the portion of the local SIV with the IVC-LSB concatenated to the ciphertext ; in response to the portion of the local SIV matching the IVC-LSB concatenated to the ciphertext , decrypting , with the decryption circuit , the ciphertext into a decrypted first digital signature and a decrypted plaintext message ; authenticating the decrypted plaintext message by comparing the decrypted first digital signature with a second digital signature of the decrypted plaintext message by the decryption circuit ; and after authenticating the decrypted plaintext message , incrementing, by the decryption circuit , the local SIV to match an increment by the encryption circuit of the SIV. <EOS>