A NAND flash memory logical unit comprising: a plurality of memory cells that are programmable and erasable; a control circuit configured to respond to a plurality of commands including at least read commands, program commands, and erase commands that are targeted at the plurality of memory cells; a communication bus interface communicatively coupled to the control circuit for providing read, program and erase commands to the control circuit from an external command source, wherein the control circuit comprises: a plurality of registers comprising an internal data register , an internal address register , an external data register , an external address register , a supplemental data register , and a supplemental address register ; and a command circuit for responding to the plurality of commands by controlling the plurality of registers, wherein the supplemental data register and the supplemental address register are dedicated to read commands, and are used to interrupt processing of a program command present in the internal data register (311 A) and the internal address register (311 B), wherein the command circuit determines that a read command is to interrupt an in-process program command in manner that the read command interrupts the in-process program command during a verify phase of the program operation corresponding to the in-process program command, and wherein the internal data register is a first internal data register, and the internal address register is a first internal address register, wherein the first internal data register and the first internal address register are dedicated to non-read commands. a plurality of memory cells that are programmable and erasable; a control circuit configured to respond to a plurality of commands including at least read commands, program commands, and erase commands that are targeted at the plurality of memory cells; a communication bus interface communicatively coupled to the control circuit for providing read, program and erase commands to the control circuit from an external command source, wherein the control circuit comprises: a plurality of registers comprising an internal data register , an internal address register , an external data register , an external address register , a supplemental data register , and a supplemental address register ; and a command circuit for responding to the plurality of commands by controlling the plurality of registers, a plurality of registers comprising an internal data register , an internal address register , an external data register , an external address register , a supplemental data register , and a supplemental address register ; and a command circuit for responding to the plurality of commands by controlling the plurality of registers, wherein the supplemental data register and the supplemental address register are dedicated to read commands, and are used to interrupt processing of a program command present in the internal data register (311 A) and the internal address register (311 B), wherein the command circuit determines that a read command is to interrupt an in-process program command in manner that the read command interrupts the in-process program command during a verify phase of the program operation corresponding to the in-process program command, and wherein the internal data register is a first internal data register, and the internal address register is a first internal address register, wherein the first internal data register and the first internal address register are dedicated to non-read commands. <EOS>