An integrated circuit, IC, device comprising: a substrate ; one of the two alternatives: (a) at least one connection component defining a cavity therethrough, said connection component coupled to said substrate ; or (b) a plurality of connection components defining a cavity therebetween, said plurality of connection components coupled to said substrate ; at least one memory die positioned in said cavity , said at least one memory die electrically coupled to said substrate ; and a logic die extending over said at least one memory die and at least a portion of said connection component , or at least a portion of said plurality of connection components , said at least one logic die being electrically coupled to said connection component , or to the plurality of connection components , and to said at least one memory die , wherein the connection component or the plurality of connection components is or are free of through silicon vias, and is or are electrically coupled to said substrate , wherein said connection component or said plurality of connection components comprises or comprise a redistribution wiring layer , comprising at least one wire bonding pad , said connection component or said plurality of connection components being electrically coupled to said substrate through at least one wire bond, and wherein at least one connection component or one or more of the plurality of connection components comprises or comprise at least one passive component, or in alternative one active electrical component, embedded therein, said passive component comprising one or more of the following: resistors, capacitors, and inductors, said active electrical component comprising one or more of the following: transistors, signal amplifiers, and signal filters. a substrate ; one of the two alternatives: (a) at least one connection component defining a cavity therethrough, said connection component coupled to said substrate ; or (b) a plurality of connection components defining a cavity therebetween, said plurality of connection components coupled to said substrate ; (a) at least one connection component defining a cavity therethrough, said connection component coupled to said substrate ; or (b) a plurality of connection components defining a cavity therebetween, said plurality of connection components coupled to said substrate ; at least one memory die positioned in said cavity , said at least one memory die electrically coupled to said substrate ; and a logic die extending over said at least one memory die and at least a portion of said connection component , or at least a portion of said plurality of connection components , said at least one logic die being electrically coupled to said connection component , or to the plurality of connection components , and to said at least one memory die , wherein the connection component or the plurality of connection components is or are free of through silicon vias, and is or are electrically coupled to said substrate , wherein said connection component or said plurality of connection components comprises or comprise a redistribution wiring layer , comprising at least one wire bonding pad , said connection component or said plurality of connection components being electrically coupled to said substrate through at least one wire bond, and wherein at least one connection component or one or more of the plurality of connection components comprises or comprise at least one passive component, or in alternative one active electrical component, embedded therein, said passive component comprising one or more of the following: resistors, capacitors, and inductors, said active electrical component comprising one or more of the following: transistors, signal amplifiers, and signal filters. <EOS>