An array structure comprising plural memory cells (c11∼c33) in an array arrangement, each of the plural memory cells (c11∼c33) comprising: a latch connected with a first node (a) and a second node (b), and receiving a first power voltage (Vdd) and a second power voltage (Vss), wherein the latch is connected with an enable line (EN), and the latch is selectively enabled or disabled according to an enable line voltage from the enable line (EN); a first antifuse element comprising a first antifuse transistor (Mf1) having a gate terminal connected with the antifuse control line (AF) and a first drain/source terminal coupled with the first node (a), wherein if a first voltage difference between the gate terminal and the first drain/source terminal of the first antifuse transistor (Mf1) exceeds a threshold value, a gate oxide layer of the first antifuse transistor (Mf1) is ruptured; a second antifuse element comprising a second antifuse transistor (Mf2) having a gate terminal connected with the antifuse control line (AF) and a first drain/source terminal coupled with the second node (b), wherein if a second voltage difference between the gate terminal and the first drain/source terminal of the second antifuse transistor (Mf2) exceeds the threshold value, a gate oxide layer of the second antifuse transistor (Mf2) is ruptured; a first select transistor (Ms1), wherein a gate terminal of the first select transistor (Ms1) is connected with a word line (WL), a first drain/source terminal of the first select transistor (Ms1) is connected with the first node (a), and a second drain/source terminal of the first select transistor (Ms1) is connected with a bit line (BL); and a second select transistor (Ms2), wherein a gate terminal of the second select transistor (Ms2) is connected with the word line (WL), a first drain/source terminal of the second select transistor (Ms2) is connected with the second node (b), and a second drain/source terminal of the second select transistor (Ms2) is connected with an inverted bit line (BLB). a latch connected with a first node (a) and a second node (b), and receiving a first power voltage (Vdd) and a second power voltage (Vss), wherein the latch is connected with an enable line (EN), and the latch is selectively enabled or disabled according to an enable line voltage from the enable line (EN); a first antifuse element comprising a first antifuse transistor (Mf1) having a gate terminal connected with the antifuse control line (AF) and a first drain/source terminal coupled with the first node (a), wherein if a first voltage difference between the gate terminal and the first drain/source terminal of the first antifuse transistor (Mf1) exceeds a threshold value, a gate oxide layer of the first antifuse transistor (Mf1) is ruptured; a second antifuse element comprising a second antifuse transistor (Mf2) having a gate terminal connected with the antifuse control line (AF) and a first drain/source terminal coupled with the second node (b), wherein if a second voltage difference between the gate terminal and the first drain/source terminal of the second antifuse transistor (Mf2) exceeds the threshold value, a gate oxide layer of the second antifuse transistor (Mf2) is ruptured; a first select transistor (Ms1), wherein a gate terminal of the first select transistor (Ms1) is connected with a word line (WL), a first drain/source terminal of the first select transistor (Ms1) is connected with the first node (a), and a second drain/source terminal of the first select transistor (Ms1) is connected with a bit line (BL); and a second select transistor (Ms2), wherein a gate terminal of the second select transistor (Ms2) is connected with the word line (WL), a first drain/source terminal of the second select transistor (Ms2) is connected with the second node (b), and a second drain/source terminal of the second select transistor (Ms2) is connected with an inverted bit line (BLB). <EOS>