A method for electroplating a copper deposit onto a semiconductor integrated circuit device substrate with electrical interconnect features including submicron-sized features having bottoms, sidewalls, and top openings, characterized by : immersing the semiconductor integrated circuit device substrate including submicron-sized features having bottoms, sidewalls, and top openings wherein said submicron-sized features include high aspect ratio features having dimensions such that the high aspect ratio features have aspect ratios of at least about 3:1 into an electrolytic plating composition comprising a source of Cu ions in an amount sufficient to electrolytically deposit Cu onto the substrate and into the electrical interconnect features, an accelerator comprising a compound of the formula R 1 -(S) n RXO 3 M, wherein M is hydrogen, alkali metal or ammonium as needed to satisfy the valence; X is S or P; R is an alkylene or cyclic alkylene group of 1 to 8 carbon atoms, an aromatic hydrocarbon or an aliphatic aromatic hydrocarbon of 6 to 12 carbon atoms; n is 1 to 6; and R 1 is MO 3 XR wherein M, X and R are as defined above, and a polyether suppressor compound comprising a combination of propylene oxide (PO) repeat units and ethylene oxide (EO) repeat units in a PO:EO ratio between about 1:9 and about 9:1 and covalently bonded to a cationic species comprising a nitrogen atom, wherein the molecular weight of the suppressor compound is between about 1000 and about 30,000 g/ mol; and supplying electrical current to the electrolytic composition to deposit Cu onto the substrate and superfill the submicron-sized features by rapid bottom-up deposition at a rate of growth in the vertical direction which is greater than a rate of growth in the horizontal direction. immersing the semiconductor integrated circuit device substrate including submicron-sized features having bottoms, sidewalls, and top openings wherein said submicron-sized features include high aspect ratio features having dimensions such that the high aspect ratio features have aspect ratios of at least about 3:1 into an electrolytic plating composition comprising a source of Cu ions in an amount sufficient to electrolytically deposit Cu onto the substrate and into the electrical interconnect features, an accelerator comprising a compound of the formula R 1 -(S) n RXO 3 M, wherein M is hydrogen, alkali metal or ammonium as needed to satisfy the valence; X is S or P; R is an alkylene or cyclic alkylene group of 1 to 8 carbon atoms, an aromatic hydrocarbon or an aliphatic aromatic hydrocarbon of 6 to 12 carbon atoms; n is 1 to 6; and R 1 is MO 3 XR wherein M, X and R are as defined above, and a polyether suppressor compound comprising a combination of propylene oxide (PO) repeat units and ethylene oxide (EO) repeat units in a PO:EO ratio between about 1:9 and about 9:1 and covalently bonded to a cationic species comprising a nitrogen atom, wherein the molecular weight of the suppressor compound is between about 1000 and about 30,000 g/ mol; and supplying electrical current to the electrolytic composition to deposit Cu onto the substrate and superfill the submicron-sized features by rapid bottom-up deposition at a rate of growth in the vertical direction which is greater than a rate of growth in the horizontal direction. <EOS>