A sample and hold circuit for converting an analog input signal into an output sampling signal , comprising a hold-capacitor unit , comprising a voltage-amplifier unit containing an input , to which an analog input-voltage signal can be applied, and containing an output , which is connected to the hold-capacitor unit , comprising an operating-point adjusting unit for generating a control signal applied to an output thereof, which signal is applied to a control input of the voltage-amplifier unit , a clock signal being applied to an input of the operating-point adjusting unit , in a sampling operation of the sample-and-hold circuit, an output signal applied to the output of the voltage-amplifier unit following an input signal applied to the input of the voltage-amplifier unit and, in a holding operation of the sample- and-hold circuit, the output signal of the voltage-amplifier unit being constant, comprising a clock-signal source for generating a sequence of the clock signals applied to the input of the operating-point adjusting unit (2, 2', 2", 2"', 2 IV ), the operating-point adjusting unit (2, 2', 2", 2"', 2 IV ) comprising electro-optical means for generating the control signal , the clock-signal source being configured as an optical clock-signal source, an optical pulse sequence having high and low clock signals being applied to the input of the operating-point adjusting unit (2, 2', 2", 2"', 2 IV ) in the form of a clock signal, and the operating-point adjusting unit being controlled in this way by means of the clock signal, the voltage-amplifier unit either being in holding operation or sampling operation, characterized in that - the operating-point adjusting unit (2, 2', 2", 2"', 2 IV ) comprises a reverse-voltage constant circuit , by means of which the photodiode (PD) can be operated in sampling operation at a constant reverse voltage, and in that the reverse-voltage constant circuit comprises a transistor (Q2, Q12) in a common base circuit, to the base of which a predetermined constant operating-point voltage source (V B ) is applied, and in that the photodiode (PD) is connected to an emitter terminal of the transistor (Q2, Q12) and in that the collector of the transistor (Q2, Q12) is connected to the output of the operating-point adjusting unit (2', 2"'), or - in that the operating-point adjusting unit (2", 2 IV ) comprises a base-emitter voltage-limiting circuit for limiting the base-emitter voltage (U BE ) of the emitter follower (Q1, Q11) of the voltage-amplifier unit in holding operation, a current (I EE ) flowing from the input of the voltage-amplifier unit via an input resistor (R1) of a base terminal of the emitter follower (Q1) in parallel therewith. - the operating-point adjusting unit (2, 2', 2", 2"', 2 IV ) comprises a reverse-voltage constant circuit , by means of which the photodiode (PD) can be operated in sampling operation at a constant reverse voltage, and in that the reverse-voltage constant circuit comprises a transistor (Q2, Q12) in a common base circuit, to the base of which a predetermined constant operating-point voltage source (V B ) is applied, and in that the photodiode (PD) is connected to an emitter terminal of the transistor (Q2, Q12) and in that the collector of the transistor (Q2, Q12) is connected to the output of the operating-point adjusting unit (2', 2"'), or - in that the operating-point adjusting unit (2", 2 IV ) comprises a base-emitter voltage-limiting circuit for limiting the base-emitter voltage (U BE ) of the emitter follower (Q1, Q11) of the voltage-amplifier unit in holding operation, a current (I EE ) flowing from the input of the voltage-amplifier unit via an input resistor (R1) of a base terminal of the emitter follower (Q1) in parallel therewith. <EOS>