A data caching method applying in a computer system including a processor , a cache , and a hybrid memory , wherein the method is executed by the cache, and comprises: receiving a data access request sent by the processor, wherein the data access request comprises an access address; determining , according to the access address, whether to-be-accessed data is cached in the cache; when the to-be-accessed data is not cached in the cache, determining , according to a historical access frequency of a cache line in the cache and a type of a memory corresponding to the cache line, whether a cache line that meets a first preset condition exists in the cache, wherein the cache line that meets the first preset condition comprises a cache line whose historical access frequency is lower than a preset frequency and that is corresponding to a memory of a dynamic random access memory, DRAM, type, and the hybrid memory comprises the memory of the DRAM type and a memory of a nonvolatile memory, NVM, type; selecting , when the cache line that meets the first preset condition exists in the cache, a to-be-replaced first cache line from the cache line that meets the first preset condition; and when no cache line that meets the first preset condition exists in the cache, determining whether a cache line that meets a second preset condition exists in the cache and selecting , when the cache line that meets the second preset condition exists in the cache, the to-be-replaced first cache line from the cache line that meets the second preset condition, wherein the cache line that meets the second preset condition comprises an unmodified cache line whose historical access frequency is lower than the preset frequency and that is corresponding to the memory of the NVM type; reading the to-be-accessed data from the hybrid memory according to the access address; replacing the first cache line with a second cache line, wherein the second cache line comprises the access address and the to-be-accessed data; sending the to-be-accessed data to the processor. receiving a data access request sent by the processor, wherein the data access request comprises an access address; determining , according to the access address, whether to-be-accessed data is cached in the cache; when the to-be-accessed data is not cached in the cache, determining , according to a historical access frequency of a cache line in the cache and a type of a memory corresponding to the cache line, whether a cache line that meets a first preset condition exists in the cache, wherein the cache line that meets the first preset condition comprises a cache line whose historical access frequency is lower than a preset frequency and that is corresponding to a memory of a dynamic random access memory, DRAM, type, and the hybrid memory comprises the memory of the DRAM type and a memory of a nonvolatile memory, NVM, type; selecting , when the cache line that meets the first preset condition exists in the cache, a to-be-replaced first cache line from the cache line that meets the first preset condition; and when no cache line that meets the first preset condition exists in the cache, determining whether a cache line that meets a second preset condition exists in the cache and selecting , when the cache line that meets the second preset condition exists in the cache, the to-be-replaced first cache line from the cache line that meets the second preset condition, wherein the cache line that meets the second preset condition comprises an unmodified cache line whose historical access frequency is lower than the preset frequency and that is corresponding to the memory of the NVM type; reading the to-be-accessed data from the hybrid memory according to the access address; replacing the first cache line with a second cache line, wherein the second cache line comprises the access address and the to-be-accessed data; sending the to-be-accessed data to the processor. <EOS>