A liquid crystal display comprising: a gate line (121a,b), a data line , and a compensation voltage line disposed on an insulation substrate ; a thin film transistor disposed on the insulation substrate and connected to the gate line (121a,b) and the data line ; a first passivation layer disposed on the gate line (121a,b), the data line , and the compensation voltage line ; a pixel electrode disposed on the first passivation layer and connected to the gate line (121a,b) and the data line through the thin film transistor, a compensation electrode (80-84) disposed on the first passivation layer and connected to the compensation voltage line ; and a common electrode arranged above the first passivation layer , wherein the compensation electrode (80-84) and the compensation voltage line are adapted to compensate a common voltage ripple generated by the capacitive coupling between the data line and the common electrode by applying a voltage of a polarity opposite to the common voltage ripple, wherein the compensation electrode (80-84) overlaps at least a portion of the data line , the compensation voltage line is formed from a same layer as the gate line (121a,b) or the data line , and the common electrode overlaps the data line and the compensation electrode (80-84), and wherein the compensation voltage line is connected to the compensation electrode (80-84) and not connected to the common electrode , the pixel electrode and the compensation electrode (80-84) are disposed on the same layer, and a second passivation layer is disposed between the pixel electrode and the common electrode and the second passivation layer is also disposed between the compensation electrode (80-84) and the common electrode . a gate line (121a,b), a data line , and a compensation voltage line disposed on an insulation substrate ; a thin film transistor disposed on the insulation substrate and connected to the gate line (121a,b) and the data line ; a first passivation layer disposed on the gate line (121a,b), the data line , and the compensation voltage line ; a pixel electrode disposed on the first passivation layer and connected to the gate line (121a,b) and the data line through the thin film transistor, a compensation electrode (80-84) disposed on the first passivation layer and connected to the compensation voltage line ; and a common electrode arranged above the first passivation layer , wherein the compensation electrode (80-84) and the compensation voltage line are adapted to compensate a common voltage ripple generated by the capacitive coupling between the data line and the common electrode by applying a voltage of a polarity opposite to the common voltage ripple, wherein the compensation electrode (80-84) overlaps at least a portion of the data line , the compensation voltage line is formed from a same layer as the gate line (121a,b) or the data line , and the common electrode overlaps the data line and the compensation electrode (80-84), and wherein the compensation voltage line is connected to the compensation electrode (80-84) and not connected to the common electrode , the pixel electrode and the compensation electrode (80-84) are disposed on the same layer, and a second passivation layer is disposed between the pixel electrode and the common electrode and the second passivation layer is also disposed between the compensation electrode (80-84) and the common electrode . <EOS>