A gate driver communication system , comprising: a cored transformer comprising a primary coil arranged on a primary side, a secondary coil arranged on a secondary side, and a core that links the primary coil to the secondary coil, wherein the secondary coil is configured to receive power signals and uplink data signals from the primary coil ; a primary side power signal generator coupled to the primary coil and configured to generate the power signals having a first frequency; a primary side data transmitter coupled to the primary coil and configured to generate the uplink data signals having a second frequency different from the first frequency; and a primary side controller configured to allocate the power signals and the uplink data signals to the primary coil according to a plurality of time slots, wherein the power signals are allocated to first time slots of the plurality of time slots and the uplink data signals are allocated to second times slots of the plurality of time slots, characterized in that : the primary side controller is configured to activate the primary side power signal generator and deactivate the primary side data transmitter during the first time slots, and the primary side controller is configured to activate the primary side data transmitter and deactivate the primary side power signal generator during the second time slots, and wherein the first frequency is less than the second frequency. a cored transformer comprising a primary coil arranged on a primary side, a secondary coil arranged on a secondary side, and a core that links the primary coil to the secondary coil, wherein the secondary coil is configured to receive power signals and uplink data signals from the primary coil ; a primary side power signal generator coupled to the primary coil and configured to generate the power signals having a first frequency; a primary side data transmitter coupled to the primary coil and configured to generate the uplink data signals having a second frequency different from the first frequency; and a primary side controller configured to allocate the power signals and the uplink data signals to the primary coil according to a plurality of time slots, wherein the power signals are allocated to first time slots of the plurality of time slots and the uplink data signals are allocated to second times slots of the plurality of time slots, characterized in that : the primary side controller is configured to activate the primary side power signal generator and deactivate the primary side data transmitter during the first time slots, and the primary side controller is configured to activate the primary side data transmitter and deactivate the primary side power signal generator during the second time slots, and wherein the first frequency is less than the second frequency. the primary side controller is configured to activate the primary side power signal generator and deactivate the primary side data transmitter during the first time slots, and the primary side controller is configured to activate the primary side data transmitter and deactivate the primary side power signal generator during the second time slots, and wherein the first frequency is less than the second frequency. <EOS>