A flying capacitor charging method, wherein the method is applied to a flying capacitor catching multi-level topology circuit, the multi-level topology circuit is connected to an input power source (DC1) via a first switch (K1), the multi-level topology circuit is connected to an output power source (DC2) via a second switch (K2), and the multi-level topology circuit comprises a plurality of flying capacitors (Cflyl, Cfly2); a first end of a first capacitor (Cflyl) in the plurality of flying capacitors is connected to a first electrode of a first semiconductor switch transistor (T2), a second end of the first capacitor (Cflyl) is connected to a second electrode of a second semiconductor switch transistor (T5), and a second electrode of the first semiconductor switch transistor (T2) is connected to a first electrode of the second semiconductor switch transistor (T5) via a second capacitor (Cfly2); a first end of the second capacitor (Cfly2) in the plurality of flying capacitors is connected to a first electrode of a third semiconductor switch transistor (T1), a second end of the second capacitor (Cfly2) is connected to a second electrode of a fourth semiconductor switch transistor (T6), and a second electrode of the third semiconductor switch transistor (T1) is connected to a first electrode of the fourth semiconductor switch transistor (T6) via a third capacitor (Cin); and the first capacitor (Cflyl) is any one of the plurality of flying capacitors, and the second capacitor (Cfly2) is any one of the plurality of flying capacitors and the third capacitor (Cin) is an input capacitor, an output capacitor, or a flying capacitor other than the first or second capacitor in the plurality of flying capacitors; and the method comprises: closing the first semiconductor switch transistor (T2), the second semiconductor switch transistor (T5), the third semiconductor switch transistor (T1) and the fourth semiconductor switch transistor (T6), to connect the first capacitor (Cfly 1) to the second capacitor (Cfly2) and the third capacitor (Cin) in parallel; charging the first capacitor (Cflyl) and the second capacitor (Cfly2) and the third capacitor (Cin) to a first specified voltage value; opening the first semiconductor switch transistor (T2) and the second semiconductor switch transistor (T5); and charging the second capacitor (Cfly2) and the third capacitor (Cin) to a second specified voltage value; opening the third semiconductor switch transistor (T1) and the fourth semiconductor switch transistor (T6); charging the third capacitor (Cin) to a specified voltage value, wherein the first specified voltage value is U*1/2 N , the second specified voltage value is U*1/2 N-1 , U is a voltage value of the input power source (DC1) or a voltage value of output power source (DC2), and N is the number of the plurality of flying capacitors. closing the first semiconductor switch transistor (T2), the second semiconductor switch transistor (T5), the third semiconductor switch transistor (T1) and the fourth semiconductor switch transistor (T6), to connect the first capacitor (Cfly 1) to the second capacitor (Cfly2) and the third capacitor (Cin) in parallel; charging the first capacitor (Cflyl) and the second capacitor (Cfly2) and the third capacitor (Cin) to a first specified voltage value; opening the first semiconductor switch transistor (T2) and the second semiconductor switch transistor (T5); and charging the second capacitor (Cfly2) and the third capacitor (Cin) to a second specified voltage value; opening the third semiconductor switch transistor (T1) and the fourth semiconductor switch transistor (T6); charging the third capacitor (Cin) to a specified voltage value, wherein the first specified voltage value is U*1/2 N , the second specified voltage value is U*1/2 N-1 , U is a voltage value of the input power source (DC1) or a voltage value of output power source (DC2), and N is the number of the plurality of flying capacitors. <EOS>