A signal receiving device comprising: a transition detecting device configured to, receive first to third input signals (A, B, C) wherein, in each of a plurality of unit intervals (UI1-UI5, UI11-UI18), the first to third input signals each have a different signal level relative to other ones of the first to third input signals, determine whether a signal level of a first differential signal (A-B), which is a differential signal between the first input signal and the second input signal among the first to third input signals, is greater than a first reference signal level (+Vth) to output a first comparison signal (PAB) of a plurality of comparison signals, and determine whether the signal level of the first differential signal is less than a second reference signal level (-Vth) different from the first reference signal level to output a second comparison signal (NAB) of the plurality of comparison signals, wherein the first reference signal level has a positive polarity and the second reference signal level has a negative polarity; and a clock data recovering device configured to recover a clock signal embedded in the first to third input signals based on the first comparison signal and the second comparison signal to generate a recovery clock signal (RECK). a transition detecting device configured to, receive first to third input signals (A, B, C) wherein, in each of a plurality of unit intervals (UI1-UI5, UI11-UI18), the first to third input signals each have a different signal level relative to other ones of the first to third input signals, determine whether a signal level of a first differential signal (A-B), which is a differential signal between the first input signal and the second input signal among the first to third input signals, is greater than a first reference signal level (+Vth) to output a first comparison signal (PAB) of a plurality of comparison signals, and determine whether the signal level of the first differential signal is less than a second reference signal level (-Vth) different from the first reference signal level to output a second comparison signal (NAB) of the plurality of comparison signals, wherein the first reference signal level has a positive polarity and the second reference signal level has a negative polarity; and receive first to third input signals (A, B, C) wherein, in each of a plurality of unit intervals (UI1-UI5, UI11-UI18), the first to third input signals each have a different signal level relative to other ones of the first to third input signals, determine whether a signal level of a first differential signal (A-B), which is a differential signal between the first input signal and the second input signal among the first to third input signals, is greater than a first reference signal level (+Vth) to output a first comparison signal (PAB) of a plurality of comparison signals, and determine whether the signal level of the first differential signal is less than a second reference signal level (-Vth) different from the first reference signal level to output a second comparison signal (NAB) of the plurality of comparison signals, wherein the first reference signal level has a positive polarity and the second reference signal level has a negative polarity; and a clock data recovering device configured to recover a clock signal embedded in the first to third input signals based on the first comparison signal and the second comparison signal to generate a recovery clock signal (RECK). <EOS>