A three-dimensional semiconductor memory device, comprising: a semiconductor layer including a cell array region (CAR) and a connection region (CNR); a plurality of first vertical structures (VS1) on the cell array region (CAR) and extending in a first direction perpendicular to a top surface of the semiconductor layer ; and a plurality of second vertical structures (VS2) on the connection region (CNR) and extending in the first direction, wherein each of the first vertical structures (VS1) comprises: a vertical semiconductor pattern (USP1) extending in the first direction and contacting the semiconductor layer ; and a first data storage pattern (VP1) surrounding a periphery of the vertical semiconductor pattern (USP1), and wherein each of the second vertical structures (VS2) comprises: an insulation structure (IP) extending in the first direction and contacting the semiconductor layer ; and a second data storage pattern (VP2) surrounding a periphery of the insulation structure (IP), the second data storage pattern (VP2) directly contacting a sidewall of the insulation structure (IP), wherein the insulation structure (IP) fills empty spaces defined by the second data storage patterns (VP2), wherein a bottom surface of the insulation structure (IP) of one of the second vertical structures (VS2) is lower than the top surface of the semiconductor layer . a semiconductor layer including a cell array region (CAR) and a connection region (CNR); a plurality of first vertical structures (VS1) on the cell array region (CAR) and extending in a first direction perpendicular to a top surface of the semiconductor layer ; and a plurality of second vertical structures (VS2) on the connection region (CNR) and extending in the first direction, wherein each of the first vertical structures (VS1) comprises: a vertical semiconductor pattern (USP1) extending in the first direction and contacting the semiconductor layer ; and a first data storage pattern (VP1) surrounding a periphery of the vertical semiconductor pattern (USP1), and a vertical semiconductor pattern (USP1) extending in the first direction and contacting the semiconductor layer ; and a first data storage pattern (VP1) surrounding a periphery of the vertical semiconductor pattern (USP1), and wherein each of the second vertical structures (VS2) comprises: an insulation structure (IP) extending in the first direction and contacting the semiconductor layer ; and a second data storage pattern (VP2) surrounding a periphery of the insulation structure (IP), the second data storage pattern (VP2) directly contacting a sidewall of the insulation structure (IP), wherein the insulation structure (IP) fills empty spaces defined by the second data storage patterns (VP2), an insulation structure (IP) extending in the first direction and contacting the semiconductor layer ; and a second data storage pattern (VP2) surrounding a periphery of the insulation structure (IP), the second data storage pattern (VP2) directly contacting a sidewall of the insulation structure (IP), wherein the insulation structure (IP) fills empty spaces defined by the second data storage patterns (VP2), wherein a bottom surface of the insulation structure (IP) of one of the second vertical structures (VS2) is lower than the top surface of the semiconductor layer . <EOS>