A processor to perform operations corresponding to a single-instruction, multiple-thread, SIMT, instruction, the SIMT instruction being a single instruction to have a format that is to include an opcode to indicate a reduction operation and a plurality of operands to indicate a mask for the reduction operation on a thread group and a plurality of registers to be used by the reduction operation, the processor including: the plurality of registers; and a plurality of compute units to respectively perform the SIMT instruction for corresponding threads of the thread group, to: perform the indicated reduction operation on a plurality of data elements, which are to be stored in the plurality of registers, which are indicated by the SIMT instruction and respectively correspond to the plurality of compute units, to generate a result data element to be stored in a destination register as indicated by the SIMT instruction, wherein the mask stored in a mask register is to have a plurality of first values that are each to indicate that a corresponding data element of the plurality of data elements is to be included in the reduction operation, and the mask is to have zero or more second values that are each to indicate that a corresponding additional data element is not to be included in the reduction operation; perform a synchronization indicated by the SIMT instruction to synchronize the threads of the thread group by causing the threads of the thread group to wait until all threads of the thread group have performed the SIMT instruction; and store the result data element in the destination register. the plurality of registers; and a plurality of compute units to respectively perform the SIMT instruction for corresponding threads of the thread group, to: perform the indicated reduction operation on a plurality of data elements, which are to be stored in the plurality of registers, which are indicated by the SIMT instruction and respectively correspond to the plurality of compute units, to generate a result data element to be stored in a destination register as indicated by the SIMT instruction, wherein the mask stored in a mask register is to have a plurality of first values that are each to indicate that a corresponding data element of the plurality of data elements is to be included in the reduction operation, and the mask is to have zero or more second values that are each to indicate that a corresponding additional data element is not to be included in the reduction operation; perform a synchronization indicated by the SIMT instruction to synchronize the threads of the thread group by causing the threads of the thread group to wait until all threads of the thread group have performed the SIMT instruction; and store the result data element in the destination register. perform the indicated reduction operation on a plurality of data elements, which are to be stored in the plurality of registers, which are indicated by the SIMT instruction and respectively correspond to the plurality of compute units, to generate a result data element to be stored in a destination register as indicated by the SIMT instruction, wherein the mask stored in a mask register is to have a plurality of first values that are each to indicate that a corresponding data element of the plurality of data elements is to be included in the reduction operation, and the mask is to have zero or more second values that are each to indicate that a corresponding additional data element is not to be included in the reduction operation; perform a synchronization indicated by the SIMT instruction to synchronize the threads of the thread group by causing the threads of the thread group to wait until all threads of the thread group have performed the SIMT instruction; and store the result data element in the destination register. <EOS>