A method for forming a mark structure, comprising: providing (S101) a substrate (200; 300) having a device region (240; 340) and a mark region including a first mark region (250; 350) and a second mark region (260; 360) surrounded by the first mark region; sequentially forming a device layer (210; 310), a dielectric layer (220; 320) and a mask layer (230; 330) on a surface of the substrate (200; 300); forming (S102) a first opening (241; 341) in the dielectric layer (220; 320) in the device region (240; 340), a first mark including a plurality of first mark trenches or a plurality of first mark protruding parts in the dielectric layer (220; 320) in the first mark region (250; 350), and a mark opening (261; 361) in the dielectric layer in the second mark region (260; 360), a bottom of the first opening (241; 341), a bottom of the first mark (251; 351) and a bottom of the mark opening (261; 361) being lower than a surface of the dielectric layer (220; 320), and higher than a surface of the device layer (210; 310); forming (S103) a second opening (242; 342) exposing the device layer (210; 310) in the dielectric layer (220; 320) on the bottom of the first opening (241; 341) and a second mark including a plurality of second mark trenches (262; 362) in the dielectric layer (220; 320) on the bottom of the mark opening (261; 361); and forming (S104) a conductive structure in the first opening (241; 341) and the second opening (242; 342); wherein the bottoms of the first mark trenches and the bottoms of the second mark trenches , or the bottoms of the second mark trenches , are lower than the surface of the dielectric layer (220; 320). providing (S101) a substrate (200; 300) having a device region (240; 340) and a mark region including a first mark region (250; 350) and a second mark region (260; 360) surrounded by the first mark region; sequentially forming a device layer (210; 310), a dielectric layer (220; 320) and a mask layer (230; 330) on a surface of the substrate (200; 300); forming (S102) a first opening (241; 341) in the dielectric layer (220; 320) in the device region (240; 340), a first mark including a plurality of first mark trenches or a plurality of first mark protruding parts in the dielectric layer (220; 320) in the first mark region (250; 350), and a mark opening (261; 361) in the dielectric layer in the second mark region (260; 360), a bottom of the first opening (241; 341), a bottom of the first mark (251; 351) and a bottom of the mark opening (261; 361) being lower than a surface of the dielectric layer (220; 320), and higher than a surface of the device layer (210; 310); forming (S103) a second opening (242; 342) exposing the device layer (210; 310) in the dielectric layer (220; 320) on the bottom of the first opening (241; 341) and a second mark including a plurality of second mark trenches (262; 362) in the dielectric layer (220; 320) on the bottom of the mark opening (261; 361); and forming (S104) a conductive structure in the first opening (241; 341) and the second opening (242; 342); wherein the bottoms of the first mark trenches and the bottoms of the second mark trenches , or the bottoms of the second mark trenches , are lower than the surface of the dielectric layer (220; 320). <EOS>