A method of verifying access to a Level-2, L2, cache, comprising: collecting transmission information associated with transmitted data sent by a single-core processor to a multi-core interconnect system; determining , using the collected transmission information, whether the transmitted data needs to access the L2 cache; storing , in a cache expectation queue, the determined transmitted data that needs to access the L2 cache; collecting access request information associated with an access request sent by the multi-core interconnect system to the L2 cache; and searching , according to the collected access request information, the cache expectation queue to find an expected transmitted data corresponding to the access request, wherein the searching comprises finding an error in response to a finding that there is no valid expected result in the cache expectation queue or there is a valid expected result but the expected result is inconsistent with an actual result, characterized by , when an error is not found: collecting feedback information sent by the L2 cache to the multi-core interconnect system; obtaining statuses of cache lines in the single-core processors according to the collected feedback information; determining whether the L2 cache is to be accessed again; updating corresponding entry information in the cache expectation queue in response to a determination that the L2 cache is to be accessed again; and deleting the corresponding entry information in the cache expectation queue in response to a determination that the L2 cache is not to be accessed again. collecting transmission information associated with transmitted data sent by a single-core processor to a multi-core interconnect system; determining , using the collected transmission information, whether the transmitted data needs to access the L2 cache; storing , in a cache expectation queue, the determined transmitted data that needs to access the L2 cache; collecting access request information associated with an access request sent by the multi-core interconnect system to the L2 cache; and searching , according to the collected access request information, the cache expectation queue to find an expected transmitted data corresponding to the access request, wherein the searching comprises finding an error in response to a finding that there is no valid expected result in the cache expectation queue or there is a valid expected result but the expected result is inconsistent with an actual result, characterized by , when an error is not found: collecting feedback information sent by the L2 cache to the multi-core interconnect system; obtaining statuses of cache lines in the single-core processors according to the collected feedback information; determining whether the L2 cache is to be accessed again; updating corresponding entry information in the cache expectation queue in response to a determination that the L2 cache is to be accessed again; and deleting the corresponding entry information in the cache expectation queue in response to a determination that the L2 cache is not to be accessed again. collecting feedback information sent by the L2 cache to the multi-core interconnect system; obtaining statuses of cache lines in the single-core processors according to the collected feedback information; determining whether the L2 cache is to be accessed again; updating corresponding entry information in the cache expectation queue in response to a determination that the L2 cache is to be accessed again; and deleting the corresponding entry information in the cache expectation queue in response to a determination that the L2 cache is not to be accessed again. <EOS>