An apparatus comprising: instruction decoding circuitry to decode instructions and generate control signals in dependence on the instructions; and data processing circuitry to perform data processing operations in response to the control signals generated by the instruction decoding circuitry, wherein the instruction decoding circuitry is responsive to a bit-testing instruction specifying a source vector register and an index to cause the data processing circuitry to: perform a bit-testing procedure on plural elements stored in the source vector register to generate plural result bits, the bit-testing procedure comprising for each processed element of the plural elements: setting a respective result bit of the plural result bits in dependence on a value of a tested bit at a bit position in the processed element of the source vector register indicated by the index; wherein in the bit-testing procedure an element of the plural elements is subjected to the bit-testing procedure as the processed element when a respective predicate bit of a set of predicate bit values has a first predetermined value, and wherein in the bit-testing procedure each of the plural result bits, corresponding to one of the predicate bit values that does not have the first predetermined value, is set to a same predetermined value. instruction decoding circuitry to decode instructions and generate control signals in dependence on the instructions; and data processing circuitry to perform data processing operations in response to the control signals generated by the instruction decoding circuitry, wherein the instruction decoding circuitry is responsive to a bit-testing instruction specifying a source vector register and an index to cause the data processing circuitry to: perform a bit-testing procedure on plural elements stored in the source vector register to generate plural result bits, the bit-testing procedure comprising for each processed element of the plural elements: setting a respective result bit of the plural result bits in dependence on a value of a tested bit at a bit position in the processed element of the source vector register indicated by the index; wherein in the bit-testing procedure an element of the plural elements is subjected to the bit-testing procedure as the processed element when a respective predicate bit of a set of predicate bit values has a first predetermined value, and wherein in the bit-testing procedure each of the plural result bits, corresponding to one of the predicate bit values that does not have the first predetermined value, is set to a same predetermined value. setting a respective result bit of the plural result bits in dependence on a value of a tested bit at a bit position in the processed element of the source vector register indicated by the index; wherein in the bit-testing procedure an element of the plural elements is subjected to the bit-testing procedure as the processed element when a respective predicate bit of a set of predicate bit values has a first predetermined value, and wherein in the bit-testing procedure each of the plural result bits, corresponding to one of the predicate bit values that does not have the first predetermined value, is set to a same predetermined value. <EOS>