An inverter circuit , comprising: a first node for coupling to a first electrical potential; a second node for coupling to a second electrical potential different from the first electrical potential; a third node configured to output an output signal of the inverter circuit; a plurality of transistors of a first conductivity type (140-1, ..., 140-N) coupled in series between the first node and the third node ; a plurality of transistors of a second conductivity type (150-1, ..., 150-M) coupled in series between the third node and the second node, the second conductivity type being different from the first conductivity type; a fourth node configured to receive an input signal to be inverted, wherein the input signal is a digital signal, wherein the fourth node is coupled to a gate terminal of one of the plurality of transistors of the first conductivity type (140-1, ..., 140-N) and a gate terminal of one of the plurality of transistors of the second conductivity type (150-1, ..., 150-M), and wherein the gate terminals of the other transistors of the plurality of transistors of the first conductivity type (140-1, ..., 140-N) and the plurality of transistors of the second conductivity type (150-1, ..., 150-M) are configured to receive a respective fixed electrical potential; and wherein a source terminal of the one of the plurality of transistors of the first conductivity type is coupled to the first node and a source terminal of the one of the plurality of transistors of the second conductivity type is coupled to the second node ; and characterized by at least one coupling path (160, ..., 163) comprising a capacitive element (165, ..., 168), wherein the at least one coupling path (160, ..., 163) is coupled between a source terminal of one of the other transistors of the plurality of transistors of the first conductivity type (140-1, ..., 140-N) and a source terminal of one of the other transistors of the plurality of transistors of the second conductivity type (150-1, ..., 150-M). a first node for coupling to a first electrical potential; a second node for coupling to a second electrical potential different from the first electrical potential; a third node configured to output an output signal of the inverter circuit; a plurality of transistors of a first conductivity type (140-1, ..., 140-N) coupled in series between the first node and the third node ; a plurality of transistors of a second conductivity type (150-1, ..., 150-M) coupled in series between the third node and the second node, the second conductivity type being different from the first conductivity type; a fourth node configured to receive an input signal to be inverted, wherein the input signal is a digital signal, wherein the fourth node is coupled to a gate terminal of one of the plurality of transistors of the first conductivity type (140-1, ..., 140-N) and a gate terminal of one of the plurality of transistors of the second conductivity type (150-1, ..., 150-M), and wherein the gate terminals of the other transistors of the plurality of transistors of the first conductivity type (140-1, ..., 140-N) and the plurality of transistors of the second conductivity type (150-1, ..., 150-M) are configured to receive a respective fixed electrical potential; and wherein a source terminal of the one of the plurality of transistors of the first conductivity type is coupled to the first node and a source terminal of the one of the plurality of transistors of the second conductivity type is coupled to the second node ; and characterized by at least one coupling path (160, ..., 163) comprising a capacitive element (165, ..., 168), wherein the at least one coupling path (160, ..., 163) is coupled between a source terminal of one of the other transistors of the plurality of transistors of the first conductivity type (140-1, ..., 140-N) and a source terminal of one of the other transistors of the plurality of transistors of the second conductivity type (150-1, ..., 150-M). <EOS>