A level shifter for receiving an input (A) of a first voltage domain and generating an output of a second voltage domain (OUTPUT), wherein a "0" in the first voltage domain is a first voltage and a "1" in the first voltage domain is a second voltage (VDDL) and a "0" in the second voltage domain is the first voltage and a "1" in the second voltage domain is a third voltage (VDDH) different than the second voltage, the level shifter comprising: a first power source providing the third voltage; a first PMOS transistor comprising a first terminal coupled to the first power source, a gate, and a second terminal; a second PMOS transistor comprising a first terminal coupled to the first power source, a gate coupled to the second terminal of the first PMOS transistor, and a second terminal coupled to the gate of the first PMOS transistor and to an output node for providing the output; a first NMOS transistor comprising a first terminal coupled to the second terminal of the first PMOS transistor, a gate configured to receive a first signal (AA); and a second terminal configured to receive a complement of the input; a second NMOS transistor comprising a first terminal coupled to the second terminal of the first PMOS transistor, a gate configured to receive the input, and a second terminal coupled to the first voltage; a third NMOS transistor comprising a first terminal coupled to the output node, a gate configured to receive the complement of the input, and a second terminal coupled to the first voltage; and a fourth NMOS transistor comprising a first terminal coupled to the output node, a gate coupled to receive a second signal (AA_BAR), and a second terminal configured to receive the input; wherein the first signal is floating or is twice the second voltage when the input is at the second voltage and is the second voltage when the input is at the first voltage; and wherein the second signal is floating or is twice the second voltage when the input is at the first voltage and is the second voltage when the input is at the second voltage. a first power source providing the third voltage; a first PMOS transistor comprising a first terminal coupled to the first power source, a gate, and a second terminal; a second PMOS transistor comprising a first terminal coupled to the first power source, a gate coupled to the second terminal of the first PMOS transistor, and a second terminal coupled to the gate of the first PMOS transistor and to an output node for providing the output; a first NMOS transistor comprising a first terminal coupled to the second terminal of the first PMOS transistor, a gate configured to receive a first signal (AA); and a second terminal configured to receive a complement of the input; a second NMOS transistor comprising a first terminal coupled to the second terminal of the first PMOS transistor, a gate configured to receive the input, and a second terminal coupled to the first voltage; a third NMOS transistor comprising a first terminal coupled to the output node, a gate configured to receive the complement of the input, and a second terminal coupled to the first voltage; and a fourth NMOS transistor comprising a first terminal coupled to the output node, a gate coupled to receive a second signal (AA_BAR), and a second terminal configured to receive the input; wherein the first signal is floating or is twice the second voltage when the input is at the second voltage and is the second voltage when the input is at the first voltage; and wherein the second signal is floating or is twice the second voltage when the input is at the first voltage and is the second voltage when the input is at the second voltage. <EOS>