A computer-implemented method of transforming a high-level program for mapping onto a reconfigurable data processor with an array of configurable units , the method including: partitioning a dataflow graph of the high-level program into memory allocations and execution fragments , wherein the memory allocations represent creation of logical memory spaces in on-processor and/or off-processor memories for data required to implement the dataflow graph , and the execution fragments require operations on the data including loading the data from allocated memory and computing with the data; designating the memory allocations to virtual memory units and designating the execution fragments to virtual compute units ; partitioning the execution fragments into memory fragments and compute fragments , wherein each memory fragment of the memory fragments includes an address calculation operation leading up to a memory access operation, and wherein each compute fragment of the compute fragments comprises all other operations of a respective execution fragment of the execution fragments ; assigning the memory fragments to the virtual memory units and assigning the compute fragments to the virtual compute units ; allocating the virtual memory units to physical memory units and allocating the virtual compute units to physical compute units ; placing the physical memory units and the physical compute units onto positions in the array of configurable units and routing data and control networks between the placed positions; and generating a bit file with configuration data for the placed positions and the routed data and control networks, wherein the bit file , when loaded onto an instance of the array of configurable units , causes the array of configurable units to implement the dataflow graph . partitioning a dataflow graph of the high-level program into memory allocations and execution fragments , wherein the memory allocations represent creation of logical memory spaces in on-processor and/or off-processor memories for data required to implement the dataflow graph , and the execution fragments require operations on the data including loading the data from allocated memory and computing with the data; designating the memory allocations to virtual memory units and designating the execution fragments to virtual compute units ; partitioning the execution fragments into memory fragments and compute fragments , wherein each memory fragment of the memory fragments includes an address calculation operation leading up to a memory access operation, and wherein each compute fragment of the compute fragments comprises all other operations of a respective execution fragment of the execution fragments ; assigning the memory fragments to the virtual memory units and assigning the compute fragments to the virtual compute units ; allocating the virtual memory units to physical memory units and allocating the virtual compute units to physical compute units ; placing the physical memory units and the physical compute units onto positions in the array of configurable units and routing data and control networks between the placed positions; and generating a bit file with configuration data for the placed positions and the routed data and control networks, wherein the bit file , when loaded onto an instance of the array of configurable units , causes the array of configurable units to implement the dataflow graph . <EOS>