A hardware monitor configured to be used by a formal verification tool to verify that an integrated circuit defined by a hardware design meets a power requirement , the hardware monitor comprising: one or more flip-flop transition detection logic units , wherein each flip-flop transition detection logic unit is configured to detect a flip-flop transition of one of one or more flip-flops of the hardware design ; one or more clock trigger signal transition detection logic units , wherein each clock trigger signal transition detection logic unit is configured to detect a clock trigger signal transition of one of the one or more flip-flops ; a first counter for each of the one or more flip-flops configured to store a count of the number of flip-flop transitions for that flip-flop; a second counter for each of the one or more flip-flops configured to store a count of the number of clock trigger signal transitions for that flip-flop; a first counter update logic unit in communication with the one or more flip-flop transition detection logic units , the first counter update logic unit configured to update the first counter for a flip-flop after the flip-flop transition detection logic unit for that flip-flop detects a flip-flop transition; a second counter update logic unit configured to update the second counter for a flip-flop after the clock trigger signal transition detection logic unit for that flip-flop detects a clock trigger signal transition; and a property verification logic unit configured to determine whether the power requirement is met at a particular point in time by evaluating a cover property for each of the one or more flip-flops that the number of clock trigger signal transitions counted by the second counter for that flip-flop is greater than the number of flip-flop transitions counted by the first counter for that flip-flop, wherein each cover property is written in an assertion language for being formally verified by the formal verification tool . one or more flip-flop transition detection logic units , wherein each flip-flop transition detection logic unit is configured to detect a flip-flop transition of one of one or more flip-flops of the hardware design ; one or more clock trigger signal transition detection logic units , wherein each clock trigger signal transition detection logic unit is configured to detect a clock trigger signal transition of one of the one or more flip-flops ; a first counter for each of the one or more flip-flops configured to store a count of the number of flip-flop transitions for that flip-flop; a second counter for each of the one or more flip-flops configured to store a count of the number of clock trigger signal transitions for that flip-flop; a first counter update logic unit in communication with the one or more flip-flop transition detection logic units , the first counter update logic unit configured to update the first counter for a flip-flop after the flip-flop transition detection logic unit for that flip-flop detects a flip-flop transition; a second counter update logic unit configured to update the second counter for a flip-flop after the clock trigger signal transition detection logic unit for that flip-flop detects a clock trigger signal transition; and a property verification logic unit configured to determine whether the power requirement is met at a particular point in time by evaluating a cover property for each of the one or more flip-flops that the number of clock trigger signal transitions counted by the second counter for that flip-flop is greater than the number of flip-flop transitions counted by the first counter for that flip-flop, wherein each cover property is written in an assertion language for being formally verified by the formal verification tool . <EOS>