A method of forming a three-dimensional memory device, comprising: forming at least one sacrificial semiconductor structure (114;114L) over a substrate ; forming source-level memory openings at a level of the at least one sacrificial semiconductor structure (114;114L); forming sacrificial semiconductor pedestals within the source-level memory openings ; forming a vertically alternating stack of insulating layers and spacer material layers over the at least one sacrificial semiconductor structure (114;114L), wherein the spacer material layers are formed as, or are subsequently replaced with, electrically conductive layers ; forming memory openings through the vertically alternating stack by etching through the vertically alternating stack and removing the sacrificial semiconductor pedestals , wherein each of the memory openings includes a volume of a respective one of the sacrificial semiconductor pedestals , and a lower portion of each memory opening has a bulging portion that has a greater lateral dimension than an overlying portion of the memory opening ; forming memory stack structures in the memory openings , each memory stack structure including a semiconductor channel and a memory film laterally surrounding the semiconductor channel , wherein a lower portion of each memory stack structure has a bulging portion that has a greater lateral dimension than an overlying portion of the respective memory stack structure ; forming at least one source cavity by removing the at least one sacrificial semiconductor structure (114;114L) and portions of each memory film adjacent to the at least one sacrificial semiconductor structure (114;114L); and forming at least one source strap structure in the at least one source cavity and directly on sidewalls of the semiconductor channels . forming at least one sacrificial semiconductor structure (114;114L) over a substrate ; forming source-level memory openings at a level of the at least one sacrificial semiconductor structure (114;114L); forming sacrificial semiconductor pedestals within the source-level memory openings ; forming a vertically alternating stack of insulating layers and spacer material layers over the at least one sacrificial semiconductor structure (114;114L), wherein the spacer material layers are formed as, or are subsequently replaced with, electrically conductive layers ; forming memory openings through the vertically alternating stack by etching through the vertically alternating stack and removing the sacrificial semiconductor pedestals , wherein each of the memory openings includes a volume of a respective one of the sacrificial semiconductor pedestals , and a lower portion of each memory opening has a bulging portion that has a greater lateral dimension than an overlying portion of the memory opening ; forming memory stack structures in the memory openings , each memory stack structure including a semiconductor channel and a memory film laterally surrounding the semiconductor channel , wherein a lower portion of each memory stack structure has a bulging portion that has a greater lateral dimension than an overlying portion of the respective memory stack structure ; forming at least one source cavity by removing the at least one sacrificial semiconductor structure (114;114L) and portions of each memory film adjacent to the at least one sacrificial semiconductor structure (114;114L); and forming at least one source strap structure in the at least one source cavity and directly on sidewalls of the semiconductor channels . <EOS>