A method for fabricating an NAND flash memory, comprising: providing a semiconductor substrate including a core region and a peripheral region; forming a plurality of discrete gate stack structures in the core region with neighboring gate stack structures separated by a trench ; forming a first dielectric layer to fill each trench , wherein voids and seams are formed in a top portion of said first dielectric layer ; forming a flowable dielectric layer on the first dielectric layer and the gate stack structures; performing a solidification treatment process on the flowable dielectric layer to form a solid dielectric layer , wherein said voids and seams formed in a top portion of the first dielectric layer are filled by the solid dielectric layer , wherein preferably a thickness of the solid dielectric layer is greater than 200 Å; performing an etch-back process to remove the solid dielectric layer and a portion of the first dielectric layer to expose at least a top portion of the gate stack structures; forming a metal silicide layer on an exposed portion of the gate stack structures and the first dielectric layer , wherein preferably the metal silicide layer is made of one of NiSi, WSi, MoSi, TiSi, CoSi, and TISi; and removing a portion of the metal silicide layer formed on the first dielectric layer , characterized in that the solid dielectric layer is SiO 2 and is formed by a fluid chemical vapor deposition, CVD, method, including a deposition process and a conversion process following the deposition process, wherein during the deposition process, a silica SiO x precursor is used to react with ammonia plasma to form a flowable polymer through free radical polymerization, said flowable polymer being said flowable dielectric layer and filling said voids and seams formed in a top surface of said first dielectric layer ; and during the conversion process, ozone steam at a temperature between 100 °C and 200 °C is used to convert said flowable polymer into solid SiO 2 through oxidation, said conversion process being said solidification process treatment. providing a semiconductor substrate including a core region and a peripheral region; forming a plurality of discrete gate stack structures in the core region with neighboring gate stack structures separated by a trench ; forming a first dielectric layer to fill each trench , wherein voids and seams are formed in a top portion of said first dielectric layer ; forming a flowable dielectric layer on the first dielectric layer and the gate stack structures; performing a solidification treatment process on the flowable dielectric layer to form a solid dielectric layer , wherein said voids and seams formed in a top portion of the first dielectric layer are filled by the solid dielectric layer , wherein preferably a thickness of the solid dielectric layer is greater than 200 Å; performing an etch-back process to remove the solid dielectric layer and a portion of the first dielectric layer to expose at least a top portion of the gate stack structures; forming a metal silicide layer on an exposed portion of the gate stack structures and the first dielectric layer , wherein preferably the metal silicide layer is made of one of NiSi, WSi, MoSi, TiSi, CoSi, and TISi; and removing a portion of the metal silicide layer formed on the first dielectric layer , wherein during the deposition process, a silica SiO x precursor is used to react with ammonia plasma to form a flowable polymer through free radical polymerization, said flowable polymer being said flowable dielectric layer and filling said voids and seams formed in a top surface of said first dielectric layer ; and during the conversion process, ozone steam at a temperature between 100 °C and 200 °C is used to convert said flowable polymer into solid SiO 2 through oxidation, said conversion process being said solidification process treatment. <EOS>