A method of manufacturing first and second trenches (T1,T2) in a semiconductor body (SB), comprising the following steps in the following order: A) providing a semiconductor body, B) depositing and structuring a hard mask on a surface of the semiconductor body, the hard mask having first elongated openings of a first width (W1) and second elongated openings of a second width (W2), which is larger than the first width (W1), C) etching first trenches (T1) to a first depth (d0) into the semiconductor body through the first openings of the hard mask and second trenches (T2) to a second depth (d2), which is larger than the first depth, into the semiconductor body through the second openings of the hard mask in a common RIE etching step for all trenches at the same time, D) introducing a dopant into the sidewalls of at least one of the first trenches, E) covering the sidewalls of the first and second trenches with a dielectric, F) driving the dopant into a region surrounding said at least one first trench (T1), wherein - introducing the dopant into the sidewalls of the first trench comprises - depositing a dopant source layer to the entire surface of the semiconductor body and the sidewalls of the trenches, - structuring same such that the remaining portion of the dopant source layer covers the sidewalls and an adjacent region of the first trench, and - driving the dopant out of the source layer into said sidewalls, and removing the source layer, and - step D) is repeated to introduce a dopant of opposite conductivity type into the sidewalls of another one of the first trenches. A) providing a semiconductor body, B) depositing and structuring a hard mask on a surface of the semiconductor body, the hard mask having first elongated openings of a first width (W1) and second elongated openings of a second width (W2), which is larger than the first width (W1), C) etching first trenches (T1) to a first depth (d0) into the semiconductor body through the first openings of the hard mask and second trenches (T2) to a second depth (d2), which is larger than the first depth, into the semiconductor body through the second openings of the hard mask in a common RIE etching step for all trenches at the same time, D) introducing a dopant into the sidewalls of at least one of the first trenches, E) covering the sidewalls of the first and second trenches with a dielectric, F) driving the dopant into a region surrounding said at least one first trench (T1), wherein - introducing the dopant into the sidewalls of the first trench comprises - depositing a dopant source layer to the entire surface of the semiconductor body and the sidewalls of the trenches, - structuring same such that the remaining portion of the dopant source layer covers the sidewalls and an adjacent region of the first trench, and - driving the dopant out of the source layer into said sidewalls, and removing the source layer, and - step D) is repeated to introduce a dopant of opposite conductivity type into the sidewalls of another one of the first trenches. - introducing the dopant into the sidewalls of the first trench comprises - depositing a dopant source layer to the entire surface of the semiconductor body and the sidewalls of the trenches, - structuring same such that the remaining portion of the dopant source layer covers the sidewalls and an adjacent region of the first trench, and - driving the dopant out of the source layer into said sidewalls, and removing the source layer, and - depositing a dopant source layer to the entire surface of the semiconductor body and the sidewalls of the trenches, - structuring same such that the remaining portion of the dopant source layer covers the sidewalls and an adjacent region of the first trench, and - driving the dopant out of the source layer into said sidewalls, and removing the source layer, and - step D) is repeated to introduce a dopant of opposite conductivity type into the sidewalls of another one of the first trenches. <EOS>