A pixel, comprising: a light emitting diode (LDa to LDf) including an anode coupled to a first node (N1a to N1e), and a cathode coupled to a second power line (ELVSS); a first transistor (T1a to T1e) including a gate electrode coupled to a second node (N2a to N2e), a first electrode coupled to a third node (N3a to N3e), and a second electrode coupled to a fourth node (N4a to N4e); a first capacitor (C1a to C1e) including a first electrode directly coupled to the anode of the light emitting diode, and a second electrode directly coupled to the gate electrode of the first transistor; a second transistor (T2a to T2e) including a gate electrode coupled to a first scan line (GWi), a first electrode coupled to a data line (Dj), and a second electrode coupled to the third node (N3a to N3e); a third transistor (T3a to T3e) including a gate electrode coupled to a second scan line (GBi), a first electrode coupled to an initialization line (INTL), and a second electrode coupled to the first node (N1a to N1e); a fourth transistor (T4a to T4e) including a gate electrode coupled to an emission line (Ei), a first electrode coupled to the fourth node (N4a to N4e), and a second electrode coupled to the first node (N1a to N1e); a fifth transistor (T5a to T5e) including a gate electrode coupled to the emission line (Ei), a first electrode coupled to a first power line (ELVDDL), and a second electrode coupled to the third node (N3a to N3e); a sixth transistor (T6a to T6e) including a gate electrode coupled to a third scan line (Gli), a first electrode coupled to the fourth node (N4a to N4e), and a second electrode coupled to the initialization line (INTL); and a seventh transistor (T7a to T7e) including a gate electrode coupled to the first scan line (GWi), a first electrode coupled to the second node (N2a to N2e), and a second electrode coupled to the fourth node (N4a to N4e). a light emitting diode (LDa to LDf) including an anode coupled to a first node (N1a to N1e), and a cathode coupled to a second power line (ELVSS); a first transistor (T1a to T1e) including a gate electrode coupled to a second node (N2a to N2e), a first electrode coupled to a third node (N3a to N3e), and a second electrode coupled to a fourth node (N4a to N4e); a first capacitor (C1a to C1e) including a first electrode directly coupled to the anode of the light emitting diode, and a second electrode directly coupled to the gate electrode of the first transistor; a second transistor (T2a to T2e) including a gate electrode coupled to a first scan line (GWi), a first electrode coupled to a data line (Dj), and a second electrode coupled to the third node (N3a to N3e); a third transistor (T3a to T3e) including a gate electrode coupled to a second scan line (GBi), a first electrode coupled to an initialization line (INTL), and a second electrode coupled to the first node (N1a to N1e); a fourth transistor (T4a to T4e) including a gate electrode coupled to an emission line (Ei), a first electrode coupled to the fourth node (N4a to N4e), and a second electrode coupled to the first node (N1a to N1e); a fifth transistor (T5a to T5e) including a gate electrode coupled to the emission line (Ei), a first electrode coupled to a first power line (ELVDDL), and a second electrode coupled to the third node (N3a to N3e); a sixth transistor (T6a to T6e) including a gate electrode coupled to a third scan line (Gli), a first electrode coupled to the fourth node (N4a to N4e), and a second electrode coupled to the initialization line (INTL); and a seventh transistor (T7a to T7e) including a gate electrode coupled to the first scan line (GWi), a first electrode coupled to the second node (N2a to N2e), and a second electrode coupled to the fourth node (N4a to N4e). <EOS>