A stream-based NTT, Number Theoretic Transform, processor comprising a plurality K of processing stages (210 k ) with k comprised between 0 and K-1, organised in pipeline , each stage comprising a permutation module followed by a radix module, each sequence of data to be transformed being provided to the processor under the form of N = N / W successive data blocks of size W , the result of the NTT transform of this data sequence also being provided in the form of a sequence of N blocks, each block being of size W , characterised in that it comprises: - a plurality, G + 1, of memory banks (220 g ), with g comprised between 0 and G , where G is the maximum number of data sequences to be transformed simultaneously present in the pipeline, each memory bank (220 g ) being associated with an NTT transform of size N over a given body, Z p l , and comprising K memories MEM k g with k comprised between 0 and K-1, respectively associated with the K processing stages (210 k ) with k comprised between 0 and K-1 each memory being intended to store a set of rotation factors to parameterise a processing stage; - a write management module for receiving, in the form of a sequence of successive blocks, each block being of size W , an assembly ( ψ l ) of rotation factors relating to an NTT transform on said body Z p l , said assembly consisting of K sets of rotation factors, denoted Ψ k l with k comprised between 0 and K-1, and for writing these sets of rotation factors into the respective memories of a memory bank, the writing being performed cyclically in the memory banks, each new set of rotation factors being written to a new memory bank; - a read management module for reading the sets of rotation factors within the memories MEM k g of a memory bank (220 g ) of the processor and for configuring the processing stages (210 k ) as the data blocks progress through processing stages; - a control module to control the write management module , the read management module as well as the progression of the data blocks through the processing stages. - a plurality, G + 1, of memory banks (220 g ), with g comprised between 0 and G , where G is the maximum number of data sequences to be transformed simultaneously present in the pipeline, each memory bank (220 g ) being associated with an NTT transform of size N over a given body, Z p l , and comprising K memories MEM k g with k comprised between 0 and K-1, respectively associated with the K processing stages (210 k ) with k comprised between 0 and K-1 each memory being intended to store a set of rotation factors to parameterise a processing stage; - a write management module for receiving, in the form of a sequence of successive blocks, each block being of size W , an assembly ( ψ l ) of rotation factors relating to an NTT transform on said body Z p l , said assembly consisting of K sets of rotation factors, denoted Ψ k l with k comprised between 0 and K-1, and for writing these sets of rotation factors into the respective memories of a memory bank, the writing being performed cyclically in the memory banks, each new set of rotation factors being written to a new memory bank; - a read management module for reading the sets of rotation factors within the memories MEM k g of a memory bank (220 g ) of the processor and for configuring the processing stages (210 k ) as the data blocks progress through processing stages; - a control module to control the write management module , the read management module as well as the progression of the data blocks through the processing stages. <EOS>