A built-in gate driver for a display panel comprising: a shift register (SR) including a plurality of stages (ST1, ..., STn) for individually driving gate lines (G1, ..., Gn) of a display region of the display panel ; a first clock group (CG1) including clock lines (CLa) arranged at a first side of the shift register (SR), the first side being an outer side of the shift register (SR); and a second clock group (CG2) including clock lines (CLb) arranged at a second side of the shift register (SR), the second side being an inner side between the shift register (SR) and the display region, wherein each of the clock lines (CLa, CLb) includes a main line (MLa, MLb) and a branch line (BLa, BLb) branched from the main line (MLa, MLb) and connected to a corresponding stage (ST1, ..., STn); wherein each of the stages (ST1, ..., STn) includes a first output unit and a second output unit for generating outputs (OUTnA, OUTnB) using different clocks (A, B), wherein a first clock (A) is supplied to the first output unit through the first clock group (CG1) to generate a first output (OUTnA), wherein a second clock (B) is supplied to the second output unit through the second clock group (CG2) to generate a second output (OUTnB) wherein the first clock (A) generated from the first clock group (CG1) is used as a scan output of a first gate line (Ga) connected to a first switching transistor (ST1) for switching a data signal (D) in one subpixel and the second clock (B) generated from the second clock group (CG2) is used as a scan output of a second gate line (Gb) connected to a second switching transistor (ST2) for switching another signal in the subpixel or is used as a carry output to be supplied to another stage as a carry signal for controlling the other stage. a shift register (SR) including a plurality of stages (ST1, ..., STn) for individually driving gate lines (G1, ..., Gn) of a display region of the display panel ; a first clock group (CG1) including clock lines (CLa) arranged at a first side of the shift register (SR), the first side being an outer side of the shift register (SR); and a second clock group (CG2) including clock lines (CLb) arranged at a second side of the shift register (SR), the second side being an inner side between the shift register (SR) and the display region, wherein each of the clock lines (CLa, CLb) includes a main line (MLa, MLb) and a branch line (BLa, BLb) branched from the main line (MLa, MLb) and connected to a corresponding stage (ST1, ..., STn); wherein each of the stages (ST1, ..., STn) includes a first output unit and a second output unit for generating outputs (OUTnA, OUTnB) using different clocks (A, B), wherein a first clock (A) is supplied to the first output unit through the first clock group (CG1) to generate a first output (OUTnA), wherein a second clock (B) is supplied to the second output unit through the second clock group (CG2) to generate a second output (OUTnB) wherein the first clock (A) generated from the first clock group (CG1) is used as a scan output of a first gate line (Ga) connected to a first switching transistor (ST1) for switching a data signal (D) in one subpixel and the second clock (B) generated from the second clock group (CG2) is used as a scan output of a second gate line (Gb) connected to a second switching transistor (ST2) for switching another signal in the subpixel or is used as a carry output to be supplied to another stage as a carry signal for controlling the other stage. <EOS>