A shift register comprising: a pulling-up unit , a clock control unit , a resetting unit , an inverting unit and a pulling-down unit ; the pulling-up unit is connected with a shift trigging signal terminal, a high level signal terminal and the resetting unit , respectively, wherein a node at which the pulling-up unit is connected with the resetting unit is a pulling-up node, the pulling-up unit is configured to pull up a voltage at the pulling-up node according to a shift trigging signal from the shift trigging signal terminal; the clock control unit is connected with the pulling-up node, a clock signal terminal and the pulling-down unit , respectively, wherein a node at which the clock control unit is connected with the pulling-down unit is an output terminal, the clock control unit is configured to control whether to transmit a clock signal from the clock signal terminal to the output terminal according to the voltage at the pulling-up node; the resetting unit is connected with a reset signal terminal, a low level signal terminal, the pulling-up node and the output terminal, respectively, and is configured to pull down the voltage at the pulling-up node and the voltage at the output terminal according to a reset signal from the reset signal terminal; the inverting unit is connected with the high level signal terminal, the low level signal terminal, the pulling-up node and the pulling-down unit , respectively, wherein a node at which the inverting unit is connected with the pulling-down unit is a pulling-down node, the inverting unit is configured to ensure level of the voltage at the pulling-up node and level of the voltage at the pulling-down node to be inverted to each other; the pulling-down unit is connected with the pulling-up node, the pulling-down node, the low level signal terminal, and the output terminal, respectively, and is configured to pull down the voltages at the pulling-up node and the output terminal according to the voltage at the pulling-down node; wherein the clock control unit comprises a first thin film transistor (T3) having a gate connected with the pulling-up node, a source connected with the clock signal terminal, and a drain connected with the output terminal; the pulling-down unit comprises a first pulling-down thin film transistor (T9) and a second pulling-down thin film transistor (T6); wherein a gate of said second pulling-down thin film transistor (T6) is connected with the pulling-down node, a drain thereof is connected with the output terminal, and a source thereof is connected with the low level signal terminal; and a gate of said first pulling-down thin film transistor (T9) is connected with the pulling-down node, a drain thereof is connected with the pulling-up node, and a source thereof is connected with the low level signal terminal; characterized in that the pulling-down unit is further connected with the shift trigging signal terminal and is further configured to pull down the voltage at the output terminal according to the shift trigging signal from the shift trigging signal terminal; and characterized in that the pulling-down unit further comprises a third pulling-down thin film transistor (T5) configured to discharge the output terminal of the shift register when the shift triggering signal from the shift trigging signal terminal is active so as to eliminate a noise at the output terminal generated by the clock signal, wherein a gate of said third pulling-down thin film transistor (T5) is connected with the shift trigging signal terminal, a drain thereof is connected with the output terminal, and a source thereof is connected with the low level signal terminal. <EOS>