A counter circuit (CNT_0) that counts a high period or a low period of an input signal (CDS_OUT0) using a clock signal (CLK), the counter circuit (CNT_0) comprising: a first AND gate configured to perform an AND operation on the input signal (CDS_OUT0) and the clock signal (CLK); and a ripple counter triggered by an output of the first AND gate to count a length of the input signal (CDS_OUT0), the ripple counter including a plurality of counting units (142 - 145; CU<0> - CU<n-1>) for counting up or counting down the length of the input signal (CDS_OUT0), each of the plurality of counting units (142 - 145; CU<0> - CU<n-1>) including: a D-latch configured to store an inverted counting bit in response to a first complement control signal (BWI_C); and a D-flip-flop that is set or reset by the inverted counting bit stored in the D-latch in response to a second complement control signal (BWI), characterised in that each of the plurality of counting units (142 - 145; CU<0> - CU<n-1>) further comprises a complement operation controller including: a second AND gate configured to transfer a non-inverted output signal (Q) of the D-latch to a set input terminal (SET) of the D-flip-flop in synchronization with the second complement control signal (BWI); and a third AND gate configured to transfer an inverted output signal (/Q) of the D-latch to a reset input terminal (RESET) of the D-flip-flop in synchronization with the second complement control signal (BWI). a first AND gate configured to perform an AND operation on the input signal (CDS_OUT0) and the clock signal (CLK); and a ripple counter triggered by an output of the first AND gate to count a length of the input signal (CDS_OUT0), the ripple counter including a plurality of counting units (142 - 145; CU<0> - CU<n-1>) for counting up or counting down the length of the input signal (CDS_OUT0), each of the plurality of counting units (142 - 145; CU<0> - CU<n-1>) including: a D-latch configured to store an inverted counting bit in response to a first complement control signal (BWI_C); and a D-flip-flop that is set or reset by the inverted counting bit stored in the D-latch in response to a second complement control signal (BWI), characterised in that each of the plurality of counting units (142 - 145; CU<0> - CU<n-1>) further comprises a complement operation controller including: a second AND gate configured to transfer a non-inverted output signal (Q) of the D-latch to a set input terminal (SET) of the D-flip-flop in synchronization with the second complement control signal (BWI); and a third AND gate configured to transfer an inverted output signal (/Q) of the D-latch to a reset input terminal (RESET) of the D-flip-flop in synchronization with the second complement control signal (BWI). a second AND gate configured to transfer a non-inverted output signal (Q) of the D-latch to a set input terminal (SET) of the D-flip-flop in synchronization with the second complement control signal (BWI); and a third AND gate configured to transfer an inverted output signal (/Q) of the D-latch to a reset input terminal (RESET) of the D-flip-flop in synchronization with the second complement control signal (BWI). <EOS>