A pixel structure comprising a first pixel and a second pixel in a same column of pixels, wherein the second pixel is directly adjacent to the first pixel and both are connected to a same data line (data1, data2), and wherein the first pixel is connected a first scan line (scan1) and the second pixel is connected to a second scan line (scan2), wherein the first pixel and the second pixel each comprise a pixel driving circuit, wherein each pixel driving circuit comprises a switching transistor (T2a, T2b, T4a, T4b) comprising a dual gate field effect transistor, and the dual gate field effect transistor comprises a first gate electrode (g1), a second gate electrode (g2), a source electrode (s) and a drain electrode (d), and the source electrode (s) of dual gate field effect transistor in the first pixel and the second pixel is connected to the same data line (data1, data2), wherein the first gate electrode (g1) and the second gate electrode (g2) of the dual gate field effect transistor in the first pixel are connected to the first scan line (scan1), the first gate electrode (g1) and the second gate electrode (g2) of the dual gate field effect transistor in the second pixel are connected to the second scan line (scan2), characterized in that the dual gate field effect transistor of the switching transistor (T2a, T2b) of the first pixel comprises a first semiconductor channel layer electrically connecting the source electrode (s) and the drain electrode (d), the dual gate field effect transistor of the switching transistor (T4a, T4b) of the second pixel comprises a second semiconductor channel layer electrically connecting the source electrode (s) and the drain electrode (d), and a part of the first semiconductor channel layer between the first gate electrode (g1) and the second gate electrode (g2) of the first pixel and a part of the second semiconductor channel layer between the first gate electrode (g1) and the second gate electrode (g2) of the second pixel share a common portion (T24). wherein the first pixel and the second pixel each comprise a pixel driving circuit, wherein each pixel driving circuit comprises a switching transistor (T2a, T2b, T4a, T4b) comprising a dual gate field effect transistor, and the dual gate field effect transistor comprises a first gate electrode (g1), a second gate electrode (g2), a source electrode (s) and a drain electrode (d), and the source electrode (s) of dual gate field effect transistor in the first pixel and the second pixel is connected to the same data line (data1, data2), wherein the first gate electrode (g1) and the second gate electrode (g2) of the dual gate field effect transistor in the first pixel are connected to the first scan line (scan1), the first gate electrode (g1) and the second gate electrode (g2) of the dual gate field effect transistor in the second pixel are connected to the second scan line (scan2), characterized in that the dual gate field effect transistor of the switching transistor (T2a, T2b) of the first pixel comprises a first semiconductor channel layer electrically connecting the source electrode (s) and the drain electrode (d), the dual gate field effect transistor of the switching transistor (T4a, T4b) of the second pixel comprises a second semiconductor channel layer electrically connecting the source electrode (s) and the drain electrode (d), and a part of the first semiconductor channel layer between the first gate electrode (g1) and the second gate electrode (g2) of the first pixel and a part of the second semiconductor channel layer between the first gate electrode (g1) and the second gate electrode (g2) of the second pixel share a common portion (T24). <EOS>