An operating method of a memory controller , comprising: receiving first decision data , hereinafter referred to as M-bit first decision data , from a memory device comprising memory cells, where M is a natural number, the M-bit first decision data being generated by performing a hard decision read operation and M-level soft decision read operations whereby the soft decision read operations add reliability to data read by the hard decision read operation; wherein a number of possible M-bit first decision data values for each memory cell is 2 M ; the method being characterised by : converting the M-bit first decision data into second decision data (3SD ), hereinafter referred to as N-bit second decision data (3SD ), where N is a natural number less than M; the N-bit second decision data (3SD ) being generated by performing a hard decision read operation and N-level soft decision read operations; wherein a number of possible N-bit second decision data values for each memory cell is 2 N ; the converting of M-bit first decision data into N-bit second decision data comprising mapping the 2 M possible M-bit first decision data values to the 2 N possible N-bit second decision data values; and attempting a first decoding (S153) using the N-bit second decision data (3SD ). receiving first decision data , hereinafter referred to as M-bit first decision data , from a memory device comprising memory cells, where M is a natural number, the M-bit first decision data being generated by performing a hard decision read operation and M-level soft decision read operations whereby the soft decision read operations add reliability to data read by the hard decision read operation; wherein a number of possible M-bit first decision data values for each memory cell is 2 M ; the method being characterised by : converting the M-bit first decision data into second decision data (3SD ), hereinafter referred to as N-bit second decision data (3SD ), where N is a natural number less than M; the N-bit second decision data (3SD ) being generated by performing a hard decision read operation and N-level soft decision read operations; wherein a number of possible N-bit second decision data values for each memory cell is 2 N ; the converting of M-bit first decision data into N-bit second decision data comprising mapping the 2 M possible M-bit first decision data values to the 2 N possible N-bit second decision data values; and attempting a first decoding (S153) using the N-bit second decision data (3SD ). converting the M-bit first decision data into second decision data (3SD ), hereinafter referred to as N-bit second decision data (3SD ), where N is a natural number less than M; the N-bit second decision data (3SD ) being generated by performing a hard decision read operation and N-level soft decision read operations; wherein a number of possible N-bit second decision data values for each memory cell is 2 N ; the converting of M-bit first decision data into N-bit second decision data comprising mapping the 2 M possible M-bit first decision data values to the 2 N possible N-bit second decision data values; and attempting a first decoding (S153) using the N-bit second decision data (3SD ). <EOS>