Negative charge pump (NCP), comprising - a supply terminal (VDD), a GND terminal (GND), an output terminal (OUT, Vneg), a first clock terminal (CT1) and an internal node (vpos); - a first inverter (INV1), a second inverter (INV2), and a first charge storage (CS1, C1), - a regulation circuit (RC) connected between the supply terminal (VDD), the first inverter (INV1) via the internal node (vpos), the GND terminal (GND), and the output terminal (OUT, vneg); where - the first inverter (INV1) is connected between the supply terminal (VDD), the first clock terminal (CT1), the first charge storage (CS1, C1), and said internal node (vpos); - the second inverter (INV2) is connected between the first charge storage (CS1, C), the GND terminal (GND), and the output terminal (OUT, vneg); and coupled to the first clock terminal (CT1) ; - the first charge storage (CS1, C1) is connected between the first inverter (INV1) and the second inverter (INV2); - the negative charge pump (NCP) is configured such that during operation and with respect to the electric potential of the GND terminal (GND) the electric potential of the supply terminal (VDD) is positive while the electric potential of the output terminal (OUT, vneg) is negative, - the regulation circuit (RC) has a voltage divider (VD), an error amplifier (EA), and a transistor (TR); - the voltage divider (VD) is connected between the supply terminal (VDD) and the output terminal (OUT, vneg); characterized in that - the error amplifier (EA) is connected between the supply terminal (VDD), the voltage divider (VD), the GND terminal (GND), and the transistor (TR); - the transistor (TR) is connected between the first inverter (INV1) via said internal node (vpos), the error amplifier (EA), and the GND terminal (GND) such that the voltage settings in the negative charge pump can be readjusted utilizing transistor (TR) and the output of the charge pump (OUT, vneg) can be regulated by means of regulating the voltage at the internal node (vpos). - a supply terminal (VDD), a GND terminal (GND), an output terminal (OUT, Vneg), a first clock terminal (CT1) and an internal node (vpos); - a first inverter (INV1), a second inverter (INV2), and a first charge storage (CS1, C1), - a regulation circuit (RC) connected between the supply terminal (VDD), the first inverter (INV1) via the internal node (vpos), the GND terminal (GND), and the output terminal (OUT, vneg); where - the first inverter (INV1) is connected between the supply terminal (VDD), the first clock terminal (CT1), the first charge storage (CS1, C1), and said internal node (vpos); - the second inverter (INV2) is connected between the first charge storage (CS1, C), the GND terminal (GND), and the output terminal (OUT, vneg); and coupled to the first clock terminal (CT1) ; - the first charge storage (CS1, C1) is connected between the first inverter (INV1) and the second inverter (INV2); - the negative charge pump (NCP) is configured such that during operation and with respect to the electric potential of the GND terminal (GND) the electric potential of the supply terminal (VDD) is positive while the electric potential of the output terminal (OUT, vneg) is negative, - the regulation circuit (RC) has a voltage divider (VD), an error amplifier (EA), and a transistor (TR); - the voltage divider (VD) is connected between the supply terminal (VDD) and the output terminal (OUT, vneg); characterized in that - the error amplifier (EA) is connected between the supply terminal (VDD), the voltage divider (VD), the GND terminal (GND), and the transistor (TR); - the transistor (TR) is connected between the first inverter (INV1) via said internal node (vpos), the error amplifier (EA), and the GND terminal (GND) such that the voltage settings in the negative charge pump can be readjusted utilizing transistor (TR) and the output of the charge pump (OUT, vneg) can be regulated by means of regulating the voltage at the internal node (vpos). <EOS>