A microcontroller comprising a housing having a predetermined number of external pins (RA0; RA1, RA2, RA3, VSS, VDD), comprising: a central processing core ;a plurality of peripherals (104; 110) operably coupled to the central processing core, the plurality of peripherals including at least one digital peripheral and at least one configurable logic cell peripheral (104; 1002; 1102), the at least one configurable logic cell peripheral (104; 1002; 1102) having n input/output connections including a plurality of inputs and an output, a plurality of selectors , each selector being associated with one of the inputs of the at least one configurable logic cell peripheral (104; 1002; 1102), wherein the at least one configurable logic cell peripheral (104; 1002; 1102) is adapted to receive input signals through said selectors , wherein each input signal for the at least one configurable logic cell peripheral can be selected at least from output signals of the digital peripheral (104; 110) and from a first external pin and wherein an output signal of the at least one configurable logic cell peripheral (104; 1002; 1102) is provided to a second external pin, wherein n is greater than a number of input-output connections of the microcontroller that are coupled with said external pins (RA0; RA1, RA2, RA3),wherein the at least one configurable logic cell peripheral (104; 1002; 1102) is configured through a plurality of special function registers of the microcontroller which are programmable by the central processing core , wherein the plurality of special function registers comprise first control bits (LCMODE) which define a configurable logic function and a second control bit (LCEN) which enables the logic output of the configurable logic cell peripheral (104; 1002; 1102). a central processing core ;a plurality of peripherals (104; 110) operably coupled to the central processing core, the plurality of peripherals including at least one digital peripheral and at least one configurable logic cell peripheral (104; 1002; 1102), the at least one configurable logic cell peripheral (104; 1002; 1102) having n input/output connections including a plurality of inputs and an output, a plurality of selectors , each selector being associated with one of the inputs of the at least one configurable logic cell peripheral (104; 1002; 1102), wherein the at least one configurable logic cell peripheral (104; 1002; 1102) is adapted to receive input signals through said selectors , wherein each input signal for the at least one configurable logic cell peripheral can be selected at least from output signals of the digital peripheral (104; 110) and from a first external pin and wherein an output signal of the at least one configurable logic cell peripheral (104; 1002; 1102) is provided to a second external pin, wherein n is greater than a number of input-output connections of the microcontroller that are coupled with said external pins (RA0; RA1, RA2, RA3),wherein the at least one configurable logic cell peripheral (104; 1002; 1102) is configured through a plurality of special function registers of the microcontroller which are programmable by the central processing core , wherein the plurality of special function registers comprise first control bits (LCMODE) which define a configurable logic function and a second control bit (LCEN) which enables the logic output of the configurable logic cell peripheral (104; 1002; 1102). <EOS>