A semiconductor power device comprising: - a first substrate comprising a first patterned electrically conductive layer , the first substrate having a first surface on which the first patterned electrically conductive layer is provided, - a second substrate comprising a second patterned electrically conductive layer and a second surface facing the first surface , the second patterned electrically conductive layer being provided on the second surface , - a switching semiconductor element arranged between the first patterned electrically conductive layer and the second patterned electrically conductive layer , the switching semiconductor element being provided on the first patterned electrically conductive layer, - a stack of an electrically conductive track and a layer of a dielectric material, the layer of the dielectric material being at least partly provided on the first patterned electrically conductive layer , or on the second patterned electrically conductive layer isolating the electrically conductive track from said patterned electrically conductive layer on which the stack is provided, the electrically conductive track being electrically coupled to a gate or a base of the switching semiconductor element (115, 415, 465, 465', 465") for controlling the switching semiconductor element (115, 415, 465, 465', 465"),and - an interconnect structure for providing at least - a first electrical connection between a surface of the switching semiconductor element , and the second patterned electrically conductive layer , and - a second electrical connection between the surface of the switching semiconductor element or the first patterned electrically conductive layer, and the electrically conductive track at the other side. - a first substrate comprising a first patterned electrically conductive layer , the first substrate having a first surface on which the first patterned electrically conductive layer is provided, - a second substrate comprising a second patterned electrically conductive layer and a second surface facing the first surface , the second patterned electrically conductive layer being provided on the second surface , - a switching semiconductor element arranged between the first patterned electrically conductive layer and the second patterned electrically conductive layer , the switching semiconductor element being provided on the first patterned electrically conductive layer, - a stack of an electrically conductive track and a layer of a dielectric material, the layer of the dielectric material being at least partly provided on the first patterned electrically conductive layer , or on the second patterned electrically conductive layer isolating the electrically conductive track from said patterned electrically conductive layer on which the stack is provided, the electrically conductive track being electrically coupled to a gate or a base of the switching semiconductor element (115, 415, 465, 465', 465") for controlling the switching semiconductor element (115, 415, 465, 465', 465"),and - an interconnect structure for providing at least - a first electrical connection between a surface of the switching semiconductor element , and the second patterned electrically conductive layer , and - a second electrical connection between the surface of the switching semiconductor element or the first patterned electrically conductive layer, and the electrically conductive track at the other side. <EOS>