An output driver comprising: a pull-up driver including first (PM1), second (PM2) and third (PM3) PMOSFETs connected by a cascode structure between a voltage supply node (OVDD) and an output node (NO1), wherein the voltage difference between the voltage supply node and the output node at a grounded level is greater than an operation voltage of each of the first, second and third PMOSFETs; and a pull-down driver including first (NM1), second (NM2) and third (NM3) NMOSFETs connected by a cascode structure between a ground node and the output node, and wherein, during a pull-up operation: a first high voltage (PG1), and a first power supply voltage (PG2) are applied to the gates of the first and second PMOSFETs, respectively; a ground voltage (NG1), a second power supply voltage (VDD, NG2) and a second high voltage (NG3) are applied to the gates of the first, second and third NMOSFETs respectively, wherein the second high voltage (NG3) is equal to a voltage at the voltage supply node (OVDD), the first power supply voltage (PG2) is an absolute difference voltage between the second power supply voltage (VDD, NG2) and the voltage at the voltage supply node (OVDD), and the second power supply voltage (VDD, NG2) is higher than the first power supply voltage (PG2). a pull-up driver including first (PM1), second (PM2) and third (PM3) PMOSFETs connected by a cascode structure between a voltage supply node (OVDD) and an output node (NO1), wherein the voltage difference between the voltage supply node and the output node at a grounded level is greater than an operation voltage of each of the first, second and third PMOSFETs; and a pull-down driver including first (NM1), second (NM2) and third (NM3) NMOSFETs connected by a cascode structure between a ground node and the output node, and wherein, during a pull-up operation: a first high voltage (PG1), and a first power supply voltage (PG2) are applied to the gates of the first and second PMOSFETs, respectively; a ground voltage (NG1), a second power supply voltage (VDD, NG2) and a second high voltage (NG3) are applied to the gates of the first, second and third NMOSFETs respectively, wherein the second high voltage (NG3) is equal to a voltage at the voltage supply node (OVDD), the first power supply voltage (PG2) is an absolute difference voltage between the second power supply voltage (VDD, NG2) and the voltage at the voltage supply node (OVDD), and the second power supply voltage (VDD, NG2) is higher than the first power supply voltage (PG2). a first high voltage (PG1), and a first power supply voltage (PG2) are applied to the gates of the first and second PMOSFETs, respectively; a ground voltage (NG1), a second power supply voltage (VDD, NG2) and a second high voltage (NG3) are applied to the gates of the first, second and third NMOSFETs respectively, wherein the second high voltage (NG3) is equal to a voltage at the voltage supply node (OVDD), the first power supply voltage (PG2) is an absolute difference voltage between the second power supply voltage (VDD, NG2) and the voltage at the voltage supply node (OVDD), and the second power supply voltage (VDD, NG2) is higher than the first power supply voltage (PG2). <EOS>