A static random access memory, SRAM , comprising: a plurality of word lines (WL); a dummy bit line ; a dummy write driver configured to discharge the dummy bit line responsive to a memory clock signal to model a bit line discharge during a write operation; and a row decoder configured to decode an address signal to assert an addressed one of the word lines, wherein the row decoder includes a word line delay circuit configured to delay the decoding of the address signal in the write operation until the dummy bit line is discharged and to not delay the decoding of the address signal in a read operation, wherein the row decoder is a two-level row decoder comprising: a predecoder configured to predecode the address signal into a plurality of asserted first predecoded address signals (125, ra, rb) and into an asserted second predecoded address signal (125, rc) responsive to the memory clock signal; an inverter for inverting the asserted second predecoded address signal into a second de-asserted predecoded address signal , wherein the word line delay logic circuit is configured to invert the de-asserted second predecoded address signal into a re-asserted second predecoded address signal responsive to the discharge of the dummy bit line during the write operation; and a final row decoder configured to assert the addressed one of the word lines responsive to the assertion of the plurality of first predecoded address signals and the re-asserted second predecoded address signal. a plurality of word lines (WL); a dummy bit line ; a dummy write driver configured to discharge the dummy bit line responsive to a memory clock signal to model a bit line discharge during a write operation; and a row decoder configured to decode an address signal to assert an addressed one of the word lines, wherein the row decoder includes a word line delay circuit configured to delay the decoding of the address signal in the write operation until the dummy bit line is discharged and to not delay the decoding of the address signal in a read operation, wherein the row decoder is a two-level row decoder comprising: a predecoder configured to predecode the address signal into a plurality of asserted first predecoded address signals (125, ra, rb) and into an asserted second predecoded address signal (125, rc) responsive to the memory clock signal; an inverter for inverting the asserted second predecoded address signal into a second de-asserted predecoded address signal , wherein the word line delay logic circuit is configured to invert the de-asserted second predecoded address signal into a re-asserted second predecoded address signal responsive to the discharge of the dummy bit line during the write operation; and a final row decoder configured to assert the addressed one of the word lines responsive to the assertion of the plurality of first predecoded address signals and the re-asserted second predecoded address signal. a predecoder configured to predecode the address signal into a plurality of asserted first predecoded address signals (125, ra, rb) and into an asserted second predecoded address signal (125, rc) responsive to the memory clock signal; an inverter for inverting the asserted second predecoded address signal into a second de-asserted predecoded address signal , wherein the word line delay logic circuit is configured to invert the de-asserted second predecoded address signal into a re-asserted second predecoded address signal responsive to the discharge of the dummy bit line during the write operation; and a final row decoder configured to assert the addressed one of the word lines responsive to the assertion of the plurality of first predecoded address signals and the re-asserted second predecoded address signal. <EOS>