A driving circuit comprising: a first inverter (INV1) that is driven by a first power supply voltage (VDD1) and inverts and outputs a first input signal (D1); a second inverter (INV2) that is driven by a second power supply voltage (VDD2) higher than the first power supply voltage and inverts and outputs the first input signal (D1); a first PMOS transistor (MP3) that controls a current flowing to an external output terminal (OUT1) from a power supply voltage terminal (VDD2) to which the second power supply voltage is supplied on the basis of an output signal of the second inverter(INV2) ; a first NMOS transistor (MN3) that controls a current flowing to a reference voltage terminal (VSS) from the external output terminal (OUT1) on the basis of an output signal of the first inverter(INV1) ; a second PMOS transistor (MP4) that is provided between the power supply voltage terminal (VDD2) to which the second power supply voltage is supplied and the gate of the first PMOS transistor (MP3); and a signal generation circuit having an output terminal coupled to a gate of the second PMOS transistor(MP4), wherein the signal generation circuit is configured to generate and supply a second input signal (P1) to the gate of the second PMOS transistor (MP4), wherein the signal generation circuit is configured to fall the second input signal (P1) in accordance with falling of the first input signal (D1), thereby turning on the second PMOS transistor (MP4), and wherein the signal generation circuit is configured to rise the second input signal (P1) after a predetermined time from the falling of the first input signal (D1), thereby turning off the second PMOS transistor (MP4). a first inverter (INV1) that is driven by a first power supply voltage (VDD1) and inverts and outputs a first input signal (D1); a second inverter (INV2) that is driven by a second power supply voltage (VDD2) higher than the first power supply voltage and inverts and outputs the first input signal (D1); a first PMOS transistor (MP3) that controls a current flowing to an external output terminal (OUT1) from a power supply voltage terminal (VDD2) to which the second power supply voltage is supplied on the basis of an output signal of the second inverter(INV2) ; a first NMOS transistor (MN3) that controls a current flowing to a reference voltage terminal (VSS) from the external output terminal (OUT1) on the basis of an output signal of the first inverter(INV1) ; a second PMOS transistor (MP4) that is provided between the power supply voltage terminal (VDD2) to which the second power supply voltage is supplied and the gate of the first PMOS transistor (MP3); and a signal generation circuit having an output terminal coupled to a gate of the second PMOS transistor(MP4), wherein the signal generation circuit is configured to generate and supply a second input signal (P1) to the gate of the second PMOS transistor (MP4), wherein the signal generation circuit is configured to fall the second input signal (P1) in accordance with falling of the first input signal (D1), thereby turning on the second PMOS transistor (MP4), and wherein the signal generation circuit is configured to rise the second input signal (P1) after a predetermined time from the falling of the first input signal (D1), thereby turning off the second PMOS transistor (MP4). <EOS>