A power amplifier circuit for broadband data communication over a path in a communication network while maintaining low distortion gain performance, the power amplifier circuit comprising: a differential pair of first and second transistors (Q1a, Q1b), respectively coupled to a common emitter bias node via respective first and second resistors; a dynamic variable bias current circuit , coupled to the common emitter bias node of the differential pair to provide a dynamic variable bias current thereto as a function of an input signal amplitude of an input signal communicated to differential pair of the first and second transistors (Q1a, Q1b); first and second cascode transistors (Q7a, Q7b) coupled to receive respective output currents of the differential pair of the first and second transistors (Q1a, Q1b); a balun (T3) comprising a first winding and a second winding, the first and second windings each comprising a first and a second terminal respectively, wherein the first terminal of the first winding and the second terminal of the second winding are coupled such that the direction of a bias current within the balun results in magnetic flux cancellation and the second terminal of the first winding and the first terminal of the second winding are coupled to the respective collector terminals of the differential pair of the first and second transistors (Q1a, Q1b) via the first and second cascode transistors (Q7a, Q7b) respectively to short out even order harmonics; an output transformer (T2), coupled to the respective collector terminals of the differential pair of the first and second transistors (Q1a, Q1b) to convert output currents of the differential pair of the first and second transistors (Q1a, Q1b) into an output voltage; and a passive LC notch filter comprising a series connection of an inductor (L1) and a capacitor (C1) connected between respective collector terminals of the first and second cascode transistors (Q1a, Q1b) to short out second order harmonics. a differential pair of first and second transistors (Q1a, Q1b), respectively coupled to a common emitter bias node via respective first and second resistors; a dynamic variable bias current circuit , coupled to the common emitter bias node of the differential pair to provide a dynamic variable bias current thereto as a function of an input signal amplitude of an input signal communicated to differential pair of the first and second transistors (Q1a, Q1b); first and second cascode transistors (Q7a, Q7b) coupled to receive respective output currents of the differential pair of the first and second transistors (Q1a, Q1b); a balun (T3) comprising a first winding and a second winding, the first and second windings each comprising a first and a second terminal respectively, wherein the first terminal of the first winding and the second terminal of the second winding are coupled such that the direction of a bias current within the balun results in magnetic flux cancellation and the second terminal of the first winding and the first terminal of the second winding are coupled to the respective collector terminals of the differential pair of the first and second transistors (Q1a, Q1b) via the first and second cascode transistors (Q7a, Q7b) respectively to short out even order harmonics; an output transformer (T2), coupled to the respective collector terminals of the differential pair of the first and second transistors (Q1a, Q1b) to convert output currents of the differential pair of the first and second transistors (Q1a, Q1b) into an output voltage; and a passive LC notch filter comprising a series connection of an inductor (L1) and a capacitor (C1) connected between respective collector terminals of the first and second cascode transistors (Q1a, Q1b) to short out second order harmonics. <EOS>