A display panel (DP), including a display region (DA) provided with pixels (PX) and a non-display region (NDA) located outside the display region (DA), wherein the display panel (DP) comprises: emission elements (OLED) corresponding to the pixels (PX), respectively, each of the emission elements (OLED) comprising a first electrode (AE), an emission layer (EML) disposed on the first electrode (AE), and a second electrode (CE) disposed on the emission layer (EML); a pixel definition layer (PDL) including a first opening (OP1) that exposes the first electrode (AE) of each of the emission elements (OLED); a first encapsulation layer (TFE1) disposed on the pixel definition layer (PDL) and overlapping the emission elements (OLED); a partition wall (BW) disposed on the first encapsulation layer (TFE1) and including a second opening (OP2) corresponding to the first opening (OP1) and a dummy opening (OP-D) overlapping the non-display region (NDA); a light control pattern (CCF-R) disposed in the second opening (OP2); a second encapsulation layer (TFE2) disposed on the partition wall (BW) and overlapping the light control pattern (CCF-R); and a color filter (CF-R) disposed on the second encapsulation layer (TFE2) and overlapping the light control pattern (CCF-R), wherein the second encapsulation layer (TFE2) is located between the light control pattern (CCF-R) and the color filter (CF-R), wherein the second encapsulation layer (TFE2) comprises: a first encapsulation inorganic layer (IOL10) disposed on the partition wall (BW); an encapsulation organic layer (OL-1) disposed on the first encapsulation inorganic layer (IOL10) and including an edge overlapping the dummy opening (OP-D); and a second encapsulation inorganic layer (IOL20) disposed on the encapsulation organic layer (OL-1). emission elements (OLED) corresponding to the pixels (PX), respectively, each of the emission elements (OLED) comprising a first electrode (AE), an emission layer (EML) disposed on the first electrode (AE), and a second electrode (CE) disposed on the emission layer (EML); a pixel definition layer (PDL) including a first opening (OP1) that exposes the first electrode (AE) of each of the emission elements (OLED); a first encapsulation layer (TFE1) disposed on the pixel definition layer (PDL) and overlapping the emission elements (OLED); a partition wall (BW) disposed on the first encapsulation layer (TFE1) and including a second opening (OP2) corresponding to the first opening (OP1) and a dummy opening (OP-D) overlapping the non-display region (NDA); a light control pattern (CCF-R) disposed in the second opening (OP2); a second encapsulation layer (TFE2) disposed on the partition wall (BW) and overlapping the light control pattern (CCF-R); and a color filter (CF-R) disposed on the second encapsulation layer (TFE2) and overlapping the light control pattern (CCF-R), wherein the second encapsulation layer (TFE2) is located between the light control pattern (CCF-R) and the color filter (CF-R), wherein the second encapsulation layer (TFE2) comprises: a first encapsulation inorganic layer (IOL10) disposed on the partition wall (BW); an encapsulation organic layer (OL-1) disposed on the first encapsulation inorganic layer (IOL10) and including an edge overlapping the dummy opening (OP-D); and a second encapsulation inorganic layer (IOL20) disposed on the encapsulation organic layer (OL-1). a first encapsulation inorganic layer (IOL10) disposed on the partition wall (BW); an encapsulation organic layer (OL-1) disposed on the first encapsulation inorganic layer (IOL10) and including an edge overlapping the dummy opening (OP-D); and a second encapsulation inorganic layer (IOL20) disposed on the encapsulation organic layer (OL-1). <EOS>