A three-dimensional, 3D, memory device , comprising: a substrate ; a memory stack comprising: a first high-κ dielectric layer above the substrate , and a plurality of interleaved conductor layers and dielectric layers above the first high-κ dielectric layer ; and a semiconductor plug disposed above the substrate and in an opening of the first high-κ dielectric layer , further comprising a first channel structure extending vertically above the semiconductor plug and through the memory stack , the first channel structure comprising: a first memory film above the first high-x dielectric layer and along a sidewall of the first channel structure , said first memory film being in contact with the semiconductor plug , further comprising: a second channel structure extending vertically above the first channel structure and through the memory stack , a second high-κ dielectric layer disposed between the first channel structure and the second channel structure ; and an inter-deck plug disposed in an opening of the second high-κ dielectric layer , said 3D memory device further comprising a second memory film above the second high-κ dielectric layer and along a sidewall of the second channel structure , said second memory film being in contact with the inter-deck plug . a substrate ; a memory stack comprising: a first high-κ dielectric layer above the substrate , and a plurality of interleaved conductor layers and dielectric layers above the first high-κ dielectric layer ; and a first high-κ dielectric layer above the substrate , and a plurality of interleaved conductor layers and dielectric layers above the first high-κ dielectric layer ; and a semiconductor plug disposed above the substrate and in an opening of the first high-κ dielectric layer , further comprising a first channel structure extending vertically above the semiconductor plug and through the memory stack , the first channel structure comprising: a first memory film above the first high-x dielectric layer and along a sidewall of the first channel structure , said first memory film being in contact with the semiconductor plug , further comprising: a second channel structure extending vertically above the first channel structure and through the memory stack , a second high-κ dielectric layer disposed between the first channel structure and the second channel structure ; and an inter-deck plug disposed in an opening of the second high-κ dielectric layer , said 3D memory device further comprising a second memory film above the second high-κ dielectric layer and along a sidewall of the second channel structure , said second memory film being in contact with the inter-deck plug . a first memory film above the first high-x dielectric layer and along a sidewall of the first channel structure , said first memory film being in contact with the semiconductor plug , further comprising: a second channel structure extending vertically above the first channel structure and through the memory stack , a second high-κ dielectric layer disposed between the first channel structure and the second channel structure ; and an inter-deck plug disposed in an opening of the second high-κ dielectric layer , said 3D memory device further comprising a second memory film above the second high-κ dielectric layer and along a sidewall of the second channel structure , said second memory film being in contact with the inter-deck plug . a second channel structure extending vertically above the first channel structure and through the memory stack , a second high-κ dielectric layer disposed between the first channel structure and the second channel structure ; and an inter-deck plug disposed in an opening of the second high-κ dielectric layer , said 3D memory device further comprising a second memory film above the second high-κ dielectric layer and along a sidewall of the second channel structure , said second memory film being in contact with the inter-deck plug . <EOS>