An apparatus comprising: an input port ; an output port ; a common port ; an input impedance of the input port being lower than an input impedance of the output port and an input impedance of the common port ; a first impedance matching network coupled between said input port and said common port ; a second impedance matching network coupled between said common port and said output port ; a first switch circuit coupled between said input port and a circuit ground potential, wherein said first switch circuit comprises: a transistor (Q1) configured to operate as a switch; a capacitor (C1); and a resistor (R1), wherein (i) a first terminal of said resistor (R1) is coupled to a base terminal of said transistor (Q1), (ii) said capacitor (C1) is coupled between an emitter terminal and said base terminal of said transistor, (iii) said emitter terminal of said transistor (Q1) is coupled to said input port , and (iv) a collector terminal of said transistor is coupled to said circuit ground potential; and a second switch circuit coupled between said output port and said circuit ground potential, wherein (i) said first impedance matching network provides the input impedance of the input port when said first switch circuit is in a non-conducting state and said second switch circuit is in a conducting state, (ii) said second impedance matching network provides the input impedance of the output port when said first switch circuit is in a conducting state and said second switch circuit is in a non-conducting state, and (iii) the input impedance of the input port and the input impedance of the output port are asymmetrical. an input port ; an output port ; a common port ; an input impedance of the input port being lower than an input impedance of the output port and an input impedance of the common port ; a first impedance matching network coupled between said input port and said common port ; a second impedance matching network coupled between said common port and said output port ; a first switch circuit coupled between said input port and a circuit ground potential, wherein said first switch circuit comprises: a transistor (Q1) configured to operate as a switch; a capacitor (C1); and a resistor (R1), wherein (i) a first terminal of said resistor (R1) is coupled to a base terminal of said transistor (Q1), (ii) said capacitor (C1) is coupled between an emitter terminal and said base terminal of said transistor, (iii) said emitter terminal of said transistor (Q1) is coupled to said input port , and (iv) a collector terminal of said transistor is coupled to said circuit ground potential; and a transistor (Q1) configured to operate as a switch; a capacitor (C1); and a resistor (R1), wherein (i) a first terminal of said resistor (R1) is coupled to a base terminal of said transistor (Q1), (ii) said capacitor (C1) is coupled between an emitter terminal and said base terminal of said transistor, (iii) said emitter terminal of said transistor (Q1) is coupled to said input port , and (iv) a collector terminal of said transistor is coupled to said circuit ground potential; and a second switch circuit coupled between said output port and said circuit ground potential, wherein (i) said first impedance matching network provides the input impedance of the input port when said first switch circuit is in a non-conducting state and said second switch circuit is in a conducting state, (ii) said second impedance matching network provides the input impedance of the output port when said first switch circuit is in a conducting state and said second switch circuit is in a non-conducting state, and (iii) the input impedance of the input port and the input impedance of the output port are asymmetrical. <EOS>