An address generator , comprising: a first processing unit comprising a first adder , a first register coupled to an output of the first adder , a first multiplexer , a subtractor , a second register coupled to an output of the subtractor to generate a stage output , wherein an output of the first register is coupled to a first input of the subtractor and an output of the first multiplexer is coupled to a second input of the subtractor , wherein a first input of the first multiplexer is a null value and a second input of the first multiplexer is a block size of K , wherein the stage output is fed back to the first adder ; and a second processing unit coupled to receive the stage output from the first processing unit and configured to provide an address output, the second processing unit comprising a second adder ; a third register coupled to an output of the second adder , a second multiplexer ; a third adder , and a fourth register coupled to an output of the third adder to generate the address output , wherein the second adder is adapted to receive the stage output , and the output of the third register is coupled to a first input of the third adder and an output of the second multiplexer is coupled to a second input of the third adder , and wherein the address output is fed-back to an input of the second adder ; wherein the output of the first register is used to select either the null value or the block size of K as the output of the first multiplexer and the output of the third register is used to select either the null value or the block size of K as the output of the second multiplexer in order to force the stage output to be negative and in a first range from -K to -1 for the block size of K , and the address output of the second processing unit to be in a second range from 0 to K-1. a first processing unit comprising a first adder , a first register coupled to an output of the first adder , a first multiplexer , a subtractor , a second register coupled to an output of the subtractor to generate a stage output , wherein an output of the first register is coupled to a first input of the subtractor and an output of the first multiplexer is coupled to a second input of the subtractor , wherein a first input of the first multiplexer is a null value and a second input of the first multiplexer is a block size of K , wherein the stage output is fed back to the first adder ; and a second processing unit coupled to receive the stage output from the first processing unit and configured to provide an address output, the second processing unit comprising a second adder ; a third register coupled to an output of the second adder , a second multiplexer ; a third adder , and a fourth register coupled to an output of the third adder to generate the address output , wherein the second adder is adapted to receive the stage output , and the output of the third register is coupled to a first input of the third adder and an output of the second multiplexer is coupled to a second input of the third adder , and wherein the address output is fed-back to an input of the second adder ; wherein the output of the first register is used to select either the null value or the block size of K as the output of the first multiplexer and the output of the third register is used to select either the null value or the block size of K as the output of the second multiplexer in order to force the stage output to be negative and in a first range from -K to -1 for the block size of K , and the address output of the second processing unit to be in a second range from 0 to K-1. <EOS>