A programmable logic device (PLD) , comprising: a programmable input/output, I/O, interface configured to interface with a user device over an external bus coupled to the PLD; a bus protection circuit arrangement integrated with the programmable I/O interface and configured to provide I/O bus supply voltage protection for the programmable I/O interface, wherein the bus protection circuit arrangement comprises a cascode transistor arrangement disposed between a bus supply voltage and a ground for the programmable I/O interface; and a bus protection control signal generator coupled to the programmable I/O interface and/or the bus protection circuit arrangement, wherein the bus protection control signal generator is configured to: generate a default bus protection control signal for the cascode transistor arrangement of the PLD prior to completion of a power ramp performed by the user device; generate an intermediate bus protection control signal for the cascode transistor arrangement of the PLD after the completion of the power ramp performed by the user device and prior to completion of loading a PLD configuration into a PLD fabric of the PLD; and generate an operational bus protection control signal for the cascode transistor arrangement of the PLD after the completion of the loading the PLD configuration into the PLD fabric, wherein the cascode transistor arrangement comprises a PMOS protection transistor and an NMOS protection transistor configured to receive the default, intermediate, and operational bus protection control signals generated by the bus protection control signal generator. a programmable input/output, I/O, interface configured to interface with a user device over an external bus coupled to the PLD; a bus protection circuit arrangement integrated with the programmable I/O interface and configured to provide I/O bus supply voltage protection for the programmable I/O interface, wherein the bus protection circuit arrangement comprises a cascode transistor arrangement disposed between a bus supply voltage and a ground for the programmable I/O interface; and a bus protection control signal generator coupled to the programmable I/O interface and/or the bus protection circuit arrangement, wherein the bus protection control signal generator is configured to: generate a default bus protection control signal for the cascode transistor arrangement of the PLD prior to completion of a power ramp performed by the user device; generate an intermediate bus protection control signal for the cascode transistor arrangement of the PLD after the completion of the power ramp performed by the user device and prior to completion of loading a PLD configuration into a PLD fabric of the PLD; and generate an operational bus protection control signal for the cascode transistor arrangement of the PLD after the completion of the loading the PLD configuration into the PLD fabric, generate a default bus protection control signal for the cascode transistor arrangement of the PLD prior to completion of a power ramp performed by the user device; generate an intermediate bus protection control signal for the cascode transistor arrangement of the PLD after the completion of the power ramp performed by the user device and prior to completion of loading a PLD configuration into a PLD fabric of the PLD; and generate an operational bus protection control signal for the cascode transistor arrangement of the PLD after the completion of the loading the PLD configuration into the PLD fabric, wherein the cascode transistor arrangement comprises a PMOS protection transistor and an NMOS protection transistor configured to receive the default, intermediate, and operational bus protection control signals generated by the bus protection control signal generator. <EOS>