A method of manufacturing a tunnel field effect transistor having a group IV semiconductor substrate and a group III-V compound semiconductor nanowire , comprising: a step of preparing a substrate comprising a group IV semiconductor substrate having a 2×1 surface and an insulating film covering the 2×1 surface and having an opening; a step of applying heat treatment at a temperature between 830 and 900 o C to the substrate to convert the 2×1 surface exposed in the opening to a 1×1 surface; a step of lowering a temperature of the substrate to less than 830°C thus losing the 1×1 surface and then further lowering a temperature of the substrate to 350 to 450°C to recover the 1×1 surface; a step of supplying a group III raw material to the substrate under a temperature of 400 to 500°C and converting the 1×1 surface exposed in the opening to a A surface, or supplying a group V raw material to the substrate under a temperature of 400 to 500°C and converting the 1×1 surface exposed in the opening to a B surface; a step of growing a group III-V compound semiconductor nanowire without a metal catalyst from the 1×1 surface converted to the A surface or the B surface and exposed in the opening; a step of forming a gate electrode for applying an electric field to an interface between the 1×1 surface of the group IV semiconductor substrate and the group III-V compound semiconductor nanowire ; and a step of forming one of a source electrode and a drain electrode on the group IV semiconductor substrate so as not to contact the group III-V compound semiconductor nanowire and forming the other of the source electrode and the drain electrode on the group III-V compound semiconductor nanowire . a step of preparing a substrate comprising a group IV semiconductor substrate having a 2×1 surface and an insulating film covering the 2×1 surface and having an opening; a step of applying heat treatment at a temperature between 830 and 900 o C to the substrate to convert the 2×1 surface exposed in the opening to a 1×1 surface; a step of lowering a temperature of the substrate to less than 830°C thus losing the 1×1 surface and then further lowering a temperature of the substrate to 350 to 450°C to recover the 1×1 surface; a step of supplying a group III raw material to the substrate under a temperature of 400 to 500°C and converting the 1×1 surface exposed in the opening to a A surface, or supplying a group V raw material to the substrate under a temperature of 400 to 500°C and converting the 1×1 surface exposed in the opening to a B surface; a step of growing a group III-V compound semiconductor nanowire without a metal catalyst from the 1×1 surface converted to the A surface or the B surface and exposed in the opening; a step of forming a gate electrode for applying an electric field to an interface between the 1×1 surface of the group IV semiconductor substrate and the group III-V compound semiconductor nanowire ; and a step of forming one of a source electrode and a drain electrode on the group IV semiconductor substrate so as not to contact the group III-V compound semiconductor nanowire and forming the other of the source electrode and the drain electrode on the group III-V compound semiconductor nanowire . <EOS>