A device, comprising: an amplifier , comprising: an input ; an output ; and a first set of transistors coupled between the input and the output; and a linearizer , comprising: a second set of transistors (3 12a, 312b, 312c, 312d) coupled between a DC power supply and the input of the amplifier and configured to receive a DC power supply voltage from the DC power supply; and wherein the first set of transistors comprises a cascode topology of transistors that is formed by a first and a second field effect transistor, FET, comprising a common-gate and a common-source configuration, respectively; characterized in that the linearizer is configured to provide a non-linear shunt impedance for an AC signal received at the input of the amplifier ; wherein the second set of transistors comprises a cascode topology of transistors that is formed by a first and a second transistor each comprising a common-control terminal configuration, wherein channels of the first and second transistors of the second set of transistors are coupled to one another between the input of the amplifier and the DC power supply in such a way that said first and second transistors are coupled in series and a serial connection formed by said first and second transistors is directly coupled between the input of the amplifier and the DC power supply, and wherein each of the first and second transistors of the second set of transistors is a FET, and comprises a common-gate configuration with the respective gate configured to be biased by a respective selectable DC bias voltage to set the non-linear shunt impedance. an amplifier , comprising: an input ; an output ; and a first set of transistors coupled between the input and the output; and an input ; an output ; and a first set of transistors coupled between the input and the output; and a linearizer , comprising: a second set of transistors (3 12a, 312b, 312c, 312d) coupled between a DC power supply and the input of the amplifier and configured to receive a DC power supply voltage from the DC power supply; and wherein the first set of transistors comprises a cascode topology of transistors that is formed by a first and a second field effect transistor, FET, comprising a common-gate and a common-source configuration, respectively; characterized in that the linearizer is configured to provide a non-linear shunt impedance for an AC signal received at the input of the amplifier ; wherein the second set of transistors comprises a cascode topology of transistors that is formed by a first and a second transistor each comprising a common-control terminal configuration, wherein channels of the first and second transistors of the second set of transistors are coupled to one another between the input of the amplifier and the DC power supply in such a way that said first and second transistors are coupled in series and a serial connection formed by said first and second transistors is directly coupled between the input of the amplifier and the DC power supply, and wherein each of the first and second transistors of the second set of transistors is a FET, and comprises a common-gate configuration with the respective gate configured to be biased by a respective selectable DC bias voltage to set the non-linear shunt impedance. <EOS>