A battery powered electronic device comprising: internal circuitry ; and power saving circuitry coupled to the internal circuitry, wherein the power saving circuitry is configured to apply a first effective voltage (VDD-VSS) across the internal circuitry during a non-idle state of the internal circuitry, and apply a second effective voltage ((VDD-Vtp) - (VSS+Vtn)) across the internal circuitry during an idle state of the internal circuitry, wherein the second effective voltage is less than the first effective voltage, and wherein the second effective voltage is selected to ensure that data stored by the internal circuitry is retained during the idle state, and wherein the power saving circuitry comprises: a first transistor configured to couple a first nominal supply voltage terminal to a first internal supply node (N1) used to power the internal circuitry during the non-idle state; and a second transistor having a first threshold voltage (Vtp), wherein the second transistor is configured to couple the first nominal supply voltage terminal to the first internal supply node in a source-follower configuration during the idle state, wherein a first internal supply voltage (VDDa) applied to the first internal supply node changes by a voltage equal to the first threshold voltage for transitions between the idle state and the non-idle state, characterised in that : the power saving circuitry includes means for reverse biasing (VBIAS_P, VBIAS_N) body regions of transistors (131-132) of the internal circuitry during the idle state. internal circuitry ; and power saving circuitry coupled to the internal circuitry, wherein the power saving circuitry is configured to apply a first effective voltage (VDD-VSS) across the internal circuitry during a non-idle state of the internal circuitry, and apply a second effective voltage ((VDD-Vtp) - (VSS+Vtn)) across the internal circuitry during an idle state of the internal circuitry, wherein the second effective voltage is less than the first effective voltage, and wherein the second effective voltage is selected to ensure that data stored by the internal circuitry is retained during the idle state, and wherein the power saving circuitry comprises: a first transistor configured to couple a first nominal supply voltage terminal to a first internal supply node (N1) used to power the internal circuitry during the non-idle state; and a second transistor having a first threshold voltage (Vtp), wherein the second transistor is configured to couple the first nominal supply voltage terminal to the first internal supply node in a source-follower configuration during the idle state, wherein a first internal supply voltage (VDDa) applied to the first internal supply node changes by a voltage equal to the first threshold voltage for transitions between the idle state and the non-idle state, characterised in that : the power saving circuitry includes means for reverse biasing (VBIAS_P, VBIAS_N) body regions of transistors (131-132) of the internal circuitry during the idle state. a first transistor configured to couple a first nominal supply voltage terminal to a first internal supply node (N1) used to power the internal circuitry during the non-idle state; and a second transistor having a first threshold voltage (Vtp), wherein the second transistor is configured to couple the first nominal supply voltage terminal to the first internal supply node in a source-follower configuration during the idle state, wherein a first internal supply voltage (VDDa) applied to the first internal supply node changes by a voltage equal to the first threshold voltage for transitions between the idle state and the non-idle state, characterised in that : the power saving circuitry includes means for reverse biasing (VBIAS_P, VBIAS_N) body regions of transistors (131-132) of the internal circuitry during the idle state. <EOS>