A method for manufacturing a VDMOS device, comprising: forming a trench in a semiconductor substrate , the trench comprising a first trench region , a second trench region , and a third trench region connecting the first trench region and the second trench region , wherein a width of the first trench region is greater than widths of the second trench region and the third trench region , the widths of the first and second trench regions extending in a first direction and the width of the third trench region extending in a direction perpendicular to the first direction; forming an insulating layer on the semiconductor substrate , the insulating layer filling up the second trench region and the third trench region and being attached to a sidewall of the first trench region ; forming a first polysilicon layer on the insulating layer , the first polysilicon layer filling up the first trench region ; removing a portion of the first polysilicon layer until the insulating layer being exposed, wherein the first polysilicon layer formed in the first trench region serves as a first electrode serving as a deep gate; removing all of the insulating layer on a surface of the semiconductor substrate and a portion of the insulating layer in the trench; forming a gate oxide layer on the semiconductor substrate ; forming a second polysilicon layer on the gate oxide layer , the second polysilicon layer filling up the trench, the gate oxide layer isolating the first polysilicon layer and the second polysilicon layer ; and removing a portion of the second polysilicon layer until the gate oxide layer on the surface of the semiconductor substrate and on a top of the first polysilicon layer being exposed, wherein the second polysilicon layer formed in the trench serves as a second electrode serving as a shallow gate. forming a trench in a semiconductor substrate , the trench comprising a first trench region , a second trench region , and a third trench region connecting the first trench region and the second trench region , wherein a width of the first trench region is greater than widths of the second trench region and the third trench region , the widths of the first and second trench regions extending in a first direction and the width of the third trench region extending in a direction perpendicular to the first direction; forming an insulating layer on the semiconductor substrate , the insulating layer filling up the second trench region and the third trench region and being attached to a sidewall of the first trench region ; forming a first polysilicon layer on the insulating layer , the first polysilicon layer filling up the first trench region ; removing a portion of the first polysilicon layer until the insulating layer being exposed, wherein the first polysilicon layer formed in the first trench region serves as a first electrode serving as a deep gate; removing all of the insulating layer on a surface of the semiconductor substrate and a portion of the insulating layer in the trench; forming a gate oxide layer on the semiconductor substrate ; forming a second polysilicon layer on the gate oxide layer , the second polysilicon layer filling up the trench, the gate oxide layer isolating the first polysilicon layer and the second polysilicon layer ; and removing a portion of the second polysilicon layer until the gate oxide layer on the surface of the semiconductor substrate and on a top of the first polysilicon layer being exposed, wherein the second polysilicon layer formed in the trench serves as a second electrode serving as a shallow gate. <EOS>