A power amplifier comprising a circuit that comprises an RF-LDMOS transistor and a DC biasing circuit for biasing the RF-LDMOS transistor, wherein the biasing circuit is incorporated into a same semiconductor substrate as the RF-LDMOS transistor for which the bias point is to be provided, said semiconductor substrate having a major surface , and wherein a source of the RF-LDMOS transistor is electrically connected to the semiconductor substrate ; wherein the DC biasing circuit includes a DC LDMOS transistor that comprises: a gate located on the major surface ; a drain region having a first conductivity type; a source region having the first conductivity type, wherein the source region is located within a region having a second conductivity type, said region having the second conductivity extending laterally within the DC LDMOS transistor to a greater extent than the source region so as to surround the source region beneath the major surface ; a channel region comprised of a part of said region having the second conductivity type that is located beneath the gate ; and a common contact connected to both the source region and the region having the second conductivity type; wherein the semiconductor substrate is doped to have the same conductivity type as the channel region, wherein the drain region extends laterally away from the gate along the major surface of the substrate and wherein the drain region also extends beneath the gate , the source region and the region having the second conductivity type, the drain region surrounding the region having the second conductivity type beneath the major surface so that the source region and the region having the second conductivity type are electrically cut off from the underlying substrate . wherein the DC biasing circuit includes a DC LDMOS transistor that comprises: a gate located on the major surface ; a drain region having a first conductivity type; a source region having the first conductivity type, wherein the source region is located within a region having a second conductivity type, said region having the second conductivity extending laterally within the DC LDMOS transistor to a greater extent than the source region so as to surround the source region beneath the major surface ; a channel region comprised of a part of said region having the second conductivity type that is located beneath the gate ; and a common contact connected to both the source region and the region having the second conductivity type; a gate located on the major surface ; a drain region having a first conductivity type; a source region having the first conductivity type, wherein the source region is located within a region having a second conductivity type, said region having the second conductivity extending laterally within the DC LDMOS transistor to a greater extent than the source region so as to surround the source region beneath the major surface ; a channel region comprised of a part of said region having the second conductivity type that is located beneath the gate ; and a common contact connected to both the source region and the region having the second conductivity type; wherein the semiconductor substrate is doped to have the same conductivity type as the channel region, wherein the drain region extends laterally away from the gate along the major surface of the substrate and wherein the drain region also extends beneath the gate , the source region and the region having the second conductivity type, the drain region surrounding the region having the second conductivity type beneath the major surface so that the source region and the region having the second conductivity type are electrically cut off from the underlying substrate . <EOS>