A circuit configured to reduce a sense amplifier offset voltage, the circuit comprising: a sense amplifier that is responsive to a plurality of latches for storing a particular test code of a series of test codes, wherein the sense amplifier comprises a plurality of transistors (252 - 258, 262 - 268) and wherein the state of the plurality of transistors (252 - 258, 262 - 268) is controlled based on the particular test code;a first bit line coupled to a data cell and coupled to a first input of the sense amplifier , wherein a current determined by the plurality of transistors (252 - 258, 262 - 268) is applied to the data cell via the first bit line ; characterized by : a second bit line coupled to a reference cell and coupled to a second input of the sense amplifier ; a test mode reference circuit including a first test mode resistor coupled to the first bit line and a second test mode resistor coupled to the second bit line wherein the first test mode resistor and the second test mode resistor have substantially equal resistances, the test mode reference circuit configured to provide at least one test voltage to the first input and the second input of the sense amplifier ; and a test mode control circuit configured to provide the series of test codes to the plurality of latches to determine a characteristic of a sense amplifier , wherein: the particular test code is for causing an output of the sense amplifier to change a state of the sense amplifier; the output of the sense amplifier is configured to be provided to the test mode control circuit ; and the test mode control circuit is configured to determine an offset compensation code based on the changed state of the sense amplifier. a sense amplifier that is responsive to a plurality of latches for storing a particular test code of a series of test codes, wherein the sense amplifier comprises a plurality of transistors (252 - 258, 262 - 268) and wherein the state of the plurality of transistors (252 - 258, 262 - 268) is controlled based on the particular test code;a first bit line coupled to a data cell and coupled to a first input of the sense amplifier , wherein a current determined by the plurality of transistors (252 - 258, 262 - 268) is applied to the data cell via the first bit line ; characterized by : a second bit line coupled to a reference cell and coupled to a second input of the sense amplifier ; a test mode reference circuit including a first test mode resistor coupled to the first bit line and a second test mode resistor coupled to the second bit line wherein the first test mode resistor and the second test mode resistor have substantially equal resistances, the test mode reference circuit configured to provide at least one test voltage to the first input and the second input of the sense amplifier ; and a test mode control circuit configured to provide the series of test codes to the plurality of latches to determine a characteristic of a sense amplifier , wherein: the particular test code is for causing an output of the sense amplifier to change a state of the sense amplifier; the output of the sense amplifier is configured to be provided to the test mode control circuit ; and the test mode control circuit is configured to determine an offset compensation code based on the changed state of the sense amplifier. the particular test code is for causing an output of the sense amplifier to change a state of the sense amplifier; the output of the sense amplifier is configured to be provided to the test mode control circuit ; and the test mode control circuit is configured to determine an offset compensation code based on the changed state of the sense amplifier. <EOS>