A current source, comprising: a first transistor having a gate/ base, a drain/ collector, and a source/ emitter, the first transistor configured to source a current at the source/ emitter; a second transistor having a gate/ base, a drain/ collector, and a source/ emitter, the source/ emitter of the second transistor being electrically coupled to a common node , and the drain/ collector of the second transistor receiving an input current; a resistor electrically coupled between the source/ emitter of the first transistor and the common node, a decoupling capacitor having first and second terminals; a first switch (140-1) having first and second terminals; a second switch (120-1) having first and second terminals; a shunt capacitor coupled between the gate/ base of the first transistor and the common node; a third switch (140-2) coupled between the shunt capacitor and the drain/ collector of the second transistor ; and a fourth switch (120-2) coupled between gate/ base and the drain/ collector of the second transistor; wherein the gate/ base of the second transistor is coupled to the first terminal of the decoupling capacitor ; wherein the second terminal of the decoupling capacitor is coupled to a first terminal of the first switch (140-1); wherein the second terminal of the first switch (140-1) is coupled to the source/ emitter of the first transistor; wherein the first terminal of the second switch (120-1) is coupled to the second terminal of the decoupling capacitor ; wherein a bias voltage is applied to the second terminal of the second switch (120-1); whereby when the first and third switches are closed with the second and fourth switches open, a gain mode is provided, and with the first and third switches open and the second and fourth switches closed, a clamp mode is provided wherein the shunt capacitor retains at the gate/ base of the first transistor a value sampled during the gain mode. a first transistor having a gate/ base, a drain/ collector, and a source/ emitter, the first transistor configured to source a current at the source/ emitter; a second transistor having a gate/ base, a drain/ collector, and a source/ emitter, the source/ emitter of the second transistor being electrically coupled to a common node , and the drain/ collector of the second transistor receiving an input current; a resistor electrically coupled between the source/ emitter of the first transistor and the common node, a decoupling capacitor having first and second terminals; a first switch (140-1) having first and second terminals; a second switch (120-1) having first and second terminals; a shunt capacitor coupled between the gate/ base of the first transistor and the common node; a third switch (140-2) coupled between the shunt capacitor and the drain/ collector of the second transistor ; and a fourth switch (120-2) coupled between gate/ base and the drain/ collector of the second transistor; wherein the gate/ base of the second transistor is coupled to the first terminal of the decoupling capacitor ; wherein the second terminal of the decoupling capacitor is coupled to a first terminal of the first switch (140-1); wherein the second terminal of the first switch (140-1) is coupled to the source/ emitter of the first transistor; wherein the first terminal of the second switch (120-1) is coupled to the second terminal of the decoupling capacitor ; wherein a bias voltage is applied to the second terminal of the second switch (120-1); whereby when the first and third switches are closed with the second and fourth switches open, a gain mode is provided, and with the first and third switches open and the second and fourth switches closed, a clamp mode is provided wherein the shunt capacitor retains at the gate/ base of the first transistor a value sampled during the gain mode. <EOS>