A display device, comprising: a substrate (SUB) comprising a display area (AA) and a non-display area (NA) adjacent to the display area (AA); an anode electrode (ANO) positioned in the display area (AA); an organic light emitting layer (OL) disposed on the anode electrode (ANO) and positioned in the display area (AA); a cathode electrode (CAT) disposed on the organic light emitting layer (OL); and a gate driver positioned in the display area (AA), a driving thin film transistor, TFT, positioned in the display area (AA), a protective layer (PAS) covering the gate driver ; and a planarizing layer (PL) disposed on the protective layer (PAS), wherein the driving TFT (DT) is disposed on the planarizing layer (PL) and comprises: a D-drain electrode (DD) connected to the anode electrode; a D-source electrode (DS); a D-gate electrode (DG); and a D-semiconductor layer (DA), wherein the gate driver is disposed on the substrate (SUB), and wherein the driving TFT (DT) is disposed on the gate driver , wherein the gate driver comprises a plurality of gate TFTs (GT), wherein each of the plurality of gate TFTs (GT) comprises: a G-semiconductor layer (GA); a G-gate electrode (GG); a G-source electrode (GS); and a G-drain electrode (GD), wherein a contact hole (H) is formed in the planarizing layer (PL) and the protective layer (PAS), and the D-gate electrode (DG) passes through the contact hole (H) such that the D-gate electrode (DG) is contacted with the G-drain electrode (GD), wherein the D-gate electrode (DG) does not overlap the D-source electrode (DS) nor the D-drain electrode (DD). a substrate (SUB) comprising a display area (AA) and a non-display area (NA) adjacent to the display area (AA); an anode electrode (ANO) positioned in the display area (AA); an organic light emitting layer (OL) disposed on the anode electrode (ANO) and positioned in the display area (AA); a cathode electrode (CAT) disposed on the organic light emitting layer (OL); and a gate driver positioned in the display area (AA), a driving thin film transistor, TFT, positioned in the display area (AA), a protective layer (PAS) covering the gate driver ; and a planarizing layer (PL) disposed on the protective layer (PAS), wherein the driving TFT (DT) is disposed on the planarizing layer (PL) and comprises: a D-drain electrode (DD) connected to the anode electrode; a D-source electrode (DS); a D-gate electrode (DG); and a D-semiconductor layer (DA), a D-drain electrode (DD) connected to the anode electrode; a D-source electrode (DS); a D-gate electrode (DG); and a D-semiconductor layer (DA), wherein the gate driver is disposed on the substrate (SUB), and wherein the driving TFT (DT) is disposed on the gate driver , wherein the gate driver comprises a plurality of gate TFTs (GT), wherein each of the plurality of gate TFTs (GT) comprises: a G-semiconductor layer (GA); a G-gate electrode (GG); a G-source electrode (GS); and a G-drain electrode (GD), a G-semiconductor layer (GA); a G-gate electrode (GG); a G-source electrode (GS); and a G-drain electrode (GD), wherein a contact hole (H) is formed in the planarizing layer (PL) and the protective layer (PAS), and the D-gate electrode (DG) passes through the contact hole (H) such that the D-gate electrode (DG) is contacted with the G-drain electrode (GD), wherein the D-gate electrode (DG) does not overlap the D-source electrode (DS) nor the D-drain electrode (DD). <EOS>