A level shifter for receiving an input of a first voltage domain and generating an output of a second voltage domain, wherein a "0" in the first voltage domain is a first voltage and a "1" in the first voltage domain is a second voltage and a "0" in the second voltage domain is the first voltage and a "1" in the second voltage domain is a third voltage different than the second voltage, the level shifter comprising: a first power source providing the third voltage (VDDH); a first PMOS transistor comprising a first terminal coupled to the first power source, a gate, and a second terminal; a second PMOS transistor comprising a first terminal coupled to the first power source, a gate coupled to the second terminal of the first PMOS transistor, and a second terminal coupled to the gate of the first PMOS transistor and to an output node (OUT) for providing the output; a first NMOS transistor comprising a first terminal coupled to the second terminal of the first PMOS transistor, a gate configured to receive a first signal (CC); and a second terminal; a second NMOS transistor comprising a first terminal coupled to the second terminal of the first NMOS transistor, a gate configured to receive the input (C), and a second terminal coupled to the first voltage; a third NMOS transistor comprising a first terminal coupled to the output node, a gate coupled to receive a second signal (CC-BAR), and a second terminal; and a fourth NMOS transistor comprising a first terminal coupled to the second terminal of the third NMOS transistor, a gate configured to receive a complement of the input (C-BAR), and a second terminal coupled to the first voltage; wherein the first signal is twice the second voltage when the input is at the second voltage and is the second voltage when the input is at the first voltage; wherein the second signal is twice the second voltage when the input is at the first voltage and is the second voltage when the input is at the second voltage; and wherein when the input is the first voltage, the output is the first voltage, and when the input is the second voltage, the output is the third voltage. a first power source providing the third voltage (VDDH); a first PMOS transistor comprising a first terminal coupled to the first power source, a gate, and a second terminal; a second PMOS transistor comprising a first terminal coupled to the first power source, a gate coupled to the second terminal of the first PMOS transistor, and a second terminal coupled to the gate of the first PMOS transistor and to an output node (OUT) for providing the output; a first NMOS transistor comprising a first terminal coupled to the second terminal of the first PMOS transistor, a gate configured to receive a first signal (CC); and a second terminal; a second NMOS transistor comprising a first terminal coupled to the second terminal of the first NMOS transistor, a gate configured to receive the input (C), and a second terminal coupled to the first voltage; a third NMOS transistor comprising a first terminal coupled to the output node, a gate coupled to receive a second signal (CC-BAR), and a second terminal; and a fourth NMOS transistor comprising a first terminal coupled to the second terminal of the third NMOS transistor, a gate configured to receive a complement of the input (C-BAR), and a second terminal coupled to the first voltage; wherein the first signal is twice the second voltage when the input is at the second voltage and is the second voltage when the input is at the first voltage; wherein the second signal is twice the second voltage when the input is at the first voltage and is the second voltage when the input is at the second voltage; and wherein when the input is the first voltage, the output is the first voltage, and when the input is the second voltage, the output is the third voltage. <EOS>