A flash memory system, comprising: a read circuit comprising a selected flash memory cell , a first bit line coupled to the selected flash memory cell, a first variable capacitor , a first voltage source , and a first switch , wherein prior to a read operation, the first switch is opened and the first voltage source charges the first variable capacitor, and at the beginning of a read operation, the first switch is closed and the first variable capacitor charges the first bit line and then the first switch is opened and the first bit line discharges through the selected flash memory cell; a reference circuit comprising a reference flash memory cell , a second bit line coupled to the reference flash memory cell, a second variable capacitor , a second voltage source , and a second switch , wherein prior to a read operation, the second switch is opened and the second voltage source charges the second variable capacitor, and at the beginning of a read operation, the second switch is closed and the second variable capacitor charges the second bit line and then the second switch is opened and the second bit line discharges through the reference flash memory cell; a timing comparison circuit for outputting a first value when the voltage of the first bit line drops below a voltage threshold before the voltage of the second bit line during a read operation and for outputting a second value when the voltage of the second bit line drops below the voltage threshold before the voltage of the first bit line during a read operation, wherein the first value and second value each indicate a value stored in the selected flash memory cell; and a trim controller for adjusting the capacitance of the first variable capacitor and the capacitance of the second variable capacitor during a calibration process. a read circuit comprising a selected flash memory cell , a first bit line coupled to the selected flash memory cell, a first variable capacitor , a first voltage source , and a first switch , wherein prior to a read operation, the first switch is opened and the first voltage source charges the first variable capacitor, and at the beginning of a read operation, the first switch is closed and the first variable capacitor charges the first bit line and then the first switch is opened and the first bit line discharges through the selected flash memory cell; a reference circuit comprising a reference flash memory cell , a second bit line coupled to the reference flash memory cell, a second variable capacitor , a second voltage source , and a second switch , wherein prior to a read operation, the second switch is opened and the second voltage source charges the second variable capacitor, and at the beginning of a read operation, the second switch is closed and the second variable capacitor charges the second bit line and then the second switch is opened and the second bit line discharges through the reference flash memory cell; a timing comparison circuit for outputting a first value when the voltage of the first bit line drops below a voltage threshold before the voltage of the second bit line during a read operation and for outputting a second value when the voltage of the second bit line drops below the voltage threshold before the voltage of the first bit line during a read operation, wherein the first value and second value each indicate a value stored in the selected flash memory cell; and a trim controller for adjusting the capacitance of the first variable capacitor and the capacitance of the second variable capacitor during a calibration process. <EOS>