A chip , wherein the chip is connectable to a controller , and the chip comprises: a first silicon-based driver die , a second silicon-based driver die , a first gallium nitride die , and a second gallium nitride die , wherein the first silicon-based driver die is connected to the first gallium nitride die , the second silicon-based driver die is connected to the second gallium nitride die , and the first gallium nitride die is connected to the second silicon-based driver die ; the first silicon-based driver die is connectable to a first output terminal of the controller and a second output terminal of the controller , a pulse signal (HI) output by the first output terminal is used for driving a high-side gallium nitride power transistor , and a pulse signal output by the second output terminal is used for driving a low-side gallium nitride power transistor ; a first silicon-based circuit is integrated on the first silicon-based driver die , a second silicon-based circuit is integrated on the second silicon-based driver die , a gallium nitride circuit and the low-side gallium nitride power transistor are integrated on the first gallium nitride die , the high-side gallium nitride power transistor is integrated on the second gallium nitride die , and the gallium nitride circuit is high-voltage resistant; the first silicon-based circuit is connected to the gallium nitride circuit , and the gallium nitride circuit is connected to the second silicon-based circuit ; the first silicon-based circuit receives the pulse signal (HI) output by the first output terminal , and transfers the pulse signal (HI) to the gallium nitride circuit ; the gallium nitride circuit is configured to share an input voltage (VB) of the second silicon-based circuit ; and the gallium nitride circuit transfers the pulse signal (HI) to the second silicon-based circuit . a first silicon-based driver die , a second silicon-based driver die , a first gallium nitride die , and a second gallium nitride die , wherein the first silicon-based driver die is connected to the first gallium nitride die , the second silicon-based driver die is connected to the second gallium nitride die , and the first gallium nitride die is connected to the second silicon-based driver die ; the first silicon-based driver die is connectable to a first output terminal of the controller and a second output terminal of the controller , a pulse signal (HI) output by the first output terminal is used for driving a high-side gallium nitride power transistor , and a pulse signal output by the second output terminal is used for driving a low-side gallium nitride power transistor ; a first silicon-based circuit is integrated on the first silicon-based driver die , a second silicon-based circuit is integrated on the second silicon-based driver die , a gallium nitride circuit and the low-side gallium nitride power transistor are integrated on the first gallium nitride die , the high-side gallium nitride power transistor is integrated on the second gallium nitride die , and the gallium nitride circuit is high-voltage resistant; the first silicon-based circuit is connected to the gallium nitride circuit , and the gallium nitride circuit is connected to the second silicon-based circuit ; the first silicon-based circuit receives the pulse signal (HI) output by the first output terminal , and transfers the pulse signal (HI) to the gallium nitride circuit ; the gallium nitride circuit is configured to share an input voltage (VB) of the second silicon-based circuit ; and the gallium nitride circuit transfers the pulse signal (HI) to the second silicon-based circuit . <EOS>