A folded cascode amplifier , comprising: a first cascode circuit including a first transistor (M19) and a second transistor (M20); a second cascode circuit coupled to a differential output (V o1 , V o2 ) and including a first pair (M37, M38) of transistors including a first transistor (M37) and a second transistor (M38) and a second pair (M39, M40) of transistors including a third transistor (M39) and a fourth transistor (M40), wherein a gate of each of the first, second, third and fourth transistors of the second cascode circuit is configured to receive a bias voltage (Vb2), and a drain of the first transistor (M19) of the first cascode circuit is coupled to a source of each of the first (M37) and second (M38) transistors of the second cascode circuit; and a differential input including a first transistor (M21) of a differential pair of input transistors coupled to each of the first transistor (M19) of the first cascode circuit and the first (M37) and second transistors (M38) of the second cascode circuit, the differential input further including a second transistor (M22) of the differential pair of input transistors coupled to each of the second transistor (M20) of the first cascode circuit and the third (M39) and fourth (M40) transistors of the second cascode circuit, wherein the first transistor (M19) of the first cascode circuit, the first transistor (M21) of the differential pair of input transistors (M21, M22) and the first pair of transistors (M37, M38) of the second cascode circuit form a first plurality of current paths to generate a first output (V o2 ) of the differential output (V o1 , V o2 ). a first cascode circuit including a first transistor (M19) and a second transistor (M20); a second cascode circuit coupled to a differential output (V o1 , V o2 ) and including a first pair (M37, M38) of transistors including a first transistor (M37) and a second transistor (M38) and a second pair (M39, M40) of transistors including a third transistor (M39) and a fourth transistor (M40), wherein a gate of each of the first, second, third and fourth transistors of the second cascode circuit is configured to receive a bias voltage (Vb2), and a drain of the first transistor (M19) of the first cascode circuit is coupled to a source of each of the first (M37) and second (M38) transistors of the second cascode circuit; and a differential input including a first transistor (M21) of a differential pair of input transistors coupled to each of the first transistor (M19) of the first cascode circuit and the first (M37) and second transistors (M38) of the second cascode circuit, the differential input further including a second transistor (M22) of the differential pair of input transistors coupled to each of the second transistor (M20) of the first cascode circuit and the third (M39) and fourth (M40) transistors of the second cascode circuit, wherein the first transistor (M19) of the first cascode circuit, the first transistor (M21) of the differential pair of input transistors (M21, M22) and the first pair of transistors (M37, M38) of the second cascode circuit form a first plurality of current paths to generate a first output (V o2 ) of the differential output (V o1 , V o2 ). <EOS>