A method of controlling timing of switch control signals of a switching voltage regulator, comprising: generating a regulated output voltage based upon a switching voltage; generating the switching voltage through controlled closing and opening of a series switch element (SW1) and a shunt switch element (SW2); controlling, by a delay block , the closing and opening of the series switch element (SW1) and a shunt switch element (SW2), comprising; receiving, by the delay block , a timing signal; generating a series switch control signal by controllably delaying the timing signal with a first delay, characterised in that both rising and falling edges of the timing signal are delayed by the first delay, and wherein the first delay includes a sum of a non-overlap time Tnon and a variable skew delay Tskew_var; and generating a shunt switch control signal by inverting the timing signal, forming an AND conjunction of the inverted timing signal and a delayed inverted timing signal, wherein the delayed inverted timing signal is delayed by a second delay, wherein the second delay includes two of the non-overlap time Tnon, wherein an intermediate output is generated by forming the AND conjunction of the inverted timing signal and the delayed inverted timing signal, and wherein the shunt switch control signal is generated by further delaying the intermediate output by a delay Tskew_fixed. generating a regulated output voltage based upon a switching voltage; generating the switching voltage through controlled closing and opening of a series switch element (SW1) and a shunt switch element (SW2); controlling, by a delay block , the closing and opening of the series switch element (SW1) and a shunt switch element (SW2), comprising; receiving, by the delay block , a timing signal; generating a series switch control signal by controllably delaying the timing signal with a first delay, characterised in that both rising and falling edges of the timing signal are delayed by the first delay, and wherein the first delay includes a sum of a non-overlap time Tnon and a variable skew delay Tskew_var; and generating a shunt switch control signal by inverting the timing signal, forming an AND conjunction of the inverted timing signal and a delayed inverted timing signal, wherein the delayed inverted timing signal is delayed by a second delay, wherein the second delay includes two of the non-overlap time Tnon, wherein an intermediate output is generated by forming the AND conjunction of the inverted timing signal and the delayed inverted timing signal, and wherein the shunt switch control signal is generated by further delaying the intermediate output by a delay Tskew_fixed. receiving, by the delay block , a timing signal; generating a series switch control signal by controllably delaying the timing signal with a first delay, characterised in that both rising and falling edges of the timing signal are delayed by the first delay, and wherein the first delay includes a sum of a non-overlap time Tnon and a variable skew delay Tskew_var; and generating a shunt switch control signal by inverting the timing signal, forming an AND conjunction of the inverted timing signal and a delayed inverted timing signal, wherein the delayed inverted timing signal is delayed by a second delay, wherein the second delay includes two of the non-overlap time Tnon, wherein an intermediate output is generated by forming the AND conjunction of the inverted timing signal and the delayed inverted timing signal, and wherein the shunt switch control signal is generated by further delaying the intermediate output by a delay Tskew_fixed. <EOS>