An event-driven sensor comprising: - a pixel array ; - a column readout circuit coupled to column output lines of the pixel array, the column readout circuit comprising a plurality of column register cells , each column register cell being coupled to a corresponding one of the column output lines, wherein each column register cell is configured to activate a column event output signal (addrx, xi) in response to the detection of an event indicated on the column output line; and - a row readout circuit comprising a readout memory having a storage location corresponding to each pixel of the pixel array, the readout memory having sets of one or more row lines for writing to rows of memory locations of the readout memory , wherein each row output line of the pixel array is coupled, via a corresponding row line control circuit , to a corresponding one of the sets of one or more row lines of the readout memory , wherein: the column output lines are column readout request lines, the column readout circuit being further coupled to acknowledgement column lines of the pixel array, and wherein the row output lines are row readout request lines, the row readout circuit being further coupled to acknowledgement row lines of the pixel array; and the readout memory further comprises sets of one or more column lines for controlling write operations to columns of memory locations of the readout memory, each set of one or more column lines being controlled based on a corresponding one of the column event output signals. - a pixel array ; - a column readout circuit coupled to column output lines of the pixel array, the column readout circuit comprising a plurality of column register cells , each column register cell being coupled to a corresponding one of the column output lines, wherein each column register cell is configured to activate a column event output signal (addrx, xi) in response to the detection of an event indicated on the column output line; and - a row readout circuit comprising a readout memory having a storage location corresponding to each pixel of the pixel array, the readout memory having sets of one or more row lines for writing to rows of memory locations of the readout memory , wherein each row output line of the pixel array is coupled, via a corresponding row line control circuit , to a corresponding one of the sets of one or more row lines of the readout memory , wherein: the column output lines are column readout request lines, the column readout circuit being further coupled to acknowledgement column lines of the pixel array, and wherein the row output lines are row readout request lines, the row readout circuit being further coupled to acknowledgement row lines of the pixel array; and the readout memory further comprises sets of one or more column lines for controlling write operations to columns of memory locations of the readout memory, each set of one or more column lines being controlled based on a corresponding one of the column event output signals. the column output lines are column readout request lines, the column readout circuit being further coupled to acknowledgement column lines of the pixel array, and wherein the row output lines are row readout request lines, the row readout circuit being further coupled to acknowledgement row lines of the pixel array; and the readout memory further comprises sets of one or more column lines for controlling write operations to columns of memory locations of the readout memory, each set of one or more column lines being controlled based on a corresponding one of the column event output signals. <EOS>