A wiring board for simultaneous testing of multiple semiconductor devices, comprising: a multilayer ceramic substrate having a plurality of ceramic layers and a plurality of conductor layers alternately stacked to each other and via conductors formed in the ceramic layers ; an organic wiring structure arranged on a main surface of the multilayer ceramic substrate ; a plurality of connection pads formed on a surface of the organic wiring structure for connection to capacitors ; and a plurality of test pad groups formed on the surface of the organic wiring structure , each of the test pad groups having a plurality of test pads for testing of any one of the semiconductor devices, the organic wiring structure having a plurality of insulating resin layers (43 to 49) and a plurality of inner conductor layers alternately stacked to each other such that one of the plurality of insulating resin layers is located outermost of the organic wiring structure , the plurality of inner conductor layers including a plurality of first plane layers (P11, P12, P13) and a plurality of second plane layers (P2), wherein: each of the first plane layers (P11, P12, P13) is divided in a plurality of regions as viewed from the surface of the organic wiring structure; each of the second plane layers (P2) is placed in a different layer from the first plane layers and having an area larger than that of the first plane layer as viewed from the surface of the organic wiring structure ; and the test pads of the respective test pad groups are electrically connected to the connection pads via different regions of an outermost one (P11) of the first plane layers and by via holes of at least the outermost one of the resin insulating layers. a multilayer ceramic substrate having a plurality of ceramic layers and a plurality of conductor layers alternately stacked to each other and via conductors formed in the ceramic layers ; an organic wiring structure arranged on a main surface of the multilayer ceramic substrate ; a plurality of connection pads formed on a surface of the organic wiring structure for connection to capacitors ; and a plurality of test pad groups formed on the surface of the organic wiring structure , each of the test pad groups having a plurality of test pads for testing of any one of the semiconductor devices, the organic wiring structure having a plurality of insulating resin layers (43 to 49) and a plurality of inner conductor layers alternately stacked to each other such that one of the plurality of insulating resin layers is located outermost of the organic wiring structure , the plurality of inner conductor layers including a plurality of first plane layers (P11, P12, P13) and a plurality of second plane layers (P2), wherein: each of the first plane layers (P11, P12, P13) is divided in a plurality of regions as viewed from the surface of the organic wiring structure; each of the second plane layers (P2) is placed in a different layer from the first plane layers and having an area larger than that of the first plane layer as viewed from the surface of the organic wiring structure ; and the test pads of the respective test pad groups are electrically connected to the connection pads via different regions of an outermost one (P11) of the first plane layers and by via holes of at least the outermost one of the resin insulating layers. each of the first plane layers (P11, P12, P13) is divided in a plurality of regions as viewed from the surface of the organic wiring structure; each of the second plane layers (P2) is placed in a different layer from the first plane layers and having an area larger than that of the first plane layer as viewed from the surface of the organic wiring structure ; and the test pads of the respective test pad groups are electrically connected to the connection pads via different regions of an outermost one (P11) of the first plane layers and by via holes of at least the outermost one of the resin insulating layers. <EOS>