A processor , comprising: an instruction queue , configured to: cache a first to-be-processed load/store instruction and a second to-be-processed load/store instruction and obtain first dependency information between the first load/store instruction and the second load/store instruction, wherein the first dependency information is used to indicate that an address to be accessed by using the second load/store instruction depends on a value of a first destination register of the first load/store instruction, and the first destination register is configured to store a first load/store result of the first load/store instruction; and a load/store unit , configured to send a first load/store request to a memory controller in a computer system based on the first load/store instruction, wherein the load/store unit is further configured to send a second load/store request to the memory controller based on the second load/store instruction, wherein the second load/store request comprises the first dependency information, characterized in that the load/store unit is specifically configured to: set a first identifier for the first destination register when the first load/store instruction does not hit a cache of the computer system , wherein the first identifier is used to indicate that a value of the first destination register is speculative, wherein said first dependency information includes said first identifier for the first register, an add or subtract arithmetic symbol in front of said first identifier and offset information, and is arranged to be used by said memory controller to calculate an address to be accessed by the second load/store request. an instruction queue , configured to: cache a first to-be-processed load/store instruction and a second to-be-processed load/store instruction and obtain first dependency information between the first load/store instruction and the second load/store instruction, wherein the first dependency information is used to indicate that an address to be accessed by using the second load/store instruction depends on a value of a first destination register of the first load/store instruction, and the first destination register is configured to store a first load/store result of the first load/store instruction; and a load/store unit , configured to send a first load/store request to a memory controller in a computer system based on the first load/store instruction, wherein the load/store unit is further configured to send a second load/store request to the memory controller based on the second load/store instruction, wherein the second load/store request comprises the first dependency information, characterized in that the load/store unit is specifically configured to: set a first identifier for the first destination register when the first load/store instruction does not hit a cache of the computer system , wherein the first identifier is used to indicate that a value of the first destination register is speculative, wherein said first dependency information includes said first identifier for the first register, an add or subtract arithmetic symbol in front of said first identifier and offset information, and is arranged to be used by said memory controller to calculate an address to be accessed by the second load/store request. <EOS>