A semiconductor device comprising: an active pattern on a substrate ; a gate structure in an upper portion of the active pattern; a bit line structure on the active pattern, wherein the bit line structure includes a first conductive pattern , a diffusion barrier , a second conductive pattern and a capping pattern sequentially stacked on the substrate, wherein the first conductive pattern includes polysilicon doped with n-type impurities, and wherein the second conductive pattern includes a metal; a lower spacer structure extending on a lower portion of a sidewall of the bit line structure; an upper spacer structure extending on an upper portion of the sidewall of the bit line structure, wherein the upper spacer structure is on the lower spacer structure; a contact plug structure on the active pattern adjacent to the bit line structure; and a capacitor on the contact plug structure, wherein the lower spacer structure includes a first lower spacer and a second lower spacer sequentially stacked on the lower portion of the sidewall of the first conductive pattern of the bit line structure, the first lower spacer contacts the lower portion of the sidewall of the first conductive pattern of the bit line structure and does not include nitrogen, and the second lower spacer includes a material different from that of the first lower spacer, wherein the lower spacer structure further includes third and fourth 365 lower spacers sequentially stacked between the first and second lower spacers, wherein the first lower spacer includes an oxide, the second lower spacer includes a nitride, the third lower spacer includes a nitride, and the fourth lower spacer includes an oxide; and wherein a portion of the upper spacer structure contacts the upper portion of the sidewall of the bit line structure and includes a material different from that of the first lower spacer, and wherein the first lower spacer does not contact the upper portion of the sidewall of the bit line structure. an active pattern on a substrate ; a gate structure in an upper portion of the active pattern; a bit line structure on the active pattern, wherein the bit line structure includes a first conductive pattern , a diffusion barrier , a second conductive pattern and a capping pattern sequentially stacked on the substrate, wherein the first conductive pattern includes polysilicon doped with n-type impurities, and wherein the second conductive pattern includes a metal; a lower spacer structure extending on a lower portion of a sidewall of the bit line structure; an upper spacer structure extending on an upper portion of the sidewall of the bit line structure, wherein the upper spacer structure is on the lower spacer structure; a contact plug structure on the active pattern adjacent to the bit line structure; and a capacitor on the contact plug structure, wherein the lower spacer structure includes a first lower spacer and a second lower spacer sequentially stacked on the lower portion of the sidewall of the first conductive pattern of the bit line structure, the first lower spacer contacts the lower portion of the sidewall of the first conductive pattern of the bit line structure and does not include nitrogen, and the second lower spacer includes a material different from that of the first lower spacer, wherein the lower spacer structure further includes third and fourth 365 lower spacers sequentially stacked between the first and second lower spacers, wherein the first lower spacer includes an oxide, the second lower spacer includes a nitride, the third lower spacer includes a nitride, and the fourth lower spacer includes an oxide; and wherein a portion of the upper spacer structure contacts the upper portion of the sidewall of the bit line structure and includes a material different from that of the first lower spacer, and wherein the first lower spacer does not contact the upper portion of the sidewall of the bit line structure. <EOS>