A method for manufacturing a solar cell, comprising: providing a wafer , wherein the wafer comprises a substrate and a doped conducting material layer , the substrate comprises a first surface (F), a second surface (S), and a plurality of first side surfaces (C1), the first surface and the second surface are opposite to each other, the plurality of first side surfaces are adjacent to and between the first surface and the second surface, the first surface and a portion of the first side surface of the substrate comprise a textured structure , the doped conducting material layer is disposed on the first surface and the portion of the first side surface to cover the textured structure; forming a passivating contact material layer on each surface of the wafer; cutting the wafer formed with the passivating contact material layer along the thickness direction of the substrate to form a sub-wafer , so as to cut the doped conducting material layer into a doped conducting layer ; etching to remove the passivating contact material layer on a surface (F') of a first side of the sub-wafer and on each side surface of the sub-wafer, thereby forming a passivating contact layer on the sub-wafer, wherein the surface of the first side of the sub-wafer corresponds to the first surface of the substrate; and forming a first passivation layer on the doped conducting layer, wherein the first passivation layer covers the first surface and at least the portion of the first side surface, so as to cover at least the doped conducting layer, and the first passivation layer further covers at least a portion of a cut edge side surface (C2), the cut edge side surface is a side surface of the sub-wafer formed by cutting the wafer. providing a wafer , wherein the wafer comprises a substrate and a doped conducting material layer , the substrate comprises a first surface (F), a second surface (S), and a plurality of first side surfaces (C1), the first surface and the second surface are opposite to each other, the plurality of first side surfaces are adjacent to and between the first surface and the second surface, the first surface and a portion of the first side surface of the substrate comprise a textured structure , the doped conducting material layer is disposed on the first surface and the portion of the first side surface to cover the textured structure; forming a passivating contact material layer on each surface of the wafer; cutting the wafer formed with the passivating contact material layer along the thickness direction of the substrate to form a sub-wafer , so as to cut the doped conducting material layer into a doped conducting layer ; etching to remove the passivating contact material layer on a surface (F') of a first side of the sub-wafer and on each side surface of the sub-wafer, thereby forming a passivating contact layer on the sub-wafer, wherein the surface of the first side of the sub-wafer corresponds to the first surface of the substrate; and forming a first passivation layer on the doped conducting layer, wherein the first passivation layer covers the first surface and at least the portion of the first side surface, so as to cover at least the doped conducting layer, and the first passivation layer further covers at least a portion of a cut edge side surface (C2), the cut edge side surface is a side surface of the sub-wafer formed by cutting the wafer. <EOS>