A light emitting diode display apparatus, comprising: a pixel (P) disposed on a substrate and configured to display an image, wherein the pixel (P) includes: a first light emitting portion connected to a first gate line (GLa) disposed in a first direction, a data line (DL) disposed in a second direction perpendicular to the first direction, and a first driving power line (PL1) parallel to the data line (DL); a second light emitting portion connected to the data line (DL), the first driving power line (PL1), and a second gate line (GLb) parallel to the first gate line (GLa); and a common connection pattern (CCP) connecting the first light emitting portion and the second light emitting portion in common, wherein the first light emitting portion includes a first light emitting device (ED1) including a anode terminal (T1) and a cathode terminal (T2), wherein the second light emitting portion includes a second light emitting device (ED2) including a anode terminal (T1) and a cathode terminal (T2), wherein the cathode terminal (T2) of the first light emitting device (ED1) and the second light emitting device (ED2) are connected to the common connection pattern (CCP), characterised in that the pixel further includes a third light emitting portion connected between a second driving power line (PL2) and the common connection pattern (CPP), wherein at least a portion of the common connection pattern (CPP) overlaps with the second driving power line (PL2), wherein the third light emitting portion includes a third light emitting device (ED3) including an anode terminal (T1) and a cathode terminal (T2), and wherein the anode terminal (T1) of the third light emitting device (ED3) is connected to the common connection pattern (CCP). a first light emitting portion connected to a first gate line (GLa) disposed in a first direction, a data line (DL) disposed in a second direction perpendicular to the first direction, and a first driving power line (PL1) parallel to the data line (DL); a second light emitting portion connected to the data line (DL), the first driving power line (PL1), and a second gate line (GLb) parallel to the first gate line (GLa); and a common connection pattern (CCP) connecting the first light emitting portion and the second light emitting portion in common, wherein the first light emitting portion includes a first light emitting device (ED1) including a anode terminal (T1) and a cathode terminal (T2), wherein the second light emitting portion includes a second light emitting device (ED2) including a anode terminal (T1) and a cathode terminal (T2), wherein the cathode terminal (T2) of the first light emitting device (ED1) and the second light emitting device (ED2) are connected to the common connection pattern (CCP), characterised in that the pixel further includes a third light emitting portion connected between a second driving power line (PL2) and the common connection pattern (CPP), wherein at least a portion of the common connection pattern (CPP) overlaps with the second driving power line (PL2), wherein the third light emitting portion includes a third light emitting device (ED3) including an anode terminal (T1) and a cathode terminal (T2), and wherein the anode terminal (T1) of the third light emitting device (ED3) is connected to the common connection pattern (CCP). <EOS>