A semiconductor device, comprising: a logic cell on a substrate, the logic cell including a p-channel metal-oxide-semiconductor field-effect transistor, PMOSFET, region and an n-channel-metal-oxide-semiconductor field-effect transistor, NMOSFET, region; and a first metal layer on the logic cell, wherein the first metal layer includes, a first power line (MPR1) and a second power line (MPR2) that extend parallel to each other along a first direction (D2), and a first lower line, a second lower line (MI2), and a third lower line respectively on a first wiring track (MTR1), a second wiring track (MTR2), and a third wiring track (MTR5) that are defined between the first power line and the second power line, wherein the first, second, and third wiring tracks extend parallel to each other along the first direction, the first lower line includes a first line (MI1a) and a second line (MI1b) that are spaced apart from each other in the first direction at a first distance (DI1), the third lower line includes a third line (MI5a) and a fourth line (MI5b) that are spaced apart from each other in the first direction at a second distance(DI2) different from the first distance, the first line has a first end (EN1) that faces the second line, the third line has a second end (EN4) that faces the fourth line, and a curvature (R1) at the first end is the same as a curvature (R1) at the second end wherein: the second line has a third end (EN3) that is opposite to the first end, and a curvature (R2) at the third end is different from the curvature (R1) at the first end, and wherein the third end is convexly rounded. a logic cell on a substrate, the logic cell including a p-channel metal-oxide-semiconductor field-effect transistor, PMOSFET, region and an n-channel-metal-oxide-semiconductor field-effect transistor, NMOSFET, region; and a first metal layer on the logic cell, wherein the first metal layer includes, a first power line (MPR1) and a second power line (MPR2) that extend parallel to each other along a first direction (D2), and a first lower line, a second lower line (MI2), and a third lower line respectively on a first wiring track (MTR1), a second wiring track (MTR2), and a third wiring track (MTR5) that are defined between the first power line and the second power line, a first power line (MPR1) and a second power line (MPR2) that extend parallel to each other along a first direction (D2), and a first lower line, a second lower line (MI2), and a third lower line respectively on a first wiring track (MTR1), a second wiring track (MTR2), and a third wiring track (MTR5) that are defined between the first power line and the second power line, wherein the first, second, and third wiring tracks extend parallel to each other along the first direction, the first lower line includes a first line (MI1a) and a second line (MI1b) that are spaced apart from each other in the first direction at a first distance (DI1), the third lower line includes a third line (MI5a) and a fourth line (MI5b) that are spaced apart from each other in the first direction at a second distance(DI2) different from the first distance, the first line has a first end (EN1) that faces the second line, the third line has a second end (EN4) that faces the fourth line, and a curvature (R1) at the first end is the same as a curvature (R1) at the second end wherein: the second line has a third end (EN3) that is opposite to the first end, and a curvature (R2) at the third end is different from the curvature (R1) at the first end, and wherein the third end is convexly rounded. the second line has a third end (EN3) that is opposite to the first end, and a curvature (R2) at the third end is different from the curvature (R1) at the first end, and wherein the third end is convexly rounded. <EOS>