A radar data acquisition apparatus for use with sensor circuitry, including multiple radar sensors, to provide sensor data via multiple virtual channels and multiple data types using a Mobile Industry Processor Interface Camera Serial Interface 2, MIPI CSI2 interface, and to receive configuration data useful for configuring the multiple radar sensors, the apparatus comprising: a memory circuit having a plurality of buffers; a bus-interface circuit configured to operate in compliance with MIPI CSI2 and control bus interconnects for bus communications involving a radar signal transmitter and the memory circuit; and a radar signal receiving circuit configured to receive radar signals and including data acquisition path circuitry with multiple circuit paths configured to process streams of analog-to-digital converted data to support the sensor circuitry, and further including a receive-side master controller configured to: convey data, via the bus-interface circuit , to the plurality of buffers of the memory circuit for supporting the sensor data via the multiple virtual channels and the multiple data types; and generate a plurality of selectable-type transactions to be linked in selected ones of the plurality of buffers, in response to the data provided from the sensor circuitry and based on the sensor data being provided via different ones of the multiple virtual channels and of the multiple data types; wherein each of the plurality of selectable-type transactions is identifiable as either a coherent transaction or a non-coherent transaction and / or traceable transaction or a non-traceable transaction ; and further including a Silicon-on-chip integrated circuit, SOC IC, wherein at least the bus-interface circuit is part of the SoC IC, and wherein at least one of the of the plurality of selectable-type transactions is identifiable as a traceable transaction for debug tracing in the SOC IC. a memory circuit having a plurality of buffers; a bus-interface circuit configured to operate in compliance with MIPI CSI2 and control bus interconnects for bus communications involving a radar signal transmitter and the memory circuit; and a radar signal receiving circuit configured to receive radar signals and including data acquisition path circuitry with multiple circuit paths configured to process streams of analog-to-digital converted data to support the sensor circuitry, and further including a receive-side master controller configured to: convey data, via the bus-interface circuit , to the plurality of buffers of the memory circuit for supporting the sensor data via the multiple virtual channels and the multiple data types; and generate a plurality of selectable-type transactions to be linked in selected ones of the plurality of buffers, in response to the data provided from the sensor circuitry and based on the sensor data being provided via different ones of the multiple virtual channels and of the multiple data types; convey data, via the bus-interface circuit , to the plurality of buffers of the memory circuit for supporting the sensor data via the multiple virtual channels and the multiple data types; and generate a plurality of selectable-type transactions to be linked in selected ones of the plurality of buffers, in response to the data provided from the sensor circuitry and based on the sensor data being provided via different ones of the multiple virtual channels and of the multiple data types; wherein each of the plurality of selectable-type transactions is identifiable as either a coherent transaction or a non-coherent transaction and / or traceable transaction or a non-traceable transaction ; and further including a Silicon-on-chip integrated circuit, SOC IC, wherein at least the bus-interface circuit is part of the SoC IC, and wherein at least one of the of the plurality of selectable-type transactions is identifiable as a traceable transaction for debug tracing in the SOC IC. <EOS>