Apparatus for processing data comprising: memory access circuitry responsive to a memory access program instruction of a program to perform one or more memory accesses within a memory address space, wherein when said memory access program instruction is a contingent memory access program instruction, said one or more memory accesses include at least one contingent memory access and program flow to a next program instruction to be executed following said contingent memory access program instructions is independent of whether said at least one contingent memory access is permitted; and when said memory access program instruction is a non-contingent memory access program instruction, said one or more memory accesses are one or more non-contingent memory accesses and program flow to a next program instruction to be executed following said non-contingent memory access program instructions is dependent upon whether said one or more non-contingent memory accesses is permitted; and memory permission circuitry to control whether said memory access circuitry is permitted to perform said memory access, wherein in respect of said one or more contingent memory accesses, said memory permission circuitry is responsive to a contingent-access permission checking disable flag having a first value to disable said control by said memory permission circuitry and to said contingent-access permission checking disable flag having a second value to enable said control by said memory permission circuitry; and in respect of said one or more non contingent memory accesses, said control by said memory permission circuitry is independent of said contingent-access permission checking disable flag. memory access circuitry responsive to a memory access program instruction of a program to perform one or more memory accesses within a memory address space, wherein when said memory access program instruction is a contingent memory access program instruction, said one or more memory accesses include at least one contingent memory access and program flow to a next program instruction to be executed following said contingent memory access program instructions is independent of whether said at least one contingent memory access is permitted; and when said memory access program instruction is a non-contingent memory access program instruction, said one or more memory accesses are one or more non-contingent memory accesses and program flow to a next program instruction to be executed following said non-contingent memory access program instructions is dependent upon whether said one or more non-contingent memory accesses is permitted; and memory permission circuitry to control whether said memory access circuitry is permitted to perform said memory access, wherein in respect of said one or more contingent memory accesses, said memory permission circuitry is responsive to a contingent-access permission checking disable flag having a first value to disable said control by said memory permission circuitry and to said contingent-access permission checking disable flag having a second value to enable said control by said memory permission circuitry; and in respect of said one or more non contingent memory accesses, said control by said memory permission circuitry is independent of said contingent-access permission checking disable flag. in respect of said one or more contingent memory accesses, said memory permission circuitry is responsive to a contingent-access permission checking disable flag having a first value to disable said control by said memory permission circuitry and to said contingent-access permission checking disable flag having a second value to enable said control by said memory permission circuitry; and in respect of said one or more non contingent memory accesses, said control by said memory permission circuitry is independent of said contingent-access permission checking disable flag. <EOS>