A solid-state image pickup element including: an analog-to-digital conversion unit in which a plurality of analog-to-digital converters is arranged in a two-dimensional grid pattern, the plurality of analog-to-digital converters each being configured to convert an analog signal into a digital signal; a plurality of pixel circuits each configured to generate an analog signal and to supply the analog signal to the analog-to-digital conversion unit ; a correlated double sampling, CDS, circuit configured to generate a frame in which a predetermined number of lines each including a plurality of digital signals are arranged; a CDS frame memory configured to store a frame of reset levels obtained from the plurality of pixel circuits via the analog-to-digital conversion unit during initialization of the plurality of pixel circuits due to a reset signal, as a reset frame; a time delay integration, TDI, frame memory configured to retain a (K - 1)-th frame generated before a K-th frame, K being an integer; and a TDI circuit configured to perform time delay integration processing of adding the line having a predetermined address in the K-th frame and the line having an address at a certain distance from the predetermined address in the (K - 1)-th frame; wherein the CDS circuit is configured to generate the frame with correlated double sampling processing of acquiring, in order to obtain the plurality of digital signals, differences between the stored reset levels and signal levels corresponding to an amount of exposure; the CDS circuit is disposed on a predetermined circuit chip between the analog-to-digital conversion unit and the CDS frame memory ; the TDI circuit is disposed on the predetermined circuit chip between the CDS frame memory and the TDI frame memory ; the plurality of pixel circuits is disposed on a predetermined light-receiving chip ; and the TDI frame memory is disposed on the predetermined circuit chip layered to the light-receiving chip . an analog-to-digital conversion unit in which a plurality of analog-to-digital converters is arranged in a two-dimensional grid pattern, the plurality of analog-to-digital converters each being configured to convert an analog signal into a digital signal; a plurality of pixel circuits each configured to generate an analog signal and to supply the analog signal to the analog-to-digital conversion unit ; a correlated double sampling, CDS, circuit configured to generate a frame in which a predetermined number of lines each including a plurality of digital signals are arranged; a CDS frame memory configured to store a frame of reset levels obtained from the plurality of pixel circuits via the analog-to-digital conversion unit during initialization of the plurality of pixel circuits due to a reset signal, as a reset frame; a time delay integration, TDI, frame memory configured to retain a (K - 1)-th frame generated before a K-th frame, K being an integer; and a TDI circuit configured to perform time delay integration processing of adding the line having a predetermined address in the K-th frame and the line having an address at a certain distance from the predetermined address in the (K - 1)-th frame; wherein the CDS circuit is configured to generate the frame with correlated double sampling processing of acquiring, in order to obtain the plurality of digital signals, differences between the stored reset levels and signal levels corresponding to an amount of exposure; the CDS circuit is disposed on a predetermined circuit chip between the analog-to-digital conversion unit and the CDS frame memory ; the TDI circuit is disposed on the predetermined circuit chip between the CDS frame memory and the TDI frame memory ; the plurality of pixel circuits is disposed on a predetermined light-receiving chip ; and the TDI frame memory is disposed on the predetermined circuit chip layered to the light-receiving chip . <EOS>