A manufacturing method of a semiconductor structure, comprising: providing a stacked structure, wherein the stacked structure comprises a first chip and a second chip , the second chip is bonded onto the first chip in a face-to-face (F2F) manner, and the first chip and the second chip each comprise a substrate , a dielectric layer on the substrate and a metal layer in the dielectric layer (S1); forming a through silicon via (TSV) in the stacked structure, wherein the TSV comprises a first part and a second part communicating with the first part ; the first part penetrates through the substrate of the second chip ; a sidewall of the first part is a vertical sidewall; the second part penetrates through the metal layer of the second chip and at least a part of the metal layer in the first chip ; a sidewall of the second part is an inclined sidewall; and a bottom of the second part is narrower than a top of the second part (S2); forming an insulating layer on the sidewall of the first part (S3); and forming a conductive layer in the TSV , the conductive layer being electrically connected to the penetrated metal layer in each of the first chip and the second chip (S4); characterized in that , forming an insulating layer on the sidewall of the first part (S3) comprises: forming an insulating material layer on a sidewall and a bottom of the TSV ; and removing the insulating material layer on the sidewall and the bottom of the second part with dry etching, the remaining insulating material layer on the sidewall of the first part being the insulating layer . providing a stacked structure, wherein the stacked structure comprises a first chip and a second chip , the second chip is bonded onto the first chip in a face-to-face (F2F) manner, and the first chip and the second chip each comprise a substrate , a dielectric layer on the substrate and a metal layer in the dielectric layer (S1); forming a through silicon via (TSV) in the stacked structure, wherein the TSV comprises a first part and a second part communicating with the first part ; the first part penetrates through the substrate of the second chip ; a sidewall of the first part is a vertical sidewall; the second part penetrates through the metal layer of the second chip and at least a part of the metal layer in the first chip ; a sidewall of the second part is an inclined sidewall; and a bottom of the second part is narrower than a top of the second part (S2); forming an insulating layer on the sidewall of the first part (S3); and forming a conductive layer in the TSV , the conductive layer being electrically connected to the penetrated metal layer in each of the first chip and the second chip (S4); characterized in that , forming an insulating layer on the sidewall of the first part (S3) comprises: forming an insulating material layer on a sidewall and a bottom of the TSV ; and removing the insulating material layer on the sidewall and the bottom of the second part with dry etching, the remaining insulating material layer on the sidewall of the first part being the insulating layer . forming an insulating material layer on a sidewall and a bottom of the TSV ; and removing the insulating material layer on the sidewall and the bottom of the second part with dry etching, the remaining insulating material layer on the sidewall of the first part being the insulating layer . <EOS>