An electronic multi-output device comprising: a substrate including a pad and pins; a composite first chip having a first and a second transistor integrated so that the first terminals of the transistors are merged into a common terminal on one chip surface, and the patterned second and third terminals are on the opposite chip surface; the common first terminal attached to the substrate pad, and the second terminals connected by discrete first and second metal clips to respective substrate pins; a second chip with a third transistor having the first terminal on one chip surface, and the second and third terminals on the opposite chip surface, the second chip with its first terminal vertically attached to the first clip; and a third chip with a fourth transistor having the first terminal on one chip surface, and the second and third terminals on the opposite chip surface, the third chip with its first terminal vertically attached to the second clip; and the second and third chips having their second terminals connected by a common clip to a substrate pin, and wherein the first, second, third and fourth transistors are either: source-down MOS field-effect transistors , with the first terminals being the source terminals, the second terminals being the drain terminals, and the third terminals being the gate terminals of the respective transistors, or drain-down MOS field-effect transistors, transistors , with the first terminals being the drain terminals, the second terminals being the source terminals, and the third terminals being the gate terminals of the respective transistors. a substrate including a pad and pins; a composite first chip having a first and a second transistor integrated so that the first terminals of the transistors are merged into a common terminal on one chip surface, and the patterned second and third terminals are on the opposite chip surface; the common first terminal attached to the substrate pad, and the second terminals connected by discrete first and second metal clips to respective substrate pins; a second chip with a third transistor having the first terminal on one chip surface, and the second and third terminals on the opposite chip surface, the second chip with its first terminal vertically attached to the first clip; and a third chip with a fourth transistor having the first terminal on one chip surface, and the second and third terminals on the opposite chip surface, the third chip with its first terminal vertically attached to the second clip; and the second and third chips having their second terminals connected by a common clip to a substrate pin, and wherein the first, second, third and fourth transistors are either: source-down MOS field-effect transistors , with the first terminals being the source terminals, the second terminals being the drain terminals, and the third terminals being the gate terminals of the respective transistors, or drain-down MOS field-effect transistors, transistors , with the first terminals being the drain terminals, the second terminals being the source terminals, and the third terminals being the gate terminals of the respective transistors. source-down MOS field-effect transistors , with the first terminals being the source terminals, the second terminals being the drain terminals, and the third terminals being the gate terminals of the respective transistors, or drain-down MOS field-effect transistors, transistors , with the first terminals being the drain terminals, the second terminals being the source terminals, and the third terminals being the gate terminals of the respective transistors. <EOS>