A configurable channel system comprising: a plurality of control channels; and a plurality of processing platforms, each of the plurality of processing platforms being associated with one of the plurality of control channels and being configured to perform channel management and channel monitoring of the associated one of the plurality of control channels, each of the plurality of processing platforms comprising: a first microcontroller comprising a first core; and a second microcontroller comprising a second core, wherein the second microcontroller is dissimilar to the first microcontroller, wherein each microcontroller of the first and second microcontrollers loads a unique soft core, as the first and second cores respectively, from a corresponding flash memory at runtime and executes on the first core and the second core resident software in one of an active state and a monitor state, wherein the first core is configured in the active state to perform the channel management of the associated one of the plurality of control channels, wherein the second core is configured in the monitor state to perform the channel monitoring of the associated one of the plurality of control channels, and wherein if a failure occurs with the first core or the first microcontroller associated with the active state, the second core and the second microcontroller in the monitor state change to the active state and perform the channel management. a plurality of control channels; and a plurality of processing platforms, each of the plurality of processing platforms being associated with one of the plurality of control channels and being configured to perform channel management and channel monitoring of the associated one of the plurality of control channels, each of the plurality of processing platforms comprising: a first microcontroller comprising a first core; and a second microcontroller comprising a second core, wherein the second microcontroller is dissimilar to the first microcontroller, wherein each microcontroller of the first and second microcontrollers loads a unique soft core, as the first and second cores respectively, from a corresponding flash memory at runtime and executes on the first core and the second core resident software in one of an active state and a monitor state, wherein the first core is configured in the active state to perform the channel management of the associated one of the plurality of control channels, wherein the second core is configured in the monitor state to perform the channel monitoring of the associated one of the plurality of control channels, and wherein if a failure occurs with the first core or the first microcontroller associated with the active state, the second core and the second microcontroller in the monitor state change to the active state and perform the channel management. a first microcontroller comprising a first core; and a second microcontroller comprising a second core, wherein the second microcontroller is dissimilar to the first microcontroller, wherein each microcontroller of the first and second microcontrollers loads a unique soft core, as the first and second cores respectively, from a corresponding flash memory at runtime and executes on the first core and the second core resident software in one of an active state and a monitor state, wherein the first core is configured in the active state to perform the channel management of the associated one of the plurality of control channels, wherein the second core is configured in the monitor state to perform the channel monitoring of the associated one of the plurality of control channels, and wherein if a failure occurs with the first core or the first microcontroller associated with the active state, the second core and the second microcontroller in the monitor state change to the active state and perform the channel management. <EOS>