A method comprising: dithering an input frequency control word (FCW.I) of an integer all-digital phase locked loop, ADPLL, such that the ADPLL functions as a fractional-n ADPLL , wherein the ADPLL comprising: a delta-sigma modulator configured to dither the input frequency control word (FCW.I) with a fractional frequency control word signal (FCW.F), a reference phase generator 110) configured to integrate the dithered input frequency control word to generate a reference phase (PHI_REF), a phase detector configured to compare the reference phase (PHI_REF) with a feedback phase (PHV), a loop filter configured to receive the phase comparison result (PHE) from the phase detector and generate control signals (PVT,ACQ,TR), a digitally controlled oscillator, DCO, , configured to receive control signals (PVT,ACQ,TR) and generate an output signal (CLK_OUT), a feedback path including a counter and a time-to-digital converter, TDC, , configured to receive a delay-modulated frequency reference and the output signal (CLK_OUT), and generate the feedback phase (PHV), and a delay line configured to receive a frequency reference (FREF) and generate the delay-modulated frequency reference ; and generating a randomly modulated delay based on a uniformly distributed random number with a flat spectrum shaped by a high pass filter , wherein the random number has the triangular distribution spanning at least q to -q after shaping by the high pass filter; adding the randomly modulated delay having a triangular distribution to the frequency reference at an input of the fractional-n ADPLL, by modulating the delay of the delay line to generate the delay-modulated frequency reference provided to the input of the fractional-n ADPLL, wherein a range of the randomly modulated delay spans at least q to -q, wherein q is a quantization step of the time-to-digital converter of the ADPLL. dithering an input frequency control word (FCW.I) of an integer all-digital phase locked loop, ADPLL, such that the ADPLL functions as a fractional-n ADPLL , wherein the ADPLL comprising: a delta-sigma modulator configured to dither the input frequency control word (FCW.I) with a fractional frequency control word signal (FCW.F), a reference phase generator 110) configured to integrate the dithered input frequency control word to generate a reference phase (PHI_REF), a phase detector configured to compare the reference phase (PHI_REF) with a feedback phase (PHV), a loop filter configured to receive the phase comparison result (PHE) from the phase detector and generate control signals (PVT,ACQ,TR), a digitally controlled oscillator, DCO, , configured to receive control signals (PVT,ACQ,TR) and generate an output signal (CLK_OUT), a feedback path including a counter and a time-to-digital converter, TDC, , configured to receive a delay-modulated frequency reference and the output signal (CLK_OUT), and generate the feedback phase (PHV), and a delay line configured to receive a frequency reference (FREF) and generate the delay-modulated frequency reference ; and generating a randomly modulated delay based on a uniformly distributed random number with a flat spectrum shaped by a high pass filter , wherein the random number has the triangular distribution spanning at least q to -q after shaping by the high pass filter; adding the randomly modulated delay having a triangular distribution to the frequency reference at an input of the fractional-n ADPLL, by modulating the delay of the delay line to generate the delay-modulated frequency reference provided to the input of the fractional-n ADPLL, wherein a range of the randomly modulated delay spans at least q to -q, wherein q is a quantization step of the time-to-digital converter of the ADPLL. <EOS>