An electronic driver circuit for a Mach-Zehnder modulator, comprising: a first delay buffer implemented as a first complementary metal-oxide-semiconductor (CMOS) inverter having a first gate width, wherein the first CMOS inverter is configured to produce a first delayed electrical signal from a received electrical signal and output said first delayed electrical signal to a first output buffer and subsequently to a first segment of the modulator; and a second delay buffer following the first delay buffer , wherein the second delay buffer is implemented as a second CMOS inverter having a second gate width smaller than the first gate width of the first CMOS inverter, and wherein the second CMOS inverter is configured to produce a second delayed electrical signal from the first delayed electrical signal produced by the first CMOS inverter and output said second delayed electrical signal to a second output buffer and subsequently to a second segment of the modulator; wherein, the electronic driver circuit further comprises a third delay buffer following the second delay buffer , the third delay buffer implemented as a third CMOS inverter having a third gate width smaller than the second gate width of the second CMOS inverter, wherein the third CMOS inverter produces a third delayed electrical signal from the second delayed electrical signal produced by the second CMOS inverter and output said third delayed electrical signal to a third output buffer and subsequently to a third segment of the modulator; and wherein the first delayed electrical signal is provided to a first output buffer , the second delayed electrical signal is provided to a second output buffer , and the third delayed electrical signal is provided to a third output buffer ; and wherein the second delay buffer includes a first metal trace operably coupled to the second CMOS inverter and the third delay buffer includes a second metal trace operably coupled to the second CMOS inverter. a first delay buffer implemented as a first complementary metal-oxide-semiconductor (CMOS) inverter having a first gate width, wherein the first CMOS inverter is configured to produce a first delayed electrical signal from a received electrical signal and output said first delayed electrical signal to a first output buffer and subsequently to a first segment of the modulator; and a second delay buffer following the first delay buffer , wherein the second delay buffer is implemented as a second CMOS inverter having a second gate width smaller than the first gate width of the first CMOS inverter, and wherein the second CMOS inverter is configured to produce a second delayed electrical signal from the first delayed electrical signal produced by the first CMOS inverter and output said second delayed electrical signal to a second output buffer and subsequently to a second segment of the modulator; wherein, the electronic driver circuit further comprises a third delay buffer following the second delay buffer , the third delay buffer implemented as a third CMOS inverter having a third gate width smaller than the second gate width of the second CMOS inverter, wherein the third CMOS inverter produces a third delayed electrical signal from the second delayed electrical signal produced by the second CMOS inverter and output said third delayed electrical signal to a third output buffer and subsequently to a third segment of the modulator; and wherein the first delayed electrical signal is provided to a first output buffer , the second delayed electrical signal is provided to a second output buffer , and the third delayed electrical signal is provided to a third output buffer ; and wherein the second delay buffer includes a first metal trace operably coupled to the second CMOS inverter and the third delay buffer includes a second metal trace operably coupled to the second CMOS inverter. <EOS>