A pseudo dual-port memory , comprising: a single-port memory ; a multiplexer , configured to receive a first address and a second address, and output one of the first address and the second address to the single-port memory ; a timing control circuit , configured to sequentially generate: a first multiplexer control signal to control the multiplexer to output the first address to the single-port memory , a first sense amplifier control signal, a second multiplexer control signal to control the multiplexer to output the second address to the single-port memory , and a second sense amplifier control signal; and an output circuit , comprising: a first sense amplifier , a first latch coupled to the first sense amplifier , a second sense amplifier , and a second latch coupled to the second sense amplifier , wherein the first sense amplifier is configured to receive output data from a complementary bit line pair of the single-port memory to output a first output signal, and to amplify the first output signal according to the first sense amplifier control signal, the amplified first output signal being provided as first data to the first latch , wherein the first data stored in the first latch serves as a first reading result corresponding to the first address, the second sense amplifier is configured to receive the output data from the complementary bit line pair the single-port memory to output a second output signal, and to amplify the second output signal according to the second sense amplifier control signal, the amplified second output signal being provided as second data to the second latch , wherein the second data stored in the second latch serves as a second reading result corresponding to the second address, and wherein the pseudo dual-port memory is such that a period of provision of the second output signal and a period of provision of the amplified first output signal are partially overlapped. a single-port memory ; a multiplexer , configured to receive a first address and a second address, and output one of the first address and the second address to the single-port memory ; a timing control circuit , configured to sequentially generate: a first multiplexer control signal to control the multiplexer to output the first address to the single-port memory , a first sense amplifier control signal, a second multiplexer control signal to control the multiplexer to output the second address to the single-port memory , and a second sense amplifier control signal; and an output circuit , comprising: a first sense amplifier , a first latch coupled to the first sense amplifier , a second sense amplifier , and a second latch coupled to the second sense amplifier , wherein the first sense amplifier is configured to receive output data from a complementary bit line pair of the single-port memory to output a first output signal, and to amplify the first output signal according to the first sense amplifier control signal, the amplified first output signal being provided as first data to the first latch , wherein the first data stored in the first latch serves as a first reading result corresponding to the first address, the second sense amplifier is configured to receive the output data from the complementary bit line pair the single-port memory to output a second output signal, and to amplify the second output signal according to the second sense amplifier control signal, the amplified second output signal being provided as second data to the second latch , wherein the second data stored in the second latch serves as a second reading result corresponding to the second address, and wherein the pseudo dual-port memory is such that a period of provision of the second output signal and a period of provision of the amplified first output signal are partially overlapped. <EOS>