A method of fabricating a III-Nitride based High Electron Mobility Transistor , comprising: providing a substrate capable of supporting growth of III-nitride materials; providing a III-nitride barrier layer on a III-nitride channel layer on or above the substrate ; providing a group III-nitride semiconductor spacer layer directly on the barrier layer ; providing an opening in the group III-nitride semiconductor spacer layer for a gate contact ; depositing the gate contact in the opening such that the bottom of the gate contact is directly on the barrier layer ; providing a source contact in direct contact with the channel layer and a drain contact in direct contact with the channel layer , wherein the source and drain contacts make ohmic contact through the barrier layer such that an electric current flows between the source and drain electrodes via a two-dimensional electron gas induced at the heterointerface between the channel layer and barrier layer when the gate contact is biased at an appropriate level; creating at least one field plate on and in direct contact with the group III-nitride semiconductor spacer layer , wherein the field plate is a top of the gate contact and is formed from the gate material extending across the group III-nitride semiconductor spacer layer such that it extends a distance Lf from an edge of the gate contact towards the drain contact ; and covering the field plate and group III-nitride semiconductor spacer layer with a dielectric passivation layer so that the passivation layer is in direct contact with the field plate and group III-nitride semiconductor spacer layer ; and wherein the group III-nitride semiconductor spacer layer is in direct contact with the barrier layer across the entire length between the source contact and the gate and across the entire length between the drain contact and the gate . providing a substrate capable of supporting growth of III-nitride materials; providing a III-nitride barrier layer on a III-nitride channel layer on or above the substrate ; providing a group III-nitride semiconductor spacer layer directly on the barrier layer ; providing an opening in the group III-nitride semiconductor spacer layer for a gate contact ; depositing the gate contact in the opening such that the bottom of the gate contact is directly on the barrier layer ; providing a source contact in direct contact with the channel layer and a drain contact in direct contact with the channel layer , wherein the source and drain contacts make ohmic contact through the barrier layer such that an electric current flows between the source and drain electrodes via a two-dimensional electron gas induced at the heterointerface between the channel layer and barrier layer when the gate contact is biased at an appropriate level; creating at least one field plate on and in direct contact with the group III-nitride semiconductor spacer layer , wherein the field plate is a top of the gate contact and is formed from the gate material extending across the group III-nitride semiconductor spacer layer such that it extends a distance Lf from an edge of the gate contact towards the drain contact ; and covering the field plate and group III-nitride semiconductor spacer layer with a dielectric passivation layer so that the passivation layer is in direct contact with the field plate and group III-nitride semiconductor spacer layer ; and wherein the group III-nitride semiconductor spacer layer is in direct contact with the barrier layer across the entire length between the source contact and the gate and across the entire length between the drain contact and the gate . <EOS>