A semiconductor structure of two-transistor capacitor-less DRAM comprising: a substrate ; a semiconductor pillar located on the substrate and a gate pillar located on the semiconductor pillar , wherein the semiconductor pillar and the gate pillar both extend in a direction perpendicular to a plane of the substrate ; a first word line (WL1) extending in a first direction parallel to the plane of the substrate and surrounding the semiconductor pillar ; and a semiconductor layer located above the semiconductor pillar and at least surrounding a sidewall of the gate pillar ; wherein the semiconductor layer comprises a first sub-portion , a second sub-portion , and a third sub-portion connected to each other, and wherein the first sub-portion covers a top surface of the gate pillar , the second sub-portion covers the sidewall of the gate pillar , and the third sub-portion partially covers an upper surface of the substrate between adjacent gate pillars ; wherein the semiconductor structure further comprises: a second word line (WL2) extending in the first direction, surrounding an end, close to the semiconductor pillar , of the second sub-portion and covering an upper surface of the third sub-portion ; and a first bit line (BL1) and a second bit line (BL2) extending in a second direction parallel to the plane of the substrate and perpendicular to the first direction, wherein the first bit line (BL1) is located below the semiconductor pillar and electrically connected to a lower portion of the semiconductor pillar , while the second bit line (BL2) is located above the semiconductor layer and electrically connected to the first sub-portion . a substrate ; a semiconductor pillar located on the substrate and a gate pillar located on the semiconductor pillar , wherein the semiconductor pillar and the gate pillar both extend in a direction perpendicular to a plane of the substrate ; a first word line (WL1) extending in a first direction parallel to the plane of the substrate and surrounding the semiconductor pillar ; and a semiconductor layer located above the semiconductor pillar and at least surrounding a sidewall of the gate pillar ; wherein the semiconductor layer comprises a first sub-portion , a second sub-portion , and a third sub-portion connected to each other, and wherein the first sub-portion covers a top surface of the gate pillar , the second sub-portion covers the sidewall of the gate pillar , and the third sub-portion partially covers an upper surface of the substrate between adjacent gate pillars ; wherein the semiconductor structure further comprises: a second word line (WL2) extending in the first direction, surrounding an end, close to the semiconductor pillar , of the second sub-portion and covering an upper surface of the third sub-portion ; and a first bit line (BL1) and a second bit line (BL2) extending in a second direction parallel to the plane of the substrate and perpendicular to the first direction, wherein the first bit line (BL1) is located below the semiconductor pillar and electrically connected to a lower portion of the semiconductor pillar , while the second bit line (BL2) is located above the semiconductor layer and electrically connected to the first sub-portion . a second word line (WL2) extending in the first direction, surrounding an end, close to the semiconductor pillar , of the second sub-portion and covering an upper surface of the third sub-portion ; and a first bit line (BL1) and a second bit line (BL2) extending in a second direction parallel to the plane of the substrate and perpendicular to the first direction, wherein the first bit line (BL1) is located below the semiconductor pillar and electrically connected to a lower portion of the semiconductor pillar , while the second bit line (BL2) is located above the semiconductor layer and electrically connected to the first sub-portion . <EOS>