A method of synchronising the frequency of an oscillator in a slave device to the frequency of a master clock in a master device, the method including the steps of: a) receiving in the slave device a first message from said master device having a first time-stamp which is a time-stamp of said master clock indicating the precise time of sending of said first message and a first correction value which is the cumulative delay encountered by the first message during its passage from the master device to the slave device; b) extracting said time-stamp and said first correction value from said first message and recording a first value of a counter in the slave device at the time of receipt of the first message; c) receiving in the slave device a further message from said master device having a second time stamp which is a time-stamp of said master clock indicating the precise time of sending of said further message and a further correction value which is the cumulative delay encountered by the further message during its passage from the master device to the slave device; d) extracting said time-stamp and said further correction value from said further message and recording a further value of the counter in the slave device at the time of receipt of the further message; e) determining an error signal which is representative of the difference between the first and second time-stamps and the first and further values of the counter, the first and further values of the counter being adjusted by the difference between the first and further correction values and the error signal being described by the equation: e n = Δ ⁢ T n − Δ R ∗ n , where Δ T ( n ) is the difference between the first and further time-stamps, and Δ R ∗ ( n ) is the difference between the first and further values of the counter adjusted by the difference between the first and further correction values; and f) adjusting the frequency of the oscillator based on said error signal. a) receiving in the slave device a first message from said master device having a first time-stamp which is a time-stamp of said master clock indicating the precise time of sending of said first message and a first correction value which is the cumulative delay encountered by the first message during its passage from the master device to the slave device; b) extracting said time-stamp and said first correction value from said first message and recording a first value of a counter in the slave device at the time of receipt of the first message; c) receiving in the slave device a further message from said master device having a second time stamp which is a time-stamp of said master clock indicating the precise time of sending of said further message and a further correction value which is the cumulative delay encountered by the further message during its passage from the master device to the slave device; d) extracting said time-stamp and said further correction value from said further message and recording a further value of the counter in the slave device at the time of receipt of the further message; e) determining an error signal which is representative of the difference between the first and second time-stamps and the first and further values of the counter, the first and further values of the counter being adjusted by the difference between the first and further correction values and the error signal being described by the equation: e n = Δ ⁢ T n − Δ R ∗ n , where Δ T ( n ) is the difference between the first and further time-stamps, and Δ R ∗ ( n ) is the difference between the first and further values of the counter adjusted by the difference between the first and further correction values; and f) adjusting the frequency of the oscillator based on said error signal. <EOS>