A clock and data recovery, CDR, circuit , comprising: a first phase detector , configured to compare a phase of an input signal and a phase of a clock signal to generate a first phase detection result; a controller , coupled to the first phase detector , configured to generate a control signal according to the first phase detection result; and a phase filter , coupled to the controller , configured to receive the control signal and an auxiliary signal to generate the clock signal, wherein the auxiliary signal is generated according to the first phase detection result; and a second phase interpolator, coupled to the first phase detector and the phase filter , configured to use a phase control signal generated based on the first phase detection result to adjust a phase of a reference clock signal to generate a phase-shifted reference clock signal serving as the auxiliary signal; wherein the phase filter comprises: a first phase interpolator , configured to refer to the control signal to adjust the phase of the clock signal to generate a phase-shifted clock signal; a second phase detector or a phase and frequency detector, coupled to the first phase interpolator , configured to compare a phase of the phase-shifted clock signal and a phase of the auxiliary signal to generate a second phase detection result; a loop filter , coupled to the second phase detector , configured to receive the second phase detection result to generate a filtered signal; and an oscillator , coupled to the loop filter , configured to receive the filtered signal to generate the clock signal. a first phase detector , configured to compare a phase of an input signal and a phase of a clock signal to generate a first phase detection result; a controller , coupled to the first phase detector , configured to generate a control signal according to the first phase detection result; and a phase filter , coupled to the controller , configured to receive the control signal and an auxiliary signal to generate the clock signal, wherein the auxiliary signal is generated according to the first phase detection result; and a second phase interpolator, coupled to the first phase detector and the phase filter , configured to use a phase control signal generated based on the first phase detection result to adjust a phase of a reference clock signal to generate a phase-shifted reference clock signal serving as the auxiliary signal; wherein the phase filter comprises: a first phase interpolator , configured to refer to the control signal to adjust the phase of the clock signal to generate a phase-shifted clock signal; a second phase detector or a phase and frequency detector, coupled to the first phase interpolator , configured to compare a phase of the phase-shifted clock signal and a phase of the auxiliary signal to generate a second phase detection result; a loop filter , coupled to the second phase detector , configured to receive the second phase detection result to generate a filtered signal; and an oscillator , coupled to the loop filter , configured to receive the filtered signal to generate the clock signal. a first phase interpolator , configured to refer to the control signal to adjust the phase of the clock signal to generate a phase-shifted clock signal; a second phase detector or a phase and frequency detector, coupled to the first phase interpolator , configured to compare a phase of the phase-shifted clock signal and a phase of the auxiliary signal to generate a second phase detection result; a loop filter , coupled to the second phase detector , configured to receive the second phase detection result to generate a filtered signal; and an oscillator , coupled to the loop filter , configured to receive the filtered signal to generate the clock signal. <EOS>