An electronic system, comprising: a processor , and a flash memory device coupled to the processor , wherein the flash memory device includes: a flash memory array having a plurality of flash memory cells (401-410) with a silicon-on-insulator structure ; and control circuitry for decoding signals provided by the processor to control the data read, data write, and data erase, operations of the memory array ; each flash memory cell (401-410) of the flash memory array comprising: a drain region comprising a first doped material formed in the silicon-on-insulator ; a source region comprising the first doped material formed in the silicon-on-insulator ; a body region located between the drain region and the source region ; a control gate formed above and substantially between the drain and source regions ; and a charge storage region formed above and between the source region and the drain region , and located between said control gate and the body region ; characterised in that : each flash memory cell (401-410) has an extractor contact , of second doped material, coupled to the body region ; and the extractor contact is configured to receive a voltage to reverse bias the extractor contact during an erase operation of the flash memory cell (401-410), and to remove minority carriers from the body region when the extractor contact is reverse biased. a processor , and a flash memory device coupled to the processor , wherein the flash memory device includes: a flash memory array having a plurality of flash memory cells (401-410) with a silicon-on-insulator structure ; and control circuitry for decoding signals provided by the processor to control the data read, data write, and data erase, operations of the memory array ; a flash memory array having a plurality of flash memory cells (401-410) with a silicon-on-insulator structure ; and control circuitry for decoding signals provided by the processor to control the data read, data write, and data erase, operations of the memory array ; each flash memory cell (401-410) of the flash memory array comprising: a drain region comprising a first doped material formed in the silicon-on-insulator ; a source region comprising the first doped material formed in the silicon-on-insulator ; a body region located between the drain region and the source region ; a control gate formed above and substantially between the drain and source regions ; and a charge storage region formed above and between the source region and the drain region , and located between said control gate and the body region ; a drain region comprising a first doped material formed in the silicon-on-insulator ; a source region comprising the first doped material formed in the silicon-on-insulator ; a body region located between the drain region and the source region ; a control gate formed above and substantially between the drain and source regions ; and a charge storage region formed above and between the source region and the drain region , and located between said control gate and the body region ; characterised in that : each flash memory cell (401-410) has an extractor contact , of second doped material, coupled to the body region ; and the extractor contact is configured to receive a voltage to reverse bias the extractor contact during an erase operation of the flash memory cell (401-410), and to remove minority carriers from the body region when the extractor contact is reverse biased. each flash memory cell (401-410) has an extractor contact , of second doped material, coupled to the body region ; and the extractor contact is configured to receive a voltage to reverse bias the extractor contact during an erase operation of the flash memory cell (401-410), and to remove minority carriers from the body region when the extractor contact is reverse biased. <EOS>