A variable capacitor comprising: a capacitor bank comprising a plurality of capacitor segments connected in parallel; and a plurality of switch segments configured to control connection states of the plurality of capacitor segments by a control code (b0, b1, b2), wherein the capacitor bank provides a capacitance from a set of candidate capacitances in response to the connection states, wherein the capacitance provided by the capacitor bank is linearly changed on a log scale by increasing a value of the control code, wherein the set of candidate capacitances form a geometric series with a constant ratio between successive candidate capacitances, characterised in that the plurality of switch segments comprises seven switch segments and the control code comprises a 3-bit digital code, and wherein switching of a first switch segment is controlled by a first bit (b0) of the 3-bit digital code, switching of a second switch segment is controlled by a second bit (b1) of the 3-bit digital code, and switching of a fourth switch segment is controlled by a third bit (b2) of the 3-bit digital code, switching of a third switch segment is controlled by a result (b0b1) of an AND operation of the first bit and the second bit of the digital code, switching of a fifth switch segment is controlled by a result (b0b2) of an AND operation of the first bit and the third bit of the digital code, switching of a sixth switch segment is controlled by a result (b1b2) of an AND operation of the second bit and the third bit of the digital code, and switching of a seventh switch segment is controlled by a result (b0b1b2) of an AND operation of the first bit, the second bit, and the third bit of the digital code. a capacitor bank comprising a plurality of capacitor segments connected in parallel; and a plurality of switch segments configured to control connection states of the plurality of capacitor segments by a control code (b0, b1, b2), wherein the capacitor bank provides a capacitance from a set of candidate capacitances in response to the connection states, wherein the capacitance provided by the capacitor bank is linearly changed on a log scale by increasing a value of the control code, wherein the set of candidate capacitances form a geometric series with a constant ratio between successive candidate capacitances, characterised in that the plurality of switch segments comprises seven switch segments and the control code comprises a 3-bit digital code, and wherein switching of a first switch segment is controlled by a first bit (b0) of the 3-bit digital code, switching of a second switch segment is controlled by a second bit (b1) of the 3-bit digital code, and switching of a fourth switch segment is controlled by a third bit (b2) of the 3-bit digital code, switching of a third switch segment is controlled by a result (b0b1) of an AND operation of the first bit and the second bit of the digital code, switching of a fifth switch segment is controlled by a result (b0b2) of an AND operation of the first bit and the third bit of the digital code, switching of a sixth switch segment is controlled by a result (b1b2) of an AND operation of the second bit and the third bit of the digital code, and switching of a seventh switch segment is controlled by a result (b0b1b2) of an AND operation of the first bit, the second bit, and the third bit of the digital code. <EOS>