An apparatus, comprising: a multicore processor including a plurality of processing cores , a plurality of memory management units , and a plurality of peripheral access management units , each of the processing cores configured to operate exclusively with only one of the plurality of memory management units and each of the processing cores configured to operate with one or more of the plurality of peripheral access management units; a first shared cache and a second shared cache configured to be selectively shared by the plurality of processing cores ; and a separation kernel configured to execute within each of the plurality of processing cores , the separation kernel configured to enforce static virtual address mappings that form at least two isolated memory domains within a shared system memory , wherein the apparatus is configured to isolate at least two domains within a shared data storage including the shared system memory , to operate at least a first one of the plurality of processing cores with one of the at least two domains and to separately operate at least a second one of the plurality of processing cores with another of the at least two domains, by enforcing the static virtual address mappings such that the first processing core employs the first shared cache within the shared data storage and the second processing core employs the second shared cache within the shared data storage, and wherein two or more of the plurality of processing cores including the first processing core and excluding the second processing core are configured to employ the first shared cache , and wherein two or more of the plurality of processing cores including the second processing core and excluding the first processing core are configured to employ the second shared cache . a multicore processor including a plurality of processing cores , a plurality of memory management units , and a plurality of peripheral access management units , each of the processing cores configured to operate exclusively with only one of the plurality of memory management units and each of the processing cores configured to operate with one or more of the plurality of peripheral access management units; a first shared cache and a second shared cache configured to be selectively shared by the plurality of processing cores ; and a separation kernel configured to execute within each of the plurality of processing cores , the separation kernel configured to enforce static virtual address mappings that form at least two isolated memory domains within a shared system memory , wherein the apparatus is configured to isolate at least two domains within a shared data storage including the shared system memory , to operate at least a first one of the plurality of processing cores with one of the at least two domains and to separately operate at least a second one of the plurality of processing cores with another of the at least two domains, by enforcing the static virtual address mappings such that the first processing core employs the first shared cache within the shared data storage and the second processing core employs the second shared cache within the shared data storage, and wherein two or more of the plurality of processing cores including the first processing core and excluding the second processing core are configured to employ the first shared cache , and wherein two or more of the plurality of processing cores including the second processing core and excluding the first processing core are configured to employ the second shared cache . <EOS>