A method of forming a monolithic LED array precursor, the method comprising: (i) providing a substrate having a surface; (ii) forming a continuous first semiconductor layer on the surface of the substrate; (iii) selectively masking the first semiconductor layer, by depositing a masking layer , which comprises a plurality of apertures, on the first semiconductor layer; (iv) growing a second semiconductor layer on unmasked portions of the first semiconductor layer, through the apertures of the masking layer to form a plurality of columns each having a regular trapezoidal cross-section normal to the substrate with sloped sides and a substantially flat upper surface portion; (v) forming a third semiconductor layer covering the flat upper surface portion and the sloped sides of the second semiconductor layer, wherein the third semiconductor layer comprises one or more quantum well sub-layers and has sloped sides and a substantially flat upper surface portion conforming to the shape of the underlying second semiconductor layer; (vi) forming a fourth semiconductor layer covering the flat upper surface portion and the sloped sides of the third semiconductor layer, whereby the fourth semiconductor layer has sloped sides and a substantially flat upper surface portion conforming to the shape of the underlying third and second semiconductor layers; (vii) forming primary electrical contacts on the substantially flat upper surface portion of the fourth semiconductor layer; and wherein the first to fourth semiconductor layers comprise Group III-nitrides; (viii) forming electrically insulating, optically transparent spacers on the sloped sides of the fourth semiconductor layer, the spacers having an internal surface facing the sloped sides of the fourth semiconductor layer and an opposing external surface, wherein the external surface of the spacers has a parabolic profile; and (ix) depositing a reflecting, electrically conducting layer over the external surface of the spacers. (i) providing a substrate having a surface; (ii) forming a continuous first semiconductor layer on the surface of the substrate; (iii) selectively masking the first semiconductor layer, by depositing a masking layer , which comprises a plurality of apertures, on the first semiconductor layer; (iv) growing a second semiconductor layer on unmasked portions of the first semiconductor layer, through the apertures of the masking layer to form a plurality of columns each having a regular trapezoidal cross-section normal to the substrate with sloped sides and a substantially flat upper surface portion; (v) forming a third semiconductor layer covering the flat upper surface portion and the sloped sides of the second semiconductor layer, wherein the third semiconductor layer comprises one or more quantum well sub-layers and has sloped sides and a substantially flat upper surface portion conforming to the shape of the underlying second semiconductor layer; (vi) forming a fourth semiconductor layer covering the flat upper surface portion and the sloped sides of the third semiconductor layer, whereby the fourth semiconductor layer has sloped sides and a substantially flat upper surface portion conforming to the shape of the underlying third and second semiconductor layers; (vii) forming primary electrical contacts on the substantially flat upper surface portion of the fourth semiconductor layer; and wherein the first to fourth semiconductor layers comprise Group III-nitrides; (viii) forming electrically insulating, optically transparent spacers on the sloped sides of the fourth semiconductor layer, the spacers having an internal surface facing the sloped sides of the fourth semiconductor layer and an opposing external surface, wherein the external surface of the spacers has a parabolic profile; and (ix) depositing a reflecting, electrically conducting layer over the external surface of the spacers. <EOS>