A non-volatile storage device, comprising: a semiconductor channel (337; 699); a tunnel dielectric region (335; 698) adjacent to the semiconductor channel, wherein the tunnel dielectric region comprises a first tunnel dielectric layer (335; 712); a charge trapping region (CS0-CS7; 697) having a first charge trapping layer (341; 710) adjacent to the first tunnel dielectric layer, a second charge trapping layer (343; 708), and a third charge trapping layer (345; 706), wherein the second charge trapping layer is between the first and third charge trapping layers, wherein the second charge trapping layer has a smaller conduction band offset relative to the semiconductor channel than a conduction band offset of the first charge trapping layer relative to the semiconductor channel and has a smaller conduction band offset relative to the semiconductor channel than a conduction band offset of the third charge trapping layer relative to the semiconductor channel, wherein the first charge trapping layer has a smaller valence band offset relative to the semiconductor channel than a valence band offset of the first tunnel dielectric layer relative to the semiconductor channel, wherein the second charge trapping layer comprises a high-k material having a dielectric constant greater than 7.9; a control gate dielectric (333; 696); and a control gate (351; 605), wherein the control gate dielectric is between the control gate and the charge trapping region; wherein the high-k material in the second charge trapping layer is ZrZnON; and the first charge trapping layer material and the third charge trapping layer material each is lanthanum oxide. a semiconductor channel (337; 699); a tunnel dielectric region (335; 698) adjacent to the semiconductor channel, wherein the tunnel dielectric region comprises a first tunnel dielectric layer (335; 712); a charge trapping region (CS0-CS7; 697) having a first charge trapping layer (341; 710) adjacent to the first tunnel dielectric layer, a second charge trapping layer (343; 708), and a third charge trapping layer (345; 706), wherein the second charge trapping layer is between the first and third charge trapping layers, wherein the second charge trapping layer has a smaller conduction band offset relative to the semiconductor channel than a conduction band offset of the first charge trapping layer relative to the semiconductor channel and has a smaller conduction band offset relative to the semiconductor channel than a conduction band offset of the third charge trapping layer relative to the semiconductor channel, wherein the first charge trapping layer has a smaller valence band offset relative to the semiconductor channel than a valence band offset of the first tunnel dielectric layer relative to the semiconductor channel, wherein the second charge trapping layer comprises a high-k material having a dielectric constant greater than 7.9; a control gate dielectric (333; 696); and a control gate (351; 605), wherein the control gate dielectric is between the control gate and the charge trapping region; wherein the high-k material in the second charge trapping layer is ZrZnON; and the first charge trapping layer material and the third charge trapping layer material each is lanthanum oxide. <EOS>