A display panel (DP) comprising: a first display substrate (DS) including a first base substrate (SUB) including a display region (DA) and a non-display region (NDA), a circuit layer (DP-CL) disposed on the base substrate (SUB), and display elements (DP-OLED) disposed on the circuit layer (DP-CL) and overlapped with the display region (DA); a second display substrate (ES) disposed over the first display substrate (DS); and a sealing member bonding the first display substrate (DS) and the second display substrate (ES) and overlapping the non-display region in a normal direction (DR3) of a display surface (DP-IS); wherein the sealing member comprises: a frit sealing member (S-I) including an outer region (S-IO) and an inner region (S-II), with the inner region (S-II) disposed next to an inner side of the outer region (S-IO), so that the outer region (S-IO) is placed farther away from the display region (DA) than the inner region (S-II) when viewed in a plan view along the normal direction (DR3), and having a first crystallization temperature lower than a second crystallization temperature of the outer region (S-IO); characterized in that , the frit sealing member (S-I) includes Vanadium and Zinc and a ratio in weight of Vanadium (V) to Zinc (Zn) in the inner region (S-II) is lower than a ratio in weight of Vanadium (V) to Zinc (Zn) in the outer region (S-IO), and an organic sealing member (S-O) is disposed next to an inner side of the frit sealing member (S-I). a first display substrate (DS) including a first base substrate (SUB) including a display region (DA) and a non-display region (NDA), a circuit layer (DP-CL) disposed on the base substrate (SUB), and display elements (DP-OLED) disposed on the circuit layer (DP-CL) and overlapped with the display region (DA); a second display substrate (ES) disposed over the first display substrate (DS); and a sealing member bonding the first display substrate (DS) and the second display substrate (ES) and overlapping the non-display region in a normal direction (DR3) of a display surface (DP-IS); wherein the sealing member comprises: a frit sealing member (S-I) including an outer region (S-IO) and an inner region (S-II), with the inner region (S-II) disposed next to an inner side of the outer region (S-IO), so that the outer region (S-IO) is placed farther away from the display region (DA) than the inner region (S-II) when viewed in a plan view along the normal direction (DR3), and having a first crystallization temperature lower than a second crystallization temperature of the outer region (S-IO); characterized in that , the frit sealing member (S-I) includes Vanadium and Zinc and a ratio in weight of Vanadium (V) to Zinc (Zn) in the inner region (S-II) is lower than a ratio in weight of Vanadium (V) to Zinc (Zn) in the outer region (S-IO), and an organic sealing member (S-O) is disposed next to an inner side of the frit sealing member (S-I). a frit sealing member (S-I) including an outer region (S-IO) and an inner region (S-II), with the inner region (S-II) disposed next to an inner side of the outer region (S-IO), so that the outer region (S-IO) is placed farther away from the display region (DA) than the inner region (S-II) when viewed in a plan view along the normal direction (DR3), and having a first crystallization temperature lower than a second crystallization temperature of the outer region (S-IO); characterized in that , the frit sealing member (S-I) includes Vanadium and Zinc and a ratio in weight of Vanadium (V) to Zinc (Zn) in the inner region (S-II) is lower than a ratio in weight of Vanadium (V) to Zinc (Zn) in the outer region (S-IO), and an organic sealing member (S-O) is disposed next to an inner side of the frit sealing member (S-I). <EOS>