A processor , comprising: a central processing unit , a first bus coupled to the central processing unit; a side-band communication path coupled the central processing unit, the side-band communication path is separate from the first bus; a secure memory for storing a plurality of key entries, each key entry associated with a key identifier , including a thread owner field, and key data corresponding to a cryptography key; and a co-processor coupled to the central processing unit and the memory, wherein the co-processor is coupled to the central processing unit via the first bus and the side-band communication path, the co-processor comprising logic circuitry adapted to execute a plurality of operations comprising: receiving a command and a key identifier value from the central processing unit over the first bus, and receiving a thread identifier value for a current thread being executed by the central processing unit over the side-band communication path; retrieving a key entry in the secure memory corresponding to the received key identifier value and the thread owner associated with the key entry; and responsive to the thread identifier value corresponding to the thread owner field associated with the accessed key entry, executing a cryptography operation corresponding to the received command using the cryptography key data associated with the accessed key entry. a central processing unit , a first bus coupled to the central processing unit; a side-band communication path coupled the central processing unit, the side-band communication path is separate from the first bus; a secure memory for storing a plurality of key entries, each key entry associated with a key identifier , including a thread owner field, and key data corresponding to a cryptography key; and a co-processor coupled to the central processing unit and the memory, wherein the co-processor is coupled to the central processing unit via the first bus and the side-band communication path, the co-processor comprising logic circuitry adapted to execute a plurality of operations comprising: receiving a command and a key identifier value from the central processing unit over the first bus, and receiving a thread identifier value for a current thread being executed by the central processing unit over the side-band communication path; retrieving a key entry in the secure memory corresponding to the received key identifier value and the thread owner associated with the key entry; and responsive to the thread identifier value corresponding to the thread owner field associated with the accessed key entry, executing a cryptography operation corresponding to the received command using the cryptography key data associated with the accessed key entry. receiving a command and a key identifier value from the central processing unit over the first bus, and receiving a thread identifier value for a current thread being executed by the central processing unit over the side-band communication path; retrieving a key entry in the secure memory corresponding to the received key identifier value and the thread owner associated with the key entry; and responsive to the thread identifier value corresponding to the thread owner field associated with the accessed key entry, executing a cryptography operation corresponding to the received command using the cryptography key data associated with the accessed key entry. <EOS>