An apparatus comprising: a memory array having a plurality of memory cells ; memory access circuits coupled to the memory array and configured to perform write operations responsive to control signals; control logic coupled to the memory access circuits and configured to apply a set of write parameters based, at least in part, on a number of write operations performed by the memory access circuits and further configured to provide the control signals to the memory access circuits to perform the write operations on the plurality of memory cells according to the set of write parameters; and a parameter table defining a plurality of write cycle bins, wherein the parameter table includes a minimum number of write operations and a maximum number of write operations for each of the plurality of write cycle bins, wherein the control logic is configured to compare the number of write operations performed by the memory access circuits to the plurality of write cycle bins to select the set of write parameters, the apparatus being characterized in that a first range defining a first write cycle bin of the plurality of write cycle bins at least partially overlaps a second range defining a second write cycle bin of the plurality of write cycle bins, the minimum of the second range being higher than the minimum of the first range; and in that the control logic is further configured to select the second write cycle bin among the first and second write cycle bins once every block of memory cells in the memory array has been written a number of times equal or larger than the minimum of the second range. a memory array having a plurality of memory cells ; memory access circuits coupled to the memory array and configured to perform write operations responsive to control signals; control logic coupled to the memory access circuits and configured to apply a set of write parameters based, at least in part, on a number of write operations performed by the memory access circuits and further configured to provide the control signals to the memory access circuits to perform the write operations on the plurality of memory cells according to the set of write parameters; and a parameter table defining a plurality of write cycle bins, wherein the parameter table includes a minimum number of write operations and a maximum number of write operations for each of the plurality of write cycle bins, wherein the control logic is configured to compare the number of write operations performed by the memory access circuits to the plurality of write cycle bins to select the set of write parameters, the apparatus being characterized in that a first range defining a first write cycle bin of the plurality of write cycle bins at least partially overlaps a second range defining a second write cycle bin of the plurality of write cycle bins, the minimum of the second range being higher than the minimum of the first range; and in that the control logic is further configured to select the second write cycle bin among the first and second write cycle bins once every block of memory cells in the memory array has been written a number of times equal or larger than the minimum of the second range. <EOS>