A discrete time filter network with an input connection and an output connection comprising: a plurality of N history capacitors CHi (i=1-N), wherein N≥3, and wherein one of the plurality of history capacitors CHi is connected to the input connection and another one of the plurality of history capacitors CHi is connected to the output connection, at least one sampling capacitor CS which is coupled either parallel or antiparallel to one of the plurality of history capacitors CHi at a time to share electrical charge with positive and negative sign respectively, wherein the antiparallel connection provides a negative feedback path, and a switch network comprising a plurality of clock driven switches for making a predetermined sequential cyclical connection between the at least one sampling capacitor CS and the history capacitors CHi (i=1-N) at a predetermined cycling rate; characterized in that the discrete time filter network comprises a predefined number M of feedback paths, wherein M≥1, the location of which is identified with a predefined list L of M feedback location numbers wherein each location number Lj (j=1-M) ranges from 2 to N and defines the feedback path of the history capacitor Chi to the input, wherein i ranges from i=1 to Lj, and is associated with a sub-cycle j within a cycle, in accordance with the predetermined cycling rate, and that in each sub-cycle j (j=1-M), the at least one sampling capacitor CS is connected sequentially parallel to each history capacitor CHi wherein i ranges from i=1 to Lj, and that upon reaching and connecting to a history capacitor CHi, wherein i=Lj, the at least one sampling capacitor CS is subsequently flipped and connected back antiparallel so as to provide its charge with inverted polarity to the history capacitor CHi, wherein i=1. a plurality of N history capacitors CHi (i=1-N), wherein N≥3, and wherein one of the plurality of history capacitors CHi is connected to the input connection and another one of the plurality of history capacitors CHi is connected to the output connection, at least one sampling capacitor CS which is coupled either parallel or antiparallel to one of the plurality of history capacitors CHi at a time to share electrical charge with positive and negative sign respectively, wherein the antiparallel connection provides a negative feedback path, and a switch network comprising a plurality of clock driven switches for making a predetermined sequential cyclical connection between the at least one sampling capacitor CS and the history capacitors CHi (i=1-N) at a predetermined cycling rate; characterized in that the discrete time filter network comprises a predefined number M of feedback paths, wherein M≥1, the location of which is identified with a predefined list L of M feedback location numbers wherein each location number Lj (j=1-M) ranges from 2 to N and defines the feedback path of the history capacitor Chi to the input, wherein i ranges from i=1 to Lj, and is associated with a sub-cycle j within a cycle, in accordance with the predetermined cycling rate, and that in each sub-cycle j (j=1-M), the at least one sampling capacitor CS is connected sequentially parallel to each history capacitor CHi wherein i ranges from i=1 to Lj, and that upon reaching and connecting to a history capacitor CHi, wherein i=Lj, the at least one sampling capacitor CS is subsequently flipped and connected back antiparallel so as to provide its charge with inverted polarity to the history capacitor CHi, wherein i=1. <EOS>