An execution subsystem within a processing array of a general-purpose graphics processing unit, GPGPU, the execution subsystem including: multiple compute blocks (620A-620B, 1220A-1220N), each compute block including multiple processing clusters (214A-214N, 614A-614H) configured for parallel operation, wherein each of the multiple compute blocks (620A-620B, 1220A-1220N) is independently preemptable, an embedded microcontroller configured to schedule a workload to the multiple compute blocks (620A-620B, 1220A-1220N); and shared assets including hardware resources, wherein various execution resources within each compute block (620A-620B, 1220A-1220N) make use of the shared assets , characterized in that the embedded microcontroller is configured to execute firmware logic to perform scheduling operations for the multiple compute blocks (620A-620B, 1220A-1220N), and the embedded microcontroller is configured to avoid overly aggressive preemption by monitoring average page fault latency on a per-context basis, wherein the average page fault latency for a context is compared against a low-watermark threshold and a high-watermark threshold, and when the embedded microcontroller detects that the average page fault latency for the context is below the low-watermark threshold, the embedded microcontroller is configured to disable page fault based work group preemption or page fault based thread preemption for that context, and when the embedded microcontroller detects that the average page fault latency for the context is above the high-watermark threshold, the embedded microcontroller is configured to enable page fault based work group preemption or page fault based thread preemption for that context, wherein a compute block of the multiple compute blocks (620A-620B, 1220A-1220N) is transitioned into a preemption ready state once the number of page faults within the compute block exceeds a threshold. multiple compute blocks (620A-620B, 1220A-1220N), each compute block including multiple processing clusters (214A-214N, 614A-614H) configured for parallel operation, wherein each of the multiple compute blocks (620A-620B, 1220A-1220N) is independently preemptable, an embedded microcontroller configured to schedule a workload to the multiple compute blocks (620A-620B, 1220A-1220N); and shared assets including hardware resources, wherein various execution resources within each compute block (620A-620B, 1220A-1220N) make use of the shared assets , characterized in that the embedded microcontroller is configured to execute firmware logic to perform scheduling operations for the multiple compute blocks (620A-620B, 1220A-1220N), and the embedded microcontroller is configured to avoid overly aggressive preemption by monitoring average page fault latency on a per-context basis, wherein the average page fault latency for a context is compared against a low-watermark threshold and a high-watermark threshold, and when the embedded microcontroller detects that the average page fault latency for the context is below the low-watermark threshold, the embedded microcontroller is configured to disable page fault based work group preemption or page fault based thread preemption for that context, and when the embedded microcontroller detects that the average page fault latency for the context is above the high-watermark threshold, the embedded microcontroller is configured to enable page fault based work group preemption or page fault based thread preemption for that context, wherein a compute block of the multiple compute blocks (620A-620B, 1220A-1220N) is transitioned into a preemption ready state once the number of page faults within the compute block exceeds a threshold. <EOS>