A systolic array implemented in circuitry of an integrated circuit , comprising: a processing element array , comprising processing elements; one or more feeder circuits communicatively coupled to the processing element array , wherein each of the one or more feeder circuits comprises: a first section configured to receive data stored in memory external to the integrated circuit ; and a second section configured to send the received data to the processing element array , wherein data transferring from the memory to the processing element array is double buffered by the first section and the second section ; one or more drain circuits communicatively coupled to the processing element array , comprising one or more memory buffers configured to store data output by the processing element array ; and a first controller communicatively coupled to the one or more feeder circuits , wherein the first controller comprises: a read controller configured to enable reading the data stored in the memory external to the integrated circuit ; a valid check logic configured to perform valid check on the first section and the second section ; and a backpressure check logic configured to provide indication relating to backpressure from the one or more drain circuits to the read controller . a processing element array , comprising processing elements; one or more feeder circuits communicatively coupled to the processing element array , wherein each of the one or more feeder circuits comprises: a first section configured to receive data stored in memory external to the integrated circuit ; and a second section configured to send the received data to the processing element array , wherein data transferring from the memory to the processing element array is double buffered by the first section and the second section ; a first section configured to receive data stored in memory external to the integrated circuit ; and a second section configured to send the received data to the processing element array , wherein data transferring from the memory to the processing element array is double buffered by the first section and the second section ; one or more drain circuits communicatively coupled to the processing element array , comprising one or more memory buffers configured to store data output by the processing element array ; and a first controller communicatively coupled to the one or more feeder circuits , wherein the first controller comprises: a read controller configured to enable reading the data stored in the memory external to the integrated circuit ; a valid check logic configured to perform valid check on the first section and the second section ; and a backpressure check logic configured to provide indication relating to backpressure from the one or more drain circuits to the read controller . a read controller configured to enable reading the data stored in the memory external to the integrated circuit ; a valid check logic configured to perform valid check on the first section and the second section ; and a backpressure check logic configured to provide indication relating to backpressure from the one or more drain circuits to the read controller . <EOS>