A storage device comprising: a nonvolatile memory comprising memory blocks including a first memory block (BLK1) and a second memory block (BLK2); a buffer memory configured to apply a first read voltage having a first read level (Read Level 1) and a second read voltage having a second read level (Read Level 2) higher than the first read level (Read Level 1) to memory cells connected to a reference word line (Ref WL) for each of the memory blocks (BLK1, BLK2), and store a first ON cell count, hereinafter referred to as OCC1, indicating a number of memory cells turned ON by the first read voltage and a second ON cell count, hereinafter referred to as OCC2, indicating the number of memory cells turned ON by the second read voltage among the memory cells connected to the reference word line (Ref WL); and a controller configured to store the OCC1 for each of the memory blocks in a power loss protection, hereinafter referred to as PLP, area of the nonvolatile memory when a sudden power off occurs in the storage device , wherein the controller is further configured to: when successive writing of data to the first memory block (BLK1) is possible, select the first memory block (BLK1) as the PLP area and store the OCC1 for each of the memory blocks (BLK1, BLK2) in the PLP area when the sudden power off occurs while writing data to the first memory block (BLK1); and, when successive writing of data to the first memory block (BLK1) is not possible, select the second memory block (BLK2) as the PLP area and store the OCC1 for each of the memory blocks (BLK1, BLK2) in the PLP area, when the sudden power off occurs while writing data to the first memory block (BLK1). a nonvolatile memory comprising memory blocks including a first memory block (BLK1) and a second memory block (BLK2); a buffer memory configured to apply a first read voltage having a first read level (Read Level 1) and a second read voltage having a second read level (Read Level 2) higher than the first read level (Read Level 1) to memory cells connected to a reference word line (Ref WL) for each of the memory blocks (BLK1, BLK2), and store a first ON cell count, hereinafter referred to as OCC1, indicating a number of memory cells turned ON by the first read voltage and a second ON cell count, hereinafter referred to as OCC2, indicating the number of memory cells turned ON by the second read voltage among the memory cells connected to the reference word line (Ref WL); and a controller configured to store the OCC1 for each of the memory blocks in a power loss protection, hereinafter referred to as PLP, area of the nonvolatile memory when a sudden power off occurs in the storage device , wherein the controller is further configured to: when successive writing of data to the first memory block (BLK1) is possible, select the first memory block (BLK1) as the PLP area and store the OCC1 for each of the memory blocks (BLK1, BLK2) in the PLP area when the sudden power off occurs while writing data to the first memory block (BLK1); and, when successive writing of data to the first memory block (BLK1) is not possible, select the second memory block (BLK2) as the PLP area and store the OCC1 for each of the memory blocks (BLK1, BLK2) in the PLP area, when the sudden power off occurs while writing data to the first memory block (BLK1). when successive writing of data to the first memory block (BLK1) is possible, select the first memory block (BLK1) as the PLP area and store the OCC1 for each of the memory blocks (BLK1, BLK2) in the PLP area when the sudden power off occurs while writing data to the first memory block (BLK1); and, when successive writing of data to the first memory block (BLK1) is not possible, select the second memory block (BLK2) as the PLP area and store the OCC1 for each of the memory blocks (BLK1, BLK2) in the PLP area, when the sudden power off occurs while writing data to the first memory block (BLK1). <EOS>