A power conversion device, comprising: - a plurality of semiconductor elements (Q1, Q2, Q3, Q4) provided in parallel; - a gate drive unit configured to send a drive signal to each gate of the plurality of semiconductor elements (Q1, Q2, Q3, Q4); and - a gate voltage adjustment unit configured to act on the drive signal from the gate drive unit and to adjust a gate voltage of the semiconductor element (Q1, Q2, Q3, Q4), in order to balance currents in said plurality of parallel semiconductor elements, wherein: - the gate voltage adjustment unit is configured to superimpose an induction voltage generated on a basis of a difference between a magnetic flux due to a current flowing through one of the plurality of semiconductor elements (Q1, Q2, Q3, Q4) and a magnetic flux due to a current flowing through each of the other semiconductor elements (Q1, Q2, Q3, Q4), onto a gate voltage sent to at least one gate of the plurality of semiconductor elements (Q1, Q2, Q3, Q4), and characterized in that: - the gate voltage adjustment unit includes a plurality of coiled wiring patterns formed between the plurality of semiconductor elements (Q1, Q2, Q3, Q4) and the gate drive unit , - the gate voltage adjustment unit is provided between wirings routed from one semiconductor element (Q1, Q2, Q3, Q4) and each of the other semiconductor elements (Q1, Q2, Q3, Q4) among the plurality of semiconductor elements (Q1, Q2, Q3, Q4), the wirings serving as a main current path, and - the plurality of coiled wiring patterns is provided adjacent to wirings serving as a main current path routed from the plurality of semiconductor elements (Q1, Q2, Q3, Q4). - a plurality of semiconductor elements (Q1, Q2, Q3, Q4) provided in parallel; - a gate drive unit configured to send a drive signal to each gate of the plurality of semiconductor elements (Q1, Q2, Q3, Q4); and - a gate voltage adjustment unit configured to act on the drive signal from the gate drive unit and to adjust a gate voltage of the semiconductor element (Q1, Q2, Q3, Q4), in order to balance currents in said plurality of parallel semiconductor elements, - the gate voltage adjustment unit is configured to superimpose an induction voltage generated on a basis of a difference between a magnetic flux due to a current flowing through one of the plurality of semiconductor elements (Q1, Q2, Q3, Q4) and a magnetic flux due to a current flowing through each of the other semiconductor elements (Q1, Q2, Q3, Q4), onto a gate voltage sent to at least one gate of the plurality of semiconductor elements (Q1, Q2, Q3, Q4), and - the gate voltage adjustment unit includes a plurality of coiled wiring patterns formed between the plurality of semiconductor elements (Q1, Q2, Q3, Q4) and the gate drive unit , - the gate voltage adjustment unit is provided between wirings routed from one semiconductor element (Q1, Q2, Q3, Q4) and each of the other semiconductor elements (Q1, Q2, Q3, Q4) among the plurality of semiconductor elements (Q1, Q2, Q3, Q4), the wirings serving as a main current path, and - the plurality of coiled wiring patterns is provided adjacent to wirings serving as a main current path routed from the plurality of semiconductor elements (Q1, Q2, Q3, Q4). <EOS>