A multi-chip package, comprising: an interconnect bridge having a first contact pad and a second contact pad thereon, the interconnect bridge comprising a silicon die , wherein the interconnect bridge is mounted on a conductive layer ; a first dielectric layer (351-2), the first dielectric layer (351-2) laterally adjacent the interconnect bridge , and the first dielectric layer (351-2) laterally adjacent and in contact with the conductive layer ; a second dielectric layer (351-3) on the first dielectric layer (351-2) and on the interconnect bridge , the second dielectric layer (351-3) over the conductive layer ; a first via in the second dielectric layer (351-3), the first via coupled to the first contact pad ; a second via in the second dielectric layer (351-3), the second via coupled to the second contact pad ; a third via in the second dielectric layer (351-3), the third via coupled to a via in the first dielectric layer (351-2); a third dielectric layer (351-4) on the second dielectric layer (351-3), the third dielectric layer (351-4) over the interconnect bridge and over the conductive layer ; a first conductive trace in the third dielectric layer (351-4), the first conductive trace coupled to the first via; a second conductive trace in the third dielectric layer (351-4), the second conductive trace coupled to the second via; a third conductive trace in the third dielectric layer (351-4), the third conductive trace coupled to the third via; a first die over the third dielectric layer (351-4), the first die over the interconnect bridge and over the conductive layer , and the first die coupled to the first conductive trace and to the second conductive trace; and a second die over the interconnect bridge , the second die coupled to the first die by the interconnect bridge . an interconnect bridge having a first contact pad and a second contact pad thereon, the interconnect bridge comprising a silicon die , wherein the interconnect bridge is mounted on a conductive layer ; a first dielectric layer (351-2), the first dielectric layer (351-2) laterally adjacent the interconnect bridge , and the first dielectric layer (351-2) laterally adjacent and in contact with the conductive layer ; a second dielectric layer (351-3) on the first dielectric layer (351-2) and on the interconnect bridge , the second dielectric layer (351-3) over the conductive layer ; a first via in the second dielectric layer (351-3), the first via coupled to the first contact pad ; a second via in the second dielectric layer (351-3), the second via coupled to the second contact pad ; a third via in the second dielectric layer (351-3), the third via coupled to a via in the first dielectric layer (351-2); a third dielectric layer (351-4) on the second dielectric layer (351-3), the third dielectric layer (351-4) over the interconnect bridge and over the conductive layer ; a first conductive trace in the third dielectric layer (351-4), the first conductive trace coupled to the first via; a second conductive trace in the third dielectric layer (351-4), the second conductive trace coupled to the second via; a third conductive trace in the third dielectric layer (351-4), the third conductive trace coupled to the third via; a first die over the third dielectric layer (351-4), the first die over the interconnect bridge and over the conductive layer , and the first die coupled to the first conductive trace and to the second conductive trace; and a second die over the interconnect bridge , the second die coupled to the first die by the interconnect bridge . <EOS>