A non-volatile memory device including memory blocks, each of the memory blocks including a plurality of cell strings connected in parallel between a bitline and a common source line, each of the cell strings comprising a plurality of memory cells respectively connected with a plurality of word lines and at least a first ground selection transistor connected with a first ground selection line and a second ground selection transistor connected with a second ground selection line ; wherein a plurality of first ground selection transistors connected with the first ground selection line is programmed to have a first threshold voltage; a plurality of second ground selection transistors connected with the second ground selection line is programmed to have a second threshold voltage which differs from the first threshold voltage; and a control circuit configured to: control an erase operation (S630, S640) to be performed on each of at least one first ground selection transistor of the plurality of first ground selection transistors based on a threshold voltage of each of the at least one first ground selection transistor being greater than a predetermined first criterion; and control a threshold voltage of each of the plurality of second ground selection transistors to be compared (S650) with a predetermined second criterion based on the erase operation on the at least one first ground selection transistor being completed. a plurality of memory cells respectively connected with a plurality of word lines and at least a first ground selection transistor connected with a first ground selection line and a second ground selection transistor connected with a second ground selection line ; wherein a plurality of first ground selection transistors connected with the first ground selection line is programmed to have a first threshold voltage; a plurality of second ground selection transistors connected with the second ground selection line is programmed to have a second threshold voltage which differs from the first threshold voltage; and a control circuit configured to: control an erase operation (S630, S640) to be performed on each of at least one first ground selection transistor of the plurality of first ground selection transistors based on a threshold voltage of each of the at least one first ground selection transistor being greater than a predetermined first criterion; and control a threshold voltage of each of the plurality of second ground selection transistors to be compared (S650) with a predetermined second criterion based on the erase operation on the at least one first ground selection transistor being completed. control an erase operation (S630, S640) to be performed on each of at least one first ground selection transistor of the plurality of first ground selection transistors based on a threshold voltage of each of the at least one first ground selection transistor being greater than a predetermined first criterion; and control a threshold voltage of each of the plurality of second ground selection transistors to be compared (S650) with a predetermined second criterion based on the erase operation on the at least one first ground selection transistor being completed. <EOS>