A display panel comprising: a plurality of subpixels (SP) arrayed as a matrix; a plurality of data lines (DL) and a plurality of gate lines (GL) for driving the plurality of subpixels; a plurality of phototransistors (PHT) respectively comprising a gate electrode (PG) to which a photo-control signal (Vsto) is applied, a first electrode (PE1) to which a photo-driving signal (Vdrv) is applied, and a second electrode (PE2) serving as a signal output node outputting a signal in response to illumination light; and a plurality of photo-driving lines (PDL) and a plurality of photo-control lines (PCL) through which the photo-driving signal (Vdrv) and the photo-control signal (Vsto) are transferred to the plurality of phototransistors (PHT), a first subpixel row (SPR1), a second subpixel row (SPR2), a third subpixel row (SPR3), and a fourth subpixel row (SPR4), sequentially arrayed and respectively comprising subpixels among the plurality of subpixels (SP), wherein the plurality of phototransistors (PHT) include a first phototransistor (PHT1) and a second phototransistor (PHT2) disposed between the first subpixel row (SPR1) and the second subpixel row (SPR2), a first photo-driving line (PDL1) among the plurality of photo-driving lines (PDL) and a first photo-control line (PCL1) among the plurality of photo-control lines (PCL) are disposed between the first subpixel row (SPR1) and the second subpixel row (SPR2), the first photo-driving line (PDL1) allowing the photo-driving signal (Vdrv) to be transferred to the first electrode (PE1) of each of the first phototransistor (PHT1) and the second phototransistor (PHT2) therethrough, the first photo-control line (PCL1) allowing the photo-control signal (Vsto) to be transferred to the gate electrode (PG) of each of the first phototransistor (PHT1) and the second phototransistor (PHT2) therethrough. a plurality of subpixels (SP) arrayed as a matrix; a plurality of data lines (DL) and a plurality of gate lines (GL) for driving the plurality of subpixels; a plurality of phototransistors (PHT) respectively comprising a gate electrode (PG) to which a photo-control signal (Vsto) is applied, a first electrode (PE1) to which a photo-driving signal (Vdrv) is applied, and a second electrode (PE2) serving as a signal output node outputting a signal in response to illumination light; and a plurality of photo-driving lines (PDL) and a plurality of photo-control lines (PCL) through which the photo-driving signal (Vdrv) and the photo-control signal (Vsto) are transferred to the plurality of phototransistors (PHT), a first subpixel row (SPR1), a second subpixel row (SPR2), a third subpixel row (SPR3), and a fourth subpixel row (SPR4), sequentially arrayed and respectively comprising subpixels among the plurality of subpixels (SP), wherein the plurality of phototransistors (PHT) include a first phototransistor (PHT1) and a second phototransistor (PHT2) disposed between the first subpixel row (SPR1) and the second subpixel row (SPR2), a first photo-driving line (PDL1) among the plurality of photo-driving lines (PDL) and a first photo-control line (PCL1) among the plurality of photo-control lines (PCL) are disposed between the first subpixel row (SPR1) and the second subpixel row (SPR2), the first photo-driving line (PDL1) allowing the photo-driving signal (Vdrv) to be transferred to the first electrode (PE1) of each of the first phototransistor (PHT1) and the second phototransistor (PHT2) therethrough, the first photo-control line (PCL1) allowing the photo-control signal (Vsto) to be transferred to the gate electrode (PG) of each of the first phototransistor (PHT1) and the second phototransistor (PHT2) therethrough. <EOS>