A sensor configured to provide a digital output signal (S O ), the sensor comprising: a digital detector , configured to detect a physical quantity and generate a conditioned digital signal (S D ) indicative of the detected physical quantity; and a rate modification stage , configured to receive the conditioned digital signal and a group of parameters (K), the group of parameters comprising an interpolation factor (I 1 ) and a downsampling factor (D 1 , M), and to provide the digital output signal, wherein the rate modification stage comprises an interpolator and a decimation element , the interpolator being configured to receive and upsample the conditioned digital signal based on the interpolation factor and to provide an interpolated signal (S D,int ), and the decimation element being configured to downsample the interpolated signal based on the downsampling factor, thereby generating the digital output signal, wherein the decimation element comprises a first decimator including a filtering stage , a downsampling stage and a gain stage ; the filtering stage comprising a low-pass filter having a respective cut-off frequency (f c ) and being configured to receive the interpolated signal (S D,int ) and generate a filtered signal (F); the downsampling stage being configured to downsample the filtered signal using a first decimation factor (D 1 ) and to generate a downsampled signal (D S ) having a DC component; and the gain stage being configured to amplify or attenuate the DC component of the downsampled signal by a gain value (G), wherein the cut-off frequency of the filtering stage and the gain value of the gain stage are a function of the first decimation factor (D 1 ). a digital detector , configured to detect a physical quantity and generate a conditioned digital signal (S D ) indicative of the detected physical quantity; and a rate modification stage , configured to receive the conditioned digital signal and a group of parameters (K), the group of parameters comprising an interpolation factor (I 1 ) and a downsampling factor (D 1 , M), and to provide the digital output signal, wherein the rate modification stage comprises an interpolator and a decimation element , the interpolator being configured to receive and upsample the conditioned digital signal based on the interpolation factor and to provide an interpolated signal (S D,int ), and the decimation element being configured to downsample the interpolated signal based on the downsampling factor, thereby generating the digital output signal, wherein the decimation element comprises a first decimator including a filtering stage , a downsampling stage and a gain stage ; the filtering stage comprising a low-pass filter having a respective cut-off frequency (f c ) and being configured to receive the interpolated signal (S D,int ) and generate a filtered signal (F); the downsampling stage being configured to downsample the filtered signal using a first decimation factor (D 1 ) and to generate a downsampled signal (D S ) having a DC component; and the gain stage being configured to amplify or attenuate the DC component of the downsampled signal by a gain value (G), wherein the cut-off frequency of the filtering stage and the gain value of the gain stage are a function of the first decimation factor (D 1 ). <EOS>