A switch for routing a packet from an input port of said switch to an output port of said switch, said switch comprising: a plurality of said input ports ; a plurality of said output ports ; a plurality of routing modules , each of said routing modules associated with one of said input ports ; and said routing modules comprising: one or more memory modules to store a plurality of routing tables to store a plurality of entries, each of said entries to store a plurality of output port identifiers; a table address generation module to select an entry from each of said routing tables, said entry selection based in part on a first subset of bits of a Destination Location ID, DLID, associated with said packet; and said table address generation module further to select one or more output ports from each of said selected entries, said output port selection based in part on a second subset of bits of said DLID, wherein the routing modules further comprise an output port down-select module to reduce the number of said selected output ports based on selected data values of a header of said packet and further based on status bits of said selected output ports , wherein the selected data values of the header include the virtual lane of the packet. a plurality of said input ports ; a plurality of said output ports ; a plurality of routing modules , each of said routing modules associated with one of said input ports ; and said routing modules comprising: one or more memory modules to store a plurality of routing tables to store a plurality of entries, each of said entries to store a plurality of output port identifiers; a table address generation module to select an entry from each of said routing tables, said entry selection based in part on a first subset of bits of a Destination Location ID, DLID, associated with said packet; and said table address generation module further to select one or more output ports from each of said selected entries, said output port selection based in part on a second subset of bits of said DLID, wherein the routing modules further comprise an output port down-select module to reduce the number of said selected output ports based on selected data values of a header of said packet and further based on status bits of said selected output ports , wherein the selected data values of the header include the virtual lane of the packet. one or more memory modules to store a plurality of routing tables to store a plurality of entries, each of said entries to store a plurality of output port identifiers; a table address generation module to select an entry from each of said routing tables, said entry selection based in part on a first subset of bits of a Destination Location ID, DLID, associated with said packet; and said table address generation module further to select one or more output ports from each of said selected entries, said output port selection based in part on a second subset of bits of said DLID, wherein the routing modules further comprise an output port down-select module to reduce the number of said selected output ports based on selected data values of a header of said packet and further based on status bits of said selected output ports , wherein the selected data values of the header include the virtual lane of the packet. <EOS>