An operating method of a processor supporting a coarse-grained array mode and a very long instruction word, VLIW, mode, wherein the processor comprises: a core having a plurality of functional units; a scratch pad memory including a shared section, being shared between the plurality of functional units; a cache memory configured to cache a variable used in the VLIW mode from a dynamic random access memory, DRAM, including a local/stack section ; and an address decoding unit ; the method comprising: separately disposing, by a compiler, a global variable in a respective predetermined address section for a data section that is one of the shared section or the local/stack section in response to a respective code declaration designating the shared section or the local/stack section as the data section in which the global variable is to be located; receiving , by the address decoding unit , a memory access request with respect to a variable access from the core of the processor; and determining , by the address decoding unit , which of the shared section and the local/stack section is associated with the memory access request received from the core, based on a memory address corresponding to the memory access request received from the core, wherein: the global variable used in the coarse-grained array mode is disposed in a first memory address section set to correspond to the shared section in response to the code declaration designating the shared section as the data section in which the global variable is to be located, and the global variable used in the VLIW mode is disposed in a second memory address section set to correspond to the local/stack section in response to the code declaration designating the local/stack section as the data section in which the global variable is to be located. a core having a plurality of functional units; a scratch pad memory including a shared section, being shared between the plurality of functional units; a cache memory configured to cache a variable used in the VLIW mode from a dynamic random access memory, DRAM, including a local/stack section ; and an address decoding unit ; separately disposing, by a compiler, a global variable in a respective predetermined address section for a data section that is one of the shared section or the local/stack section in response to a respective code declaration designating the shared section or the local/stack section as the data section in which the global variable is to be located; receiving , by the address decoding unit , a memory access request with respect to a variable access from the core of the processor; and determining , by the address decoding unit , which of the shared section and the local/stack section is associated with the memory access request received from the core, based on a memory address corresponding to the memory access request received from the core, the global variable used in the coarse-grained array mode is disposed in a first memory address section set to correspond to the shared section in response to the code declaration designating the shared section as the data section in which the global variable is to be located, and the global variable used in the VLIW mode is disposed in a second memory address section set to correspond to the local/stack section in response to the code declaration designating the local/stack section as the data section in which the global variable is to be located. <EOS>