A method for making a semiconductor device (100, 100', 100") comprising: forming a plurality of fins on a substrate by forming a plurality of spaced apart lower semiconductor fin portions (105, 105', 105") extending vertically upward from the substrate, forming at least one respective superlattice punch-through stop layer (125, 125', 125") on each of the lower semiconductor fin portions, each superlattice punch-through stop layer including a plurality of stacked groups of layers (45a-45n, 45a'-45n'), each group of layers of the superlattice punch-through stop layer comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions, and forming a respective upper semiconductor fin portion (106, 106', 106") on each of the at least one superlattice punch-through stop layers and extending vertically upward therefrom; forming source and drain regions at opposing ends of the plurality of fins ; and forming a gate overlying the plurality of fins ; characterized in that forming the at least one respective superlattice punch-through stop layer comprises forming a respective plurality of vertically stacked superlattice punch-through stop layers on each of the lower semiconductor fin portions with a respective bulk semiconductor layer between each of the superlattice punch-through stop layers, the bulk semiconductor layers having opposite conductivity types defining an embedded junction therebetween. forming a plurality of fins on a substrate by forming a plurality of spaced apart lower semiconductor fin portions (105, 105', 105") extending vertically upward from the substrate, forming at least one respective superlattice punch-through stop layer (125, 125', 125") on each of the lower semiconductor fin portions, each superlattice punch-through stop layer including a plurality of stacked groups of layers (45a-45n, 45a'-45n'), each group of layers of the superlattice punch-through stop layer comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions, and forming a respective upper semiconductor fin portion (106, 106', 106") on each of the at least one superlattice punch-through stop layers and extending vertically upward therefrom; forming a plurality of spaced apart lower semiconductor fin portions (105, 105', 105") extending vertically upward from the substrate, forming at least one respective superlattice punch-through stop layer (125, 125', 125") on each of the lower semiconductor fin portions, each superlattice punch-through stop layer including a plurality of stacked groups of layers (45a-45n, 45a'-45n'), each group of layers of the superlattice punch-through stop layer comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions, and forming a respective upper semiconductor fin portion (106, 106', 106") on each of the at least one superlattice punch-through stop layers and extending vertically upward therefrom; forming source and drain regions at opposing ends of the plurality of fins ; and forming a gate overlying the plurality of fins ; characterized in that forming the at least one respective superlattice punch-through stop layer comprises forming a respective plurality of vertically stacked superlattice punch-through stop layers on each of the lower semiconductor fin portions with a respective bulk semiconductor layer between each of the superlattice punch-through stop layers, the bulk semiconductor layers having opposite conductivity types defining an embedded junction therebetween. <EOS>