In a processor, a method for out-of-order loads in a memory consistency model using shared memory resources, the method comprising: defining a memory resource that is accessible by a plurality of asynchronous cores, wherein the plurality of asynchronous cores share a unified store queue and a unified load queue; characterized by : implementing an access mask operable to track which words of a cache line are accessed via a load, wherein the cache line comprises the memory resource, wherein the load sets a mask bit within the access mask when accessing a word of the cache line, wherein the mask bit blocks accesses from other loads from the plurality of asynchronous cores, and wherein the load clears the mask bit when the load retires; checking the access mask upon execution of subsequent stores from the plurality of asynchronous cores to the cache line, wherein stores from different threads forward to loads of different threads while still maintaining in-order memory consistency semantics; and causing a miss prediction when a store to the word of the cache line corresponding to the load detects a prior mask bit from the load in the access mask, wherein the store signals a load queue entry corresponding to the load by using a tracker register and a thread ID register. defining a memory resource that is accessible by a plurality of asynchronous cores, wherein the plurality of asynchronous cores share a unified store queue and a unified load queue; characterized by : implementing an access mask operable to track which words of a cache line are accessed via a load, wherein the cache line comprises the memory resource, wherein the load sets a mask bit within the access mask when accessing a word of the cache line, wherein the mask bit blocks accesses from other loads from the plurality of asynchronous cores, and wherein the load clears the mask bit when the load retires; checking the access mask upon execution of subsequent stores from the plurality of asynchronous cores to the cache line, wherein stores from different threads forward to loads of different threads while still maintaining in-order memory consistency semantics; and causing a miss prediction when a store to the word of the cache line corresponding to the load detects a prior mask bit from the load in the access mask, wherein the store signals a load queue entry corresponding to the load by using a tracker register and a thread ID register. implementing an access mask operable to track which words of a cache line are accessed via a load, wherein the cache line comprises the memory resource, wherein the load sets a mask bit within the access mask when accessing a word of the cache line, wherein the mask bit blocks accesses from other loads from the plurality of asynchronous cores, and wherein the load clears the mask bit when the load retires; checking the access mask upon execution of subsequent stores from the plurality of asynchronous cores to the cache line, wherein stores from different threads forward to loads of different threads while still maintaining in-order memory consistency semantics; and causing a miss prediction when a store to the word of the cache line corresponding to the load detects a prior mask bit from the load in the access mask, wherein the store signals a load queue entry corresponding to the load by using a tracker register and a thread ID register. <EOS>