An apparatus comprising: a plurality of blocks (110-1, 110-2) of memory cells in a memory device, at least one of the plurality of blocks including two or more sub-blocks, and at least one of the two or more sub-blocks including a vertical string of memory cells, the vertical string including a plurality of memory cells and a select transistor (150-1, 150-2, 150-n, 152-1, 152-2, 152-n); and a sub-block disabling circuit including a memory to store a block address and sub-block address associated with a sub-block determined to be defective, wherein the sub-block disabling circuit is configured to selectively disable a sub-block within a block associated with the stored block address and sub-block address without disabling the block in which the sub-block is contained, responsive to receiving a user request for access to the memory device, after initialization of the memory device, at a block address and sub-block address that matches the stored block address and sub-block address; wherein the select transistor (150-1, 150-2, 150-n, 152-1, 152-2, 152-n) is a drain select gate, SGD, transistor, wherein the sub-block disabling circuit further comprises a drain select gate, SGD, driver , and wherein the sub-block disabling circuit being configured to disable the sub-block associated with the stored block address and sub-block address responsive to receiving a block address and sub-block address that matches the stored block address and sub-block address comprises the sub-block disabling circuit being configured to output a signal to the SGD driver of the sub-block responsive to receiving a block address and sub-block address that matches the stored block address and sub-block address, with the SGD driver configured to cause, based on the sub-block address, a gate of a SGD transistor that corresponds to the sub-block to be biased to ground potential. a plurality of blocks (110-1, 110-2) of memory cells in a memory device, at least one of the plurality of blocks including two or more sub-blocks, and at least one of the two or more sub-blocks including a vertical string of memory cells, the vertical string including a plurality of memory cells and a select transistor (150-1, 150-2, 150-n, 152-1, 152-2, 152-n); and a sub-block disabling circuit including a memory to store a block address and sub-block address associated with a sub-block determined to be defective, wherein the sub-block disabling circuit is configured to selectively disable a sub-block within a block associated with the stored block address and sub-block address without disabling the block in which the sub-block is contained, responsive to receiving a user request for access to the memory device, after initialization of the memory device, at a block address and sub-block address that matches the stored block address and sub-block address; wherein the select transistor (150-1, 150-2, 150-n, 152-1, 152-2, 152-n) is a drain select gate, SGD, transistor, wherein the sub-block disabling circuit further comprises a drain select gate, SGD, driver , and wherein the sub-block disabling circuit being configured to disable the sub-block associated with the stored block address and sub-block address responsive to receiving a block address and sub-block address that matches the stored block address and sub-block address comprises the sub-block disabling circuit being configured to output a signal to the SGD driver of the sub-block responsive to receiving a block address and sub-block address that matches the stored block address and sub-block address, with the SGD driver configured to cause, based on the sub-block address, a gate of a SGD transistor that corresponds to the sub-block to be biased to ground potential. <EOS>