A method for manufacturing an integrated device comprising a Junction Field-Effect Transistor, JFET, and a vertical double-diffused metal-oxide-semiconductor field-effect transistor, VDMOS, the integrated device being divided into a JFET region and a VDMOS region, the method comprising: providing (S510) a substrate of a first conduction type on which a first conduction type region is formed; while the first conduction type is opposite to a second conduction type; implanting (S520) ions of the second conduction type into the first conduction type region and forming a first well within the first conduction type region by driving-in; growing (S530) a field oxide layer and a gate oxide layer on a surface of the first conduction type region in sequence, forming a polysilicon layer on the surface of the first conduction type region, and implanting ions of the second conduction type into the first conduction type region of the VDMOS region and forming a plurality of second wells by driving-in; implanting (S540) ions of the first conduction type into each of the second wells of the VDMOS region to form a VDMOS source ; implanting (S550) ions of the first conduction type between two adjacent second wells of the JFET region to form a JFET source ; photoetching (S560) and etching a plurality of contact holes, implanting ions of the second conduction type into the contact holes, to form a clamping region within the first well and at a bottom of each of the second wells , wherein an ion concentration of the clamping region is greater than that of the first well ; and depositing (S570) a metal layer and filling the contact holes with the metal layer to form a metal electrode of the JFET source, a JFET metal gate and a metal contact of the VDMOS source respectively; wherein the first well is deeper than each of the second wells . providing (S510) a substrate of a first conduction type on which a first conduction type region is formed; while the first conduction type is opposite to a second conduction type; implanting (S520) ions of the second conduction type into the first conduction type region and forming a first well within the first conduction type region by driving-in; growing (S530) a field oxide layer and a gate oxide layer on a surface of the first conduction type region in sequence, forming a polysilicon layer on the surface of the first conduction type region, and implanting ions of the second conduction type into the first conduction type region of the VDMOS region and forming a plurality of second wells by driving-in; implanting (S540) ions of the first conduction type into each of the second wells of the VDMOS region to form a VDMOS source ; implanting (S550) ions of the first conduction type between two adjacent second wells of the JFET region to form a JFET source ; photoetching (S560) and etching a plurality of contact holes, implanting ions of the second conduction type into the contact holes, to form a clamping region within the first well and at a bottom of each of the second wells , wherein an ion concentration of the clamping region is greater than that of the first well ; and depositing (S570) a metal layer and filling the contact holes with the metal layer to form a metal electrode of the JFET source, a JFET metal gate and a metal contact of the VDMOS source respectively; wherein the first well is deeper than each of the second wells . <EOS>