A logic circuit comprising: a plurality of function blocks forming a redundant system and configured to output pieces of data, each piece of data including a bit string; a plurality of test pattern generation circuits configured to combine test patterns for abnormality detection with the pieces of data outputted from the function blocks ; and a comparison circuit (30 - 3n) configured to make a comparison between the pieces of data combined with the test patterns, characterized in that : the logic circuit further comprises synchronizing means, wherein: the synchronizing means comprises an element arranged to receive data increment signals from each of the plurality of function blocks respectively, and then to output a signal to synchronize the timing for outputting the next data by the plurality of function blocks ; the synchronizing means further comprises a further element and a counter , wherein the further element is arranged to receive orthogonal waveform increment signals from the plurality of function blocks , respectively, and to then output a signal that increments the counter for generating an argument x, whereby the counter alternately outputs to the plurality of test pattern generation circuits an argument x indicating the state that a test pattern is to be combined with the pieces of data outputted from the function blocks and an argument x indicating the state that a test pattern is not to be combined with the pieces of data outputted from the function blocks . a plurality of function blocks forming a redundant system and configured to output pieces of data, each piece of data including a bit string; a plurality of test pattern generation circuits configured to combine test patterns for abnormality detection with the pieces of data outputted from the function blocks ; and a comparison circuit (30 - 3n) configured to make a comparison between the pieces of data combined with the test patterns, characterized in that : the logic circuit further comprises synchronizing means, wherein: the synchronizing means comprises an element arranged to receive data increment signals from each of the plurality of function blocks respectively, and then to output a signal to synchronize the timing for outputting the next data by the plurality of function blocks ; the synchronizing means further comprises a further element and a counter , wherein the further element is arranged to receive orthogonal waveform increment signals from the plurality of function blocks , respectively, and to then output a signal that increments the counter for generating an argument x, whereby the counter alternately outputs to the plurality of test pattern generation circuits an argument x indicating the state that a test pattern is to be combined with the pieces of data outputted from the function blocks and an argument x indicating the state that a test pattern is not to be combined with the pieces of data outputted from the function blocks . the synchronizing means comprises an element arranged to receive data increment signals from each of the plurality of function blocks respectively, and then to output a signal to synchronize the timing for outputting the next data by the plurality of function blocks ; the synchronizing means further comprises a further element and a counter , wherein the further element is arranged to receive orthogonal waveform increment signals from the plurality of function blocks , respectively, and to then output a signal that increments the counter for generating an argument x, whereby the counter alternately outputs to the plurality of test pattern generation circuits an argument x indicating the state that a test pattern is to be combined with the pieces of data outputted from the function blocks and an argument x indicating the state that a test pattern is not to be combined with the pieces of data outputted from the function blocks . <EOS>