A physical unclonable function circuit structure, comprising n passive conductor groups (10 , 10 , 10 ,... 10(n)) and n XOR units (20 , 20 , 20 ,... 20(n)), the n passive conductor groups (10 , 10 , 10 ,... 10(n)) and the n XOR units (20 , 20 , 20 ,... 20(n)) being in an one-to-one correspondence relationship, wherein each of said passive conductor groups (10 , 10 , 10 ,... 10(n)) comprises m passive conductors (NET , NET ,... NET(m-2), NET(m-1)), each of said passive conductors (NET , NET ,... NET(m-2), NET(m-1)) comprises a first terminal and a second terminal, the first terminal of each of said passive conductors (NET , NET ,... NET(m-2), NET(m-1)) is connected to a power supply, and the second terminal is connected to an input terminal of the XOR unit (20 , 20 , 20 ,... 20(n)), wherein the second terminal of the passive conductor (NET , NET ,... NET(m-2), NET(m-1)) within a same passive conductor group (10 , 10 , 10 ,... 10(n)) is connected to the input terminal of the corresponding XOR unit (20 , 20 , 20 ,... 20(n)), wherein when the passive conductor (NET , NET ,... NET(m-2), NET(m-1)) is in a connected state, the second terminal of the passive conductor (NET , NET ,... NET(m-2), NET(m-1)) outputs a high level signal, when the passive conductor (NET , NET ,... NET(m-2), NET(m-1)) is in a disconnected state, the second terminal of the passive conductor (NET , NET ,... NET(m-2), NET(m-1)) outputs a low level signal, and the signal outputted from the second terminal of the passive conductor (NET , NET ,... NET(m-2), NET(m-1)) is inputted to the corresponding XOR unit, wherein each of the n XOR units (20 , 20 , 20 ,... 20(n)) performs an XOR operation on the signals outputted by the passive conductors (NET , NET ,... NET(m-2), NET(m-1)) within the same passive conductor group (10 , 10 , 10 ,... 10(n)) to obtain an XOR operation result, and XOR operation results obtained by all the XOR units (20 , 20 , 20 ,... 20(n)) is PUF data, wherein both n and m are positive integers, characterized in that widths of the passive conductors (NET , NET ,... NET(m-2), NET(m-1)) within the same passive conductor group are not exactly the same, and the width difference between the width of at least one passive conductor (NET , NET ,... NET(m-2), NET(m-1)) of the passive conductor group (10 , 10 , 10 ,... 10(n)) and a critical width of the same passive conductor group (10 , 10 , 10 ,... 10(n)) is less than or equal to a first threshold so that the said at least one passive conductor (NET , NET ,... NET(m-2), NET(m-1)) has connectivity uncertainty in a chip fabrication process, or within the same said passive conductor group (NET , NET ,... NET(m-2), NET(m-1)), said at least one passive conductor (NET , NET ,... NET(m-2), NET(m-1)) comprises at least a first passive conductor segment and a second passive conductor segment, a space (D , D ,... D(m-2), D(m-1)) exists between the said first passive conductor segment and the said second passive conductor segment, and a space difference between at least one said space (D , D ,... D(m-2), D(m-1)) and a critical space is less than or equal to a second threshold so that the said at least one passive conductor (NET , NET ,... NET(m-2), NET(m-1)) has connectivity uncertainty during the chip manufacturing process, wherein the said critical width is a minimum width that ensures that the passive conductor (NET , NET ,... NET(m-2), NET(m-1)) is able to be connected when the passive conductor (NET , NET ,... NET(m-2), NET(m-1)) is fabricated during the chip fabrication process, and the said critical space is a minimum space which ensures that the passive conductor (NET , NET ,... NET(m-2), NET(m-1)) is able to be connected when the passive conductor (NET , NET ,... NET(m-2), NET(m-1)) comprising a plurality of passive conductor segments spaced apart from each other is fabricated during the chip fabrication process. <EOS>