A memory device comprising: a cell array including a plurality of pages; and a control logic circuitry configured to control program operations of the cell array and read operations of the cell array , wherein the control logic circuitry is configured to control the program operations and read operations such that (A) in response to a program command for a page, the memory device stores first through N-th codewords (CW1...CWN) in a first page (PAGE1) among the plurality of pages and the memory device programs a page parity (PAR_P) corresponding in common to the first through N-th codewords (CW1...CWN) to the first page (PAGE1), and (B) in response to a read command for a sub-page, the memory device selectively reads the first codeword (CW1) among the first through N-th codewords, where N is an integer of at least 2, wherein a size of the sub page is less than a size of the page, wherein the first codeword (CW1) includes first sub-page data (DATA_S1) and a first sub-parity (PAR_S1) corresponding to the first sub-page data (DATA_S1), and the first sub-parity (PAR_S1) includes information associated with correcting an error in the first sub-page data (DATA_S1) through error correction code (ECC) decoding, the ECC decoding independently performable on each of the first through N-th codewords (CW1...CWN), wherein the memory device is configured to program the first through N-th codewords (CW1...CWN) to the first page (PAGE1) in a single program operation in response to a plurality of write requests from a host; and wherein the memory device is configured to provide the first codeword (CW1) to the host in a single read operation in response to a single read request from the host. a cell array including a plurality of pages; and a control logic circuitry configured to control program operations of the cell array and read operations of the cell array , wherein the control logic circuitry is configured to control the program operations and read operations such that (A) in response to a program command for a page, the memory device stores first through N-th codewords (CW1...CWN) in a first page (PAGE1) among the plurality of pages and the memory device programs a page parity (PAR_P) corresponding in common to the first through N-th codewords (CW1...CWN) to the first page (PAGE1), and (B) in response to a read command for a sub-page, the memory device selectively reads the first codeword (CW1) among the first through N-th codewords, where N is an integer of at least 2, wherein a size of the sub page is less than a size of the page, (A) in response to a program command for a page, the memory device stores first through N-th codewords (CW1...CWN) in a first page (PAGE1) among the plurality of pages and the memory device programs a page parity (PAR_P) corresponding in common to the first through N-th codewords (CW1...CWN) to the first page (PAGE1), and (B) in response to a read command for a sub-page, the memory device selectively reads the first codeword (CW1) among the first through N-th codewords, where N is an integer of at least 2, wherein a size of the sub page is less than a size of the page, wherein the first codeword (CW1) includes first sub-page data (DATA_S1) and a first sub-parity (PAR_S1) corresponding to the first sub-page data (DATA_S1), and the first sub-parity (PAR_S1) includes information associated with correcting an error in the first sub-page data (DATA_S1) through error correction code (ECC) decoding, the ECC decoding independently performable on each of the first through N-th codewords (CW1...CWN), wherein the memory device is configured to program the first through N-th codewords (CW1...CWN) to the first page (PAGE1) in a single program operation in response to a plurality of write requests from a host; and wherein the memory device is configured to provide the first codeword (CW1) to the host in a single read operation in response to a single read request from the host. <EOS>