An IGBT that is equipped with a semiconductor substrate , the IGBT comprising: an n-type emitter region that is formed in such a range as to be exposed to an upper face of the semiconductor substrate ; a p-type top body region that is formed below the emitter region ; an n-type floating region that is formed below the top body region and separated from the emitter region by the top body region ; a p-type bottom body region that is formed below the floating region ; a trench that is formed in the upper face of the semiconductor substrate and penetrates the emitter region , the top body region , the floating region , and the bottom body region ; a gate insulating film that covers an inner face of the trench ; and a gate electrode that is arranged inside the trench , wherein when a distribution of a concentration of p-type impurities in the top body region and the floating region , which are located below the emitter region , is viewed along a thickness direction of the semiconductor substrate , the concentration of the p-type impurities decreases as a downward distance increases from an upper end of the top body region that is located below the emitter region , and assumes a local minimum value (PLL) at a position in the floating region , the p-type bottom body region is separated from the top body region by the floating region (24, wherein when the distribution of the concentration of p-type impurities in the floating region and the bottom body region is viewed along the thickness direction of the semiconductor substrate , the concentration of p-type impurities increases as the downward distance increases from the position in the floating region where the concentration of the p-type impurities has the local minimum value and assumes a local maximum value (PLH) in the bottom body region . an n-type emitter region that is formed in such a range as to be exposed to an upper face of the semiconductor substrate ; a p-type top body region that is formed below the emitter region ; an n-type floating region that is formed below the top body region and separated from the emitter region by the top body region ; a p-type bottom body region that is formed below the floating region ; a trench that is formed in the upper face of the semiconductor substrate and penetrates the emitter region , the top body region , the floating region , and the bottom body region ; a gate insulating film that covers an inner face of the trench ; and a gate electrode that is arranged inside the trench , wherein when a distribution of a concentration of p-type impurities in the top body region and the floating region , which are located below the emitter region , is viewed along a thickness direction of the semiconductor substrate , the concentration of the p-type impurities decreases as a downward distance increases from an upper end of the top body region that is located below the emitter region , and assumes a local minimum value (PLL) at a position in the floating region , the p-type bottom body region is separated from the top body region by the floating region (24, wherein when the distribution of the concentration of p-type impurities in the floating region and the bottom body region is viewed along the thickness direction of the semiconductor substrate , the concentration of p-type impurities increases as the downward distance increases from the position in the floating region where the concentration of the p-type impurities has the local minimum value and assumes a local maximum value (PLH) in the bottom body region . <EOS>