A command interface of a memory device , comprising circuitry, configured to: identify a command acquisition mode from a plurality of command acquisition modes of a command interface of a memory device ; identify a state of a chip select signal, CS,; when the CS transitions to low from high: capture a first portion of a command address in a first clock cycle after the CS transitions; when the command acquisition mode is in a first mode, capture a second portion of the command address in a second clock cycle immediately after the first clock cycle; otherwise, when the command acquisition mode is in a second mode : maintain a toggle indicating when a cycle is a decode cycle, when the toggle indicates that a cycle immediately previous to a current cycle is a decode cycle, skip command address acquisition during the current cycle, and when the toggle indicates that the cycle immediately previous to the current cycle is not a decode cycle, perform command address acquisition during the current cycle; and fire an internal command, using the first portion of the command address and the second portion of the command address. identify a command acquisition mode from a plurality of command acquisition modes of a command interface of a memory device ; identify a state of a chip select signal, CS,; when the CS transitions to low from high: capture a first portion of a command address in a first clock cycle after the CS transitions; when the command acquisition mode is in a first mode, capture a second portion of the command address in a second clock cycle immediately after the first clock cycle; otherwise, when the command acquisition mode is in a second mode : maintain a toggle indicating when a cycle is a decode cycle, when the toggle indicates that a cycle immediately previous to a current cycle is a decode cycle, skip command address acquisition during the current cycle, and when the toggle indicates that the cycle immediately previous to the current cycle is not a decode cycle, perform command address acquisition during the current cycle; and fire an internal command, using the first portion of the command address and the second portion of the command address. capture a first portion of a command address in a first clock cycle after the CS transitions; when the command acquisition mode is in a first mode, capture a second portion of the command address in a second clock cycle immediately after the first clock cycle; otherwise, when the command acquisition mode is in a second mode : maintain a toggle indicating when a cycle is a decode cycle, when the toggle indicates that a cycle immediately previous to a current cycle is a decode cycle, skip command address acquisition during the current cycle, and when the toggle indicates that the cycle immediately previous to the current cycle is not a decode cycle, perform command address acquisition during the current cycle; and maintain a toggle indicating when a cycle is a decode cycle, when the toggle indicates that a cycle immediately previous to a current cycle is a decode cycle, skip command address acquisition during the current cycle, and when the toggle indicates that the cycle immediately previous to the current cycle is not a decode cycle, perform command address acquisition during the current cycle; and fire an internal command, using the first portion of the command address and the second portion of the command address. <EOS>