A processor device having an executable implementation of the cryptographic algorithm DES comprising several rounds implemented thereon, which cryptographic algorithm DES is arranged to generate, using a secret key K from an entry text, an exit text, wherein the implementation comprises in at least one or in each round - optionally with the exception of a first or/and last round of the algorithm configured partly in a deviating manner: - reception means for right r and left input values 1 of the round; - an expansion operation E arranged to expand at least some of the right input values r into expanded right input values r'; - an implemented computation step S arranged to map expanded right input values r' as computation step entry values x = r' onto exit values s = S[x]; - a XOR linkage operation at the round exit, arranged to link exit values s of the computation step S of the round with left input values 1 of the round and to supply these to the subsequent round; wherein the computation step S is implemented as a key-dependent computation step which in addition to the computation step S further comprises a key linkage operation for linking input values of the round with key values of the round derived directly or indirectly from the key; characterized in that: the computation step S is implemented as a combined key-dependent computation step T which further comprises: - a permutation operation P associated with the round, arranged to be applied to exit values s of the computation step S and to supply the XOR linkage operation and the exit values s of the computation step in permutated form to the XOR linkage operation at the round exit, wherein to at least a subset of the left input values 1 of the round not the computation step S is applied and wherein to each of the right input values x = r XOR k the computation step S is applied, so that the computation step T in each round delivers exit values which include both output values s of the computation step S and bits of the left side of the round. - reception means for right r and left input values 1 of the round; - an expansion operation E arranged to expand at least some of the right input values r into expanded right input values r'; - an implemented computation step S arranged to map expanded right input values r' as computation step entry values x = r' onto exit values s = S[x]; - a XOR linkage operation at the round exit, arranged to link exit values s of the computation step S of the round with left input values 1 of the round and to supply these to the subsequent round; - a permutation operation P associated with the round, arranged to be applied to exit values s of the computation step S and to supply the XOR linkage operation and the exit values s of the computation step in permutated form to the XOR linkage operation at the round exit, wherein to at least a subset of the left input values 1 of the round not the computation step S is applied and wherein to each of the right input values x = r XOR k the computation step S is applied, so that the computation step T in each round delivers exit values which include both output values s of the computation step S and bits of the left side of the round. <EOS>