Arrangement for redundant data processing with an integrated circuit, wherein the functionality of a multi-core processor with a plurality of processor cores is implemented in the integrated circuit, wherein the processor cores are each embodied to execute a useful program, wherein the arrangement comprises a comparison module, which is configured to compare results which emerge from execution of the useful program by different representatives of the processor cores in each case, wherein a first processor core and a second processor core different from the first processor core out of the plurality of processor cores are implemented such - that the first processor core uses a first address structure (AS1) to store and read data items in or from a first memory area assigned to the first processor core that differs from a second address structure (AS2) used by the second processor core to store and read data items in or from a second memory area assigned to the second processor core, wherein the second address structure (AS2) is transformed, in particular scrambled, compared to the first address structure (AS1), and/or - that the first processor core uses a first data structure (DS1) to store and read data items in or from the first memory area that differs from a second data structure (DS2) used by the second processor core to store and read data items in or from the second memory area, wherein the second data structure (DS2) transforms data words compared to the first data structure (DS1), in particular by means of bit shifting or other arithmetic operations, and wherein the implementation of the first processor core in the integrated circuit is at least partially separated from the implementation of the second processor core in terms of hardware, characterised in that the functionality of transforming the address structure and/or the data structure for the first processor core and the second processor core are implemented separately in a processor-core-specific manner in the integrated circuit in terms of hardware in each case, wherein a check is thereby not provided as to whether these functionalities are in each case linked to the correct processor core. - that the first processor core uses a first address structure (AS1) to store and read data items in or from a first memory area assigned to the first processor core that differs from a second address structure (AS2) used by the second processor core to store and read data items in or from a second memory area assigned to the second processor core, wherein the second address structure (AS2) is transformed, in particular scrambled, compared to the first address structure (AS1), and/or - that the first processor core uses a first data structure (DS1) to store and read data items in or from the first memory area that differs from a second data structure (DS2) used by the second processor core to store and read data items in or from the second memory area, wherein the second data structure (DS2) transforms data words compared to the first data structure (DS1), in particular by means of bit shifting or other arithmetic operations, and wherein the implementation of the first processor core in the integrated circuit is at least partially separated from the implementation of the second processor core in terms of hardware, characterised in that the functionality of transforming the address structure and/or the data structure for the first processor core and the second processor core are implemented separately in a processor-core-specific manner in the integrated circuit in terms of hardware in each case, wherein a check is thereby not provided as to whether these functionalities are in each case linked to the correct processor core. <EOS>