A dynamic current sink suitable for stabilizing an output voltage at an output node (NOUT) of an LDO (Low Dropout Linear Regulator) , when the dynamic current sink is coupled to said LDO , the dynamic current sink comprising: a first voltage comparator , suitable for comparing a first reference voltage (VREF1) with a second control signal (SC2) from the LDO when the dynamic current sink is coupled to said LDO , so as to generate a first control signal (SC1); a first transistor (M1), wherein the first transistor (M1) has a control terminal for receiving the first control signal (SC1), a first terminal coupled to a ground voltage (VSS), and a second terminal coupled to a first node (N1); a first current source , supplying a first current to the first node (N1); a first inverter , wherein the first inverter has an input terminal coupled to the first node (N1), and an output terminal coupled to a second node (N2); a second current source , supplying a second current to a third node (N3); an NAND gate , wherein the NAND gate has a first input terminal coupled to the third node (N3), a second input terminal coupled to the second node (N2), and an output terminal coupled to a fourth node (N4); a first capacitor (C1), coupled between the fourth node (N4) and a fifth node (N5); a first resistor (R1), coupled between the fifth node (N5) and the ground voltage (VSS); a second transistor (M2), wherein the second transistor (M2) has a control terminal coupled to the fifth node (N5), a first terminal coupled to the ground voltage (VSS), and a second terminal coupled to the third node (N3); and a third transistor (M3), wherein the third transistor (M3) has a control terminal coupled to the fifth node (N5), a first terminal coupled to the ground voltage (VSS), and a second terminal suitable for being coupled to the output node (NOUT) when the dynamic current sink is coupled to said LDO ; wherein the third transistor (M3) is configured to selectively draw a first discharge current (ID1) from the output node (NOUT). a first voltage comparator , suitable for comparing a first reference voltage (VREF1) with a second control signal (SC2) from the LDO when the dynamic current sink is coupled to said LDO , so as to generate a first control signal (SC1); a first transistor (M1), wherein the first transistor (M1) has a control terminal for receiving the first control signal (SC1), a first terminal coupled to a ground voltage (VSS), and a second terminal coupled to a first node (N1); a first current source , supplying a first current to the first node (N1); a first inverter , wherein the first inverter has an input terminal coupled to the first node (N1), and an output terminal coupled to a second node (N2); a second current source , supplying a second current to a third node (N3); an NAND gate , wherein the NAND gate has a first input terminal coupled to the third node (N3), a second input terminal coupled to the second node (N2), and an output terminal coupled to a fourth node (N4); a first capacitor (C1), coupled between the fourth node (N4) and a fifth node (N5); a first resistor (R1), coupled between the fifth node (N5) and the ground voltage (VSS); a second transistor (M2), wherein the second transistor (M2) has a control terminal coupled to the fifth node (N5), a first terminal coupled to the ground voltage (VSS), and a second terminal coupled to the third node (N3); and a third transistor (M3), wherein the third transistor (M3) has a control terminal coupled to the fifth node (N5), a first terminal coupled to the ground voltage (VSS), and a second terminal suitable for being coupled to the output node (NOUT) when the dynamic current sink is coupled to said LDO ; wherein the third transistor (M3) is configured to selectively draw a first discharge current (ID1) from the output node (NOUT). <EOS>