A chip package formed over a substrate, the chip package comprising: a processor unit , wherein said processor unit comprises a first cache memory chip, denoted first chip , over said substrate, wherein said first chip comprises a first silicon substrate and a first metal interconnect line connected to a first through-silicon via passing through said first silicon substrate and a first metal pad ; wherein said processor unit comprises further a processor chip, denoted second chip , provided vertically over said first chip, wherein said second chip comprises a second silicon substrate and second and third metal interconnect lines connecting second and third through-silicon vias , respectively, passing through said second silicon substrate with a respective one of second metal pads ; a first metal bump between said first and second chips, wherein a first inter-chip buffer of said second chip is connected to a second inter-chip buffer of said first chip through said first and second metal interconnect lines, said first and one of said second metal pads and said first metal bump, wherein a terminal (F3) is coupled to said second metal interconnect line between said first metal bump and said first inter-chip buffer of said second chip; a testing interface circuit coupled to said terminal, wherein an output capacitance seen from said terminal coupled to said inter-chip buffer of said second chip and coupled to the testing interface circuit is smaller than 2 pF; and a second metal bump between said first and second chips, wherein said third metal interconnect line is connected to said first chip through said second metal bump; and wherein the first and second metal bumps are microbumps of a plurality of microbumps that connect the first and the second chip, wherein a pitch between a neighbouring two of said plurality of microbumps is smaller than 60 micrometers, and wherein a thickness of the microbumps is 5 micrometers or more. a processor unit , wherein said processor unit comprises a first cache memory chip, denoted first chip , over said substrate, wherein said first chip comprises a first silicon substrate and a first metal interconnect line connected to a first through-silicon via passing through said first silicon substrate and a first metal pad ; wherein said processor unit comprises further a processor chip, denoted second chip , provided vertically over said first chip, wherein said second chip comprises a second silicon substrate and second and third metal interconnect lines connecting second and third through-silicon vias , respectively, passing through said second silicon substrate with a respective one of second metal pads ; a first metal bump between said first and second chips, wherein a first inter-chip buffer of said second chip is connected to a second inter-chip buffer of said first chip through said first and second metal interconnect lines, said first and one of said second metal pads and said first metal bump, wherein a terminal (F3) is coupled to said second metal interconnect line between said first metal bump and said first inter-chip buffer of said second chip; a testing interface circuit coupled to said terminal, wherein an output capacitance seen from said terminal coupled to said inter-chip buffer of said second chip and coupled to the testing interface circuit is smaller than 2 pF; and a second metal bump between said first and second chips, wherein said third metal interconnect line is connected to said first chip through said second metal bump; and wherein the first and second metal bumps are microbumps of a plurality of microbumps that connect the first and the second chip, wherein a pitch between a neighbouring two of said plurality of microbumps is smaller than 60 micrometers, and wherein a thickness of the microbumps is 5 micrometers or more. <EOS>