A safety industrial controller comprising: a first and second processor each including hardware memory management units ; an electronic memory having a plurality of addresses electronically addressable by both the first and second processor and holding a first and second program executable by the first and second processors respectively; and I/O circuitry adapted to communicate between industrial actuators and sensors and at least one of the first and second processors of the safety industrial controller ; wherein the hardware memory management units each include a memory protection table having entries mapping to addresses of the electronic memory and wherein the entries hold protection flags which when set block a writing to addresses of the entries ; wherein the first processor executes the first program to: (i) set protection flags of its memory management unit to permit writing to the electronic memory in a first region holding the first program and not to permit writing in a second region holding the second program ; and (ii) periodically attempt to write to the second region ; and wherein the second processor executes the second program to: (i) set protection flags of its memory management unit to permit writing to the electronic memory in the second region holding the second program and not to permit writing in the first region holding the first program ; and (ii) confirm that the first processor is blocked by its memory management unit from writing in the second region . a first and second processor each including hardware memory management units ; an electronic memory having a plurality of addresses electronically addressable by both the first and second processor and holding a first and second program executable by the first and second processors respectively; and I/O circuitry adapted to communicate between industrial actuators and sensors and at least one of the first and second processors of the safety industrial controller ; wherein the hardware memory management units each include a memory protection table having entries mapping to addresses of the electronic memory and wherein the entries hold protection flags which when set block a writing to addresses of the entries ; wherein the first processor executes the first program to: (i) set protection flags of its memory management unit to permit writing to the electronic memory in a first region holding the first program and not to permit writing in a second region holding the second program ; and (ii) periodically attempt to write to the second region ; and (i) set protection flags of its memory management unit to permit writing to the electronic memory in a first region holding the first program and not to permit writing in a second region holding the second program ; and (ii) periodically attempt to write to the second region ; and wherein the second processor executes the second program to: (i) set protection flags of its memory management unit to permit writing to the electronic memory in the second region holding the second program and not to permit writing in the first region holding the first program ; and (ii) confirm that the first processor is blocked by its memory management unit from writing in the second region . (i) set protection flags of its memory management unit to permit writing to the electronic memory in the second region holding the second program and not to permit writing in the first region holding the first program ; and (ii) confirm that the first processor is blocked by its memory management unit from writing in the second region . <EOS>