A gate driver for outputting gate signals to gate lines of a display, the gate driver comprising a plurality of stages (STA1, ... STA4, STB1, ..., STB4), wherein a stage (STAq) of the plurality of stages includes: a pull-up transistor (TU) configured to output a clock signal input to a first clock terminal (CT1) to an output terminal (OT) depending on a voltage of a pull-up node (NQ); a pull-down transistor (TD) configured to output a first source voltage input to a first source voltage terminal (VSST) to the output terminal (OT) depending on a voltage of a pull-down node (NQB); a boosting capacitor (CB) connected between the output terminal (OT) and the pull-up node (NQ) and configured to maintain a difference voltage between the output terminal (OT) and the pull-up node (NQ); and a first noise removing unit configured to supply a gate-off voltage to the pull-up node (NQ) to remove noise of the pull-up node (NQ), characterized by the first noise removing unit comprising: a first transistor (T1) configured to be turned on in response to a gate-on voltage of a first node (N1) and to thereby supply the first source voltage of the first source voltage terminal (VSST) to the pull-up node (NQ); a second transistor (T2) configured to be turned on in response to a gate-on voltage of the clock signal input to the first clock terminal (CT1) and to thereby supply the gate-on voltage of the clock signal to the first node (N1); and a third transistor (T3) configured to be turned on in response to a gate-on voltage of the pull-up node (NQ) and to thereby supply the first source voltage of the first source voltage terminal (VSST) to the first node (N1); and the stage (STAq) further including a second noise removing unit including a fifth transistor (T5) configured to be turned on in response to a gate-on voltage of another clock signal input to a second clock terminal (CT2) and to thereby connect the pull-up node (NQ) to an input terminal (PT) configured to receive the output signal of a previous stage (STAq-1). a pull-up transistor (TU) configured to output a clock signal input to a first clock terminal (CT1) to an output terminal (OT) depending on a voltage of a pull-up node (NQ); a pull-down transistor (TD) configured to output a first source voltage input to a first source voltage terminal (VSST) to the output terminal (OT) depending on a voltage of a pull-down node (NQB); a boosting capacitor (CB) connected between the output terminal (OT) and the pull-up node (NQ) and configured to maintain a difference voltage between the output terminal (OT) and the pull-up node (NQ); and a first noise removing unit configured to supply a gate-off voltage to the pull-up node (NQ) to remove noise of the pull-up node (NQ), a first transistor (T1) configured to be turned on in response to a gate-on voltage of a first node (N1) and to thereby supply the first source voltage of the first source voltage terminal (VSST) to the pull-up node (NQ); a second transistor (T2) configured to be turned on in response to a gate-on voltage of the clock signal input to the first clock terminal (CT1) and to thereby supply the gate-on voltage of the clock signal to the first node (N1); and a third transistor (T3) configured to be turned on in response to a gate-on voltage of the pull-up node (NQ) and to thereby supply the first source voltage of the first source voltage terminal (VSST) to the first node (N1); and the stage (STAq) further including a second noise removing unit including a fifth transistor (T5) configured to be turned on in response to a gate-on voltage of another clock signal input to a second clock terminal (CT2) and to thereby connect the pull-up node (NQ) to an input terminal (PT) configured to receive the output signal of a previous stage (STAq-1). <EOS>