A light receiving element , comprising: a plurality of pixels ; a semiconductor layer configured to photoelectrically convert infrared light and disposed between on-chip lenses for respective pixels and a multi wiring layer in a cross-sectional view; wherein each pixel includes: an on-chip lens ; a first deep trench isolation portion disposed in the semiconductor layer ; a second deep trench isolation portion disposed adjacent to the first deep trench isolation portion in the semiconductor layer in the cross-sectional view; a photodiode (PD) disposed between the first deep trench isolation portion and the second deep trench isolation portion in the semiconductor layer in the cross-sectional view; a first transfer transistor (TRG1) configured to transfer electric charge generated in the photodiode (PD) to a first floating diffusion region (FD1); a second transfer transistor (TRG2) configured to transfer electric charge generated in the photodiode (PD) to a second floating diffusion region (FD2); and a charge ejection transistor (OFG) configured to eject charges accumulated in the photodiode (PD), wherein one of a source and a drain of the charge ejection transistor (OFG) is coupled to the photodiode (PD), and wherein another one of the source and the drain of the charge ejection transistor (OFG) is coupled to a wiring configured to receive a voltage source potential; wherein the first deep trench isolation portion and the second deep trench isolation portion are formed in a depth direction from a back side of the semiconductor layer facing the on-chip lens ; wherein the first transfer transistor (TRG1), the second transfer transistor (TRG2) and the charge ejection transistor (OFG) are formed on a front side of the semiconductor layer opposite to the back side; and wherein the first deep trench isolation portion and the second deep trench isolation portion are configured to separate adjacent pixels from one another and to prevent incident light from reaching an adjacent pixel. an on-chip lens ; a first deep trench isolation portion disposed in the semiconductor layer ; a second deep trench isolation portion disposed adjacent to the first deep trench isolation portion in the semiconductor layer in the cross-sectional view; a photodiode (PD) disposed between the first deep trench isolation portion and the second deep trench isolation portion in the semiconductor layer in the cross-sectional view; a first transfer transistor (TRG1) configured to transfer electric charge generated in the photodiode (PD) to a first floating diffusion region (FD1); a second transfer transistor (TRG2) configured to transfer electric charge generated in the photodiode (PD) to a second floating diffusion region (FD2); and a charge ejection transistor (OFG) configured to eject charges accumulated in the photodiode (PD), wherein one of a source and a drain of the charge ejection transistor (OFG) is coupled to the photodiode (PD), and wherein another one of the source and the drain of the charge ejection transistor (OFG) is coupled to a wiring configured to receive a voltage source potential; wherein the first deep trench isolation portion and the second deep trench isolation portion are formed in a depth direction from a back side of the semiconductor layer facing the on-chip lens ; wherein the first transfer transistor (TRG1), the second transfer transistor (TRG2) and the charge ejection transistor (OFG) are formed on a front side of the semiconductor layer opposite to the back side; and wherein the first deep trench isolation portion and the second deep trench isolation portion are configured to separate adjacent pixels from one another and to prevent incident light from reaching an adjacent pixel. <EOS>