A memory device , comprising: a memory chip (CHIP1) including a memory cell array including a three-dimensional, 3D, cell array connected to first word lines and first bit lines, first word line bonding pads (WLBP1) respectively connected to the first word lines, and first bit line bonding pads (BLBP1) respectively connected to the first bit lines; and a peripheral circuit chip (CHIP2), wherein the peripheral circuit chip includes a test cell array including a two-dimensional, 2D, cell array connected to second word lines and second bit lines, second word line bonding pads (WLBP2) respectively connected to the first word line bonding pads, second bit line bonding pads (BLBP2) respectively connected to the first bit line bonding pads, and a peripheral circuit connected to the second word line bonding pads and the second word lines, or the second bit line bonding pads and the second bit lines; wherein the peripheral circuit chip is vertically connected to the memory chip via the first and second word line bonding pads and the first and second bit line bonding pads, wherein the peripheral circuit chip is configured to perform an electrical die sorting, EDS, process before the peripheral circuit chip is bonded to the memory chip, wherein the EDS process inspects whether or not the test cell array and the peripheral circuit electrically operate. a memory chip (CHIP1) including a memory cell array including a three-dimensional, 3D, cell array connected to first word lines and first bit lines, first word line bonding pads (WLBP1) respectively connected to the first word lines, and first bit line bonding pads (BLBP1) respectively connected to the first bit lines; and a memory cell array including a three-dimensional, 3D, cell array connected to first word lines and first bit lines, first word line bonding pads (WLBP1) respectively connected to the first word lines, and first bit line bonding pads (BLBP1) respectively connected to the first bit lines; and a peripheral circuit chip (CHIP2), wherein the peripheral circuit chip includes a test cell array including a two-dimensional, 2D, cell array connected to second word lines and second bit lines, second word line bonding pads (WLBP2) respectively connected to the first word line bonding pads, second bit line bonding pads (BLBP2) respectively connected to the first bit line bonding pads, and a peripheral circuit connected to the second word line bonding pads and the second word lines, or the second bit line bonding pads and the second bit lines; a test cell array including a two-dimensional, 2D, cell array connected to second word lines and second bit lines, second word line bonding pads (WLBP2) respectively connected to the first word line bonding pads, second bit line bonding pads (BLBP2) respectively connected to the first bit line bonding pads, and a peripheral circuit connected to the second word line bonding pads and the second word lines, or the second bit line bonding pads and the second bit lines; the second word line bonding pads and the second word lines, or the second bit line bonding pads and the second bit lines; wherein the peripheral circuit chip is vertically connected to the memory chip via the first and second word line bonding pads and the first and second bit line bonding pads, wherein the peripheral circuit chip is configured to perform an electrical die sorting, EDS, process before the peripheral circuit chip is bonded to the memory chip, wherein the EDS process inspects whether or not the test cell array and the peripheral circuit electrically operate. <EOS>