Quantum device including at least: - a semiconductor portion comprising several first regions configured to form quantum dots of at least one spin qubit of the quantum device , each disposed between at least two second regions forming tunnel barriers and juxtaposed with the two second regions ; - first electrostatic control gates each comprising at least a first portion of electrically conductive material ; - second electrostatic control gates each comprising at least a second portion of electrically conductive material and at least a second gate dielectric disposed between the second portion of electrically conductive material and the first portion of electrically conductive material of one of the first electrostatic control gates, such that each of the first electrostatic control gates is disposed between the semiconductor portion and one of the second electrostatic control gates; wherein the second electrostatic control gates are solely located in the vertical extension, perpendicular to the main plane of the semiconductor portion , of the first electrostatic control gates; and wherein, in a first configuration, the first and second electrostatic control gates are disposed above the first regions of the semiconductor portion , the second regions of the semiconductor portion not being covered by the first and second electrostatic control gates, or wherein, in a second configuration, the first and second electrostatic control gates are disposed above the second regions of the semiconductor portion , the first regions of the semiconductor portion not being covered by the first and second electrostatic control gates. - a semiconductor portion comprising several first regions configured to form quantum dots of at least one spin qubit of the quantum device , each disposed between at least two second regions forming tunnel barriers and juxtaposed with the two second regions ; - first electrostatic control gates each comprising at least a first portion of electrically conductive material ; - second electrostatic control gates each comprising at least a second portion of electrically conductive material and at least a second gate dielectric disposed between the second portion of electrically conductive material and the first portion of electrically conductive material of one of the first electrostatic control gates, such that each of the first electrostatic control gates is disposed between the semiconductor portion and one of the second electrostatic control gates; wherein the second electrostatic control gates are solely located in the vertical extension, perpendicular to the main plane of the semiconductor portion , of the first electrostatic control gates; and wherein, in a first configuration, the first and second electrostatic control gates are disposed above the first regions of the semiconductor portion , the second regions of the semiconductor portion not being covered by the first and second electrostatic control gates, or wherein, in a second configuration, the first and second electrostatic control gates are disposed above the second regions of the semiconductor portion , the first regions of the semiconductor portion not being covered by the first and second electrostatic control gates. <EOS>