A method of fabricating a stacked microelectronic assembly from one or more wafers having dies to be separated from one another, each wafer having a substrate with a first, front, surface , a second, rear, surface, and bond pads exposed at the front surface , the method comprising: forming a first microelectronic device from a said wafer by: a) patterning a metal film deposited on the front surface to form a first metallization layer , having first conductive elements that extend as conductive traces from the bond pads to the edges of the dies and second conductive elements used to connect stacked components, b) attaching the wafer to a carrier substrate using an adhesive layer so that the first metallization layer is facing down and attached to the carrier substrate, c) cutting or etching channels into the substrate to expose a portion of the first metallization layer and form die structures having edges that extend at an acute angle to the rear surface, d) forming a dielectric layer on the rear surface of the substrate such that a portion of the first metallization layer is exposed, e) forming a second metallization layer on the rear surface of the substrate , providing third conductive elements extending along the edges of the die structures to electrically connect portions of the first and second metallization layers to one another, f) removing the carrier substrate , g) singulating or severing the wafer to form individual severed die structures, wherein one of the individual severed die structures is a first microelectronic device, h) stacking the first microelectronic device and a second microelectronic device also formed by steps a) to g) and conductively bonding the first metallization layer of one of the first and second microelectronic devices to the second metallization layer of the other of the first and second microelectronic devices, wherein the die structures of the first and second microelectronic devices are singulated from the same wafer or from different wafers. a) patterning a metal film deposited on the front surface to form a first metallization layer , having first conductive elements that extend as conductive traces from the bond pads to the edges of the dies and second conductive elements used to connect stacked components, b) attaching the wafer to a carrier substrate using an adhesive layer so that the first metallization layer is facing down and attached to the carrier substrate, c) cutting or etching channels into the substrate to expose a portion of the first metallization layer and form die structures having edges that extend at an acute angle to the rear surface, d) forming a dielectric layer on the rear surface of the substrate such that a portion of the first metallization layer is exposed, e) forming a second metallization layer on the rear surface of the substrate , providing third conductive elements extending along the edges of the die structures to electrically connect portions of the first and second metallization layers to one another, f) removing the carrier substrate , g) singulating or severing the wafer to form individual severed die structures, wherein one of the individual severed die structures is a first microelectronic device, h) stacking the first microelectronic device and a second microelectronic device also formed by steps a) to g) and conductively bonding the first metallization layer of one of the first and second microelectronic devices to the second metallization layer of the other of the first and second microelectronic devices, wherein the die structures of the first and second microelectronic devices are singulated from the same wafer or from different wafers. <EOS>