A method , comprising: obtaining a trained model for a deep learning process ; converting the trained model to design abstraction (DA) code ; programming a field programmable gate array (FPGA) device in a system based on the DA code , wherein the DA code comprises code for programming a plurality of logic block circuits in the FPGA device , each of the plurality of logic block circuits representing one of a plurality of modules for executing a processing step between different layers of the deep learning process; characterized by : prior to the programming, determining that the FPGA device is insufficient for the plurality of logic block circuits required by the DA code; in response to determining that the FPGA device is insufficient for the plurality of logic block circuits required by the DA code, implementing an alternate programming mode for the FPGA device during the programming, wherein implementing the alternate programming mode during the programming comprises: identifying DA code corresponding to one or more of the plurality of logic block circuits representing an operation performed by another component in the system to yield duplicate logic block circuits; deleting the duplicate logic block circuits from the DA code; and updating the DA code to configure the FPGA device to perform the duplicates of the operation using the other component. obtaining a trained model for a deep learning process ; converting the trained model to design abstraction (DA) code ; programming a field programmable gate array (FPGA) device in a system based on the DA code , wherein the DA code comprises code for programming a plurality of logic block circuits in the FPGA device , each of the plurality of logic block circuits representing one of a plurality of modules for executing a processing step between different layers of the deep learning process; characterized by : prior to the programming, determining that the FPGA device is insufficient for the plurality of logic block circuits required by the DA code; in response to determining that the FPGA device is insufficient for the plurality of logic block circuits required by the DA code, implementing an alternate programming mode for the FPGA device during the programming, wherein implementing the alternate programming mode during the programming comprises: identifying DA code corresponding to one or more of the plurality of logic block circuits representing an operation performed by another component in the system to yield duplicate logic block circuits; deleting the duplicate logic block circuits from the DA code; and updating the DA code to configure the FPGA device to perform the duplicates of the operation using the other component. prior to the programming, determining that the FPGA device is insufficient for the plurality of logic block circuits required by the DA code; in response to determining that the FPGA device is insufficient for the plurality of logic block circuits required by the DA code, implementing an alternate programming mode for the FPGA device during the programming, wherein implementing the alternate programming mode during the programming comprises: identifying DA code corresponding to one or more of the plurality of logic block circuits representing an operation performed by another component in the system to yield duplicate logic block circuits; deleting the duplicate logic block circuits from the DA code; and updating the DA code to configure the FPGA device to perform the duplicates of the operation using the other component. identifying DA code corresponding to one or more of the plurality of logic block circuits representing an operation performed by another component in the system to yield duplicate logic block circuits; deleting the duplicate logic block circuits from the DA code; and updating the DA code to configure the FPGA device to perform the duplicates of the operation using the other component. <EOS>