A field effect transistor (FET) apparatus comprising: an FET device (400; 500; 600; 700; 1005) including: a semiconducting channel (405; 710; 810; 1105); spaced apart source (410; 510; 715; 815; 1020) and drain (415; 515; 720; 820; 1010) regions disposed on a surface of the semiconducting channel; a dielectric layer (420; 725; 825; 1130) disposed on the surface of the semiconducting channel between the source and drain regions; a gate region (425; 525; 730; 830; 1015) disposed on a surface of the dielectric layer opposite the surface of the semiconducting channel and between the source and drain regions; the source, gate and drain regions each being a metallic region; a control region (735; 1025) disposed on the surface of the dielectric layer between the gate region and the drain region, the control region not connected to the gate region, the control region comprising Mo x W 1-x Te 2 phase change material which has a semiconductor phase and an insulator phase selectable based on whether a control voltage field, which is independent from a field produced by a voltage applied at the drain region, is or is not present across the control region; the control region in the semiconductor phase functioning as a shield to passivate traps at the surface of the semiconducting channel between the gate region and the drain region; the control region in the insulator phase enhancing high frequency response of the FET by not presenting a physically active region adjacent the gate region; the phase change material being changed from one of semiconductor and insulator phases to the other of semiconductor and insulator phases at room temperature dependent on whether a voltage differential greater than a predetermined phase change voltage exists across the phase change material. a semiconducting channel (405; 710; 810; 1105); spaced apart source (410; 510; 715; 815; 1020) and drain (415; 515; 720; 820; 1010) regions disposed on a surface of the semiconducting channel; a dielectric layer (420; 725; 825; 1130) disposed on the surface of the semiconducting channel between the source and drain regions; a gate region (425; 525; 730; 830; 1015) disposed on a surface of the dielectric layer opposite the surface of the semiconducting channel and between the source and drain regions; the source, gate and drain regions each being a metallic region; a control region (735; 1025) disposed on the surface of the dielectric layer between the gate region and the drain region, the control region not connected to the gate region, the control region comprising Mo x W 1-x Te 2 phase change material which has a semiconductor phase and an insulator phase selectable based on whether a control voltage field, which is independent from a field produced by a voltage applied at the drain region, is or is not present across the control region; the control region in the semiconductor phase functioning as a shield to passivate traps at the surface of the semiconducting channel between the gate region and the drain region; the control region in the insulator phase enhancing high frequency response of the FET by not presenting a physically active region adjacent the gate region; the phase change material being changed from one of semiconductor and insulator phases to the other of semiconductor and insulator phases at room temperature dependent on whether a voltage differential greater than a predetermined phase change voltage exists across the phase change material. <EOS>