A voltage regulator , comprising: a plurality of pass transistors (M1...M4), each of the plurality of pass transistors (M1...M4) having a gate, a source coupled to an input supply rail (VDDIN) and a drain coupled to a respective one of a plurality of regulator outputs (VDD1...VDD4); a plurality of voltage dividers (235-1...235-4), wherein each of the plurality of voltage dividers (235-1...235-4) is configured to divide a voltage of a respective one of the plurality of regulator outputs (VDD1 ... VDD4) to generate a respective one of a plurality of feedback voltages (V FB1 ...V FB4 ); a plurality of averaging resistors (R AVG1 )...R AVG4 ) configured to average the plurality of feedback voltages (V FB1 )...V FB4 ) to generate an average feedback voltage at a common node , wherein each of the plurality of averaging resistors R AVG1 ...R AVG4 ) is between a node (237-1...237-4) corresponding to a respective one of the plurality of feedback voltages (V FB1 ...V FB4 ) and the common node , and wherein each of the plurality of feedback voltages (V FB1 ...V FB4 ) provides voltage feedback for the respective one of the plurality of regulator outputs (VDD1... VDD4); and an amplifier having a first input coupled to the average feedback voltage at the common node , and a second input coupled to a reference voltage (V REF ), wherein the output of the amplifier is connected to the gates of the plurality of the pass transistors (M1...M4); characterized by : a plurality of voltage-divider switches (610-1...610-4), wherein each of the plurality of voltage-divider switches (610-1...610-4) is configured to selectively couple a respective one of the plurality of a voltage dividers (235-1...235-4) to a ground based on a respective control signal from a controller. a plurality of pass transistors (M1...M4), each of the plurality of pass transistors (M1...M4) having a gate, a source coupled to an input supply rail (VDDIN) and a drain coupled to a respective one of a plurality of regulator outputs (VDD1...VDD4); a plurality of voltage dividers (235-1...235-4), wherein each of the plurality of voltage dividers (235-1...235-4) is configured to divide a voltage of a respective one of the plurality of regulator outputs (VDD1 ... VDD4) to generate a respective one of a plurality of feedback voltages (V FB1 ...V FB4 ); a plurality of averaging resistors (R AVG1 )...R AVG4 ) configured to average the plurality of feedback voltages (V FB1 )...V FB4 ) to generate an average feedback voltage at a common node , wherein each of the plurality of averaging resistors R AVG1 ...R AVG4 ) is between a node (237-1...237-4) corresponding to a respective one of the plurality of feedback voltages (V FB1 ...V FB4 ) and the common node , and wherein each of the plurality of feedback voltages (V FB1 ...V FB4 ) provides voltage feedback for the respective one of the plurality of regulator outputs (VDD1... VDD4); and an amplifier having a first input coupled to the average feedback voltage at the common node , and a second input coupled to a reference voltage (V REF ), wherein the output of the amplifier is connected to the gates of the plurality of the pass transistors (M1...M4); characterized by : a plurality of voltage-divider switches (610-1...610-4), wherein each of the plurality of voltage-divider switches (610-1...610-4) is configured to selectively couple a respective one of the plurality of a voltage dividers (235-1...235-4) to a ground based on a respective control signal from a controller. <EOS>