A display device , comprising: a substrate including a display area (AA) which has an irregularly shaped side and a non-display area (NA) which includes a notch area (NTA) defined by a shape of the irregularly shaped side of the display area (AA) and is disposed to enclose the display area (AA); a plurality of pixels (P) disposed in the display area (AA) where images are displayed; a plurality of power lines (PL) which are adapted to apply a high-potential power and a low-potential power to the plurality of pixels (P); a plurality of gate lines (GL) which are adapted to apply a gate signal to the plurality of pixels (P) and are divided to be disposed in a left display area of the display area (AA) and a right display area of the display area (AA) due to the irregularly shaped side of the display area (AA); and a connecting metal line (CML) connecting the plurality of gate lines (GL) divided to be disposed in the left display area and the right display area in the notch area (NTA), wherein in the notch area (NTA), a plurality of high-potential power link lines (VDDA) and a plurality of low-potential power link lines (VSSA) are further disposed to supply the high-potential power and the low-potential power to the display area (AA), wherein the connecting metal line (CML) is disposed on a different layer from that of the plurality of high-potential power link lines and the plurality of low-potential power link lines, wherein the connecting metal line (CML) overlaps the plurality of high-potential power link lines or the plurality of low-potential power link lines, whereby a capacitance compensating pattern is formed to compensate a capacitance of the display area (AA) having the irregularly shaped side, wherein a further capacitance compensating pattern together with the connecting metal line (CML) is formed by an active layer (ACT) or a light blocking layer (LS) below a gate insulating layer (GI) which are disposed in the display area (AA) . a substrate including a display area (AA) which has an irregularly shaped side and a non-display area (NA) which includes a notch area (NTA) defined by a shape of the irregularly shaped side of the display area (AA) and is disposed to enclose the display area (AA); a plurality of pixels (P) disposed in the display area (AA) where images are displayed; a plurality of power lines (PL) which are adapted to apply a high-potential power and a low-potential power to the plurality of pixels (P); a plurality of gate lines (GL) which are adapted to apply a gate signal to the plurality of pixels (P) and are divided to be disposed in a left display area of the display area (AA) and a right display area of the display area (AA) due to the irregularly shaped side of the display area (AA); and a connecting metal line (CML) connecting the plurality of gate lines (GL) divided to be disposed in the left display area and the right display area in the notch area (NTA), wherein in the notch area (NTA), a plurality of high-potential power link lines (VDDA) and a plurality of low-potential power link lines (VSSA) are further disposed to supply the high-potential power and the low-potential power to the display area (AA), wherein the connecting metal line (CML) is disposed on a different layer from that of the plurality of high-potential power link lines and the plurality of low-potential power link lines, wherein the connecting metal line (CML) overlaps the plurality of high-potential power link lines or the plurality of low-potential power link lines, whereby a capacitance compensating pattern is formed to compensate a capacitance of the display area (AA) having the irregularly shaped side, wherein a further capacitance compensating pattern together with the connecting metal line (CML) is formed by an active layer (ACT) or a light blocking layer (LS) below a gate insulating layer (GI) which are disposed in the display area (AA) . <EOS>