A write assist circuit, capable of writing data to a memory cell with a bit line (BL) and a bit line bar (BLB), comprising: a clamping circuit , coupled to a first node (N1) and a second node (N2) to prevent the voltage of the first node and the second node from being lower than a data-retention voltage, wherein the second node is different from the first node, the first node and the second node are supplied with a first voltage source and a second voltage source different from the first voltage source, and the memory cell is supplied by the first voltage source at the first node and the second voltage source at the second node respectively; a first coupling circuit , connected between the first node and the bit line; and a second coupling circuit , connected between the second node and the bit line bar, wherein when the data is written to the memory cell, one of the first coupling circuit and the second coupling circuit is utilized to pull down a voltage of one of the first node or the second node according to the data while a voltage of the other one of the first node or the second node is kept at a power supply voltage level, characterized in that the clamping circuit comprises: a first clamping PMOS transistor , having a source coupled to the first node (N1), a gate connected to the source, a drain coupled to a clamping bias node (NCL) and a bulk connected the drain; and a second clamping PMOS transistor , having a source coupled to the second node (N2), a gate connected to the source, a drain coupled to the clamping bias node (NCL) and a bulk connected the drain. a clamping circuit , coupled to a first node (N1) and a second node (N2) to prevent the voltage of the first node and the second node from being lower than a data-retention voltage, wherein the second node is different from the first node, the first node and the second node are supplied with a first voltage source and a second voltage source different from the first voltage source, and the memory cell is supplied by the first voltage source at the first node and the second voltage source at the second node respectively; a first coupling circuit , connected between the first node and the bit line; and a second coupling circuit , connected between the second node and the bit line bar, wherein when the data is written to the memory cell, one of the first coupling circuit and the second coupling circuit is utilized to pull down a voltage of one of the first node or the second node according to the data while a voltage of the other one of the first node or the second node is kept at a power supply voltage level, characterized in that the clamping circuit comprises: a first clamping PMOS transistor , having a source coupled to the first node (N1), a gate connected to the source, a drain coupled to a clamping bias node (NCL) and a bulk connected the drain; and a second clamping PMOS transistor , having a source coupled to the second node (N2), a gate connected to the source, a drain coupled to the clamping bias node (NCL) and a bulk connected the drain. a first clamping PMOS transistor , having a source coupled to the first node (N1), a gate connected to the source, a drain coupled to a clamping bias node (NCL) and a bulk connected the drain; and a second clamping PMOS transistor , having a source coupled to the second node (N2), a gate connected to the source, a drain coupled to the clamping bias node (NCL) and a bulk connected the drain. <EOS>