A semiconductor device comprising a top surface and sidewalls, the device further comprising: a substrate ; a plurality of metal layers and dielectric layers coupled to a top surface of the substrate ; a pad coupled to one of the plurality of metal layers ; a passivation layer on the plurality of metal layers and dielectric layers and coupled to the pad wherein the passivation layer exposes at least a portion of the pad ; a first metal redistribution layer above the passivation layer ; a first insulation layer between the passivation layer and the first metal redistribution layer , the first insulating layer having a cavity over the pad , wherein the first metal redistribution layer is coupled to the pad; a second insulation layer above the first metal redistribution layer ; an under bump metallization, UBM, layer above the second insulation layer , coupled to the first metal redistribution layer via a cavity in the second insulation layer ; a solder ball on the UBM layer ; and a mold layer forming the top surface of the device and covering the second insulation layer and the |UBM layer ; wherein the sidewall of the device comprises a first sidewall portion comprising side portions of the passivation layer , the first insulation layer , the second insulation layer and at least one of the plurality of metal layers and dielectric layers and a second sidewall portion comprising the substrate and the remaining ones of the plurality of metal layers and dielectric layers , the first sidewall portion being recessed with respect to the second sidewall portion; wherein the mold layer covers the side portions of the passivation layer , the first insulation layer , the second insulation layer and the at least one of the plurality of metal layers and dielectric layers and fills the recessed first sidewall portion; and wherein the mold layer is a transparent epoxy layer. a substrate ; a plurality of metal layers and dielectric layers coupled to a top surface of the substrate ; a pad coupled to one of the plurality of metal layers ; a passivation layer on the plurality of metal layers and dielectric layers and coupled to the pad wherein the passivation layer exposes at least a portion of the pad ; a first metal redistribution layer above the passivation layer ; a first insulation layer between the passivation layer and the first metal redistribution layer , the first insulating layer having a cavity over the pad , wherein the first metal redistribution layer is coupled to the pad; a second insulation layer above the first metal redistribution layer ; an under bump metallization, UBM, layer above the second insulation layer , coupled to the first metal redistribution layer via a cavity in the second insulation layer ; a solder ball on the UBM layer ; and a mold layer forming the top surface of the device and covering the second insulation layer and the |UBM layer ; wherein the sidewall of the device comprises a first sidewall portion comprising side portions of the passivation layer , the first insulation layer , the second insulation layer and at least one of the plurality of metal layers and dielectric layers and a second sidewall portion comprising the substrate and the remaining ones of the plurality of metal layers and dielectric layers , the first sidewall portion being recessed with respect to the second sidewall portion; wherein the mold layer covers the side portions of the passivation layer , the first insulation layer , the second insulation layer and the at least one of the plurality of metal layers and dielectric layers and fills the recessed first sidewall portion; and wherein the mold layer is a transparent epoxy layer. <EOS>