A processor comprising: a plurality of operational units to execute instructions associated with machine learning operations; a local memory comprising a plurality of dual-ported static random-access memory, SRAM, banks to store data associated with one or more of the instructions; a decoder to decode a matrix multiplication instruction; circuitry to permute a first plurality of source data elements associated with a first multidimensional array in accordance with a permutation pattern included with the matrix multiplication instruction and route the first plurality of source data elements to the plurality of operational units; the plurality of operational units to perform a plurality of parallel multiply-accumulate, MAC, operations in accordance with the matrix multiplication instruction, each operational unit comprising: a multiplier to multiply a first source data element of the first plurality of source data elements provided by the circuitry to permute and a second source data element of a second plurality of source data elements associated with a second multidimensional array to generate a product, and an accumulator to add the product to an accumulation value to generate a result value, the first source data element and the second source data element each having a first bit width and the accumulation value having a second bit width at least twice the first bit width. a plurality of operational units to execute instructions associated with machine learning operations; a local memory comprising a plurality of dual-ported static random-access memory, SRAM, banks to store data associated with one or more of the instructions; a decoder to decode a matrix multiplication instruction; circuitry to permute a first plurality of source data elements associated with a first multidimensional array in accordance with a permutation pattern included with the matrix multiplication instruction and route the first plurality of source data elements to the plurality of operational units; the plurality of operational units to perform a plurality of parallel multiply-accumulate, MAC, operations in accordance with the matrix multiplication instruction, each operational unit comprising: a multiplier to multiply a first source data element of the first plurality of source data elements provided by the circuitry to permute and a second source data element of a second plurality of source data elements associated with a second multidimensional array to generate a product, and an accumulator to add the product to an accumulation value to generate a result value, the first source data element and the second source data element each having a first bit width and the accumulation value having a second bit width at least twice the first bit width. a multiplier to multiply a first source data element of the first plurality of source data elements provided by the circuitry to permute and a second source data element of a second plurality of source data elements associated with a second multidimensional array to generate a product, and an accumulator to add the product to an accumulation value to generate a result value, the first source data element and the second source data element each having a first bit width and the accumulation value having a second bit width at least twice the first bit width. <EOS>