A processor device having debug capabilities, comprising: a central processing unit ; an interrupt controller; a status unit operable to be set into a first mode indicating an interrupt has occurred or in a second mode indicating normal execution of code; a debug unit coupled with said status unit and comprising a configurable breakpoint unit , wherein a condition can be set that a breakpoint is only activated if the device is executing any instruction within an interrupt service routine and if the status unit is in the first mode, and wherein the status unit comprises: a final stage interrupt detection unit ; a return from interrupt detection unit ; a first multiplexer having a first input receiving a logic 1 at a first input and being controlled by the final stage interrupt detection unit ; a second multiplexer receiving a logic 0 at a first input and having a second input coupled with an output of the first multiplexer , wherein the second multiplexer is controlled by the return from interrupt detection unit ; and a clock controlled register receiving an output signal from the second multiplexer and having an output coupled with a second input of the first multiplexer wherein the output of the register indicates a current interrupt status of the central processing unit . a central processing unit ; an interrupt controller; a status unit operable to be set into a first mode indicating an interrupt has occurred or in a second mode indicating normal execution of code; a debug unit coupled with said status unit and comprising a configurable breakpoint unit , wherein a condition can be set that a breakpoint is only activated if the device is executing any instruction within an interrupt service routine and if the status unit is in the first mode, and wherein the status unit comprises: a final stage interrupt detection unit ; a return from interrupt detection unit ; a first multiplexer having a first input receiving a logic 1 at a first input and being controlled by the final stage interrupt detection unit ; a second multiplexer receiving a logic 0 at a first input and having a second input coupled with an output of the first multiplexer , wherein the second multiplexer is controlled by the return from interrupt detection unit ; and a clock controlled register receiving an output signal from the second multiplexer and having an output coupled with a second input of the first multiplexer wherein the output of the register indicates a current interrupt status of the central processing unit . a final stage interrupt detection unit ; a return from interrupt detection unit ; a first multiplexer having a first input receiving a logic 1 at a first input and being controlled by the final stage interrupt detection unit ; a second multiplexer receiving a logic 0 at a first input and having a second input coupled with an output of the first multiplexer , wherein the second multiplexer is controlled by the return from interrupt detection unit ; and a clock controlled register receiving an output signal from the second multiplexer and having an output coupled with a second input of the first multiplexer wherein the output of the register indicates a current interrupt status of the central processing unit . <EOS>