A bus node for a serial, bidirectional, differential two-wire communication bus (DB) comprising a first single-wire bus (DB1) as well as a second single-wire bus (DB2) and a bus master (ECU) connected thereto, wherein the differential two-wire communication bus (DB) has a reference potential from which the potentials of the single-wire buses (DBa, DBb) are different, and wherein information signals are transmitted between the bus master (ECU) and the bus node as a voltage difference between the two single-wire buses (DBa, DBb) via the latter, comprising - a first bus shunt resistor (R2) connected serially with the first single-wire bus (DB1), and - a second bus shunt resistor (R2') connected serially with the second single-wire bus (DB2), - a first addressing current source (Iqj) for determining the bus position of the bus node (BKj) in the two-wire communication bus (DB), which can feed a first addressing current into the first single-wire bus (DBa) of the two-wire communication bus (DB) in a controlled manner, wherein a first total current (ij) through the first bus shunt resistor (R2) of the bus node (BKj) is adapted to be regulated to a predetermined first sum current value (Iref), - a second addressing current source (Iq'j) for determining the bus position of the bus node (BKj) in the two-wire communication bus (DB), which can feed a second addressing current into the second single-wire bus (DBb) of the two-wire communication bus (DB) in a controlled manner, wherein a second total current (ij) through the second bus shunt resistor (R2') of the bus node (BKj) is adapted to be regulated to a predetermined second sum current value (I'reg), - wherein the first addressing current of the first addressing current source (Iqj) of the bus node (BKj) flows through the first bus shunt resistor (R2) of the bus node (BKj), and - wherein the second addressing current of the second addressing current source (Iq'i) of the bus node (BKj) flows through the second bus shunt resistor (R2') of the bus node (BKj). - a first bus shunt resistor (R2) connected serially with the first single-wire bus (DB1), and - a second bus shunt resistor (R2') connected serially with the second single-wire bus (DB2), - a first addressing current source (Iqj) for determining the bus position of the bus node (BKj) in the two-wire communication bus (DB), which can feed a first addressing current into the first single-wire bus (DBa) of the two-wire communication bus (DB) in a controlled manner, wherein a first total current (ij) through the first bus shunt resistor (R2) of the bus node (BKj) is adapted to be regulated to a predetermined first sum current value (Iref), - a second addressing current source (Iq'j) for determining the bus position of the bus node (BKj) in the two-wire communication bus (DB), which can feed a second addressing current into the second single-wire bus (DBb) of the two-wire communication bus (DB) in a controlled manner, wherein a second total current (ij) through the second bus shunt resistor (R2') of the bus node (BKj) is adapted to be regulated to a predetermined second sum current value (I'reg), - wherein the first addressing current of the first addressing current source (Iqj) of the bus node (BKj) flows through the first bus shunt resistor (R2) of the bus node (BKj), and - wherein the second addressing current of the second addressing current source (Iq'i) of the bus node (BKj) flows through the second bus shunt resistor (R2') of the bus node (BKj). <EOS>