A time measurement circuit , comprising: a signal input configured to receive a to-be-tested signal; a delay line including n delay units that are sequentially connected, a first delay unit of the delay line being connected to the signal input to receive the to-be-tested signal from the signal input , the delay line being configured to sequentially transmit a first rising edge of the to-be-tested signal received at the first delay unit from the first delay unit to an n-th delay unit of the delay line in response to the to-be-tested signal being received by the first delay unit, and n being a positive integer larger than two; and a latch connected to the n delay units and configured to latch output signals of the n delay units; characterized in that the time measurement circuit further comprises a logic controller including an input connected to the signal input to receive the to-be-tested signal and an output connected to a k-th delay unit of the n delay units, the logic controller being configured to send a second rising edge received at the input of the logic controller to the k-th delay unit and to have the delay line sequentially transmit the second rising edge from the k-th delay unit to the n-th delay unit in response to the to-be-tested signal being received at the input of the logic controller , and to send a low-level signal to the k-th delay unit and to have the delay line sequentially transmit the low-level signal from the k-th delay unit to the n-th delay unit after the second rising edge is transmitted to the k-th delay unit and before the first rising edge arrives at the k-th delay unit, and 1<k<n. a signal input configured to receive a to-be-tested signal; a delay line including n delay units that are sequentially connected, a first delay unit of the delay line being connected to the signal input to receive the to-be-tested signal from the signal input , the delay line being configured to sequentially transmit a first rising edge of the to-be-tested signal received at the first delay unit from the first delay unit to an n-th delay unit of the delay line in response to the to-be-tested signal being received by the first delay unit, and n being a positive integer larger than two; and a latch connected to the n delay units and configured to latch output signals of the n delay units; characterized in that the time measurement circuit further comprises a logic controller including an input connected to the signal input to receive the to-be-tested signal and an output connected to a k-th delay unit of the n delay units, the logic controller being configured to send a second rising edge received at the input of the logic controller to the k-th delay unit and to have the delay line sequentially transmit the second rising edge from the k-th delay unit to the n-th delay unit in response to the to-be-tested signal being received at the input of the logic controller , and to send a low-level signal to the k-th delay unit and to have the delay line sequentially transmit the low-level signal from the k-th delay unit to the n-th delay unit after the second rising edge is transmitted to the k-th delay unit and before the first rising edge arrives at the k-th delay unit, and 1<k<n. <EOS>