An integrated circuit device, comprising: a first address bus; and an address translation unit, ATU , wherein the integrated circuit is configured for: remapping the first address bus into a first remapped address bus by replacing bit lines of the first address bus with attribute bit lines of an attribute bus, the replacing resulting in substitute bit lines and remaining bit lines of the first address bus, and the first remapped address bus comprising the substitute bit lines and the remaining bit lines of the first address bus, and the first remapped address bus supplying updated first address information; connecting the first remapped address bus to the ATU , the ATU configured to translate the updated first address information into translated address information supplied to a second address bus; and remapping the second address bus into a second remapped address bus by replacing a portion of the second address bus with the bit lines of the first address bus that were replaced by the attribute bit lines, the replacing resulting in restored bit lines and remaining bit lines of the second address bus, the second remapped address bus comprising the restored bit lines and the remaining bit lines of the second address bus, and the second remapped address bus supplying updated translated address information. a first address bus; and an address translation unit, ATU , wherein the integrated circuit is configured for: remapping the first address bus into a first remapped address bus by replacing bit lines of the first address bus with attribute bit lines of an attribute bus, the replacing resulting in substitute bit lines and remaining bit lines of the first address bus, and the first remapped address bus comprising the substitute bit lines and the remaining bit lines of the first address bus, and the first remapped address bus supplying updated first address information; connecting the first remapped address bus to the ATU , the ATU configured to translate the updated first address information into translated address information supplied to a second address bus; and remapping the second address bus into a second remapped address bus by replacing a portion of the second address bus with the bit lines of the first address bus that were replaced by the attribute bit lines, the replacing resulting in restored bit lines and remaining bit lines of the second address bus, the second remapped address bus comprising the restored bit lines and the remaining bit lines of the second address bus, and the second remapped address bus supplying updated translated address information. remapping the first address bus into a first remapped address bus by replacing bit lines of the first address bus with attribute bit lines of an attribute bus, the replacing resulting in substitute bit lines and remaining bit lines of the first address bus, and the first remapped address bus comprising the substitute bit lines and the remaining bit lines of the first address bus, and the first remapped address bus supplying updated first address information; connecting the first remapped address bus to the ATU , the ATU configured to translate the updated first address information into translated address information supplied to a second address bus; and remapping the second address bus into a second remapped address bus by replacing a portion of the second address bus with the bit lines of the first address bus that were replaced by the attribute bit lines, the replacing resulting in restored bit lines and remaining bit lines of the second address bus, the second remapped address bus comprising the restored bit lines and the remaining bit lines of the second address bus, and the second remapped address bus supplying updated translated address information. <EOS>