A protection device , comprising: a first transistor (MN1) configured to receive a first input (VIN) and a first control signal (VINT) and comprising an n-type metal oxide semiconductor field effect transistor, NFET, wherein the first control signal is chosen such that the first transistor is shut off in response to the first input comprising a voltage greater than a predetermined threshold; a voltage level shifter coupled to a terminal of the first transistor, wherein the voltage level shifter comprises a second transistor (MN2), a control terminal of the second transistor coupled to a terminal of the second transistor, a third transistor (MP1) coupled to the second transistor, and a first resistor (R1) coupled to the third transistor and wherein the second transistor comprises a p-type metal oxide semiconductor field effect transistor, PFET, and the third transistor comprises an NFET; a current mirror coupled to the first resistor at a first node , wherein the current mirror comprises a fourth transistor (MP2) and a fifth transistor (MP3) coupled to the fourth transistor, wherein the fourth transistor and fifth transistor are configured to receive a first control signal and comprise PFETs; a regulator coupled to the fifth transistor at a second node, wherein the regulator comprises a sixth transistor (MN3) coupled to a seventh transistor (MP4), a second resistor (R2) coupled to the seventh transistor, wherein the sixth transistor is configured to receive a second control signal and comprises an NFET and the seventh transistor comprises a PFET; and an eighth transistor (MN0) coupled to the first node and configured to receive the second control signal from the first node and to receive the first input, wherein the eighth transistor comprises an NFET. a first transistor (MN1) configured to receive a first input (VIN) and a first control signal (VINT) and comprising an n-type metal oxide semiconductor field effect transistor, NFET, wherein the first control signal is chosen such that the first transistor is shut off in response to the first input comprising a voltage greater than a predetermined threshold; a voltage level shifter coupled to a terminal of the first transistor, wherein the voltage level shifter comprises a second transistor (MN2), a control terminal of the second transistor coupled to a terminal of the second transistor, a third transistor (MP1) coupled to the second transistor, and a first resistor (R1) coupled to the third transistor and wherein the second transistor comprises a p-type metal oxide semiconductor field effect transistor, PFET, and the third transistor comprises an NFET; a current mirror coupled to the first resistor at a first node , wherein the current mirror comprises a fourth transistor (MP2) and a fifth transistor (MP3) coupled to the fourth transistor, wherein the fourth transistor and fifth transistor are configured to receive a first control signal and comprise PFETs; a regulator coupled to the fifth transistor at a second node, wherein the regulator comprises a sixth transistor (MN3) coupled to a seventh transistor (MP4), a second resistor (R2) coupled to the seventh transistor, wherein the sixth transistor is configured to receive a second control signal and comprises an NFET and the seventh transistor comprises a PFET; and an eighth transistor (MN0) coupled to the first node and configured to receive the second control signal from the first node and to receive the first input, wherein the eighth transistor comprises an NFET. <EOS>