An apparatus, comprising: one set of memory cells in a block (BLKO, BLK1, BLK2 and BLK3) of a flash memory device, the one set of memory cells arranged in NAND strings (700n-7003n, 710n-713n, 720n-723n and 730n-733n), each NAND string comprising data memory cells (704, 705, 706, 707, 708, 709, 710, 711, 712, 713 and 714; 724, 725, 726, 727, 728, 729, 730, 731, 732, 733 and 734; 744, 745, 746, 747, 748, 749, 750, 751, 752, 753 and 754; 764, 765, 766, 767, 768, 769, 770, 771, 772, 773 and 774) and a dummy memory cell (715 and 716; 735 and 736; 755 and 756; 775 and 776); and a control circuit (110, 112, 114, 116, 122, 128, 132, SBb, SB2,...,SBp); the control circuit is configured to determine when a number of program-erase cycles of the block reaches a threshold and in response to the number of program-erase cycles reaching the threshold, to measure an endurance of the block, perform an evaluation of threshold voltages of the dummy memory cells and based on the evaluation, decide whether to perform a corrective action for the data memory cells, wherein: the control circuit, to perform the evaluation, is configured to determine a number of the dummy memory cells having a threshold voltage below a demarcation voltage (VdemLT) used to sense the dummy memory cells; characterised in that : the control circuit, to perform the corrective action, is configured to lower a read voltage (VrG) for a highest programmed data state (G) in a read operation involving selected data memory cells of the one set of memory cells if the number of the dummy memory cells having a threshold voltage below the demarcation voltage (VdemLT) is at least one number (N1) but no more than another number (N2), and to identify the block as being bad so that subsequent programming or erasing of the block is prevented if another number (N2) of the dummy memory cells have a threshold voltage below the demarcation voltage, wherein the one number (N1) is less than the another number (N2). one set of memory cells in a block (BLKO, BLK1, BLK2 and BLK3) of a flash memory device, the one set of memory cells arranged in NAND strings (700n-7003n, 710n-713n, 720n-723n and 730n-733n), each NAND string comprising data memory cells (704, 705, 706, 707, 708, 709, 710, 711, 712, 713 and 714; 724, 725, 726, 727, 728, 729, 730, 731, 732, 733 and 734; 744, 745, 746, 747, 748, 749, 750, 751, 752, 753 and 754; 764, 765, 766, 767, 768, 769, 770, 771, 772, 773 and 774) and a dummy memory cell (715 and 716; 735 and 736; 755 and 756; 775 and 776); and a control circuit (110, 112, 114, 116, 122, 128, 132, SBb, SB2,...,SBp); the control circuit is configured to determine when a number of program-erase cycles of the block reaches a threshold and in response to the number of program-erase cycles reaching the threshold, to measure an endurance of the block, perform an evaluation of threshold voltages of the dummy memory cells and based on the evaluation, decide whether to perform a corrective action for the data memory cells, wherein: the control circuit, to perform the evaluation, is configured to determine a number of the dummy memory cells having a threshold voltage below a demarcation voltage (VdemLT) used to sense the dummy memory cells; characterised in that : the control circuit, to perform the corrective action, is configured to lower a read voltage (VrG) for a highest programmed data state (G) in a read operation involving selected data memory cells of the one set of memory cells if the number of the dummy memory cells having a threshold voltage below the demarcation voltage (VdemLT) is at least one number (N1) but no more than another number (N2), and to identify the block as being bad so that subsequent programming or erasing of the block is prevented if another number (N2) of the dummy memory cells have a threshold voltage below the demarcation voltage, wherein the one number (N1) is less than the another number (N2). <EOS>