A method performed with a memory device including storage memory and a memory processing apparatus , with the memory processing apparatus including at least one execution unit , a packet parser , and a packet generator , and the method comprising: receiving and parsing a set of instructions at a memory processing apparatus using the packet parser , the instructions comprising a command selected from search, sort or compare; executing the set of instructions using the at least one execution unit , to attempt to retrieve data from the storage memory of the memory device , wherein the at least one execution units comprises a plurality of arithmetic logic units "ALUs" and a multiplexing function coupled between outputs of at least two of the plurality of the arithmetic logic units , the at least two ALUs being configured to receive operands and an operator, an operator being a command input for an ALU to apply to its input operands, the operands and operator being provided by the set of instructions, the multiplexing function selecting the output of which ALU to output by a selection signal applied to the multiplexing function , the selection signal being output by a further ALU ; combining, into a packet using the packet generator , the set of instructions with any data retrieved from the storage memory of the memory device in response to the execution of the set of instructions by the at least one execution unit ; and transmitting the packet using the packet generator , wherein the packet is transferred from the memory processing apparatus to a controller connected to the memory device , wherein the at least one execution unit , the packet parser , and the packet generator of the memory processing apparatus are located within a same hardware component as the storage memory . receiving and parsing a set of instructions at a memory processing apparatus using the packet parser , the instructions comprising a command selected from search, sort or compare; executing the set of instructions using the at least one execution unit , to attempt to retrieve data from the storage memory of the memory device , wherein the at least one execution units comprises a plurality of arithmetic logic units "ALUs" and a multiplexing function coupled between outputs of at least two of the plurality of the arithmetic logic units , the at least two ALUs being configured to receive operands and an operator, an operator being a command input for an ALU to apply to its input operands, the operands and operator being provided by the set of instructions, the multiplexing function selecting the output of which ALU to output by a selection signal applied to the multiplexing function , the selection signal being output by a further ALU ; combining, into a packet using the packet generator , the set of instructions with any data retrieved from the storage memory of the memory device in response to the execution of the set of instructions by the at least one execution unit ; and transmitting the packet using the packet generator , wherein the packet is transferred from the memory processing apparatus to a controller connected to the memory device , wherein the at least one execution unit , the packet parser , and the packet generator of the memory processing apparatus are located within a same hardware component as the storage memory . <EOS>