A data access apparatus using a memory device to map addresses, comprising: an 8-bit memory device having a plurality of addresses so that data is readable or writable; a data division unit configured to divide 24-bit data, an address mapping unit configured to map addresses of the 8-bit memory device with respective predetermined addresses, a data mapping unit configured to map segments of data divided by the data division unit with the respective predetermined addresses, and a control unit, the data division unit is configured to divide the 24-bit data into high-order 8-bit data, middle-order 8-bit data, and low-order 8-bit data; characterized in that the address mapping unit is configured to divide the addresses of the memory device into first region, second region and third region having consecutive addresses respectively, and to map the plurality of addresses of the 8-bit memory device with respective predetermined addresses in the first, second, and third regions such that they one-to-one correspond to each other; that the data mapping unit is configured to map the high-order 8-bit data with predetermined specific addresses in the first region, the middle-order 8-bit data with predetermined specific addresses in the second region, and the low-order 8-bit data with predetermined specific addresses in the third region, wherein the predetermined specific addresses in the first to third region are located in the same order in the first to third regions respectively such that they are spaced apart at a predetermined address interval; and that the control unit is configured to control the first to third segments of data such that the first to third segments of data are stored in the addresses of the 8-bit memory device mapped with the respective specific addresses in the first to third regions. an 8-bit memory device having a plurality of addresses so that data is readable or writable; a data division unit configured to divide 24-bit data, an address mapping unit configured to map addresses of the 8-bit memory device with respective predetermined addresses, a data mapping unit configured to map segments of data divided by the data division unit with the respective predetermined addresses, and a control unit, the data division unit is configured to divide the 24-bit data into high-order 8-bit data, middle-order 8-bit data, and low-order 8-bit data; characterized in that the address mapping unit is configured to divide the addresses of the memory device into first region, second region and third region having consecutive addresses respectively, and to map the plurality of addresses of the 8-bit memory device with respective predetermined addresses in the first, second, and third regions such that they one-to-one correspond to each other; that the data mapping unit is configured to map the high-order 8-bit data with predetermined specific addresses in the first region, the middle-order 8-bit data with predetermined specific addresses in the second region, and the low-order 8-bit data with predetermined specific addresses in the third region, wherein the predetermined specific addresses in the first to third region are located in the same order in the first to third regions respectively such that they are spaced apart at a predetermined address interval; and that the control unit is configured to control the first to third segments of data such that the first to third segments of data are stored in the addresses of the 8-bit memory device mapped with the respective specific addresses in the first to third regions. <EOS>