An apparatus comprising: a set of wire input nodes , each wire input node connected to a respective wire of a multi-wire bus; at least one set of differential data signal output nodes (Sub 0 - , Sub 0 + , Sub 1 - , Sub 1 + , Sub 2 - , Sub 2 + ); characterized in that the apparatus further comprising: a plurality of sets of parallel-connected signal path circuits , each set of parallel-connected signal path circuits configured to selectively connect a respective wire input node of the set of wire input nodes to a corresponding data signal output node of the at least one set of differential data signal output nodes (Sub 0 - , Sub 0 + , Sub 1 - , Sub 1 + , Sub 2 - , Sub 2 + ), each signal path circuit of the respective set of parallel-connected signal path circuits comprising: a switching element (S21, 1410, 1420, 1430) for selectively enabling a signal path to connect the respective wire input node to the corresponding data signal output node; and a resistive element (R1, R2, R3, R4, 1440) and a localized electrostatic discharge, ESD, protection circuit connected between the given wire input node and the switching element (S21, 1410, 1420, 1430) to discharge a portion of a voltage pulse on the respective wire to one or more metallic planes via the localized ESD protection circuits as a discharge current through the resistive element (R1, R2, R3, R4, 1440). a set of wire input nodes , each wire input node connected to a respective wire of a multi-wire bus; at least one set of differential data signal output nodes (Sub 0 - , Sub 0 + , Sub 1 - , Sub 1 + , Sub 2 - , Sub 2 + ); characterized in that the apparatus further comprising: a plurality of sets of parallel-connected signal path circuits , each set of parallel-connected signal path circuits configured to selectively connect a respective wire input node of the set of wire input nodes to a corresponding data signal output node of the at least one set of differential data signal output nodes (Sub 0 - , Sub 0 + , Sub 1 - , Sub 1 + , Sub 2 - , Sub 2 + ), each signal path circuit of the respective set of parallel-connected signal path circuits comprising: a switching element (S21, 1410, 1420, 1430) for selectively enabling a signal path to connect the respective wire input node to the corresponding data signal output node; and a resistive element (R1, R2, R3, R4, 1440) and a localized electrostatic discharge, ESD, protection circuit connected between the given wire input node and the switching element (S21, 1410, 1420, 1430) to discharge a portion of a voltage pulse on the respective wire to one or more metallic planes via the localized ESD protection circuits as a discharge current through the resistive element (R1, R2, R3, R4, 1440). a switching element (S21, 1410, 1420, 1430) for selectively enabling a signal path to connect the respective wire input node to the corresponding data signal output node; and a resistive element (R1, R2, R3, R4, 1440) and a localized electrostatic discharge, ESD, protection circuit connected between the given wire input node and the switching element (S21, 1410, 1420, 1430) to discharge a portion of a voltage pulse on the respective wire to one or more metallic planes via the localized ESD protection circuits as a discharge current through the resistive element (R1, R2, R3, R4, 1440). <EOS>