A packaged electronic system comprising: a slab of low-grade silicon, l-g-Si, having a first thickness and a surface in a first plane , the slab configured as a ridge in the first plane framing a depression including a recessed central area in a second plane spaced from the first plane by a first depth , the ridge and the central area covered by a metal layer patterned into pads for contacting transistor terminals, the pads of the central area grouped into an inner set and a peripheral set; a first semiconductor chip having a flat first side and an opposite flat second side , and a second thickness smaller than the first thickness , the first chip including a transistor having terminals on the first and the second side, the terminals of the first chip side attached to respective pads of the inner set of the central area of the 1-g-Si slab , creating a sub-assembly wherein the terminals of the second chip side face towards the first plane ; a second semiconductor chip having a flat third side and an opposite contoured fourth side , and a third thickness smaller than the first thickness but greater than the second thickness , the fourth side configured as a ridge in a third plane framing a depression including a flat central area in a parallel fourth plane recessed from the third plane by a second depth smaller than the first depth and accomodating the first chip , the fourth side uniformly metallized, the second chip including a transistor having terminals on the third and the fourth side; and the metallized depressed central area of the fourth side attached to the terminals on the second side of the first chip , and the metallized ridges of the second chip attached to the pads of the peripheral set of the central 1-g-Si area, so the transistor terminals on the third side of the second chip are co-planar with the metal layer on the ridges of the respective l-g-Si slab . a slab of low-grade silicon, l-g-Si, having a first thickness and a surface in a first plane , the slab configured as a ridge in the first plane framing a depression including a recessed central area in a second plane spaced from the first plane by a first depth , the ridge and the central area covered by a metal layer patterned into pads for contacting transistor terminals, the pads of the central area grouped into an inner set and a peripheral set; a first semiconductor chip having a flat first side and an opposite flat second side , and a second thickness smaller than the first thickness , the first chip including a transistor having terminals on the first and the second side, the terminals of the first chip side attached to respective pads of the inner set of the central area of the 1-g-Si slab , creating a sub-assembly wherein the terminals of the second chip side face towards the first plane ; a second semiconductor chip having a flat third side and an opposite contoured fourth side , and a third thickness smaller than the first thickness but greater than the second thickness , the fourth side configured as a ridge in a third plane framing a depression including a flat central area in a parallel fourth plane recessed from the third plane by a second depth smaller than the first depth and accomodating the first chip , the fourth side uniformly metallized, the second chip including a transistor having terminals on the third and the fourth side; and the metallized depressed central area of the fourth side attached to the terminals on the second side of the first chip , and the metallized ridges of the second chip attached to the pads of the peripheral set of the central 1-g-Si area, so the transistor terminals on the third side of the second chip are co-planar with the metal layer on the ridges of the respective l-g-Si slab . <EOS>