A semiconductor structure, comprising: a substrate; a plurality of alternating first (106; 206; 306) and second (112; 224; 324) conductive line types disposed along a same direction of a back end of line, BEOL, metallization layer disposed in an inter-layer dielectric (102; 202; 302), ILD, layer disposed above the substrate; a dielectric layer (110; 216; 316) disposed on an uppermost surface of the first conductive line types (106; 206; 306) but not along sidewalls of the first conductive line types (106; 206; 306), and disposed along sidewalls of the second conductive line types (112; 224; 324) but not on an uppermost surface of the second conductive line types (112; 224; 324); a first hardmask layer (114; 232; 332) disposed over the first conductive line types (106; 206; 306) but not over the second conductive line types; a second hardmask layer (116; 234; 334) disposed over the second conductive line types (112; 224; 324) but not over the first conductive line types (106; 206; 306), wherein the first and second hardmask layers differ in composition; and a conductive via structure (240; 340) disposed in an opening in the first hardmask layer (114; 232; 332) and connected to one of the first conductive line types (106; 206; 306), wherein a portion of the conductive via structure (240; 340) is disposed on a portion of the second hardmask layer (116; 234; 334); or a conductive via structure (240; 340) disposed in an opening in the second hardmask layer (116; 234; 334) and connected to one of the second conductive line types (112; 224; 324), wherein a portion of the conductive via structure (240; 340) is disposed on a portion of the first hardmask layer (114; 232; 332). a substrate; a plurality of alternating first (106; 206; 306) and second (112; 224; 324) conductive line types disposed along a same direction of a back end of line, BEOL, metallization layer disposed in an inter-layer dielectric (102; 202; 302), ILD, layer disposed above the substrate; a dielectric layer (110; 216; 316) disposed on an uppermost surface of the first conductive line types (106; 206; 306) but not along sidewalls of the first conductive line types (106; 206; 306), and disposed along sidewalls of the second conductive line types (112; 224; 324) but not on an uppermost surface of the second conductive line types (112; 224; 324); a first hardmask layer (114; 232; 332) disposed over the first conductive line types (106; 206; 306) but not over the second conductive line types; a second hardmask layer (116; 234; 334) disposed over the second conductive line types (112; 224; 324) but not over the first conductive line types (106; 206; 306), wherein the first and second hardmask layers differ in composition; and a conductive via structure (240; 340) disposed in an opening in the first hardmask layer (114; 232; 332) and connected to one of the first conductive line types (106; 206; 306), wherein a portion of the conductive via structure (240; 340) is disposed on a portion of the second hardmask layer (116; 234; 334); or a conductive via structure (240; 340) disposed in an opening in the second hardmask layer (116; 234; 334) and connected to one of the second conductive line types (112; 224; 324), wherein a portion of the conductive via structure (240; 340) is disposed on a portion of the first hardmask layer (114; 232; 332). <EOS>