A read operation circuit used in a semiconductor memory , wherein the semiconductor memory comprises a Data Queue, DQ, port , a Data Bus Inversion, DBI, port , and a memory bank , and the read operation circuit comprises: a DBI encoder connected to the memory bank , wherein the DBI encoder is configured to read out read data from the memory bank , and determine, according to a number of bits of low data in the read data, whether to invert the read data to output global bus data for transmission through a global bus and DBI data for transmission through a DBI signal line, the DBI port being configured to receive the DBI data; and a parallel-to-serial conversion circuit connected between the DQ port and the DBI encoder through the global bus and configured to perform parallel-to-serial conversion on the global bus data to generate output data of the DQ port , characterized in that , the read operation circuit further comprises: a precharge module comprising a plurality of P-channel Metal Oxide Semiconductor, PMOS, transistors and a plurality of hold circuits , wherein a gate of each of the plurality of PMOS transistors is connected to a precharge signal line, and a drain of each of the plurality of PMOS transistors is connected to the global bus, so as to set an initial state of the global bus to High; and an input terminal and an output terminal of each of the plurality of hold circuits is connected to the global bus to form a positive feedback circuit configured to latch the global bus at High; and a pull-down module comprising a plurality of N-channel Metal Oxide Semiconductor, NMOS, transistors , a gate of each of the plurality of NMOS transistors being connected to the memory bank , and a drain of each of the plurality of NMOS transistors being connected to the global bus, wherein when the global bus needs to be inverted to Low, the NMOS transistor is configured to pull down the global bus to Low and the hold circuit is further configured to latch the global bus at Low through the positive feedback circuit after the global bus is pulled down to Low. a DBI encoder connected to the memory bank , wherein the DBI encoder is configured to read out read data from the memory bank , and determine, according to a number of bits of low data in the read data, whether to invert the read data to output global bus data for transmission through a global bus and DBI data for transmission through a DBI signal line, the DBI port being configured to receive the DBI data; and a parallel-to-serial conversion circuit connected between the DQ port and the DBI encoder through the global bus and configured to perform parallel-to-serial conversion on the global bus data to generate output data of the DQ port , characterized in that , the read operation circuit further comprises: a precharge module comprising a plurality of P-channel Metal Oxide Semiconductor, PMOS, transistors and a plurality of hold circuits , wherein a gate of each of the plurality of PMOS transistors is connected to a precharge signal line, and a drain of each of the plurality of PMOS transistors is connected to the global bus, so as to set an initial state of the global bus to High; and an input terminal and an output terminal of each of the plurality of hold circuits is connected to the global bus to form a positive feedback circuit configured to latch the global bus at High; and a pull-down module comprising a plurality of N-channel Metal Oxide Semiconductor, NMOS, transistors , a gate of each of the plurality of NMOS transistors being connected to the memory bank , and a drain of each of the plurality of NMOS transistors being connected to the global bus, wherein when the global bus needs to be inverted to Low, the NMOS transistor is configured to pull down the global bus to Low and the hold circuit is further configured to latch the global bus at Low through the positive feedback circuit after the global bus is pulled down to Low. <EOS>