A display device comprising: a display area (DA) comprising pixels (SP); a fan-out area (FOA) disposed on a side of the display area (DA); a pad area (PDA) disposed on a side of the fan-out area (FOA); a display driver electrically connected to the pad area (PDA) and driving the pixels (SP); a metal layer (BML) disposed on a substrate (SUB); a data line (DL), a first voltage line (VDDL), and a second voltage line (VSSL) extending in a first direction (x-axis direction) in the metal layer (BML) in the display area (DA); a fan-out line (FOL) electrically connecting the data line (DL) to the display driver in the metal layer (BML) in the fan-out area (FOA); a gate line (GL) disposed on the metal layer (BML) in the display area (DA) and extending in a second direction (y-axis direction) intersecting the first direction (x-axis direction); a source-drain layer (SDL) disposed on the gate line (GL); and an electrode layer (RML) disposed on the source-drain layer (SDL), wherein the first voltage line (VDDL) comprises a first plate portion (SDP) disposed in the source-drain layer (SDL) in the fan-out area (FOA), such that the first voltage line (VDDL) extends in the fan-out area (FOA) through the source-drain layer (SDL) and extends in the display area (DA) through the metal layer (BML); and the second voltage line (VSSL) comprises a second plate portion (RMP) disposed in the electrode layer (RML) in the fan-out area (FOA), such that the second voltage line (VSSL) extends in the fan-out area (FOA) through the electrode layer (RML) and extends in the display area (DA) through the metal layer (BML). a display area (DA) comprising pixels (SP); a fan-out area (FOA) disposed on a side of the display area (DA); a pad area (PDA) disposed on a side of the fan-out area (FOA); a display driver electrically connected to the pad area (PDA) and driving the pixels (SP); a metal layer (BML) disposed on a substrate (SUB); a data line (DL), a first voltage line (VDDL), and a second voltage line (VSSL) extending in a first direction (x-axis direction) in the metal layer (BML) in the display area (DA); a fan-out line (FOL) electrically connecting the data line (DL) to the display driver in the metal layer (BML) in the fan-out area (FOA); a gate line (GL) disposed on the metal layer (BML) in the display area (DA) and extending in a second direction (y-axis direction) intersecting the first direction (x-axis direction); a source-drain layer (SDL) disposed on the gate line (GL); and an electrode layer (RML) disposed on the source-drain layer (SDL), wherein the first voltage line (VDDL) comprises a first plate portion (SDP) disposed in the source-drain layer (SDL) in the fan-out area (FOA), such that the first voltage line (VDDL) extends in the fan-out area (FOA) through the source-drain layer (SDL) and extends in the display area (DA) through the metal layer (BML); and the second voltage line (VSSL) comprises a second plate portion (RMP) disposed in the electrode layer (RML) in the fan-out area (FOA), such that the second voltage line (VSSL) extends in the fan-out area (FOA) through the electrode layer (RML) and extends in the display area (DA) through the metal layer (BML). <EOS>