A chip, comprising: a core circuit , wherein the core circuit is configured to operate from a power supply voltage (VDD); and a receiver , coupled to the core circuit , wherein the receiver has an input (VIN); wherein the receiver includes a hysteresis circuit comprising: an inverter (CK1), wherein the inverter (CK1) is configured to operate from an overdrive voltage that is twice the power supply voltage (VDD), wherein the inverter has an output (VOUT), wherein the inverter (CK1) comprises a pull-up path (M1, M3) between the overdrive voltage and the output (VOUT), and wherein the inverter (CK1) comprises a pull-down path (M2, M4) between the output (VOUT) and a ground (GND); a latch (CK2, CK3) coupled to the inverter (CK1) for positive feedback control; a protection circuit (CK4, CK5) comprising a first sub-circuit (CK4) biased by a first bias voltage (VDDA) that is lower than the power supply voltage (VDD), and a second sub-circuit (CK5) biased by a second bias voltage (VDDB) that is greater than the power supply voltage (VDD); wherein, through the first sub-circuit (CK4) of the protection circuit, the input (VIN) is coupled to the inverter (CK1) to control the pull-up path of the inverter (CK1); and wherein, through the second sub-circuit (CK5) of the protection circuit, the input (VIN) is coupled to the inverter (CK1) to control the pull-down path of the inverter. a core circuit , wherein the core circuit is configured to operate from a power supply voltage (VDD); and a receiver , coupled to the core circuit , wherein the receiver has an input (VIN); wherein the receiver includes a hysteresis circuit comprising: an inverter (CK1), wherein the inverter (CK1) is configured to operate from an overdrive voltage that is twice the power supply voltage (VDD), wherein the inverter has an output (VOUT), wherein the inverter (CK1) comprises a pull-up path (M1, M3) between the overdrive voltage and the output (VOUT), and wherein the inverter (CK1) comprises a pull-down path (M2, M4) between the output (VOUT) and a ground (GND); a latch (CK2, CK3) coupled to the inverter (CK1) for positive feedback control; a protection circuit (CK4, CK5) comprising a first sub-circuit (CK4) biased by a first bias voltage (VDDA) that is lower than the power supply voltage (VDD), and a second sub-circuit (CK5) biased by a second bias voltage (VDDB) that is greater than the power supply voltage (VDD); wherein, through the first sub-circuit (CK4) of the protection circuit, the input (VIN) is coupled to the inverter (CK1) to control the pull-up path of the inverter (CK1); and wherein, through the second sub-circuit (CK5) of the protection circuit, the input (VIN) is coupled to the inverter (CK1) to control the pull-down path of the inverter. an inverter (CK1), wherein the inverter (CK1) is configured to operate from an overdrive voltage that is twice the power supply voltage (VDD), wherein the inverter has an output (VOUT), wherein the inverter (CK1) comprises a pull-up path (M1, M3) between the overdrive voltage and the output (VOUT), and wherein the inverter (CK1) comprises a pull-down path (M2, M4) between the output (VOUT) and a ground (GND); a latch (CK2, CK3) coupled to the inverter (CK1) for positive feedback control; a protection circuit (CK4, CK5) comprising a first sub-circuit (CK4) biased by a first bias voltage (VDDA) that is lower than the power supply voltage (VDD), and a second sub-circuit (CK5) biased by a second bias voltage (VDDB) that is greater than the power supply voltage (VDD); wherein, through the first sub-circuit (CK4) of the protection circuit, the input (VIN) is coupled to the inverter (CK1) to control the pull-up path of the inverter (CK1); and wherein, through the second sub-circuit (CK5) of the protection circuit, the input (VIN) is coupled to the inverter (CK1) to control the pull-down path of the inverter. <EOS>