A system comprising: a memory ; and a processor including: at least one core to execute operations of a loop; means for receiving a pipelined schedule of a loop that comprises a plurality of iterations to be executed in parallel according to the pipelined schedule, each iteration including an assignment operation to assign a value of a variable associated with the iteration to a register, and a store operation to store contents of the register to the memory; stage insertion means for adding a delay stage to the loop to increase a lifetime of a register associated with a first variable of a first iteration of the loop and to delay storage of contents of the register; means for renaming the register in each iteration of a plurality of iterations of the loop, from the register to a respective different register; means for inserting compensation code into the loop, wherein the compensation code is for re-executing a store operation for storing contents of the register of an (N-S+M) th iteration of the loop responsive to an exception in an M th stage of an N th iteration of the loop, wherein each iteration of the loop comprises S stages , thereby recovering a live-out value of the register associated with the (N-S+M) th iteration of the loop responsive to the exception. a memory ; and a processor including: at least one core to execute operations of a loop; means for receiving a pipelined schedule of a loop that comprises a plurality of iterations to be executed in parallel according to the pipelined schedule, each iteration including an assignment operation to assign a value of a variable associated with the iteration to a register, and a store operation to store contents of the register to the memory; stage insertion means for adding a delay stage to the loop to increase a lifetime of a register associated with a first variable of a first iteration of the loop and to delay storage of contents of the register; means for renaming the register in each iteration of a plurality of iterations of the loop, from the register to a respective different register; means for inserting compensation code into the loop, wherein the compensation code is for re-executing a store operation for storing contents of the register of an (N-S+M) th iteration of the loop responsive to an exception in an M th stage of an N th iteration of the loop, wherein each iteration of the loop comprises S stages , thereby recovering a live-out value of the register associated with the (N-S+M) th iteration of the loop responsive to the exception. at least one core to execute operations of a loop; means for receiving a pipelined schedule of a loop that comprises a plurality of iterations to be executed in parallel according to the pipelined schedule, each iteration including an assignment operation to assign a value of a variable associated with the iteration to a register, and a store operation to store contents of the register to the memory; stage insertion means for adding a delay stage to the loop to increase a lifetime of a register associated with a first variable of a first iteration of the loop and to delay storage of contents of the register; means for renaming the register in each iteration of a plurality of iterations of the loop, from the register to a respective different register; means for inserting compensation code into the loop, wherein the compensation code is for re-executing a store operation for storing contents of the register of an (N-S+M) th iteration of the loop responsive to an exception in an M th stage of an N th iteration of the loop, wherein each iteration of the loop comprises S stages , thereby recovering a live-out value of the register associated with the (N-S+M) th iteration of the loop responsive to the exception. <EOS>