A method for processing a test signal for inputting into a system configured to accentuate amplitude or timing errors of a digital-to-analog converter, DAC , having a plurality of DAC bit cells, the method comprising: providing the test signal, d[k]; generating a first version of the test signal corresponding to the weight of a first DAC bit cell and a second version of the test signal corresponding to the weight of a second DAC bit cell, wherein said generating comprises multiplying the test signal by a ratio of the weight (w2) of the second DAC bit cell and the weight (w1) of the first DAC bit cell to generate the first version of the test signal, the plurality of DAC bit cells comprising the first DAC bit cell and the second DAC bit cell , wherein one of the first version of the test signal or the second version of the test signal is inverted with respect to the other of the first version of the test signal or the second version of the test signal; encoding, using a digital noise shaper, the first version of the test signal and the second version of the test signal as two-level bit streams to generate a first test input signal and a second test input signal respectively, wherein the digital noise shaper comprises a delta-sigma encoder and wherein the said encoding comprises encoding each of the first version of the test signal and the second version of the test signal as a delta-sigma bit stream, wherein, the first test input signal and the second test input signal have equal amplitude and inverse polarity; and providing the first test input signal and the second test input signal to the first DAC bit cell and the second DAC bit cell , respectively, whereby to enable the amplitude or timing error of the second DAC bit cell , with respect to the first DAC bit cell , to be accentuated. providing the test signal, d[k]; generating a first version of the test signal corresponding to the weight of a first DAC bit cell and a second version of the test signal corresponding to the weight of a second DAC bit cell, wherein said generating comprises multiplying the test signal by a ratio of the weight (w2) of the second DAC bit cell and the weight (w1) of the first DAC bit cell to generate the first version of the test signal, the plurality of DAC bit cells comprising the first DAC bit cell and the second DAC bit cell , wherein one of the first version of the test signal or the second version of the test signal is inverted with respect to the other of the first version of the test signal or the second version of the test signal; encoding, using a digital noise shaper, the first version of the test signal and the second version of the test signal as two-level bit streams to generate a first test input signal and a second test input signal respectively, wherein the digital noise shaper comprises a delta-sigma encoder and wherein the said encoding comprises encoding each of the first version of the test signal and the second version of the test signal as a delta-sigma bit stream, wherein, the first test input signal and the second test input signal have equal amplitude and inverse polarity; and providing the first test input signal and the second test input signal to the first DAC bit cell and the second DAC bit cell , respectively, whereby to enable the amplitude or timing error of the second DAC bit cell , with respect to the first DAC bit cell , to be accentuated. <EOS>