An integrated circuit for an electronic pen, the circuit comprising: a first terminal (C1P) that is configured to be connected to a resonant circuit, the resonant circuit including a first capacitor (VC) and a coil (L), the first terminal being configured to be connected to a first end of the first capacitor; a second terminal (C1M) that is configured to be connected to a second end of the first capacitor; a plurality of second capacitors (C a ) connected in parallel between the first and second terminals; and a control circuit which, in operation, is adapted to change a capacitance of each of the second capacitors; the integrated circuit characterized in further comprising: a plurality of first switches (S a ), each of the first switches being connected to an associated one of the second capacitors; and a plurality of second switches (S b ), each of the second switches being connected to an associated one of the second capacitors, wherein the second capacitors each have a laminated structure including: a substrate formed of an n-type semiconductor or of an p-type semiconductor, an insulating film , a floating gate , and a gate electrode , wherein the first switches each include a common terminal, the common terminal of the first switches being connected to the gate electrode of the associated second capacitor, the second switches each include a common terminal, the common terminal of the second switches being connected to the substrate of the associated second capacitor. a first terminal (C1P) that is configured to be connected to a resonant circuit, the resonant circuit including a first capacitor (VC) and a coil (L), the first terminal being configured to be connected to a first end of the first capacitor; a second terminal (C1M) that is configured to be connected to a second end of the first capacitor; a plurality of second capacitors (C a ) connected in parallel between the first and second terminals; and a control circuit which, in operation, is adapted to change a capacitance of each of the second capacitors; the integrated circuit characterized in further comprising: a plurality of first switches (S a ), each of the first switches being connected to an associated one of the second capacitors; and a plurality of second switches (S b ), each of the second switches being connected to an associated one of the second capacitors, wherein the second capacitors each have a laminated structure including: a substrate formed of an n-type semiconductor or of an p-type semiconductor, an insulating film , a floating gate , and a gate electrode , wherein the first switches each include a common terminal, the common terminal of the first switches being connected to the gate electrode of the associated second capacitor, the second switches each include a common terminal, the common terminal of the second switches being connected to the substrate of the associated second capacitor. a substrate formed of an n-type semiconductor or of an p-type semiconductor, an insulating film , a floating gate , and a gate electrode , wherein the first switches each include a common terminal, the common terminal of the first switches being connected to the gate electrode of the associated second capacitor, the second switches each include a common terminal, the common terminal of the second switches being connected to the substrate of the associated second capacitor. <EOS>