A memory device, comprising: a plurality of memory cells arranged in rows and columns, wherein each of the memory cells includes: spaced apart source and drain regions in a semiconductor substrate , with a channel region of the semiconductor substrate extending there between, a floating gate disposed over and insulated from a first portion of the channel region, and a control gate disposed over and insulated from a second portion of the channel region; a plurality of word lines each directly connected to the control gates for an entire one of the rows of the memory cells; a plurality of bit lines each directly connected to the drain regions for an entire one of the columns of the memory cells; a word line driver connected to the word lines; a bit line driver connected to the bit lines; a plurality of word line switches each disposed on one of the word lines for selectively connecting and disconnecting the control gates for an entire one of the rows of the memory cells to and from the word line driver; a plurality of bit line switches each disposed on one of the bit lines for selectively connecting and disconnecting the drain regions for an entire one of the columns of the memory cells to and from the bit line driver; and a controller configured to control, during an analog operation to manage peak current demands of the word line driver and the bit line driver, the plurality of word line switches to connect the control gates in some but not all of the rows of memory cells to the word line driver at a first point in time, and configured to control the plurality of bit line switches to connect the drain regions in some but not all of the columns of memory cells to the bit line driver at a second point in time. a plurality of memory cells arranged in rows and columns, wherein each of the memory cells includes: spaced apart source and drain regions in a semiconductor substrate , with a channel region of the semiconductor substrate extending there between, a floating gate disposed over and insulated from a first portion of the channel region, and a control gate disposed over and insulated from a second portion of the channel region; spaced apart source and drain regions in a semiconductor substrate , with a channel region of the semiconductor substrate extending there between, a floating gate disposed over and insulated from a first portion of the channel region, and a control gate disposed over and insulated from a second portion of the channel region; a plurality of word lines each directly connected to the control gates for an entire one of the rows of the memory cells; a plurality of bit lines each directly connected to the drain regions for an entire one of the columns of the memory cells; a word line driver connected to the word lines; a bit line driver connected to the bit lines; a plurality of word line switches each disposed on one of the word lines for selectively connecting and disconnecting the control gates for an entire one of the rows of the memory cells to and from the word line driver; a plurality of bit line switches each disposed on one of the bit lines for selectively connecting and disconnecting the drain regions for an entire one of the columns of the memory cells to and from the bit line driver; and a controller configured to control, during an analog operation to manage peak current demands of the word line driver and the bit line driver, the plurality of word line switches to connect the control gates in some but not all of the rows of memory cells to the word line driver at a first point in time, and configured to control the plurality of bit line switches to connect the drain regions in some but not all of the columns of memory cells to the bit line driver at a second point in time. <EOS>