A device , comprising: a substrate an input terminal and an output terminal mounted to the substrate; a transistor die coupled to the substrate , the transistor die including: a transistor formed from a plurality of transistor cells , each transistor cell in the plurality of transistor cells including a control terminal ; and a second die coupled to the substrate , the second die including: a primary capacitor having a first terminal or plate connected to the input terminal , which is configured to receive an input signal, and to the control terminal of each transistor cell in the plurality of transistor cells , and a second terminal or plate connected to a ground reference node or terminal, the primary capacitor being configured to at least partially determine an input impedance of the device ; and a plurality of shunt capacitors , each shunt capacitor in the plurality of shunt capacitors being electrically coupled to the ground reference node and to the control terminal of a different transistor cell in the plurality of transistor cells , wherein at least two shunt capacitors of the plurality of shunt capacitors have capacitance values that are different from each other by at least 5 to 10 percent and wire bonds connecting each shunt capacitor to each transistor cell. a substrate an input terminal and an output terminal mounted to the substrate; a transistor die coupled to the substrate , the transistor die including: a transistor formed from a plurality of transistor cells , each transistor cell in the plurality of transistor cells including a control terminal ; and a second die coupled to the substrate , the second die including: a primary capacitor having a first terminal or plate connected to the input terminal , which is configured to receive an input signal, and to the control terminal of each transistor cell in the plurality of transistor cells , and a second terminal or plate connected to a ground reference node or terminal, the primary capacitor being configured to at least partially determine an input impedance of the device ; and a plurality of shunt capacitors , each shunt capacitor in the plurality of shunt capacitors being electrically coupled to the ground reference node and to the control terminal of a different transistor cell in the plurality of transistor cells , wherein at least two shunt capacitors of the plurality of shunt capacitors have capacitance values that are different from each other by at least 5 to 10 percent and wire bonds connecting each shunt capacitor to each transistor cell. a primary capacitor having a first terminal or plate connected to the input terminal , which is configured to receive an input signal, and to the control terminal of each transistor cell in the plurality of transistor cells , and a second terminal or plate connected to a ground reference node or terminal, the primary capacitor being configured to at least partially determine an input impedance of the device ; and a plurality of shunt capacitors , each shunt capacitor in the plurality of shunt capacitors being electrically coupled to the ground reference node and to the control terminal of a different transistor cell in the plurality of transistor cells , wherein at least two shunt capacitors of the plurality of shunt capacitors have capacitance values that are different from each other by at least 5 to 10 percent and wire bonds connecting each shunt capacitor to each transistor cell. <EOS>