A half-bridge gate driver , comprising: a high-side region that operates in a first voltage domain; a low-side region that operates in a second voltage domain lower than the first voltage domain; a termination region interposed between the high-side region and the low-side region and configured to isolate the first voltage domain from the second voltage domain; a high-side gate driver disposed in the high-side region and configured to drive a high-side power transistor ; a low-side gate driver disposed in the low-side region and configured to drive a low-side power transistor , the low-side power transistor and the high-side power transistor forming a half-bridge ; and a plurality of termination diodes disposed in the termination region and configured to transmit information bits between the high-side region and the low-side region , wherein each of the plurality of termination diodes includes an anode coupled to the low-side gate driver and a cathode coupled to the high-side gate driver , and wherein the plurality of termination diodes is configured to transmit information bits between the high-side region and the low-side region when the first voltage domain and the second voltage domain are aligned, and interrupt a transmission of the information bits between the high-side region and the low-side region when the first voltage domain and the second voltage domain are not aligned, wherein the first voltage domain and the second voltage domain are aligned while the low-side power transistor is turned on, and wherein the first voltage domain and the second voltage domain are not aligned while the high-side power transistor is turned on. a high-side region that operates in a first voltage domain; a low-side region that operates in a second voltage domain lower than the first voltage domain; a termination region interposed between the high-side region and the low-side region and configured to isolate the first voltage domain from the second voltage domain; a high-side gate driver disposed in the high-side region and configured to drive a high-side power transistor ; a low-side gate driver disposed in the low-side region and configured to drive a low-side power transistor , the low-side power transistor and the high-side power transistor forming a half-bridge ; and a plurality of termination diodes disposed in the termination region and configured to transmit information bits between the high-side region and the low-side region , wherein each of the plurality of termination diodes includes an anode coupled to the low-side gate driver and a cathode coupled to the high-side gate driver , and wherein the plurality of termination diodes is configured to transmit information bits between the high-side region and the low-side region when the first voltage domain and the second voltage domain are aligned, and interrupt a transmission of the information bits between the high-side region and the low-side region when the first voltage domain and the second voltage domain are not aligned, wherein the first voltage domain and the second voltage domain are aligned while the low-side power transistor is turned on, and wherein the first voltage domain and the second voltage domain are not aligned while the high-side power transistor is turned on. transmit information bits between the high-side region and the low-side region when the first voltage domain and the second voltage domain are aligned, and interrupt a transmission of the information bits between the high-side region and the low-side region when the first voltage domain and the second voltage domain are not aligned, wherein the first voltage domain and the second voltage domain are aligned while the low-side power transistor is turned on, and wherein the first voltage domain and the second voltage domain are not aligned while the high-side power transistor is turned on. <EOS>