A liquid crystal display comprising: an upper plate and a lower plate positioned opposite each other with a liquid crystal layer interposed therebetween; and a spacer (CS) positioned between the upper plate and the lower plate, wherein the upper plate includes a black matrix (BM), wherein the lower plate includes: a gate line(GL) and a data line (DL) configured to cross each other, a lower electrode (COM; PXL) and an upper electrode (PXL; COM) configured to overlap each other with an insulating layer (PAS1) interposed therebetween and an alignment layer (PI) configured to be in contact with the lower electrode and the upper electrode; wherein the lower plate further comprises a thin film transistor (TFT) connected to the gate line (GL), to the data line (DL) and to a pixel electrode (PXL), the pixel electrode (PXL) being one of the lower electrode (COM; PXL) and the upper electrode (PXL; COM), wherein the alignment layer (PI) is in contact with the lower electrode (COM; PXL) via a first conductive connector (CNT2) disposed in a hole passing through the insulating layer (PAS1) and contacting the lower electrode (COM; PXL), wherein the first conductive connector (CNT2) overlaps both the spacer (CS) and the thin film transistor (TFT) and wherein the gate line (GL), the data line (DL), the thin film transistor (TFT), the spacer (CS) and the first conducive connector (CNT2)are covered by the black matrix. an upper plate and a lower plate positioned opposite each other with a liquid crystal layer interposed therebetween; and a spacer (CS) positioned between the upper plate and the lower plate, wherein the upper plate includes a black matrix (BM), wherein the lower plate includes: a gate line(GL) and a data line (DL) configured to cross each other, a lower electrode (COM; PXL) and an upper electrode (PXL; COM) configured to overlap each other with an insulating layer (PAS1) interposed therebetween and an alignment layer (PI) configured to be in contact with the lower electrode and the upper electrode; wherein the lower plate further comprises a thin film transistor (TFT) connected to the gate line (GL), to the data line (DL) and to a pixel electrode (PXL), the pixel electrode (PXL) being one of the lower electrode (COM; PXL) and the upper electrode (PXL; COM), wherein the alignment layer (PI) is in contact with the lower electrode (COM; PXL) via a first conductive connector (CNT2) disposed in a hole passing through the insulating layer (PAS1) and contacting the lower electrode (COM; PXL), wherein the first conductive connector (CNT2) overlaps both the spacer (CS) and the thin film transistor (TFT) and wherein the gate line (GL), the data line (DL), the thin film transistor (TFT), the spacer (CS) and the first conducive connector (CNT2)are covered by the black matrix. a gate line(GL) and a data line (DL) configured to cross each other, a lower electrode (COM; PXL) and an upper electrode (PXL; COM) configured to overlap each other with an insulating layer (PAS1) interposed therebetween and an alignment layer (PI) configured to be in contact with the lower electrode and the upper electrode; wherein the lower plate further comprises a thin film transistor (TFT) connected to the gate line (GL), to the data line (DL) and to a pixel electrode (PXL), the pixel electrode (PXL) being one of the lower electrode (COM; PXL) and the upper electrode (PXL; COM), wherein the alignment layer (PI) is in contact with the lower electrode (COM; PXL) via a first conductive connector (CNT2) disposed in a hole passing through the insulating layer (PAS1) and contacting the lower electrode (COM; PXL), wherein the first conductive connector (CNT2) overlaps both the spacer (CS) and the thin film transistor (TFT) and wherein the gate line (GL), the data line (DL), the thin film transistor (TFT), the spacer (CS) and the first conducive connector (CNT2)are covered by the black matrix. <EOS>