A vertical power transistor device, comprising: a substrate formed from a III-V semiconductor material, the substrate comprising a recess extending from a surface of the substrate at a first side of the substrate into the III-V semiconductor material, a multi-layer stack at least partially situated in the recess , the multi-layer stack comprising: a first layer disposed in the recess formed from a first III-V semiconductor material, a second layer formed from a second III-V semiconductor material, a heterojunction formed at an interface of the first layer and the second layer , a semi-insulating layer disposed in the recess between the substrate and the first layer , for electrically insulating in the recess the hetero-junction from the substrate ; a drain contact formed on a second side of the substrate opposite to the first side and being electrically connected to the substrate ; a source contact and a gate contact formed at the first side on the multi-layer stack ; wherein the interface is located level with or below the surface of the substrate at the first side, the semi-insulating layer and the first layer are surrounded by sides of the recess of the substrate in a horizontal plane parallel to the surface of the substrate , and the semi-insulating layer is arranged for forcing electrical current to flow laterally towards regions of the substrate adjacent to the sides of the recess before the electrical current flows vertically through the substrate towards the drain contact . a substrate formed from a III-V semiconductor material, the substrate comprising a recess extending from a surface of the substrate at a first side of the substrate into the III-V semiconductor material, a multi-layer stack at least partially situated in the recess , the multi-layer stack comprising: a first layer disposed in the recess formed from a first III-V semiconductor material, a second layer formed from a second III-V semiconductor material, a heterojunction formed at an interface of the first layer and the second layer , a semi-insulating layer disposed in the recess between the substrate and the first layer , for electrically insulating in the recess the hetero-junction from the substrate ; a first layer disposed in the recess formed from a first III-V semiconductor material, a second layer formed from a second III-V semiconductor material, a heterojunction formed at an interface of the first layer and the second layer , a semi-insulating layer disposed in the recess between the substrate and the first layer , for electrically insulating in the recess the hetero-junction from the substrate ; a drain contact formed on a second side of the substrate opposite to the first side and being electrically connected to the substrate ; a source contact and a gate contact formed at the first side on the multi-layer stack ; wherein the interface is located level with or below the surface of the substrate at the first side, the semi-insulating layer and the first layer are surrounded by sides of the recess of the substrate in a horizontal plane parallel to the surface of the substrate , and the semi-insulating layer is arranged for forcing electrical current to flow laterally towards regions of the substrate adjacent to the sides of the recess before the electrical current flows vertically through the substrate towards the drain contact . <EOS>