Electrical circuit for identifying circuit defects and/or for avoiding overvoltages in regulators, comprising - a power regulator circuit, having a first transistor (MOS PWR ), a control loop comprising a first operational amplifier (OTA PWR ) and a first reference voltage source (V REF1 ), and feedback resistors (R1, R2, R3), and - an overvoltage suppression circuit, having a second transistor (MOS PROT ), which receives an output voltage (V DD_PWR ) of the power regulator circuit at its drain connection and provides a protected voltage (V DD_PROT ) to its source connection, a control loop comprising a second operational amplifier (OTA PROT ) and a second reference voltage source (V REF2 ), and feedback resistors (R 4 , R 5 , R 6 ), wherein the power regulator circuit is provided in order to provide the output voltage (V DD_PWR ) for the overvoltage suppression circuit and the overvoltage suppression circuit is provided in order to provide the protected voltage (V DD_PROT ), characterized by a first comparator (COMP OV ) and a third transistor (MOSov), the gate connection of which is connected to the source connection of the second transistor (MOS PROT ), and which is provided to limit an overvoltage at the source connection of the third transistor (MOS OV ), wherein an input of the first comparator (COMP OV ) is connected to the source connection of the third transistor (MOSov), which comparator is provided to detect the overvoltage by comparing the limited voltage (V OV ) with a voltage of the second reference voltage source (V REF2 ), wherein the inputs of the second operational amplifier (OTA PROT ) comprise the feedback voltage and a reference voltage provided by the second reference voltage source (V REF2 ) and the output thereof connects the gate connection of the second transistor (MOS PROT ) . - a power regulator circuit, having a first transistor (MOS PWR ), a control loop comprising a first operational amplifier (OTA PWR ) and a first reference voltage source (V REF1 ), and feedback resistors (R1, R2, R3), and - an overvoltage suppression circuit, having a second transistor (MOS PROT ), which receives an output voltage (V DD_PWR ) of the power regulator circuit at its drain connection and provides a protected voltage (V DD_PROT ) to its source connection, a control loop comprising a second operational amplifier (OTA PROT ) and a second reference voltage source (V REF2 ), and feedback resistors (R 4 , R 5 , R 6 ), wherein the power regulator circuit is provided in order to provide the output voltage (V DD_PWR ) for the overvoltage suppression circuit and the overvoltage suppression circuit is provided in order to provide the protected voltage (V DD_PROT ), characterized by a first comparator (COMP OV ) and a third transistor (MOSov), the gate connection of which is connected to the source connection of the second transistor (MOS PROT ), and which is provided to limit an overvoltage at the source connection of the third transistor (MOS OV ), wherein an input of the first comparator (COMP OV ) is connected to the source connection of the third transistor (MOSov), which comparator is provided to detect the overvoltage by comparing the limited voltage (V OV ) with a voltage of the second reference voltage source (V REF2 ), wherein the inputs of the second operational amplifier (OTA PROT ) comprise the feedback voltage and a reference voltage provided by the second reference voltage source (V REF2 ) and the output thereof connects the gate connection of the second transistor (MOS PROT ) . <EOS>