An erasable programmable single-poly nonvolatile memory, comprising: a substrate structure (P-substrate); a first PMOS transistor comprising a select gate , a first source/drain region , and a second source/drain region , wherein the select gate is connected to a select gate voltage (V SG ), and the first source/drain region is connected to a source line voltage (V SL ); a second PMOS transistor comprising the second source/drain region , a third source/drain region , and a floating gate , wherein the third source/drain region is connected to a bit line voltage (V BL ), and the first source/drain region , the second source/drain region , and the third source/drain region are constructed in a N-well region (NW); and an erase gate region , wherein said floating gate extends over said erase gate region and wherein the erase gate region comprises an n-type source/drain region connected to an erase line voltage (V EL ) and a P-well region (PW); wherein the N-well region (NW) and the P-well region (PW) are formed in the substrate structure; characterized in that the erase gate region further comprises a first n-type double diffused drain region formed between the n-type source/drain region and the P-well region (PW), wherein the P-well region (PW) comprises: a first p-type region (p1) formed under a surface of the substrate structure and contacted to the first n-type double diffused drain region ; a plurality of second p-type regions (p2); and a third p-type region (p3) formed under the first p-type region (p1); wherein the first p-type region (p1) and the third p-type region (p3) are located between the second p-type regions (p2); and wherein a dosage in the second p-type regions (p2) is higher than a dosage in the first p-type region (p1), and a dosage in the third p-type region (p3) is higher than the dosage in the first p-type region (p1). a substrate structure (P-substrate); a first PMOS transistor comprising a select gate , a first source/drain region , and a second source/drain region , wherein the select gate is connected to a select gate voltage (V SG ), and the first source/drain region is connected to a source line voltage (V SL ); a second PMOS transistor comprising the second source/drain region , a third source/drain region , and a floating gate , wherein the third source/drain region is connected to a bit line voltage (V BL ), and the first source/drain region , the second source/drain region , and the third source/drain region are constructed in a N-well region (NW); and an erase gate region , wherein said floating gate extends over said erase gate region and wherein the erase gate region comprises an n-type source/drain region connected to an erase line voltage (V EL ) and a P-well region (PW); wherein the N-well region (NW) and the P-well region (PW) are formed in the substrate structure; characterized in that the erase gate region further comprises a first n-type double diffused drain region formed between the n-type source/drain region and the P-well region (PW), wherein the P-well region (PW) comprises: a first p-type region (p1) formed under a surface of the substrate structure and contacted to the first n-type double diffused drain region ; a plurality of second p-type regions (p2); and a third p-type region (p3) formed under the first p-type region (p1); wherein the first p-type region (p1) and the third p-type region (p3) are located between the second p-type regions (p2); and wherein a dosage in the second p-type regions (p2) is higher than a dosage in the first p-type region (p1), and a dosage in the third p-type region (p3) is higher than the dosage in the first p-type region (p1). <EOS>