A stacked memory chip device , comprising: a plurality of stacked memory chips (401_1 to 401_N); read/write logic circuitry to service read/write requests for cache lines kept within the plurality of stacked memory chips (401_1 to 401_N); data error recovery protection circuitry configured to: store information to protect substantive data of cache lines in the plurality of stacked memory chips (401_1 to 401_N), the information being error correction coding, ECC, information, store the information in more than one of the plurality of stacked memory chips (401_1 to 401_N), and store any subset of the information that protects respective substantive data of a particular one of the cache lines in a memory chip different from the memory chip in which the respective substantive data is stored, wherein the data error recovery protection circuitry comprises a parsing circuitry configured to parse a received write cache line into separate pieces that are stored on different memory chips (401_1 to 401_N), characterized in that each memory chip (401_1 to 401_N) of the plurality of stacked memory chips contains its own respective ECC circuitry to determine the ECC information to be written into its own memory chip (401_1 to 401_N), the respective ECC circuitries being a component of the data error recovery protection circuitry. a plurality of stacked memory chips (401_1 to 401_N); read/write logic circuitry to service read/write requests for cache lines kept within the plurality of stacked memory chips (401_1 to 401_N); data error recovery protection circuitry configured to: store information to protect substantive data of cache lines in the plurality of stacked memory chips (401_1 to 401_N), the information being error correction coding, ECC, information, store the information in more than one of the plurality of stacked memory chips (401_1 to 401_N), and store any subset of the information that protects respective substantive data of a particular one of the cache lines in a memory chip different from the memory chip in which the respective substantive data is stored, wherein the data error recovery protection circuitry comprises a parsing circuitry configured to parse a received write cache line into separate pieces that are stored on different memory chips (401_1 to 401_N), store information to protect substantive data of cache lines in the plurality of stacked memory chips (401_1 to 401_N), the information being error correction coding, ECC, information, store the information in more than one of the plurality of stacked memory chips (401_1 to 401_N), and store any subset of the information that protects respective substantive data of a particular one of the cache lines in a memory chip different from the memory chip in which the respective substantive data is stored, wherein the data error recovery protection circuitry comprises a parsing circuitry configured to parse a received write cache line into separate pieces that are stored on different memory chips (401_1 to 401_N), characterized in that each memory chip (401_1 to 401_N) of the plurality of stacked memory chips contains its own respective ECC circuitry to determine the ECC information to be written into its own memory chip (401_1 to 401_N), the respective ECC circuitries being a component of the data error recovery protection circuitry. <EOS>