A pulsed-power device comprising: a pulsed-power circuit comprising first, second, third and fourth compression stages, characterised in that said first stage comprises first and second capacitors ( C 1a , C 1 b ) coupled in parallel and pre-charged to a voltage (+HV 1 ), said first and second capacitors ( C 1a , C 1 b ) being coupled in series respectively to first and second inductors ( L 1 a , L 1 b ) , and a first stage switch (Si) coupled to said first and second capacitors ( C 1a , C 1 b ) ; said second stage comprises first and second capacitors ( C 2 a , C 2 b ) coupled in parallel and pre-charged to a voltage (-HV 2 ) in a negative direction with respect to the pre-charge voltage (+HV 1 ) of the first stage, said first and second capacitors ( C 2 a , C 2 b ) of the second stage being coupled in series respectively to first and second inductors ( L 2 a , L 2 b ) , and a first switch ( S 2 a ) coupled to said first capacitor ( C 1 a ) and said first inductor ( L 1 a ) of said first stage and to said first capacitor ( C 2 a ) and said first inductor ( L 2 a ) of said second stage, and a second switch ( S 2 b ) coupled to said second capacitor ( C 1 b ) and said second inductor ( L 1 b ) of said first stage and to said second capacitor ( C 2 b ) and said second inductor ( L 2 b ) of said second stage; said third stage comprises a first DSRD (DSRD1) coupled in series to an inductor ( L 3 ): said fourth stage comprises a second DSRD (DSRD2) coupled in series to a capacitor ( C 3 ); and wherein said switch ( S 1 ) of said first stage is coupled to a driver (Driver) such that turning on said switch ( S 1 ) of said first stage causes said driver (Driver) to pump said first and second DSRDs (DSRD1, DSRD2) and turning on said first and second switches ( S 2 a , S 2 b ) of said second stage pulses said first and second DSRDs (DSRD1, DSRD2). a pulsed-power circuit comprising first, second, third and fourth compression stages, characterised in that said first stage comprises first and second capacitors ( C 1a , C 1 b ) coupled in parallel and pre-charged to a voltage (+HV 1 ), said first and second capacitors ( C 1a , C 1 b ) being coupled in series respectively to first and second inductors ( L 1 a , L 1 b ) , and a first stage switch (Si) coupled to said first and second capacitors ( C 1a , C 1 b ) ; said second stage comprises first and second capacitors ( C 2 a , C 2 b ) coupled in parallel and pre-charged to a voltage (-HV 2 ) in a negative direction with respect to the pre-charge voltage (+HV 1 ) of the first stage, said first and second capacitors ( C 2 a , C 2 b ) of the second stage being coupled in series respectively to first and second inductors ( L 2 a , L 2 b ) , and a first switch ( S 2 a ) coupled to said first capacitor ( C 1 a ) and said first inductor ( L 1 a ) of said first stage and to said first capacitor ( C 2 a ) and said first inductor ( L 2 a ) of said second stage, and a second switch ( S 2 b ) coupled to said second capacitor ( C 1 b ) and said second inductor ( L 1 b ) of said first stage and to said second capacitor ( C 2 b ) and said second inductor ( L 2 b ) of said second stage; said third stage comprises a first DSRD (DSRD1) coupled in series to an inductor ( L 3 ): said fourth stage comprises a second DSRD (DSRD2) coupled in series to a capacitor ( C 3 ); and wherein said switch ( S 1 ) of said first stage is coupled to a driver (Driver) such that turning on said switch ( S 1 ) of said first stage causes said driver (Driver) to pump said first and second DSRDs (DSRD1, DSRD2) and turning on said first and second switches ( S 2 a , S 2 b ) of said second stage pulses said first and second DSRDs (DSRD1, DSRD2). <EOS>