A multi-bit digital-to-analog converter (DAC) comprising: - a chopped reference voltage generator generating a reference voltage and offset voltage, wherein the offset voltage is alternatingly added to or subtracted from the reference voltage; - a switched capacitor stage (102; 155) receiving said chopped reference voltage and configured to generate a plurality of output voltages according to respective DAC input values; - a switching sequencer (160; 610) for generating control signals, wherein for generating one of said plurality of output voltages said switching sequencer controls said switched capacitor stage (102; 155) to generate one of a plurality of switching patterns through said control signals, wherein each switching pattern controls switches of said switched capacitor stage (102; 155) during a charge phase and a transfer phase thereby generating the one of said plurality of output voltages, characterized in that chopping of the chopped reference voltage generator is synchronized with the charge phase and the transfer phase, and for at least one DAC input value the switching sequencer (160; 610) provides two different switching patterns (A, B), wherein each of the two different switching patterns (A, B) generates a first one of said plurality of output voltages defined by said at least one DAC input value with a different output offset voltage added thereto, and wherein one of the two switching patterns (A) contributes a positive output offset voltage to the first one output voltage and the respective other switching pattern (B) contributes a negative output offset voltage to the first one output voltage and wherein output offset voltages added to the first one output voltages generated by the two different switching patterns cancel each other out. - a chopped reference voltage generator generating a reference voltage and offset voltage, wherein the offset voltage is alternatingly added to or subtracted from the reference voltage; - a switched capacitor stage (102; 155) receiving said chopped reference voltage and configured to generate a plurality of output voltages according to respective DAC input values; - a switching sequencer (160; 610) for generating control signals, wherein for generating one of said plurality of output voltages said switching sequencer controls said switched capacitor stage (102; 155) to generate one of a plurality of switching patterns through said control signals, wherein each switching pattern controls switches of said switched capacitor stage (102; 155) during a charge phase and a transfer phase thereby generating the one of said plurality of output voltages, chopping of the chopped reference voltage generator is synchronized with the charge phase and the transfer phase, and for at least one DAC input value the switching sequencer (160; 610) provides two different switching patterns (A, B), wherein each of the two different switching patterns (A, B) generates a first one of said plurality of output voltages defined by said at least one DAC input value with a different output offset voltage added thereto, and wherein one of the two switching patterns (A) contributes a positive output offset voltage to the first one output voltage and the respective other switching pattern (B) contributes a negative output offset voltage to the first one output voltage and wherein output offset voltages added to the first one output voltages generated by the two different switching patterns cancel each other out. <EOS>