A relay drive circuit comprising: a current mirror circuit including a first semiconductor element (Q1) and a second semiconductor element (Q2), the current mirror circuit being configured to adjust a current flowing through a first current path including the first semiconductor element (Q1) according to a current flowing through a second current path including the second semiconductor element (Q2); and a control switch (Q3) provided on the second current path, wherein a relay coil is provided on the first current path, the relay drive circuit further comprising: a current suppression circuit provided on the second current path and configured to suppress, after conduction of the second semiconductor element (Q2) has been made, the current flowing through the second current path as compared to that in the conduction of the second semiconductor element (Q2); characterized in that the current suppression circuit includes: a capacitor (C1) and a resistor element (R4) connected in series; a current setting element (R3) connected in parallel such that a current flow is divided for the capacitor (C1) and the resistor element (R4) connected in series, and being configured to set the current flowing through the second current path. a current mirror circuit including a first semiconductor element (Q1) and a second semiconductor element (Q2), the current mirror circuit being configured to adjust a current flowing through a first current path including the first semiconductor element (Q1) according to a current flowing through a second current path including the second semiconductor element (Q2); and a control switch (Q3) provided on the second current path, wherein a relay coil is provided on the first current path, the relay drive circuit further comprising: a current suppression circuit provided on the second current path and configured to suppress, after conduction of the second semiconductor element (Q2) has been made, the current flowing through the second current path as compared to that in the conduction of the second semiconductor element (Q2); characterized in that the current suppression circuit includes: a capacitor (C1) and a resistor element (R4) connected in series; a current setting element (R3) connected in parallel such that a current flow is divided for the capacitor (C1) and the resistor element (R4) connected in series, and being configured to set the current flowing through the second current path. a current suppression circuit provided on the second current path and configured to suppress, after conduction of the second semiconductor element (Q2) has been made, the current flowing through the second current path as compared to that in the conduction of the second semiconductor element (Q2); characterized in that the current suppression circuit includes: a capacitor (C1) and a resistor element (R4) connected in series; a current setting element (R3) connected in parallel such that a current flow is divided for the capacitor (C1) and the resistor element (R4) connected in series, and being configured to set the current flowing through the second current path. a capacitor (C1) and a resistor element (R4) connected in series; a current setting element (R3) connected in parallel such that a current flow is divided for the capacitor (C1) and the resistor element (R4) connected in series, and being configured to set the current flowing through the second current path. <EOS>