A method for reading a memory cell of a vertical ferroelectric memory device, said vertical ferroelectric memory device comprising: - a stack of horizontal layers on a semiconductor substrate having a major surface , the stack of layers comprising a repetitive sequence of a metal gate electrode layer on an insulating layer ; - a vertical structure extending through the stack of horizontal layers and perpendicular to the major surface of the substrate , the vertical structure having a sidewall along the stack of horizontal layers ; - the vertical structure comprising o along the sidewall a vertical transition metal oxide (TMO) ferroelectric layer ; o aside and along the vertical Transition Metal Oxide (TMO) ferroelectric layer , a vertical channel layer thereby forming at the overlap of a metal gate electrode layer with the vertical channel layer a memory cell and characterized in that said vertical channel layer comprises doped silicon having a dopant concentration between 10 18 dopants/cm 3 and 10 20 dopants/cm 3 and further comprises source and drain regions having the same doping type and the same doping concentration as the vertical channel region so that the doping profile along the vertical channel layer is uniform; the method comprising : - applying 0V to all metal gate electrode layers in the memory device, except to the metal gate electrode of the memory cell to be read; - applying a negative selected wordline read voltage to the metal gate electrode of the memory cell to be read, and ; - measuring the current flowing through the vertical channel layer , whereby the current is high or low dependent on the polarization state of the vertical TMO ferroelectric layer in between the metal gate electrode of the memory cell to be read and the vertical channel layer. - a stack of horizontal layers on a semiconductor substrate having a major surface , the stack of layers comprising a repetitive sequence of a metal gate electrode layer on an insulating layer ; - a vertical structure extending through the stack of horizontal layers and perpendicular to the major surface of the substrate , the vertical structure having a sidewall along the stack of horizontal layers ; - the vertical structure comprising o along the sidewall a vertical transition metal oxide (TMO) ferroelectric layer ; o aside and along the vertical Transition Metal Oxide (TMO) ferroelectric layer , a vertical channel layer thereby forming at the overlap of a metal gate electrode layer with the vertical channel layer a memory cell and o along the sidewall a vertical transition metal oxide (TMO) ferroelectric layer ; o aside and along the vertical Transition Metal Oxide (TMO) ferroelectric layer , a vertical channel layer - applying 0V to all metal gate electrode layers in the memory device, except to the metal gate electrode of the memory cell to be read; - applying a negative selected wordline read voltage to the metal gate electrode of the memory cell to be read, and ; - measuring the current flowing through the vertical channel layer , whereby the current is high or low dependent on the polarization state of the vertical TMO ferroelectric layer in between the metal gate electrode of the memory cell to be read and the vertical channel layer. <EOS>