An operating method of a system comprising a memory device and a memory controller , the memory device in communication with the memory controller , the method comprising: at the memory controller : including information about a processing interval between consecutive processing commands; determining whether a first processing interval between a command (read/write) for processing the first data stream and a command (read/write) for processing the second data stream is shorter than a reference interval; and when it is determined that the first processing interval is shorter than the reference interval, outputting a first command (CASL) to the memory device ; and at the memory device : receiving the first command (CASL) from the memory controller , the first command (CMD) indicating initiation of synchronization of a data clock signal (WCK) with a clock signal (CK) and defining a period (tWCK_SYNC) of a first clock section corresponding to the synchronization; preparing a toggling of the data clock signal (WCK) during a preparation time period (tSYNC_Prepare); processing a first data stream based on the data clock signal (WCK) toggling at a reference frequency (tWCK_Toggle); and processing a second data stream based on the data clock signal (WCK) toggling at the reference frequency (tWCK Toggle) during the period (tWCK_SYNC) of the first clock section such that the toggling of the data clock signal (tWCK_Toggle) is maintained from when the first data stream is processed to when the second data stream is processed. including information about a processing interval between consecutive processing commands; determining whether a first processing interval between a command (read/write) for processing the first data stream and a command (read/write) for processing the second data stream is shorter than a reference interval; and when it is determined that the first processing interval is shorter than the reference interval, outputting a first command (CASL) to the memory device ; and at the memory device : receiving the first command (CASL) from the memory controller , the first command (CMD) indicating initiation of synchronization of a data clock signal (WCK) with a clock signal (CK) and defining a period (tWCK_SYNC) of a first clock section corresponding to the synchronization; preparing a toggling of the data clock signal (WCK) during a preparation time period (tSYNC_Prepare); processing a first data stream based on the data clock signal (WCK) toggling at a reference frequency (tWCK_Toggle); and processing a second data stream based on the data clock signal (WCK) toggling at the reference frequency (tWCK Toggle) during the period (tWCK_SYNC) of the first clock section such that the toggling of the data clock signal (tWCK_Toggle) is maintained from when the first data stream is processed to when the second data stream is processed. receiving the first command (CASL) from the memory controller , the first command (CMD) indicating initiation of synchronization of a data clock signal (WCK) with a clock signal (CK) and defining a period (tWCK_SYNC) of a first clock section corresponding to the synchronization; preparing a toggling of the data clock signal (WCK) during a preparation time period (tSYNC_Prepare); processing a first data stream based on the data clock signal (WCK) toggling at a reference frequency (tWCK_Toggle); and processing a second data stream based on the data clock signal (WCK) toggling at the reference frequency (tWCK Toggle) during the period (tWCK_SYNC) of the first clock section such that the toggling of the data clock signal (tWCK_Toggle) is maintained from when the first data stream is processed to when the second data stream is processed. <EOS>