A method of analog-to-digital conversion in a sensor circuit with an input of V IN and having an analog-to-digital converter, ADC, with a capacitor array comprising a plurality of capacitors connected through a respective plurality of switches, collectively forming a DAC, a comparator, a successive- approximation-register, SAR, module and a multiplexer, MUX, connected between the DAC and the SAR module, the method comprising: executing a track phase when a sample clock signal CK_SMP is low by applying an input voltage V IN over all capacitors in the capacitor array of the DAC; executing a sampling phase on a subsequent rising edge of CK_SMP by opening the respective plurality of switches such that a sample of V IN is stored over the capacitor array of the DAC; executing a comparison phase, by setting the MUX to select an n-bit threshold value D THRESHOLD.0 which is applied to the DAC capacitor array, connecting all switches S i , where i is in the range from 0 to n-1, which receive 1, to a reference voltage V REF and connecting the remaining switches to a common mode voltage V CM such that the output VP of the DAC reaches a value equal to the input voltage V IN subtracted from the analog of D THRESHOLD.0 , and completing the comparison to V CM by the comparator at the comparator clock CK, such that if VP > V CM , then DP is 1 and the sample of V IN is larger than D THRESHOLD,0 , and otherwise, if VP < V CM , then DP is 0 and the sample of V IN is smaller than D THRESHOLD, 0 ; wherein the result DP of the comparison is then used as a threshold trigger, and if the comparison reaches the trigger threshold, a full SAR conversion is executed, and wherein, if the comparison does not reach the trigger threshold, another threshold value D THRESHOLD,j , is selected, where j is in the range from 1 to M, via the MUX and the comparison phase is repeated until all M threshold values have been compared, wherein after any number of comparisons and based on the results of the corresponding threshold conversions a full SAR comparison is carried out to obtain a full quantization of the input voltage. executing a track phase when a sample clock signal CK_SMP is low by applying an input voltage V IN over all capacitors in the capacitor array of the DAC; executing a sampling phase on a subsequent rising edge of CK_SMP by opening the respective plurality of switches such that a sample of V IN is stored over the capacitor array of the DAC; executing a comparison phase, by setting the MUX to select an n-bit threshold value D THRESHOLD.0 which is applied to the DAC capacitor array, connecting all switches S i , where i is in the range from 0 to n-1, which receive 1, to a reference voltage V REF and connecting the remaining switches to a common mode voltage V CM such that the output VP of the DAC reaches a value equal to the input voltage V IN subtracted from the analog of D THRESHOLD.0 , and completing the comparison to V CM by the comparator at the comparator clock CK, such that if VP > V CM , then DP is 1 and the sample of V IN is larger than D THRESHOLD,0 , and otherwise, if VP < V CM , then DP is 0 and the sample of V IN is smaller than D THRESHOLD, 0 ; wherein the result DP of the comparison is then used as a threshold trigger, and if the comparison reaches the trigger threshold, a full SAR conversion is executed, and wherein, if the comparison does not reach the trigger threshold, another threshold value D THRESHOLD,j , is selected, where j is in the range from 1 to M, via the MUX and the comparison phase is repeated until all M threshold values have been compared, wherein after any number of comparisons and based on the results of the corresponding threshold conversions a full SAR comparison is carried out to obtain a full quantization of the input voltage. <EOS>