An integrated circuit, comprising: a bandgap core circuit including: a first bipolar junction transistor, BJT, ; a second BJT having a control electrode coupled to a control electrode of the first BJT ; a first resistor having a first terminal coupled to a first current electrode of the first BJT , and a second terminal coupled to a first current electrode of the second BJT ; a second resistor having a first terminal coupled to a second current electrode of the second BJT ; and a third resistor having a first terminal coupled to the first current electrode of the second BJT , and a second terminal coupled to an output terminal (VOUT); and a cascode amplifier circuit having a first branch coupled to a second current electrode of the first BJT at a first cascode node (CC1) and a second branch coupled to a second terminal of the second resistor at a second cascode node (CC2), said cascode amplifier being coupled to receive a bias voltage (VBIAS) provided to an output of a bias circuit and said bias circuit having an input terminal connected to said output terminal (VOUT); a first current source coupled to the first cascode note (CC1) and a second current source coupled to the second cascode note (CC2); wherein the first resistor and second resistor are configured to have IR drop across the second resistor be substantially equal to IR drop across the first resistor and the first and second transistors are configured to operate in saturation mode. a bandgap core circuit including: a first bipolar junction transistor, BJT, ; a second BJT having a control electrode coupled to a control electrode of the first BJT ; a first resistor having a first terminal coupled to a first current electrode of the first BJT , and a second terminal coupled to a first current electrode of the second BJT ; a second resistor having a first terminal coupled to a second current electrode of the second BJT ; and a third resistor having a first terminal coupled to the first current electrode of the second BJT , and a second terminal coupled to an output terminal (VOUT); and a first bipolar junction transistor, BJT, ; a second BJT having a control electrode coupled to a control electrode of the first BJT ; a first resistor having a first terminal coupled to a first current electrode of the first BJT , and a second terminal coupled to a first current electrode of the second BJT ; a second resistor having a first terminal coupled to a second current electrode of the second BJT ; and a third resistor having a first terminal coupled to the first current electrode of the second BJT , and a second terminal coupled to an output terminal (VOUT); and a cascode amplifier circuit having a first branch coupled to a second current electrode of the first BJT at a first cascode node (CC1) and a second branch coupled to a second terminal of the second resistor at a second cascode node (CC2), said cascode amplifier being coupled to receive a bias voltage (VBIAS) provided to an output of a bias circuit and said bias circuit having an input terminal connected to said output terminal (VOUT); a first current source coupled to the first cascode note (CC1) and a second current source coupled to the second cascode note (CC2); wherein the first resistor and second resistor are configured to have IR drop across the second resistor be substantially equal to IR drop across the first resistor and the first and second transistors are configured to operate in saturation mode. <EOS>