A flip-flop comprising a slave latch and a master latch , each of the slave latch and master latch comprising a pair of cross-coupled logic gates, wherein a cross coupling connection of the slave or master latch comprises a resistive element arranged to reduce the sensitivity of the flip-flop to a current injection, wherein the pair of cross-coupled logic gates of the master latch comprise a forward inverter and a reverse inverter , and the pair of cross-coupled logic gates of the slave latch comprise a forward inverter and a reverse inverter ; wherein at least one of the logic gates of the slave latch is connected to a voltage supply via a transistor that is controlled by a voltage at a node of the master latch , and wherein: both of the forward inverter and reverse inverter of the slave latch are connected to a voltage supply via a transistor that is controlled by a voltage at a node of the master latch ; the transistor connecting the forward inverter of the slave latch to the voltage supply is configured to cause the voltage supplied to the forward inverter of the slave latch to float when the output node of the reverse inverter of the master latch is high; and the transistor connecting the reverse inverter of the slave latch to the voltage supply is configured to cause the voltage supplied to the reverse inverter of the slave latch to float when the output node of the forward inverter of the master latch is high. wherein the pair of cross-coupled logic gates of the master latch comprise a forward inverter and a reverse inverter , and the pair of cross-coupled logic gates of the slave latch comprise a forward inverter and a reverse inverter ; wherein at least one of the logic gates of the slave latch is connected to a voltage supply via a transistor that is controlled by a voltage at a node of the master latch , and wherein: both of the forward inverter and reverse inverter of the slave latch are connected to a voltage supply via a transistor that is controlled by a voltage at a node of the master latch ; the transistor connecting the forward inverter of the slave latch to the voltage supply is configured to cause the voltage supplied to the forward inverter of the slave latch to float when the output node of the reverse inverter of the master latch is high; and the transistor connecting the reverse inverter of the slave latch to the voltage supply is configured to cause the voltage supplied to the reverse inverter of the slave latch to float when the output node of the forward inverter of the master latch is high. both of the forward inverter and reverse inverter of the slave latch are connected to a voltage supply via a transistor that is controlled by a voltage at a node of the master latch ; the transistor connecting the forward inverter of the slave latch to the voltage supply is configured to cause the voltage supplied to the forward inverter of the slave latch to float when the output node of the reverse inverter of the master latch is high; and the transistor connecting the reverse inverter of the slave latch to the voltage supply is configured to cause the voltage supplied to the reverse inverter of the slave latch to float when the output node of the forward inverter of the master latch is high. <EOS>