A memory device, comprising: an array (402; 606) of memory cells, wherein cells in the array (402; 606) of memory cells are phase change memory, PCM, cells ; and circuitry configured to: apply a set demarcation bias voltage (Vdms) to a plurality of PCM cells and detect the presence or absence of a resulting transient snapback current; after applying the set demarcation bias voltage (Vdms) to the plurality of PCM cells , receive data comprising set bits and reset bits: identify an array location to write data comprising the set bits and the reset bits; map the set bits and the reset bits of the data to corresponding cells of the array location; apply a reset demarcation bias voltage (Vdmr) to reset bit-mapped cells and detect the presence or absence of a resulting snapback current, wherein the reset demarcation bias voltage (Vdmr) has a higher voltage than the set demarcation bias voltage (Vdms); apply a set pulse to set bit-mapped cells in which the transient snapback current is absent; and apply a reset pulse to reset bit-mapped cells in which the transient snapback current is present. an array (402; 606) of memory cells, wherein cells in the array (402; 606) of memory cells are phase change memory, PCM, cells ; and circuitry configured to: apply a set demarcation bias voltage (Vdms) to a plurality of PCM cells and detect the presence or absence of a resulting transient snapback current; after applying the set demarcation bias voltage (Vdms) to the plurality of PCM cells , receive data comprising set bits and reset bits: identify an array location to write data comprising the set bits and the reset bits; map the set bits and the reset bits of the data to corresponding cells of the array location; apply a reset demarcation bias voltage (Vdmr) to reset bit-mapped cells and detect the presence or absence of a resulting snapback current, wherein the reset demarcation bias voltage (Vdmr) has a higher voltage than the set demarcation bias voltage (Vdms); apply a set pulse to set bit-mapped cells in which the transient snapback current is absent; and apply a reset pulse to reset bit-mapped cells in which the transient snapback current is present. apply a set demarcation bias voltage (Vdms) to a plurality of PCM cells and detect the presence or absence of a resulting transient snapback current; after applying the set demarcation bias voltage (Vdms) to the plurality of PCM cells , receive data comprising set bits and reset bits: identify an array location to write data comprising the set bits and the reset bits; map the set bits and the reset bits of the data to corresponding cells of the array location; apply a reset demarcation bias voltage (Vdmr) to reset bit-mapped cells and detect the presence or absence of a resulting snapback current, wherein the reset demarcation bias voltage (Vdmr) has a higher voltage than the set demarcation bias voltage (Vdms); apply a set pulse to set bit-mapped cells in which the transient snapback current is absent; and apply a reset pulse to reset bit-mapped cells in which the transient snapback current is present. identify an array location to write data comprising the set bits and the reset bits; map the set bits and the reset bits of the data to corresponding cells of the array location; apply a reset demarcation bias voltage (Vdmr) to reset bit-mapped cells and detect the presence or absence of a resulting snapback current, wherein the reset demarcation bias voltage (Vdmr) has a higher voltage than the set demarcation bias voltage (Vdms); apply a set pulse to set bit-mapped cells in which the transient snapback current is absent; and apply a reset pulse to reset bit-mapped cells in which the transient snapback current is present. <EOS>