A method for fabricating a TFT backplane, characterized in that the method for fabricating the TFT backplane comprises: providing a substrate ; forming a first active region on the substrate , wherein the first active region is a polysilicon material; depositing an oxide layer and a nitride layer sequentially on the first active region and on the substrate not covered by the first active region to form as a first insulating layer , wherein the nitride layer is SiN; forming a first gate electrode and a second gate electrode spaced to each other and positioned on the nitride layer , respectively, and the first gate electrode is positioned above the first active region ; removing the nitride layer not covered by the first gate electrode and the second gate electrode by dry etching with the self-alignment of the first gate electrode and the second gate electrode ; depositing a second insulating layer on the first gate electrode and the second gate electrode and the oxide layer not covered by the nitride layer ; forming a second active region on the second insulating layer above the second gate electrode , wherein a material of the second active region is different from the material of the first active region and the second active region is made of indium gallium zinc oxide or indium tin zinc oxide; and forming a first source electrode , a first drain electrode , a second source , and a second drain for the first active region and the second active region , respectively; wherein the first active region , the first gate electrode , the first source electrode , and the first drain electrode correspond to a driver TFT, and the second active region , the second gate electrode , the second source electrode , and the second drain electrode correspond to a switching TFT. providing a substrate ; forming a first active region on the substrate , wherein the first active region is a polysilicon material; depositing an oxide layer and a nitride layer sequentially on the first active region and on the substrate not covered by the first active region to form as a first insulating layer , wherein the nitride layer is SiN; forming a first gate electrode and a second gate electrode spaced to each other and positioned on the nitride layer , respectively, and the first gate electrode is positioned above the first active region ; removing the nitride layer not covered by the first gate electrode and the second gate electrode by dry etching with the self-alignment of the first gate electrode and the second gate electrode ; depositing a second insulating layer on the first gate electrode and the second gate electrode and the oxide layer not covered by the nitride layer ; forming a second active region on the second insulating layer above the second gate electrode , wherein a material of the second active region is different from the material of the first active region and the second active region is made of indium gallium zinc oxide or indium tin zinc oxide; and forming a first source electrode , a first drain electrode , a second source , and a second drain for the first active region and the second active region , respectively; wherein the first active region , the first gate electrode , the first source electrode , and the first drain electrode correspond to a driver TFT, and the second active region , the second gate electrode , the second source electrode , and the second drain electrode correspond to a switching TFT. <EOS>