A circuit to generate an output voltage, the circuit comprising: a voltage divider including at least a first resistive device (R A ) and a second resistive device (R B ), wherein the output voltage is generated at a node along the voltage divider between the first and second resistive devices (R A , R B ); a first closed-loop amplifier circuit to: drive a first terminal (Va) of the voltage divider; and receive a first reference voltage (VA), wherein the first closed-loop amplifier circuit is configured to derive first biasing currents of a first differential input transistor pair (mip1, min1) from a current through the voltage divider, and the first biasing currents are generated from a first tail current that is a scaled version of the current through the voltage divider; and a second closed-loop amplifier circuit to: drive a second terminal (Vb) of the voltage divider; and receive a second reference voltage (VB), wherein the second closed-loop amplifier circuit is configured to derive second biasing currents of a second differential input transistor pair (mip2, min2) from the current through the voltage divider, and the second biasing currents are generated from a second tail current that is a scaled version of the current through the voltage divider. a voltage divider including at least a first resistive device (R A ) and a second resistive device (R B ), wherein the output voltage is generated at a node along the voltage divider between the first and second resistive devices (R A , R B ); a first closed-loop amplifier circuit to: drive a first terminal (Va) of the voltage divider; and receive a first reference voltage (VA), wherein the first closed-loop amplifier circuit is configured to derive first biasing currents of a first differential input transistor pair (mip1, min1) from a current through the voltage divider, and the first biasing currents are generated from a first tail current that is a scaled version of the current through the voltage divider; and drive a first terminal (Va) of the voltage divider; and receive a first reference voltage (VA), wherein the first closed-loop amplifier circuit is configured to derive first biasing currents of a first differential input transistor pair (mip1, min1) from a current through the voltage divider, and the first biasing currents are generated from a first tail current that is a scaled version of the current through the voltage divider; and a second closed-loop amplifier circuit to: drive a second terminal (Vb) of the voltage divider; and receive a second reference voltage (VB), wherein the second closed-loop amplifier circuit is configured to derive second biasing currents of a second differential input transistor pair (mip2, min2) from the current through the voltage divider, and the second biasing currents are generated from a second tail current that is a scaled version of the current through the voltage divider. drive a second terminal (Vb) of the voltage divider; and receive a second reference voltage (VB), wherein the second closed-loop amplifier circuit is configured to derive second biasing currents of a second differential input transistor pair (mip2, min2) from the current through the voltage divider, and the second biasing currents are generated from a second tail current that is a scaled version of the current through the voltage divider. <EOS>