A method comprising: setting a differential output of a multi-input summation latch in a pre-charged state by pre-charging two or more sets of nodes connected to respective sets of input field effect transistors, FETs, of the multi-input summation latch, the two or more sets of nodes comprising (i) a set of data signal nodes connected to a first set of input FETs of the respective sets of input FETs and (ii) a set of decision feedback equalization, DFE, correction nodes connected to a second set of input FETs of the respective sets of input FETs; in response to a sampling clock, generating an integrated differential data voltage signal at the first set of input FETs of the multi-input summation latch by discharging the set of data signal nodes according to a respective set of FETs of a discrete time integration stage receiving a differential input voltage signal and generating an integrated aggregate differential DFE correction voltage signal at the second set of input FETs of the multi-input summation latch by discharging the set of DFE correction nodes according to a respective set of FETs of the discrete time integration stage receiving a plurality of DFE correction factors; and generating a data decision by driving the differential output of the multi-input summation latch into one of two possible output states according to a summation of currents generated by the first and second sets of input FETs receiving the integrated differential data voltage signal and the integrated aggregate differential DFE correction voltage signal, respectively, and subsequently holding the data decision by holding the differential output of the multi-input summation latch in a latched state for a duration determined by the sampling clock. setting a differential output of a multi-input summation latch in a pre-charged state by pre-charging two or more sets of nodes connected to respective sets of input field effect transistors, FETs, of the multi-input summation latch, the two or more sets of nodes comprising (i) a set of data signal nodes connected to a first set of input FETs of the respective sets of input FETs and (ii) a set of decision feedback equalization, DFE, correction nodes connected to a second set of input FETs of the respective sets of input FETs; in response to a sampling clock, generating an integrated differential data voltage signal at the first set of input FETs of the multi-input summation latch by discharging the set of data signal nodes according to a respective set of FETs of a discrete time integration stage receiving a differential input voltage signal and generating an integrated aggregate differential DFE correction voltage signal at the second set of input FETs of the multi-input summation latch by discharging the set of DFE correction nodes according to a respective set of FETs of the discrete time integration stage receiving a plurality of DFE correction factors; and generating a data decision by driving the differential output of the multi-input summation latch into one of two possible output states according to a summation of currents generated by the first and second sets of input FETs receiving the integrated differential data voltage signal and the integrated aggregate differential DFE correction voltage signal, respectively, and subsequently holding the data decision by holding the differential output of the multi-input summation latch in a latched state for a duration determined by the sampling clock. <EOS>