A neuromorphic circuit comprising: - a matrix network (RN) of discharge neurons, each identified by a neuron address in the network, each neuron being able to receive and process at least one input signal applied to an input of the neuron and then later transmit, on an output of the neuron, an event signal representing a result of the activity of the neuron, - a programmable matrix memory composed of elementary memories (ME1, ME2), each associated with a respective neuron, the elementary memory associated with a neuron comprising a datum, this datum comprising one or more addresses of other neurons and a respective weight associated with each address, - column conductors, each linking all elementary memories of a same column of the matrix memory, - means for extracting, from each elementary memory, the datum relating to a neuron, after this neuron has transmitted an event signal representing a result of the activity of the neuron, - and a processing circuit, comprising an address decoder (DEC), capable of selecting in row and column a determined neuron, and means (DAC, DEC) for applying a weighted input signal to the input of a neuron identified by an address contained in an extracted datum, the input signal being weighted in function of the weight associated with this address in the said datum, - a so-called post-synaptic bus linked to the processing circuit for applying to it data extracted from the programmable matrix memory, each association of a neuron address and its respective weight stored for a datum being transmitted successively to the processing circuit, - a conflicts management circuit disposed between the said at least one column conductor and the post-synaptic bus, characterized in that each elementary memory comprises a logic circuit (CG 11 ) for triggering the extraction of the datum from the elementary memory after reception of the event signal, an activation input (SPK 1 ) of this logic circuit, linked directly to the output of the associated neuron for directly receiving the event signal transmitted by this neuron, and outputs (bl, blb) linked to the post-synaptic bus for transmitting the datum across this bus to the processing circuit. - a matrix network (RN) of discharge neurons, each identified by a neuron address in the network, each neuron being able to receive and process at least one input signal applied to an input of the neuron and then later transmit, on an output of the neuron, an event signal representing a result of the activity of the neuron, - a programmable matrix memory composed of elementary memories (ME1, ME2), each associated with a respective neuron, the elementary memory associated with a neuron comprising a datum, this datum comprising one or more addresses of other neurons and a respective weight associated with each address, - column conductors, each linking all elementary memories of a same column of the matrix memory, - means for extracting, from each elementary memory, the datum relating to a neuron, after this neuron has transmitted an event signal representing a result of the activity of the neuron, - and a processing circuit, comprising an address decoder (DEC), capable of selecting in row and column a determined neuron, and means (DAC, DEC) for applying a weighted input signal to the input of a neuron identified by an address contained in an extracted datum, the input signal being weighted in function of the weight associated with this address in the said datum, - a so-called post-synaptic bus linked to the processing circuit for applying to it data extracted from the programmable matrix memory, each association of a neuron address and its respective weight stored for a datum being transmitted successively to the processing circuit, - a conflicts management circuit disposed between the said at least one column conductor and the post-synaptic bus, <EOS>