A display substrate, comprising: a display region and a peripheral region surrounding the display region; the display region comprises: a plurality of gate lines, a plurality of data lines, and a plurality of pixel units, and each of the plurality of pixel units comprises a driving transistor and a pixel electrode that are connected to each other; and the peripheral region comprises: signal lines and at least one electrostatic discharge structure for performing electrostatic discharge on the signal lines , wherein the electrostatic discharge structure comprises: a third electrostatic discharge pattern arranged in a different layer from the signal lines , wherein a second insulation layer is arranged between the third electrostatic discharge pattern and the signal lines ; and a plurality of conductive patterns connected to the third electrostatic discharge pattern , wherein end portions of a part or all of the conductive patterns away from the third electrostatic discharge pattern are configured as tip portions, characterized in that the third electrostatic discharge pattern comprises a first end portion and a second end portion , wherein an orthogonal projection of the first end portion on the base substrate of the display substrate and an orthogonal projection of the second end portion on the base substrate at least partially overlap an orthogonal projection of the signal lines on the base substrate . the display region comprises: a plurality of gate lines, a plurality of data lines, and a plurality of pixel units, and each of the plurality of pixel units comprises a driving transistor and a pixel electrode that are connected to each other; and the peripheral region comprises: signal lines and at least one electrostatic discharge structure for performing electrostatic discharge on the signal lines , wherein the electrostatic discharge structure comprises: a third electrostatic discharge pattern arranged in a different layer from the signal lines , wherein a second insulation layer is arranged between the third electrostatic discharge pattern and the signal lines ; and a plurality of conductive patterns connected to the third electrostatic discharge pattern , wherein end portions of a part or all of the conductive patterns away from the third electrostatic discharge pattern are configured as tip portions, characterized in that the third electrostatic discharge pattern comprises a first end portion and a second end portion , wherein an orthogonal projection of the first end portion on the base substrate of the display substrate and an orthogonal projection of the second end portion on the base substrate at least partially overlap an orthogonal projection of the signal lines on the base substrate . a third electrostatic discharge pattern arranged in a different layer from the signal lines , wherein a second insulation layer is arranged between the third electrostatic discharge pattern and the signal lines ; and a plurality of conductive patterns connected to the third electrostatic discharge pattern , wherein end portions of a part or all of the conductive patterns away from the third electrostatic discharge pattern are configured as tip portions, characterized in that the third electrostatic discharge pattern comprises a first end portion and a second end portion , wherein an orthogonal projection of the first end portion on the base substrate of the display substrate and an orthogonal projection of the second end portion on the base substrate at least partially overlap an orthogonal projection of the signal lines on the base substrate . <EOS>