A preprocessor circuit for formatting image data into a plurality of streams of image samples, the preprocessor circuit comprising: a first buffer configured to store a plurality of rows of the image data and output a row of the plurality of rows; a second buffer , coupled to the first buffer , including a plurality of storage locations each to store an image sample of the row output by the first buffer ; a plurality of shift registers ; an interconnect network including a plurality of connections , each connection of the plurality of connections coupling a respective one of the plurality of shift registers to more than one of the plurality of storage locations , one or more of the plurality of storage locations being coupled to more than one of the plurality of connections , wherein each connection of the plurality of connections couples a respective shift register of the plurality of shift registers to a different pattern of the plurality of storage locations in the second buffer , wherein the pattern of the plurality of storage locations coupled to a first shift register (712 1 ) of the plurality of shift registers through a first connection of the plurality of connections overlaps the pattern of the plurality of storage locations coupled to a second shift register (712 2 ) of the plurality of shift registers through a second connection of the plurality of connections , wherein the different patterns of the plurality of storage locations are defined by parameters of a convolution between the image data and a filter, the parameters including a width of the filter, a horizontal stride, and a horizontal dilation; and a control circuit configured to parallel-load the plurality of shift registers with the plurality of image samples based on the plurality of connections and shift the plurality of shift registers to output the plurality of streams of image samples. a first buffer configured to store a plurality of rows of the image data and output a row of the plurality of rows; a second buffer , coupled to the first buffer , including a plurality of storage locations each to store an image sample of the row output by the first buffer ; a plurality of shift registers ; an interconnect network including a plurality of connections , each connection of the plurality of connections coupling a respective one of the plurality of shift registers to more than one of the plurality of storage locations , one or more of the plurality of storage locations being coupled to more than one of the plurality of connections , wherein each connection of the plurality of connections couples a respective shift register of the plurality of shift registers to a different pattern of the plurality of storage locations in the second buffer , wherein the pattern of the plurality of storage locations coupled to a first shift register (712 1 ) of the plurality of shift registers through a first connection of the plurality of connections overlaps the pattern of the plurality of storage locations coupled to a second shift register (712 2 ) of the plurality of shift registers through a second connection of the plurality of connections , wherein the different patterns of the plurality of storage locations are defined by parameters of a convolution between the image data and a filter, the parameters including a width of the filter, a horizontal stride, and a horizontal dilation; and a control circuit configured to parallel-load the plurality of shift registers with the plurality of image samples based on the plurality of connections and shift the plurality of shift registers to output the plurality of streams of image samples. <EOS>