A data reception chip arrangement comprising a data reception chip and an external voltage generation module , the data reception chip being coupled to an external memory comprising a first input-output pin to output first data (DQ<0>), the data reception chip comprising: a comparison module coupled to the first input-output pin, configured to receive the first data (DQ<0>), and comparing the first data (DQ<0>) with a first reference voltage (VREF) to identify the value of the first data (DQ<0>); a voltage generation module inside the data reception chip , the voltage generation module being configured to generate the first reference voltage (VREF); a logic unit coupled to the comparison module and the voltage generation module and output at least one switching signal; a detection module detecting the internal state of the logic unit to generate at least one detection signal; and a switching module transmitting the detection signal to a test pin according to the switching signal, wherein the external voltage generation module is provided outside of the data reception chip , wherein the external voltage generation module is coupled to the test pin via an external switch , wherein the external voltage generation module provides the first reference voltage (VREF) to the comparison module via the the test pin when the external switch is turned on, and the first reference voltage (VREF) is provided to the comparison module via the voltage generation module when the external switch is turned off, wherein responsive to the external memory being a DDR3 SDRAM, the external switch is turned on and the voltage generation module is disabled, and wherein responsive to the external memory being a DDR4 SDRAM, the external switch is turned off. a comparison module coupled to the first input-output pin, configured to receive the first data (DQ<0>), and comparing the first data (DQ<0>) with a first reference voltage (VREF) to identify the value of the first data (DQ<0>); a voltage generation module inside the data reception chip , the voltage generation module being configured to generate the first reference voltage (VREF); a logic unit coupled to the comparison module and the voltage generation module and output at least one switching signal; a detection module detecting the internal state of the logic unit to generate at least one detection signal; and a switching module transmitting the detection signal to a test pin according to the switching signal, wherein the external voltage generation module is provided outside of the data reception chip , wherein the external voltage generation module is coupled to the test pin via an external switch , wherein the external voltage generation module provides the first reference voltage (VREF) to the comparison module via the the test pin when the external switch is turned on, and the first reference voltage (VREF) is provided to the comparison module via the voltage generation module when the external switch is turned off, wherein responsive to the external memory being a DDR3 SDRAM, the external switch is turned on and the voltage generation module is disabled, and wherein responsive to the external memory being a DDR4 SDRAM, the external switch is turned off. <EOS>