A method for fabricating a Fin-FET device, comprising: forming (S201) a plurality of discrete fin structures and an isolation layer on a substrate , wherein the plurality of fin structures are separated from each other by the isolation layer , the isolation layer covers a bottom portion of sidewall surfaces of each fin structure, and a top surface of the isolation layer is below a top surface of the fin structures; forming (S202) a dielectric layer on a portion of the isolation layer and also on a portion of sidewall and top surfaces of the plurality of fin structures , wherein another portion of sidewall and top surfaces of the plurality of fin structures is exposed by an opening formed across the plurality of fin structures in the dielectric layer; forming (S203) a first oxidation layer on the exposed portion of sidewall and top surfaces of each fin structure through an oxidation process; forming (S204) a second oxidation layer between the first oxidation layer and the sidewall and the top surfaces of each fin structure through a first annealing process, whereby the atomic percentage concentration of oxygen ions in the second oxidation layer is higher than the atomic percentage concentration of oxygen ions in the first oxidation layer ; forming (S205) a gate dielectric layer on the first oxidation layer , wherein preferably the gate dielectric layer is made of a high-k dielectric material; forming (S206) a sacrificial adsorption layer (210; 310) on the gate dielectric layer , wherein the sacrificial adsorption layer (210; 310) is made of polycrystalline silicon or TiAlC; performing (S207) a second annealing process after forming the sacrificial adsorption layer (210; 310); removing (S208) the sacrificial adsorption layer (210; 310); and forming (S209) a gate electrode layer (212; 312) to fill the opening formed in the dielectric layer . forming (S201) a plurality of discrete fin structures and an isolation layer on a substrate , wherein the plurality of fin structures are separated from each other by the isolation layer , the isolation layer covers a bottom portion of sidewall surfaces of each fin structure, and a top surface of the isolation layer is below a top surface of the fin structures; forming (S202) a dielectric layer on a portion of the isolation layer and also on a portion of sidewall and top surfaces of the plurality of fin structures , wherein another portion of sidewall and top surfaces of the plurality of fin structures is exposed by an opening formed across the plurality of fin structures in the dielectric layer; forming (S203) a first oxidation layer on the exposed portion of sidewall and top surfaces of each fin structure through an oxidation process; forming (S204) a second oxidation layer between the first oxidation layer and the sidewall and the top surfaces of each fin structure through a first annealing process, whereby the atomic percentage concentration of oxygen ions in the second oxidation layer is higher than the atomic percentage concentration of oxygen ions in the first oxidation layer ; forming (S205) a gate dielectric layer on the first oxidation layer , wherein preferably the gate dielectric layer is made of a high-k dielectric material; forming (S206) a sacrificial adsorption layer (210; 310) on the gate dielectric layer , wherein the sacrificial adsorption layer (210; 310) is made of polycrystalline silicon or TiAlC; performing (S207) a second annealing process after forming the sacrificial adsorption layer (210; 310); removing (S208) the sacrificial adsorption layer (210; 310); and forming (S209) a gate electrode layer (212; 312) to fill the opening formed in the dielectric layer . <EOS>