A memory chip for dynamic approximate storage, comprising: an array of memory cells , the array comprising at least two regions , wherein the memory cells comprise at least one of a single level cell or a multi-level cell, wherein the at least two regions have a corresponding at least two types of available error correction overhead; at least one threshold register for storing values for thresholds for memory cells corresponding to each of the at least two regions, wherein the values for thresholds represent resistance thresholds, and wherein the resistance thresholds for the memory cells for at least one of the at least two regions are biased to generate a non-uniform distribution of log scale resistance bands in the memory cells; control logic for controlling the at least one threshold register to programmatically adjust the values for the thresholds for the memory cells, wherein the programmatic adjustments are based on at least one attribute for an allowed error rate for data, the at least one attribute being arranged to indicate to the memory chip from an operating system the allowed error rate associated with certain bits or bytes of data, the thresholds forming levels or binary values in the memory cells of the at least two regions; and at least one bit pattern mapping register for storing a bit pattern table that maps a particular bit pattern to a particular level in a multilevel cell of at least one of the regions of the at least two regions, wherein a bit pattern that is most common is mapped to a highest resistance band and wherein the control logic further comprises control logic to programmatically assign the particular bit pattern being mapped to the particular level. an array of memory cells , the array comprising at least two regions , wherein the memory cells comprise at least one of a single level cell or a multi-level cell, wherein the at least two regions have a corresponding at least two types of available error correction overhead; at least one threshold register for storing values for thresholds for memory cells corresponding to each of the at least two regions, wherein the values for thresholds represent resistance thresholds, and wherein the resistance thresholds for the memory cells for at least one of the at least two regions are biased to generate a non-uniform distribution of log scale resistance bands in the memory cells; control logic for controlling the at least one threshold register to programmatically adjust the values for the thresholds for the memory cells, wherein the programmatic adjustments are based on at least one attribute for an allowed error rate for data, the at least one attribute being arranged to indicate to the memory chip from an operating system the allowed error rate associated with certain bits or bytes of data, the thresholds forming levels or binary values in the memory cells of the at least two regions; and at least one bit pattern mapping register for storing a bit pattern table that maps a particular bit pattern to a particular level in a multilevel cell of at least one of the regions of the at least two regions, wherein a bit pattern that is most common is mapped to a highest resistance band and wherein the control logic further comprises control logic to programmatically assign the particular bit pattern being mapped to the particular level. <EOS>