mhurhangee/patent-ind-claim-en huggingface dataset:
A method comprising: determining an event; determining a first haptic effect based at least in part on the event; determining a second haptic effect based at least in part on the event; transmitting a first haptic signal associated with the first haptic effect to a first haptic output device , wherein the first haptic output device is configured to receive the first haptic signal and output the first haptic effect to a deformable surface ; and transmitting a second haptic signal associated with the second haptic effect to a second haptic output device , wherein the second haptic output device is configured to receive the second haptic signal and output the second haptic effect to the deformable surface; wherein the method further comprises determining a composite haptic effect in response to the event, wherein the first and second haptic effects are configured, when combined, to output the composite haptic effect; characterized in that : the first haptic effect comprises a change in the coefficient of friction of the deformable surface , and the second haptic effect comprises a change in the stiffness of the deformable surface . determining an event; determining a first haptic effect based at least in part on the event; determining a second haptic effect based at least in part on the event; transmitting a first haptic signal associated with the first haptic effect to a first haptic output device , wherein the first haptic output device is configured to receive the first haptic signal and output the first haptic effect to a deformable surface ; and transmitting a second haptic signal associated with the second haptic effect to a second haptic output device , wherein the second haptic output device is configured to receive the second haptic signal and output the second haptic effect to the deformable surface;
A method performed by a base station for wireless communication with a user equipment, UE, the method comprising: identifying a reference signal configuration of a shortened transmission time interval, sTTI, in a subframe, the reference signal configuration including at least one of a channel state information reference signal, CSI-RS, configuration or a cell-specific reference signal, CRS, configuration;selecting, based at least in part on the reference signal configuration of the sTTI, a demodulation reference signal, DMRS, mapping pattern from a plurality of DMRS mapping patterns for mapping DMRS data to resource elements, REs, within the sTTI, wherein the DMRS mapping pattern comprises DMRS data for a first antenna port pair being mapped to a third-lowest-frequency RE and a ninth-lowest-frequency RE within a first, lower frequency, RB of an OFDM symbol and to a fifth-lowest-frequency RE and a twelfth-lowest frequency RE within a second, higher frequency, RB of the OFDM symbol, wherein the sTTI comprises two or three OFDM symbols; configuring REs within the sTTI according to the selected DMRS mapping pattern; and transmitting DMRS data on the configured REs. identifying a reference signal configuration of a shortened transmission time interval, sTTI, in a subframe, the reference signal configuration including at least one of a channel state information reference signal, CSI-RS, configuration or a cell-specific reference signal, CRS, configuration;selecting, based at least in part on the reference signal configuration of the sTTI, a demodulation reference signal, DMRS, mapping pattern from a plurality of DMRS mapping patterns for mapping DMRS data to resource elements, REs, within the sTTI, wherein the DMRS mapping pattern comprises DMRS data for a first antenna port pair being mapped to a third-lowest-frequency RE and a ninth-lowest-frequency RE within a first, lower frequency, RB of an OFDM symbol and to a fifth-lowest-frequency RE and a twelfth-lowest frequency RE within a second, higher frequency, RB of the OFDM symbol, wherein the sTTI comprises two or three OFDM symbols; configuring REs within the sTTI according to the selected DMRS mapping pattern; and transmitting DMRS data on the configured REs.
A memory circuit comprising a first memory word (MW) comprising: a plurality of variable resistors, each variable resistor (VR) forming one memory cell and having a first electrode (BE) and a second electrode (TE) connected to a bit line control circuit (BLDV); and a first selection transistor (ST, ST1) comprising a first conduction terminal connected to the first electrode (BE) of each variable resistor of the first memory word, a second conduction terminal (SL) and a control terminal connected to a word line control circuit (WLDV), wherein: the second conduction terminal (SL) of the first selection transistor (ST, ST1) is connected to a ground of the memory circuit, and each bit line control circuit is configured to set the second electrode (TE) of one of the variable resistors to a high positive voltage (STV) to set the corresponding memory cell, to a high negative voltage (RSV) to reset the corresponding memory cell and to a read voltage to detect whether the corresponding memory cell is set or reset. a plurality of variable resistors, each variable resistor (VR) forming one memory cell and having a first electrode (BE) and a second electrode (TE) connected to a bit line control circuit (BLDV); and a first selection transistor (ST, ST1) comprising a first conduction terminal connected to the first electrode (BE) of each variable resistor of the first memory word, a second conduction terminal (SL) and a control terminal connected to a word line control circuit (WLDV), wherein: the second conduction terminal (SL) of the first selection transistor (ST, ST1) is connected to a ground of the memory circuit, and each bit line control circuit is configured to set the second electrode (TE) of one of the variable resistors to a high positive voltage (STV) to set the corresponding memory cell, to a high negative voltage (RSV) to reset the corresponding memory cell and to a read voltage to detect whether the corresponding memory cell is set or reset. the second conduction terminal (SL) of the first selection transistor (ST, ST1) is connected to a ground of the memory circuit, and each bit line control circuit is configured to set the second electrode (TE) of one of the variable resistors to a high positive voltage (STV) to set the corresponding memory cell, to a high negative voltage (RSV) to reset the corresponding memory cell and to a read voltage to detect whether the corresponding memory cell is set or reset.
A fluid pressure circuit for controlling a rod stroke of a cylinder device in accordance with an operation command, the fluid pressure circuit comprising: a tank having a fluid stored therein; a fluid pressure actuator configured to pressurize the fluid supplied from the tank for extending and retracting the cylinder device ; a flow control valve configured to be arranged between the fluid pressure actuator and the cylinder device and configured to switch a flow passage of the pressurized fluid and to discharge via a first throttle the fluid returned from the cylinder device ; a variable regeneration switching valve configured to discharge the fluid returned from the cylinder device to the flow control valve upon non-regeneration of fluid energy and to, upon regeneration of the fluid energy, branch part of the fluid returned from the cylinder device and discharge via a second throttle the fluid branched; a regenerative motor configured to be driven for the regeneration by the fluid branched by the variable regeneration switching valve ; and a third throttle configured to be connected in series with the first throttle upon the regeneration to limit flow of the fluid returned from the cylinder device , characterized in that Ax = As ⋅ As − Ab / √ ( Ab ⋅ ( 2 × As − Ab)), where As, Ab, and Ax are an opening area of the first throttle, an opening area of the second throttle, and an opening area of the third throttle, respectively, for the operation command. a tank having a fluid stored therein; a fluid pressure actuator configured to pressurize the fluid supplied from the tank for extending and retracting the cylinder device ; a flow control valve configured to be arranged between the fluid pressure actuator and the cylinder device and configured to switch a flow passage of the pressurized fluid and to discharge via a first throttle the fluid returned from the cylinder device ; a variable regeneration switching valve configured to discharge the fluid returned from the cylinder device to the flow control valve upon non-regeneration of fluid energy and to, upon regeneration of the fluid energy, branch part of the fluid returned from the cylinder device and discharge via a second throttle the fluid branched; a regenerative motor configured to be driven for the regeneration by the fluid branched by the variable regeneration switching valve ; and a third throttle configured to be connected in series with the first throttle upon the regeneration to limit flow of the fluid returned from the cylinder device , characterized in that Ax = As ⋅ As − Ab / √ ( Ab ⋅ ( 2 × As − Ab)), where As, Ab, and Ax are an opening area of the first throttle, an opening area of the second throttle, and an opening area of the third throttle, respectively, for the operation command.
A microparticle composition suitable for molecular imaging, the composition comprising microparticles, wherein the microparticles comprise: a core microparticle structure having a central area and a shell, and wherein the core microparticle structure comprises: (i) a phosphatidylcholine lipid; (ii) a phosphatidylethanolamine lipid comprising at least one maleimide moiety; and (iii) an alkoxylated fatty acid, and wherein the molar ratio of (i) to (iii) satisfies the following ranges: (i) 70 to 80; (ii) 5 to 15; and (iii) 10 to 20. (i) a phosphatidylcholine lipid; (ii) a phosphatidylethanolamine lipid comprising at least one maleimide moiety; and (iii) an alkoxylated fatty acid, and (i) 70 to 80; (ii) 5 to 15; and (iii) 10 to 20.
A device comprising: circuitry (106; 116) to: obtain a key usable to search a memory (110; 120) associated with a memory augmented neural network for one or more data sets; perform a stochastic associative search to identify a group of data sets within the memory (110; 120) that satisfy the key; and write to the identified group of data sets concurrently to update the memory augmented neural network , characterized in that concurrently writing to the identified group of data sets comprises writing to columns of the data sets in the identified group using a scatter operation, wherein writing to the identified group using a scatter operation comprises writing to non-contiguous rows defining the data sets of the identified group and the non-contiguous columns of those non-contiguous rows using a template. obtain a key usable to search a memory (110; 120) associated with a memory augmented neural network for one or more data sets; perform a stochastic associative search to identify a group of data sets within the memory (110; 120) that satisfy the key; and write to the identified group of data sets concurrently to update the memory augmented neural network , characterized in that concurrently writing to the identified group of data sets comprises writing to columns of the data sets in the identified group using a scatter operation, wherein writing to the identified group using a scatter operation comprises writing to non-contiguous rows defining the data sets of the identified group and the non-contiguous columns of those non-contiguous rows using a template.
A method for enabling random access of a wireless device being in connected mode in a cell served by a radio network node of a wireless communication system, the method being performed in the radio network node , the method comprising: - allocating a contention-free random access preamble to the wireless device , wherein the contention-free random access preamble is de-allocated after a period of time spanning a plurality of coming random access occasions; - transmitting an indicator of the contention-free random access preamble to the wireless device , for use by the wireless device for performing random access in the cell at a coming random access occasion, the random access being initiated by the wireless device when data is available at the wireless device for uplink transmission; - transmitting a time value defining said period of time to the wireless device ; and characterized by when the contention-free random access preamble is de-allocated: - transmitting an indication to the wireless device that the contention-free random access preamble is de-allocated. - allocating a contention-free random access preamble to the wireless device , wherein the contention-free random access preamble is de-allocated after a period of time spanning a plurality of coming random access occasions; - transmitting an indicator of the contention-free random access preamble to the wireless device , for use by the wireless device for performing random access in the cell at a coming random access occasion, the random access being initiated by the wireless device when data is available at the wireless device for uplink transmission; - transmitting a time value defining said period of time to the wireless device ; and characterized by - transmitting an indication to the wireless device that the contention-free random access preamble is de-allocated.
A computer-implemented method comprising: obtaining , by a client device, respective recipient data for multiple recipients; generating , by the client device, an attestation token comprising a set of data and a digital signature of the set of data; generating , by the client device, an attachment element for each recipient of the multiple recipients, each attachment element comprising the respective recipient data for the recipient and a binding that cryptographically binds the attachment element to the attestation token; and sending , by the client device, a communication that includes the attestation token and the attachment elements to at least one recipient. obtaining , by a client device, respective recipient data for multiple recipients; generating , by the client device, an attestation token comprising a set of data and a digital signature of the set of data; generating , by the client device, an attachment element for each recipient of the multiple recipients, each attachment element comprising the respective recipient data for the recipient and a binding that cryptographically binds the attachment element to the attestation token; and sending , by the client device, a communication that includes the attestation token and the attachment elements to at least one recipient.
A positive active material for a rechargeable lithium battery, comprising particles of a first compound represented by Chemical Formula 1 and particles of a second compound represented by Chemical Formula 2, wherein the particles of the first compound have an average particle diameter D50 of 15 μm to 20 μm and the particles of the second compound have an average particle diameter D50 of 2 μm to 5 μm measured by scanning electron microscopy, SEM, wherein the first compound and the second compound have a Ni content of 50 at% to 60 at% of the metal elements excluding Li: [Chemical Formula 1] Li a Ni x Co y M 1 z O 2 [Chemical Formula 2] Li a Ni x Co y M 2 z O 2 wherein, in Chemical Formula 1 and Chemical Formula 2, 0.9 ≤ a ≤ 1.05, 0.5 ≤ x ≤ 0.6, 0.05 ≤ y ≤0.35, 0.05 ≤ z ≤ 0.35, x + y + z =1, and M 1 and M 2 are independently at least one metal element selected from Mn, Al, Cr, Fe, V, Mg, Ti, Zr, Nb, Mo, W, Cu, Zn, Ga, In, Sn, La, and Ce, wherein at least one of the particles of the first compound and the particles of the second compound comprises a core and a surface layer surrounding the core and a Ni atom concentration (at%) of the metal elements except Li in the surface layer is higher than a Ni atom concentration (at%) of the metal elements except Li in the core. wherein the first compound and the second compound have a Ni content of 50 at% to 60 at% of the metal elements excluding Li: [Chemical Formula 1] Li a Ni x Co y M 1 z O 2 [Chemical Formula 2] Li a Ni x Co y M 2 z O 2 wherein, in Chemical Formula 1 and Chemical Formula 2, 0.9 ≤ a ≤ 1.05, 0.5 ≤ x ≤ 0.6, 0.05 ≤ y ≤0.35, 0.05 ≤ z ≤ 0.35, x + y + z =1, and M 1 and M 2 are independently at least one metal element selected from Mn, Al, Cr, Fe, V, Mg, Ti, Zr, Nb, Mo, W, Cu, Zn, Ga, In, Sn, La, and Ce, wherein at least one of the particles of the first compound and the particles of the second compound comprises a core and a surface layer surrounding the core and a Ni atom concentration (at%) of the metal elements except Li in the surface layer is higher than a Ni atom concentration (at%) of the metal elements except Li in the core.
A smart power unit arranged for managing a hydraulic system , said smart power unit comprising - a hydraulic power pack comprising -- a hydraulic open circuit type pump and -- an electric motor arranged to drive the hydraulic pump, - a hydraulic process computer comprising integrated therein -- a programmable computer board , and -- a sensor board directly connected to the programmable computer board and comprising first one or more sensors (51-.53) arranged to sense operation parameters of the pump and to directly feedback operation parameters of the pump to the programmable computer board, wherein - said hydraulic process computer is arranged to control said electric motor. - a hydraulic power pack comprising -- a hydraulic open circuit type pump and -- an electric motor arranged to drive the hydraulic pump, - a hydraulic process computer comprising integrated therein -- a programmable computer board , and -- a sensor board directly connected to the programmable computer board and comprising first one or more sensors (51-.53) arranged to sense operation parameters of the pump and to directly feedback operation parameters of the pump to the programmable computer board, wherein -- a hydraulic open circuit type pump and -- an electric motor arranged to drive the hydraulic pump, - a hydraulic process computer comprising integrated therein -- a programmable computer board , and -- a sensor board directly connected to the programmable computer board and comprising first one or more sensors (51-.53) arranged to sense operation parameters of the pump and to directly feedback operation parameters of the pump to the programmable computer board, wherein - said hydraulic process computer is arranged to control said electric motor.
An electronic device , the electronic device comprising - a plurality of LEDs , - a driving unit for applying a driving algorithm for driving the LEDs during normal operation, - the electronic device comprising a measurement unit characterized in that the measurement unit comprises an internal current source connectable, sequentially, to each LED of the plurality of LEDs , the measurement unit being adapted for determining the forward voltage of each LED by imposing a test current of said internal current source to each LED , sequentially, during a limited amount of time in order not to disturb the operation mode, and being adapted for using the forward voltage of the LED being tested for determining environmental effects and/or aging effects on the LED . - a plurality of LEDs , - a driving unit for applying a driving algorithm for driving the LEDs during normal operation, - the electronic device comprising a measurement unit characterized in that the measurement unit comprises an internal current source connectable, sequentially, to each LED of the plurality of LEDs , the measurement unit being adapted for determining the forward voltage of each LED by imposing a test current of said internal current source to each LED , sequentially, during a limited amount of time in order not to disturb the operation mode, and being adapted for using the forward voltage of the LED being tested for determining environmental effects and/or aging effects on the LED .
A compute node for managing cache quality of service, QoS, the compute node comprising: a network interface controller, NIC, arranged to include: cache ways prediction circuitry which comprises: means for identifying a total amount of available shared cache ways of a last level cache, LLC, of the compute node, means for determining a workload type associated with each of a plurality of virtual machines, VMs, managed by the compute node based on network traffic to be received by the NIC and processed by each of the plurality of VMs, means for calculating a recommended amount of cache ways for each workload type based on at least one of received shared resource data, received heuristic data, and the total amount of available shared cache ways, wherein the recommended amount of cache ways includes a recommended amount of direct data I/O, DDIO, cache ways and a recommended amount of non-DDIO cache ways; a cache quality of service, QoS, register configured as write accessible only by firmware of the NIC; and cache quality of service, QoS, register management circuitry which comprises: means for updating the cache QoS register to include the recommended amount of cache ways for each workload type. cache ways prediction circuitry which comprises: means for identifying a total amount of available shared cache ways of a last level cache, LLC, of the compute node, means for determining a workload type associated with each of a plurality of virtual machines, VMs, managed by the compute node based on network traffic to be received by the NIC and processed by each of the plurality of VMs, means for calculating a recommended amount of cache ways for each workload type based on at least one of received shared resource data, received heuristic data, and the total amount of available shared cache ways, wherein the recommended amount of cache ways includes a recommended amount of direct data I/O, DDIO, cache ways and a recommended amount of non-DDIO cache ways; means for identifying a total amount of available shared cache ways of a last level cache, LLC, of the compute node, means for determining a workload type associated with each of a plurality of virtual machines, VMs, managed by the compute node based on network traffic to be received by the NIC and processed by each of the plurality of VMs, means for calculating a recommended amount of cache ways for each workload type based on at least one of received shared resource data, received heuristic data, and the total amount of available shared cache ways, wherein the recommended amount of cache ways includes a recommended amount of direct data I/O, DDIO, cache ways and a recommended amount of non-DDIO cache ways; a cache quality of service, QoS, register configured as write accessible only by firmware of the NIC; and cache quality of service, QoS, register management circuitry which comprises: means for updating the cache QoS register to include the recommended amount of cache ways for each workload type.