A digital-to-analog converter, DAC , comprising: an impedance network , comprising a plurality of resistor elements coupled together via a plurality of nodes , wherein the impedance network is configured to be coupled to a reference voltage and to generate a plurality of voltage values at the plurality of nodes; and a transfer function modification circuit comprising a plurality of trim current DACs, an output of each trim current DAC being coupled to a respective node of the plurality of nodes, and the transfer function modification circuit being configured to inject current into, or drain current from, two or more of the plurality of nodes of the impedance network , in order to modify the transfer function of the DAC ; wherein the DAC is configured to select a node , from the plurality of nodes, to generate an analog output voltage; wherein the amount of current injected to or drained from each node is selected by determining a trim code for each trim current DAC, each of the trim codes being dependent on the measured voltage errors at a respective one of the plurality of nodes such that the combined contribution to the voltage at a given node achieves or approximates a desired transfer function, characterized in that each of the trim codes is determined by solving a transfer matrix, the transfer matrix comprising a plurality of transfer coefficients Cij defining the relationship between an input code on a particular trim current DAC and the voltage change on a particular node, wherein i represents the particular node of the plurality of nodes and j represents the particular trim current DAC, wherein: Cij = Vnodej , i − Vnode _ 0 , i / N , wherein Vnode_0,i is the voltage at node i when all trim codes are set to 0 and V_nodej,i is the voltage at each node i when trim current DAC j is set to a particular value N, and wherein N is selected to minimize read errors in the measurements. an impedance network , comprising a plurality of resistor elements coupled together via a plurality of nodes , wherein the impedance network is configured to be coupled to a reference voltage and to generate a plurality of voltage values at the plurality of nodes; and a transfer function modification circuit comprising a plurality of trim current DACs, an output of each trim current DAC being coupled to a respective node of the plurality of nodes, and the transfer function modification circuit being configured to inject current into, or drain current from, two or more of the plurality of nodes of the impedance network , in order to modify the transfer function of the DAC ; wherein the DAC is configured to select a node , from the plurality of nodes, to generate an analog output voltage; wherein the amount of current injected to or drained from each node is selected by determining a trim code for each trim current DAC, each of the trim codes being dependent on the measured voltage errors at a respective one of the plurality of nodes such that the combined contribution to the voltage at a given node achieves or approximates a desired transfer function, characterized in that each of the trim codes is determined by solving a transfer matrix, the transfer matrix comprising a plurality of transfer coefficients Cij defining the relationship between an input code on a particular trim current DAC and the voltage change on a particular node, wherein i represents the particular node of the plurality of nodes and j represents the particular trim current DAC, wherein: Cij = Vnodej , i − Vnode _ 0 , i / N , wherein Vnode_0,i is the voltage at node i when all trim codes are set to 0 and V_nodej,i is the voltage at each node i when trim current DAC j is set to a particular value N, and wherein N is selected to minimize read errors in the measurements. <EOS>