A signal isolator, comprising: a first die portion ; a first metal region electrically connected to the first die portion ; a second die portion isolated from the first die portion ; a second metal region electrically connected to the second die portion ; a third metal region electrically isolated from the first and second metal regions; a third die portio electrically isolated from the first, second and third metal regions and electrically isolated from the first and second die portions , wherein the first metal region , the second metal region , and the third metal region provide a first isolated signal path from the first die portion to the second die portion ; the first metal region , the second metal region and the third die portion provide a second isolated signal path from the first die portion to the second die portion in parallel with the first isolated signal path; the die portions are arranged in a single layer; the first isolated signal path comprises a first capacitor capacitively coupled with a second capacitor , wherein the first capacitor comprises the first metal region and the third metal region , and the second capacitor comprises the third metal region and the second metal region ; and the second isolated signal path includes a third capacitor capacitively coupled to a fourth capacitor , wherein the third capacitor comprises the first metal region and the third die portion , and the fourth capacitor comprises the third die portion and the second metal region . a first die portion ; a first metal region electrically connected to the first die portion ; a second die portion isolated from the first die portion ; a second metal region electrically connected to the second die portion ; a third metal region electrically isolated from the first and second metal regions; a third die portio electrically isolated from the first, second and third metal regions and electrically isolated from the first and second die portions , wherein the first metal region , the second metal region , and the third metal region provide a first isolated signal path from the first die portion to the second die portion ; the first metal region , the second metal region and the third die portion provide a second isolated signal path from the first die portion to the second die portion in parallel with the first isolated signal path; the die portions are arranged in a single layer; the first isolated signal path comprises a first capacitor capacitively coupled with a second capacitor , wherein the first capacitor comprises the first metal region and the third metal region , and the second capacitor comprises the third metal region and the second metal region ; and the second isolated signal path includes a third capacitor capacitively coupled to a fourth capacitor , wherein the third capacitor comprises the first metal region and the third die portion , and the fourth capacitor comprises the third die portion and the second metal region . the first metal region , the second metal region , and the third metal region provide a first isolated signal path from the first die portion to the second die portion ; the first metal region , the second metal region and the third die portion provide a second isolated signal path from the first die portion to the second die portion in parallel with the first isolated signal path; the die portions are arranged in a single layer; the first isolated signal path comprises a first capacitor capacitively coupled with a second capacitor , wherein the first capacitor comprises the first metal region and the third metal region , and the second capacitor comprises the third metal region and the second metal region ; and the second isolated signal path includes a third capacitor capacitively coupled to a fourth capacitor , wherein the third capacitor comprises the first metal region and the third die portion , and the fourth capacitor comprises the third die portion and the second metal region . <EOS>