A manufacturing method of a semiconductor device, the semiconductor device comprising: a first electrode (MSF); a second electrode (MSS) electrically coupled to the first electrode (MSF); a first plating deposition portion (PLF) formed on the first electrode (MSF); and a second plating deposition portion (PLS) formed on the second electrode (MSS) and having an area smaller than an area of the first plating deposition portion (PLF), the method comprising: preparing a semiconductor wafer (WF) including a plurality of chip regions and a dicing region (DA), the first and second electrodes (MSF, MSS) being arranged in each of the chip regions , a third electrode (ESE) electrically coupled to at least one of the first electrode (MSF) and the second electrode (MSS) and being arranged as an electron supplying electrode in the dicing region (DA); performing electroless plating such that the first plating deposition portion (PLF) is formed on the first electrode (MSF), the second plating deposition portion (PLS) is formed on the second electrode (MSS), and a third plating deposition portion is formed on the third electrode (ESE), the third plating deposition portion having an area smaller than the area of the first plating deposition portion (PLF); and cutting the semiconductor wafer (WF) along the dicing region (DA) to form semiconductor chips. a first electrode (MSF); a second electrode (MSS) electrically coupled to the first electrode (MSF); a first plating deposition portion (PLF) formed on the first electrode (MSF); and a second plating deposition portion (PLS) formed on the second electrode (MSS) and having an area smaller than an area of the first plating deposition portion (PLF), the method comprising: preparing a semiconductor wafer (WF) including a plurality of chip regions and a dicing region (DA), the first and second electrodes (MSF, MSS) being arranged in each of the chip regions , a third electrode (ESE) electrically coupled to at least one of the first electrode (MSF) and the second electrode (MSS) and being arranged as an electron supplying electrode in the dicing region (DA); performing electroless plating such that the first plating deposition portion (PLF) is formed on the first electrode (MSF), the second plating deposition portion (PLS) is formed on the second electrode (MSS), and a third plating deposition portion is formed on the third electrode (ESE), the third plating deposition portion having an area smaller than the area of the first plating deposition portion (PLF); and cutting the semiconductor wafer (WF) along the dicing region (DA) to form semiconductor chips. preparing a semiconductor wafer (WF) including a plurality of chip regions and a dicing region (DA), the first and second electrodes (MSF, MSS) being arranged in each of the chip regions , a third electrode (ESE) electrically coupled to at least one of the first electrode (MSF) and the second electrode (MSS) and being arranged as an electron supplying electrode in the dicing region (DA); performing electroless plating such that the first plating deposition portion (PLF) is formed on the first electrode (MSF), the second plating deposition portion (PLS) is formed on the second electrode (MSS), and a third plating deposition portion is formed on the third electrode (ESE), the third plating deposition portion having an area smaller than the area of the first plating deposition portion (PLF); and cutting the semiconductor wafer (WF) along the dicing region (DA) to form semiconductor chips. <EOS>