A chip package structure , comprising: a chip package over a printed circuit board , wherein the chip package includes a substrate and one or more semiconductor dies (108; 108A, 108B; 208A, 208B) disposed over the substrate ; a plurality of conductive elements formed between the substrate and the semiconductor dies (108; 108A, 108B; 208A, 208B); a first plurality of conductive pads formed at a first surface side of the substrate and electrically connected to the conductive elements ; a second plurality of conductive pads formed at a second surface side of the substrate , said second surface side opposite from said first surface side of the substrate ; a plurality of conductive bumps between the chip package and the printed circuit board , wherein a conductive bump among said plurality of conductive bumps is bonded to a first conductive pad among said second plurality of conductive pads ; at least one thermal conductive element between the chip package and the printed circuit board , wherein the thermal conductive element is electrically connected to a second conductive pad among said second plurality of conductive pads , and has a thermal conductivity higher than a thermal conductivity of each of the conductive bumps ; a first bonding layer between the thermal conductive element and the chip package ; and a second bonding layer between the thermal conductive element and the printed circuit board ; wherein the first bonding layer and the second bonding layer are made of different solder materials; wherein the first bonding layer has a melting point higher than that of the second bonding layer . a chip package over a printed circuit board , wherein the chip package includes a substrate and one or more semiconductor dies (108; 108A, 108B; 208A, 208B) disposed over the substrate ; a plurality of conductive elements formed between the substrate and the semiconductor dies (108; 108A, 108B; 208A, 208B); a first plurality of conductive pads formed at a first surface side of the substrate and electrically connected to the conductive elements ; a second plurality of conductive pads formed at a second surface side of the substrate , said second surface side opposite from said first surface side of the substrate ; a plurality of conductive bumps between the chip package and the printed circuit board , wherein a conductive bump among said plurality of conductive bumps is bonded to a first conductive pad among said second plurality of conductive pads ; at least one thermal conductive element between the chip package and the printed circuit board , wherein the thermal conductive element is electrically connected to a second conductive pad among said second plurality of conductive pads , and has a thermal conductivity higher than a thermal conductivity of each of the conductive bumps ; a first bonding layer between the thermal conductive element and the chip package ; and a second bonding layer between the thermal conductive element and the printed circuit board ; wherein the first bonding layer and the second bonding layer are made of different solder materials; wherein the first bonding layer has a melting point higher than that of the second bonding layer . <EOS>