A method for fabricating a Fin-FET device, comprising: forming (s401) a plurality of fin structures , an isolation layer , and an interlayer dielectric layer , on a substrate , wherein the substrate includes an N-type metal-oxide-semiconductor, NMOS, region, the isolation layer covers a portion of sidewall surfaces of the fin structures and has a top surface lower than top surfaces of the fin structures , the interlayer dielectric layer covers the isolation layer ; forming (s401) a first opening in the interlayer dielectric layer , wherein the first opening is formed across the fin structures in the NMOS region (II) and exposes a portion of top and sidewall surfaces of the fin structures in the NMOS region (II), and a corner region (B) is adjacent to a joint between a bottom surface and a sidewall surface of the first opening ; forming (s402) a high-k dielectric layer on the bottom and the sidewall surfaces of the first opening , wherein the high-k dielectric layer covers the portion of the top and the sidewall surfaces of the fin structures exposed in the first opening ; forming (s403) a barrier layer comprising a second work function layer on the high-k dielectric layer in the first opening ; forming (s404) an N-type work function layer on the barrier layer, wherein the N-type work function layer is made of an N-type work function material containing aluminum ions; performing (s405) a back-flow annealing process on the N-type work function layer such that the N-type work function layer has a thickened portion and the barrier layer comprising the second work function layer has a smaller thickness at the corner region (B) and a portion of the N-type work function layer at the corner region (B) includes diffused aluminum ions; and forming (s406) a metal layer on the N-type work function layer to fill up the first opening . forming (s401) a plurality of fin structures , an isolation layer , and an interlayer dielectric layer , on a substrate , wherein the substrate includes an N-type metal-oxide-semiconductor, NMOS, region, the isolation layer covers a portion of sidewall surfaces of the fin structures and has a top surface lower than top surfaces of the fin structures , the interlayer dielectric layer covers the isolation layer ; forming (s401) a first opening in the interlayer dielectric layer , wherein the first opening is formed across the fin structures in the NMOS region (II) and exposes a portion of top and sidewall surfaces of the fin structures in the NMOS region (II), and a corner region (B) is adjacent to a joint between a bottom surface and a sidewall surface of the first opening ; forming (s402) a high-k dielectric layer on the bottom and the sidewall surfaces of the first opening , wherein the high-k dielectric layer covers the portion of the top and the sidewall surfaces of the fin structures exposed in the first opening ; forming (s403) a barrier layer comprising a second work function layer on the high-k dielectric layer in the first opening ; forming (s404) an N-type work function layer on the barrier layer, wherein the N-type work function layer is made of an N-type work function material containing aluminum ions; performing (s405) a back-flow annealing process on the N-type work function layer such that the N-type work function layer has a thickened portion and the barrier layer comprising the second work function layer has a smaller thickness at the corner region (B) and a portion of the N-type work function layer at the corner region (B) includes diffused aluminum ions; and forming (s406) a metal layer on the N-type work function layer to fill up the first opening . <EOS>