A method for incremental-step-pulse programming in a non-volatile memory device, comprising: applying at least one programming pulse to a non-volatile memory cell of the non-volatile memory device during each of a plurality of programming loops including a current programming loop; and comparing a threshold voltage (Vt) of the non-volatile memory cell with a low verify level (VL) and/or a high verify level (VH) of a target data state of the non-volatile memory cell; characterized in that : - if the threshold voltage (Vt) of the non-volatile memory cell is below the high verify level of a target data state of the non-volatile memory cell in all of the previous programming loops and the current programming loop, and the threshold voltage (Vt) is higher than the low verify level of the target data state of the non-volatile memory cell in the current programming loop and/or at least one of the previous programming loops, and a number of programming loops providing a first intermediate voltage as a bitline bias voltage is not greater than a first predetermined number, then providing the first intermediate voltage as a bitline bias voltage in the next programming loop; - if the threshold voltage (Vt) of the non-volatile memory cell is below the high verify level (VH) of a target data state of the non-volatile memory cell in all of the previous programming loops and the current programming loop, and the threshold voltage (Vt) is higher than the low verify level (VL) of the target data state of the non-volatile memory cell in the current programming loop and/or at least one of the previous programming loops, and the number of programming loops providing the first intermediate voltage as a bitline bias voltage is greater than the first predetermined number, providing a second intermediate voltage as the bitline bias voltage in the next programming loop, wherein the second intermediate voltage is higher than the first intermediate voltage. - if the threshold voltage (Vt) of the non-volatile memory cell is below the high verify level of a target data state of the non-volatile memory cell in all of the previous programming loops and the current programming loop, and the threshold voltage (Vt) is higher than the low verify level of the target data state of the non-volatile memory cell in the current programming loop and/or at least one of the previous programming loops, and a number of programming loops providing a first intermediate voltage as a bitline bias voltage is not greater than a first predetermined number, then providing the first intermediate voltage as a bitline bias voltage in the next programming loop; - if the threshold voltage (Vt) of the non-volatile memory cell is below the high verify level (VH) of a target data state of the non-volatile memory cell in all of the previous programming loops and the current programming loop, and the threshold voltage (Vt) is higher than the low verify level (VL) of the target data state of the non-volatile memory cell in the current programming loop and/or at least one of the previous programming loops, and the number of programming loops providing the first intermediate voltage as a bitline bias voltage is greater than the first predetermined number, providing a second intermediate voltage as the bitline bias voltage in the next programming loop, wherein the second intermediate voltage is higher than the first intermediate voltage. <EOS>