A method to be performed by a processor, the processor comprising: a cache memory; fetch and decode circuitry to fetch and decode instructions from a memory ; and execution circuitry comprising a binary translator, BT, to respond to the decoded instructions by: storing a plurality of the decoded instructions in a BT cache ; identifying a delinquent irregular load, DIRRL, among the stored instructions ; determining whether the DIRRL is prefetchable; and if so, generating a custom prefetcher to cause the processor to prefetch a region of instructions leading up to the prefetchable DIRRL, wherein the DIRRL is a delinquent load that experiences greater than a first threshold number of cache misses on successive dynamic instances, wherein the DIRRL is an irregular load having at least a second threshold number of address deltas among its successive dynamic instances, the second threshold number of address deltas covering less than a third threshold number of successive dynamic instances herein and the address deltas being defined as numerical differences between virtual addresses of successive dynamic instances, wherein the execution circuitry computes a backslice between two successive dynamic instances of the DIRRL, and to determine that the DIRRL is prefetchable when the backslice comprises cycles made entirely of non-memory operations or regular memory operations , the backslice of the DIRRL being a set of instructions in a program that are executed prior to and contribute to operands of the DIRRL, and wherein the custom prefetcher causes the processor, when performing prefetching, to focus on one or more critical loads among the backslice by only enqueueing the one or more critical loads and no others in a first-in, first-out, FIFO, buffer, and to perform the one or more critical loads enqueued in the FIFO. a cache memory; fetch and decode circuitry to fetch and decode instructions from a memory ; and execution circuitry comprising a binary translator, BT, to respond to the decoded instructions by: storing a plurality of the decoded instructions in a BT cache ; identifying a delinquent irregular load, DIRRL, among the stored instructions ; determining whether the DIRRL is prefetchable; and if so, generating a custom prefetcher to cause the processor to prefetch a region of instructions leading up to the prefetchable DIRRL, storing a plurality of the decoded instructions in a BT cache ; identifying a delinquent irregular load, DIRRL, among the stored instructions ; determining whether the DIRRL is prefetchable; and if so, generating a custom prefetcher to cause the processor to prefetch a region of instructions leading up to the prefetchable DIRRL, wherein the DIRRL is a delinquent load that experiences greater than a first threshold number of cache misses on successive dynamic instances, wherein the DIRRL is an irregular load having at least a second threshold number of address deltas among its successive dynamic instances, the second threshold number of address deltas covering less than a third threshold number of successive dynamic instances herein and the address deltas being defined as numerical differences between virtual addresses of successive dynamic instances, wherein the execution circuitry computes a backslice between two successive dynamic instances of the DIRRL, and to determine that the DIRRL is prefetchable when the backslice comprises cycles made entirely of non-memory operations or regular memory operations , the backslice of the DIRRL being a set of instructions in a program that are executed prior to and contribute to operands of the DIRRL, and wherein the custom prefetcher causes the processor, when performing prefetching, to focus on one or more critical loads among the backslice by only enqueueing the one or more critical loads and no others in a first-in, first-out, FIFO, buffer, and to perform the one or more critical loads enqueued in the FIFO. <EOS>