A transistor, comprising: a gate (G1) on a substrate (SUB1); a channel layer (C1) having a three-dimensional channel region covering at least a portion of the gate; a source electrode (S10) contacting a first region of the channel layer; and a drain electrode (D10) contacting a second region of the channel layer, wherein the channel layer (C1) covers both side surfaces and a top surface of the gate, and wherein the channel layer (C1) includes graphene; wherein the source electrode (S10) and the drain electrode (D10) are respectively at sides of the gate, the source electrode includes a first source electrode portion (S11) spaced apart from the 3D channel region, and the drain electrode includes a first drain electrode portion (D11) spaced apart from the 3D channel region, wherein the source electrode further includes a second source electrode portion (S12) between the first source electrode portion and the 3D channel region; and the drain electrode further includes a second drain electrode portion (D12) between the first drain electrode portion and the 3D channel region; characterised in that each of the first source electrode portion (S11) and the first drain electrode portion (D11) has a height greater than a height of the 3D channel region ; wherein each of the second source electrode portion (S12) and the second drain electrode portion (D12) has a height equal to, or less than, a height of the 3D channel region , so that the effective channel length of the transistor is determined by the height of each of the second source electrode portion and the second drain electrode portion. a gate (G1) on a substrate (SUB1); a channel layer (C1) having a three-dimensional channel region covering at least a portion of the gate; a source electrode (S10) contacting a first region of the channel layer; and a drain electrode (D10) contacting a second region of the channel layer, wherein the channel layer (C1) covers both side surfaces and a top surface of the gate, and wherein the channel layer (C1) includes graphene; wherein the source electrode (S10) and the drain electrode (D10) are respectively at sides of the gate, the source electrode includes a first source electrode portion (S11) spaced apart from the 3D channel region, and the drain electrode includes a first drain electrode portion (D11) spaced apart from the 3D channel region, wherein the source electrode further includes a second source electrode portion (S12) between the first source electrode portion and the 3D channel region; and the drain electrode further includes a second drain electrode portion (D12) between the first drain electrode portion and the 3D channel region; characterised in that each of the first source electrode portion (S11) and the first drain electrode portion (D11) has a height greater than a height of the 3D channel region ; wherein each of the second source electrode portion (S12) and the second drain electrode portion (D12) has a height equal to, or less than, a height of the 3D channel region , so that the effective channel length of the transistor is determined by the height of each of the second source electrode portion and the second drain electrode portion. <EOS>