A frequency governor system for a processor having a first core, the system comprising: a power state data collection subsystem configured to read power management information from the processor, wherein the processor is configured to selectively operate in a plurality of power saving states (C1, C3, C5, C6, C7), wherein the power management information includes (i) first information indicating occupancy of the first core of the processor in an active state (C0) and (ii) second information indicating occupancy of the first core of the processor in a subset (C5, C6, C7) of the plurality of power saving states, and wherein the one or more power saving states of the subset present a latency of the first core to return to the active state that is the greatest among the plurality of power saving states; a utilization analyzer configured to generate an effective utilization based on the first information and the second information; and a frequency control circuit configured to: set a target frequency by performing a selected action of: a first action including increasing the target frequency; and a second action including decreasing the target frequency with respect to a current frequency of the processor based on the effective utilization, wherein the selected action is selected according to the effective utilization; and instruct the processor to operate the first core at the target frequency. a power state data collection subsystem configured to read power management information from the processor, wherein the processor is configured to selectively operate in a plurality of power saving states (C1, C3, C5, C6, C7), wherein the power management information includes (i) first information indicating occupancy of the first core of the processor in an active state (C0) and (ii) second information indicating occupancy of the first core of the processor in a subset (C5, C6, C7) of the plurality of power saving states, and wherein the one or more power saving states of the subset present a latency of the first core to return to the active state that is the greatest among the plurality of power saving states; a utilization analyzer configured to generate an effective utilization based on the first information and the second information; and a frequency control circuit configured to: set a target frequency by performing a selected action of: a first action including increasing the target frequency; and a second action including decreasing the target frequency with respect to a current frequency of the processor based on the effective utilization, wherein the selected action is selected according to the effective utilization; and instruct the processor to operate the first core at the target frequency. set a target frequency by performing a selected action of: a first action including increasing the target frequency; and a second action including decreasing the target frequency with respect to a current frequency of the processor based on the effective utilization, wherein the selected action is selected according to the effective utilization; and a first action including increasing the target frequency; and a second action including decreasing the target frequency with respect to a current frequency of the processor based on the effective utilization, wherein the selected action is selected according to the effective utilization; and instruct the processor to operate the first core at the target frequency. <EOS>