A random code generator , wherein the random code generator comprises: an address Y decoder comprising plural Y control lines (Y0∼Y255), wherein the address Y decoder selectively activates the plural Y control lines (Y0∼Y255) according to a first address Y signal (Addr_Y); an address X decoder comprising plural X control lines (X0∼X255), wherein the address X decoder selectively activates the plural X control lines (X0∼X255) according to a first address X signal (Addr_X); an address Y generator connected with the address Y decoder , wherein the address Y generator receives a first clock signal (CK1) and continuously generates the first address Y signal (Addr_Y) to the address Y decoder ; an address X generator connected with the address X decoder , wherein the address X generator receives a second clock signal (CK2) and continuously generates the first address X signal (Addr_X) to the address X decoder ; a PUF entropy pool connected with the plural Y control lines (Y0∼Y255) and the plural X control lines (XO-X255), wherein the PUF entropy pool generates an output data (Do) according to the activated Y control lines and the activated X control lines; a processing circuit connected with the PUF entropy pool to receive the output data (Do); and an entropy key storage circuit connected with the PUF entropy pool to receive plural entropy keys (Key_1∼Key_x) from the PUF entropy pool , wherein when the random code generator is in a normal working state, the entropy key storage circuit provides at least one entropy key of the plural entropy keys (Key_1∼Key_x) to the processing circuit , and the processing circuit processes the output data (Do) into a random code stream (Code_r) according to the at least one entropy key, the first clock signal (CK1) and the second clock signal (CK2); wherein the address Y generator and the address X generator are linear feedback shift registers or deterministic random bit generators. an address Y decoder comprising plural Y control lines (Y0∼Y255), wherein the address Y decoder selectively activates the plural Y control lines (Y0∼Y255) according to a first address Y signal (Addr_Y); an address X decoder comprising plural X control lines (X0∼X255), wherein the address X decoder selectively activates the plural X control lines (X0∼X255) according to a first address X signal (Addr_X); an address Y generator connected with the address Y decoder , wherein the address Y generator receives a first clock signal (CK1) and continuously generates the first address Y signal (Addr_Y) to the address Y decoder ; an address X generator connected with the address X decoder , wherein the address X generator receives a second clock signal (CK2) and continuously generates the first address X signal (Addr_X) to the address X decoder ; a PUF entropy pool connected with the plural Y control lines (Y0∼Y255) and the plural X control lines (XO-X255), wherein the PUF entropy pool generates an output data (Do) according to the activated Y control lines and the activated X control lines; a processing circuit connected with the PUF entropy pool to receive the output data (Do); and an entropy key storage circuit connected with the PUF entropy pool to receive plural entropy keys (Key_1∼Key_x) from the PUF entropy pool , wherein when the random code generator is in a normal working state, the entropy key storage circuit provides at least one entropy key of the plural entropy keys (Key_1∼Key_x) to the processing circuit , and the processing circuit processes the output data (Do) into a random code stream (Code_r) according to the at least one entropy key, the first clock signal (CK1) and the second clock signal (CK2); wherein the address Y generator and the address X generator are linear feedback shift registers or deterministic random bit generators. <EOS>