A digital signal processor comprising: a data register file including a plurality of data registers designated by register number and storing data; an instruction memory storing instructions each specifying a data processing operation and at least one data operand field; an instruction decoder connected to the instruction memory for determining the specified data processing operation and the specified at least one operand, and an instruction fetch unit for sequentially recalling instructions from the instruction memory; at least one functional unit connected to the data register file and the instruction decoder for performing data processing operations upon at least one operand corresponding to an instruction decoded by the instruction decoder and storing results in an instruction specified data register; a streaming engine connected to the instruction decoder operable in response to a stream start instruction to recall from memory a stream of a specified sequence of data elements, the streaming engine including a stream head register storing a data element of the stream next to be used; and wherein the instruction decoder is operable to: decode an instruction having a data operand field having a first subset of bit codings to supply data stored in a corresponding data register to a corresponding functional unit; decode an instruction having a data operand field having a predetermined read bit coding to supply the data stored in the stream head register to the corresponding functional unit; and decode an instruction having a data operand field having a predetermined read/advance bit coding to supply the data stored in the stream head register to the corresponding functional unit and to advance the streaming engine by storing a next sequential data element of the stream in the stream head register. a data register file including a plurality of data registers designated by register number and storing data; an instruction memory storing instructions each specifying a data processing operation and at least one data operand field; an instruction decoder connected to the instruction memory for determining the specified data processing operation and the specified at least one operand, and an instruction fetch unit for sequentially recalling instructions from the instruction memory; at least one functional unit connected to the data register file and the instruction decoder for performing data processing operations upon at least one operand corresponding to an instruction decoded by the instruction decoder and storing results in an instruction specified data register; a streaming engine connected to the instruction decoder operable in response to a stream start instruction to recall from memory a stream of a specified sequence of data elements, the streaming engine including a stream head register storing a data element of the stream next to be used; and wherein the instruction decoder is operable to: decode an instruction having a data operand field having a first subset of bit codings to supply data stored in a corresponding data register to a corresponding functional unit; decode an instruction having a data operand field having a predetermined read bit coding to supply the data stored in the stream head register to the corresponding functional unit; and decode an instruction having a data operand field having a predetermined read/advance bit coding to supply the data stored in the stream head register to the corresponding functional unit and to advance the streaming engine by storing a next sequential data element of the stream in the stream head register. <EOS>