A programming and verifying method for a non-volatile multi-level memory cell array, the non-volatile multi-level memory cell array comprising a first row, a plurality of floating gate memory cells (c11~c1n) in the first row being connected with a first word line (WL1), a source line (SL), an erase line (EL) and a plurality of bit lines (BL1~BLn), the plurality of floating gate memory cells (c11~c1n) being separated by a shielding line (SH), each of the plurality of floating gate memory cells (c11~c1n) being programmed to a target storage state of X storage states, X being an integer larger than or equal to 4, the programming and verifying method comprising steps of: (a1) determining the first row as a selected row (S504) by activating the first word line (WL1), and setting A as 1 (S506) for indicating a stage of programming to a first storage state; (a2) programming first-portion memory cells of the selected row to the A-th storage state, wherein the memory cells in the selected row excluding the memory cells in the target storage state and bad memory cells are defined as the first-portion memory cells of the selected row (S508), and wherein the bad memory cells cannot reach the A-th storage state; (a3) if A is not equal to X (S510), adding 1 to A (S512) for indicating a stage of programming to the (A+1)-th storage state, and performing the step (a2) again; (a4) if A is equal to X (S510), ending the program cycle, wherein A is an integer smaller than or equal to X, wherein in the step (a2), the first-portion memory cells of the selected row are subjected to a plurality of write actions and a plurality of verification actions until all of the first-portion memory cells reach the A-th storage state; and wherein during a read cycle and a program cycle of the non-volatile multi-level memory cell array, the shielding line (SH) and the erase line (EL) receive a same voltage to prevent from a coupling effect between the plurality of floating gate memory cells (c11~c1n). (a1) determining the first row as a selected row (S504) by activating the first word line (WL1), and setting A as 1 (S506) for indicating a stage of programming to a first storage state; (a2) programming first-portion memory cells of the selected row to the A-th storage state, wherein the memory cells in the selected row excluding the memory cells in the target storage state and bad memory cells are defined as the first-portion memory cells of the selected row (S508), and wherein the bad memory cells cannot reach the A-th storage state; (a3) if A is not equal to X (S510), adding 1 to A (S512) for indicating a stage of programming to the (A+1)-th storage state, and performing the step (a2) again; (a4) if A is equal to X (S510), ending the program cycle, wherein A is an integer smaller than or equal to X, wherein in the step (a2), the first-portion memory cells of the selected row are subjected to a plurality of write actions and a plurality of verification actions until all of the first-portion memory cells reach the A-th storage state; and wherein during a read cycle and a program cycle of the non-volatile multi-level memory cell array, the shielding line (SH) and the erase line (EL) receive a same voltage to prevent from a coupling effect between the plurality of floating gate memory cells (c11~c1n). <EOS>