A semiconductor structure comprising: a substrate ; a plurality of first active columns , arranged in an array along a first direction and a second direction; wherein both the first direction and the second direction are perpendicular to an extension direction of the first active column , and the first direction is intersected with the second direction; a plurality of first electrodes , arranged at intervals; wherein each of the first electrodes covers a side wall of a respective one of the first active columns ; a plurality of first dielectric layers ; wherein each of the first dielectric layers covers a side wall of one of the first electrodes and a bottom of a gap between two adjacent first electrodes ; second electrodes covering surfaces of the plurality of first dielectric layers ; wherein the first dielectric layer covers a top surface of a first sacrificial layer a plurality of third active columns, wherein each of the third active columns is located on a top surface of a corresponding first active column ; and a plurality of transistors, wherein each of the transistors has a channel structure located in the third active column and having an extension direction perpendicular to the plane where the first direction and the second direction are located; characterized in that a second oxide layer (103-3) is formed on a surface of the substrate ; a plurality of oxide columns (103-1) are located on the second oxide layer (103-3); wherein each of the first active columns is located on a top surface of a corresponding oxide column (103-1); the first sacrificial layer is located in a gap between the plurality of the oxide columns (103-1). a substrate ; a plurality of first active columns , arranged in an array along a first direction and a second direction; wherein both the first direction and the second direction are perpendicular to an extension direction of the first active column , and the first direction is intersected with the second direction; a plurality of first electrodes , arranged at intervals; wherein each of the first electrodes covers a side wall of a respective one of the first active columns ; a plurality of first dielectric layers ; wherein each of the first dielectric layers covers a side wall of one of the first electrodes and a bottom of a gap between two adjacent first electrodes ; second electrodes covering surfaces of the plurality of first dielectric layers ; wherein the first dielectric layer covers a top surface of a first sacrificial layer a plurality of third active columns, wherein each of the third active columns is located on a top surface of a corresponding first active column ; and a plurality of transistors, wherein each of the transistors has a channel structure located in the third active column and having an extension direction perpendicular to the plane where the first direction and the second direction are located; characterized in that a second oxide layer (103-3) is formed on a surface of the substrate ; a plurality of oxide columns (103-1) are located on the second oxide layer (103-3); wherein each of the first active columns is located on a top surface of a corresponding oxide column (103-1); the first sacrificial layer is located in a gap between the plurality of the oxide columns (103-1). <EOS>