A processor comprising: one or more model specific registers, MSRs, comprising a user-enabled field which, when set by an operating system or a system BIOS, configures the processor to be in a first execution state to specify support of a user-level thread synchronization architecture, and which, when not set, restricts address monitoring and power management to privilege level zero; and a plurality of execution cores having corresponding monitored address state storage configured to store a last monitored address for each of a plurality of execution threads that issues a MONITOR request and a cache memory configured to record MONITOR requests and associated states for addresses of memory storage locations in the monitored address state storage , wherein the processor , responsive to receipt of a MONITOR request for an address from an execution thread of the user-level, is configured to store, as the last monitored address in the monitored address state storage , the address and record an associated state of the monitored address for a first execution core of the plurality of execution cores associated with the execution thread when the processor is configured to be in the first execution state, and, further responsive to receipt of an MWAIT request from the execution thread for the address, is configured to record an associated wait-to-trigger state of the monitored address for said first execution core associated with the execution thread, wherein the first execution core is configured to transition the execution thread to an optimized sleep state responsive to the receipt of said MWAIT request from the execution thread when the processor is configured to be in the first execution state, and wherein the optimized sleep state is a C1 state, while transitions to deeper sleep states are reserved only for MWAIT requests at a privilege level zero. one or more model specific registers, MSRs, comprising a user-enabled field which, when set by an operating system or a system BIOS, configures the processor to be in a first execution state to specify support of a user-level thread synchronization architecture, and which, when not set, restricts address monitoring and power management to privilege level zero; and a plurality of execution cores having corresponding monitored address state storage configured to store a last monitored address for each of a plurality of execution threads that issues a MONITOR request and a cache memory configured to record MONITOR requests and associated states for addresses of memory storage locations in the monitored address state storage , wherein the processor , responsive to receipt of a MONITOR request for an address from an execution thread of the user-level, is configured to store, as the last monitored address in the monitored address state storage , the address and record an associated state of the monitored address for a first execution core of the plurality of execution cores associated with the execution thread when the processor is configured to be in the first execution state, and, further responsive to receipt of an MWAIT request from the execution thread for the address, is configured to record an associated wait-to-trigger state of the monitored address for said first execution core associated with the execution thread, wherein the first execution core is configured to transition the execution thread to an optimized sleep state responsive to the receipt of said MWAIT request from the execution thread when the processor is configured to be in the first execution state, and wherein the optimized sleep state is a C1 state, while transitions to deeper sleep states are reserved only for MWAIT requests at a privilege level zero. <EOS>