An apparatus for generating an identification key, the apparatus comprising: a reader configured to determine whether a first node and a second node are shorted and to provide an identification key; characterized by a first conductive layer formed in a semiconductor chip, associated with the first node , the first conductive layer having a first edge; a second conductive layer formed in the semiconductor chip, associated with the second node , the second conductive layer having a second edge in parallel with the first edge, the first and second conductive layer extending in mutually opposite directions from the first and second edge respectively in the layout, a spacing (S) in the layout, between the first and second edge, being equal to or greater than a first threshold (S1) and equal to or less than a second threshold (S2), wherein the first threshold (S1) is equal to or greater than a maximum spacing between the first conductive layer and the second conductive layer to guarantee that the first node and the second node are shorted by the first conductive layer and the second conductive layer, and wherein the second threshold (S2) is equal to or less than a minimum spacing between the first conductive layer and the second conductive layer to guarantee that the first node and the second node are open by the first conductive layer and the second conductive layer wherein the first node and the second node associated with the second conductive layer are randomly shorted or opened based upon a process variation occurring in the semiconductor chip, the process variation causing a layer to remain between the first node and the second node locally along the edges. a reader configured to determine whether a first node and a second node are shorted and to provide an identification key; characterized by a first conductive layer formed in a semiconductor chip, associated with the first node , the first conductive layer having a first edge; a second conductive layer formed in the semiconductor chip, associated with the second node , the second conductive layer having a second edge in parallel with the first edge, the first and second conductive layer extending in mutually opposite directions from the first and second edge respectively in the layout, a spacing (S) in the layout, between the first and second edge, being equal to or greater than a first threshold (S1) and equal to or less than a second threshold (S2), wherein the first threshold (S1) is equal to or greater than a maximum spacing between the first conductive layer and the second conductive layer to guarantee that the first node and the second node are shorted by the first conductive layer and the second conductive layer, and wherein the second threshold (S2) is equal to or less than a minimum spacing between the first conductive layer and the second conductive layer to guarantee that the first node and the second node are open by the first conductive layer and the second conductive layer wherein the first node and the second node associated with the second conductive layer are randomly shorted or opened based upon a process variation occurring in the semiconductor chip, the process variation causing a layer to remain between the first node and the second node locally along the edges. <EOS>