An insulation detection circuit for a two-way on-board charger, comprising an inverter circuit, and further comprising a live line sampling circuit and a neutral line sampling circuit correspondingly connected with an output live line (L) and an output neutral line (N) of the inverter circuit, and a controller (MCU) connected with the live line sampling circuit and the neutral line sampling circuit, wherein the controller determines an insulation state of the two-way on-board charger according to sampling voltages (VL, VN) respectively output by the two sampling circuits, characterized in that said insulation detection circuit further comprises a first Y capacitor (C1) connected between said output live line and a ground line of said inverter circuit, and a second Y capacitor (C2) connected between said output neutral line and said ground line of said inverter circuit, wherein the live line sampling circuit and the neutral line sampling circuit have a same circuit structure, and each comprises a voltage dividing circuit (R1, R6 and R2, R5, respectively), a bias power source (v_pwl1), a bias circuit (R4 and R3, respectively), and an impedance matching circuit, wherein: the voltage dividing circuit is connected with the output live line or the output neutral line, and configured to proportionally reduce voltages to output a divided voltage (VC, VB); the bias circuit is connected between an output terminal (C, B) of the voltage dividing circuit and the bias power source and configured to bias the divided voltage; and the impedance matching circuit is connected with the output terminal of the voltage dividing circuit, and configured to perform impedance matching and output a sampling voltage. characterized in that said insulation detection circuit further comprises a first Y capacitor (C1) connected between said output live line and a ground line of said inverter circuit, and a second Y capacitor (C2) connected between said output neutral line and said ground line of said inverter circuit, wherein the live line sampling circuit and the neutral line sampling circuit have a same circuit structure, and each comprises a voltage dividing circuit (R1, R6 and R2, R5, respectively), a bias power source (v_pwl1), a bias circuit (R4 and R3, respectively), and an impedance matching circuit, wherein: the voltage dividing circuit is connected with the output live line or the output neutral line, and configured to proportionally reduce voltages to output a divided voltage (VC, VB); the bias circuit is connected between an output terminal (C, B) of the voltage dividing circuit and the bias power source and configured to bias the divided voltage; and the impedance matching circuit is connected with the output terminal of the voltage dividing circuit, and configured to perform impedance matching and output a sampling voltage. the voltage dividing circuit is connected with the output live line or the output neutral line, and configured to proportionally reduce voltages to output a divided voltage (VC, VB); the bias circuit is connected between an output terminal (C, B) of the voltage dividing circuit and the bias power source and configured to bias the divided voltage; and the impedance matching circuit is connected with the output terminal of the voltage dividing circuit, and configured to perform impedance matching and output a sampling voltage. <EOS>