An erasable programmable single-poly nonvolatile memory, comprising: a substrate structure, an N-well region (NW), a P-well region (PW, p1, p2, p3) and isolation structures formed in said substrate structure, wherein one isolation structure is formed between said N-well region (NW) and said P-well region (PW); a floating gate transistor comprising a floating gate , a gate oxide layer under the floating gate , and a channel region, wherein the channel region is formed in said N-well region (NW); and an erase gate region (38, p1, p2, p3, 62, 64) wherein the floating gate extends over the erase gate region (38, p1, p2, p3, 62, 64) and the erase gate region comprises said P-well region (PW, p1, p2, p3) and a first n-type region connected to an erase line voltage (V EL ); characterized in that the gate oxide layer comprises a first portion above the channel region of the floating gate transistor and a second portion above the erase gate region, and a thickness of the first portion of the gate oxide layer is thicker than a thickness of the second portion of the gate oxide layer ; the P-well region (PW) comprises: a first p-type region (p1) formed under a surface of the substrate structure and contacted to the first n-type region ; two second p-type regions (p2); and a third p-type region (p3) formed under the first p-type region (p1); and the first p-type region (p1) and the third p-type region (p3) are located between the second p-type regions (p2), said two second p-type regions (p2) being located under said one isolation structure and under another isolation structure , respectively; and a dosage in the second p-type regions (p2) is higher than a dosage in the first p-type region (p1), and a dosage in the third p-type region (p3) is higher than the dosage in the first p-type region (p1). a substrate structure, an N-well region (NW), a P-well region (PW, p1, p2, p3) and isolation structures formed in said substrate structure, wherein one isolation structure is formed between said N-well region (NW) and said P-well region (PW); a floating gate transistor comprising a floating gate , a gate oxide layer under the floating gate , and a channel region, wherein the channel region is formed in said N-well region (NW); and an erase gate region (38, p1, p2, p3, 62, 64) wherein the floating gate extends over the erase gate region (38, p1, p2, p3, 62, 64) and the erase gate region comprises said P-well region (PW, p1, p2, p3) and a first n-type region connected to an erase line voltage (V EL ); characterized in that the gate oxide layer comprises a first portion above the channel region of the floating gate transistor and a second portion above the erase gate region, and a thickness of the first portion of the gate oxide layer is thicker than a thickness of the second portion of the gate oxide layer ; the P-well region (PW) comprises: a first p-type region (p1) formed under a surface of the substrate structure and contacted to the first n-type region ; two second p-type regions (p2); and a third p-type region (p3) formed under the first p-type region (p1); and the first p-type region (p1) and the third p-type region (p3) are located between the second p-type regions (p2), said two second p-type regions (p2) being located under said one isolation structure and under another isolation structure , respectively; and a dosage in the second p-type regions (p2) is higher than a dosage in the first p-type region (p1), and a dosage in the third p-type region (p3) is higher than the dosage in the first p-type region (p1). <EOS>