An arithmetic processing device, comprising: a first instruction execution unit configured to include plural staging latches and execute a first instruction by a pipeline operation requiring only a single clock for transition of data between first plural staging latches including a staging latch at a final stage from among the plural staging latches, and a multi-cycle operation requiring plural clocks for transition of data between second plural staging latches positioned at a previous stage side from the first plural staging latches, from among the plural staging latches; a second instruction execution unit configured to execute a second instruction, wherein a part of the first instruction and a part of the second instruction share resources relating to the execution of the multi-cycle operation , and the first instruction and the second instruction use some of the same resources for execution; and an instruction control unit configured to input the first instruction and the second instruction, issue the first instruction to the first instruction execution unit and issue the second instruction to the second instruction execution unit, wherein issuance of the second instruction is prohibited for a period such that the execution of the first instruction and the execution of the second instruction are partly overlapped; wherein the instruction control unit determines an indefinite finish cycle of the first instruction while the first instruction execution unit executes the first instruction, and releases suppression of issuance to the second instruction execution unit of the second instruction in accordance with the determined finish cycle. a first instruction execution unit configured to include plural staging latches and execute a first instruction by a pipeline operation requiring only a single clock for transition of data between first plural staging latches including a staging latch at a final stage from among the plural staging latches, and a multi-cycle operation requiring plural clocks for transition of data between second plural staging latches positioned at a previous stage side from the first plural staging latches, from among the plural staging latches; a second instruction execution unit configured to execute a second instruction, wherein a part of the first instruction and a part of the second instruction share resources relating to the execution of the multi-cycle operation , and the first instruction and the second instruction use some of the same resources for execution; and an instruction control unit configured to input the first instruction and the second instruction, issue the first instruction to the first instruction execution unit and issue the second instruction to the second instruction execution unit, wherein issuance of the second instruction is prohibited for a period such that the execution of the first instruction and the execution of the second instruction are partly overlapped; wherein the instruction control unit determines an indefinite finish cycle of the first instruction while the first instruction execution unit executes the first instruction, and releases suppression of issuance to the second instruction execution unit of the second instruction in accordance with the determined finish cycle. <EOS>