A three-dimensional memory device , comprising: a P-type doped region of a substrate; an N-type doped semiconductor layer on the P-type doped region ; a memory stack comprising interleaved conductive layers and dielectric layers on the N-type doped semiconductor layer ; a channel structure extending vertically through the memory stack and the N-type doped semiconductor layer into the P-type doped region wherein the channel structure comprises a memory film and a semiconductor channel , and part of the semiconductor channel along the sidewall of the channel structure is in contact with the N-type doped semiconductor layer ; an N-type doped semiconductor plug extending vertically into the P-type doped region ; and a source contact structure extending vertically through the memory stack to be in contact with the N-type doped semiconductor plug , wherein a lateral dimension of the N-type doped semiconductor plug is greater than a lateral dimension of the source contact structure , wherein a lateral dimension of a portion of the N-type doped semiconductor plug surrounded by the P-type doped region is greater than a lateral dimension of a portion of the N-type doped semiconductor plug surrounded by the N-type doped semiconductor layer , wherein a lateral dimension of N-type doped semiconductor plug is the minimum lateral dimension along the vertical direction, and a lateral dimension of source contact structure is the maximum lateral dimension along the vertical direction, such that any lateral dimension of N-type doped semiconductor plug is greater than any lateral dimension of the source contact structure . a P-type doped region of a substrate; an N-type doped semiconductor layer on the P-type doped region ; a memory stack comprising interleaved conductive layers and dielectric layers on the N-type doped semiconductor layer ; a channel structure extending vertically through the memory stack and the N-type doped semiconductor layer into the P-type doped region wherein the channel structure comprises a memory film and a semiconductor channel , and part of the semiconductor channel along the sidewall of the channel structure is in contact with the N-type doped semiconductor layer ; an N-type doped semiconductor plug extending vertically into the P-type doped region ; and a source contact structure extending vertically through the memory stack to be in contact with the N-type doped semiconductor plug , wherein a lateral dimension of the N-type doped semiconductor plug is greater than a lateral dimension of the source contact structure , wherein a lateral dimension of a portion of the N-type doped semiconductor plug surrounded by the P-type doped region is greater than a lateral dimension of a portion of the N-type doped semiconductor plug surrounded by the N-type doped semiconductor layer , wherein a lateral dimension of N-type doped semiconductor plug is the minimum lateral dimension along the vertical direction, and a lateral dimension of source contact structure is the maximum lateral dimension along the vertical direction, such that any lateral dimension of N-type doped semiconductor plug is greater than any lateral dimension of the source contact structure . <EOS>