A semiconductor package comprising: a metal plate comprising a first surface , a second surface opposite to the first surface and a side surface between the first surface and the second surface ; a conductive layer comprising a first surface and a second surface opposite to the first surface; a semiconductor chip on the first surface of the metal plate , the semiconductor chip comprising a first surface , a second surface opposite to the first surface and a side surface between the first surface and the second surface; a first insulating layer that covers the second surface of the metal plate ; a second insulating layer that covers the first surface of the metal plate , and the first surface and the side surface of the semiconductor chip ; and a wiring structure on the second insulating layer and comprising: a wiring layer electrically connected to the semiconductor chip ; and an interlayer insulating layer on the wiring layer , wherein a thickness of the metal plate is thinner than that of the semiconductor chip , and wherein the side surface of the metal plate is covered by the first insulating layer or the second insulating layer characterised in that the first surface of the conductive layer is flush with the first surface of the metal plate , and the second surface of the conductive layer is flush with the second surface of the metal plate , wherein the second insulating layer is exposed in an annular shape between the conductive layer and the metal plate , and the metal plate surrounds the conductive layer , and wherein the second surface of the conductive layer , which is exposed from the first insulating layer , is configured as a pad to be electrically connected to another semiconductor package. a metal plate comprising a first surface , a second surface opposite to the first surface and a side surface between the first surface and the second surface ; a conductive layer comprising a first surface and a second surface opposite to the first surface; a semiconductor chip on the first surface of the metal plate , the semiconductor chip comprising a first surface , a second surface opposite to the first surface and a side surface between the first surface and the second surface; a first insulating layer that covers the second surface of the metal plate ; a second insulating layer that covers the first surface of the metal plate , and the first surface and the side surface of the semiconductor chip ; and a wiring structure on the second insulating layer and comprising: a wiring layer electrically connected to the semiconductor chip ; and an interlayer insulating layer on the wiring layer , a wiring layer electrically connected to the semiconductor chip ; and an interlayer insulating layer on the wiring layer , wherein a thickness of the metal plate is thinner than that of the semiconductor chip , and wherein the side surface of the metal plate is covered by the first insulating layer or the second insulating layer characterised in that the first surface of the conductive layer is flush with the first surface of the metal plate , and the second surface of the conductive layer is flush with the second surface of the metal plate , wherein the second insulating layer is exposed in an annular shape between the conductive layer and the metal plate , and the metal plate surrounds the conductive layer , and wherein the second surface of the conductive layer , which is exposed from the first insulating layer , is configured as a pad to be electrically connected to another semiconductor package. <EOS>