Receiver module (EM) comprising - an optically operated voltage source (SP), wherein the voltage source (SP) comprises a first stack (SP1) with an upper side (OSP1) and a lower side (USP1) and is constructed on the basis of III-V semiconductor layers, which are arranged in stack shape, on an upper side (OS1) of a non-Si-substrate (NSSUB), and has a second electrical terminal contact (K2) at the upper side (OSP1) of the first stack (SP1) and a first electrical terminal contact (K1) at a lower side (US1) of the non-Si-substrate (NSSUB), wherein a voltage generated by means of irradiation of light (L) on the upper side (OSP1) of the first stack (SP1) lies between the two terminal contacts (K1, K2), - a second stack (ST2) with an FET transistor structure (FET1), which comprises III-V semiconductor layers, with a control terminal (G1) and a drain terminal (DR1) and a source terminal (S1), - the first stack and the second stack have a common non-Si-substrate (NSSUB), - the FET transistor structure (FET1) is constructed as a self-conducting field effect transistor and the control terminal (G1) and the source terminal are connected with one of the two terminal contacts (K1, K2) and the drain terminal (DR1) is connected with the other one of the two terminal contacts (K1, K2), wherein the field effect transistor short-circuits the two terminal contacts (K1, K2) insofar as the generated voltage drops below a threshold value, and the control terminal (G1) and the source terminal (S1) are short-circuited together or a Schottky diode (SKYD1) is connected between the control terminal (G1) and the source terminal (S1). - an optically operated voltage source (SP), wherein the voltage source (SP) comprises a first stack (SP1) with an upper side (OSP1) and a lower side (USP1) and is constructed on the basis of III-V semiconductor layers, which are arranged in stack shape, on an upper side (OS1) of a non-Si-substrate (NSSUB), and has a second electrical terminal contact (K2) at the upper side (OSP1) of the first stack (SP1) and a first electrical terminal contact (K1) at a lower side (US1) of the non-Si-substrate (NSSUB), wherein a voltage generated by means of irradiation of light (L) on the upper side (OSP1) of the first stack (SP1) lies between the two terminal contacts (K1, K2), - a second stack (ST2) with an FET transistor structure (FET1), which comprises III-V semiconductor layers, with a control terminal (G1) and a drain terminal (DR1) and a source terminal (S1), - the first stack and the second stack have a common non-Si-substrate (NSSUB), - the FET transistor structure (FET1) is constructed as a self-conducting field effect transistor and the control terminal (G1) and the source terminal are connected with one of the two terminal contacts (K1, K2) and the drain terminal (DR1) is connected with the other one of the two terminal contacts (K1, K2), wherein the field effect transistor short-circuits the two terminal contacts (K1, K2) insofar as the generated voltage drops below a threshold value, and the control terminal (G1) and the source terminal (S1) are short-circuited together or a Schottky diode (SKYD1) is connected between the control terminal (G1) and the source terminal (S1). <EOS>