A multilayer structure comprising: a single crystal semiconductor handle substrate comprising two major, generally parallel surfaces, one of which is a front surface of the single crystal semiconductor handle substrate and the other of which is a back surface of the single crystal semiconductor handle substrate, an imaginary central plane between the front surface and the back surface, a circumferential edge joining the front and back surfaces of the single crystal semiconductor handle substrate, and a bulk region between the front and back surfaces of the single crystal semiconductor handle substrate, wherein the single crystal semiconductor handle substrate has a minimum bulk region resistivity of at least about 500 ohm-cm; a semiconductor oxide layer in interfacial contact with the front surface of the single crystal semiconductor handle substrate; a charge trapping layer comprising a polycrystalline silicon layer, the charge trapping layer being in interfacial contact with the semiconductor oxide layer, wherein the charge trapping layer has a minimum resistivity of at least about 1000 ohm-cm; an insulating layer comprising silicon nitride or silicon oxynitride in interfacial contact with the charge trapping layer comprising the polycrystalline silicon layer; a dielectric layer in interfacial contact with the insulating layer, the dielectric layer comprising two or more layers, wherein each of the two or more layers comprises a material selected from the group consisting of silicon dioxide, silicon oxynitride, and silicon nitride; and a single crystal silicon device layer , wherein the single crystal silicon device layer is in interfacial contact with the dielectric layer. a single crystal semiconductor handle substrate comprising two major, generally parallel surfaces, one of which is a front surface of the single crystal semiconductor handle substrate and the other of which is a back surface of the single crystal semiconductor handle substrate, an imaginary central plane between the front surface and the back surface, a circumferential edge joining the front and back surfaces of the single crystal semiconductor handle substrate, and a bulk region between the front and back surfaces of the single crystal semiconductor handle substrate, wherein the single crystal semiconductor handle substrate has a minimum bulk region resistivity of at least about 500 ohm-cm; a semiconductor oxide layer in interfacial contact with the front surface of the single crystal semiconductor handle substrate; a charge trapping layer comprising a polycrystalline silicon layer, the charge trapping layer being in interfacial contact with the semiconductor oxide layer, wherein the charge trapping layer has a minimum resistivity of at least about 1000 ohm-cm; an insulating layer comprising silicon nitride or silicon oxynitride in interfacial contact with the charge trapping layer comprising the polycrystalline silicon layer; a dielectric layer in interfacial contact with the insulating layer, the dielectric layer comprising two or more layers, wherein each of the two or more layers comprises a material selected from the group consisting of silicon dioxide, silicon oxynitride, and silicon nitride; and a single crystal silicon device layer , wherein the single crystal silicon device layer is in interfacial contact with the dielectric layer. <EOS>