An apparatus comprising: an output driver comprising a pull-up circuit including one or more pull-up legs , and a pull-down circuit including one or more pull-down legs ; a control circuit coupled to the output driver , the control circuit comprising at least a first leg control circuit coupled to the pull-up circuit and a second leg control circuit coupled to the pull-down circuit , wherein the control circuit is configured to: receive an input signal having a first logical value and a second logical value; determine whether a logical transition has occurred in the input signal, between the first logical value and the second logic value; cause, via the first leg control circuit and the second leg control circuit , in response to determining the logical transition has occurred from the second logic value to the first logic value, the pull-up circuit and pull-down circuit respectively to enter a first state for a duration of a first portion of a bit period and to enter a second state for a duration of a second portion of the bit period proceeding the first portion; wherein when the pull-up circuit and the pull-down circuit are in the first state , the output driver drives an output signal to a first amplitude (V1) corresponding to the first logic value; wherein when the pull-up circuit and the pull-down circuit are in the second state , the output driver drives the output signal to a second amplitude (V3) less than the first amplitude (V1); characterized in that the control circuit is configured to adjust the second amplitude (V3) based at least in part on a control signal. an output driver comprising a pull-up circuit including one or more pull-up legs , and a pull-down circuit including one or more pull-down legs ; a control circuit coupled to the output driver , the control circuit comprising at least a first leg control circuit coupled to the pull-up circuit and a second leg control circuit coupled to the pull-down circuit , wherein the control circuit is configured to: receive an input signal having a first logical value and a second logical value; determine whether a logical transition has occurred in the input signal, between the first logical value and the second logic value; cause, via the first leg control circuit and the second leg control circuit , in response to determining the logical transition has occurred from the second logic value to the first logic value, the pull-up circuit and pull-down circuit respectively to enter a first state for a duration of a first portion of a bit period and to enter a second state for a duration of a second portion of the bit period proceeding the first portion; receive an input signal having a first logical value and a second logical value; determine whether a logical transition has occurred in the input signal, between the first logical value and the second logic value; cause, via the first leg control circuit and the second leg control circuit , in response to determining the logical transition has occurred from the second logic value to the first logic value, the pull-up circuit and pull-down circuit respectively to enter a first state for a duration of a first portion of a bit period and to enter a second state for a duration of a second portion of the bit period proceeding the first portion; wherein when the pull-up circuit and the pull-down circuit are in the first state , the output driver drives an output signal to a first amplitude (V1) corresponding to the first logic value; wherein when the pull-up circuit and the pull-down circuit are in the second state , the output driver drives the output signal to a second amplitude (V3) less than the first amplitude (V1); characterized in that the control circuit is configured to adjust the second amplitude (V3) based at least in part on a control signal. <EOS>