A processor, comprising: a mode indicator; a plurality of processing cores; and a neural network unit, NNU, comprising: a memory array; a plurality of neural processing units, NPUs; cache control logic; and selection logic, configured to selectively couple the plurality of NPUs and the cache control logic to the memory array; wherein when the mode indicator indicates a first mode, the selection logic enables the plurality of NPUs to read neural network weights from the memory array to perform computations using the weights; wherein when the mode indicator indicates a second mode, the selection logic enables the plurality of processing cores to access the memory array through the cache control logic as a cache memory; characterised in that : to transition from the second mode to the first mode, the cache control logic is configured to write-back-invalidate the memory array; two different hash algorithms are employed: one that excludes the memory array as a last-level cache, LLC, slice and one that includes the memory array as a LLC slice; and the two hash algorithms are designed to support a selective write-back-invalidate operation. a mode indicator; a plurality of processing cores; and a neural network unit, NNU, comprising: a memory array; a plurality of neural processing units, NPUs; cache control logic; and selection logic, configured to selectively couple the plurality of NPUs and the cache control logic to the memory array; wherein when the mode indicator indicates a first mode, the selection logic enables the plurality of NPUs to read neural network weights from the memory array to perform computations using the weights; wherein when the mode indicator indicates a second mode, the selection logic enables the plurality of processing cores to access the memory array through the cache control logic as a cache memory; characterised in that : to transition from the second mode to the first mode, the cache control logic is configured to write-back-invalidate the memory array; two different hash algorithms are employed: one that excludes the memory array as a last-level cache, LLC, slice and one that includes the memory array as a LLC slice; and the two hash algorithms are designed to support a selective write-back-invalidate operation. a memory array; a plurality of neural processing units, NPUs; cache control logic; and selection logic, configured to selectively couple the plurality of NPUs and the cache control logic to the memory array; wherein when the mode indicator indicates a first mode, the selection logic enables the plurality of NPUs to read neural network weights from the memory array to perform computations using the weights; wherein when the mode indicator indicates a second mode, the selection logic enables the plurality of processing cores to access the memory array through the cache control logic as a cache memory; characterised in that : to transition from the second mode to the first mode, the cache control logic is configured to write-back-invalidate the memory array; two different hash algorithms are employed: one that excludes the memory array as a last-level cache, LLC, slice and one that includes the memory array as a LLC slice; and the two hash algorithms are designed to support a selective write-back-invalidate operation. to transition from the second mode to the first mode, the cache control logic is configured to write-back-invalidate the memory array; two different hash algorithms are employed: one that excludes the memory array as a last-level cache, LLC, slice and one that includes the memory array as a LLC slice; and the two hash algorithms are designed to support a selective write-back-invalidate operation. <EOS>