A self-powering tamper detection system architecture, comprising: a power source ; a tamper detector , configured to mechanically actuate a tamper switch when a tamper event occurs; a tamper switch , electrically connected to the power source and mechanically connected to the tamper detector; a tamper unlock system , configured to provide a tamper unlock signal when an authorized maintenance condition exists; a tamper controller , configured: to produce a tamper response when the tamper event is identified; and to not produce the tamper response when the tamper unlock signal is provided; and program memory , configured to store program data; wherein the tamper response comprises a disruption of the program data; and further comprising: a test interface ; a test communications bus , configured to receive a tamper inhibit signal from the test interface; an embedded control processing system , configured to receive the tamper inhibit signal from the communications bus; non-volatile memory , configured to store a lock-unlock signal; and a data bus , configured to provide the lock-unlock signal to the tamper controller; and a memory-mapped location wherein: the tamper unlock system is configured to generate a tamper inhibit condition when the tamper inhibit signal is received from the test interface; the tamper controller is configured to ignore the tamper event when the tamper inhibit condition is present; the memory-mapped location is concealed within the non-volatile memory; and the tamper inhibit signal is written to the memory-mapped location by an authorized technician. a power source ; a tamper detector , configured to mechanically actuate a tamper switch when a tamper event occurs; a tamper switch , electrically connected to the power source and mechanically connected to the tamper detector; a tamper unlock system , configured to provide a tamper unlock signal when an authorized maintenance condition exists; a tamper controller , configured: to produce a tamper response when the tamper event is identified; and to not produce the tamper response when the tamper unlock signal is provided; and to produce a tamper response when the tamper event is identified; and to not produce the tamper response when the tamper unlock signal is provided; and program memory , configured to store program data; wherein the tamper response comprises a disruption of the program data; and a test interface ; a test communications bus , configured to receive a tamper inhibit signal from the test interface; an embedded control processing system , configured to receive the tamper inhibit signal from the communications bus; non-volatile memory , configured to store a lock-unlock signal; and a data bus , configured to provide the lock-unlock signal to the tamper controller; and a memory-mapped location wherein: the tamper unlock system is configured to generate a tamper inhibit condition when the tamper inhibit signal is received from the test interface; the tamper controller is configured to ignore the tamper event when the tamper inhibit condition is present; the tamper unlock system is configured to generate a tamper inhibit condition when the tamper inhibit signal is received from the test interface; the tamper controller is configured to ignore the tamper event when the tamper inhibit condition is present; the memory-mapped location is concealed within the non-volatile memory; and the tamper inhibit signal is written to the memory-mapped location by an authorized technician. <EOS>