An output circuit configured to generate a digital output (DOUTx) from one or more arrays of non-volatile memory cells, comprising: a plurality of current-to-voltage converters , each of the plurality of current-to-voltage converters configured to receive currents from a respective bitline pair (BLw+, BLw-), each bitline pair providing differential weight , W+, W-, outputs from a respective bitline coupled to one or more non-volatile memory cells of the one or more arrays storing W+ values and from a respective bitline coupled to one or more non-volatile memory cells of the one or more arrays storing W- values, and to convert said values into differential voltage outputs (ITVO+, ITVO-); a multiplexor configured to receive respective differential voltage outputs from the plurality of current-to-voltage converters and to time-multiplex respective differential voltage outputs; a plurality of sample-and-hold circuits configured to be shared across the plurality of current-to-voltage converters through the multiplexer, the number (k) of sample-and-hold circuits thus being smaller than the number (i) of current-to-voltage converters, and configured to generate respective held differentail voltage outputs (OSH+, OSH-); a channel multiplexor configured to receive the respective held differential voltage outputs (OSH+, OSH-) from the plurality of sample-and-hold circuits and to provide as an output a selected pair (ITVSH+, ITVSH-) of the held differential voltage outputs in response to a control signal received by the channel multiplexor; and an analog-to-digital converter configured to convert the selected pair of differential voltage outputs (ITVSH+, ITVSH-) received from the channel multiplexer into the digital output representing the output of one of the bit line pairs at a time. a plurality of current-to-voltage converters , each of the plurality of current-to-voltage converters configured to receive currents from a respective bitline pair (BLw+, BLw-), each bitline pair providing differential weight , W+, W-, outputs from a respective bitline coupled to one or more non-volatile memory cells of the one or more arrays storing W+ values and from a respective bitline coupled to one or more non-volatile memory cells of the one or more arrays storing W- values, and to convert said values into differential voltage outputs (ITVO+, ITVO-); a multiplexor configured to receive respective differential voltage outputs from the plurality of current-to-voltage converters and to time-multiplex respective differential voltage outputs; a plurality of sample-and-hold circuits configured to be shared across the plurality of current-to-voltage converters through the multiplexer, the number (k) of sample-and-hold circuits thus being smaller than the number (i) of current-to-voltage converters, and configured to generate respective held differentail voltage outputs (OSH+, OSH-); a channel multiplexor configured to receive the respective held differential voltage outputs (OSH+, OSH-) from the plurality of sample-and-hold circuits and to provide as an output a selected pair (ITVSH+, ITVSH-) of the held differential voltage outputs in response to a control signal received by the channel multiplexor; and an analog-to-digital converter configured to convert the selected pair of differential voltage outputs (ITVSH+, ITVSH-) received from the channel multiplexer into the digital output representing the output of one of the bit line pairs at a time. <EOS>