A memory system comprising: an array of memory cells arranged in rows and columns;a set of read word-lines coupled to a plurality of memory cells in the array of the memory cells, wherein each of the set of the read word-lines comprises a line not including any Josephson transmission line, JTL, elements; a set of read bit-lines coupled to the plurality of memory cells in the array of the memory cells ; a set of write word-lines coupled to the plurality of memory cells in the array of memory cells , wherein each of the set of the write word-lines comprises a line including at least one Josephson transmission line, JTL, element being clocked by a clock, and wherein each of the plurality of the memory cells comprises: at least one storage circuit and at least one read superconducting quantum interference device, SQUID , wherein a read bit-line corresponding to the set of read bit-lines is coupled to the at least one read SQUID, wherein the read bit-line is not coupled to the at least one read SQUID via a JTL, wherein the at least one storage circuit is configured to maintain a state of the memory cell , and wherein the at least one read SQUID is configured to read the state of the memory cell in response to an application of word-line current provided via a read word-line corresponding to the set of read word-lines, wherein the at least one storage circuit comprises a differential flip-flop, DFF, wherein the DFF is configured to provide a first current to the at least one read SQUID when the memory cell is in a logic one state and provide a second current to the at least one read SQUID when the memory cell is in a logic zero state, wherein an amount of the first current is higher than an amount of the second current, wherein signals on neither the read bit-line nor the read word-line are phase-aligned with respect to the at least one JTL element being clocked by the clock. an array of memory cells arranged in rows and columns;a set of read word-lines coupled to a plurality of memory cells in the array of the memory cells, wherein each of the set of the read word-lines comprises a line not including any Josephson transmission line, JTL, elements; a set of read bit-lines coupled to the plurality of memory cells in the array of the memory cells ; a set of write word-lines coupled to the plurality of memory cells in the array of memory cells , wherein each of the set of the write word-lines comprises a line including at least one Josephson transmission line, JTL, element being clocked by a clock, and wherein each of the plurality of the memory cells comprises: at least one storage circuit and at least one read superconducting quantum interference device, SQUID , wherein a read bit-line corresponding to the set of read bit-lines is coupled to the at least one read SQUID, wherein the read bit-line is not coupled to the at least one read SQUID via a JTL, wherein the at least one storage circuit is configured to maintain a state of the memory cell , and wherein the at least one read SQUID is configured to read the state of the memory cell in response to an application of word-line current provided via a read word-line corresponding to the set of read word-lines, wherein the at least one storage circuit comprises a differential flip-flop, DFF, wherein the DFF is configured to provide a first current to the at least one read SQUID when the memory cell is in a logic one state and provide a second current to the at least one read SQUID when the memory cell is in a logic zero state, wherein an amount of the first current is higher than an amount of the second current, wherein signals on neither the read bit-line nor the read word-line are phase-aligned with respect to the at least one JTL element being clocked by the clock. <EOS>