An apparatus for generating an identification key, the apparatus comprising: a first via connected to a first conductive layer included in a semiconductor chip, a first node being formed by electrically connecting the first via and the first conductive layer ; a second via connected to a second conductive layer included in the semiconductor chip, a second node being formed by electrically connecting the second via and the second conductive layer , and a value of a spacing between the first via and the second via in a patterning layout of the semiconductor chip being less than a minimum spacing value guaranteeing that the first node and the second node are not shorted; and a reader configured to determine whether the first node and the second node are electrically shorted and to generate an identification key, wherein the value of the spacing between the first via and the second via is equal to or greater than a first threshold (S1) and equal to or less than a second threshold (S2), characterised in that the first threshold (S1) is a lower limit value of a range of values of the spacing to allow a difference between a probability that the first node and the second node are shorted and a probability that the first node and the second node are not shorted to be within a predetermined error range, and wherein the second threshold (S2) is an upper limit value of the range of the values of the spacing to allow the difference between the probability that the first node and the second node are shorted and the probability that the first node and the second node are not shorted to be within the predetermined error range. a first via connected to a first conductive layer included in a semiconductor chip, a first node being formed by electrically connecting the first via and the first conductive layer ; a second via connected to a second conductive layer included in the semiconductor chip, a second node being formed by electrically connecting the second via and the second conductive layer , and a value of a spacing between the first via and the second via in a patterning layout of the semiconductor chip being less than a minimum spacing value guaranteeing that the first node and the second node are not shorted; and a reader configured to determine whether the first node and the second node are electrically shorted and to generate an identification key, wherein the value of the spacing between the first via and the second via is equal to or greater than a first threshold (S1) and equal to or less than a second threshold (S2), characterised in that the first threshold (S1) is a lower limit value of a range of values of the spacing to allow a difference between a probability that the first node and the second node are shorted and a probability that the first node and the second node are not shorted to be within a predetermined error range, and wherein the second threshold (S2) is an upper limit value of the range of the values of the spacing to allow the difference between the probability that the first node and the second node are shorted and the probability that the first node and the second node are not shorted to be within the predetermined error range. <EOS>