A memory device, comprising: a substrate of semiconductor material with a substrate upper surface having a memory cell region and a logic region ; a floating gate disposed vertically over and insulated from the memory cell region of the substrate upper surface, wherein the floating gate includes an upper surface that terminates in opposing front and back edges and in opposing first and second side edges; an oxide layer having a first portion that extends on the logic region of the substrate upper surface and has a first thickness, a second portion that extends on the memory cell region of the substrate upper surface and has the first thickness, and a third portion that extends on the front and back edges and on the first and second side edges; wherein the third portion of the oxide layer extending on the front edge has the first thickness, and wherein the third portion of the oxide layer extending on a tunnel region portion (TR) of the first side edge has a second thickness less than the first thickness; a control gate having a first portion disposed on the second portion of the oxide layer, and having a second portion disposed vertically over the front edge and vertically over the tunnel region portion of the first side edge; and a logic gate on the first portion of the oxide layer; wherein the first portion of the oxide layer insulates the substrate from the logic gate, the second portion of the oxide layer insulates the substrate from the control gate first portion, and the third portion of the oxide layer on the tunnel region portion of the first side edge insulates the control gate second portion from the tunnel region portion of the first side edge, the lesser thickness of the third portion of the oxide layer on the tunnel region portion of the first side edge enhancing the tunneling efficiency between the second portion of the control gate and the tunnel region portion of the first side edge. a substrate of semiconductor material with a substrate upper surface having a memory cell region and a logic region ; a floating gate disposed vertically over and insulated from the memory cell region of the substrate upper surface, wherein the floating gate includes an upper surface that terminates in opposing front and back edges and in opposing first and second side edges; an oxide layer having a first portion that extends on the logic region of the substrate upper surface and has a first thickness, a second portion that extends on the memory cell region of the substrate upper surface and has the first thickness, and a third portion that extends on the front and back edges and on the first and second side edges; wherein the third portion of the oxide layer extending on the front edge has the first thickness, and wherein the third portion of the oxide layer extending on a tunnel region portion (TR) of the first side edge has a second thickness less than the first thickness; a control gate having a first portion disposed on the second portion of the oxide layer, and having a second portion disposed vertically over the front edge and vertically over the tunnel region portion of the first side edge; and a logic gate on the first portion of the oxide layer; wherein the first portion of the oxide layer insulates the substrate from the logic gate, the second portion of the oxide layer insulates the substrate from the control gate first portion, and the third portion of the oxide layer on the tunnel region portion of the first side edge insulates the control gate second portion from the tunnel region portion of the first side edge, the lesser thickness of the third portion of the oxide layer on the tunnel region portion of the first side edge enhancing the tunneling efficiency between the second portion of the control gate and the tunnel region portion of the first side edge. <EOS>