A hash value generating device comprising: a θ processing means for performing θ processing included in round processing of Secure Hash Algorithm 3 (SHA-3 algorithm), wherein the round processing is performed on a set of bits structured as a rectangular parallelepiped; a p' processing means for performing p' processing corresponding to ρ processing included in the round processing; a n processing means for performing π processing included in the round processing; a χ processing means for performing χ processing included in the round processing; and an processing means for performing processing included in the round processing, wherein the p' processing is different from the ρ processing in shifting amounts for respective lanes which are determined in consideration of rearrangement of lanes in the π processing, wherein the θ processing means includes a θ1 processing means for calculating a sum of two columns which are adjacent to each column as an intermediate value and a θ2 processing means for adding the calculated intermediate value to each bit in a column determined in consideration of rearrangement of lanes in the π processing, wherein, in the round processing, the π processing means performs processing before the θ2 processing means and the p' processing means perform processing, wherein the set of bits for the round processing is input in units of lanes, the θ1 processing means calculates the intermediate value by updating an intermediate value in the process of calculation every time a lane of bits is input, while the input lane of bits is accumulated in a register for the π processing, and the π processing means performs the π processing on the set of bits input for the round processing accumulated in the register, and wherein the θ2 processing means adds the intermediate value to each bit in a column determined in consideration of rearrangement of lanes in the π processing. a θ processing means for performing θ processing included in round processing of Secure Hash Algorithm 3 (SHA-3 algorithm), wherein the round processing is performed on a set of bits structured as a rectangular parallelepiped; a p' processing means for performing p' processing corresponding to ρ processing included in the round processing; a n processing means for performing π processing included in the round processing; a χ processing means for performing χ processing included in the round processing; and an processing means for performing processing included in the round processing, wherein the p' processing is different from the ρ processing in shifting amounts for respective lanes which are determined in consideration of rearrangement of lanes in the π processing, wherein the θ processing means includes a θ1 processing means for calculating a sum of two columns which are adjacent to each column as an intermediate value and a θ2 processing means for adding the calculated intermediate value to each bit in a column determined in consideration of rearrangement of lanes in the π processing, wherein, in the round processing, the π processing means performs processing before the θ2 processing means and the p' processing means perform processing, wherein the set of bits for the round processing is input in units of lanes, the θ1 processing means calculates the intermediate value by updating an intermediate value in the process of calculation every time a lane of bits is input, while the input lane of bits is accumulated in a register for the π processing, and the π processing means performs the π processing on the set of bits input for the round processing accumulated in the register, and wherein the θ2 processing means adds the intermediate value to each bit in a column determined in consideration of rearrangement of lanes in the π processing. <EOS>