A multi-processor comprising: a plurality of cores being a first core and at least one remaining core ; and a debugging control unit configured to control debugging of a program executed in the first core in accordance with instructions from a debugger , wherein each of the plurality of cores includes a register for storing register information, and the register of the first core is connected to the debugging control unit so that the debugging control unit can refer to and update the register information stored in the register of the first core , characterized in that : the register of the at least one remaining core is not connected to the debugging control unit , the debugging control unit is configured, in response to a debugging target change instruction from the debugger for debugging a second program executed in a second core that is one of the at least one remaining core , to transfer the register information of the first core to the at least one remaining core for storage in the register of the at least one remaining core , and transfer the register information of the second core to the first core for storage in the register of the first core , and after the register information of the second core has been transferred to the register of the first core , the debugging control unit is configured to control debugging of the second program executed in the first core by using the register information stored in the register of the first core , in accordance with instructions from the debugger . a plurality of cores being a first core and at least one remaining core ; and a debugging control unit configured to control debugging of a program executed in the first core in accordance with instructions from a debugger , wherein each of the plurality of cores includes a register for storing register information, and the register of the first core is connected to the debugging control unit so that the debugging control unit can refer to and update the register information stored in the register of the first core , characterized in that : the register of the at least one remaining core is not connected to the debugging control unit , the debugging control unit is configured, in response to a debugging target change instruction from the debugger for debugging a second program executed in a second core that is one of the at least one remaining core , to transfer the register information of the first core to the at least one remaining core for storage in the register of the at least one remaining core , and transfer the register information of the second core to the first core for storage in the register of the first core , and after the register information of the second core has been transferred to the register of the first core , the debugging control unit is configured to control debugging of the second program executed in the first core by using the register information stored in the register of the first core , in accordance with instructions from the debugger . the register of the at least one remaining core is not connected to the debugging control unit , the debugging control unit is configured, in response to a debugging target change instruction from the debugger for debugging a second program executed in a second core that is one of the at least one remaining core , to transfer the register information of the first core to the at least one remaining core for storage in the register of the at least one remaining core , and transfer the register information of the second core to the first core for storage in the register of the first core , and after the register information of the second core has been transferred to the register of the first core , the debugging control unit is configured to control debugging of the second program executed in the first core by using the register information stored in the register of the first core , in accordance with instructions from the debugger . <EOS>