A semiconductor device, comprising: a silicon layer; a first metal layer above the silicon layer; a second layer above the first metal layer, the second layer consisting of second metal and a porous region ; and a hard mask , above the second metal of the second layer, defining the porous region within the second layer, the porous region being an anodized section of the second metal of the second layer and comprising an anodic oxide layer having pores, the pores being vertical and reaching through the full thickness of the second layer, wherein the hard mask is deformed, but has no cracks, on top of the second metal layer, despite a volume increase of the anodized section of the second metal layer during anodization, and wherein the hard mask is conductive and a conductive path exists between the hard mask and the first metal layer via the second metal layer wherein the device further comprises: a structure comprising a first conductive layer , a first insulator laye covering the first conductive layer, and a second conductive layer covering the first insulator layer, the structure formed inside the pores of the porous region; and a third metal layer , above the structure, wherein the first metal layer and the third metal layer are respectively in contact with the first and second conductive layers, and the first metal layer and the third metal layer are respectively the bottom and top electrodes of a capacitor provided by the structure. a silicon layer; a first metal layer above the silicon layer; a second layer above the first metal layer, the second layer consisting of second metal and a porous region ; and a hard mask , above the second metal of the second layer, defining the porous region within the second layer, the porous region being an anodized section of the second metal of the second layer and comprising an anodic oxide layer having pores, the pores being vertical and reaching through the full thickness of the second layer, wherein the hard mask is deformed, but has no cracks, on top of the second metal layer, despite a volume increase of the anodized section of the second metal layer during anodization, and wherein the hard mask is conductive and a conductive path exists between the hard mask and the first metal layer via the second metal layer wherein the device further comprises: a structure comprising a first conductive layer , a first insulator laye covering the first conductive layer, and a second conductive layer covering the first insulator layer, the structure formed inside the pores of the porous region; and a third metal layer , above the structure, wherein the first metal layer and the third metal layer are respectively in contact with the first and second conductive layers, and the first metal layer and the third metal layer are respectively the bottom and top electrodes of a capacitor provided by the structure. a structure comprising a first conductive layer , a first insulator laye covering the first conductive layer, and a second conductive layer covering the first insulator layer, the structure formed inside the pores of the porous region; and a third metal layer , above the structure, wherein the first metal layer and the third metal layer are respectively in contact with the first and second conductive layers, and the first metal layer and the third metal layer are respectively the bottom and top electrodes of a capacitor provided by the structure. <EOS>