A memory unit , comprising: a first memory cell comprising: a first floating gate transistor (FGT1) having a first terminal configured to receive a first bit line signal (BL), a second terminal, and a floating gate (FG1); and a first capacitance element having a first terminal, a second terminal, a control terminal coupled to the floating gate (FG1) of the first floating gate transistor (FGT1), and a body configured to receive a first control signal (CS1); characterized in that the memory unit further comprises: a first voltage passing device configured to output voltages according to operations of the memory unit , the first voltage passing device comprising a first passing gate transistor (PG1') having a first terminal configured to receive an inhibit signal (INH), a second terminal coupled to the first terminal of the first capacitance element , and a control terminal configured to receive a passing gate control signal (PL); wherein: the first terminal of the first capacitance element is coupled to the first voltage passing device ; and the first capacitance element and the first voltage passing device are disposed in a first N-well (NW1). a first memory cell comprising: a first floating gate transistor (FGT1) having a first terminal configured to receive a first bit line signal (BL), a second terminal, and a floating gate (FG1); and a first capacitance element having a first terminal, a second terminal, a control terminal coupled to the floating gate (FG1) of the first floating gate transistor (FGT1), and a body configured to receive a first control signal (CS1); a first floating gate transistor (FGT1) having a first terminal configured to receive a first bit line signal (BL), a second terminal, and a floating gate (FG1); and a first capacitance element having a first terminal, a second terminal, a control terminal coupled to the floating gate (FG1) of the first floating gate transistor (FGT1), and a body configured to receive a first control signal (CS1); characterized in that the memory unit further comprises: a first voltage passing device configured to output voltages according to operations of the memory unit , the first voltage passing device comprising a first passing gate transistor (PG1') having a first terminal configured to receive an inhibit signal (INH), a second terminal coupled to the first terminal of the first capacitance element , and a control terminal configured to receive a passing gate control signal (PL); wherein: the first terminal of the first capacitance element is coupled to the first voltage passing device ; and the first capacitance element and the first voltage passing device are disposed in a first N-well (NW1). a first voltage passing device configured to output voltages according to operations of the memory unit , the first voltage passing device comprising a first passing gate transistor (PG1') having a first terminal configured to receive an inhibit signal (INH), a second terminal coupled to the first terminal of the first capacitance element , and a control terminal configured to receive a passing gate control signal (PL); wherein: the first terminal of the first capacitance element is coupled to the first voltage passing device ; and the first capacitance element and the first voltage passing device are disposed in a first N-well (NW1). the first terminal of the first capacitance element is coupled to the first voltage passing device ; and the first capacitance element and the first voltage passing device are disposed in a first N-well (NW1). <EOS>