A processing system, comprising: a first data structure comprising a plurality of entries, each of the plurality of entries including a physical register value and one or more flag values; a second data structure including a plurality of pointers mapping logical register identifiers to entries of the first data structure, and one or more flag logical registers mapping a flag value to an entry in the first data structure; a third data structure including a plurality of move elimination sets comprising a set of bits representing a move elimination operation, a bit representing a logical data register, and indicating when set that the corresponding logical data register is to participate in the move elimination operation, the third data structure further comprising at least one bit associated with each move elimination set, the at least one bit representing one or more logical flag registers; a fourth data structure including an identifier of a logical data register sharing an entry of the first data structure with a flag logical register; and a move elimination logic configured to perform a move elimination operation by causing a source logical register pointer of the second data structure referencing an element of the first data structure to be copied to a destination logical register pointer of the second data structure, wherein the move elimination logic is further configured to track, using at least one of the third data structure and the fourth data structure, availability of entries of the first data structure for use by subsequent instructions, wherein an entry of the first data structure referenced by multiple second data structure pointers becomes available to use by subsequent instructions after the multiple second data structure pointers, including logical register and flag pointers, have been overwritten by one or more instructions. a first data structure comprising a plurality of entries, each of the plurality of entries including a physical register value and one or more flag values; a second data structure including a plurality of pointers mapping logical register identifiers to entries of the first data structure, and one or more flag logical registers mapping a flag value to an entry in the first data structure; a third data structure including a plurality of move elimination sets comprising a set of bits representing a move elimination operation, a bit representing a logical data register, and indicating when set that the corresponding logical data register is to participate in the move elimination operation, the third data structure further comprising at least one bit associated with each move elimination set, the at least one bit representing one or more logical flag registers; a fourth data structure including an identifier of a logical data register sharing an entry of the first data structure with a flag logical register; and a move elimination logic configured to perform a move elimination operation by causing a source logical register pointer of the second data structure referencing an element of the first data structure to be copied to a destination logical register pointer of the second data structure, wherein the move elimination logic is further configured to track, using at least one of the third data structure and the fourth data structure, availability of entries of the first data structure for use by subsequent instructions, wherein an entry of the first data structure referenced by multiple second data structure pointers becomes available to use by subsequent instructions after the multiple second data structure pointers, including logical register and flag pointers, have been overwritten by one or more instructions. <EOS>