A non-transitory computer readable medium configured to store instructions that, when executed, are configured to perform a method for generating a Reciprocal Quantum Logic, RQL, circuit design via a synthesis tool, the method comprising: providing data associated with behavior and constraints of the RQL circuit design and a component library to the synthesis tool; generating an RQL netlist circuit comprising a flip-flop device placeholder and a circuit system coupled to at least one of an input and an output of the flip-flop device placeholder via the synthesis tool based on the data and the component library; replacing the flip-flop device placeholder in the RQL netlist circuit with a plurality of sequential flip-flop devices via input scripts provided to the synthesis tool; performing a register rebalance operation on the RQL netlist circuit via the input scripts provided to the synthesis tool to separate the circuit system into a plurality of circuit subsystems that are each associated with a separate respective phase of a clock signal via the synthesis tool, each of the plurality of sequential flip-flop devices being associated with a separate respective one of the plurality of circuit subsystems and interconnecting a respective pair of the plurality of circuit subsystems, each of the plurality of sequential flip-flop devices being controlled by a separate clock signal corresponding respectively to each separate phase of the clock signal; removing the plurality of sequential flip-flop devices from the RQL netlist circuit via the input scripts provided to the synthesis tool to generate the RQL circuit design from the RQL netlist circuit; and controlling fabrication of a semiconductor circuit based on the generated RQL circuit design. providing data associated with behavior and constraints of the RQL circuit design and a component library to the synthesis tool; generating an RQL netlist circuit comprising a flip-flop device placeholder and a circuit system coupled to at least one of an input and an output of the flip-flop device placeholder via the synthesis tool based on the data and the component library; replacing the flip-flop device placeholder in the RQL netlist circuit with a plurality of sequential flip-flop devices via input scripts provided to the synthesis tool; performing a register rebalance operation on the RQL netlist circuit via the input scripts provided to the synthesis tool to separate the circuit system into a plurality of circuit subsystems that are each associated with a separate respective phase of a clock signal via the synthesis tool, each of the plurality of sequential flip-flop devices being associated with a separate respective one of the plurality of circuit subsystems and interconnecting a respective pair of the plurality of circuit subsystems, each of the plurality of sequential flip-flop devices being controlled by a separate clock signal corresponding respectively to each separate phase of the clock signal; removing the plurality of sequential flip-flop devices from the RQL netlist circuit via the input scripts provided to the synthesis tool to generate the RQL circuit design from the RQL netlist circuit; and controlling fabrication of a semiconductor circuit based on the generated RQL circuit design. <EOS>