A display device comprising: a display panel including a plurality of pixels; a controller configured to output image data (DAT) and a gated clock signal (GATED_CLK), the image data (DAT) including a plurality of pixel data for the plurality of pixels; and a data driver configured to receive the image data (DAT) and the gated clock signal (GATED_CLK) from the controller , and to sample the image data (DAT) in response to the gated clock signal (GATED_CLK), wherein the controller is further configured to: detect a repeated data pattern (RDP) where same pixel data is repeated in the image data (DAT); generate a clock enable signal (CLK_EN) having an off level during a power saving period (RDPP) in which the repeated data pattern is transferred and during a horizontal blank period; and perform a clock gating operation for an input clock signal (CLK) in response to the clock enable signal (CLK_EN) to produce the gated clock signal (GATED_CLK), wherein the gated clock signal (GATED_CLK) has a constant off level during the power saving period and during the horizontal blank period (HBP), and the data driver is configured to sample the image data (DAT) during periods when the gated clock signal (GATED_CLK) periodically toggles between an on-level and an off-level, and not to sample the image data (DAT) during periods when the gated clock signal (GATED_CLK) has the constant off level. a display panel including a plurality of pixels; a controller configured to output image data (DAT) and a gated clock signal (GATED_CLK), the image data (DAT) including a plurality of pixel data for the plurality of pixels; and a data driver configured to receive the image data (DAT) and the gated clock signal (GATED_CLK) from the controller , and to sample the image data (DAT) in response to the gated clock signal (GATED_CLK), wherein the controller is further configured to: detect a repeated data pattern (RDP) where same pixel data is repeated in the image data (DAT); generate a clock enable signal (CLK_EN) having an off level during a power saving period (RDPP) in which the repeated data pattern is transferred and during a horizontal blank period; and perform a clock gating operation for an input clock signal (CLK) in response to the clock enable signal (CLK_EN) to produce the gated clock signal (GATED_CLK), wherein detect a repeated data pattern (RDP) where same pixel data is repeated in the image data (DAT); generate a clock enable signal (CLK_EN) having an off level during a power saving period (RDPP) in which the repeated data pattern is transferred and during a horizontal blank period; and perform a clock gating operation for an input clock signal (CLK) in response to the clock enable signal (CLK_EN) to produce the gated clock signal (GATED_CLK), wherein the gated clock signal (GATED_CLK) has a constant off level during the power saving period and during the horizontal blank period (HBP), and the data driver is configured to sample the image data (DAT) during periods when the gated clock signal (GATED_CLK) periodically toggles between an on-level and an off-level, and not to sample the image data (DAT) during periods when the gated clock signal (GATED_CLK) has the constant off level. <EOS>