Method for display of an animation by a display chip (PA) of an electronic device (DE), said electronic device (DE) comprising a non-volatile memory (MN) and a random-access memory (MV), said display chip (PA) comprising a video output register (RV) and a display register (RA); the method being performed when the electronic device (DE) is started and being characterized in that it comprises a first static programming phase comprising: - a step (E1) for configuration of the video output register (RV), which is carried out so that the display is achieved either in progressive mode or interlaced mode; - a step (E2) for writing n images into the random-access memory (MV), where n is an integer equal to or greater than two, the n images forming, when they are displayed successively, the animation to be displayed; - a step (E3) for writing a plurality of nodes (Ni) into the random-access memory (MV) such that each node comprises the random-access memory (MV) address of at least a frame of an image from amongst the n images, as well as the random-access memory (MV) address of the following node, where the last node comprises the random access memory (MV) address of the first node, the step E3 being function of a display mode chosen during the step E1; - a step (E4) for configuration of the display register (RA), during which a node of the plurality of nodes (Ni) is loaded in the display register (RA) ; and in that it then comprises a second phase for reading of the n images by said display chip (PA), the reading phase comprising: - a display phase, by the display chip (PA), of the image or of the frame of the image whose address is contained in the node of the plurality of nodes (Ni) loaded in the display register (RA), said "loaded node"; - then, once this image or this frame of the image is displayed, a phase of loading into the display register (RA), by the display chip (PA), the node whose address in the random-access memory (MV) is included in the "loaded node"; these two phases being repeated so as to scan the plurality of nodes (Ni) and thus to display the animation obtained by the successive display of the n images. - a step (E1) for configuration of the video output register (RV), which is carried out so that the display is achieved either in progressive mode or interlaced mode; - a step (E2) for writing n images into the random-access memory (MV), where n is an integer equal to or greater than two, the n images forming, when they are displayed successively, the animation to be displayed; - a step (E3) for writing a plurality of nodes (Ni) into the random-access memory (MV) such that each node comprises the random-access memory (MV) address of at least a frame of an image from amongst the n images, as well as the random-access memory (MV) address of the following node, where the last node comprises the random access memory (MV) address of the first node, the step E3 being function of a display mode chosen during the step E1; - a step (E4) for configuration of the display register (RA), during which a node of the plurality of nodes (Ni) is loaded in the display register (RA) ; - a display phase, by the display chip (PA), of the image or of the frame of the image whose address is contained in the node of the plurality of nodes (Ni) loaded in the display register (RA), said "loaded node"; - then, once this image or this frame of the image is displayed, a phase of loading into the display register (RA), by the display chip (PA), the node whose address in the random-access memory (MV) is included in the "loaded node"; <EOS>