A display substrate , comprising a display region and a peripheral region around the display region , wherein the display region comprises an opening, and the peripheral region comprises a first peripheral region at least partially around the opening; the first peripheral region comprises a first dam region , a second dam region , and an interval region , the first dam region is at least partially around the opening, the interval region is at least partially around the first dam region , and the second dam region is at least partially around the interval region ; the display substrate comprises a base substrate , a first conductive semiconductor pattern , a first conductive pattern , and a second conductive pattern ; the first conductive semiconductor pattern is on the base substrate , the first conductive pattern is on a side of the first conductive semiconductor pattern away from the base substrate , and is spaced apart and insulated from the first conductive semiconductor pattern to form a capacitor, and the second conductive pattern is on a side of the first conductive pattern away from the first conductive semiconductor pattern , and is spaced apart and insulated from the first conductive pattern to form a capacitor; the first conductive pattern is configured to transmit an electrical signal for the display region ; the second conductive pattern is electrically connected to the first conductive semiconductor pattern through a plurality of via holes in the first peripheral region ; and characterized in that the first conductive semiconductor pattern , the first conductive pattern , and the second conductive pattern are at least in the first dam region and the second dam region , and the interval region , and an arrangement density of the plurality of via holes in the interval region in the first peripheral region is smaller than an arrangement density of the plurality of via holes in the first dam region and in the second dam region in the first peripheral region . wherein the display region comprises an opening, and the peripheral region comprises a first peripheral region at least partially around the opening; the first peripheral region comprises a first dam region , a second dam region , and an interval region , the first dam region is at least partially around the opening, the interval region is at least partially around the first dam region , and the second dam region is at least partially around the interval region ; the display substrate comprises a base substrate , a first conductive semiconductor pattern , a first conductive pattern , and a second conductive pattern ; the first conductive semiconductor pattern is on the base substrate , the first conductive pattern is on a side of the first conductive semiconductor pattern away from the base substrate , and is spaced apart and insulated from the first conductive semiconductor pattern to form a capacitor, and the second conductive pattern is on a side of the first conductive pattern away from the first conductive semiconductor pattern , and is spaced apart and insulated from the first conductive pattern to form a capacitor; the first conductive pattern is configured to transmit an electrical signal for the display region ; the second conductive pattern is electrically connected to the first conductive semiconductor pattern through a plurality of via holes in the first peripheral region ; and characterized in that the first conductive semiconductor pattern , the first conductive pattern , and the second conductive pattern are at least in the first dam region and the second dam region , and the interval region , and an arrangement density of the plurality of via holes in the interval region in the first peripheral region is smaller than an arrangement density of the plurality of via holes in the first dam region and in the second dam region in the first peripheral region . <EOS>