A switching element comprising: a semiconductor substrate including a first n-type semiconductor layer exposed to a surface of the semiconductor substrate , a p-type body layer constituted by an epitaxial layer exposed to the surface of the semiconductor substrate , and a second n-type semiconductor layer exposed to the surface of the semiconductor substrate and separated from the first n-type semiconductor layer by the body layer ; a gate insulating film configured to cover a range across a surface of the first n-type semiconductor layer , a surface of the body layer between the first n-type semiconductor layer and the second n-type semiconductor layer , and a surface of the second n-type semiconductor layer ; and a gate electrode configured to face the body layer between the first n-type semiconductor layer and the second n-type semiconductor layer through the gate insulating film , wherein an interface between the first n-type semiconductor layer and the body layer includes an inclined surface , the inclined surface is inclined such that a depth of the body layer increases as a distance from an end of the body layer increases in a horizontal direction, and the inclined surface is disposed below the gate electrode , wherein the interface includes a surface layer portion interface extending downward from the surface of the semiconductor substrate below the gate electrode and having an angle with respect to the surface of the semiconductor substrate being equal to or greater than 80° and equal to or less than 90°; the inclined surface is positioned on a lower side of the surface layer portion interface ; and an angle of the inclined surface with respect to the surface of the semiconductor substrate is less than 60°. a semiconductor substrate including a first n-type semiconductor layer exposed to a surface of the semiconductor substrate , a p-type body layer constituted by an epitaxial layer exposed to the surface of the semiconductor substrate , and a second n-type semiconductor layer exposed to the surface of the semiconductor substrate and separated from the first n-type semiconductor layer by the body layer ; a first n-type semiconductor layer exposed to a surface of the semiconductor substrate , a p-type body layer constituted by an epitaxial layer exposed to the surface of the semiconductor substrate , and a second n-type semiconductor layer exposed to the surface of the semiconductor substrate and separated from the first n-type semiconductor layer by the body layer ; a gate insulating film configured to cover a range across a surface of the first n-type semiconductor layer , a surface of the body layer between the first n-type semiconductor layer and the second n-type semiconductor layer , and a surface of the second n-type semiconductor layer ; and a gate electrode configured to face the body layer between the first n-type semiconductor layer and the second n-type semiconductor layer through the gate insulating film , wherein an interface between the first n-type semiconductor layer and the body layer includes an inclined surface , the inclined surface is inclined such that a depth of the body layer increases as a distance from an end of the body layer increases in a horizontal direction, and the inclined surface is disposed below the gate electrode , wherein the interface includes a surface layer portion interface extending downward from the surface of the semiconductor substrate below the gate electrode and having an angle with respect to the surface of the semiconductor substrate being equal to or greater than 80° and equal to or less than 90°; the inclined surface is positioned on a lower side of the surface layer portion interface ; and an angle of the inclined surface with respect to the surface of the semiconductor substrate is less than 60°. <EOS>