A display device comprising: a first conductive layer disposed on a substrate (SUB); a passivation layer disposed on the first conductive layer ; a second conductive layer disposed on the passivation layer ; a via layer disposed on the second conductive layer ; a first bank disposed on the via layer ; a third conductive layer disposed on the first bank , the third conductive layer including: a first electrode ; a second electrode ; and a connection pattern , the first electrode , the second electrode , and the connection pattern being spaced apart from each other; a light emitting element (ED), a first end and a second end of the light emitting element (ED) being disposed on the first electrode and the second electrode , respectively; and a transistor (TR) disposed between the substrate (SUB) and the second conductive layer , the transistor (TR) comprising: an active layer (ACT); a gate electrode (GE); a first source/drain electrode (SD1); and a second source/drain electrode (SD2), wherein the connection pattern electrically connects the first conductive layer and the second conductive layer through a first contact hole (CT13) penetrating the first bank , the via layer and the passivation layer ; wherein the first source/drain electrode (SD1) and the second source/drain electrode (SD2) are included in the first conductive layer ; and wherein the second conductive layer further comprises a first power line (VL1), and the connection pattern electrically connects the first power line (VL1) and the first source/drain electrode (SD1) of the transistor (TR) through the first contact hole (CT13). a first conductive layer disposed on a substrate (SUB); a passivation layer disposed on the first conductive layer ; a second conductive layer disposed on the passivation layer ; a via layer disposed on the second conductive layer ; a first bank disposed on the via layer ; a third conductive layer disposed on the first bank , the third conductive layer including: a first electrode ; a second electrode ; and a connection pattern , the first electrode , the second electrode , and the connection pattern being spaced apart from each other; a first electrode ; a second electrode ; and a connection pattern , the first electrode , the second electrode , and the connection pattern being spaced apart from each other; a light emitting element (ED), a first end and a second end of the light emitting element (ED) being disposed on the first electrode and the second electrode , respectively; and a transistor (TR) disposed between the substrate (SUB) and the second conductive layer , the transistor (TR) comprising: an active layer (ACT); a gate electrode (GE); a first source/drain electrode (SD1); and a second source/drain electrode (SD2), an active layer (ACT); a gate electrode (GE); a first source/drain electrode (SD1); and a second source/drain electrode (SD2), wherein the connection pattern electrically connects the first conductive layer and the second conductive layer through a first contact hole (CT13) penetrating the first bank , the via layer and the passivation layer ; wherein the first source/drain electrode (SD1) and the second source/drain electrode (SD2) are included in the first conductive layer ; and wherein the second conductive layer further comprises a first power line (VL1), and the connection pattern electrically connects the first power line (VL1) and the first source/drain electrode (SD1) of the transistor (TR) through the first contact hole (CT13). <EOS>