A level shifter circuit comprising: a first pair of transistors having first and second transistors (P11, P12) connected to a first supply voltage node (VDDH); a pair of diode connected transistors having third and fourth transistors (P13, P14), which are connected to the first and second transistors (P11, P12) , respectively, via first and second output nodes (outb-h, out-h), respectively; a second pair of transistors (N11, N12) connected to the third and fourth transistors, respectively, via first and second intermediate nodes , respectively, and a ground node (GNDH); wherein gates of the second pair of transistors (N11, N12) are connected to a pair of input nodes , respectively; wherein gates of the third and fourth transistors (P13, P14), are connected to the first and second intermediate nodes , respectively; wherein gates of the first and second transistors (P11, P12) are connected to the second and first intermediate nodes , respectively; third pair of transistors having fifth and sixth transistors (N13, N14); wherein drains of the fifth and sixth transistors (N13, N14) are connected to the first and second output nodes (outb-h, out-h), respectively; wherein sources of the fifth and sixth transistors (N13, N14); are connected to the first and second intermediate nodes , respectively; wherein gates of the fifth and sixth transistors (N13, N14) are connected to the second and first output nodes (outh, outb-h), respectively, characterized in that the gates of the fifth and sixth transistors (N13,N14) are arranged to be controlled by signals at the second and first output nodes (out-h, outb-h) respectively. a first pair of transistors having first and second transistors (P11, P12) connected to a first supply voltage node (VDDH); a pair of diode connected transistors having third and fourth transistors (P13, P14), which are connected to the first and second transistors (P11, P12) , respectively, via first and second output nodes (outb-h, out-h), respectively; a second pair of transistors (N11, N12) connected to the third and fourth transistors, respectively, via first and second intermediate nodes , respectively, and a ground node (GNDH); wherein gates of the second pair of transistors (N11, N12) are connected to a pair of input nodes , respectively; wherein gates of the third and fourth transistors (P13, P14), are connected to the first and second intermediate nodes , respectively; wherein gates of the first and second transistors (P11, P12) are connected to the second and first intermediate nodes , respectively; third pair of transistors having fifth and sixth transistors (N13, N14); wherein drains of the fifth and sixth transistors (N13, N14) are connected to the first and second output nodes (outb-h, out-h), respectively; wherein sources of the fifth and sixth transistors (N13, N14); are connected to the first and second intermediate nodes , respectively; wherein gates of the fifth and sixth transistors (N13, N14) are connected to the second and first output nodes (outh, outb-h), respectively, characterized in that the gates of the fifth and sixth transistors (N13,N14) are arranged to be controlled by signals at the second and first output nodes (out-h, outb-h) respectively. <EOS>