An apparatus, comprising: a memory access instruction pipeline ; a translation lookaside buffer, TLB, coupled to the memory access instruction pipeline; and a TLB miss queue coupled to the TLB and to the memory access instruction pipeline; characterized in that the TLB miss queue is configured to selectively store both: a first memory access instruction that has been removed from the memory access instruction pipeline as a result of the first memory access instruction missing in the TLB; and information associated with the first memory access instruction; and wherein the TLB miss queue is further configured to reintroduce the first memory access instruction to the memory access instruction pipeline associated with a return of an address translation related to the first memory access instruction; wherein either the information associated with the first memory access instruction does not comprise hazard detection information, and wherein the TLB miss queue is further configured to reintroduce the first memory access instruction to the memory access instruction pipeline such that the memory access instruction pipeline will perform hazard detection on the first memory access instruction as if it were a new instruction; or the information associated with the first memory access instruction comprises hazard detection information, and wherein the TLB miss queue is further configured to reintroduce the first memory access instruction to the memory access instruction pipeline such that the memory access instruction pipeline does not perform hazard detection on the first memory access instruction as if it were a new instruction. a memory access instruction pipeline ; a translation lookaside buffer, TLB, coupled to the memory access instruction pipeline; and a TLB miss queue coupled to the TLB and to the memory access instruction pipeline; characterized in that the TLB miss queue is configured to selectively store both: a first memory access instruction that has been removed from the memory access instruction pipeline as a result of the first memory access instruction missing in the TLB; and information associated with the first memory access instruction; and a first memory access instruction that has been removed from the memory access instruction pipeline as a result of the first memory access instruction missing in the TLB; and information associated with the first memory access instruction; and wherein the TLB miss queue is further configured to reintroduce the first memory access instruction to the memory access instruction pipeline associated with a return of an address translation related to the first memory access instruction; wherein either the information associated with the first memory access instruction does not comprise hazard detection information, and wherein the TLB miss queue is further configured to reintroduce the first memory access instruction to the memory access instruction pipeline such that the memory access instruction pipeline will perform hazard detection on the first memory access instruction as if it were a new instruction; or the information associated with the first memory access instruction comprises hazard detection information, and wherein the TLB miss queue is further configured to reintroduce the first memory access instruction to the memory access instruction pipeline such that the memory access instruction pipeline does not perform hazard detection on the first memory access instruction as if it were a new instruction. <EOS>