An information processing apparatus comprising: a main CPU as an execution means configured to execute predetermined software ; a sub-CPU as a verification means configured to perform verification of the predetermined software , wherein the predetermined software is a program and data used when the execution means boots up; power supply means configured to output a voltage to the execution means ; retaining means configured to retain information corresponding to a voltage to be applied to the execution means , wherein the execution means sets the voltage to be output by the power supply means on the basis of the information retained by the retaining means ; and clock signal output means configured to output a clock signal having a first frequency to the verification means at least during verification processing of the predetermined software performed by the verification means , and output a clock signal having a second frequency lower than the first frequency to the execution means at least during execution of the predetermined software by the execution means and during setting processing of the voltage to be output by the power supply means performed by the execution means , wherein in a case where the predetermined software is successfully verified by the verification means , the clock signal output means is configured to output the clock signal having the second frequency to the execution means which is configured to execute the predetermined software and then the setting processing of the voltage, and the clock signal output means is configured to output, after the voltage to be output by the power supply means is set by the execution means , a clock signal having a third frequency higher than the second frequency to the execution means. a main CPU as an execution means configured to execute predetermined software ; a sub-CPU as a verification means configured to perform verification of the predetermined software , wherein the predetermined software is a program and data used when the execution means boots up; power supply means configured to output a voltage to the execution means ; retaining means configured to retain information corresponding to a voltage to be applied to the execution means , wherein the execution means sets the voltage to be output by the power supply means on the basis of the information retained by the retaining means ; and clock signal output means configured to output a clock signal having a first frequency to the verification means at least during verification processing of the predetermined software performed by the verification means , and output a clock signal having a second frequency lower than the first frequency to the execution means at least during execution of the predetermined software by the execution means and during setting processing of the voltage to be output by the power supply means performed by the execution means , wherein in a case where the predetermined software is successfully verified by the verification means , the clock signal output means is configured to output the clock signal having the second frequency to the execution means which is configured to execute the predetermined software and then the setting processing of the voltage, and the clock signal output means is configured to output, after the voltage to be output by the power supply means is set by the execution means , a clock signal having a third frequency higher than the second frequency to the execution means. <EOS>