A method for making on a plate a plurality of chips each comprising an integrated circuit comprising an individualisation area , each chip being intended to comprise at least: • a first and a second levels of the electrical tracks , • a level of interconnections located between the first and second levels of the electrical tracks and including vias intended to electrically connect electrical tracks of the first level with electrical tracks of the second level , the method comprising at least the following steps performed simultaneously for a plurality of chips of the plate : • provide at least the first level of the electrical tracks and a dielectric layer covering the first level , • make over the dielectric layer a hard mask having openings located in line with the electrical tracks and making the dielectric layer accessible, • make, in an area of the chip intended to comprise the individualisation area , patterns shaped so that: i. first openings of the hard mask are not masked by the patterns so as to leave the dielectric layer accessible in line with the first openings and that ii. second openings of the hard mask are masked by the patterns , the arrangement of the patterns being different for each of the chips of the plurality of chips of the plate , • make via openings in the dielectric layer in line only with the first openings so as to expose the electrical tracks of the first level , • fill the via openings with an electrically-conductive material so as to form vias in line only with the first openings of the hard mask , • make the second level of the electrical tracks over the vias . • a first and a second levels of the electrical tracks , • a level of interconnections located between the first and second levels of the electrical tracks and including vias intended to electrically connect electrical tracks of the first level with electrical tracks of the second level , • provide at least the first level of the electrical tracks and a dielectric layer covering the first level , • make over the dielectric layer a hard mask having openings located in line with the electrical tracks and making the dielectric layer accessible, • make, in an area of the chip intended to comprise the individualisation area , patterns shaped so that: i. first openings of the hard mask are not masked by the patterns so as to leave the dielectric layer accessible in line with the first openings and that ii. second openings of the hard mask are masked by the patterns , the arrangement of the patterns being different for each of the chips of the plurality of chips of the plate , i. first openings of the hard mask are not masked by the patterns so as to leave the dielectric layer accessible in line with the first openings and that ii. second openings of the hard mask are masked by the patterns , the arrangement of the patterns being different for each of the chips of the plurality of chips of the plate , • make via openings in the dielectric layer in line only with the first openings so as to expose the electrical tracks of the first level , • fill the via openings with an electrically-conductive material so as to form vias in line only with the first openings of the hard mask , • make the second level of the electrical tracks over the vias . <EOS>