A method for error finding in the programming logic of a computer system (CS) in which a global system time is defined, comprising at least one first programmable gate array (G1), for example a first FPGA, and a second programmable gate array (G2), for example a second FPGA, comprising the following method steps: programming a first logic circuit (L1) on the first programmable gate array (G1), programming a second logic circuit (L2) on the second programmable gate array (G2); programming on the first programmable gate array (G1) a first monitor circuit (D1) communicatively isolated from the first logic circuit (L1) and comprising a first signal input (S1), a first trigger signal input (TI1), and a first trigger signal output (TO1) and being set up for reading and saving a signal value of a signal present at a first signal input (S1) as a result of a trigger signal present at the first trigger signal input (TI1); programming on the second programmable gate array (G2) a second monitor circuit (D2) communicatively isolated from the second logic circuit (L2) and comprising a second signal input (S2) and a second trigger signal input (TE2) and being set up for reading and saving a signal value of a signal present at the second signal input (S2) as a result of a trigger signal present at the second trigger signal input (TE2); applying the first trigger signal output (TO1) to a signal output pin (PO) of the first programmable gate array (G1) when programming the first monitor circuit (D1), the signal output pin (PO) being connected to the second trigger signal input by means of a bus (B) or a signal line of the computer system (CS); programming a first signal line (SI1) applying a signal from the first logic circuit (L1) to the first signal input (S1) in the first programmable gate array (G1) without changing the first logic circuit (L1); programming a second signal line (SI2) applying a signal from the second logic circuit (L2) to the second signal input (S2) in the second programmable gate array (G2) without changing the second logic circuit (L2); and generating a first trigger signal present at the first trigger signal input (TI1) causing the first monitor circuit (D1) to read and save a first signal value from the first signal input (S1); characterized in that both the first monitor circuit (D1) and the second monitor circuit (D2) are set up for reading the global system time; the first monitor circuit (D1) is set up for determining a point in time of the global system time in the future as a result of the first trigger signal present at the first trigger signal input (TI1), the time spacing thereof relative to the present at least corresponding to the signal propagation time of the second trigger signal to the second trigger signal input (TE2); the first monitor circuit (D1) is set up for generating a second trigger signal present at the second trigger signal input (TI2) as a result of the trigger signal present at the first trigger signal input (TI1), from which the point in time can be read, and for outputting said trigger signal by means of the first trigger signal output (TO1); the second monitor circuit (D2) is set up for reading the point in time from the second trigger signal; the first monitor circuit (D1) is set up for reading and saving the first signal value of the first signal present at the first signal input (S1) at said point in time; and the second monitor circuit (D2) is set up for reading and saving the second signal value of the second signal present at the second signal input (S2) at said point in time. <EOS>