A semiconductor package , comprising: a package substrate ; a first semiconductor chip on the package substrate ; and a second semiconductor chip on the first semiconductor chip , wherein the first semiconductor chip comprises: a chip substrate including a first surface and a second surface opposite to the first surface; a plurality of first chip pads between the package substrate and the chip substrate , and electrically connecting the first semiconductor chip to the package substrate ; a plurality of second chip pads disposed on the second surface and between the second semiconductor chip and the second surface; a plurality of redistribution lines on the second surface, the redistribution lines electrically connecting to the second semiconductor chip ; and a plurality of first bonding wires electrically connecting the redistribution lines to the package substrate , characterized in that the second semiconductor chip further comprises a through via penetrating the second semiconductor chip , and in that the semiconductor package further comprises: a third semiconductor chip on the second semiconductor chip , the third semiconductor chip electrically connected to the first semiconductor chip through the through via ; and a solder ball electrically connected to the through via between the second semiconductor chip and the third semiconductor chip . a package substrate ; a first semiconductor chip on the package substrate ; and a second semiconductor chip on the first semiconductor chip , wherein the first semiconductor chip comprises: a chip substrate including a first surface and a second surface opposite to the first surface; a plurality of first chip pads between the package substrate and the chip substrate , and electrically connecting the first semiconductor chip to the package substrate ; a plurality of second chip pads disposed on the second surface and between the second semiconductor chip and the second surface; a plurality of redistribution lines on the second surface, the redistribution lines electrically connecting to the second semiconductor chip ; and a plurality of first bonding wires electrically connecting the redistribution lines to the package substrate , characterized in that the second semiconductor chip further comprises a through via penetrating the second semiconductor chip , and a chip substrate including a first surface and a second surface opposite to the first surface; a plurality of first chip pads between the package substrate and the chip substrate , and electrically connecting the first semiconductor chip to the package substrate ; a plurality of second chip pads disposed on the second surface and between the second semiconductor chip and the second surface; a plurality of redistribution lines on the second surface, the redistribution lines electrically connecting to the second semiconductor chip ; and a plurality of first bonding wires electrically connecting the redistribution lines to the package substrate , characterized in that the second semiconductor chip further comprises a through via penetrating the second semiconductor chip , and in that the semiconductor package further comprises: a third semiconductor chip on the second semiconductor chip , the third semiconductor chip electrically connected to the first semiconductor chip through the through via ; and a solder ball electrically connected to the through via between the second semiconductor chip and the third semiconductor chip . a third semiconductor chip on the second semiconductor chip , the third semiconductor chip electrically connected to the first semiconductor chip through the through via ; and a solder ball electrically connected to the through via between the second semiconductor chip and the third semiconductor chip . <EOS>