A circuit , comprising: - an analog-to-digital conversion circuit path configured to provide converted digital data (20 1 , 20 2 , ..., 20 N ) from analog input signals (I), - a further analog-to-digital conversion circuit path configured to provide further converted digital data from the analog input signals (I), - comparison circuitry configured to perform a comparison of the digital data (20 1 , 20 2 , ..., 20 N ) from the analog-to-digital conversion circuit path with the further digital data from the further analog-to-digital conversion circuit path and declare a fault condition of the circuit as a result of the comparison revealing a mismatch between the digital data (20 1 , 20 2 , ..., 20 N ) from the analog-to-digital conversion circuit path and the further digital data from the further analog-to-digital conversion circuit path , characterized in that : the circuit comprises a sampling circuit stage configured to receive the analog input signals (I) and provide a sampled version thereof, the sampling circuit stage being common to the analog-to-digital conversion circuit path and the further analog-to-digital conversion circuit path , wherein: - the analog-to-digital conversion circuit path comprises a quantization circuit stage coupled to the common sampling circuit stage and configured to provide said digital data (20 1 , 20 2 , ..., 20 N ) from said sampled version of the analog input signals (I); and - the further analog-to-digital conversion circuit path comprises a further quantization circuit stage coupled to the common sampling circuit stage and configured to provide said further digital data from said sampled version of the analog input signals (I). - an analog-to-digital conversion circuit path configured to provide converted digital data (20 1 , 20 2 , ..., 20 N ) from analog input signals (I), - a further analog-to-digital conversion circuit path configured to provide further converted digital data from the analog input signals (I), - comparison circuitry configured to perform a comparison of the digital data (20 1 , 20 2 , ..., 20 N ) from the analog-to-digital conversion circuit path with the further digital data from the further analog-to-digital conversion circuit path and declare a fault condition of the circuit as a result of the comparison revealing a mismatch between the digital data (20 1 , 20 2 , ..., 20 N ) from the analog-to-digital conversion circuit path and the further digital data from the further analog-to-digital conversion circuit path , the circuit comprises a sampling circuit stage configured to receive the analog input signals (I) and provide a sampled version thereof, the sampling circuit stage being common to the analog-to-digital conversion circuit path and the further analog-to-digital conversion circuit path , wherein: - the analog-to-digital conversion circuit path comprises a quantization circuit stage coupled to the common sampling circuit stage and configured to provide said digital data (20 1 , 20 2 , ..., 20 N ) from said sampled version of the analog input signals (I); and - the further analog-to-digital conversion circuit path comprises a further quantization circuit stage coupled to the common sampling circuit stage and configured to provide said further digital data from said sampled version of the analog input signals (I). - the analog-to-digital conversion circuit path comprises a quantization circuit stage coupled to the common sampling circuit stage and configured to provide said digital data (20 1 , 20 2 , ..., 20 N ) from said sampled version of the analog input signals (I); and - the further analog-to-digital conversion circuit path comprises a further quantization circuit stage coupled to the common sampling circuit stage and configured to provide said further digital data from said sampled version of the analog input signals (I). <EOS>