A NAND gate circuit, comprising a first input transistor (T1) and a second input transistor (T2), a gate electrode of the first input transistor being connected to a first input signal (IN1), a gate electrode of the second input transistor being connected to a second input signal (IN2), a first electrode of the first input transistor being connected to an NAND gate output end (OUT), a second electrode of the second input transistor being connected to a low level supply voltage (VSS), and a second electrode of the first input transistor being connected to a first electrode of the second input transistor, wherein the NAND gate circuit further comprises a first pull-up module , a second pull-up module , a first input control transistors (T3) and a second input control transistor (T4), a gate electrode of the first input control transistor (T3) is connected to the first input signal (IN1), a first electrode thereof is connected to a control end of the first pull-up module , and a second electrode thereof is connected to the low level supply voltage, a gate electrode of the second input control transistor (T4) is connected to the second input signal (IN2), a first electrode thereof is connected to a control end of the second pull-up module , and a second electrode thereof is connected to the low level supply voltage, the first electrode of the first input transistor (T1) is connected to a high level supply voltage (VDD) via the first pull-up module , the first electrode of the first input transistor (T1) is connected to the high level supply voltage via the second pull-up module , the first input control transistor (T3) is configured to enable a potential of the control end of the first pull-up module connected to the first electrode of the first input transistor (T1) to be the low level voltage when the first input signal (IN1) connected to the gate electrode of the first input control transistor is at a high level voltage, the second input control transistor (T4) is configured to enable a potential of the control end of the second pull-up module connected to the first electrode of the second input control transistor (T4) to be the low level voltage when the second input signal (IN2) connected to the gate electrode of the second input control transistor is at a high level voltage, and the two pull-up modules are configured to cut off the connection between the high level supply voltage (VDD) and the NAND gate output end (OUT) when the first input signal and the second input signal are both at the high level voltage, and enable the connection between the high level supply voltage (VDD) and the NAND gate output end (OUT) when at least one of the first input signal (IN1) and the second input signal (IN2) is not at the high level voltage, each of the two pull-up modules comprises a first pull-up transistor (T5, T7), a second pull-up transistor (T6, T8) and a storage capacitor (C1, C2), wherein a gate electrode of the second pull-up transistor (T6, T8) is the control end of the corresponding pull-up module , a gate electrode of the first pull-up transistor (T5, T7) is connected to the high level supply voltage (VDD), a first electrode of the first pull-up transistor is connected to the gate electrode of the first pull-up transistor (T5, T7), and a second electrode of the first pull-up transistor (T5, T7) is connected to the gate electrode of the second pull-up transistor (T6, T8), a first electrode of the second pull-up transistor (T6, T8) is connected to the high level supply voltage (VDD), and a second electrode thereof is connected to the NAND gate output end (OUT), and the storage capacitor (C1, C2) is connected between the gate electrode and the second electrode of the second pull-up transistor (T6, T8). <EOS>