An integrated circuit , comprising: a clock generator configured to generate a first clock signal (A); a delay circuit coupled to the clock generator and configured to generate a second clock signal (B) as a delayed version of the first clock signal; a plurality of series-connected delay elements coupled to receive the second clock signal from the delay circuit and having a plurality of outputs (C,D,E,F,G), wherein each output of the plurality of outputs from an initial output (C) to a last output (G) is configured to provide the second clock signal delayed by an increasing number of series-connected delay elements of the plurality of series-connected delay elements; a plurality of flip-flops , from an initial flip-flop to a last flip-flop , wherein a first input of each flip flop is coupled to receive the first clock signal (A) and a second input of each flip flop from the initial flip-flop to the last flip-flop is coupled to receive a corresponding output of the plurality of series-connected delay elements from the initial output to the last output, respectively; and a plurality of sticky flops , each corresponding to a flip-flop of the plurality of flip-flops, wherein a clock input of each sticky flop is coupled to receive the corresponding output (C,D) of the plurality of series-connected delay elements that is provided to the second input of the corresponding flip-flop, and a data input of each sticky flop is generated from a data output of the sticky flop and a data output of the corresponding flip-flop, wherein each sticky flop is configured to capture and maintain an indication of whether a transition of the data output of the corresponding flip-flop has occurred. a clock generator configured to generate a first clock signal (A); a delay circuit coupled to the clock generator and configured to generate a second clock signal (B) as a delayed version of the first clock signal; a plurality of series-connected delay elements coupled to receive the second clock signal from the delay circuit and having a plurality of outputs (C,D,E,F,G), wherein each output of the plurality of outputs from an initial output (C) to a last output (G) is configured to provide the second clock signal delayed by an increasing number of series-connected delay elements of the plurality of series-connected delay elements; a plurality of flip-flops , from an initial flip-flop to a last flip-flop , wherein a first input of each flip flop is coupled to receive the first clock signal (A) and a second input of each flip flop from the initial flip-flop to the last flip-flop is coupled to receive a corresponding output of the plurality of series-connected delay elements from the initial output to the last output, respectively; and a plurality of sticky flops , each corresponding to a flip-flop of the plurality of flip-flops, wherein a clock input of each sticky flop is coupled to receive the corresponding output (C,D) of the plurality of series-connected delay elements that is provided to the second input of the corresponding flip-flop, and a data input of each sticky flop is generated from a data output of the sticky flop and a data output of the corresponding flip-flop, wherein each sticky flop is configured to capture and maintain an indication of whether a transition of the data output of the corresponding flip-flop has occurred. <EOS>