A device comprising: an array of non-volatile split-gate flash memory cells organized in rows along word lines (WL), erase gate lines (EG) and source lines (SL), and in columns along bit lines (BL), wherein each non-volatile split-gate flash memory cell is a four-terminal cell comprising a bit line terminal, a word line terminal, an erase gate terminal, and a source line terminal; a high voltage row decoder configured to receive select signals, select one of a plurality of different voltages to generate read, erase, and programming voltages, and apply the selected voltage to one or more source lines (SL)(SL) coupled to source line terminals of a first plurality of non-volatile four-terminal split-gate flash memory cells in the array during a program operation; and a second plurality of non-volatile four-terminal split-gate flash memory cells in the array being in an erased state and operating as dummy memory cells not used to store data and arranged, during a read operation, to pull down , through one or more dummy bit lines (1526, BL_PWDN) and one or more switches, one or more source lines to ground, and arranged , during the program operation, to connect, through the one or more dummy bit lines and the one or more switches, the one or more source lines to an inhibit voltage (VDD), wherein the one or more source lines are connected to the source terminals of the first plurality of non-volatile four-terminal split-gate flash memory cells in the respective one or more rows in the array and to the source terminals of the second plurality of non-volatile four-terminal split-gate flash memory cells operating as dummy cells in the respective one or more rows in the array. an array of non-volatile split-gate flash memory cells organized in rows along word lines (WL), erase gate lines (EG) and source lines (SL), and in columns along bit lines (BL), wherein each non-volatile split-gate flash memory cell is a four-terminal cell comprising a bit line terminal, a word line terminal, an erase gate terminal, and a source line terminal; a high voltage row decoder configured to receive select signals, select one of a plurality of different voltages to generate read, erase, and programming voltages, and apply the selected voltage to one or more source lines (SL)(SL) coupled to source line terminals of a first plurality of non-volatile four-terminal split-gate flash memory cells in the array during a program operation; and a second plurality of non-volatile four-terminal split-gate flash memory cells in the array being in an erased state and operating as dummy memory cells not used to store data and arranged, during a read operation, to pull down , through one or more dummy bit lines (1526, BL_PWDN) and one or more switches, one or more source lines to ground, and arranged , during the program operation, to connect, through the one or more dummy bit lines and the one or more switches, the one or more source lines to an inhibit voltage (VDD), wherein the one or more source lines are connected to the source terminals of the first plurality of non-volatile four-terminal split-gate flash memory cells in the respective one or more rows in the array and to the source terminals of the second plurality of non-volatile four-terminal split-gate flash memory cells operating as dummy cells in the respective one or more rows in the array. <EOS>