A low-profile microelectronic package comprising: a microelectronic die having a first surface and an opposing second surface ; a package substrate built up around at least a portion of the microelectronic die, the package substrate comprising: an electrically insulating layer that forms a first side of the package substrate, the electrically insulating layer having a plurality of pads formed therein, wherein the first surface of the microelectronic die is located at the first side of the package substrate; an electrically conductive layer electrically connected to the microelectronic die; and a protective layer over the electrically conductive layer, the protective layer forming a second side of the package substrate; and an array of electrically conductive interconnect structures located at the first side of the package substrate, wherein each individual interconnect structure in the array of electrically conductive interconnect structures has a first end and an opposing second end , and wherein the first end is connected to one of the plurality of pads; characterized in that the pads define a plane within the electrically insulating layer; and the array of electrically conductive interconnect structures is on a first side of the plane and the protective layer is on a second side of the plane; and the first surface and the second surface of the microelectronic die are on the first side of the plane. a microelectronic die having a first surface and an opposing second surface ; a package substrate built up around at least a portion of the microelectronic die, the package substrate comprising: an electrically insulating layer that forms a first side of the package substrate, the electrically insulating layer having a plurality of pads formed therein, wherein the first surface of the microelectronic die is located at the first side of the package substrate; an electrically conductive layer electrically connected to the microelectronic die; and a protective layer over the electrically conductive layer, the protective layer forming a second side of the package substrate; and an array of electrically conductive interconnect structures located at the first side of the package substrate, wherein each individual interconnect structure in the array of electrically conductive interconnect structures has a first end and an opposing second end , and wherein the first end is connected to one of the plurality of pads; characterized in that the pads define a plane within the electrically insulating layer; and the array of electrically conductive interconnect structures is on a first side of the plane and the protective layer is on a second side of the plane; and the first surface and the second surface of the microelectronic die are on the first side of the plane. an electrically insulating layer that forms a first side of the package substrate, the electrically insulating layer having a plurality of pads formed therein, wherein the first surface of the microelectronic die is located at the first side of the package substrate; an electrically conductive layer electrically connected to the microelectronic die; and a protective layer over the electrically conductive layer, the protective layer forming a second side of the package substrate; and an array of electrically conductive interconnect structures located at the first side of the package substrate, wherein each individual interconnect structure in the array of electrically conductive interconnect structures has a first end and an opposing second end , and wherein the first end is connected to one of the plurality of pads; characterized in that the pads define a plane within the electrically insulating layer; and the array of electrically conductive interconnect structures is on a first side of the plane and the protective layer is on a second side of the plane; and the first surface and the second surface of the microelectronic die are on the first side of the plane. <EOS>