A system-on-chip comprising: processing circuitry to perform data processing operations; a first plurality of devices; an interconnect to couple the processing circuitry to the first plurality of devices, the first plurality of devices being a first level of devices within a hierarchical structure of devices forming a device network, where devices within the device network are arranged to communicate using a device communication protocol, the device communication protocol providing an enumeration mechanism to enable software executed on the processing circuitry to discover and configure the devices within the network of devices; and an address decoder to decode an address specified by a request issued by the processing circuitry in order to determine a recipient for the request; within a system address space a pool of addresses being reserved for allocation to the first plurality of devices, and the address decoder comprising a device address decoder to maintain, for each device in the first plurality of devices, an indication of which addresses within the pool are allocated to that device; wherein the address decoder is responsive to detecting that the address specified by the request is within the pool of addresses, to employ the device address decoder to determine which device amongst the first plurality of devices the request is directed to and to cause the request to be routed to the determined device within said first plurality; characterized in that : wherein the device address decoder is arranged to be exposed to the software as a device of the device network so as to enable the software executing on the processing circuitry to discover and configure the device address decoder using the enumeration mechanism, thereby enabling the allocation of the pool of addresses amongst the first plurality of devices to be dynamically reconfigured under software control. processing circuitry to perform data processing operations; a first plurality of devices; an interconnect to couple the processing circuitry to the first plurality of devices, the first plurality of devices being a first level of devices within a hierarchical structure of devices forming a device network, where devices within the device network are arranged to communicate using a device communication protocol, the device communication protocol providing an enumeration mechanism to enable software executed on the processing circuitry to discover and configure the devices within the network of devices; and an address decoder to decode an address specified by a request issued by the processing circuitry in order to determine a recipient for the request; within a system address space a pool of addresses being reserved for allocation to the first plurality of devices, and the address decoder comprising a device address decoder to maintain, for each device in the first plurality of devices, an indication of which addresses within the pool are allocated to that device; wherein the address decoder is responsive to detecting that the address specified by the request is within the pool of addresses, to employ the device address decoder to determine which device amongst the first plurality of devices the request is directed to and to cause the request to be routed to the determined device within said first plurality; characterized in that : wherein the device address decoder is arranged to be exposed to the software as a device of the device network so as to enable the software executing on the processing circuitry to discover and configure the device address decoder using the enumeration mechanism, thereby enabling the allocation of the pool of addresses amongst the first plurality of devices to be dynamically reconfigured under software control. <EOS>