A system for an agnostic runtime architecture for emulating/converting a guest image having both application code and system-specific code of a first system architecture implemented on a processor having a second architecture, the system comprising: a system emulator used in case that the first and the second system architecture are different, the system emulator comprising a system emulation/virtualization converter to manage emulation and virtualization of system code of the guest image; and an application code converter to manage emulation of application code of the guest image; and a system converter used in case that the first architecture has similar system characteristics as the second architecture, but the non-system part of the first and the second architecture are different; wherein the system converter comprises a bare metal component and an application code converter for converting application code of the guest image, wherein the application code converter of the system converter or the system emulators are operable to implement: a run ahead run time guest conversion process; and a prefetching process where guest code is pre-fetched from corresponding targets of guest branches in an instruction sequence, and is converted to native conversion blocks, wherein address mappings between guest code and native conversion blocks are cached in a conversion look aside buffer, CLB, and wherein a CLB counter is set at conversion time, and is decremented every time the instruction sequence is executed; and wherein, if the CLB counter reaches a threshold, the instruction sequence is optimized by renaming registers in a guest branch, and moving instructions that use these registers ahead of the guest branch, the system further comprising hardware configured to keep track of whether a guest branch biased decision is true or not, and, if the guest branch is miss-predicted, jump to the original instructions of the guest branch in memory, execute the original instructions , and flush the miss-predicted instruction sequence. a system converter used in case that the first architecture has similar system characteristics as the second architecture, but the non-system part of the first and the second architecture are different; wherein the system converter comprises a bare metal component and an application code converter for converting application code of the guest image, wherein the application code converter of the system converter or the system emulators are operable to implement: a run ahead run time guest conversion process; and a prefetching process where guest code is pre-fetched from corresponding targets of guest branches in an instruction sequence, and is converted to native conversion blocks, wherein address mappings between guest code and native conversion blocks are cached in a conversion look aside buffer, CLB, and wherein a CLB counter is set at conversion time, and is decremented every time the instruction sequence is executed; and a run ahead run time guest conversion process; and a prefetching process where guest code is pre-fetched from corresponding targets of guest branches in an instruction sequence, and is converted to native conversion blocks, wherein address mappings between guest code and native conversion blocks are cached in a conversion look aside buffer, CLB, and wherein a CLB counter is set at conversion time, and is decremented every time the instruction sequence is executed; and wherein, if the CLB counter reaches a threshold, the instruction sequence is optimized by renaming registers in a guest branch, and moving instructions that use these registers ahead of the guest branch, the system further comprising hardware configured to keep track of whether a guest branch biased decision is true or not, and, if the guest branch is miss-predicted, jump to the original instructions of the guest branch in memory, execute the original instructions , and flush the miss-predicted instruction sequence. <EOS>