A computing system , comprising: at least one processing unit; at least one memory controller in operative communication with the at least one processing unit, with or without cache; and a main memory in operative communication with the at least one processing unit through the at least one memory controller; wherein a memory hierarchy of the computing system includes at least one cache , the at least one memory controller, and the main memory, wherein the memory hierarchy is divided into a plurality of memory pools; wherein the main memory comprises a set of memory modules split in ranks each having a rank address defined by a set of rank address bits, and each rank having a set of memory devices , each of the memory devices comprising one or more banks each having a bank address defined by a set of bank address bits; wherein a plurality of threads execute on the at least one processing unit and are assigned to the memory pools based on memory partitioning techniques comprising: bank partitioning , which uses the bank address bits to define a size and pattern of one or more of the memory pools; rank partitioning , which uses the rank address bits to access the one or more ranks; and memory controller partitioning , which uses memory controller interleaving to isolate memory requests to the at least one memory controller; wherein the system is configured to provide levels of memory pool access isolation comprising: a single memory pool allocated to the at least one memory controller; and a single memory pool isolated to the one or more banks in one or more of the ranks. at least one processing unit; at least one memory controller in operative communication with the at least one processing unit, with or without cache; and a main memory in operative communication with the at least one processing unit through the at least one memory controller; wherein a memory hierarchy of the computing system includes at least one cache , the at least one memory controller, and the main memory, wherein the memory hierarchy is divided into a plurality of memory pools; wherein the main memory comprises a set of memory modules split in ranks each having a rank address defined by a set of rank address bits, and each rank having a set of memory devices , each of the memory devices comprising one or more banks each having a bank address defined by a set of bank address bits; wherein a plurality of threads execute on the at least one processing unit and are assigned to the memory pools based on memory partitioning techniques comprising: bank partitioning , which uses the bank address bits to define a size and pattern of one or more of the memory pools; rank partitioning , which uses the rank address bits to access the one or more ranks; and memory controller partitioning , which uses memory controller interleaving to isolate memory requests to the at least one memory controller; bank partitioning , which uses the bank address bits to define a size and pattern of one or more of the memory pools; rank partitioning , which uses the rank address bits to access the one or more ranks; and memory controller partitioning , which uses memory controller interleaving to isolate memory requests to the at least one memory controller; wherein the system is configured to provide levels of memory pool access isolation comprising: a single memory pool allocated to the at least one memory controller; and a single memory pool isolated to the one or more banks in one or more of the ranks. a single memory pool allocated to the at least one memory controller; and a single memory pool isolated to the one or more banks in one or more of the ranks. <EOS>