An apparatus, comprising: a set of NAND strings , the set of NAND strings extends in a lower tier and an upper tier of a stack , the lower tier separated from the upper tier by an interface (IF), each NAND string comprising a channel , a set of memory cells (703-714, 713-734, 743-754, 753-774), a source end , a drain end and a drain-side select gate transistor ; and a control circuit configured to, in response to a read command, discharge the channels during a discharge period before reading selected memory cells in the set of NAND strings , wherein the discharge period is longer when the selected memory cells are at a top of the lower tier than when the selected memory cells are at a bottom of the lower tier , wherein in the discharge period, a voltage applied to the selected memory cells is ramped up from an initial voltage to a peak voltage while the drain ends and source ends of the NAND strings are grounded; wherein when the selected memory cells are in the lower tier : the control circuit is configured to increase the discharge period as a function of an increasing height of the selected memory cells when the selected memory cells are in a group of memory cells adjacent to a bottom of the lower tier ; and the discharge period is non-increasing with the increasing height of the selected memory cells when the selected memory cells are in a group of memory cells adjacent to a top of the lower tier . a set of NAND strings , the set of NAND strings extends in a lower tier and an upper tier of a stack , the lower tier separated from the upper tier by an interface (IF), each NAND string comprising a channel , a set of memory cells (703-714, 713-734, 743-754, 753-774), a source end , a drain end and a drain-side select gate transistor ; and a control circuit configured to, in response to a read command, discharge the channels during a discharge period before reading selected memory cells in the set of NAND strings , wherein the discharge period is longer when the selected memory cells are at a top of the lower tier than when the selected memory cells are at a bottom of the lower tier , wherein in the discharge period, a voltage applied to the selected memory cells is ramped up from an initial voltage to a peak voltage while the drain ends and source ends of the NAND strings are grounded; wherein when the selected memory cells are in the lower tier : the control circuit is configured to increase the discharge period as a function of an increasing height of the selected memory cells when the selected memory cells are in a group of memory cells adjacent to a bottom of the lower tier ; and the discharge period is non-increasing with the increasing height of the selected memory cells when the selected memory cells are in a group of memory cells adjacent to a top of the lower tier . the control circuit is configured to increase the discharge period as a function of an increasing height of the selected memory cells when the selected memory cells are in a group of memory cells adjacent to a bottom of the lower tier ; and the discharge period is non-increasing with the increasing height of the selected memory cells when the selected memory cells are in a group of memory cells adjacent to a top of the lower tier . <EOS>