A storage controller , comprising: a host interface circuit configured to receive first to eighth requests respectively corresponding to first to eighth logical addresses from a host device ; a memory interface circuit configured to communicate with one or more first nonvolatile memories (NVM0) through a first channel (CH0), to communicate with one or more second nonvolatile memories (NVM1) through a second channel (CH1), to communicate with one or more third nonvolatile memories (NVM2) through a third channel (CH2) and to communicate with one or more fourth nonvolatile memories (NVM3) through a fourth channel (CH3); a first flash translation layer (FTL0) configured to manage the one or more first nonvolatile memories (NVM0) through the first channel (CH0); a second flash translation layer (FTL1) configured to manage the one or more second nonvolatile memories (NVM1) through the second channel (CH1), a third flash translation layer (FTL2) configured to manage the one or more third nonvolatile memories (NVM2) through the third channel (CH2); a fourth flash translation layer (FTL3) configured to manage the one or more fourth nonvolatile memories (NVM3) through the fourth channel (CH3); and a scramble circuit configured to allocate the first to fourth requests corresponding to a first section of the first to eighth logical addresses to the first to fourth flash translation layers (FTL3) in a first allocation sequence, and to allocate the fifth to eighth requests corresponding to a second section of the first to eighth logical addresses to the first to fourth flash translation layers (FTL3) in a second allocation sequence different from the first sequence. a host interface circuit configured to receive first to eighth requests respectively corresponding to first to eighth logical addresses from a host device ; a memory interface circuit configured to communicate with one or more first nonvolatile memories (NVM0) through a first channel (CH0), to communicate with one or more second nonvolatile memories (NVM1) through a second channel (CH1), to communicate with one or more third nonvolatile memories (NVM2) through a third channel (CH2) and to communicate with one or more fourth nonvolatile memories (NVM3) through a fourth channel (CH3); a first flash translation layer (FTL0) configured to manage the one or more first nonvolatile memories (NVM0) through the first channel (CH0); a second flash translation layer (FTL1) configured to manage the one or more second nonvolatile memories (NVM1) through the second channel (CH1), a third flash translation layer (FTL2) configured to manage the one or more third nonvolatile memories (NVM2) through the third channel (CH2); a fourth flash translation layer (FTL3) configured to manage the one or more fourth nonvolatile memories (NVM3) through the fourth channel (CH3); and a scramble circuit configured to allocate the first to fourth requests corresponding to a first section of the first to eighth logical addresses to the first to fourth flash translation layers (FTL3) in a first allocation sequence, and to allocate the fifth to eighth requests corresponding to a second section of the first to eighth logical addresses to the first to fourth flash translation layers (FTL3) in a second allocation sequence different from the first sequence. <EOS>