A method comprising: generating a destination domain current buffer signal (DCB) in a destination clock domain (DCD), the destination domain current buffer signal (DCB) having a value indicating which one of a first data buffer (B0) and a second data buffer (B1) in a source clock domain (SCD) is a current buffer to be utilized during a current data transfer cycle; synchronizing the destination domain current buffer signal (DCB) in the source clock domain (SCD) to generate a synchronized destination domain current buffer signal; generating a source domain current buffer signal (SCB) based on the synchronized destination domain current buffer signal, the generated source domain current buffer signal having a value indicating the current buffer; generating a source data transfer request signal (SDTR) in the source clock domain (SCD) based on the source domain current buffer signal (SCB), the source data transfer request signal (SDTR) being associated with the current buffer indicated by the source domain current buffer signal (SCB); synchronizing the source data transfer request signal (SDTR) in the destination clock domain (DCD) to thereby generate a destination domain data transfer request signal (SDTR-BO-SYNC, SDTR-B1-SYNC); and delaying the transfer of data between a memory in the destination clock domain (DCD) and the current buffer to a subsequent data transfer cycle when the current buffer associated with the destination domain data transfer request signal (SDTR-BO-SYNC, SDTR-B1-SYNC) does not correspond to the current buffer indicated by the destination domain current buffer signal (DCB). generating a destination domain current buffer signal (DCB) in a destination clock domain (DCD), the destination domain current buffer signal (DCB) having a value indicating which one of a first data buffer (B0) and a second data buffer (B1) in a source clock domain (SCD) is a current buffer to be utilized during a current data transfer cycle; synchronizing the destination domain current buffer signal (DCB) in the source clock domain (SCD) to generate a synchronized destination domain current buffer signal; generating a source domain current buffer signal (SCB) based on the synchronized destination domain current buffer signal, the generated source domain current buffer signal having a value indicating the current buffer; generating a source data transfer request signal (SDTR) in the source clock domain (SCD) based on the source domain current buffer signal (SCB), the source data transfer request signal (SDTR) being associated with the current buffer indicated by the source domain current buffer signal (SCB); synchronizing the source data transfer request signal (SDTR) in the destination clock domain (DCD) to thereby generate a destination domain data transfer request signal (SDTR-BO-SYNC, SDTR-B1-SYNC); and delaying the transfer of data between a memory in the destination clock domain (DCD) and the current buffer to a subsequent data transfer cycle when the current buffer associated with the destination domain data transfer request signal (SDTR-BO-SYNC, SDTR-B1-SYNC) does not correspond to the current buffer indicated by the destination domain current buffer signal (DCB). <EOS>