An integrated circuit, comprising: a first data line group , comprising a plurality of local data lines (Ldat) arranged in an array; a second data line group , comprising a plurality of complementary local data lines (Ldat#) arranged in an array, wherein the plurality of complementary local data lines (Ldat#) and the plurality of local data lines (Ldat) respectively transmit signals having opposite phases; and a plurality of read circuits , configured to read, in response to a read control signal, signals of the local data lines (Ldat) or the complementary local data lines (Ldat#) during a read operation, wherein each of the plurality of read circuits is electrically connected to a local data line (Ldat) at a boundary of the first data line group or connected to a complementary local data line (Ldat#) at a boundary of the second data line group ; characterized in that the first data line group comprises a first local data line (Ldat1), a second local data line (Ldat2), a third local data line (Ldat3), and a fourth local data line (Ldat4) arranged in sequence, the second data line group comprises a second complementary local data line (Ldat#2), a first complementary local data line (Ldat#1), a fourth complementary local data line (Ldat#4), and a third complementary local data line (Ldat#3) arranged in sequence, and the first local data line (Ldat1), the fourth local data line (Ldat4), the second complementary local data line (Ldat#2), and the third complementary local data line (Ldat#3) are electrically connected to the read circuits , respectively; and wherein the first local data line (Ldat1) and the first complementary local data line (Ldat#1), the second local data line (Ldat2) and the second complementary local data line (Ldat#2), the third local data line (Ldat3) and the third complementary local data line (Ldat#3), and the fourth local data line (Ldat4) and the fourth complementary local data line (Ldat#4) each transmit signals having opposite phases. a first data line group , comprising a plurality of local data lines (Ldat) arranged in an array; a second data line group , comprising a plurality of complementary local data lines (Ldat#) arranged in an array, wherein the plurality of complementary local data lines (Ldat#) and the plurality of local data lines (Ldat) respectively transmit signals having opposite phases; and a plurality of read circuits , configured to read, in response to a read control signal, signals of the local data lines (Ldat) or the complementary local data lines (Ldat#) during a read operation, wherein each of the plurality of read circuits is electrically connected to a local data line (Ldat) at a boundary of the first data line group or connected to a complementary local data line (Ldat#) at a boundary of the second data line group ; characterized in that the first data line group comprises a first local data line (Ldat1), a second local data line (Ldat2), a third local data line (Ldat3), and a fourth local data line (Ldat4) arranged in sequence, the second data line group comprises a second complementary local data line (Ldat#2), a first complementary local data line (Ldat#1), a fourth complementary local data line (Ldat#4), and a third complementary local data line (Ldat#3) arranged in sequence, and the first local data line (Ldat1), the fourth local data line (Ldat4), the second complementary local data line (Ldat#2), and the third complementary local data line (Ldat#3) are electrically connected to the read circuits , respectively; and wherein the first local data line (Ldat1) and the first complementary local data line (Ldat#1), the second local data line (Ldat2) and the second complementary local data line (Ldat#2), the third local data line (Ldat3) and the third complementary local data line (Ldat#3), and the fourth local data line (Ldat4) and the fourth complementary local data line (Ldat#4) each transmit signals having opposite phases. <EOS>