An active inductor load comprising: a pair of active inductors , each active inductor comprising a transistor (M1, M2, M5, M6) and a resistor (R 1 , R 2 ) electrically coupled to the transistor; and a pair of cross-coupled capacitive elements (M3/M4, M7/M8) electrically coupled to the pair of active inductors , wherein: the pair of active inductors comprise first and second transistors (M1, M2, M5, M6); the pair of cross-coupled capacitive elements (M3/M4, M7/M8) comprise first and second capacitive elements (M3, M4, M7, M8); the first capacitive element (M3, M4, M7, M8) is electrically coupled between a gate of the first transistor (M1, M2, M5, M6) and a drain of the second transistor (M1, M2, M5, M6); the second capacitive element (M3, M4, M7, M8) is electrically coupled between a gate of the second transistor (M1, M2, M5, M6) and a drain of the first transistor (M1, M2, M5, M6); the first capacitive element (M3, M4, M7, M8) comprises a third transistor (M3, M4, M7, M8); a drain of the third transistor (M3, M4, M7, M8) is shorted to a source of the third transistor; a gate of the third transistor (M3, M4, M7, M8) is electrically coupled to the gate of the first transistor (M1, M2, M5, M6); and at least one of the source or the drain of the third transistor (M3, M4, M7, M8) is electrically coupled to the drain of the second transistor (M1, M2, M5, M6). a pair of active inductors , each active inductor comprising a transistor (M1, M2, M5, M6) and a resistor (R 1 , R 2 ) electrically coupled to the transistor; and a pair of cross-coupled capacitive elements (M3/M4, M7/M8) electrically coupled to the pair of active inductors , wherein: the pair of active inductors comprise first and second transistors (M1, M2, M5, M6); the pair of cross-coupled capacitive elements (M3/M4, M7/M8) comprise first and second capacitive elements (M3, M4, M7, M8); the first capacitive element (M3, M4, M7, M8) is electrically coupled between a gate of the first transistor (M1, M2, M5, M6) and a drain of the second transistor (M1, M2, M5, M6); the second capacitive element (M3, M4, M7, M8) is electrically coupled between a gate of the second transistor (M1, M2, M5, M6) and a drain of the first transistor (M1, M2, M5, M6); the first capacitive element (M3, M4, M7, M8) comprises a third transistor (M3, M4, M7, M8); a drain of the third transistor (M3, M4, M7, M8) is shorted to a source of the third transistor; a gate of the third transistor (M3, M4, M7, M8) is electrically coupled to the gate of the first transistor (M1, M2, M5, M6); and at least one of the source or the drain of the third transistor (M3, M4, M7, M8) is electrically coupled to the drain of the second transistor (M1, M2, M5, M6). the pair of active inductors comprise first and second transistors (M1, M2, M5, M6); the pair of cross-coupled capacitive elements (M3/M4, M7/M8) comprise first and second capacitive elements (M3, M4, M7, M8); the first capacitive element (M3, M4, M7, M8) is electrically coupled between a gate of the first transistor (M1, M2, M5, M6) and a drain of the second transistor (M1, M2, M5, M6); the second capacitive element (M3, M4, M7, M8) is electrically coupled between a gate of the second transistor (M1, M2, M5, M6) and a drain of the first transistor (M1, M2, M5, M6); the first capacitive element (M3, M4, M7, M8) comprises a third transistor (M3, M4, M7, M8); a drain of the third transistor (M3, M4, M7, M8) is shorted to a source of the third transistor; a gate of the third transistor (M3, M4, M7, M8) is electrically coupled to the gate of the first transistor (M1, M2, M5, M6); and at least one of the source or the drain of the third transistor (M3, M4, M7, M8) is electrically coupled to the drain of the second transistor (M1, M2, M5, M6). <EOS>