A system for process and temperature compensated passive signal detection, the system comprising: a voltage level detector ; a first transistor with a drain electrically connected to a first input of the voltage level detector , the first transistor having a threshold voltage (Vth) of a first voltage value, wherein the threshold voltage (Vth) corresponds to a minimum gate-to-source voltage of the first voltage value to create a conducting path between source and drain terminals of a transistor; and a second transistor with a drain electrically connected to a second input of the voltage level detector , the second transistor having a threshold voltage (Vth) of the first voltage value; wherein a third transistor and a fourth transistor configured to generate an offset voltage (VC_OS, 225, 235) configured to be process and temperature dependent and to counter a threshold voltage (Vth) variation; wherein the offset voltage (VC_OS, 235) is applied across a gate of the first transistor and a source of the second transistor ; and the offset voltage (VC_OS, 225) is applied across a gate of the second transistor and a source of the first transistor , so that a difference between the threshold voltage (Vth) of the first voltage value and the offset voltage (VC_OS, 235) is constant; wherein the offset voltage (VC_OS) is produced using the third transistor and the fourth transistor each having a threshold voltage (Vth) of the first voltage value, a supply voltage (VDD), and a plurality of resistors (R1, R2, R3); the plurality of resistors (R1, R2, R3) comprises a first pair of resistors each with resistance of a first resistance value, a second pair of resistors each with resistance of a second resistance value, and a third pair of resistors each with resistance of a third resistance value; and the offset voltage (VC_OS) is produced across a drain of the third transistor and a source of the fourth transistor . a voltage level detector ; a first transistor with a drain electrically connected to a first input of the voltage level detector , the first transistor having a threshold voltage (Vth) of a first voltage value, wherein the threshold voltage (Vth) corresponds to a minimum gate-to-source voltage of the first voltage value to create a conducting path between source and drain terminals of a transistor; and a second transistor with a drain electrically connected to a second input of the voltage level detector , the second transistor having a threshold voltage (Vth) of the first voltage value; wherein a third transistor and a fourth transistor configured to generate an offset voltage (VC_OS, 225, 235) configured to be process and temperature dependent and to counter a threshold voltage (Vth) variation; wherein the offset voltage (VC_OS, 235) is applied across a gate of the first transistor and a source of the second transistor ; and the offset voltage (VC_OS, 225) is applied across a gate of the second transistor and a source of the first transistor , so that a difference between the threshold voltage (Vth) of the first voltage value and the offset voltage (VC_OS, 235) is constant; wherein the offset voltage (VC_OS) is produced using the third transistor and the fourth transistor each having a threshold voltage (Vth) of the first voltage value, a supply voltage (VDD), and a plurality of resistors (R1, R2, R3); the plurality of resistors (R1, R2, R3) comprises a first pair of resistors each with resistance of a first resistance value, a second pair of resistors each with resistance of a second resistance value, and a third pair of resistors each with resistance of a third resistance value; and the offset voltage (VC_OS) is produced across a drain of the third transistor and a source of the fourth transistor . <EOS>