A display apparatus comprising: a first thin-film transistor (T3) comprising a gate electrode and a first semiconductor comprising a first source area and a first drain area; a storage capacitor (Cst) comprising a first storage capacitor plate and a second storage capacitor plate, the second capacitor plate overlapping the first storage capacitor plate and being above the first storage capacitor plate, wherein the first storage capacitor plate is electrically coupled to the first drain area; a driving thin-film transistor (T1) comprising a driving gate electrode formed as an integral part of the first storage capacitor plate and a driving semiconductor comprising a driving drain area coupled to the first source area and a driving source area; a data signal line over the second storage capacitor plate; a first shield layer (SD1) in a layer between the data signal line and the first semiconductor, wherein the gate electrode of the first thin-film transistor (T3) comprises a first gate electrode and a second gate electrode, wherein the second storage capacitor plate comprises the first shield layer (SD1), and the first shield layer (SD1) overlaps a part of the first semiconductor between the first gate electrode and the second gate electrode of the first thin-film transistor; and a second shield layer (SD3) in a layer between the data signal line and the driving gate electrode, wherein the second shield layer (SD3) is integrally formed with the second storage capacitor plate as a portion of said second storage capacitor plate not overlapping with the first capacitor plate, and the second shield layer (SD3) extends from the edge of the first storage capacitor plate in a direction towards the data signal line. a first thin-film transistor (T3) comprising a gate electrode and a first semiconductor comprising a first source area and a first drain area; a storage capacitor (Cst) comprising a first storage capacitor plate and a second storage capacitor plate, the second capacitor plate overlapping the first storage capacitor plate and being above the first storage capacitor plate, wherein the first storage capacitor plate is electrically coupled to the first drain area; a driving thin-film transistor (T1) comprising a driving gate electrode formed as an integral part of the first storage capacitor plate and a driving semiconductor comprising a driving drain area coupled to the first source area and a driving source area; a data signal line over the second storage capacitor plate; a first shield layer (SD1) in a layer between the data signal line and the first semiconductor, wherein the gate electrode of the first thin-film transistor (T3) comprises a first gate electrode and a second gate electrode, wherein the second storage capacitor plate comprises the first shield layer (SD1), and the first shield layer (SD1) overlaps a part of the first semiconductor between the first gate electrode and the second gate electrode of the first thin-film transistor; and a second shield layer (SD3) in a layer between the data signal line and the driving gate electrode, wherein the second shield layer (SD3) is integrally formed with the second storage capacitor plate as a portion of said second storage capacitor plate not overlapping with the first capacitor plate, and the second shield layer (SD3) extends from the edge of the first storage capacitor plate in a direction towards the data signal line. <EOS>