A memory controller component , comprising an interface coupling the memory controller component to at least one memory component via an address bus and a first data bus , a clock line for providing a clock signal to the memory component , wherein the clock signal is adapted to serve as a timing signal associated with address and control signals that propagate along the address bus , the clock signal requires a first propagation time (t PD0 ) to propagate on the clock line from the memory controller component to the memory component ; a first dedicated timing signal line to convey a first timing signal from the memory controller component to the memory component , wherein the memory component receives the first timing signal to sample data transmitted from the memory controller component to the memory component on the first data bus , the first timing signal requiring a second propagation time (t PD2 ) to propagate on the first dedicated timing signal line from the memory controller component to the memory component ; characterized in that the memory controller component further comprises a second dedicated timing signal line to convey a second timing signal from the memory component to the memory controller component , wherein the second timing signal is used to sample data transmitted from the memory component to the memory controller component on the first data bus ; means to adjust a drive point for the first timing signal based, at least in part, on the difference between the first propagation time (t PD0 ) of the clock signal and the second propagation time (t PD2 ) of the first timing signal; and means to adjust a sampling point for the second timing signal based, at least in part, on the sum of the first propagation time (t PD0 ) and the second propagation time (t PD2 ). an interface coupling the memory controller component to at least one memory component via an address bus and a first data bus , a clock line for providing a clock signal to the memory component , wherein the clock signal is adapted to serve as a timing signal associated with address and control signals that propagate along the address bus , the clock signal requires a first propagation time (t PD0 ) to propagate on the clock line from the memory controller component to the memory component ; a first dedicated timing signal line to convey a first timing signal from the memory controller component to the memory component , wherein the memory component receives the first timing signal to sample data transmitted from the memory controller component to the memory component on the first data bus , the first timing signal requiring a second propagation time (t PD2 ) to propagate on the first dedicated timing signal line from the memory controller component to the memory component ; characterized in that the memory controller component further comprises a second dedicated timing signal line to convey a second timing signal from the memory component to the memory controller component , wherein the second timing signal is used to sample data transmitted from the memory component to the memory controller component on the first data bus ; means to adjust a drive point for the first timing signal based, at least in part, on the difference between the first propagation time (t PD0 ) of the clock signal and the second propagation time (t PD2 ) of the first timing signal; and means to adjust a sampling point for the second timing signal based, at least in part, on the sum of the first propagation time (t PD0 ) and the second propagation time (t PD2 ). <EOS>