A device , comprising a neural network architecture, including: an integrated circuit ; a plurality of digital signal processors formed in the integrated circuit ; an image and deep convolutional neural networks co-processor subsystem formed in the integrated circuit ; a bus formed in the integrated circuit and coupling the plurality of digital signal processors to the image and deep convolutional neural networks co-processor subsystem ; a reconfigurable stream switch formed in the image and deep convolutional neural networks co-processor subsystem ; a data repository formed in the image and deep convolutional neural networks co-processor subsystem and storing coefficients; a hardware-based arithmetic unit formed in the image and deep convolutional neural networks co-processor subsystem and having: at least one input arranged to receive streaming data passed through the reconfigurable stream switch ; at least one output arranged to stream output data through the reconfigurable stream switch ; and a data path between the at least one input and the at least one output , the data path being coupled to the data repository and dedicated to implementing an activation function according to a second order polynomial, the second order polynomial having the form: output = AX 2 + BX + C, wherein X is the received streaming data, wherein A, B, C, are the coefficients and wherein the activation function according to the second order polynomial is part of a convolutional neural network algorithm performed by the neural network architecture; and a further data path between the at least one input and the at least one output , the further data path being dedicated to implementing a rectified linear unit function. an integrated circuit ; a plurality of digital signal processors formed in the integrated circuit ; an image and deep convolutional neural networks co-processor subsystem formed in the integrated circuit ; a bus formed in the integrated circuit and coupling the plurality of digital signal processors to the image and deep convolutional neural networks co-processor subsystem ; a reconfigurable stream switch formed in the image and deep convolutional neural networks co-processor subsystem ; a data repository formed in the image and deep convolutional neural networks co-processor subsystem and storing coefficients; a hardware-based arithmetic unit formed in the image and deep convolutional neural networks co-processor subsystem and having: at least one input arranged to receive streaming data passed through the reconfigurable stream switch ; at least one output arranged to stream output data through the reconfigurable stream switch ; and a data path between the at least one input and the at least one output , the data path being coupled to the data repository and dedicated to implementing an activation function according to a second order polynomial, the second order polynomial having the form: output = AX 2 + BX + C, wherein X is the received streaming data, wherein A, B, C, are the coefficients and wherein the activation function according to the second order polynomial is part of a convolutional neural network algorithm performed by the neural network architecture; and at least one input arranged to receive streaming data passed through the reconfigurable stream switch ; at least one output arranged to stream output data through the reconfigurable stream switch ; and a data path between the at least one input and the at least one output , the data path being coupled to the data repository and dedicated to implementing an activation function according to a second order polynomial, the second order polynomial having the form: output = AX 2 + BX + C, wherein X is the received streaming data, wherein A, B, C, are the coefficients and wherein the activation function according to the second order polynomial is part of a convolutional neural network algorithm performed by the neural network architecture; and <EOS>