A safe digital input dynamic sampling circuit, comprising: a rectifying circuit connected to a digital input signal comprising a positive polarity (I_P) and a negative polarity (I_N), and configured to convert the digital input signal to a direct current, DC, signal; a voltage stabilizing circuit connected to the rectifying circuit, and configured to control a voltage amplitude of the DC signal to output a stabilized DC signal; and a sampling circuit including a first input terminal , a second input terminal and a sampling terminal (123; O_C), the first input terminal being configured to receive the stabilized DC signal, the second input terminal being configured to receive a sampling control signal (O_EN); characterized in that when the positive polarity (I P) of the digital input signal is high, the state of the sampling terminal (123; O_C) is determined by the sampling control signal (O_EN), and when the when the positive polarity (I_P) is low, the state of the sampling terminal (123; O_C) is maintained high; wherein the sampling circuit comprises a first photoelectric coupler and a second photoelectric coupler; wherein a fourth pin of the first photoelectric coupler and a second pin of the second photoelectric coupler are connected, as the first input terminal , to the voltage stabilizing circuit, and a third pin of the first photoelectric coupler is connected to a first pin of the second photoelectric coupler; and wherein a second pin of the first photoelectric coupler serves as the second input terminal , a first pin of the first photoelectric coupler is connected to power supply voltage; a fourth pin of the second photoelectric coupler serves as the sampling terminal (123; O_C) and also connected to power supply voltage, and a third pin of the second photoelectric coupler is grounded. a rectifying circuit connected to a digital input signal comprising a positive polarity (I_P) and a negative polarity (I_N), and configured to convert the digital input signal to a direct current, DC, signal; a voltage stabilizing circuit connected to the rectifying circuit, and configured to control a voltage amplitude of the DC signal to output a stabilized DC signal; and a sampling circuit including a first input terminal , a second input terminal and a sampling terminal (123; O_C), the first input terminal being configured to receive the stabilized DC signal, the second input terminal being configured to receive a sampling control signal (O_EN); characterized in that when the positive polarity (I P) of the digital input signal is high, the state of the sampling terminal (123; O_C) is determined by the sampling control signal (O_EN), and when the when the positive polarity (I_P) is low, the state of the sampling terminal (123; O_C) is maintained high; wherein the sampling circuit comprises a first photoelectric coupler and a second photoelectric coupler; wherein a fourth pin of the first photoelectric coupler and a second pin of the second photoelectric coupler are connected, as the first input terminal , to the voltage stabilizing circuit, and a third pin of the first photoelectric coupler is connected to a first pin of the second photoelectric coupler; and wherein a second pin of the first photoelectric coupler serves as the second input terminal , a first pin of the first photoelectric coupler is connected to power supply voltage; a fourth pin of the second photoelectric coupler serves as the sampling terminal (123; O_C) and also connected to power supply voltage, and a third pin of the second photoelectric coupler is grounded. <EOS>