A processor comprising: fetch and decode circuitry to fetch and decode an instruction having fields to specify destination, multiplier and multiplicand complex vectors; and execution circuitry, responsive to the decoded instruction, to perform two operations: first, generate a double-even multiplicand by duplicating even elements of the specified multiplicand, and generate a temporary vector using a fused multiply-add (FMA) circuit having A and B inputs set to the specified multiplier and the double-even multiplicand, respectively, and having a C input set to a specified summand if the instruction specifies a summand complex vector, and, otherwise, having the C input set to zero; and second, generate a double-odd multiplicand by duplicating odd elements of the specified multiplicand, generate a swapped multiplier by swapping even and odd elements of the specified multiplier, and generate a result using a second FMA circuit having A, B, and C inputs set to the swapped multiplier, the double-odd multiplicand, and the temporary vector, respectively, with the second FMA circuit having its even products negated, and write the result to the specified destination. fetch and decode circuitry to fetch and decode an instruction having fields to specify destination, multiplier and multiplicand complex vectors; and execution circuitry, responsive to the decoded instruction, to perform two operations: first, generate a double-even multiplicand by duplicating even elements of the specified multiplicand, and generate a temporary vector using a fused multiply-add (FMA) circuit having A and B inputs set to the specified multiplier and the double-even multiplicand, respectively, and having a C input set to a specified summand if the instruction specifies a summand complex vector, and, otherwise, having the C input set to zero; and second, generate a double-odd multiplicand by duplicating odd elements of the specified multiplicand, generate a swapped multiplier by swapping even and odd elements of the specified multiplier, and generate a result using a second FMA circuit having A, B, and C inputs set to the swapped multiplier, the double-odd multiplicand, and the temporary vector, respectively, with the second FMA circuit having its even products negated, and write the result to the specified destination. first, generate a double-even multiplicand by duplicating even elements of the specified multiplicand, and generate a temporary vector using a fused multiply-add (FMA) circuit having A and B inputs set to the specified multiplier and the double-even multiplicand, respectively, and having a C input set to a specified summand if the instruction specifies a summand complex vector, and, otherwise, having the C input set to zero; and second, generate a double-odd multiplicand by duplicating odd elements of the specified multiplicand, generate a swapped multiplier by swapping even and odd elements of the specified multiplier, and generate a result using a second FMA circuit having A, B, and C inputs set to the swapped multiplier, the double-odd multiplicand, and the temporary vector, respectively, with the second FMA circuit having its even products negated, and write the result to the specified destination. <EOS>