A duty cycle correction circuit configured to receive an input clock signal and convey a corrected clock signal, the duty cycle correction circuit including: a dual charge pump comprising a first circuit part and a second circuit part , whereby the dual charge pump is characterized in that during a first phase of the time period of the input clock signal, the first circuit part of the dual charge pump conveys an output current to a capacitor kC INT , whereby a voltage across kC INT defines an output control voltage V CP of the dual charge pump, and the up/down current mismatch of the second circuit part of the dual charge pump is integrated into a capacitor C UD2 within the second circuit part and a differential pair measures a difference between a reference voltage V REF and the voltage across capacitor C UD2 and adjusts via a feedback loop the up and down currents of the second circuit part of the dual charge pump until it matches, during a second phase of the same time period of the input clock signal, the second circuit part of the dual charge pump conveys an output current to the capacitor kC INT , whereby the voltage across kC INT defines the output control voltage V CP of the dual charge pump, and the up/down current mismatch of the first circuit part of the dual charge pump is integrated into another capacitor C UD1 within the first circuit part and another differential pair measures a difference between the reference voltage V REF and the voltage across capacitor C UD1 and adjusts via a feedback loop the up and down currents of the first circuit part of the dual charge pump until it matches; and a clock generator connected to each of the first circuit part and second circuit part of the dual charge pump and that is configured to receive the corrected clock signal and to generate an output clock signal having a frequency that is doubled relative to a frequency of the corrected clock signal. a dual charge pump comprising a first circuit part and a second circuit part , whereby the dual charge pump is characterized in that during a first phase of the time period of the input clock signal, the first circuit part of the dual charge pump conveys an output current to a capacitor kC INT , whereby a voltage across kC INT defines an output control voltage V CP of the dual charge pump, and the up/down current mismatch of the second circuit part of the dual charge pump is integrated into a capacitor C UD2 within the second circuit part and a differential pair measures a difference between a reference voltage V REF and the voltage across capacitor C UD2 and adjusts via a feedback loop the up and down currents of the second circuit part of the dual charge pump until it matches, during a second phase of the same time period of the input clock signal, the second circuit part of the dual charge pump conveys an output current to the capacitor kC INT , whereby the voltage across kC INT defines the output control voltage V CP of the dual charge pump, and the up/down current mismatch of the first circuit part of the dual charge pump is integrated into another capacitor C UD1 within the first circuit part and another differential pair measures a difference between the reference voltage V REF and the voltage across capacitor C UD1 and adjusts via a feedback loop the up and down currents of the first circuit part of the dual charge pump until it matches; and a clock generator connected to each of the first circuit part and second circuit part of the dual charge pump and that is configured to receive the corrected clock signal and to generate an output clock signal having a frequency that is doubled relative to a frequency of the corrected clock signal. <EOS>