A circuit for breaking alternating current, the circuit comprising: an input arranged to receive an alternating current (AC); an output arranged to provide the alternating current (AC) to at least one electrical load ; a first controllable switch and a second controllable switch coupled in series with each other and being arranged between the input and the output ; an impedance network (Z; 140) coupled between the first controllable switch and the second controllable switch , wherein the impedance network (Z; 140) comprises a limiting/delay circuit coupled between the first controllable switch and the second controllable switch , wherein limiting/delay circuit is arranged to limit the speed of change of the alternating current; and a transistor network (TN; 110) comprising a first transistor (T TN1 ) and a second transistor (T TN2 ), wherein an emitter/source of the first transistor (T TN1 ) is coupled to a node of the impedance network (Z; 140), a collector/drain of the first transistor (T TN1 ) is coupled to the first controllable switch and the second controllable switch , and a base/gate of the first transistor (T TN1 ) is coupled to a reference ground (REF GND ) node located between the impedance network (Z; 140) and the second controllable switch , and wherein an emitter/source of the second transistor (T TN2 ) is coupled to the reference ground (REF GND ), a collector/drain of the second transistor (T TN2 ) is coupled to the first controllable switch and the second controllable switch , and a base/gate of the second transistor (T TN2 ) is coupled to a node of the impedance network (Z; 140), the transistor network (TN; 110) being arranged to control the first controllable switch and the second controllable switch , so as to control the breaking of the alternating current (AC) provided to the at least one electrical load , based on a value of at least one voltage (V1; V2) of at least one node of the impedance network (Z; 140). an input arranged to receive an alternating current (AC); an output arranged to provide the alternating current (AC) to at least one electrical load ; a first controllable switch and a second controllable switch coupled in series with each other and being arranged between the input and the output ; an impedance network (Z; 140) coupled between the first controllable switch and the second controllable switch , wherein the impedance network (Z; 140) comprises a limiting/delay circuit coupled between the first controllable switch and the second controllable switch , wherein limiting/delay circuit is arranged to limit the speed of change of the alternating current; and a transistor network (TN; 110) comprising a first transistor (T TN1 ) and a second transistor (T TN2 ), wherein an emitter/source of the first transistor (T TN1 ) is coupled to a node of the impedance network (Z; 140), a collector/drain of the first transistor (T TN1 ) is coupled to the first controllable switch and the second controllable switch , and a base/gate of the first transistor (T TN1 ) is coupled to a reference ground (REF GND ) node located between the impedance network (Z; 140) and the second controllable switch , and wherein an emitter/source of the second transistor (T TN2 ) is coupled to the reference ground (REF GND ), a collector/drain of the second transistor (T TN2 ) is coupled to the first controllable switch and the second controllable switch , and a base/gate of the second transistor (T TN2 ) is coupled to a node of the impedance network (Z; 140), the transistor network (TN; 110) being arranged to control the first controllable switch and the second controllable switch , so as to control the breaking of the alternating current (AC) provided to the at least one electrical load , based on a value of at least one voltage (V1; V2) of at least one node of the impedance network (Z; 140). <EOS>