A content addressable memory CAM, comprising bit units of M rows and N columns, wherein both M and N are positive integers greater than or equal to 1; each bit unit comprises a first ferro-electric field effect transistor FeFET (M1) and a second FeFET (M2); a source of the first FeFET is connected to a drain of the second FeFET; and a source of the second FeFET is grounded; wherein the first and the second FeFET comprise a gate and a back gate; and one entry comprises data stored in bit cells of one column in the CAM, bit cells of a same column correspond to a same match line, a drain of a first FeFET in each bit cell of a same column is connected to a match line corresponding to the column, bit cells of a same row correspond to a same first bit line and a same second bit line, a gate of a first FeFET in each bit cell of a same row is connected to a first bit line corresponding to the row, and a gate of a second FeFET in each bit cell of a same row is connected to a second bit line corresponding to the row; bit cells of a same column separately correspond to a same first back gate line and a same second back gate line, a back gate of a first FeFET in each bit cell of a same column is connected to a first back gate line corresponding to the column, and a back gate of a second FeFET in each bit cell of a same column is connected to a second back gate line corresponding to the column; wherein voltage drains that are of first FeFETs and connected to match lines in the CAM are set as preset voltages, where preset voltages corresponding to different match lines are the same or different; and wherein a match value is input by using a first bit line and a reverse value of the match value is input by using a second bit line, or a match value is input by using the second bit line and a reverse value of the match value is input by using the first bit line. a source of the first FeFET is connected to a drain of the second FeFET; and a source of the second FeFET is grounded; wherein the first and the second FeFET comprise a gate and a back gate; and one entry comprises data stored in bit cells of one column in the CAM, bit cells of a same column correspond to a same match line, a drain of a first FeFET in each bit cell of a same column is connected to a match line corresponding to the column, bit cells of a same row correspond to a same first bit line and a same second bit line, a gate of a first FeFET in each bit cell of a same row is connected to a first bit line corresponding to the row, and a gate of a second FeFET in each bit cell of a same row is connected to a second bit line corresponding to the row; bit cells of a same column separately correspond to a same first back gate line and a same second back gate line, a back gate of a first FeFET in each bit cell of a same column is connected to a first back gate line corresponding to the column, and a back gate of a second FeFET in each bit cell of a same column is connected to a second back gate line corresponding to the column; wherein voltage drains that are of first FeFETs and connected to match lines in the CAM are set as preset voltages, where preset voltages corresponding to different match lines are the same or different; and wherein a match value is input by using a first bit line and a reverse value of the match value is input by using a second bit line, or a match value is input by using the second bit line and a reverse value of the match value is input by using the first bit line. <EOS>