A display device comprising: a display panel (DP) comprising a light emitting element (OLED) and an encapsulation layer (TFE) covering the light emitting element (OLED); and an input sensing unit (ISL) disposed on the display panel (DP), wherein: the input sensing unit (ISL) comprises: a first conductive pattern (CD1) disposed on the encapsulation layer (TFE), the first conductive pattern (CD1) including a mesh line having a first line portion (PO1) and a second line portion (PO2) extending from the first line portion (PO1), the first line portion (PO1) and the second line portion (PO2) being disposed on the same layer; an insulation layer (IL1) covering the first conductive pattern (CD1); and a second conductive pattern (CD2) disposed on the insulation layer (IL1), the second conductive pattern (CD2) including a mesh line having a third line portion (PCs) overlapping at least a portion of the first line portion (PO1) of the first conductive pattern (CD1) and a fourth line portion (PO4) extending from the third line portion (PO3), the third line portion (PO3) and the fourth line portion (PO4) being disposed on the same layer; characterised in that a width of the first line portion (PO1) is less than a width of the second line portion (PO2); and/or a width of the third line portion (PO3) is less than a width of the fourth line portion (PO4). a display panel (DP) comprising a light emitting element (OLED) and an encapsulation layer (TFE) covering the light emitting element (OLED); and an input sensing unit (ISL) disposed on the display panel (DP), wherein: the input sensing unit (ISL) comprises: a first conductive pattern (CD1) disposed on the encapsulation layer (TFE), the first conductive pattern (CD1) including a mesh line having a first line portion (PO1) and a second line portion (PO2) extending from the first line portion (PO1), the first line portion (PO1) and the second line portion (PO2) being disposed on the same layer; an insulation layer (IL1) covering the first conductive pattern (CD1); and a second conductive pattern (CD2) disposed on the insulation layer (IL1), the second conductive pattern (CD2) including a mesh line having a third line portion (PCs) overlapping at least a portion of the first line portion (PO1) of the first conductive pattern (CD1) and a fourth line portion (PO4) extending from the third line portion (PO3), the third line portion (PO3) and the fourth line portion (PO4) being disposed on the same layer; characterised in that a width of the first line portion (PO1) is less than a width of the second line portion (PO2); and/or a width of the third line portion (PO3) is less than a width of the fourth line portion (PO4). a first conductive pattern (CD1) disposed on the encapsulation layer (TFE), the first conductive pattern (CD1) including a mesh line having a first line portion (PO1) and a second line portion (PO2) extending from the first line portion (PO1), the first line portion (PO1) and the second line portion (PO2) being disposed on the same layer; an insulation layer (IL1) covering the first conductive pattern (CD1); and a second conductive pattern (CD2) disposed on the insulation layer (IL1), the second conductive pattern (CD2) including a mesh line having a third line portion (PCs) overlapping at least a portion of the first line portion (PO1) of the first conductive pattern (CD1) and a fourth line portion (PO4) extending from the third line portion (PO3), the third line portion (PO3) and the fourth line portion (PO4) being disposed on the same layer; characterised in that a width of the first line portion (PO1) is less than a width of the second line portion (PO2); and/or a width of the third line portion (PO3) is less than a width of the fourth line portion (PO4). <EOS>