An electronic panel comprising: a base substrate (BS); a display unit disposed over the base substrate and comprising a plurality of pixels (PX) and an encapsulation layer covering the pixels; a sensing unit disposed over the display unit and comprising a sensing insulating layer , a first conductive pattern, and a second conductive pattern, the first and second conductive patterns being disposed on different layers from each other with the sensing insulating layer interposed therebetween; a planarization portion (YOC) disposed between the display unit and the sensing unit, and comprising a flat surface (YF) and an inclined surface (YI) inclined at a predetermined inclination angle from the flat surface; and a crack sensing portion (HCC) disposed over the sensing insulating layer, spaced apart from the first and second conductive patterns, and comprising: a crack sensing pattern (HCP) overlapping with the planarization portion; a first connection line (BRH1) connected to one end of the crack sensing pattern and extending in a first direction; and a second connection line (BRH2) connected to the other end of the crack sensing pattern, spaced apart from the first connection line, and extending in the first direction, characterized by the planarization portion (YOC) comprising a recess portion (RC) recessed from the flat surface (YF) and the inclined surface (YI); and the at least one of the first connection line and the second connection line overlaping with the recess portion. a base substrate (BS); a display unit disposed over the base substrate and comprising a plurality of pixels (PX) and an encapsulation layer covering the pixels; a sensing unit disposed over the display unit and comprising a sensing insulating layer , a first conductive pattern, and a second conductive pattern, the first and second conductive patterns being disposed on different layers from each other with the sensing insulating layer interposed therebetween; a planarization portion (YOC) disposed between the display unit and the sensing unit, and comprising a flat surface (YF) and an inclined surface (YI) inclined at a predetermined inclination angle from the flat surface; and a crack sensing portion (HCC) disposed over the sensing insulating layer, spaced apart from the first and second conductive patterns, and comprising: a crack sensing pattern (HCP) overlapping with the planarization portion; a first connection line (BRH1) connected to one end of the crack sensing pattern and extending in a first direction; and a second connection line (BRH2) connected to the other end of the crack sensing pattern, spaced apart from the first connection line, and extending in the first direction, characterized by the planarization portion (YOC) comprising a recess portion (RC) recessed from the flat surface (YF) and the inclined surface (YI); and the at least one of the first connection line and the second connection line overlaping with the recess portion. a crack sensing pattern (HCP) overlapping with the planarization portion; a first connection line (BRH1) connected to one end of the crack sensing pattern and extending in a first direction; and a second connection line (BRH2) connected to the other end of the crack sensing pattern, spaced apart from the first connection line, and extending in the first direction, characterized by the planarization portion (YOC) comprising a recess portion (RC) recessed from the flat surface (YF) and the inclined surface (YI); <EOS>