An apparatus comprising: memory access circuitry configured to perform a tag-guarded memory access operation in response to a target address, the tag-guarded memory access operation by default comprising: comparing an address tag associated with the target address with a guard tag stored in a memory system in association with a block of one or more memory locations comprising an addressed location identified by the target address; and generating an indication of whether a match is detected between the guard tag and the address tag; and control tag storage configured to store, for each of a plurality of memory regions, configuration control information used to control how the tag-guarded memory access operation is performed by the memory access circuitry when the target address is within that memory region, each memory region corresponding to multiple of the blocks, wherein: the configuration control information comprises a match all mode field; and the memory access circuitry is arranged, when the addressed location identified by the target address is within a memory region whose match all mode field is set, to modify the tag-guarded memory access operation such that when the address tag has a predetermined value, the comparison of the address tag with the guard tag is bypassed, and the generating step comprises generating an indication that a match is detected between the guard tag and the address tag. memory access circuitry configured to perform a tag-guarded memory access operation in response to a target address, the tag-guarded memory access operation by default comprising: comparing an address tag associated with the target address with a guard tag stored in a memory system in association with a block of one or more memory locations comprising an addressed location identified by the target address; and generating an indication of whether a match is detected between the guard tag and the address tag; and comparing an address tag associated with the target address with a guard tag stored in a memory system in association with a block of one or more memory locations comprising an addressed location identified by the target address; and generating an indication of whether a match is detected between the guard tag and the address tag; and control tag storage configured to store, for each of a plurality of memory regions, configuration control information used to control how the tag-guarded memory access operation is performed by the memory access circuitry when the target address is within that memory region, each memory region corresponding to multiple of the blocks, wherein: the configuration control information comprises a match all mode field; and the memory access circuitry is arranged, when the addressed location identified by the target address is within a memory region whose match all mode field is set, to modify the tag-guarded memory access operation such that when the address tag has a predetermined value, the comparison of the address tag with the guard tag is bypassed, and the generating step comprises generating an indication that a match is detected between the guard tag and the address tag. the configuration control information comprises a match all mode field; and the memory access circuitry is arranged, when the addressed location identified by the target address is within a memory region whose match all mode field is set, to modify the tag-guarded memory access operation such that when the address tag has a predetermined value, the comparison of the address tag with the guard tag is bypassed, and the generating step comprises generating an indication that a match is detected between the guard tag and the address tag. <EOS>