A segmented digital-to-analog converter, DAC, configured to receive a K-bit digital input signal that is decoded into a M-bit first subword including the most significant bit MSB (dac<15>) of the K-bit digital input signal , a I-bit second subword including intermediate significant bits ISB (dac<6> - dac<4>) of the K-bit digital input signal , and a L-bit third subword including the least significant bit LSB (dac<0>) of the K-bit digital input signal , where M, I, and L are each greater than 1, and K = M + I + L, the segmented DAC including: an interpolation resistor digital-to-analog converter, RDAC, including: a resistor-two-resistor, R-2R, DAC configured to receive the first subword and generate an analog output signal of the R-2R DAC that is a voltage representative of the first subword , wherein the R-2R DAC includes: an R-2R circuit that includes a plurality of resistors; and a first switching circuit connected to the R-2R circuit at a plurality of tap nodes , the first switching circuit including a plurality of switches individually connected between a corresponding one of the tap nodes and one of two reference voltages , wherein one of the reference voltages is preferably ground; and a resistor ladder configured to receive the analog output signal of the R-2R DAC and an N-bit digital interpolation code signal that represents a value of the second subword , the third subword and a calibration code, where N is less than I+L, and generate an analog interpolated signal ; a buffer amplifier configured to receive the analog interpolated signal and generate an output signal for the segmented DAC. an interpolation resistor digital-to-analog converter, RDAC, including: a resistor-two-resistor, R-2R, DAC configured to receive the first subword and generate an analog output signal of the R-2R DAC that is a voltage representative of the first subword , wherein the R-2R DAC includes: an R-2R circuit that includes a plurality of resistors; and a first switching circuit connected to the R-2R circuit at a plurality of tap nodes , the first switching circuit including a plurality of switches individually connected between a corresponding one of the tap nodes and one of two reference voltages , wherein one of the reference voltages is preferably ground; and a resistor ladder configured to receive the analog output signal of the R-2R DAC and an N-bit digital interpolation code signal that represents a value of the second subword , the third subword and a calibration code, where N is less than I+L, and generate an analog interpolated signal ; a resistor-two-resistor, R-2R, DAC configured to receive the first subword and generate an analog output signal of the R-2R DAC that is a voltage representative of the first subword , wherein the R-2R DAC includes: an R-2R circuit that includes a plurality of resistors; and a first switching circuit connected to the R-2R circuit at a plurality of tap nodes , the first switching circuit including a plurality of switches individually connected between a corresponding one of the tap nodes and one of two reference voltages , wherein one of the reference voltages is preferably ground; and an R-2R circuit that includes a plurality of resistors; and a first switching circuit connected to the R-2R circuit at a plurality of tap nodes , the first switching circuit including a plurality of switches individually connected between a corresponding one of the tap nodes and one of two reference voltages , wherein one of the reference voltages is preferably ground; and a resistor ladder configured to receive the analog output signal of the R-2R DAC and an N-bit digital interpolation code signal that represents a value of the second subword , the third subword and a calibration code, where N is less than I+L, and generate an analog interpolated signal ; a buffer amplifier configured to receive the analog interpolated signal and generate an output signal for the segmented DAC. <EOS>