A processor, comprising: a register file comprising a plurality of register entries each configured to store a data value; and an instruction processing circuit, comprising: a fetch circuit configured to fetch a plurality of instructions into an instruction pipeline, the plurality of instructions comprising a producer instruction and a consumer instruction; the instruction pipeline comprises: an execution circuit configured to execute the producer instruction comprising a source register and a target register, to generate a produced value to be written to the target register in the register file; and a scheduler circuit configured to: receive a fetched consumer instruction comprising a source register corresponding to the target register of the producer instruction; and in response to determining the produced value not being available in the instruction pipeline to be consumed as the source register of the consumer instruction: insert a proxy read instruction comprising the target register storing the produced value in the instruction pipeline. a register file comprising a plurality of register entries each configured to store a data value; and an instruction processing circuit, comprising: a fetch circuit configured to fetch a plurality of instructions into an instruction pipeline, the plurality of instructions comprising a producer instruction and a consumer instruction; the instruction pipeline comprises: an execution circuit configured to execute the producer instruction comprising a source register and a target register, to generate a produced value to be written to the target register in the register file; and a scheduler circuit configured to: receive a fetched consumer instruction comprising a source register corresponding to the target register of the producer instruction; and in response to determining the produced value not being available in the instruction pipeline to be consumed as the source register of the consumer instruction: insert a proxy read instruction comprising the target register storing the produced value in the instruction pipeline. a fetch circuit configured to fetch a plurality of instructions into an instruction pipeline, the plurality of instructions comprising a producer instruction and a consumer instruction; the instruction pipeline comprises: an execution circuit configured to execute the producer instruction comprising a source register and a target register, to generate a produced value to be written to the target register in the register file; and a scheduler circuit configured to: receive a fetched consumer instruction comprising a source register corresponding to the target register of the producer instruction; and in response to determining the produced value not being available in the instruction pipeline to be consumed as the source register of the consumer instruction: insert a proxy read instruction comprising the target register storing the produced value in the instruction pipeline. receive a fetched consumer instruction comprising a source register corresponding to the target register of the producer instruction; and in response to determining the produced value not being available in the instruction pipeline to be consumed as the source register of the consumer instruction: insert a proxy read instruction comprising the target register storing the produced value in the instruction pipeline. <EOS>