A data access system comprising: a system bus ; a storage drive ; an image processing device connected to the storage drive via the system bus , the image processing device comprising a processor and a cache memory, the processor configured to generate a read request to access data identified by a first physical address that is mapped to a virtual address ; and a final level cache, FLC, module , separate from the image processing device , connected to the image processing device via the system bus, the FLC module comprising: a DRAM , a FLC controller configured to (i) receive, via the system bus , the request from the processor , and (ii) convert the first physical address to a first virtual address, and a DRAM controller configured to (i) convert the first virtual address to a second physical address, and (ii) access the DRAM based on the second physical address, wherein the FLC controller is configured to detect a cache miss while converting the first physical address to the first virtual address, and in response, signal the image processing device that a cache miss has occurred, and wherein the image processing device is configured to access said data from the storage drive in response to receiving the signal about the cache miss, including mapping the originally generated virtual address to a third physical address and access the data in the storage drive based on the third physical address. a system bus ; a storage drive ; an image processing device connected to the storage drive via the system bus , the image processing device comprising a processor and a cache memory, the processor configured to generate a read request to access data identified by a first physical address that is mapped to a virtual address ; and a final level cache, FLC, module , separate from the image processing device , connected to the image processing device via the system bus, the FLC module comprising: a DRAM , a FLC controller configured to (i) receive, via the system bus , the request from the processor , and (ii) convert the first physical address to a first virtual address, and a DRAM controller configured to (i) convert the first virtual address to a second physical address, and (ii) access the DRAM based on the second physical address, wherein the FLC controller is configured to detect a cache miss while converting the first physical address to the first virtual address, and in response, signal the image processing device that a cache miss has occurred, and wherein the image processing device is configured to access said data from the storage drive in response to receiving the signal about the cache miss, including mapping the originally generated virtual address to a third physical address and access the data in the storage drive based on the third physical address. a DRAM , a FLC controller configured to (i) receive, via the system bus , the request from the processor , and (ii) convert the first physical address to a first virtual address, and a DRAM controller configured to (i) convert the first virtual address to a second physical address, and (ii) access the DRAM based on the second physical address, wherein the FLC controller is configured to detect a cache miss while converting the first physical address to the first virtual address, and in response, signal the image processing device that a cache miss has occurred, and wherein the image processing device is configured to access said data from the storage drive in response to receiving the signal about the cache miss, including mapping the originally generated virtual address to a third physical address and access the data in the storage drive based on the third physical address. <EOS>