A non-volatile memory cell comprising: a semiconductor substrate having an upper surface with an upwardly extending fin that includes first and second side surfaces that oppose each other and an upwardly extending second fin that includes third and fourth side surfaces that oppose each other; a first electrode in electrical contact with a first portion of the fin; a second electrode in electrical contact with a second portion of the fin, wherein the first and second portions of the fin are spaced apart from each other such that a channel region of the fin includes portions of the first and second side surfaces and extends between the first and second portions of the fin; a floating gate that extends along a first portion of the channel region, wherein the floating gate extends along and is insulated from the first side surface, wherein no portion of the floating gate extends along the second side surface, wherein at least a portion of the floating gate is disposed between the fin and the second fin and extends along and is insulated from the third side surface, wherein no portion of the floating gate extends along the fourth side surface, and wherein no conductive gate is disposed along and insulated from a portion of the second side surface that is opposite to a portion of the first side surface along which the floating gate extends and no conductive gate is disposed along and insulated from a portion of the fourth side surface that is opposite to a portion of the third side surface along which the floating gate extends; a word line gate that extends along a second portion of the channel region, wherein the word line gate extends along and is insulated from the first and second side surfaces; a control gate disposed over and insulated from the floating gate; an erase gate having a first portion disposed laterally adjacent to and insulated from the floating gate and a second portion disposed vertically over and insulated from the floating gate. a semiconductor substrate having an upper surface with an upwardly extending fin that includes first and second side surfaces that oppose each other and an upwardly extending second fin that includes third and fourth side surfaces that oppose each other; a first electrode in electrical contact with a first portion of the fin; a second electrode in electrical contact with a second portion of the fin, wherein the first and second portions of the fin are spaced apart from each other such that a channel region of the fin includes portions of the first and second side surfaces and extends between the first and second portions of the fin; a floating gate that extends along a first portion of the channel region, wherein the floating gate extends along and is insulated from the first side surface, wherein no portion of the floating gate extends along the second side surface, wherein at least a portion of the floating gate is disposed between the fin and the second fin and extends along and is insulated from the third side surface, wherein no portion of the floating gate extends along the fourth side surface, and wherein no conductive gate is disposed along and insulated from a portion of the second side surface that is opposite to a portion of the first side surface along which the floating gate extends and no conductive gate is disposed along and insulated from a portion of the fourth side surface that is opposite to a portion of the third side surface along which the floating gate extends; a word line gate that extends along a second portion of the channel region, wherein the word line gate extends along and is insulated from the first and second side surfaces; a control gate disposed over and insulated from the floating gate; an erase gate having a first portion disposed laterally adjacent to and insulated from the floating gate and a second portion disposed vertically over and insulated from the floating gate. <EOS>