A data processing engine, DPE, for a DPE array in an integrated circuit (IC), comprising: a core having compute circuitry and a stall circuit coupled to the compute circuitry ; a memory module comprising random access memory, RAM, banks ; memory interfaces coupled to the RAM banks , wherein a memory interface is coupled to a memory connection of the compute circuitry , and wherein another memory interface is coupled to a memory of another DPE 110 of the DPE array ; arbitration logic configured to control which memory interface has access to which RAM bank , and to forward, to the stall circuit , a signal indicative of a memory collision; and direct memory access, DMA, circuitry coupled to the RAM banks ; and a DPE interconnect comprising streaming interconnect comprising a stream switch coupled to the DMA circuitry and the core , the stream switch being configured to route data streams through the stream switch based on configuration data stored in configuration registers in the stream switch ; and memory-mapped interconnect comprising a memory-mapped switch coupled to the core and the RAM banks , the memory-mapped switch being configured to route address transactions based on a memory address, wherein the stall circuit is configured to assert a stall signal to stall the compute circuitry in case of a memory collision. a core having compute circuitry and a stall circuit coupled to the compute circuitry ; a memory module comprising random access memory, RAM, banks ; memory interfaces coupled to the RAM banks , wherein a memory interface is coupled to a memory connection of the compute circuitry , and wherein another memory interface is coupled to a memory of another DPE 110 of the DPE array ; arbitration logic configured to control which memory interface has access to which RAM bank , and to forward, to the stall circuit , a signal indicative of a memory collision; and direct memory access, DMA, circuitry coupled to the RAM banks ; and random access memory, RAM, banks ; memory interfaces coupled to the RAM banks , wherein a memory interface is coupled to a memory connection of the compute circuitry , and wherein another memory interface is coupled to a memory of another DPE 110 of the DPE array ; arbitration logic configured to control which memory interface has access to which RAM bank , and to forward, to the stall circuit , a signal indicative of a memory collision; and direct memory access, DMA, circuitry coupled to the RAM banks ; and a DPE interconnect comprising streaming interconnect comprising a stream switch coupled to the DMA circuitry and the core , the stream switch being configured to route data streams through the stream switch based on configuration data stored in configuration registers in the stream switch ; and memory-mapped interconnect comprising a memory-mapped switch coupled to the core and the RAM banks , the memory-mapped switch being configured to route address transactions based on a memory address, streaming interconnect comprising a stream switch coupled to the DMA circuitry and the core , the stream switch being configured to route data streams through the stream switch based on configuration data stored in configuration registers in the stream switch ; and memory-mapped interconnect comprising a memory-mapped switch coupled to the core and the RAM banks , the memory-mapped switch being configured to route address transactions based on a memory address, wherein the stall circuit is configured to assert a stall signal to stall the compute circuitry in case of a memory collision. <EOS>