A method, implemented by a compiler, to automatically convert a single-threaded software application into an application-specific supercomputer, the method comprising: a. partitioning the single-threaded software application into a hardware part and a software part, wherein the hardware part corresponds to an arbitrary code fragment from the single-threaded software application; b. automatically converting the hardware part into customized hardware of the application-specific supercomputer, wherein the customized hardware comprises a plurality of components and a plurality of networks connecting the plurality of components and wherein the hardware execution of the customized hardware is functionally equivalent to software execution of the code fragment, and where an application-specific supercomputer is defined to be a hardware system exhibiting substantial parallelism, where hardware of the application-specific supercomputer is not general-purpose and is customized at the register transfer level to accelerate a software application; c. generating interfaces on said hardware and software parts of the single-threaded software application, where the interfaces, at run time: i. perform a software-to-hardware program state transfer upon entry to the code fragment; ii. perform a hardware-to-software program state transfer upon exit from the code fragment; and iii. maintain memory coherence between hardware and software memories of the single-threaded software application; where a program state comprises at least one of: a program counter; and one or more register values; and d. partitioning the customized hardware of the application-specific supercomputer obtained in steps a, b and c into a plurality of modules, implemented in at least one of ASIC technology and FPGA technology, interconnected by a scalable network. a. partitioning the single-threaded software application into a hardware part and a software part, wherein the hardware part corresponds to an arbitrary code fragment from the single-threaded software application; b. automatically converting the hardware part into customized hardware of the application-specific supercomputer, wherein the customized hardware comprises a plurality of components and a plurality of networks connecting the plurality of components and wherein the hardware execution of the customized hardware is functionally equivalent to software execution of the code fragment, and where an application-specific supercomputer is defined to be a hardware system exhibiting substantial parallelism, where hardware of the application-specific supercomputer is not general-purpose and is customized at the register transfer level to accelerate a software application; c. generating interfaces on said hardware and software parts of the single-threaded software application, where the interfaces, at run time: i. perform a software-to-hardware program state transfer upon entry to the code fragment; ii. perform a hardware-to-software program state transfer upon exit from the code fragment; and iii. maintain memory coherence between hardware and software memories of the single-threaded software application; where a program state comprises at least one of: a program counter; and one or more register values; and i. perform a software-to-hardware program state transfer upon entry to the code fragment; ii. perform a hardware-to-software program state transfer upon exit from the code fragment; and iii. maintain memory coherence between hardware and software memories of the single-threaded software application; where a program state comprises at least one of: a program counter; and one or more register values; and a program counter; and one or more register values; and d. partitioning the customized hardware of the application-specific supercomputer obtained in steps a, b and c into a plurality of modules, implemented in at least one of ASIC technology and FPGA technology, interconnected by a scalable network. <EOS>