A neural inference chip for computing neural activations ; the neural inference chip comprising: at least one neural core ; a memory array operatively coupled to the at least one neural core, the memory array comprising a plurality of elements (621,..,624; 821,..,824; 1021,..,1024; 1121,..,1124), each element comprising a memory and a horizontal buffer , the horizontal buffer of each element of the memory array being in communication with either the horizontal buffer of another of the elements of the memory array or to the at least one neural core; an instruction buffer i in communication with the memory array, the instruction buffer having a position (631 ,..,634; 831,..,834; 1031,..,1034; 1131,..,1134) corresponding to each of the plurality of elements of the memory array; a memory controller including an instruction memory in communication with the instruction buffer, wherein the memory controller is adapted to provide at least one instruction to the instruction buffer, the instruction buffer is adapted to advance the at least one instruction between positions in the instruction buffer, the instruction buffer is adapted to provide the at least one instruction to at least one of the plurality of elements of the memory array (621,..,624; 821,..,824; 1021,..,1024; 1121,..,1124) from its associated position (631,..,634; 831,..,834; 1031,..,1034; 1131,..,1134) in the instruction buffer when the memory of the at least one of the plurality of elements contains data associated with the at least one instruction, each of the plurality of elements of the memory array is adapted to provide a data block from its memory its horizontal buffer in response to the arrival of an associated instruction from the instruction buffer the horizontal buffer of each element of the memory array is adapted to provide a data block to the horizontal buffer of another of the elements of the memory array or to the at least one neural core. at least one neural core ; a memory array operatively coupled to the at least one neural core, the memory array comprising a plurality of elements (621,..,624; 821,..,824; 1021,..,1024; 1121,..,1124), each element comprising a memory and a horizontal buffer , the horizontal buffer of each element of the memory array being in communication with either the horizontal buffer of another of the elements of the memory array or to the at least one neural core; an instruction buffer i in communication with the memory array, the instruction buffer having a position (631 ,..,634; 831,..,834; 1031,..,1034; 1131,..,1134) corresponding to each of the plurality of elements of the memory array; a memory controller including an instruction memory in communication with the instruction buffer, wherein the memory controller is adapted to provide at least one instruction to the instruction buffer, the instruction buffer is adapted to advance the at least one instruction between positions in the instruction buffer, the instruction buffer is adapted to provide the at least one instruction to at least one of the plurality of elements of the memory array (621,..,624; 821,..,824; 1021,..,1024; 1121,..,1124) from its associated position (631,..,634; 831,..,834; 1031,..,1034; 1131,..,1134) in the instruction buffer when the memory of the at least one of the plurality of elements contains data associated with the at least one instruction, each of the plurality of elements of the memory array is adapted to provide a data block from its memory its horizontal buffer in response to the arrival of an associated instruction from the instruction buffer the horizontal buffer of each element of the memory array is adapted to provide a data block to the horizontal buffer of another of the elements of the memory array or to the at least one neural core. <EOS>