Inverter circuit for alternately connecting the phases of a multi-phase load (M) to the positive and negative pole of a DC voltage source (U B ), having • pairs of electronic switches (T 1 , T 2 ; T 3 , T 4 ; T 5 , T 6 ; ...) which are connected in parallel with one another and are integrated in a power module , the two switches belonging to the respective pair being connected in series, and the terminal for the respective phase (M 1 , M 2 , M 3 ; ...) of the load (M) being provided at the connection of the two electronic switches belonging to the pair, • an intermediate circuit capacitor (C ZK ) which is connected in parallel with the DC voltage source (U B ), and • electrical connections between the intermediate circuit capacitor (C ZK ) and the power module for connecting the pairs of switches (T 1 , T 2 ; T 3 , T 4 ; T 5 , T 6 ; ...), the electrical connections having distributed parasitic inductances (L PAR ) and, as a result, causing electrical oscillations during switching; comprising a circuit arrangement for regeneratively damping the electrical oscillations, having • a buffer capacitor (C Buff ), the first terminal of which is connected to a terminal of the pairs of switches (T 1 , T 2 ; T 3 , T 4 ; T 5 , T 6 ; ...), • a first diode (D High ), via which the buffer capacitor (C Buff ) is connected to the other terminal of the pairs of switches (T 1 , T 2 ; T 3 , T 4 ; T 5 , T 6 ; ...), • further diodes (D Low1 , D Low2 , D Low3 ; ...) that are arranged between the node between the buffer capacitor (C Buff ) and the first diode and the terminals for the respective phases (M 1 , M 2 , M 3 ) of the load (M) in the blocking direction, and • a buck converter (T S ), via which the buffer capacitor (C Buff ) is connected to the intermediate circuit capacitor (C ZK ) . • pairs of electronic switches (T 1 , T 2 ; T 3 , T 4 ; T 5 , T 6 ; ...) which are connected in parallel with one another and are integrated in a power module , the two switches belonging to the respective pair being connected in series, and the terminal for the respective phase (M 1 , M 2 , M 3 ; ...) of the load (M) being provided at the connection of the two electronic switches belonging to the pair, • an intermediate circuit capacitor (C ZK ) which is connected in parallel with the DC voltage source (U B ), and • electrical connections between the intermediate circuit capacitor (C ZK ) and the power module for connecting the pairs of switches (T 1 , T 2 ; T 3 , T 4 ; T 5 , T 6 ; ...), the electrical connections having distributed parasitic inductances (L PAR ) and, as a result, causing electrical oscillations during switching; comprising a circuit arrangement for regeneratively damping the electrical oscillations, having the electrical connections having distributed parasitic inductances (L PAR ) and, as a result, causing electrical oscillations during switching; comprising a circuit arrangement for regeneratively damping the electrical oscillations, having • a buffer capacitor (C Buff ), the first terminal of which is connected to a terminal of the pairs of switches (T 1 , T 2 ; T 3 , T 4 ; T 5 , T 6 ; ...), • a first diode (D High ), via which the buffer capacitor (C Buff ) is connected to the other terminal of the pairs of switches (T 1 , T 2 ; T 3 , T 4 ; T 5 , T 6 ; ...), • further diodes (D Low1 , D Low2 , D Low3 ; ...) that are arranged between the node between the buffer capacitor (C Buff ) and the first diode and the terminals for the respective phases (M 1 , M 2 , M 3 ) of the load (M) in the blocking direction, and • a buck converter (T S ), via which the buffer capacitor (C Buff ) is connected to the intermediate circuit capacitor (C ZK ) . <EOS>