A silicon-based quantum device for confining charge carriers, the device comprising: a substrate having a first planar region ; a silicon layer which forms part of the substrate and includes a step with an edge and a second planar region , wherein the second planar region is substantially parallel to and offset from the first planar region ; a first electrically insulating layer provided on the silicon layer , overlying the step ; a first metallic layer , provided on the first electrically insulating layer , overlying the step , arranged to be electrically connected such that when a first bias potential is applied to the first metallic layer , a first confinement region is induced in which a charge carrier or charge carriers are confined at the edge ; and a second metallic layer , provided overlying the second planar region of the silicon layer , wherein the second metallic layer is: electrically separated from the first metallic layer ; the second metallic layer is arranged to be electrically connected such that when a second bias potential is applied to the second metallic layer , a second confinement region is induced, and the first confinement region is couplable to the second confinement region ; wherein the first confinement region is displaced from the second confinement region in a direction that is perpendicular to the edge ; characterized in that $ a charge carrier or charge carriers are confined in the second confinement region only in the second planar region of the silicon layer under the second metallic layer . a substrate having a first planar region ; a silicon layer which forms part of the substrate and includes a step with an edge and a second planar region , wherein the second planar region is substantially parallel to and offset from the first planar region ; a first electrically insulating layer provided on the silicon layer , overlying the step ; a first metallic layer , provided on the first electrically insulating layer , overlying the step , arranged to be electrically connected such that when a first bias potential is applied to the first metallic layer , a first confinement region is induced in which a charge carrier or charge carriers are confined at the edge ; and a second metallic layer , provided overlying the second planar region of the silicon layer , wherein the second metallic layer is: electrically separated from the first metallic layer ; the second metallic layer is arranged to be electrically connected such that when a second bias potential is applied to the second metallic layer , a second confinement region is induced, and the first confinement region is couplable to the second confinement region ; wherein the first confinement region is displaced from the second confinement region in a direction that is perpendicular to the edge ; electrically separated from the first metallic layer ; the second metallic layer is arranged to be electrically connected such that when a second bias potential is applied to the second metallic layer , a second confinement region is induced, and the first confinement region is couplable to the second confinement region ; wherein the first confinement region is displaced from the second confinement region in a direction that is perpendicular to the edge ; characterized in that $ a charge carrier or charge carriers are confined in the second confinement region only in the second planar region of the silicon layer under the second metallic layer . <EOS>