A display device comprising: a base layer including a plurality of islands (IS) and a plurality of bridges (BR), the plurality of bridges (BR) connecting the plurality of islands (IS) to each other; first wirings (BL1) disposed on the plurality of bridges (BR); a plurality of pixels (PXL) disposed on the plurality of islands (IS), the first wirings (BL1) being connected to the plurality of pixels (PXL); at least one inorganic insulating layer disposed on the base layer , the inorganic insulating layer comprises an opening (OA) exposing the base layer of a bridge region including the bridges (BR); second wirings (BL2) disposed in the opening (OA); a first organic insulating layer disposed between the first wirings (BL1) and the second wirings (BL2); and a plurality of pixel bridge wirings (PB) which connect at least one pixel (PXL) of the plurality of pixels (PXL) to the first wirings (BL1), wherein a plurality of first contact holes (CNT1) are formed in the first organic insulating layer to expose the second wirings (BL2), and wherein the first wirings (BL1) are disposed in the plurality of first contact holes (CNT1), and the first wirings (BL1) are directly in contact with the second wirings (BL2), and wherein at least one inorganic insulating layer disposed on the base layer comprises a buffer layer , a gate insulating layer , a first interlayer insulating film , and a second interlayer insulating film stacked sequentially, and wherein each of the plurality of pixels (PXL) comprises a transistor, and the transistor comprises a semiconductor layer provided on the buffer layer , a gate electrode provided on the gate insulating layer , and a source electrode and a drain electrode provided on the second interlayer insulating film , and wherein the plurality of pixel bridge wirings (PB) are provided on the first interlayer insulating film , and the first wiring (BL1) is provided on the second interlayer insulating film . a base layer including a plurality of islands (IS) and a plurality of bridges (BR), the plurality of bridges (BR) connecting the plurality of islands (IS) to each other; first wirings (BL1) disposed on the plurality of bridges (BR); a plurality of pixels (PXL) disposed on the plurality of islands (IS), the first wirings (BL1) being connected to the plurality of pixels (PXL); at least one inorganic insulating layer disposed on the base layer , the inorganic insulating layer comprises an opening (OA) exposing the base layer of a bridge region including the bridges (BR); second wirings (BL2) disposed in the opening (OA); a first organic insulating layer disposed between the first wirings (BL1) and the second wirings (BL2); and a plurality of pixel bridge wirings (PB) which connect at least one pixel (PXL) of the plurality of pixels (PXL) to the first wirings (BL1), wherein a plurality of first contact holes (CNT1) are formed in the first organic insulating layer to expose the second wirings (BL2), and wherein the first wirings (BL1) are disposed in the plurality of first contact holes (CNT1), and the first wirings (BL1) are directly in contact with the second wirings (BL2), and wherein at least one inorganic insulating layer disposed on the base layer comprises a buffer layer , a gate insulating layer , a first interlayer insulating film , and a second interlayer insulating film stacked sequentially, and wherein each of the plurality of pixels (PXL) comprises a transistor, and the transistor comprises a semiconductor layer provided on the buffer layer , a gate electrode provided on the gate insulating layer , and a source electrode and a drain electrode provided on the second interlayer insulating film , and wherein the plurality of pixel bridge wirings (PB) are provided on the first interlayer insulating film , and the first wiring (BL1) is provided on the second interlayer insulating film . <EOS>