A method for initializing a differential two-wire data bus between a first subdevice, a bus master (BM), and at least two further sub-devices, the bus nodes (BS1, BS2, BS3), wherein the two-wire data bus (b1b2b3b4) comprises a first one-wire data bus (b1a, b2a, b3a) and a second one-wire data bus (b1b, b2b, b3b) which is divided by the at least two bus nodes into at least two two-wire data bus sections (b1, b2, b3) with associated first one-wire data bus sections (b1a, b2a, b3a) and second one-wire data bus sections (b1b, b2b, b3b) and which is terminated by at least one bus node (BS3) of the bus nodes (BS1, BS2, BS3), the terminal bus node (BS3), comprising the steps of: - determining a new bus node address by the bus master; - storing this bus node address in a bus node address register (BKADR) of a bus node (BS1, BS2, BS3), the bus node of interest, by the bus master (BM), wherein the bus master (BM) and the bus node of interest are connected by one or a plurality of two-wire data bus sections (b1, b2, b3) and the bus node address register (BKADR) is a data register (DR) of a modified JTAG interface or a part of a data register (DR) of a modified JTAG interface of the bus node of interest or a part of an instruction register (IR) of a modified JTAG interface of the bus node of interest, wherein a modified JTAG interface is characterized in that it comprises a JTAG test controller comprising a state diagram corresponding to the IEEE 1149 standard or one of the substandards of the same, and is operated with a differential signal as transmitted via the differential two-wire data bus, instead of being operated with an absolute voltage signal, i.e. a voltage signal changing relative to a reference level, e.g. ground potential; and - connecting one or a plurality of two-wire data bus sections (b1, b2, b3) with one or a plurality of further two-wire data bus sections (b1, b2, b3) by closing a transfer gate (TG) of the bus node of interest, whereby a storage of a bus node address in a bus node address register (BKADR) of the bus node of interest (BS1, BS2, BS3) is prevented by the bus node for as long as the transfer gate (TG) is closed. - determining a new bus node address by the bus master; - storing this bus node address in a bus node address register (BKADR) of a bus node (BS1, BS2, BS3), the bus node of interest, by the bus master (BM), wherein the bus master (BM) and the bus node of interest are connected by one or a plurality of two-wire data bus sections (b1, b2, b3) and the bus node address register (BKADR) is a data register (DR) of a modified JTAG interface or a part of a data register (DR) of a modified JTAG interface of the bus node of interest or a part of an instruction register (IR) of a modified JTAG interface of the bus node of interest, wherein a modified JTAG interface is characterized in that it comprises a JTAG test controller comprising a state diagram corresponding to the IEEE 1149 standard or one of the substandards of the same, and is operated with a differential signal as transmitted via the differential two-wire data bus, instead of being operated with an absolute voltage signal, i.e. a voltage signal changing relative to a reference level, e.g. ground potential; and - connecting one or a plurality of two-wire data bus sections (b1, b2, b3) with one or a plurality of further two-wire data bus sections (b1, b2, b3) by closing a transfer gate (TG) of the bus node of interest, whereby a storage of a bus node address in a bus node address register (BKADR) of the bus node of interest (BS1, BS2, BS3) is prevented by the bus node for as long as the transfer gate (TG) is closed. <EOS>