A method for manufacturing a capacitive micromachined ultrasonic transducer, comprising: forming a plurality of cavities in a layer of silicon oxide on a first side of a first wafer , the first wafer having a second side opposite the first side; bonding a second wafer with the first wafer such that a silicon oxide layer in the second wafer makes direct contact with the layer of silicon oxide of the first wafer, and the second wafer seals the plurality of cavities in the layer of silicon oxide , wherein the first and second wafers are silicon-on-insulator, SOI, or bulk silicon wafers; annealing the first wafer and the second wafer after bonding them together, the annealing utilizing a first temperature; thinning (104; 704) the first wafer or the second wafer after the annealing to a thickness less than 30 microns to create an engineered substrate ; etching a plurality of trenches in the engineered substrate , the plurality of trenches defining a plurality of electrode regions of the engineered substrate; filling the plurality of trenches in the engineered substrate with an insulating material ; forming metal contacts on the plurality of electrode regions of the engineered substrate; bonding (106; 706) the engineered substrate with an integrated circuit CMOS wafer having integrated circuitry formed therein using the metal contacts on the engineered substrate to contact bonding points in the integrated circuit wafer , wherein bonding the engineered substrate with the integrated circuit wafer is performed at a second temperature that is less than the first temperature and the second temperature not exceeding 450 °C; and forming a flexible membrane by thinning (108; 708), after bonding the engineered substrate with the integrated circuit wafer , the first wafer or the second wafer , whichever was not previously thinned as part of forming the engineered substrate , to a thickness less than 30 microns. forming a plurality of cavities in a layer of silicon oxide on a first side of a first wafer , the first wafer having a second side opposite the first side; bonding a second wafer with the first wafer such that a silicon oxide layer in the second wafer makes direct contact with the layer of silicon oxide of the first wafer, and the second wafer seals the plurality of cavities in the layer of silicon oxide , wherein the first and second wafers are silicon-on-insulator, SOI, or bulk silicon wafers; annealing the first wafer and the second wafer after bonding them together, the annealing utilizing a first temperature; thinning (104; 704) the first wafer or the second wafer after the annealing to a thickness less than 30 microns to create an engineered substrate ; etching a plurality of trenches in the engineered substrate , the plurality of trenches defining a plurality of electrode regions of the engineered substrate; filling the plurality of trenches in the engineered substrate with an insulating material ; forming metal contacts on the plurality of electrode regions of the engineered substrate; bonding (106; 706) the engineered substrate with an integrated circuit CMOS wafer having integrated circuitry formed therein using the metal contacts on the engineered substrate to contact bonding points in the integrated circuit wafer , wherein bonding the engineered substrate with the integrated circuit wafer is performed at a second temperature that is less than the first temperature and the second temperature not exceeding 450 °C; and forming a flexible membrane by thinning (108; 708), after bonding the engineered substrate with the integrated circuit wafer , the first wafer or the second wafer , whichever was not previously thinned as part of forming the engineered substrate , to a thickness less than 30 microns. <EOS>