An array substrate, comprising a base substrate , and multiple gate lines multiple data lines , multiple compensation blocks and multiple sub-pixels located on the base substrate , two gate lines being arranged between any two adjacent rows of the sub-pixels , wherein the data lines are provided with multiple first extensions and multiple second extensions arranged alternately, the extending direction of the first extensions intersects with the extending direction of the second extensions , and in the same data line , any two adjacent first extensions and the second extensions between the two adjacent first extensions constitute a pixel accommodating region ; the gate lines and the data lines define multiple first pixel areas and multiple second pixel areas on the base substrate , two sub-pixel s are arranged in each first pixel area , one sub-pixel is arranged in each second pixel area , the multiple first pixel areas are arranged in an array, the multiple second pixel areas are arranged in two columns, and multiple columns of the first pixel areas are located between the two columns of the second pixel areas , and the pixel accommodating region comprises at least one first pixel area or at least one second pixel area ; and the data lines comprise multiple first data lines and two second data lines , the multiple first data lines are located between the two second data lines , and orthographic projections of the second data lines on the base substrate and orthographic projections of the compensation blocks on the base substrate comprise overlapping areas; wherein a first gate line and a second gate line are arranged between two adjacent rows of the sub-pixels ; the compensation blocks and the first gate line are connected with each other to form an integrated structure. the data lines are provided with multiple first extensions and multiple second extensions arranged alternately, the extending direction of the first extensions intersects with the extending direction of the second extensions , and in the same data line , any two adjacent first extensions and the second extensions between the two adjacent first extensions constitute a pixel accommodating region ; the gate lines and the data lines define multiple first pixel areas and multiple second pixel areas on the base substrate , two sub-pixel s are arranged in each first pixel area , one sub-pixel is arranged in each second pixel area , the multiple first pixel areas are arranged in an array, the multiple second pixel areas are arranged in two columns, and multiple columns of the first pixel areas are located between the two columns of the second pixel areas , and the pixel accommodating region comprises at least one first pixel area or at least one second pixel area ; and the data lines comprise multiple first data lines and two second data lines , the multiple first data lines are located between the two second data lines , and orthographic projections of the second data lines on the base substrate and orthographic projections of the compensation blocks on the base substrate comprise overlapping areas; wherein a first gate line and a second gate line are arranged between two adjacent rows of the sub-pixels ; the compensation blocks and the first gate line are connected with each other to form an integrated structure. <EOS>