An apparatus comprising: first memory cells of a memory array ; a first access line (WL1) configured to access the first memory cells; second memory cells of the memory array , the second memory cells being different from the first memory cells; a second access line (WL2) configured to access the second memory cells; and a controller used to cause first data of a page of information to be stored in a first memory portion of the first memory cells, to cause second data of a page of information to be stored in a first memory portion of the second memory cells, wherein the page of information that include the first data is a more error-prone page of information and the page of information that include the second data is a less error-prone page of information, to cause a first portion, a second portion, and a third portion (ECC 0-1-2 DATA B WL1) of an error correction code (ECC) associated with the first data to be stored in a second memory portion of the first memory cells, to cause a fourth portion (ECC 3 DATA B WL1) of an error correction code (ECC) associated with the first data to be stored in a third memory portion of the first memory cells, to cause a fifth portion (ECC 4 DATA B WL1) of the error correction code associated with the first data to be stored in a third memory portion of the second memory cells, whereby the first data of the more error-prone page of information is associated with more portions of ECC than the second data of the less error-prone page of information, wherein the portions of the ECC have the same size, wherein the more error-prone page of information is associated with five portions of ECC in total, wherein the less error-prone page of information is associated with three portions of ECC in total. first memory cells of a memory array ; a first access line (WL1) configured to access the first memory cells; second memory cells of the memory array , the second memory cells being different from the first memory cells; a second access line (WL2) configured to access the second memory cells; and a controller used to cause first data of a page of information to be stored in a first memory portion of the first memory cells, to cause second data of a page of information to be stored in a first memory portion of the second memory cells, wherein the page of information that include the first data is a more error-prone page of information and the page of information that include the second data is a less error-prone page of information, to cause a first portion, a second portion, and a third portion (ECC 0-1-2 DATA B WL1) of an error correction code (ECC) associated with the first data to be stored in a second memory portion of the first memory cells, to cause a fourth portion (ECC 3 DATA B WL1) of an error correction code (ECC) associated with the first data to be stored in a third memory portion of the first memory cells, to cause a fifth portion (ECC 4 DATA B WL1) of the error correction code associated with the first data to be stored in a third memory portion of the second memory cells, whereby the first data of the more error-prone page of information is associated with more portions of ECC than the second data of the less error-prone page of information, wherein the portions of the ECC have the same size, wherein the more error-prone page of information is associated with five portions of ECC in total, wherein the less error-prone page of information is associated with three portions of ECC in total. <EOS>