A memory device , comprising: a plurality of pins configured to receive control signals from an external device ; a first bank having first memory cells, wherein the first bank is activated in a first operation mode and a second operation mode; a second bank having second memory cells, wherein the second bank is deactivated in the first operation mode and activated in the second operation mode; a processing unit configured to perform an operation on first data, output from the first memory cells, and second data, output from the second memory cells, in the second operation mode, the operation including at least one of an exclusive-or operation, a convolution operation, and an encryption/decryption operation; a processing-in-memory, hereinafter referred to as PIM, mode controller configured to select mode information, indicating one of the first operation mode and the second operation mode, in response to the control signals and to control at least one memory parameter, at least one mode register set, hereinafter referred to as MRS, value, or a refresh mode according to the mode information; a command decoder configured to receive the control signals and to output a corresponding mode change command, wherein the PIM mode controller comprises: a mode selector configured to select one of the first and second operation modes in response to the mode change command; and a clock divider configured to receive a clock from the external device and to generate an internal operation clock for driving the processing unit in the second operation mode. a plurality of pins configured to receive control signals from an external device ; a first bank having first memory cells, wherein the first bank is activated in a first operation mode and a second operation mode; a second bank having second memory cells, wherein the second bank is deactivated in the first operation mode and activated in the second operation mode; a processing unit configured to perform an operation on first data, output from the first memory cells, and second data, output from the second memory cells, in the second operation mode, the operation including at least one of an exclusive-or operation, a convolution operation, and an encryption/decryption operation; a processing-in-memory, hereinafter referred to as PIM, mode controller configured to select mode information, indicating one of the first operation mode and the second operation mode, in response to the control signals and to control at least one memory parameter, at least one mode register set, hereinafter referred to as MRS, value, or a refresh mode according to the mode information; a command decoder configured to receive the control signals and to output a corresponding mode change command, wherein the PIM mode controller comprises: a mode selector configured to select one of the first and second operation modes in response to the mode change command; and a clock divider configured to receive a clock from the external device and to generate an internal operation clock for driving the processing unit in the second operation mode. a mode selector configured to select one of the first and second operation modes in response to the mode change command; and a clock divider configured to receive a clock from the external device and to generate an internal operation clock for driving the processing unit in the second operation mode. <EOS>