A method for improving power consumption and timing variation of clock trees in a circuit design comprising sequential cells including at least one of flip-flops and latches, the method being implemented by software running on a computer system and comprising: a) receiving a preliminary arrangement (320; 430) of the sequential cells of a circuit design netlist, wherein the preliminary arrangement of the sequential cells has been determined by performing a preliminary placement of the sequential cells based on at least timing and routability of the sequential cells; b) based on the preliminary arrangement, identifying (322; 432) a group of the sequential cells in the preliminary arrangement which belongs to a single pipeline stage based on the criterion that a first ratio exceeds a second ratio, the first ratio being i) a total area of the group of the sequential cells, over ii) an area of a smallest rectangle enclosing the group of the sequential cells, and the second ratio being i) a total area of all sequential cells of the circuit design netlist, over ii) a total die area of the circuit design netlist minus a total area of hard macros of the circuit design netlist, and on at least one of the following criteria: - that the group constitutes a single vector at a register transfer language level, and/or - that the group of the sequential cells is clocked by a common gated clock signal or is driven by a single integrated clock gating cell, c) subsequently packing (324; 442) the group into a rectangular sequential cell bank of rows and columns of sequential cells, the sequential cell bank having a number m of rows and a number n of columns such that a height-over-width ratio of the sequential cell bank approximates the height-over-width ratio of a bounding box on the group of the sequential cells in the preliminary arrangement; the method further including - placing an integrated clock gating cell in a middle row or middle column of the sequential cell bank. a) receiving a preliminary arrangement (320; 430) of the sequential cells of a circuit design netlist, wherein the preliminary arrangement of the sequential cells has been determined by performing a preliminary placement of the sequential cells based on at least timing and routability of the sequential cells; b) based on the preliminary arrangement, identifying (322; 432) a group of the sequential cells in the preliminary arrangement which belongs to a single pipeline stage based on the criterion that a first ratio exceeds a second ratio, the first ratio being i) a total area of the group of the sequential cells, over ii) an area of a smallest rectangle enclosing the group of the sequential cells, and the second ratio being i) a total area of all sequential cells of the circuit design netlist, over ii) a total die area of the circuit design netlist minus a total area of hard macros of the circuit design netlist, and on at least one of the following criteria: - that the group constitutes a single vector at a register transfer language level, and/or - that the group of the sequential cells is clocked by a common gated clock signal or is driven by a single integrated clock gating cell, - that the group constitutes a single vector at a register transfer language level, and/or - that the group of the sequential cells is clocked by a common gated clock signal or is driven by a single integrated clock gating cell, c) subsequently packing (324; 442) the group into a rectangular sequential cell bank of rows and columns of sequential cells, the sequential cell bank having a number m of rows and a number n of columns such that a height-over-width ratio of the sequential cell bank approximates the height-over-width ratio of a bounding box on the group of the sequential cells in the preliminary arrangement; - placing an integrated clock gating cell in a middle row or middle column of the sequential cell bank. <EOS>