Photonic chip that lies essentially in a plane called the "plane of the chip", this photonic chip comprising: - a substrate having upper and lower faces parallel to the plane of the chip, this substrate comprising, between the upper and lower faces: • a carrier of thickness larger than 50 μm, this carrier being devoid of optical component, • an optical layer (38; 202) bonded, via a bonding interface , to the carrier , this optical layer comprising, in succession, from the upper face to the bonding interface : - an oxide sublayer , and - an encapsulating sublayer , • a laser source (70; 256) buried in the optical layer (38; 202), this laser source comprising a waveguide (76; 276) that is formed on the side of the oxide sublayer which faces the bonding interface and that is encapsulated in a dielectric material of the encapsulating sublayer, this waveguide comprising a first electrical contact (148A, 148B, 148C; 264) embedded in the encapsulating sublayer , characterized in that the photonic chip comprises an interconnect metal network forming a via (158A, 158B, 158C; 266) that extends, in the optical layer (38; 202), from the bonding interface to the first embedded electrical contact (148A, 148B, 148C; 264) of the waveguide, this interconnect metal network comprising metal vias that electrically connect to one another metal lines that extend mainly parallel to the plane of the chip, these metal lines being arranged one above the other within the optical layer (38; 202). - a substrate having upper and lower faces parallel to the plane of the chip, this substrate comprising, between the upper and lower faces: • a carrier of thickness larger than 50 μm, this carrier being devoid of optical component, • an optical layer (38; 202) bonded, via a bonding interface , to the carrier , this optical layer comprising, in succession, from the upper face to the bonding interface : - an oxide sublayer , and - an encapsulating sublayer , • a laser source (70; 256) buried in the optical layer (38; 202), this laser source comprising a waveguide (76; 276) that is formed on the side of the oxide sublayer which faces the bonding interface and that is encapsulated in a dielectric material of the encapsulating sublayer, this waveguide comprising a first electrical contact (148A, 148B, 148C; 264) embedded in the encapsulating sublayer , characterized in that the photonic chip comprises an interconnect metal network forming a via (158A, 158B, 158C; 266) that extends, in the optical layer (38; 202), from the bonding interface to the first embedded electrical contact (148A, 148B, 148C; 264) of the waveguide, this interconnect metal network comprising metal vias that electrically connect to one another metal lines that extend mainly parallel to the plane of the chip, these metal lines being arranged one above the other within the optical layer (38; 202). • a carrier of thickness larger than 50 μm, this carrier being devoid of optical component, • an optical layer (38; 202) bonded, via a bonding interface , to the carrier , this optical layer comprising, in succession, from the upper face to the bonding interface : - an oxide sublayer , and - an encapsulating sublayer , - an oxide sublayer , and - an encapsulating sublayer , • a laser source (70; 256) buried in the optical layer (38; 202), this laser source comprising a waveguide (76; 276) that is formed on the side of the oxide sublayer which faces the bonding interface and that is encapsulated in a dielectric material of the encapsulating sublayer, this waveguide comprising a first electrical contact (148A, 148B, 148C; 264) embedded in the encapsulating sublayer , <EOS>