A method of fabrication of a vertical power MOSFET semiconductor device, comprising: providing a substrate having a first surface and a second surface, wherein the second surface is opposite from the first surface, the substrate comprising an active area and a gate contact area at the first surface of the substrate , wherein the active area is an area of a vertical power MOSFET semiconductor device having active features including source, gate, or channel regions, wherein the gate contact area is part of the gate metal that electrically connects to gate or channel regions within the active area ; forming a drain bond pad on the second surface of the substrate , after forming the drain bond pad on the second surface of the substrate , forming a source metal layer on the first surface of the substrate over the active area and the gate contact area and etching the source metal layer to form a source bond pad on at least a portion of the active area and forming a dielectric layer over the source bond pad and an exposed surface of the substrate ; etching the dielectric layer to create a first opening over at least a portion of the source bond pad and to create a second opening over the gate contact area forming a conductive via by filling a conductive material within the second opening ; and then, forming a gate bond pad over the gate contact area and laterally extending over both (i) a portion of the source bond pad such that the portion of the source bond pad and the gate bond pad are separated by the dielectric layer and (ii) a portion of the active area where the source bond pad is not formed such that the dielectric layer is between the portion of the source bond pad and the gate bond pad and between the gate bond pad and the portion of the active area where the source bond pad is not formed, the dielectric layer electrically insulating the gate bond pad from the source bond pad and electrically insulating the gate bond pad from the active area , wherein the gate bond pad is electrically connected to the gate contact area via the conductive via . the substrate comprising an active area and a gate contact area at the first surface of the substrate , wherein the active area is an area of a vertical power MOSFET semiconductor device having active features including source, gate, or channel regions, wherein the gate contact area is part of the gate metal that electrically connects to gate or channel regions within the active area ; forming a drain bond pad on the second surface of the substrate , after forming the drain bond pad on the second surface of the substrate , forming a source metal layer on the first surface of the substrate over the active area and the gate contact area and etching the source metal layer to form a source bond pad on at least a portion of the active area and forming a dielectric layer over the source bond pad and an exposed surface of the substrate ; etching the dielectric layer to create a first opening over at least a portion of the source bond pad and to create a second opening over the gate contact area forming a conductive via by filling a conductive material within the second opening ; and then, forming a gate bond pad over the gate contact area and laterally extending over both (i) a portion of the source bond pad such that the portion of the source bond pad and the gate bond pad are separated by the dielectric layer and (ii) a portion of the active area where the source bond pad is not formed such that the dielectric layer is between the portion of the source bond pad and the gate bond pad and between the gate bond pad and the portion of the active area where the source bond pad is not formed, the dielectric layer electrically insulating the gate bond pad from the source bond pad and electrically insulating the gate bond pad from the active area , wherein the gate bond pad is electrically connected to the gate contact area via the conductive via . <EOS>