A method for controlling digital-to-analogue converters, DAC, , the method comprising: providing a plurality of digital-to-analogue converters , DAC, (21, 21-1, 21-2) of a multi-channel converter array wherein each DAC (21, 21-1, 21-2) includes a separate clock generator including a numerically controlled oscillator, NCO, or digitally controlled oscillator, DCO, (24-1, 24-2) which is arranged inside the corresponding DAC (21, 21-1, 21-2) and which operates independently from the other clock generators (24-1, 24-2) included in the other DACs (21, 21-1, 21-2); generating, by each of the NCOs or DCOs (24-1, 24-2), respectively, a corresponding RF clock signal; converting, by each DAC (21, 21-1, 21-2), digital data signals (X1, X1-1, X1-2) provided by a digital serial interface circuit into analogue RF data signals (X4, X4-1, X4-2) by using the RF clock signals of the corresponding clock generators (24-1, 24-2); providing a separate control signal (X3, X3-1, X3-2) for each of the NCOs or DCOs (24-1, 24-2), respectively, wherein the control signals (X3, X3-1, X3-2) comprise control information such that when the control signals (X3, X3-1, X3-2) are applied to the corresponding clock generators (24-1, 24-2) the different analogue RF data signals (X4, X4-1, X4-2) provided at respective output terminals of each DAC (21, 21-1, 21-2) comprise a predefined phase shift (X5) to each other by using multiphase clocking to control operation of each DAC (21, 21-1, 21-2) and delaying inputs and outputs of the DACs (21, 21-1, 21-2) with respect to each other in order to ensure that each DAC (21, 21-1, 21-2) path has a different analogue phase response; and - controlling the NCOs or DCOs (24-1, 24-2), respectively, of each DAC (21, 21-1, 21-2) directly and independently by applying the provided control signals (X3, X3-1, X3-2) to the corresponding clock generator (24-1, 24-2). providing a plurality of digital-to-analogue converters , DAC, (21, 21-1, 21-2) of a multi-channel converter array wherein each DAC (21, 21-1, 21-2) includes a separate clock generator including a numerically controlled oscillator, NCO, or digitally controlled oscillator, DCO, (24-1, 24-2) which is arranged inside the corresponding DAC (21, 21-1, 21-2) and which operates independently from the other clock generators (24-1, 24-2) included in the other DACs (21, 21-1, 21-2); generating, by each of the NCOs or DCOs (24-1, 24-2), respectively, a corresponding RF clock signal; converting, by each DAC (21, 21-1, 21-2), digital data signals (X1, X1-1, X1-2) provided by a digital serial interface circuit into analogue RF data signals (X4, X4-1, X4-2) by using the RF clock signals of the corresponding clock generators (24-1, 24-2); providing a separate control signal (X3, X3-1, X3-2) for each of the NCOs or DCOs (24-1, 24-2), respectively, wherein the control signals (X3, X3-1, X3-2) comprise control information such that when the control signals (X3, X3-1, X3-2) are applied to the corresponding clock generators (24-1, 24-2) the different analogue RF data signals (X4, X4-1, X4-2) provided at respective output terminals of each DAC (21, 21-1, 21-2) comprise a predefined phase shift (X5) to each other by using multiphase clocking to control operation of each DAC (21, 21-1, 21-2) and delaying inputs and outputs of the DACs (21, 21-1, 21-2) with respect to each other in order to ensure that each DAC (21, 21-1, 21-2) path has a different analogue phase response; and - controlling the NCOs or DCOs (24-1, 24-2), respectively, of each DAC (21, 21-1, 21-2) directly and independently by applying the provided control signals (X3, X3-1, X3-2) to the corresponding clock generator (24-1, 24-2). - controlling the NCOs or DCOs (24-1, 24-2), respectively, of each DAC (21, 21-1, 21-2) directly and independently by applying the provided control signals (X3, X3-1, X3-2) to the corresponding clock generator (24-1, 24-2). <EOS>