A reciprocal quantum logic, RQL, gate circuit comprising: an input stage (104; 204; 304; 404; 504) having at least one logical input (1I-NI; ai, bi, ci) configured to be asserted based on receiving a positive single flux quantum, SFQ, pulse, the input stage comprising one or more storage loops , at least one of the storage loops being respectively associated with each logical input, each of the storage loops comprising an input Josephson junction, JJ (b2a_1, b2b_1, b2c_1, b4_1), a storage inductor (FLstora_1, FLstorb_1, FLstorc_1, FLstor _1), and a logical decision JJ (108, b0_1), each of the one or more storage loops further having an associated storage loop input inductor (FL6a_1, FL6b_1, FL6c_1), the inductance value of the storage loop input inductor being smaller than the value of the respective storage inductor, and the respective storage loop input inductor, the respective storage inductor, and the respective input JJ being sized such that a storage loop current stored in the respective storage loop is insufficient to unflip the input JJ to allow a pulse stored in the respective storage loop to back out of the respective logical input, the logical decision JJ being common to all the storage loops associated with the logical inputs and being configured to trigger based on biasing provided by one or more currents stored in the storage loops and a first bias signal provided to the input stage; and an output stage (102; 202; 302; 402; 502) comprising phase mode logic, PML, inverter circuitry configured to de-assert an output (NO) based on a triggering of the logical decision JJ, the output stage being provided with a second bias signal , wherein an AC component of the second bias signal is out of phase with an AC component of the first bias signal. an input stage (104; 204; 304; 404; 504) having at least one logical input (1I-NI; ai, bi, ci) configured to be asserted based on receiving a positive single flux quantum, SFQ, pulse, the input stage comprising one or more storage loops , at least one of the storage loops being respectively associated with each logical input, each of the storage loops comprising an input Josephson junction, JJ (b2a_1, b2b_1, b2c_1, b4_1), a storage inductor (FLstora_1, FLstorb_1, FLstorc_1, FLstor _1), and a logical decision JJ (108, b0_1), each of the one or more storage loops further having an associated storage loop input inductor (FL6a_1, FL6b_1, FL6c_1), the inductance value of the storage loop input inductor being smaller than the value of the respective storage inductor, and the respective storage loop input inductor, the respective storage inductor, and the respective input JJ being sized such that a storage loop current stored in the respective storage loop is insufficient to unflip the input JJ to allow a pulse stored in the respective storage loop to back out of the respective logical input, the logical decision JJ being common to all the storage loops associated with the logical inputs and being configured to trigger based on biasing provided by one or more currents stored in the storage loops and a first bias signal provided to the input stage; and an output stage (102; 202; 302; 402; 502) comprising phase mode logic, PML, inverter circuitry configured to de-assert an output (NO) based on a triggering of the logical decision JJ, the output stage being provided with a second bias signal , wherein an AC component of the second bias signal is out of phase with an AC component of the first bias signal. <EOS>