An electronic circuit comprising: an input terminal ; an output terminal ; a first supply rail ; a second supply rail ; a first field effect transistor (Q1), FET, of a first type and having respective gate, source and drain terminals; a second FET (Q2) of said first type and having respective gate, source and drain terminals; a third FET (Q3) of said first type and having respective gate, source and drain terminals; a fourth FET (Q4) of said first type and having respective gate, source and drain terminals; a first load resistor (R1); and a second load resistor (R2), wherein the source of the first FET (Q1) is connected to the first supply rail, the drain of the first FET (Q1) and the source of the second FET (Q2) are connected to the output terminal, the drain of the second FET (Q2) is connected to the second supply rail, the gate of the third FET (Q3) and the gate of the fourth FET (Q4) are connected to the input terminal, the drain of the third FET (Q3) is connected to the second supply rail, the first load resistor (R1) is connected between the first supply rail and the source of the third FET (Q3), the second load resistor (R2) is connected between the drain of the fourth FET (Q4) and the second supply rail, the gate of the first FET (Q1) is connected to a node between the source of the third FET (Q3) and the first load resistor (R1) such that a voltage at the source of the third FET (Q3) is applied to the gate of the first FET (Q1), and the gate of the second FET (Q2) is connected to a node between the drain of the fourth FET (Q4) and the second load resistor (R2) such that a voltage at the drain of the fourth FET (Q4) is applied to the gate of the second FET (Q2). an input terminal ; an output terminal ; a first supply rail ; a second supply rail ; a first field effect transistor (Q1), FET, of a first type and having respective gate, source and drain terminals; a second FET (Q2) of said first type and having respective gate, source and drain terminals; a third FET (Q3) of said first type and having respective gate, source and drain terminals; a fourth FET (Q4) of said first type and having respective gate, source and drain terminals; a first load resistor (R1); and a second load resistor (R2), wherein the source of the first FET (Q1) is connected to the first supply rail, the drain of the first FET (Q1) and the source of the second FET (Q2) are connected to the output terminal, the drain of the second FET (Q2) is connected to the second supply rail, the gate of the third FET (Q3) and the gate of the fourth FET (Q4) are connected to the input terminal, the drain of the third FET (Q3) is connected to the second supply rail, the first load resistor (R1) is connected between the first supply rail and the source of the third FET (Q3), the second load resistor (R2) is connected between the drain of the fourth FET (Q4) and the second supply rail, the gate of the first FET (Q1) is connected to a node between the source of the third FET (Q3) and the first load resistor (R1) such that a voltage at the source of the third FET (Q3) is applied to the gate of the first FET (Q1), and the gate of the second FET (Q2) is connected to a node between the drain of the fourth FET (Q4) and the second load resistor (R2) such that a voltage at the drain of the fourth FET (Q4) is applied to the gate of the second FET (Q2). <EOS>