A Field-Effect Transistor, FET, cell having an asymmetric gate width layout, comprising: a substrate comprising a body having a top surface ; a FET device , comprising: a source disposed in a source epitaxial region in the substrate; a source contact disposed on the source epitaxial region; a drain disposed in a drain epitaxial region in the substrate; a drain contact disposed on the drain epitaxial region; an active gate of an active gate width (W7) formed between the source and the drain; and a channel region below the active gate; and an isolation structure disposed in the substrate adjacent to the FET device, the isolation structure comprising: a diffusion break disposed in the substrate adjacent to one of the source and the drain of the FET device, wherein an implanted depth (DP2) of the one of the source and the drain that is adjacent to the diffusion break is greater than an implanted depth (DP1) of the one of the source and the drain that is not adjacent to the diffusion break; and a dummy gate formed above the diffusion break adjacent to the active gate , the dummy gate having a dummy gate width (W6) that is smaller than the active gate width by a gate width margin, wherein one of the source contact and the drain contact, that corresponds to the one of the source and the drain adjacent to the diffusion break, is between the active gate and the dummy gate. a substrate comprising a body having a top surface ; a FET device , comprising: a source disposed in a source epitaxial region in the substrate; a source contact disposed on the source epitaxial region; a drain disposed in a drain epitaxial region in the substrate; a drain contact disposed on the drain epitaxial region; an active gate of an active gate width (W7) formed between the source and the drain; and a channel region below the active gate; and a source disposed in a source epitaxial region in the substrate; a source contact disposed on the source epitaxial region; a drain disposed in a drain epitaxial region in the substrate; a drain contact disposed on the drain epitaxial region; an active gate of an active gate width (W7) formed between the source and the drain; and a channel region below the active gate; and an isolation structure disposed in the substrate adjacent to the FET device, the isolation structure comprising: a diffusion break disposed in the substrate adjacent to one of the source and the drain of the FET device, wherein an implanted depth (DP2) of the one of the source and the drain that is adjacent to the diffusion break is greater than an implanted depth (DP1) of the one of the source and the drain that is not adjacent to the diffusion break; and a dummy gate formed above the diffusion break adjacent to the active gate , the dummy gate having a dummy gate width (W6) that is smaller than the active gate width by a gate width margin, wherein one of the source contact and the drain contact, that corresponds to the one of the source and the drain adjacent to the diffusion break, is between the active gate and the dummy gate. a diffusion break disposed in the substrate adjacent to one of the source and the drain of the FET device, wherein an implanted depth (DP2) of the one of the source and the drain that is adjacent to the diffusion break is greater than an implanted depth (DP1) of the one of the source and the drain that is not adjacent to the diffusion break; and a dummy gate formed above the diffusion break adjacent to the active gate , the dummy gate having a dummy gate width (W6) that is smaller than the active gate width by a gate width margin, wherein one of the source contact and the drain contact, that corresponds to the one of the source and the drain adjacent to the diffusion break, is between the active gate and the dummy gate. <EOS>