A relaxation oscillator circuit comprising: a current source configured to provide an input current; a current mirror configured to receive the input current from the current source and generate a plurality of starved currents; a Schmitt trigger configured to be current starved by a first starved current of the plurality of starved currents and generate a Schmitt trigger output signal in response to an oscillating voltage input, wherein the Schmitt trigger output signal oscillates from a high signal to a low signal, the high signal triggered when the oscillating input voltage is lower than a lower voltage threshold for the Schmitt trigger , and the low signal is triggered when the oscillating input voltage exceeds a high voltage threshold for the Schmitt trigger ; a plurality of inverters configured to receive the Schmitt trigger output signal and generate an output clock signal (CKP) based thereon, the plurality of inverters including: a plurality of current starved inverters that are current starved by a second starved current of the plurality of starved currents, the plurality of current starved inverters receiving the Schmitt trigger output signal and generating a first inverter output signal; and one or more edge shaping inverters configured to further shape edges for the output clock signal (CKP) and generate the output clock signal (CKP) based, at least, on the first inverter output signal; a capacitor configured to charge or discharge in response to the output clock signal (CKP); and a switching module configured to provide current from the current source to charge the capacitor when the output clock signal (CKP) is low and discharge the capacitor when the output clock signal (CKP) is high. a current source configured to provide an input current; a current mirror configured to receive the input current from the current source and generate a plurality of starved currents; a Schmitt trigger configured to be current starved by a first starved current of the plurality of starved currents and generate a Schmitt trigger output signal in response to an oscillating voltage input, wherein the Schmitt trigger output signal oscillates from a high signal to a low signal, the high signal triggered when the oscillating input voltage is lower than a lower voltage threshold for the Schmitt trigger , and the low signal is triggered when the oscillating input voltage exceeds a high voltage threshold for the Schmitt trigger ; a plurality of inverters configured to receive the Schmitt trigger output signal and generate an output clock signal (CKP) based thereon, the plurality of inverters including: a plurality of current starved inverters that are current starved by a second starved current of the plurality of starved currents, the plurality of current starved inverters receiving the Schmitt trigger output signal and generating a first inverter output signal; and one or more edge shaping inverters configured to further shape edges for the output clock signal (CKP) and generate the output clock signal (CKP) based, at least, on the first inverter output signal; a plurality of current starved inverters that are current starved by a second starved current of the plurality of starved currents, the plurality of current starved inverters receiving the Schmitt trigger output signal and generating a first inverter output signal; and one or more edge shaping inverters configured to further shape edges for the output clock signal (CKP) and generate the output clock signal (CKP) based, at least, on the first inverter output signal; a capacitor configured to charge or discharge in response to the output clock signal (CKP); and a switching module configured to provide current from the current source to charge the capacitor when the output clock signal (CKP) is low and discharge the capacitor when the output clock signal (CKP) is high. <EOS>