An integrated circuit comprising: a plurality of logic tiles, wherein each logic tile includes a plurality of edges and, during operation, is configurable to connect with at least one logic tile adjacent to each edge of the logic tile, and wherein each logic tile includes: a plurality of input/output clock paths, wherein each input/output clock path is associated with a different edge of the logic tile, the plurality of input/output clock paths include: a plurality of input clock paths, each input clock path configurable to receive a tile input clock signal from a connected first adjacent logic tile, and a plurality of output clock paths, each output clock path configurable to output a tile output clock signal to a connected second adjacent logic tile, wherein at least one of the output clock path includes: a u-turn circuit, connected to or in an associated output clock path, to (i) receive a tile clock signal having a first predetermined skew relative to the tile output clock signal and (ii) provide a tile clock signal with a second predetermined skew; clock generation circuitry, coupled to the u-turn circuit of the output clock path, to receive the tile clock signal from the u-turn circuit and generate a tile clock based thereon, wherein the tile clock of each logic tile is balanced relative to the tile clocks generated by the clock generation circuitry of the other logic tiles of the plurality of logic tiles by incorporating, matching or providing a programmable delay of the clock signals of the logic tile; and programmable logic circuitry, coupled to the clock generation circuitry, to receive the tile clock and perform operations based thereon. a plurality of input clock paths, each input clock path configurable to receive a tile input clock signal from a connected first adjacent logic tile, and a plurality of output clock paths, each output clock path configurable to output a tile output clock signal to a connected second adjacent logic tile, wherein at least one of the output clock path includes: a u-turn circuit, connected to or in an associated output clock path, to (i) receive a tile clock signal having a first predetermined skew relative to the tile output clock signal and (ii) provide a tile clock signal with a second predetermined skew; clock generation circuitry, coupled to the u-turn circuit of the output clock path, to receive the tile clock signal from the u-turn circuit and generate a tile clock based thereon, wherein the tile clock of each logic tile is balanced relative to the tile clocks generated by the clock generation circuitry of the other logic tiles of the plurality of logic tiles by incorporating, matching or providing a programmable delay of the clock signals of the logic tile; and programmable logic circuitry, coupled to the clock generation circuitry, to receive the tile clock and perform operations based thereon. a u-turn circuit, connected to or in an associated output clock path, to (i) receive a tile clock signal having a first predetermined skew relative to the tile output clock signal and (ii) provide a tile clock signal with a second predetermined skew; clock generation circuitry, coupled to the u-turn circuit of the output clock path, to receive the tile clock signal from the u-turn circuit and generate a tile clock based thereon, wherein the tile clock of each logic tile is balanced relative to the tile clocks generated by the clock generation circuitry of the other logic tiles of the plurality of logic tiles by incorporating, matching or providing a programmable delay of the clock signals of the logic tile; and programmable logic circuitry, coupled to the clock generation circuitry, to receive the tile clock and perform operations based thereon. <EOS>