An apparatus comprising: a shared local memory ; and one or more processors (2108A-2108N) including a plurality of streaming multiprocessors, SMs, to execute a plurality of thread groups via access to the shared local memory, each thread group of the plurality of thread groups including a plurality of processing threads; characterized in that the one or more processors are to: detect access patterns and data layout properties for each thread group, wherein detecting the access patterns and data layout properties for each thread group includes determining whether the access patterns and data layout properties for the thread group are multi-dimensional; generate a tiling pattern for each thread group based at least in part on the detected access patterns and data layout properties for the thread group, wherein, upon determining that the access patterns and data layout properties for the thread group are multi-dimensional, the one or more processors are to compute an array stride based on banking of the shared local memory to apply the generated tiling pattern to the memory addresses; and apply the generated tiling pattern for each thread group to memory addresses for data stored in the shared local memory. a shared local memory ; and one or more processors (2108A-2108N) including a plurality of streaming multiprocessors, SMs, to execute a plurality of thread groups via access to the shared local memory, each thread group of the plurality of thread groups including a plurality of processing threads; characterized in that the one or more processors are to: detect access patterns and data layout properties for each thread group, wherein detecting the access patterns and data layout properties for each thread group includes determining whether the access patterns and data layout properties for the thread group are multi-dimensional; generate a tiling pattern for each thread group based at least in part on the detected access patterns and data layout properties for the thread group, wherein, upon determining that the access patterns and data layout properties for the thread group are multi-dimensional, the one or more processors are to compute an array stride based on banking of the shared local memory to apply the generated tiling pattern to the memory addresses; and apply the generated tiling pattern for each thread group to memory addresses for data stored in the shared local memory. detect access patterns and data layout properties for each thread group, wherein detecting the access patterns and data layout properties for each thread group includes determining whether the access patterns and data layout properties for the thread group are multi-dimensional; generate a tiling pattern for each thread group based at least in part on the detected access patterns and data layout properties for the thread group, wherein, upon determining that the access patterns and data layout properties for the thread group are multi-dimensional, the one or more processors are to compute an array stride based on banking of the shared local memory to apply the generated tiling pattern to the memory addresses; and apply the generated tiling pattern for each thread group to memory addresses for data stored in the shared local memory. <EOS>