A data sampling circuit, comprising: a first sampling module connected to a data signal terminal (DQ), a reference signal terminal (Vref), a first node (N1), and a second node (N2), wherein the first sampling module is configured to respond to a signal from the data signal terminal (DQ) and a signal from the reference signal terminal (Vref) and to act on the first node (N1) and the second node (N2); a second sampling module connected to the first node (N1), the second node (N2), a third node (N3), and a fourth node (N4), wherein the second sampling module is configured to respond to a signal from the first node (N1) and a signal from the second node (N2) and to act on the third node (N3) and the fourth node (N4); a latch module connected to the third node (N3), the fourth node (N4), a first output terminal (OUT1), and a second output terminal (OUT2), wherein the latch module is configured to, according to a signal from the third node (N3) and a signal from the fourth node (N4), input a high level signal to the first output terminal (OUT1) and input a low level signal to the second output terminal (OUT2), or input the low level signal to the first output terminal (OUT1) and input the high level signal to the second output terminal (OUT2); and a decision feedback equalization module connected in parallel to the second sampling module and configured to reduce intersymbol interference, characterized in that the decision feedback equalization module is connected to the third node (N3), the fourth node (N4), a first control signal terminal (CN1) and a second control signal terminal (CN2), and is configured to respond to a signal from the first control signal terminal (CN1) and to respond to the inverse of the signal from the second control signal terminal (CN2) and to act on the third node (N3) and the fourth node (N4) respectively. a first sampling module connected to a data signal terminal (DQ), a reference signal terminal (Vref), a first node (N1), and a second node (N2), wherein the first sampling module is configured to respond to a signal from the data signal terminal (DQ) and a signal from the reference signal terminal (Vref) and to act on the first node (N1) and the second node (N2); a second sampling module connected to the first node (N1), the second node (N2), a third node (N3), and a fourth node (N4), wherein the second sampling module is configured to respond to a signal from the first node (N1) and a signal from the second node (N2) and to act on the third node (N3) and the fourth node (N4); a latch module connected to the third node (N3), the fourth node (N4), a first output terminal (OUT1), and a second output terminal (OUT2), wherein the latch module is configured to, according to a signal from the third node (N3) and a signal from the fourth node (N4), input a high level signal to the first output terminal (OUT1) and input a low level signal to the second output terminal (OUT2), or input the low level signal to the first output terminal (OUT1) and input the high level signal to the second output terminal (OUT2); and a decision feedback equalization module connected in parallel to the second sampling module and configured to reduce intersymbol interference, characterized in that the decision feedback equalization module is connected to the third node (N3), the fourth node (N4), a first control signal terminal (CN1) and a second control signal terminal (CN2), and is configured to respond to a signal from the first control signal terminal (CN1) and to respond to the inverse of the signal from the second control signal terminal (CN2) and to act on the third node (N3) and the fourth node (N4) respectively. <EOS>