An apparatus configured for bit packing data having various bit widths in a computer system, the apparatus comprising: a first plurality of bit locations in the computer system, each bit location of the first plurality of bit locations comprising a register with a predetermined number of bit slots and each bit slot of the predetermined number of bit slots configured to temporarily store a respective bit of a predetermined number of bits of data, the predetermined number of bits corresponding to one of a number of different data bit widths; and a fixed bit packing network configured to pack the predetermined number of bits from the first plurality of bit locations to a second plurality of bit locations in the computer system, wherein the fixed bit packing network is configured to pack the predetermined number of bits by routing all bits of the predetermined number of bits stored in a same particular bit slot position in the predetermined number of bit slots within each respective bit location of the first plurality of bit locations to bit slots of a register of a particular bit location of the second plurality of bit locations to form bit bundles in respective ones of the second plurality of bit locations , wherein the fixed bit packing network includes fixed point-to-point connections between the bit slots in the first plurality of bit locations and the bit slots in the second plurality of bit locations , and is configured to accommodate each of the number of different data bit widths input to the first plurality of bit locations, and pack data from the first plurality of bit locations into the second plurality of bit locations. a first plurality of bit locations in the computer system, each bit location of the first plurality of bit locations comprising a register with a predetermined number of bit slots and each bit slot of the predetermined number of bit slots configured to temporarily store a respective bit of a predetermined number of bits of data, the predetermined number of bits corresponding to one of a number of different data bit widths; and a fixed bit packing network configured to pack the predetermined number of bits from the first plurality of bit locations to a second plurality of bit locations in the computer system, wherein the fixed bit packing network is configured to pack the predetermined number of bits by routing all bits of the predetermined number of bits stored in a same particular bit slot position in the predetermined number of bit slots within each respective bit location of the first plurality of bit locations to bit slots of a register of a particular bit location of the second plurality of bit locations to form bit bundles in respective ones of the second plurality of bit locations , wherein the fixed bit packing network includes fixed point-to-point connections between the bit slots in the first plurality of bit locations and the bit slots in the second plurality of bit locations , and is configured to accommodate each of the number of different data bit widths input to the first plurality of bit locations, and pack data from the first plurality of bit locations into the second plurality of bit locations. accommodate each of the number of different data bit widths input to the first plurality of bit locations, and pack data from the first plurality of bit locations into the second plurality of bit locations. <EOS>