A mobile wireless communications device comprising: a display ; a graphics processing unit (GPU) being resettable and causing a change in said display when reset; a wireless transceiver ; and a processor cooperating with said GPU and said wireless transceiver for wireless communications; said processor being resettable along with said GPU during a full reset thereof, and said processor also being partially resettable without resetting said GPU to avoid a change in said display, wherein the processor being partially resettable comprises the processor being configured to access a command to reset itself automatically without a user command, wherein said processor has an output generating a GPU reset signal during the partial reset of said processor; and further comprising a power management circuit configured to shut down power to said GPU and said processor during the full reset thereof, but to maintain power to said GPU and said processor during a partial reset of said processor; wherein said power management circuit has an output generating a GPU reset hold signal, wherein the GPU reset hold signal is a power management IC general purpose input/output signal; and further comprising a logic circuit receiving as inputs the GPU reset signal and the GPU reset hold signal and outputting a reset control signal to said GPU; wherein said logic circuit comprises an OR gate, and in which during a partial reset, the processor is configured to set the reset signal to a low value which is OR' ed with the GPU reset hold signal, and said power management IC general purpose input/output signal remains at a high value and keeps the output of the OR gate, comprising the reset control signal, at a high value, thereby preventing the GPU and display from resetting. a display ; a graphics processing unit (GPU) being resettable and causing a change in said display when reset; a wireless transceiver ; and a processor cooperating with said GPU and said wireless transceiver for wireless communications; said processor being resettable along with said GPU during a full reset thereof, and said processor also being partially resettable without resetting said GPU to avoid a change in said display, wherein the processor being partially resettable comprises the processor being configured to access a command to reset itself automatically without a user command, wherein said processor has an output generating a GPU reset signal during the partial reset of said processor; and further comprising a power management circuit configured to shut down power to said GPU and said processor during the full reset thereof, but to maintain power to said GPU and said processor during a partial reset of said processor; wherein said power management circuit has an output generating a GPU reset hold signal, wherein the GPU reset hold signal is a power management IC general purpose input/output signal; and further comprising a logic circuit receiving as inputs the GPU reset signal and the GPU reset hold signal and outputting a reset control signal to said GPU; wherein said logic circuit comprises an OR gate, and in which during a partial reset, the processor is configured to set the reset signal to a low value which is OR' ed with the GPU reset hold signal, and said power management IC general purpose input/output signal remains at a high value and keeps the output of the OR gate, comprising the reset control signal, at a high value, thereby preventing the GPU and display from resetting. <EOS>