Method (MES) for measuring a set of parameters (PAR) of a transistor of the MOS type on a substrate of the SOI (Silicon On Insulator) type, said set of parameters (PAR) including at least the flatband voltage (Vfb) at the rear face of the buried oxide (DGAR), said method comprising the following steps: • Applying (APP) to the front face gate (GAV) of the transistor a direct main voltage Vgs and an alternating voltage v(t), with the direct main voltage Vgs able to sweep a predetermined range of values; • Applying (BIAS) in addition a -Vbias voltage to the front face gate (GAV) and to the source (S) and drain (D) electrodes, with the -Vbias voltage able to sweep a predetermined range of values; • For a given value of the -Vbias voltage, measuring (MIG) the electric current Ig(t) coming from the rear face gate according to Vgs and determining from this measurement the capacity between the front face gate and the rear face of the substrate of the transistor, in such a way as to obtain the characteristic C gb,Bias (Vgs; Vbias); • Varying the value of the -Vbias voltage and for each value of Vbias measuring (MIG_BIAS) the characteristic C gb,Bias (Vgs; Vbias) by varying Vgs in such a way as to obtain a set of characteristics Cgb,Bias(Vgs; Vbias), with each characteristic corresponding to a different value of -Vbias; • Using the set of characteristics C gb,Bias (Vgs; Vbias), determining (CARAC) the set of characteristics C gb,Bias (Vgb; Vbias), Vgb being the voltage between the front face gate and the rear face gate; • Determining (ENV) the characteristic C gb,Bias (Vgb), this characteristic being the envelope of the set of characteristics C gb,Bias (Vgb; Vbias); • Determining (AJU) the set of parameters by carrying out an adjustment between the characteristic C gb,Bias (Vgb) and a theoretical model that describes the behaviour of a transistor of the MOS type on a bulk substrate, said adjustment being limited to the range of values of Vgb for which the channel of the transistor is in depletion regime. • Applying (APP) to the front face gate (GAV) of the transistor a direct main voltage Vgs and an alternating voltage v(t), with the direct main voltage Vgs able to sweep a predetermined range of values; • Applying (BIAS) in addition a -Vbias voltage to the front face gate (GAV) and to the source (S) and drain (D) electrodes, with the -Vbias voltage able to sweep a predetermined range of values; • For a given value of the -Vbias voltage, measuring (MIG) the electric current Ig(t) coming from the rear face gate according to Vgs and determining from this measurement the capacity between the front face gate and the rear face of the substrate of the transistor, in such a way as to obtain the characteristic C gb,Bias (Vgs; Vbias); • Varying the value of the -Vbias voltage and for each value of Vbias measuring (MIG_BIAS) the characteristic C gb,Bias (Vgs; Vbias) by varying Vgs in such a way as to obtain a set of characteristics Cgb,Bias(Vgs; Vbias), with each characteristic corresponding to a different value of -Vbias; • Using the set of characteristics C gb,Bias (Vgs; Vbias), determining (CARAC) the set of characteristics C gb,Bias (Vgb; Vbias), Vgb being the voltage between the front face gate and the rear face gate; • Determining (ENV) the characteristic C gb,Bias (Vgb), this characteristic being the envelope of the set of characteristics C gb,Bias (Vgb; Vbias); • Determining (AJU) the set of parameters by carrying out an adjustment between the characteristic C gb,Bias (Vgb) and a theoretical model that describes the behaviour of a transistor of the MOS type on a bulk substrate, said adjustment being limited to the range of values of Vgb for which the channel of the transistor is in depletion regime. <EOS>