A method of erasing a non-volatile memory device , the non-volatile memory device including a plurality of cell strings having a plurality of memory cells and selection transistors connected together, wherein the selection transistors are located at the ends of the cell strings, the method comprising: performing a first erase operation (S120) based on an erase voltage and an erase control voltage, the erase voltage being applied to a drain electrode of at least one of two selection transistors located at opposite ends of the cell strings and the erase control voltage being applied to a gate electrode of the at least one of the two selection transistors; determining (S150) whether there are slow erase cells among the plurality of memory cells by performing an erase verify operation based on a verify voltage; the method characterized in that it further comprises: either adjusting (S170), in response to determining that the slow erase cells are present, the erase control voltage to generate an adjusted erase control voltage such that a voltage difference between the erase voltage and the adjusted erase control voltage is greater than a voltage difference between the erase voltage and the erase control voltage; and performing a second erase operation based on the adjusted erase control voltage (S120); or increasing (S160) the erase voltage and the erase control voltage by an identical voltage level, in response to determining that the slow erase cells are not present; and, performing a second erase operation based on the identically increased erase voltage and erase control voltage (S120). performing a first erase operation (S120) based on an erase voltage and an erase control voltage, the erase voltage being applied to a drain electrode of at least one of two selection transistors located at opposite ends of the cell strings and the erase control voltage being applied to a gate electrode of the at least one of the two selection transistors; determining (S150) whether there are slow erase cells among the plurality of memory cells by performing an erase verify operation based on a verify voltage; the method characterized in that it further comprises: either adjusting (S170), in response to determining that the slow erase cells are present, the erase control voltage to generate an adjusted erase control voltage such that a voltage difference between the erase voltage and the adjusted erase control voltage is greater than a voltage difference between the erase voltage and the erase control voltage; and performing a second erase operation based on the adjusted erase control voltage (S120); or increasing (S160) the erase voltage and the erase control voltage by an identical voltage level, in response to determining that the slow erase cells are not present; and, performing a second erase operation based on the identically increased erase voltage and erase control voltage (S120). either adjusting (S170), in response to determining that the slow erase cells are present, the erase control voltage to generate an adjusted erase control voltage such that a voltage difference between the erase voltage and the adjusted erase control voltage is greater than a voltage difference between the erase voltage and the erase control voltage; and performing a second erase operation based on the adjusted erase control voltage (S120); or increasing (S160) the erase voltage and the erase control voltage by an identical voltage level, in response to determining that the slow erase cells are not present; and, performing a second erase operation based on the identically increased erase voltage and erase control voltage (S120). <EOS>