A circuit arrangement (A) for transmitting - single-ended logic-level-based data signals and clock signals (HS) as well as - differential common-mode-based data signals and clock signals (LP) between at least one sending arrangement (S) of the circuit arrangement (A) assignable to at least one data source and at least one receiving arrangement (E) of the circuit arrangement (A) assignable to at least one data sink - in the form of at least one common signal stream (SI) serializing the single-ended logic-level-based data signals and clock signals (HS) and the differential data signals and clock signals (LP) and - in the form of at least one bidirectional signal stream which comprises the differential data signals and clock signals (LP) as well as further binary signals (PD), wherein the signal stream comprising both the differential data signals and clock signals (LP) and the binary signals (PD) is transmitted via at least one electrical or galvanic link (GA), and wherein the electrical or galvanic link (GA) has assigned to it, - in the sending arrangement (S) at least one sending/receiving module (TXRXS) and - in the receiving arrangement (E) at least one sending/receiving module (TXRXE), by means of which the signal stream comprising both the differential data signals and clock signals (LP) and the binary signals (PD) is sent or received, wherein the sending/receiving module (TXRXS / TXRXE) comprises: - at least one multiplexer (MUP) for serializing the differential data signals and clock signals (LP) and the binary signals (PD), - at least one binary / P[ulse]W[idth]M[odulation] converter (BPWMW) connected downstream of the multiplexer (MUP) for changing the serialized signal stream from a binary N[on]R[eturn-to]Z[ero]-format into a pulse-width-modulated format, - at least one line driver (LD) connected downstream of the binary / P[ulse]W[idth]M[odulation] converter (BPWMW) and - at least one terminating resistor (R0) connected downstream of the line driver (LD). - single-ended logic-level-based data signals and clock signals (HS) as well as - differential common-mode-based data signals and clock signals (LP) between at least one sending arrangement (S) of the circuit arrangement (A) assignable to at least one data source and at least one receiving arrangement (E) of the circuit arrangement (A) assignable to at least one data sink - in the form of at least one common signal stream (SI) serializing the single-ended logic-level-based data signals and clock signals (HS) and the differential data signals and clock signals (LP) and - in the form of at least one bidirectional signal stream which comprises the differential data signals and clock signals (LP) as well as further binary signals (PD), wherein the signal stream comprising both the differential data signals and clock signals (LP) and the binary signals (PD) is transmitted via at least one electrical or galvanic link (GA), and wherein the electrical or galvanic link (GA) has assigned to it, - in the sending arrangement (S) at least one sending/receiving module (TXRXS) and - in the receiving arrangement (E) at least one sending/receiving module (TXRXE), by means of which the signal stream comprising both the differential data signals and clock signals (LP) and the binary signals (PD) is sent or received, wherein the sending/receiving module (TXRXS / TXRXE) comprises: - at least one multiplexer (MUP) for serializing the differential data signals and clock signals (LP) and the binary signals (PD), - at least one binary / P[ulse]W[idth]M[odulation] converter (BPWMW) connected downstream of the multiplexer (MUP) for changing the serialized signal stream from a binary N[on]R[eturn-to]Z[ero]-format into a pulse-width-modulated format, - at least one line driver (LD) connected downstream of the binary / P[ulse]W[idth]M[odulation] converter (BPWMW) and - at least one terminating resistor (R0) connected downstream of the line driver (LD). <EOS>