A semiconductor device comprising: a stack structure comprising a plurality of insulating layers and a plurality of conductor layers arranged alternatingly over a substrate along a vertical direction; and a marking pattern having at least two pairs of interleaved layers of the plurality of insulating layers alternating with sacrificial material layers, over the substrate and neighboring the stack structure the material of the sacrificial layer including silicon nitride, the material of the insulating layers being different from the material of the sacrificial layer, wherein the marking pattern comprises a central marking structure (206-0, 208-0, 506-0) located in a marking area , the central marking structure (206-0, 208-0, 506-0) dividing the marking area into a first marking sub-area (208-1, 508-1) farther from the stack structure and a second marking sub-area (208-2, 508-2) closer to the stack structure , a first pattern density of the first marking sub-area (208-1, 508-1) being equal to a second pattern density of the second marking sub-area (208-2, 508-2), wherein the first marking sub-area (208-1, 508-1) comprises at least one first marking structure (206-1, 206-3, 506-1) and the second marking sub-area (208-2, 508-2) comprises at least one second marking structure (206-2, 506-2); a number of the at least one first marking structure (206-1, 206-3, 506-1) is greater than or equal to a number of the at least one second marking structure (206-2, 506-2); and each of the central marking structure (206-0, 208-0, 506-0), the at least one first marking structure (206-1, 206-3, 506-1), and the at least one second marking structure (206-2, 506-2) comprises the at least two pairs of interleaved layers, wherein the at least one first marking structure (206-1, 206-3, 506-1) and the at least one second marking structure (206-2, 506-2) are symmetrically distributed on opposite sides of the central marking structure (206-0, 208-0, 506-0) along the horizontal direction. a stack structure comprising a plurality of insulating layers and a plurality of conductor layers arranged alternatingly over a substrate along a vertical direction; and a marking pattern having at least two pairs of interleaved layers of the plurality of insulating layers alternating with sacrificial material layers, over the substrate and neighboring the stack structure the material of the sacrificial layer including silicon nitride, the material of the insulating layers being different from the material of the sacrificial layer, wherein the marking pattern comprises a central marking structure (206-0, 208-0, 506-0) located in a marking area , the central marking structure (206-0, 208-0, 506-0) dividing the marking area into a first marking sub-area (208-1, 508-1) farther from the stack structure and a second marking sub-area (208-2, 508-2) closer to the stack structure , a first pattern density of the first marking sub-area (208-1, 508-1) being equal to a second pattern density of the second marking sub-area (208-2, 508-2), wherein the first marking sub-area (208-1, 508-1) comprises at least one first marking structure (206-1, 206-3, 506-1) and the second marking sub-area (208-2, 508-2) comprises at least one second marking structure (206-2, 506-2); a number of the at least one first marking structure (206-1, 206-3, 506-1) is greater than or equal to a number of the at least one second marking structure (206-2, 506-2); and each of the central marking structure (206-0, 208-0, 506-0), the at least one first marking structure (206-1, 206-3, 506-1), and the at least one second marking structure (206-2, 506-2) comprises the at least two pairs of interleaved layers, wherein the at least one first marking structure (206-1, 206-3, 506-1) and the at least one second marking structure (206-2, 506-2) are symmetrically distributed on opposite sides of the central marking structure (206-0, 208-0, 506-0) along the horizontal direction. <EOS>