A power stage comprising a power transistor and a driver , the power transistor comprising a collector ( c '), a gate ( g ') and an emitter ( e '), the power transistor being configured to change over from a state referred to as saturated to a state referred to as off and vice versa in accordance with a control from the driver , the power stage comprising a resistor Rg positioned between the driver and the gate (g') of the power transistor , the power stage comprising a circuit for compensating for delays that is positioned in shunt with the resistor Rg, the circuit for compensating for delays comprising: - a circuit for compensating for turn-on initialization delays , which is configured to divert the current from the resistor Rg when a saturation of the power transistor is initialized, - a circuit for compensating for turn-off initialization delays , which is configured to divert the current from the resistor Rg when a switching-off of the power transistor is initialized, - a circuit for compensating for delays that is configured to divert the current from the resistor Rg when the power transistor is close to the saturated state , the circuit for compensating for turn-on initialization delays comprising: - a first signal diode (D10) configured to receive by way of its anode a control signal from the driver , - a first signal transistor (T10) connected to the cathode of the signal diode (D10) via an emitter or a source ( e T 10 ) of the first signal transistor (T10), the first signal transistor (T10) comprising a base or a gate ( b T 10 ), and the first signal transistor comprising a collector or a drain ( c T 10 ) connected to the gate (g') of the power transistor , - a first resistor (R10), connected to the emitter or to the source ( e T 10 ) of the first signal transistor (T10), and connected to the base or to the gate ( b T 10 ) of the first signal transistor (T10), - a first signal capacitor (C10) connected to the base or to the gate ( b T 10 ) of the first signal transistor (T10), and to the gate (g') of the power transistor . - a circuit for compensating for turn-on initialization delays , which is configured to divert the current from the resistor Rg when a saturation of the power transistor is initialized, - a circuit for compensating for turn-off initialization delays , which is configured to divert the current from the resistor Rg when a switching-off of the power transistor is initialized, - a circuit for compensating for delays that is configured to divert the current from the resistor Rg when the power transistor is close to the saturated state , - a first signal diode (D10) configured to receive by way of its anode a control signal from the driver , - a first signal transistor (T10) connected to the cathode of the signal diode (D10) via an emitter or a source ( e T 10 ) of the first signal transistor (T10), the first signal transistor (T10) comprising a base or a gate ( b T 10 ), and the first signal transistor comprising a collector or a drain ( c T 10 ) connected to the gate (g') of the power transistor , - a first resistor (R10), connected to the emitter or to the source ( e T 10 ) of the first signal transistor (T10), and connected to the base or to the gate ( b T 10 ) of the first signal transistor (T10), - a first signal capacitor (C10) connected to the base or to the gate ( b T 10 ) of the first signal transistor (T10), and to the gate (g') of the power transistor . <EOS>