A frequency locked loop FLL oscillator circuit suitable for use as a clock generator, comprising: a FLL oscillator generating an oscillator signal (FLL_clk) with a frequency fosc based on an oscillator control signal (OSC_cntrl); an FLL control loop configured to generate the oscillator control signal based on the frequency of the oscillator signal, including: a switched-capacitor resistor-divider circuit configured to provide a frequency control signal (Vfosc) based on the frequency of the oscillator signal (FLL_clk); a spread spectrum clocking SSC generator configured to generate a spread spectrum control signal (V REF_SS ) corresponding to a spread spectrum modulation function; and an FLL control circuit configured to provide the oscillator control signal based on an FLL control signal (FLL_cntrl), and including an amplifier circuit receiving the spread spectrum control signal from the SSC generator at a noninverting input, and the frequency control signal from the switched-capacitor resistor-divider at an inverting input, and outputting the FLL control signal corresponding to the frequency control signal with spread spectrum modulation; the FLL control circuit providing the oscillator control signal with spread spectrum modulation based on the FLL control signal, such that the FLL oscillator generates the oscillator signal (FLL_clk) with spread spectrum modulation; the switched-capacitor resistor-divider circuit including a resistor (R ref ) coupled at an R-divider node (N1) to a switched capacitor (C SW ), the switched capacitor configured to convert the frequency fosc of the oscillator signal (FLL clk) to a resistance, such that the resistor and the switched capacitor operate as resistor divider that outputs the frequency control signal at the R-divider node. a FLL oscillator generating an oscillator signal (FLL_clk) with a frequency fosc based on an oscillator control signal (OSC_cntrl); an FLL control loop configured to generate the oscillator control signal based on the frequency of the oscillator signal, including: a switched-capacitor resistor-divider circuit configured to provide a frequency control signal (Vfosc) based on the frequency of the oscillator signal (FLL_clk); a spread spectrum clocking SSC generator configured to generate a spread spectrum control signal (V REF_SS ) corresponding to a spread spectrum modulation function; and an FLL control circuit configured to provide the oscillator control signal based on an FLL control signal (FLL_cntrl), and including an amplifier circuit receiving the spread spectrum control signal from the SSC generator at a noninverting input, and the frequency control signal from the switched-capacitor resistor-divider at an inverting input, and outputting the FLL control signal corresponding to the frequency control signal with spread spectrum modulation; the FLL control circuit providing the oscillator control signal with spread spectrum modulation based on the FLL control signal, such that the FLL oscillator generates the oscillator signal (FLL_clk) with spread spectrum modulation; the switched-capacitor resistor-divider circuit including a resistor (R ref ) coupled at an R-divider node (N1) to a switched capacitor (C SW ), the switched capacitor configured to convert the frequency fosc of the oscillator signal (FLL clk) to a resistance, such that the resistor and the switched capacitor operate as resistor divider that outputs the frequency control signal at the R-divider node. <EOS>