A processor, comprising: a plurality of block-based physical processor cores (720-727) for executing a program comprising a plurality of instruction blocks, wherein an instruction block comprises an atomic collection of block-based-processor instructions that includes an instruction block header and a plurality of instructions; a thread scheduler configured to schedule a thread of the program for execution, the thread including one or more instruction blocks; and a plurality of system registers , wherein the plurality of system registers stores data (900-940) indicating a number and topology of the plurality of physical processor cores (720-727) to form a logical processor comprising two or more physical processor cores, wherein the logical processor executes the scheduled thread; and wherein the plurality of system registers is dynamically programmable by a software runtime system during execution of the thread so as to change the number and/or topology of the plurality of processor cores within the logical processor; and characterized in that : the plurality of system registers comprises: a physical core number register indicating a core number for a respective physical processor core of the plurality of processor cores (720-727) within the logical processor; a logical core number register indicating a core number associated with the logical processor; a composition topology register indicating topology of the logical processor identified by the core number; and a composition control register indicating an operating mode of the logical processor. a plurality of block-based physical processor cores (720-727) for executing a program comprising a plurality of instruction blocks, wherein an instruction block comprises an atomic collection of block-based-processor instructions that includes an instruction block header and a plurality of instructions; a thread scheduler configured to schedule a thread of the program for execution, the thread including one or more instruction blocks; and a plurality of system registers , wherein the plurality of system registers stores data (900-940) indicating a number and topology of the plurality of physical processor cores (720-727) to form a logical processor comprising two or more physical processor cores, wherein the logical processor executes the scheduled thread; and wherein the plurality of system registers is dynamically programmable by a software runtime system during execution of the thread so as to change the number and/or topology of the plurality of processor cores within the logical processor; and characterized in that : the plurality of system registers comprises: a physical core number register indicating a core number for a respective physical processor core of the plurality of processor cores (720-727) within the logical processor; a logical core number register indicating a core number associated with the logical processor; a composition topology register indicating topology of the logical processor identified by the core number; and a composition control register indicating an operating mode of the logical processor. a physical core number register indicating a core number for a respective physical processor core of the plurality of processor cores (720-727) within the logical processor; a logical core number register indicating a core number associated with the logical processor; a composition topology register indicating topology of the logical processor identified by the core number; and a composition control register indicating an operating mode of the logical processor. <EOS>