A memory device , comprising: x-level cell, XLC, blocks of non-volatile memory cells of a memory array configured to be programmable with more than one bit, wherein x represents an integer greater than one; single level cell, SLC, blocks of non-volatile memory cells of the memory array; and a memory controller operably coupled with the XLC blocks and the SLC blocks, the memory controller configured to: operate a hybrid cache including: a dynamic cache of the memory array including the XLC blocks of non-volatile memory cells shared between the dynamic cache and main memory , the dynamic cache being storage in the memory array available to the hybrid cache that is borrowed from the XLC blocks that form a bulk storage area within the memory array; and a static cache of the memory array including the SLC blocks, the static cache being SLC cache that is obtained from a reserved SLC block within the memory array; and characterised in that the memory controller is configured to disable, based on a comparison of a workload of the hybrid cache to the Total Bytes Written, TBW, Spec for the main memory over a durable lifetime for the memory device, one of the static cache or the dynamic cache so that writes to the hybrid cache are only directed to the other of the static cache or the dynamic cache. x-level cell, XLC, blocks of non-volatile memory cells of a memory array configured to be programmable with more than one bit, wherein x represents an integer greater than one; single level cell, SLC, blocks of non-volatile memory cells of the memory array; and a memory controller operably coupled with the XLC blocks and the SLC blocks, the memory controller configured to: operate a hybrid cache including: a dynamic cache of the memory array including the XLC blocks of non-volatile memory cells shared between the dynamic cache and main memory , the dynamic cache being storage in the memory array available to the hybrid cache that is borrowed from the XLC blocks that form a bulk storage area within the memory array; and a static cache of the memory array including the SLC blocks, the static cache being SLC cache that is obtained from a reserved SLC block within the memory array; and characterised in that the memory controller is configured to disable, based on a comparison of a workload of the hybrid cache to the Total Bytes Written, TBW, Spec for the main memory over a durable lifetime for the memory device, one of the static cache or the dynamic cache so that writes to the hybrid cache are only directed to the other of the static cache or the dynamic cache. operate a hybrid cache including: a dynamic cache of the memory array including the XLC blocks of non-volatile memory cells shared between the dynamic cache and main memory , the dynamic cache being storage in the memory array available to the hybrid cache that is borrowed from the XLC blocks that form a bulk storage area within the memory array; and a static cache of the memory array including the SLC blocks, the static cache being SLC cache that is obtained from a reserved SLC block within the memory array; and a dynamic cache of the memory array including the XLC blocks of non-volatile memory cells shared between the dynamic cache and main memory , the dynamic cache being storage in the memory array available to the hybrid cache that is borrowed from the XLC blocks that form a bulk storage area within the memory array; and a static cache of the memory array including the SLC blocks, the static cache being SLC cache that is obtained from a reserved SLC block within the memory array; and characterised in that the memory controller is configured to disable, based on a comparison of a workload of the hybrid cache to the Total Bytes Written, TBW, Spec for the main memory over a durable lifetime for the memory device, one of the static cache or the dynamic cache so that writes to the hybrid cache are only directed to the other of the static cache or the dynamic cache. <EOS>