A memory module comprising: storage class memory space including at least one storage class memory (SCM) component ; DRAM memory space including at least one DRAM component ; wherein a first region of the DRAM memory space is operated as a cached region of the SCM memory space to provide a caching function for transactions directed to the SCM component ; and a pin interface for coupling to a bus, the bus having a first width; wherein the memory module operates in a first mode that utilizes all of the first width, and in a second mode that utilizes less than all of the first width; further comprising: buffer circuitry to buffer operations between the at least one SCM component and a memory controller (202; 606), the buffer circuitry including a primary interface and a secondary interface coupled to the at least one SCM component; wherein the buffer circuitry includes steering logic to route data between any one of multiple paths coupled to the primary interface and any one of multiple paths coupled to the secondary interface , wherein the steering logic further comprises bypass circuitry to route data between any one of the multiple paths coupled to the primary inter-face to any other of the multiple paths coupled to the primary inter-face , wherein the bypass circuitry is further operable to pass a transaction through the memory module between a first half-width port for coupling to the primary interface , and a second memory module. storage class memory space including at least one storage class memory (SCM) component ; DRAM memory space including at least one DRAM component ; wherein a first region of the DRAM memory space is operated as a cached region of the SCM memory space to provide a caching function for transactions directed to the SCM component ; and a pin interface for coupling to a bus, the bus having a first width; wherein the memory module operates in a first mode that utilizes all of the first width, and in a second mode that utilizes less than all of the first width; further comprising: buffer circuitry to buffer operations between the at least one SCM component and a memory controller (202; 606), the buffer circuitry including a primary interface and a secondary interface coupled to the at least one SCM component; wherein the buffer circuitry includes steering logic to route data between any one of multiple paths coupled to the primary interface and any one of multiple paths coupled to the secondary interface , wherein the steering logic further comprises bypass circuitry to route data between any one of the multiple paths coupled to the primary inter-face to any other of the multiple paths coupled to the primary inter-face , wherein the bypass circuitry is further operable to pass a transaction through the memory module between a first half-width port for coupling to the primary interface , and a second memory module. buffer circuitry to buffer operations between the at least one SCM component and a memory controller (202; 606), the buffer circuitry including a primary interface and a secondary interface coupled to the at least one SCM component; wherein the buffer circuitry includes steering logic to route data between any one of multiple paths coupled to the primary interface and any one of multiple paths coupled to the secondary interface , wherein the steering logic further comprises bypass circuitry to route data between any one of the multiple paths coupled to the primary inter-face to any other of the multiple paths coupled to the primary inter-face , wherein the bypass circuitry is further operable to pass a transaction through the memory module between a first half-width port for coupling to the primary interface , and a second memory module. <EOS>