A vertical field effect transistor, FET, structure comprising: a silicon carbide substrate having a top surface and a bottom surface opposite the top surface; a drain/collector contact on the bottom surface of the silicon carbide substrate ; an epitaxial structure of a first doping type on the top surface of the silicon carbide substrate and having formed therein a first source/emitter region that comprises a first source/emitter implant of the first doping type that is arranged within a first source/emitter well of a second, opposite doping type, a second source/emitter region that comprises a second source/emitter implant of the first doping type that is arranged within a second source/emitter well of the second doping type), and a JFET region formed between the first and second source/emitter regions ; a gate dielectric on a portion of the epitaxial structure ; a first plurality of discontinuous source/emitter contact segments spaced apart from each other and directly on a continuous portion of the first source/emitter implant such that the gate dielectric is not below the first plurality of discontinuous source/emitter contact segments ; a first elongated gate contact and a second elongated gate contact on the gate dielectric and positioned such that the first source/emitter implant is below and between the first elongated gate contact and the second elongated gate contact ; and a first plurality of inter-gate plates that extend from at least one of the first elongated gate contact and the second elongated gate contact into spaces formed between the first plurality of discontinuous source/emitter contact segments , wherein the first plurality of inter-gate plates are separated from the first source/emitter implant by the gate dielectric , characterised in that the inter-gate plates do not extend completely between the first elongated gate contact and the second elongated gate contact . a silicon carbide substrate having a top surface and a bottom surface opposite the top surface; a drain/collector contact on the bottom surface of the silicon carbide substrate ; an epitaxial structure of a first doping type on the top surface of the silicon carbide substrate and having formed therein a first source/emitter region that comprises a first source/emitter implant of the first doping type that is arranged within a first source/emitter well of a second, opposite doping type, a second source/emitter region that comprises a second source/emitter implant of the first doping type that is arranged within a second source/emitter well of the second doping type), and a JFET region formed between the first and second source/emitter regions ; a gate dielectric on a portion of the epitaxial structure ; a first plurality of discontinuous source/emitter contact segments spaced apart from each other and directly on a continuous portion of the first source/emitter implant such that the gate dielectric is not below the first plurality of discontinuous source/emitter contact segments ; a first elongated gate contact and a second elongated gate contact on the gate dielectric and positioned such that the first source/emitter implant is below and between the first elongated gate contact and the second elongated gate contact ; and a first plurality of inter-gate plates that extend from at least one of the first elongated gate contact and the second elongated gate contact into spaces formed between the first plurality of discontinuous source/emitter contact segments , wherein the first plurality of inter-gate plates are separated from the first source/emitter implant by the gate dielectric , characterised in that the inter-gate plates do not extend completely between the first elongated gate contact and the second elongated gate contact . <EOS>