A method to improve a computing performance of a computing device by mapping a Recurrent Neural Network - RNN-architecture to a processor's microarchitecture of the computing device, the method comprising: obtaining values associated with levels of memory based on a description of the processor's microarchitecture; and for a lowest to a highest level of a hierarchy of the RNN architecture, each level associated with the processor's microarchitecture and being described by at least two of memory capacity, number of processor cores, bandwidth, computational bandwidth, and latency: grouping neurons into modules, each module representing a logical unit in an RNN layer within the RNN architecture; and arranging sparse connections between the modules such that the modules satisfy predefined conditions of the RNN architecture, the predefined conditions of the RNN architecture being related to the at least two of memory capacity, number of processor cores, bandwidth, computational bandwidth, and latency, the arranging connections comprising: connecting individual neurons in a fast module (310-312,554-576) located in a first RNN layer to individual neurons in a slow module (304-308,504-510) located in a second RNN layer; connecting each module in its respective layer to other modules in that layer; and connecting the fast module to the slow module via a slow-updating inter-module connection that updates at a lower frequency than other connections, wherein slow modules are modules that update at a slower rate than fast modules which update at a higher frequency and using more data. obtaining values associated with levels of memory based on a description of the processor's microarchitecture; and for a lowest to a highest level of a hierarchy of the RNN architecture, each level associated with the processor's microarchitecture and being described by at least two of memory capacity, number of processor cores, bandwidth, computational bandwidth, and latency: grouping neurons into modules, each module representing a logical unit in an RNN layer within the RNN architecture; and arranging sparse connections between the modules such that the modules satisfy predefined conditions of the RNN architecture, the predefined conditions of the RNN architecture being related to the at least two of memory capacity, number of processor cores, bandwidth, computational bandwidth, and latency, grouping neurons into modules, each module representing a logical unit in an RNN layer within the RNN architecture; and arranging sparse connections between the modules such that the modules satisfy predefined conditions of the RNN architecture, the predefined conditions of the RNN architecture being related to the at least two of memory capacity, number of processor cores, bandwidth, computational bandwidth, and latency, the arranging connections comprising: connecting individual neurons in a fast module (310-312,554-576) located in a first RNN layer to individual neurons in a slow module (304-308,504-510) located in a second RNN layer; connecting each module in its respective layer to other modules in that layer; and connecting the fast module to the slow module via a slow-updating inter-module connection that updates at a lower frequency than other connections, wherein slow modules are modules that update at a slower rate than fast modules which update at a higher frequency and using more data. individual neurons in a slow module (304-308,504-510) located in a second RNN layer; connecting each module in its respective layer to other modules in that layer; and connecting the fast module to the slow module via a slow-updating inter-module connection that updates at a lower frequency than other connections, wherein slow modules are modules that update at a slower rate than fast modules which update at a higher frequency and using more data. <EOS>