A software-defined radio (SDR) terminal device that is adaptively configured in accordance with a radio application, the SDR terminal device comprising: a storage unit; a microprocessor; and at least one baseband accelerator, wherein the microprocessor is configured to read from the storage unit and to execute a code, the code including a radio controller layer that, when executed on said microprocessor, causes the microprocessor to transmit, from an upper layer to the baseband accelerator, a control command for controlling the baseband accelerator and information to be transmitted, and to transmit, to the upper layer, the information received from the baseband accelerator, and a baseband driver layer that, when executed on said microprocessor, causes the microprocessor to enable an interface between the radio controller layer and the baseband accelerator, the microprocessor is configured in such a manner that at least one function block required for implementing the radio application is loaded from the storage unit to the baseband accelerator, and the function block loaded to the baseband accelerator includes a baseband control function block that controls the at least one baseband accelerator in real time, characterized in that the microprocessor is configured to load, from the storage unit, a loader adapted to load the function blocks from the storage unit and to re-arrange the loaded function blocks, and to execute the loader, based on pipeline configuration metadata defined in advance, wherein the loader is adapted to set a pipeline for defining an operational sequence of the loaded function block based on the pipeline configuration metadata and to transmit setting information of the pipeline to the baseband control function block, and the baseband control function block is adapted to control the baseband accelerator in accordance with the pipeline. a storage unit; a microprocessor; and at least one baseband accelerator, wherein the microprocessor is configured to read from the storage unit and to execute a code, the code including a radio controller layer that, when executed on said microprocessor, causes the microprocessor to transmit, from an upper layer to the baseband accelerator, a control command for controlling the baseband accelerator and information to be transmitted, and to transmit, to the upper layer, the information received from the baseband accelerator, and a baseband driver layer that, when executed on said microprocessor, causes the microprocessor to enable an interface between the radio controller layer and the baseband accelerator, the microprocessor is configured in such a manner that at least one function block required for implementing the radio application is loaded from the storage unit to the baseband accelerator, and the function block loaded to the baseband accelerator includes a baseband control function block that controls the at least one baseband accelerator in real time, characterized in that the microprocessor is configured to load, from the storage unit, a loader adapted to load the function blocks from the storage unit and to re-arrange the loaded function blocks, and to execute the loader, based on pipeline configuration metadata defined in advance, wherein the loader is adapted to set a pipeline for defining an operational sequence of the loaded function block based on the pipeline configuration metadata and to transmit setting information of the pipeline to the baseband control function block, and the baseband control function block is adapted to control the baseband accelerator in accordance with the pipeline. <EOS>