An apparatus comprising: a voltage sampler driver configured to generate an output differential current from a sum of at least a first and a second differential current, the voltage sampler driver comprising: an input differential branch pair configured to receive a differential set of input signals representing data, each branch of the differential branch pair comprising one or more transistors (M1, M2) configured to generate the first differential current responsive to the differential set of input signals; an offset differential branch pair configured to facilitate input offset compensation and to receive, at an input, a differential offset voltage control signal, each branch of the offset differential branch pair comprising one or more transistors (M3, M4) configured to generate the second differential current in response to receiving the differential offset voltage control signal, the differential offset voltage control signal accounting for a differential offset error introduced by components of the voltage sampler driver ; an amplifier stage connected to the voltage sampler driver , the amplifier stage configured to generate a differential output voltage based on the output differential current; and a high-pass filter configured to supplement a high-frequency component of the second differential current by injecting a high-pass filtered version of the differential set of input signals into the input of the offset differential branch pair. a voltage sampler driver configured to generate an output differential current from a sum of at least a first and a second differential current, the voltage sampler driver comprising: an input differential branch pair configured to receive a differential set of input signals representing data, each branch of the differential branch pair comprising one or more transistors (M1, M2) configured to generate the first differential current responsive to the differential set of input signals; an offset differential branch pair configured to facilitate input offset compensation and to receive, at an input, a differential offset voltage control signal, each branch of the offset differential branch pair comprising one or more transistors (M3, M4) configured to generate the second differential current in response to receiving the differential offset voltage control signal, the differential offset voltage control signal accounting for a differential offset error introduced by components of the voltage sampler driver ; an input differential branch pair configured to receive a differential set of input signals representing data, each branch of the differential branch pair comprising one or more transistors (M1, M2) configured to generate the first differential current responsive to the differential set of input signals; an offset differential branch pair configured to facilitate input offset compensation and to receive, at an input, a differential offset voltage control signal, each branch of the offset differential branch pair comprising one or more transistors (M3, M4) configured to generate the second differential current in response to receiving the differential offset voltage control signal, the differential offset voltage control signal accounting for a differential offset error introduced by components of the voltage sampler driver ; an amplifier stage connected to the voltage sampler driver , the amplifier stage configured to generate a differential output voltage based on the output differential current; and a high-pass filter configured to supplement a high-frequency component of the second differential current by injecting a high-pass filtered version of the differential set of input signals into the input of the offset differential branch pair. <EOS>