A semiconductor light-emitting element, comprising: a semiconductor stack including an n-type layer, a light-emitting layer above the n-type layer, and a p-type layer above the light-emitting layer, the semiconductor stack having at least one n exposure portion which is a recess at which the n-type layer is exposed; a p wiring electrode layer on the p-type layer; an insulating layer that (i) continuously covers inner lateral surfaces of the at least one n exposure portion and part of a top surface the p wiring electrode layer and (ii) has an opening portion that exposes the n-type layer at a bottom surface of the at least one n exposure portion ; an n wiring electrode layer disposed above the p-type layer and the p wiring electrode layer via the insulating layer , the n wiring electrode layer being in contact with the n-type layer in the opening portion ; at least one first n connecting member that is a conductive member for electric connection to an external conductor; a p connecting member in a region of the p wiring electrode layer, the region being exposed from the n wiring electrode layer and the insulating layer; and a void portion between the at least one first n connecting member and the n wiring electrode layer, wherein the at least one first n connecting member is connected to the n wiring electrode layer in at least one first n terminal region , in a plan view, the at least one first n terminal region includes at least a portion of a region above the opening portion , and the n wiring electrode layer and the p-type layer are disposed below the at least one first n terminal region in a cross section parallel to a stacking direction of the semiconductor stack . a semiconductor stack including an n-type layer, a light-emitting layer above the n-type layer, and a p-type layer above the light-emitting layer, the semiconductor stack having at least one n exposure portion which is a recess at which the n-type layer is exposed; a p wiring electrode layer on the p-type layer; an insulating layer that (i) continuously covers inner lateral surfaces of the at least one n exposure portion and part of a top surface the p wiring electrode layer and (ii) has an opening portion that exposes the n-type layer at a bottom surface of the at least one n exposure portion ; an n wiring electrode layer disposed above the p-type layer and the p wiring electrode layer via the insulating layer , the n wiring electrode layer being in contact with the n-type layer in the opening portion ; at least one first n connecting member that is a conductive member for electric connection to an external conductor; a p connecting member in a region of the p wiring electrode layer, the region being exposed from the n wiring electrode layer and the insulating layer; and a void portion between the at least one first n connecting member and the n wiring electrode layer, wherein the at least one first n connecting member is connected to the n wiring electrode layer in at least one first n terminal region , in a plan view, the at least one first n terminal region includes at least a portion of a region above the opening portion , and the n wiring electrode layer and the p-type layer are disposed below the at least one first n terminal region in a cross section parallel to a stacking direction of the semiconductor stack . <EOS>