A system , comprising: a plurality of memory cells arranged as a plurality of rows of memory cells intersecting a plurality of columns of memory cells, which, in operation, store data; memory management circuitry coupled to the plurality of memory cells, wherein the memory management circuitry, in operation, is configured to tag a first set of the plurality of memory cells as associated with a first operational mode and to tag a second set of the plurality of memory cells as associated with a second operational mode; and power control circuitry, coupled to the memory management circuitry and the plurality of memory cells, wherein the power control circuitry, in operation and based on the tags, is configured to provide a first operational voltage to the first set of memory cells and provides a second operational voltage to the second set of memory cells, wherein the first operational voltage is different from the second operational voltage, wherein the first set of memory cells includes: a subset of columns in the plurality of columns of memory cells, wherein the memory management circuitry, in operation, is configured to tag the first set of memory cells by storing a value in each of the subset of columns, or a subset of rows in the plurality of rows of memory cells, wherein the memory management circuitry is configured to tag the first set of memory cells by storing a value in each of the subset of rows. a plurality of memory cells arranged as a plurality of rows of memory cells intersecting a plurality of columns of memory cells, which, in operation, store data; memory management circuitry coupled to the plurality of memory cells, wherein the memory management circuitry, in operation, is configured to tag a first set of the plurality of memory cells as associated with a first operational mode and to tag a second set of the plurality of memory cells as associated with a second operational mode; and power control circuitry, coupled to the memory management circuitry and the plurality of memory cells, wherein the power control circuitry, in operation and based on the tags, is configured to provide a first operational voltage to the first set of memory cells and provides a second operational voltage to the second set of memory cells, wherein the first operational voltage is different from the second operational voltage, wherein the first set of memory cells includes: a subset of columns in the plurality of columns of memory cells, wherein the memory management circuitry, in operation, is configured to tag the first set of memory cells by storing a value in each of the subset of columns, or a subset of rows in the plurality of rows of memory cells, wherein the memory management circuitry is configured to tag the first set of memory cells by storing a value in each of the subset of rows. a subset of columns in the plurality of columns of memory cells, wherein the memory management circuitry, in operation, is configured to tag the first set of memory cells by storing a value in each of the subset of columns, or a subset of rows in the plurality of rows of memory cells, wherein the memory management circuitry is configured to tag the first set of memory cells by storing a value in each of the subset of rows. <EOS>