A logic gate module comprising a first, a second and a third MRAM cell , each MRAM cell including a corresponding magnetic tunnel junction comprising a corresponding sense layer having a corresponding sense magnetization , a corresponding storage layer having a corresponding storage magnetization , and a corresponding spacer layer between the corresponding sense and storage layers , the MRAM cell having a corresponding junction resistance (R MTJ ) determined by the degree of alignment between the corresponding sense magnetization and the corresponding storage magnetization ; wherein, during a programming operation for selecting a corresponding logic function, the corresponding storage magnetization is switchable between four directions to store data corresponding to one of four logic states; and wherein, during a user input operation, the sense magnetization is switchable between said four directions in accordance with a user input, such that the MRAM cell is usable as a two-bit cell; characterized in that the logic gate module further comprises a first comparator and a second comparator, the first comparator beinq configured to compare the sum of the junction resistances of the first and second MRAM cells with a first reference value and to output a first digital signal indicating a difference between the sum and the first reference value; the second comparator configured to compare the junction resistance (R MTJ ) of the third MRAM cell with a second reference value and to output a second digital signal indicating a difference between the junction resistance (R MTJ ) of the third MRAM cell and the second reference value; and the first, the second and the third MRAM cell and the first and second comparator form a half adder circuit , the first and second MRAM cells and the first comparator being configured to perform an XOR logic function, and the third MRAM cell and the second comparator being configured to perform an AND logic function, such that the first to the third MRAM cells and the first and second comparator are configured to perform a half adder function. wherein, during a programming operation for selecting a corresponding logic function, the corresponding storage magnetization is switchable between four directions to store data corresponding to one of four logic states; and wherein, during a user input operation, the sense magnetization is switchable between said four directions in accordance with a user input, such that the MRAM cell is usable as a two-bit cell; characterized in that the logic gate module further comprises a first comparator and a second comparator, the first comparator beinq configured to compare the sum of the junction resistances of the first and second MRAM cells with a first reference value and to output a first digital signal indicating a difference between the sum and the first reference value; the second comparator configured to compare the junction resistance (R MTJ ) of the third MRAM cell with a second reference value and to output a second digital signal indicating a difference between the junction resistance (R MTJ ) of the third MRAM cell and the second reference value; and the first, the second and the third MRAM cell and the first and second comparator form a half adder circuit , the first and second MRAM cells and the first comparator being configured to perform an XOR logic function, and the third MRAM cell and the second comparator being configured to perform an AND logic function, such that the first to the third MRAM cells and the first and second comparator are configured to perform a half adder function. <EOS>