A method of manufacturing a backside illumination (BSI) CMOS optical sensor having improved cross talk and enhanced photon detection efficiency (PDE), said method comprising the following operations: providing a semiconductor wafer having a semiconductor substrate , a first surface and a second surface , facing each other; performing a standard CMOS frontside manufacturing process comprising the steps of forming at least a first sensing element and a second sensing elements in the substrate between said first and second semiconductor surface, forming at least one insulating layer on said semiconductor substrate first surface, at least a first interconnection layer and at least one metal contact , said at least first interconnection layer and said at least one metal contact being embedded in the at least one insulating layer; providing a carrier semiconductor substrate and attaching said carrier semiconductor substrate to said at least one insulating layer; thinning the semiconductor wafer by removing material from said semiconductor substrate second surface ; forming a backside deep trench isolation (DTI) structure in the substrate surrounding said at least first and second sensing elements, said DTI structure extending from the thinned second surface; filling said DTI structure with first insulating material covering the side walls and the bottom of the trench and with a second conductive material filling the inside of said deep trench isolation (DTI) structure; planarizing the semiconductor wafer from said thinned second surface, so as to expose said semiconductor substrate in the region of the at least first and second sensing elements, said at least first and second sensing elements being surrounded by said DTI structure; forming a common voltage applying structure from said thinned second surface contacting said deep trench isolation (DTI) structure and said semiconductor substrate in the at least first and second sensing elements. providing a semiconductor wafer having a semiconductor substrate , a first surface and a second surface , facing each other; performing a standard CMOS frontside manufacturing process comprising the steps of forming at least a first sensing element and a second sensing elements in the substrate between said first and second semiconductor surface, forming at least one insulating layer on said semiconductor substrate first surface, at least a first interconnection layer and at least one metal contact , said at least first interconnection layer and said at least one metal contact being embedded in the at least one insulating layer; providing a carrier semiconductor substrate and attaching said carrier semiconductor substrate to said at least one insulating layer; thinning the semiconductor wafer by removing material from said semiconductor substrate second surface ; forming a backside deep trench isolation (DTI) structure in the substrate surrounding said at least first and second sensing elements, said DTI structure extending from the thinned second surface; filling said DTI structure with first insulating material covering the side walls and the bottom of the trench and with a second conductive material filling the inside of said deep trench isolation (DTI) structure; planarizing the semiconductor wafer from said thinned second surface, so as to expose said semiconductor substrate in the region of the at least first and second sensing elements, said at least first and second sensing elements being surrounded by said DTI structure; forming a common voltage applying structure from said thinned second surface contacting said deep trench isolation (DTI) structure and said semiconductor substrate in the at least first and second sensing elements. <EOS>