A method for converting instruction addresses of a first predicted address block into decoded micro-operations for output to an operations queue that stores decoded micro-operations in program order, and for subsequent execution by a remainder of an instruction execution pipeline, the method comprising: providing an index associated with the first predicted address block to an operation cache tag array to obtain a first tag associated with a first operation cache tag array entry and a second tag associated with a second operation cache tag array entry; in a first computer clock cycle, determining that both the first tag and the second tag match a tag derived from the predicted address block and that an end address associated with the first operation cache tag array entry matches a start address associated with the second operation cache tag array entry; in the first computer clock cycle, identifying a set of instructions for which decoded micro-operations are stored in an operation cache data array of an operation cache path , as instructions at addresses associated with both the first operation cache tag array entry and the second operation cache tag array entry; storing a first operation cache queue entry for the set of instructions in an operation cache queue , the first operation cache queue entry including an indication indicating whether to wait to receive a signal from an instruction cache path to proceed; obtaining decoded micro-operations corresponding to the first operation cache queue entry from the operation cache; and outputting the decoded micro-operations corresponding to the first operation cache queue entry to the operations queue , at a time that is based on the indication of the first operation cache queue entry indicating whether to wait to receive the signal from the instruction cache path to proceed. providing an index associated with the first predicted address block to an operation cache tag array to obtain a first tag associated with a first operation cache tag array entry and a second tag associated with a second operation cache tag array entry; in a first computer clock cycle, determining that both the first tag and the second tag match a tag derived from the predicted address block and that an end address associated with the first operation cache tag array entry matches a start address associated with the second operation cache tag array entry; in the first computer clock cycle, identifying a set of instructions for which decoded micro-operations are stored in an operation cache data array of an operation cache path , as instructions at addresses associated with both the first operation cache tag array entry and the second operation cache tag array entry; storing a first operation cache queue entry for the set of instructions in an operation cache queue , the first operation cache queue entry including an indication indicating whether to wait to receive a signal from an instruction cache path to proceed; obtaining decoded micro-operations corresponding to the first operation cache queue entry from the operation cache; and outputting the decoded micro-operations corresponding to the first operation cache queue entry to the operations queue , at a time that is based on the indication of the first operation cache queue entry indicating whether to wait to receive the signal from the instruction cache path to proceed. <EOS>