A logic gate comprising: a first input (A) and a second input (B); a first memristor (M 1 ), a second memristor (M 2 ), a third memristor (M 3 ), and a fourth memristor (M 4 ), each memristor having a positive terminal and a negative terminal; and a first output and a second output , wherein the negative terminal of the first memristor (M 1 ) and the positive terminal of the second memristor (M 2 ) are connected in common to the first input (A), wherein the negative terminal of the third memristor (M 3 ) and the positive terminal of the fourth memristor (M 4 ) are connected in common to the second input (B), wherein the negative terminal of the second memristor (M 2 ) and the negative terminal of the fourth memristor (M 4 ) are connected in common to the first output , wherein the positive terminal of the first memristor (M 1 ) and the positive terminal of the third memristor (M 3 ) are connected in common to the second output , further comprising a transistor (NMOST, PMOST, T), wherein the gate of the transistor is connected to one of the first and second outputs , wherein the drain of the transistor is connected to the other of the first and second outputs , and wherein the source of the transistor is connected to a positive or negative supply voltage or ground, and wherein, in use, the voltage of the first output , corresponds to the result of a first logic operation relative to voltages applied to the first and second inputs (A, B), and the voltage of the second output , corresponds to the result of a second logic operation relative to voltages applied to the first and second inputs (A, B), and wherein the first logic operation is different from the second logic operation. a first input (A) and a second input (B); a first memristor (M 1 ), a second memristor (M 2 ), a third memristor (M 3 ), and a fourth memristor (M 4 ), each memristor having a positive terminal and a negative terminal; and a first output and a second output , wherein the negative terminal of the first memristor (M 1 ) and the positive terminal of the second memristor (M 2 ) are connected in common to the first input (A), wherein the negative terminal of the third memristor (M 3 ) and the positive terminal of the fourth memristor (M 4 ) are connected in common to the second input (B), wherein the negative terminal of the second memristor (M 2 ) and the negative terminal of the fourth memristor (M 4 ) are connected in common to the first output , wherein the positive terminal of the first memristor (M 1 ) and the positive terminal of the third memristor (M 3 ) are connected in common to the second output , further comprising a transistor (NMOST, PMOST, T), wherein the gate of the transistor is connected to one of the first and second outputs , wherein the drain of the transistor is connected to the other of the first and second outputs , and wherein the source of the transistor is connected to a positive or negative supply voltage or ground, and wherein, in use, the voltage of the first output , corresponds to the result of a first logic operation relative to voltages applied to the first and second inputs (A, B), and the voltage of the second output , corresponds to the result of a second logic operation relative to voltages applied to the first and second inputs (A, B), and wherein the first logic operation is different from the second logic operation. <EOS>