A multilayer printed circuit board, having a first dielectric layer with a first surface and an opposite second surface, a second dielectric layer with a first surface and an opposite second surface, separate from the first dielectric layer, at least one core layer or sub-composite structure interposed between the first dielectric layer and the second dielectric layer, and a first plating resist selectively positioned flush with the first surface of the first dielectric layer and within the first dielectric layer, a first plurality of conductive and dielectric layers (1512a, 1606a/1612a, 1706a/1712a, 2006a/2012a, 2806a/2812a) coupled to the first dielectric layer opposite the at least one core layer, or sub-composite structure, and a second plurality of conductive and dielectric layers (1512c, 1612b/1606d, 1714b/1706e, 1814b/1806e, 2012c/2006d, 2812c/2806d) coupled to the second dielectric layer opposite the at least one core layer or sub-composite structure, a second plating resist selectively positioned flush with the second surface of the first dielectric layer and within the first dielectric layer or flush with the second surface of the second dielectric layer and within the second dielectric layer, the second plating resist disposed inline with the first plating resist along a thickness of the printed circuit board but separate from the first plating resist; and a through hole extending through the first plurality of conductive and dielectric layers, the first dielectric layer, the first plating resist, the at least one core layer or sub-composite structure, the second plating resist, the second dielectric layer, and the second plurality of conductive and dielectric layers, where an interior surface of the through hole is plated with a conductive material except along a length between the first plating resist and the second plating resist to form a partitioned plated through hole having a first via segment electrically isolated from a second via segment . a first plating resist selectively positioned flush with the first surface of the first dielectric layer and within the first dielectric layer, a first plurality of conductive and dielectric layers (1512a, 1606a/1612a, 1706a/1712a, 2006a/2012a, 2806a/2812a) coupled to the first dielectric layer opposite the at least one core layer, or sub-composite structure, and a second plurality of conductive and dielectric layers (1512c, 1612b/1606d, 1714b/1706e, 1814b/1806e, 2012c/2006d, 2812c/2806d) coupled to the second dielectric layer opposite the at least one core layer or sub-composite structure, a second plating resist selectively positioned flush with the second surface of the first dielectric layer and within the first dielectric layer or flush with the second surface of the second dielectric layer and within the second dielectric layer, the second plating resist disposed inline with the first plating resist along a thickness of the printed circuit board but separate from the first plating resist; and a through hole extending through the first plurality of conductive and dielectric layers, the first dielectric layer, the first plating resist, the at least one core layer or sub-composite structure, the second plating resist, the second dielectric layer, and the second plurality of conductive and dielectric layers, where an interior surface of the through hole is plated with a conductive material except along a length between the first plating resist and the second plating resist to form a partitioned plated through hole having a first via segment electrically isolated from a second via segment . <EOS>