A memory system , comprising: an array of memory cells arranged in rows and columns; a row decoder for receiving a row address component and asserting one of a plurality of word lines comprising 32 or more word lines, each word line coupled to a row in the array; and a hierarchical ROM encoder system , comprising: a first ROM encoder for receiving the plurality of word lines and generating a first output; a first logic block for receiving the plurality of word lines and generating a plurality of first logic block outputs, the first logic block comprising a plurality of logic gates, each logic gate being connected to a plurality of word lines and generating a corresponding first logic block output; a second ROM encoder for receiving the plurality of first logic block outputs and generating a second output, the second ROM encoder comprising a plurality of rows, each row associated with one of the plurality of first logic block outputs; a first comparator for comparing the first output and a first part of the row address component; a second comparator for comparing the second output and a second part of the row address component; and a gate for generating a row address fault detection signal based on an output from the first comparator and an output from the second comparator. an array of memory cells arranged in rows and columns; a row decoder for receiving a row address component and asserting one of a plurality of word lines comprising 32 or more word lines, each word line coupled to a row in the array; and a hierarchical ROM encoder system , comprising: a first ROM encoder for receiving the plurality of word lines and generating a first output; a first logic block for receiving the plurality of word lines and generating a plurality of first logic block outputs, the first logic block comprising a plurality of logic gates, each logic gate being connected to a plurality of word lines and generating a corresponding first logic block output; a second ROM encoder for receiving the plurality of first logic block outputs and generating a second output, the second ROM encoder comprising a plurality of rows, each row associated with one of the plurality of first logic block outputs; a first comparator for comparing the first output and a first part of the row address component; a second comparator for comparing the second output and a second part of the row address component; and a gate for generating a row address fault detection signal based on an output from the first comparator and an output from the second comparator. a first ROM encoder for receiving the plurality of word lines and generating a first output; a first logic block for receiving the plurality of word lines and generating a plurality of first logic block outputs, the first logic block comprising a plurality of logic gates, each logic gate being connected to a plurality of word lines and generating a corresponding first logic block output; a second ROM encoder for receiving the plurality of first logic block outputs and generating a second output, the second ROM encoder comprising a plurality of rows, each row associated with one of the plurality of first logic block outputs; a first comparator for comparing the first output and a first part of the row address component; a second comparator for comparing the second output and a second part of the row address component; and a gate for generating a row address fault detection signal based on an output from the first comparator and an output from the second comparator. <EOS>