A processor, comprising: a memory architecture having M-number of processing elements each having at least N-number of processing units and a local memory , wherein M, N comprising integers greater than 1 and the memory architecture comprising: a first processing element of the M-number of processing elements comprising: a first set of N-number of processing units configured to perform a computing operation, and a first local memory configured to store data capable of being utilized by the N-number of processing units ; characterized in the memory architecture further comprising a centralized data hub capable of receiving data from the M-number of processing elements and capable of providing shared data from one of the M-number of processing elements to other processing elements of the M-number of processing elements , the centralized data hub configured to distribute shared data to at least one or more of the M-number of processing elements , wherein the first processing element is coupled to the centralized data hub , and the first processing element is configured to: acquire shared data from the centralized data hub ; acquire private data local to the first processing element; store the private data in the first local memory of the first processing element; provide the shared data and the stored private data as operands to one or more processing units of the first processing element; and generate one or more results from one or more operations performed by corresponding one or more processing units . a first processing element of the M-number of processing elements comprising: a first set of N-number of processing units configured to perform a computing operation, and a first local memory configured to store data capable of being utilized by the N-number of processing units ; characterized in the memory architecture further comprising a first set of N-number of processing units configured to perform a computing operation, and a first local memory configured to store data capable of being utilized by the N-number of processing units ; characterized in the memory architecture further comprising a centralized data hub capable of receiving data from the M-number of processing elements and capable of providing shared data from one of the M-number of processing elements to other processing elements of the M-number of processing elements , the centralized data hub configured to distribute shared data to at least one or more of the M-number of processing elements , wherein the first processing element is coupled to the centralized data hub , and the first processing element is configured to: acquire shared data from the centralized data hub ; acquire private data local to the first processing element; store the private data in the first local memory of the first processing element; provide the shared data and the stored private data as operands to one or more processing units of the first processing element; and generate one or more results from one or more operations performed by corresponding one or more processing units . acquire shared data from the centralized data hub ; acquire private data local to the first processing element; store the private data in the first local memory of the first processing element; provide the shared data and the stored private data as operands to one or more processing units of the first processing element; and generate one or more results from one or more operations performed by corresponding one or more processing units . <EOS>