A method for multiplying matrices, comprising the following steps: a) storing a first source matrix (a) in row-major format in a shared memory, whereby consecutive elements of a row of the first source matrix are stored at consecutive memory addresses; b) storing a second source matrix (b) in column-maj or format in the shared memory, whereby consecutive elements of a column of the second source matrix are stored at consecutive memory addresses; c) in a single transfer cycle from the shared memory to processor registers through an N-bit memory bus: - reading an N-bit word in one of the first and second source matrixes; - writing K consecutive segments of the N-bit word at a designated position in K respective N-bit registers (V), K being such that N is divisible by K; d) performing step c) for K = R different rows of the first source matrix (a) so as to fill R first registers (VA), whereby each of the R first registers (VA0-VA3) contains a different submatrix (A) of R rows of N/R bits organized in R consecutive segments (A0j-A3j) of the register; e) performing step c) for K = Q different columns of the second source matrix (b) so as to fill Q second registers (VB), whereby each of the Q second registers (VB0-VB3) contains a different submatrix (B) of Q columns of N/Q bits organized in Q consecutive segments (Bi0-Bi3) of the register; and f) in response to the execution of a submatrix multiply machine instruction designating as first operand (VA0) one of the R first registers and as second operand (VB0) one of the Q second registers, carrying out in parallel, using a dedicated hardware operator (DP4A), a scalar product of each segment (A0j-A3j) of the first operand register by each segment of the second operand register (Bi0-Bi3), the segments of the operand registers being regarded as vectors. a) storing a first source matrix (a) in row-major format in a shared memory, whereby consecutive elements of a row of the first source matrix are stored at consecutive memory addresses; b) storing a second source matrix (b) in column-maj or format in the shared memory, whereby consecutive elements of a column of the second source matrix are stored at consecutive memory addresses; c) in a single transfer cycle from the shared memory to processor registers through an N-bit memory bus: - reading an N-bit word in one of the first and second source matrixes; - writing K consecutive segments of the N-bit word at a designated position in K respective N-bit registers (V), K being such that N is divisible by K; - reading an N-bit word in one of the first and second source matrixes; - writing K consecutive segments of the N-bit word at a designated position in K respective N-bit registers (V), K being such that N is divisible by K; d) performing step c) for K = R different rows of the first source matrix (a) so as to fill R first registers (VA), whereby each of the R first registers (VA0-VA3) contains a different submatrix (A) of R rows of N/R bits organized in R consecutive segments (A0j-A3j) of the register; e) performing step c) for K = Q different columns of the second source matrix (b) so as to fill Q second registers (VB), whereby each of the Q second registers (VB0-VB3) contains a different submatrix (B) of Q columns of N/Q bits organized in Q consecutive segments (Bi0-Bi3) of the register; and f) in response to the execution of a submatrix multiply machine instruction designating as first operand (VA0) one of the R first registers and as second operand (VB0) one of the Q second registers, carrying out in parallel, using a dedicated hardware operator (DP4A), a scalar product of each segment (A0j-A3j) of the first operand register by each segment of the second operand register (Bi0-Bi3), the segments of the operand registers being regarded as vectors. <EOS>