A frequency divider circuit comprising: a first frequency dividing circuit configured to divide a first clock signal (ICKI) to generate a first frequency-divided clock signal (WCKI) ; a second frequency dividing circuit configured to divide a second clock signal (ICKQ) having the same frequency as the first clock signal (ICKI) and having a first phase difference with respect to the first clock signal (ICKI) to generate a second frequency-divided clock signal (WCKQ); a detection circuit configured to detect a phase relationship between the first frequency-divided clock signal (WCKI) and the second frequency-divided clock signal (WCKQ); and a first selection circuit configured to select and output, as a frequency-divided clock signal (OCKQ), one of the second frequency-divided clock signal (WCKQ) and an inverted signal (WCKQX) of the second frequency-divided clock signal which are generated by the second frequency dividing circuit , based on the phase relationship detected by the detection circuit , characterised in that the detection circuit includes a first latch circuit having a data input into which the first frequency-divided clock signal (WCKI) is inputted and a second latch circuit having a data input into which an output signal from a data output of the first latch circuit is inputted, and the first latch circuit and the second latch circuit are driven based on an output signal (WCKQQ) of the second frequency dividing circuit to output an output signal (MONOUT) from a data output of the second latch circuit as a signal indicating the phase relationship between the first frequency-divided clock signal (WCKI) and the second frequency-divided clock signal (WCKQ). a first frequency dividing circuit configured to divide a first clock signal (ICKI) to generate a first frequency-divided clock signal (WCKI) ; a second frequency dividing circuit configured to divide a second clock signal (ICKQ) having the same frequency as the first clock signal (ICKI) and having a first phase difference with respect to the first clock signal (ICKI) to generate a second frequency-divided clock signal (WCKQ); a detection circuit configured to detect a phase relationship between the first frequency-divided clock signal (WCKI) and the second frequency-divided clock signal (WCKQ); and a first selection circuit configured to select and output, as a frequency-divided clock signal (OCKQ), one of the second frequency-divided clock signal (WCKQ) and an inverted signal (WCKQX) of the second frequency-divided clock signal which are generated by the second frequency dividing circuit , based on the phase relationship detected by the detection circuit , characterised in that the detection circuit includes a first latch circuit having a data input into which the first frequency-divided clock signal (WCKI) is inputted and a second latch circuit having a data input into which an output signal from a data output of the first latch circuit is inputted, and the first latch circuit and the second latch circuit are driven based on an output signal (WCKQQ) of the second frequency dividing circuit to output an output signal (MONOUT) from a data output of the second latch circuit as a signal indicating the phase relationship between the first frequency-divided clock signal (WCKI) and the second frequency-divided clock signal (WCKQ). <EOS>