An apparatus comprising: processing circuitry to process vector instructions for which at least one of a source operand and a result value is a vector value comprising a plurality of data elements; wherein in response to a given vector instruction, the processing circuitry is configured to perform a plurality of beats of processing, each beat comprising processing corresponding to a portion of the vector value; the processing circuitry is configured to set beat status information indicative of which beats of a plurality of vector instructions including said given vector instruction and a subsequent vector instruction have completed; wherein an encoding of the beat status information identifies a first number of completed beats of said given vector instruction and a second number of completed beats of the subsequent vector instruction in the plurality of vector instructions, wherein both the first number and the second number are variable and both the first number and the second number are identified by the encoding of the beat status information; in response to an event, the processing circuitry is configured to suspend processing of said plurality of vector instructions; and in response to a return-from-event request indicating a return to processing of said given vector instruction, the processing circuitry is configured to resume processing of said plurality of vector instructions while suppressing the beats of said plurality of vector instructions indicated by said beat status information as having completed; wherein the vector value comprises data elements having one of a plurality of data element sizes specified by data element size information accessible to the processing circuitry; and each beat of processing comprises processing corresponding to a fixed size portion of the vector value, irrespective of the data element size indicated by said data element size information. processing circuitry to process vector instructions for which at least one of a source operand and a result value is a vector value comprising a plurality of data elements; wherein in response to a given vector instruction, the processing circuitry is configured to perform a plurality of beats of processing, each beat comprising processing corresponding to a portion of the vector value; the processing circuitry is configured to set beat status information indicative of which beats of a plurality of vector instructions including said given vector instruction and a subsequent vector instruction have completed; wherein an encoding of the beat status information identifies a first number of completed beats of said given vector instruction and a second number of completed beats of the subsequent vector instruction in the plurality of vector instructions, wherein both the first number and the second number are variable and both the first number and the second number are identified by the encoding of the beat status information; in response to an event, the processing circuitry is configured to suspend processing of said plurality of vector instructions; and in response to a return-from-event request indicating a return to processing of said given vector instruction, the processing circuitry is configured to resume processing of said plurality of vector instructions while suppressing the beats of said plurality of vector instructions indicated by said beat status information as having completed; wherein the vector value comprises data elements having one of a plurality of data element sizes specified by data element size information accessible to the processing circuitry; and each beat of processing comprises processing corresponding to a fixed size portion of the vector value, irrespective of the data element size indicated by said data element size information. <EOS>