An image sensor comprising: a substrate comprising a plurality of pixel regions (PX), the substrate having a first surface , a second surface opposite the first surface , and a first trench (TR1) recessed from the first surface ; a shallow device isolation pattern provided in the first trench (TR1); and a deep device isolation pattern provided in the substrate between pixel regions (PX) of the plurality of pixel regions (PX), wherein the deep device isolation pattern is disposed in a second trench (TR2) that penetrates the shallow device isolation pattern and extends into the substrate towards the second surface , wherein the deep device isolation pattern comprises a semiconductor pattern penetrating at least a portion of the substrate , and an isolation pattern (IP) provided between the substrate and the semiconductor pattern , wherein the semiconductor pattern fills a lower portion of the second trench (TR2), wherein the isolation pattern (IP) comprises a first isolation pattern adjacent to the second surface of the substrate , and a second isolation pattern adjacent to the first surface of the substrate , wherein a first interface (IF1) at which the first isolation pattern contacts the second isolation pattern is spaced apart from the shallow device isolation pattern , wherein the first isolation pattern comprises a first material, and the second isolation pattern comprises a second material that is different from the first material, wherein the deep device isolation pattern further comprises an insulating pattern disposed on the semiconductor pattern and penetrating the shallow device isolation pattern , wherein the insulating pattern fills an upper portion of the second trench (TR2), and wherein the isolation pattern (IP) extends between the shallow device isolation pattern and the insulating pattern . a substrate comprising a plurality of pixel regions (PX), the substrate having a first surface , a second surface opposite the first surface , and a first trench (TR1) recessed from the first surface ; a shallow device isolation pattern provided in the first trench (TR1); and a deep device isolation pattern provided in the substrate between pixel regions (PX) of the plurality of pixel regions (PX), wherein the deep device isolation pattern is disposed in a second trench (TR2) that penetrates the shallow device isolation pattern and extends into the substrate towards the second surface , wherein the deep device isolation pattern comprises a semiconductor pattern penetrating at least a portion of the substrate , and an isolation pattern (IP) provided between the substrate and the semiconductor pattern , wherein the semiconductor pattern fills a lower portion of the second trench (TR2), wherein the isolation pattern (IP) comprises a first isolation pattern adjacent to the second surface of the substrate , and a second isolation pattern adjacent to the first surface of the substrate , wherein a first interface (IF1) at which the first isolation pattern contacts the second isolation pattern is spaced apart from the shallow device isolation pattern , wherein the first isolation pattern comprises a first material, and the second isolation pattern comprises a second material that is different from the first material, wherein the deep device isolation pattern further comprises an insulating pattern disposed on the semiconductor pattern and penetrating the shallow device isolation pattern , wherein the insulating pattern fills an upper portion of the second trench (TR2), and wherein the isolation pattern (IP) extends between the shallow device isolation pattern and the insulating pattern . <EOS>