A semiconductor device comprising: a first memory mat and a second memory mat each including a plurality of rows, each row including a plurality of split gate type memory cells; each row comprising a first control gate line (CGL) connected to a control gate (CG) of the row of the split gate type memory cells in the first memory mat; a second control gate line (CGR) connected to a control gate (CG) of the row of the split gate type memory cells in the second memory mat; a first memory gate line connected to a memory gate (MG) of the row of the split gate type memory cells in the first memory mat; a second memory gate line connected to a memory gate (MG) of the row of the split gate type memory cells in the second memory mat; a first CG driver configured to drive the first control gate line; a second CG driver configured to drive the second control gate line; at least one MG driver configured to drive the first memory gate line and the second memory gate line; wherein the first CG driver and the second CG driver are disposed between the first memory mat and the second memory mat; and wherein the at least one MG driver is disposed outside a region containing both the first memory mat and the second memory mat; characterized by a single MG driver circuit comprising a plurality of the at least one MG drivers of each row, each MG driver being configured to drive both the first memory gate line and the second memory gate line of that row; wherein the single MG driver circuit is disposed outside the region at a position adjacent to the first memory mat; and wherein the semiconductor device comprises a switch circuit for connecting or disconnecting the first memory gate lines and the second memory gate lines. a first memory mat and a second memory mat each including a plurality of rows, each row including a plurality of split gate type memory cells; each row comprising a first control gate line (CGL) connected to a control gate (CG) of the row of the split gate type memory cells in the first memory mat; a second control gate line (CGR) connected to a control gate (CG) of the row of the split gate type memory cells in the second memory mat; a first memory gate line connected to a memory gate (MG) of the row of the split gate type memory cells in the first memory mat; a second memory gate line connected to a memory gate (MG) of the row of the split gate type memory cells in the second memory mat; a first CG driver configured to drive the first control gate line; a second CG driver configured to drive the second control gate line; at least one MG driver configured to drive the first memory gate line and the second memory gate line; wherein the first CG driver and the second CG driver are disposed between the first memory mat and the second memory mat; and wherein the at least one MG driver is disposed outside a region containing both the first memory mat and the second memory mat; characterized by a single MG driver circuit comprising a plurality of the at least one MG drivers of each row, each MG driver being configured to drive both the first memory gate line and the second memory gate line of that row; wherein the single MG driver circuit is disposed outside the region at a position adjacent to the first memory mat; and wherein the semiconductor device comprises a switch circuit for connecting or disconnecting the first memory gate lines and the second memory gate lines. <EOS>