A processor comprising: a decoding unit that decodes an instruction; an address generating unit that includes an information register storing control information, and when the instruction decoded by the decoding unit is a Single Instruction Multiple Vector operation instruction to execute arithmetic processing on a plurality of vector operand sets each including a plurality of operands that are objects of the arithmetic processing, in parallel a plurality of times, generates an address set corresponding to each of the plurality of operands included in each of the plurality of operand sets of the arithmetic processing for each time, based on information regarding the first instruction received from the decoding unit and a certain address displacement with respect to the plurality of operands included in each of the plurality of operand sets, the certain address displacement being obtained with reference to control information stored in the information register ; a plurality of address holding units (303-1 to 303-4) that hold the address sets corresponding to each of the plurality of operand sets, that are generated by the address generating unit , with an operation code instructing the type of the arithmetic processing in correspondence to respective processing units (102-1 to 102-4); and a plurality of processing units (102-1 to 102-4) that perform the arithmetic processing instructed by the operation code in parallel on the plurality of operand sets obtained based on the address sets output From the plurality of address holding units selected by round-robin, wherein the plurality of address holding units (303-1 to 303-4) hold the address sets and the operation code so as to correspond to each of the plurality of processing units (102-1 to 102-4). a decoding unit that decodes an instruction; an address generating unit that includes an information register storing control information, and when the instruction decoded by the decoding unit is a Single Instruction Multiple Vector operation instruction to execute arithmetic processing on a plurality of vector operand sets each including a plurality of operands that are objects of the arithmetic processing, in parallel a plurality of times, generates an address set corresponding to each of the plurality of operands included in each of the plurality of operand sets of the arithmetic processing for each time, based on information regarding the first instruction received from the decoding unit and a certain address displacement with respect to the plurality of operands included in each of the plurality of operand sets, the certain address displacement being obtained with reference to control information stored in the information register ; a plurality of address holding units (303-1 to 303-4) that hold the address sets corresponding to each of the plurality of operand sets, that are generated by the address generating unit , with an operation code instructing the type of the arithmetic processing in correspondence to respective processing units (102-1 to 102-4); and a plurality of processing units (102-1 to 102-4) that perform the arithmetic processing instructed by the operation code in parallel on the plurality of operand sets obtained based on the address sets output From the plurality of address holding units selected by round-robin, wherein the plurality of address holding units (303-1 to 303-4) hold the address sets and the operation code so as to correspond to each of the plurality of processing units (102-1 to 102-4). <EOS>