A method for packaging a chip, comprising: providing (S101) a wafer , wherein the wafer comprises a first surface and a second surface that are opposite to each other, at least two functional circuit regions and a plurality of bonding pads are formed on the first surface, and the plurality of bonding pads are located around each of the at least two functional circuit regions; forming (S102) a passivation layer on each of the plurality of bonding pads , wherein the passivation layer comprises a center region and a peripheral region surrounding the center region; forming (S103) a first metal bonding layer on the passivation layer , wherein the first metal bonding layer covers the peripheral region of the passivation layer ; providing (S104) a substrate , wherein the substrate comprises a third surface and a fourth surface that are opposite to each other, a second metal bonding layer and a first shielding layer are formed on the third surface, the second metal bonding layer is configured to be bonded with the first metal bonding layer , the first shielding layer is configured to cover a surface of the substrate facing the wafer and to face the at least two functional circuit regions after the wafer and the substrate are bonded, and the first shielding layer is in contact with the second metal bonding layer ; bonding (S105) the first metal bonding layer with the second metal bonding layer , wherein at least a part of the center region is not covered by the second metal bonding layer , and the third surface is attached to a surface of the passivation layer away from the wafer after the bonding; performing (S106) half-cutting from the second surface of the wafer toward the substrate , to form a cutting groove exposing at least the first metal bonding layer ; and forming (S107) a second shielding layer on the second surface of the wafer and in the cutting groove , wherein the second shielding layer is electrically connected to the first metal bonding layer . providing (S101) a wafer , wherein the wafer comprises a first surface and a second surface that are opposite to each other, at least two functional circuit regions and a plurality of bonding pads are formed on the first surface, and the plurality of bonding pads are located around each of the at least two functional circuit regions; forming (S102) a passivation layer on each of the plurality of bonding pads , wherein the passivation layer comprises a center region and a peripheral region surrounding the center region; forming (S103) a first metal bonding layer on the passivation layer , wherein the first metal bonding layer covers the peripheral region of the passivation layer ; providing (S104) a substrate , wherein the substrate comprises a third surface and a fourth surface that are opposite to each other, a second metal bonding layer and a first shielding layer are formed on the third surface, the second metal bonding layer is configured to be bonded with the first metal bonding layer , the first shielding layer is configured to cover a surface of the substrate facing the wafer and to face the at least two functional circuit regions after the wafer and the substrate are bonded, and the first shielding layer is in contact with the second metal bonding layer ; bonding (S105) the first metal bonding layer with the second metal bonding layer , wherein at least a part of the center region is not covered by the second metal bonding layer , and the third surface is attached to a surface of the passivation layer away from the wafer after the bonding; performing (S106) half-cutting from the second surface of the wafer toward the substrate , to form a cutting groove exposing at least the first metal bonding layer ; and forming (S107) a second shielding layer on the second surface of the wafer and in the cutting groove , wherein the second shielding layer is electrically connected to the first metal bonding layer . <EOS>