A method for programming in a non-volatile memory device , comprising: applying at least one programming pulse to a non-volatile memory cell (C) of the non-volatile memory device during each of previous programming loops; applying at least one programming pulse to the non-volatile memory cell (C) during a current programming loop; providing a bitline bias voltage of the non-volatile memory cell (C) according to a result of comparing a threshold voltage (Vt) of the non-volatile memory cell (C) in at least one of the previous programming loops with a low verify level (VL) and/or a high verify level (VH) of a target data state of the non-volatile memory cell (C) and a result of comparing a threshold voltage (Vt) of the non-volatile memory cell (C) in the current programming loop with the low verify level (VL) and/or the high verify level (VH) of the target data state of the non-volatile memory cell characterised in that the method is further comprising : if the threshold voltage (Vt) is higher than the high verify level (VH) of the target data state of the non-volatile memory cell (C) in any of the previous programming loops and the threshold voltage (Vt) is higher than the high verify level (VH) of the target data state of the non-volatile memory cell (C) in the current programming loop, providing a system voltage (Vdd) as the bitline bias voltage permanently; and applying at least one programming pulse to the non-volatile memory cell (C) during a next programming loop after the current programming loop if number of non-volatile memory cells (C) having threshold voltage (Vt)s higher than the high verify level (VH) is lower than a predetermined number after performing the current programming loop. applying at least one programming pulse to a non-volatile memory cell (C) of the non-volatile memory device during each of previous programming loops; applying at least one programming pulse to the non-volatile memory cell (C) during a current programming loop; providing a bitline bias voltage of the non-volatile memory cell (C) according to a result of comparing a threshold voltage (Vt) of the non-volatile memory cell (C) in at least one of the previous programming loops with a low verify level (VL) and/or a high verify level (VH) of a target data state of the non-volatile memory cell (C) and a result of comparing a threshold voltage (Vt) of the non-volatile memory cell (C) in the current programming loop with the low verify level (VL) and/or the high verify level (VH) of the target data state of the non-volatile memory cell characterised in that the method is further comprising : if the threshold voltage (Vt) is higher than the high verify level (VH) of the target data state of the non-volatile memory cell (C) in any of the previous programming loops and the threshold voltage (Vt) is higher than the high verify level (VH) of the target data state of the non-volatile memory cell (C) in the current programming loop, providing a system voltage (Vdd) as the bitline bias voltage permanently; and applying at least one programming pulse to the non-volatile memory cell (C) during a next programming loop after the current programming loop if number of non-volatile memory cells (C) having threshold voltage (Vt)s higher than the high verify level (VH) is lower than a predetermined number after performing the current programming loop. <EOS>