A voltage level shifter circuit comprising: an input node to receive an input signal in a first voltage domain; a data node to hold a logic state of the input signal for generation of an output signal that corresponds to the input signal and is in a second voltage domain; a data bar node to hold a logic state of an input bar signal that is the inverse of the input signal; and a keeper transistor having a source terminal coupled to the data node , a gate terminal coupled to the data bar node, and a drain terminal to receive the input bar signal, wherein the keeper transistor is a first keeper transistor (MN3), and wherein the circuit further comprises a second keeper transistor (MN4) having a source terminal coupled to the data bar node, a gate terminal coupled to the data node , and a drain terminal to receive a delayed version of the input signal and further comprising: a first firewall transistor (MN5) coupled between the first keeper transistor (MN3) and a ground terminal; and a second firewall transistor (MN6) coupled between the second keeper (MN4) transistor and the ground terminal, wherein a gate terminal of the second firewall transistor (MN6) is coupled to a gate terminal of the first firewall transistor (MN5), and wherein the gate terminals of the first and second firewall transistors (MN5, MN6) are to receive a firewall signal to selectively drive the data node and the data bar node to 0 Volts when the first voltage domain is power gated. an input node to receive an input signal in a first voltage domain; a data node to hold a logic state of the input signal for generation of an output signal that corresponds to the input signal and is in a second voltage domain; a data bar node to hold a logic state of an input bar signal that is the inverse of the input signal; and a keeper transistor having a source terminal coupled to the data node , a gate terminal coupled to the data bar node, and a drain terminal to receive the input bar signal, wherein the keeper transistor is a first keeper transistor (MN3), and wherein the circuit further comprises a second keeper transistor (MN4) having a source terminal coupled to the data bar node, a gate terminal coupled to the data node , and a drain terminal to receive a delayed version of the input signal and further comprising: a first firewall transistor (MN5) coupled between the first keeper transistor (MN3) and a ground terminal; and a second firewall transistor (MN6) coupled between the second keeper (MN4) transistor and the ground terminal, wherein a gate terminal of the second firewall transistor (MN6) is coupled to a gate terminal of the first firewall transistor (MN5), and wherein the gate terminals of the first and second firewall transistors (MN5, MN6) are to receive a firewall signal to selectively drive the data node and the data bar node to 0 Volts when the first voltage domain is power gated. a first firewall transistor (MN5) coupled between the first keeper transistor (MN3) and a ground terminal; and a second firewall transistor (MN6) coupled between the second keeper (MN4) transistor and the ground terminal, wherein a gate terminal of the second firewall transistor (MN6) is coupled to a gate terminal of the first firewall transistor (MN5), and wherein the gate terminals of the first and second firewall transistors (MN5, MN6) are to receive a firewall signal to selectively drive the data node and the data bar node to 0 Volts when the first voltage domain is power gated. <EOS>