A pixel array , comprising: a first pixel circuit located in a first row and a first column of said pixel array; and a second pixel circuit located in a second row and a second column of said pixel array, characterized by said first and second pixel circuits sharing a dual conversion gain / high dynamic range (DCG/HDR) circuitry, wherein said shared DCG/HDR circuitry comprises: a high dynamic range circuit located in said second row and said second column of the pixel array; a dual conversion gain circuit located in said second row and said second column of the pixel array, said dual conversion gain circuit being coupled to a first floating diffusion region of the first pixel circuit located in the first row and the first column; and a control line coupled to the high dynamic range circuit and the dual conversion gain circuit for providing control signals to control both the high dynamic range circuit and the dual conversion gain circuit , wherein, when said control line is enabled, a charge of the first floating diffusion region located in the first row and the first column is read out and stored in a capacitor of the dual conversion gain circuit located in the second row and the second column. a first pixel circuit located in a first row and a first column of said pixel array; and a second pixel circuit located in a second row and a second column of said pixel array, characterized by said first and second pixel circuits sharing a dual conversion gain / high dynamic range (DCG/HDR) circuitry, wherein said shared DCG/HDR circuitry comprises: a high dynamic range circuit located in said second row and said second column of the pixel array; a dual conversion gain circuit located in said second row and said second column of the pixel array, said dual conversion gain circuit being coupled to a first floating diffusion region of the first pixel circuit located in the first row and the first column; and a control line coupled to the high dynamic range circuit and the dual conversion gain circuit for providing control signals to control both the high dynamic range circuit and the dual conversion gain circuit , wherein, when said control line is enabled, a charge of the first floating diffusion region located in the first row and the first column is read out and stored in a capacitor of the dual conversion gain circuit located in the second row and the second column. a high dynamic range circuit located in said second row and said second column of the pixel array; a dual conversion gain circuit located in said second row and said second column of the pixel array, said dual conversion gain circuit being coupled to a first floating diffusion region of the first pixel circuit located in the first row and the first column; and a control line coupled to the high dynamic range circuit and the dual conversion gain circuit for providing control signals to control both the high dynamic range circuit and the dual conversion gain circuit , wherein, when said control line is enabled, a charge of the first floating diffusion region located in the first row and the first column is read out and stored in a capacitor of the dual conversion gain circuit located in the second row and the second column. <EOS>