A quantum computing circuit comprising: a quantum RAM device for registering multiple input data in a quantum superposition state, wherein each input data is a string of n bits, and, wherein the quantum RAM device includes: a bus comprising a plurality n of bus qubits, each of the n bus qubits corresponding to a bit in the string of n bits; and a register qubit given to encode each input data of the multiple input data into a probability amplitude value; and wherein the quantum RAM device is configured, for each input data of the multiple input data, to: • apply a first controlled-bit-flip gate of the quantum RAM device, for performing controlled-bit-flip transform on the bus qubits in a first bus qubits state to output a second bus qubits state, wherein each bit of the input data controls the bit-flip transform of its corresponding bus qubit; • apply a controlled rotation gate of the quantum RAM device, for probability amplitude adjustment of a quantum superposition state given as a tensor product of a bus qubits state and a register qubit state, wherein the bus qubits in the second bus qubits state control the controlled rotation gate to rotate the register qubit in a first register qubit state, to output a second register qubit state and a third bus qubits state and • apply a second controlled-bit-flip gate of the quantum RAM device, for performing controlled-bit-flip transform on the bus qubits in the third bus qubits state to output a fourth bus qubits state, wherein each bit of the input data controls the bit-flip transform of its corresponding bus qubit. a bus comprising a plurality n of bus qubits, each of the n bus qubits corresponding to a bit in the string of n bits; and a register qubit given to encode each input data of the multiple input data into a probability amplitude value; and wherein the quantum RAM device is configured, for each input data of the multiple input data, to: • apply a first controlled-bit-flip gate of the quantum RAM device, for performing controlled-bit-flip transform on the bus qubits in a first bus qubits state to output a second bus qubits state, wherein each bit of the input data controls the bit-flip transform of its corresponding bus qubit; • apply a controlled rotation gate of the quantum RAM device, for probability amplitude adjustment of a quantum superposition state given as a tensor product of a bus qubits state and a register qubit state, wherein the bus qubits in the second bus qubits state control the controlled rotation gate to rotate the register qubit in a first register qubit state, to output a second register qubit state and a third bus qubits state and • apply a second controlled-bit-flip gate of the quantum RAM device, for performing controlled-bit-flip transform on the bus qubits in the third bus qubits state to output a fourth bus qubits state, wherein each bit of the input data controls the bit-flip transform of its corresponding bus qubit. • apply a first controlled-bit-flip gate of the quantum RAM device, for performing controlled-bit-flip transform on the bus qubits in a first bus qubits state to output a second bus qubits state, wherein each bit of the input data controls the bit-flip transform of its corresponding bus qubit; • apply a controlled rotation gate of the quantum RAM device, for probability amplitude adjustment of a quantum superposition state given as a tensor product of a bus qubits state and a register qubit state, wherein the bus qubits in the second bus qubits state control the controlled rotation gate to rotate the register qubit in a first register qubit state, to output a second register qubit state and a third bus qubits state and • apply a second controlled-bit-flip gate of the quantum RAM device, for performing controlled-bit-flip transform on the bus qubits in the third bus qubits state to output a fourth bus qubits state, wherein each bit of the input data controls the bit-flip transform of its corresponding bus qubit. <EOS>