An image sensor, comprising: a pixel array including a plurality of pixel cells (110A-C, 410A, 410B) arranged into a plurality of rows (R1,..., Ry) and a plurality of columns (C1,..., Cx) of pixel cells in a first semiconductor die ; a plurality of pixel support circuits arranged in a second semiconductor die , wherein the first and second semiconductor dies are stacked and coupled together; a plurality of interconnect lines coupled between the first and second semiconductor dies, wherein each one of the plurality of pixel cells is coupled to a corresponding one of the plurality of pixel support circuits through a corresponding one of the plurality of interconnect lines; and a plurality of shield bumps disposed proximate to corners of the pixel cells and between the first and second semiconductor dies such that each one of the plurality of shield bumps is disposed between interconnect lines adjacent along a diagonal of the pixel array and is adapted to shield a coupling capacitance between said interconnect lines, the image sensor being characterized in that : no shield bump is disposed between interconnect lines adjacent in a same row of the pixel array so that there is a coupling capacitance between said adjacent interconnect lines in the same row of the pixel array, wherein the image sensor is configured so as to read out simultaneously, during a first read out pass, every other pixel cell in a row and every other pixel cell in an adjacent row through the corresponding interconnect lines, and to read out simultaneously, during a second read out pass, the remaining pixel cells of said two rows through the corresponding interconnect lines, wherein the pixel cells read out simultaneously are arranged along diagonals of the pixel array and a corresponding shield bump is disposed between each pair of adjacent interconnect lines coupled to the pixel cells read out simultaneously. a pixel array including a plurality of pixel cells (110A-C, 410A, 410B) arranged into a plurality of rows (R1,..., Ry) and a plurality of columns (C1,..., Cx) of pixel cells in a first semiconductor die ; a plurality of pixel support circuits arranged in a second semiconductor die , wherein the first and second semiconductor dies are stacked and coupled together; a plurality of interconnect lines coupled between the first and second semiconductor dies, wherein each one of the plurality of pixel cells is coupled to a corresponding one of the plurality of pixel support circuits through a corresponding one of the plurality of interconnect lines; and a plurality of shield bumps disposed proximate to corners of the pixel cells and between the first and second semiconductor dies such that each one of the plurality of shield bumps is disposed between interconnect lines adjacent along a diagonal of the pixel array and is adapted to shield a coupling capacitance between said interconnect lines, the image sensor being characterized in that : no shield bump is disposed between interconnect lines adjacent in a same row of the pixel array so that there is a coupling capacitance between said adjacent interconnect lines in the same row of the pixel array, wherein the image sensor is configured so as to read out simultaneously, during a first read out pass, every other pixel cell in a row and every other pixel cell in an adjacent row through the corresponding interconnect lines, and to read out simultaneously, during a second read out pass, the remaining pixel cells of said two rows through the corresponding interconnect lines, wherein the pixel cells read out simultaneously are arranged along diagonals of the pixel array and a corresponding shield bump is disposed between each pair of adjacent interconnect lines coupled to the pixel cells read out simultaneously. <EOS>