A memory device , comprising: a substrate ; an active area extending along a first direction on the substrate ; a gate line (WL1) traversing the active area and extending along a second direction that is not parallel to the first direction; a source doped region (S1) in the active area and on a first side of the gate line (WL1); a main source line (SLM1) extending along the first direction; a source line extension (SLE1) coupled to the main source line (SLM1) and extending along the second direction, wherein the main source line (SLM1) is electrically connected to the source doped region (S1) via the source line extension (SLE1); a drain doped region (D) in the active area and on a second side of the gate line (WL1) that is opposite to the first side; a data storage element (MS1, MS2) electrically coupled to the drain doped region (D), wherein the data storage element (MS1, MS2) comprises a magnetic tunneling junction, MTJ, element; a landing pad (MP1) disposed directly under the MTJ element, the MTJ element comprising a bottom electrode (BE1) that is electrically connected to the landing pad (MP1); a drain contact (C1) electrically connecting the landing pad (MP1) to the drain doped region (D); a first dielectric layer disposed on the substrate , wherein the landing pad (MP1) is disposed in the first dielectric layer and is situated in a first horizontal plane; and a second dielectric layer covering the first dielectric layer and the landing pad (MP1), wherein the MTJ element is disposed in the second dielectric layer , and wherein the main source line (SLM1) and the source line extension (SLE1) are situated in a second horizontal plane, wherein the second horizontal plane is lower than the first horizontal plane. a substrate ; an active area extending along a first direction on the substrate ; a gate line (WL1) traversing the active area and extending along a second direction that is not parallel to the first direction; a source doped region (S1) in the active area and on a first side of the gate line (WL1); a main source line (SLM1) extending along the first direction; a source line extension (SLE1) coupled to the main source line (SLM1) and extending along the second direction, wherein the main source line (SLM1) is electrically connected to the source doped region (S1) via the source line extension (SLE1); a drain doped region (D) in the active area and on a second side of the gate line (WL1) that is opposite to the first side; a data storage element (MS1, MS2) electrically coupled to the drain doped region (D), wherein the data storage element (MS1, MS2) comprises a magnetic tunneling junction, MTJ, element; a landing pad (MP1) disposed directly under the MTJ element, the MTJ element comprising a bottom electrode (BE1) that is electrically connected to the landing pad (MP1); a drain contact (C1) electrically connecting the landing pad (MP1) to the drain doped region (D); a first dielectric layer disposed on the substrate , wherein the landing pad (MP1) is disposed in the first dielectric layer and is situated in a first horizontal plane; and a second dielectric layer covering the first dielectric layer and the landing pad (MP1), wherein the MTJ element is disposed in the second dielectric layer , and wherein the main source line (SLM1) and the source line extension (SLE1) are situated in a second horizontal plane, wherein the second horizontal plane is lower than the first horizontal plane. <EOS>