An apparatus comprising: a substrate ; a first memory cell block including first memory cell strings (231 - 239) located over the substrate, and first data lines (270 0 , 271 0 , and 272 0 ) coupled to the first memory cell strings; a second memory cell block including second memory cell strings (231 - 239) located over the first memory cell block, and second data lines (270 0 , 271 0 , and 272 0 ) coupled to the second memory cell strings; first conductive paths (257 0 ) located over the substrate and coupled between the first data lines and buffer circuitry (220 - 221) of the apparatus; and second conductive paths (257 1 ) located over the substrate and coupled between the second data lines and the buffer circuitry, wherein no conductive path of the first and second conductive paths is shared by the first and second memory cell blocks; first word lines (250 0 , 251 0 , 252 0 , and 253 0 ) coupled to the first memory cells strings; second word lines (250 1 , 251 1 , 252 1 , and 253 1 ) coupled to the second memory cell strings, wherein the first memory cell block shares no word line with the second memory cell block; first transistors (T0), each of the first transistors coupled to a respective word line of the first word lines, the first transistors including a first common gate ; second transistors (T1), each of the second transistors coupled to a respective word line of the second word lines, the second transistors including a second common gate different from the first common gate; and a decoder , based on address information provided to the decoder during a memory operation of the apparatus, to either concurrently turn on the first and second transistors or turn on the first transistors and turn off the second transistors while the first transistors are turned on. a substrate ; a first memory cell block including first memory cell strings (231 - 239) located over the substrate, and first data lines (270 0 , 271 0 , and 272 0 ) coupled to the first memory cell strings; a second memory cell block including second memory cell strings (231 - 239) located over the first memory cell block, and second data lines (270 0 , 271 0 , and 272 0 ) coupled to the second memory cell strings; first conductive paths (257 0 ) located over the substrate and coupled between the first data lines and buffer circuitry (220 - 221) of the apparatus; and second conductive paths (257 1 ) located over the substrate and coupled between the second data lines and the buffer circuitry, wherein no conductive path of the first and second conductive paths is shared by the first and second memory cell blocks; first word lines (250 0 , 251 0 , 252 0 , and 253 0 ) coupled to the first memory cells strings; second word lines (250 1 , 251 1 , 252 1 , and 253 1 ) coupled to the second memory cell strings, wherein the first memory cell block shares no word line with the second memory cell block; first transistors (T0), each of the first transistors coupled to a respective word line of the first word lines, the first transistors including a first common gate ; second transistors (T1), each of the second transistors coupled to a respective word line of the second word lines, the second transistors including a second common gate different from the first common gate; and a decoder , based on address information provided to the decoder during a memory operation of the apparatus, to either concurrently turn on the first and second transistors or turn on the first transistors and turn off the second transistors while the first transistors are turned on. <EOS>