A circuit device comprising: means for receiving a clock signal at an input of a digital circuit device including a capacitive node ; means for selectively activating a voltage level adjustment element to throttle an electrical discharge path from the capacitive node to an electrical ground to prevent complete discharge of the capacitive node; means for asserting a power mode control enable signal to a control input of the voltage level adjustment element to activate a voltage level adjustment circuit in a first operating mode; and means for deasserting the power mode control enable signal to bypass the voltage level adjustment circuit in a second operating mode, wherein a voltage level at the capacitive node reduces a voltage swing of a signal at the capacitive node, such that the capacitive node discharges to a non-ground voltage level instead of to a ground voltage level, and wherein the voltage level adjustment element comprises a first transistor and a second transistor coupled in parallel between the capacitive node and an electrical ground, the first transistor including a first control terminal responsive to a power mode control enable input to selectively activate the voltage level adjustment element; wherein the second transistor comprises a second control terminal coupled to a programmable voltage level control circuit ; and wherein the programmable voltage level control circuit comprises: a p-channel transistor including a first terminal coupled to a voltage source, a second terminal coupled to the input, and a third terminal coupled to the second control terminal; and an n-channel transistor including a fourth terminal coupled to the third terminal; a fifth terminal coupled to the input; and a sixth terminal coupled to the capacitive node. means for receiving a clock signal at an input of a digital circuit device including a capacitive node ; means for selectively activating a voltage level adjustment element to throttle an electrical discharge path from the capacitive node to an electrical ground to prevent complete discharge of the capacitive node; means for asserting a power mode control enable signal to a control input of the voltage level adjustment element to activate a voltage level adjustment circuit in a first operating mode; and means for deasserting the power mode control enable signal to bypass the voltage level adjustment circuit in a second operating mode, wherein a voltage level at the capacitive node reduces a voltage swing of a signal at the capacitive node, such that the capacitive node discharges to a non-ground voltage level instead of to a ground voltage level, and wherein the voltage level adjustment element comprises a first transistor and a second transistor coupled in parallel between the capacitive node and an electrical ground, the first transistor including a first control terminal responsive to a power mode control enable input to selectively activate the voltage level adjustment element; wherein the second transistor comprises a second control terminal coupled to a programmable voltage level control circuit ; and wherein the programmable voltage level control circuit comprises: a p-channel transistor including a first terminal coupled to a voltage source, a second terminal coupled to the input, and a third terminal coupled to the second control terminal; and an n-channel transistor including a fourth terminal coupled to the third terminal; a fifth terminal coupled to the input; and a sixth terminal coupled to the capacitive node. a p-channel transistor including a first terminal coupled to a voltage source, a second terminal coupled to the input, and a third terminal coupled to the second control terminal; and an n-channel transistor including a fourth terminal coupled to the third terminal; a fifth terminal coupled to the input; and a sixth terminal coupled to the capacitive node. <EOS>