A memory system , comprising: plurality of electronic chassis, each electronic chassis further comprising: a plurality of controllers , each controller operable to receive a block of data from a user and compute a parity for the block of user data and form a RAIDed data block, comprising strips of a stripe; a plurality of memory channel controllers (MC) in communication with at least some of the plurality of controllers; a plurality of memory modules (MM), wherein a group of memory modules is in communication with a memory channel controller (MC) of the plurality of memory channel controllers (MC); characterized in that the memory system comprises a switch in communication with each of the controllers and each of the memory channel controllers (MC); wherein: each controller of the plurality of controllers is operable to send individual strips of a stripe of the RAIDed data block to at least one memory channel controller (MC) to be written to memory modules (MM); and the switch is configured to assign a same global sequence number (GSN) to each of the strips of the stripe after all of the strips of the stripe are received by the memory channel controllers and are acknowledged to the switch by said memory channel controllers, wherein the GSN assigned by the switch is monotonically increasing, wherein write operations requested by the controllers are performed by the memory modules (MM) in GSN order. a plurality of controllers , each controller operable to receive a block of data from a user and compute a parity for the block of user data and form a RAIDed data block, comprising strips of a stripe; a plurality of memory channel controllers (MC) in communication with at least some of the plurality of controllers; a plurality of memory modules (MM), wherein a group of memory modules is in communication with a memory channel controller (MC) of the plurality of memory channel controllers (MC); characterized in that the memory system comprises a switch in communication with each of the controllers and each of the memory channel controllers (MC); wherein: each controller of the plurality of controllers is operable to send individual strips of a stripe of the RAIDed data block to at least one memory channel controller (MC) to be written to memory modules (MM); and the switch is configured to assign a same global sequence number (GSN) to each of the strips of the stripe after all of the strips of the stripe are received by the memory channel controllers and are acknowledged to the switch by said memory channel controllers, wherein the GSN assigned by the switch is monotonically increasing, wherein write operations requested by the controllers are performed by the memory modules (MM) in GSN order. each controller of the plurality of controllers is operable to send individual strips of a stripe of the RAIDed data block to at least one memory channel controller (MC) to be written to memory modules (MM); and the switch is configured to assign a same global sequence number (GSN) to each of the strips of the stripe after all of the strips of the stripe are received by the memory channel controllers and are acknowledged to the switch by said memory channel controllers, wherein the GSN assigned by the switch is monotonically increasing, wherein write operations requested by the controllers are performed by the memory modules (MM) in GSN order. <EOS>