An apparatus comprising: a ladar receiver for receiving a signal that includes a combination of an own pulse reflection and noise, wherein the own pulse reflection comprises a plurality of pulses separated by a known delay ( L ), and wherein the ladar receiver includes a signal processing circuit that uses the known delay to detect the own pulse reflection within the received signal; characterised in that : the signal processing circuit defines a triple comparator that comprises a sparse delay sum circuit and additional filtration circuitry, wherein the sparse delay sum circuit comprises: a delay circuit configured to delay the received signal by the known delay to generate a delayed signal ; an adder configured to sum the received signal with the delayed signal to generate a delay sum signal ; and a first comparator configured to compare the delay sum signal with a first controllable threshold ( T ); wherein the additional filtration circuitry comprises a first multiplier , a second comparator , a second multiplier , a third comparator , and logic ; wherein the first multiplier is configured to multiply the received signal with a second controllable threshold ( τ ) to generate a first product , wherein the second controllable threshold defines a permitted inter-pulse deviation for the own pulse reflection; wherein the second comparator is configured to compare the delayed signal with the first product; wherein the second multiplier is configured to multiply the delayed signal with the second controllable threshold to generate a second product ; wherein the third comparator is configured to compare the received signal with the second product; and wherein the logic is configured to detect the own pulse reflection based on results from the first, second, and third comparators. a ladar receiver for receiving a signal that includes a combination of an own pulse reflection and noise, wherein the own pulse reflection comprises a plurality of pulses separated by a known delay ( L ), and wherein the ladar receiver includes a signal processing circuit that uses the known delay to detect the own pulse reflection within the received signal; characterised in that : the signal processing circuit defines a triple comparator that comprises a sparse delay sum circuit and additional filtration circuitry, wherein the sparse delay sum circuit comprises: a delay circuit configured to delay the received signal by the known delay to generate a delayed signal ; an adder configured to sum the received signal with the delayed signal to generate a delay sum signal ; and a first comparator configured to compare the delay sum signal with a first controllable threshold ( T ); a delay circuit configured to delay the received signal by the known delay to generate a delayed signal ; an adder configured to sum the received signal with the delayed signal to generate a delay sum signal ; and a first comparator configured to compare the delay sum signal with a first controllable threshold ( T ); wherein the additional filtration circuitry comprises a first multiplier , a second comparator , a second multiplier , a third comparator , and logic ; wherein the first multiplier is configured to multiply the received signal with a second controllable threshold ( τ ) to generate a first product , wherein the second controllable threshold defines a permitted inter-pulse deviation for the own pulse reflection; wherein the second comparator is configured to compare the delayed signal with the first product; wherein the second multiplier is configured to multiply the delayed signal with the second controllable threshold to generate a second product ; wherein the third comparator is configured to compare the received signal with the second product; and wherein the logic is configured to detect the own pulse reflection based on results from the first, second, and third comparators. <EOS>