Method for forming spacers of a gate of a field effect transistor , the gate being located above an active layer made of a semi-conductive material surmounting an insulating layer and a support substrate , the active layer , the insulating layer and the support substrate defining a silicon-on-insulator (SOI)-type stack, comprising a step of forming a protective layer covering at least the gate of the transistor , the method being characterised in that it comprises: - before the step of forming the protective layer , a step of forming a porous layer between the gate and the protective layer , the porous layer having a dielectric constant k equal to or less than that of silicon oxide (SiO 2 ); - after the step of forming the protective layer , a step of etching the protective layer produced anisotropically, so as to conserve residual portions of the protective layer only at the level of the edges of the gate , these residual portions constituting protective spacers of the gate and so as to uncover the porous layer outside of the edges of the gate ; - a modification of the porous layer carried out by penetrating ions within the porous layer to form a modified layer , said modification of the porous layer being carried out using a plasma, of which the ions penetrate into the porous layer uncovered, said modification being carried out anisotropically and so as to modify the porous layer over the whole of the thickness thereof above the gate and above the active layer and so as to not modify the whole thickness of the porous layer located on the edges of the gate , the porous layer located on the edges of the gate being protected by the protective spacers and constituting porous spacers for the gate ; and - at least one step of removing the modified layer using a selective etching of the modified layer opposite said semi-conductive material of the active layer and protective spacers protecting the porous layer located on the edges of the gate and wherein, the active layer has a thickness less than 30nm and preferably less than 20nm, the porous layer is arranged directly in contact with the active layer and the step of forming the porous layer is carried out to form a porous layer of which the thickness is less than 20nm. - before the step of forming the protective layer , a step of forming a porous layer between the gate and the protective layer , the porous layer having a dielectric constant k equal to or less than that of silicon oxide (SiO 2 ); - after the step of forming the protective layer , a step of etching the protective layer produced anisotropically, so as to conserve residual portions of the protective layer only at the level of the edges of the gate , these residual portions constituting protective spacers of the gate and so as to uncover the porous layer outside of the edges of the gate ; - a modification of the porous layer carried out by penetrating ions within the porous layer to form a modified layer , said modification of the porous layer being carried out using a plasma, of which the ions penetrate into the porous layer uncovered, said modification being carried out anisotropically and so as to modify the porous layer over the whole of the thickness thereof above the gate and above the active layer and so as to not modify the whole thickness of the porous layer located on the edges of the gate , the porous layer located on the edges of the gate being protected by the protective spacers and constituting porous spacers for the gate ; and - at least one step of removing the modified layer using a selective etching of the modified layer opposite said semi-conductive material of the active layer and protective spacers protecting the porous layer located on the edges of the gate and wherein, <EOS>