A semiconductor device comprising: a multi-finger NMOS transistor formed by fingers having the same shape, the multi-finger NMOS transistor comprising: a plurality of source regions and a plurality of drain regions alternately arranged on a surface of a semiconductor substrate; a plurality of channel regions each arranged between one of the plurality of source regions and one of the plurality of drain regions; and a gate electrode formed above each of the plurality of channel regions; a source wiring formed on the gate electrode and the plurality of source regions in a region of the multi-finger NMOS transistor, for electrically connecting the gate electrode, the plurality of source regions, and a ground terminal; and a drain wiring not formed on the gate electrode and formed on the plurality of drain regions in the region of the multi-finger NMOS transistor, electrically connecting the plurality of drain regions and a pad serving as an external connection electrode wherein each finger comprises the source region, the source wiring, the drain region, and the drain wiring that sandwich one gate electrode, wherein the layout of the source and drain wiring is such that the wiring width of the drain wiring and the wiring width of the source wiring within one finger are the same, and the source and drain wiring contacts are arranged in the same manner, and wherein the resistance of said one finger is evenly distributed across a channel-width direction so that, when a surge current flows through said one finger, a value of the resistance from the pad to the ground terminal is the same regardless of which region of the channel the surge current flows through. a multi-finger NMOS transistor formed by fingers having the same shape, the multi-finger NMOS transistor comprising: a plurality of source regions and a plurality of drain regions alternately arranged on a surface of a semiconductor substrate; a plurality of channel regions each arranged between one of the plurality of source regions and one of the plurality of drain regions; and a gate electrode formed above each of the plurality of channel regions; a plurality of source regions and a plurality of drain regions alternately arranged on a surface of a semiconductor substrate; a plurality of channel regions each arranged between one of the plurality of source regions and one of the plurality of drain regions; and a gate electrode formed above each of the plurality of channel regions; a source wiring formed on the gate electrode and the plurality of source regions in a region of the multi-finger NMOS transistor, for electrically connecting the gate electrode, the plurality of source regions, and a ground terminal; and a drain wiring not formed on the gate electrode and formed on the plurality of drain regions in the region of the multi-finger NMOS transistor, electrically connecting the plurality of drain regions and a pad serving as an external connection electrode wherein each finger comprises the source region, the source wiring, the drain region, and the drain wiring that sandwich one gate electrode, wherein the layout of the source and drain wiring is such that the wiring width of the drain wiring and the wiring width of the source wiring within one finger are the same, and the source and drain wiring contacts are arranged in the same manner, and wherein the resistance of said one finger is evenly distributed across a channel-width direction so that, when a surge current flows through said one finger, a value of the resistance from the pad to the ground terminal is the same regardless of which region of the channel the surge current flows through. <EOS>