An apparatus comprising: processing circuitry to perform data processing; and an instruction decoder to decode a vector instruction to control the processing circuitry to perform a plurality of lanes of vector processing corresponding to respective data elements of a vector value; wherein in response to a vector predication instruction, the instruction decoder is configured to control the processing circuitry to set, in dependence on a plurality of element comparison operations each for determining whether a corresponding data element of a target vector value passes or fails a test condition, control information for controlling processing of a predetermined number of subsequent vector instructions after said vector predication instruction within a sequence of instructions to be processed, wherein said predetermined number is hardwired or identified by the vector predication instruction; and in response to one of said predetermined number of subsequent vector instructions, the instruction decoder is configured to control the processing circuitry to determine whether to mask an operation associated with a given portion of a given lane of vector processing in dependence on an outcome of the element comparison operation indicated by the control information for a data element of the target vector value corresponding to said given portion; wherein in response to at least one type of vector instruction, the instruction decoder is configured to control the processing circuitry to perform an additional operation independent of said plurality of lanes of vector processing; and the processing circuitry is configured to perform the additional operation independent of the control information when one of said predetermined number of subsequent vector instructions is one of said at least one type of vector instruction. processing circuitry to perform data processing; and an instruction decoder to decode a vector instruction to control the processing circuitry to perform a plurality of lanes of vector processing corresponding to respective data elements of a vector value; wherein in response to a vector predication instruction, the instruction decoder is configured to control the processing circuitry to set, in dependence on a plurality of element comparison operations each for determining whether a corresponding data element of a target vector value passes or fails a test condition, control information for controlling processing of a predetermined number of subsequent vector instructions after said vector predication instruction within a sequence of instructions to be processed, wherein said predetermined number is hardwired or identified by the vector predication instruction; and in response to one of said predetermined number of subsequent vector instructions, the instruction decoder is configured to control the processing circuitry to determine whether to mask an operation associated with a given portion of a given lane of vector processing in dependence on an outcome of the element comparison operation indicated by the control information for a data element of the target vector value corresponding to said given portion; wherein in response to at least one type of vector instruction, the instruction decoder is configured to control the processing circuitry to perform an additional operation independent of said plurality of lanes of vector processing; and the processing circuitry is configured to perform the additional operation independent of the control information when one of said predetermined number of subsequent vector instructions is one of said at least one type of vector instruction. <EOS>