A TFT substrate, wherein the TFT substrate has a plurality of sub-pixels arranged in rows and columns, and the TFT substrate comprises: a base ; a first active layer , disposed on a side of the base , wherein each sub-pixel comprises the first active layer ; a first source drain layer, disposed on a side that is of the first active layer and that is away from the base , wherein the first source drain layer comprises a first source and a first drain in each sub-pixel , and both the first source and the first drain in each sub-pixel are coupled to the first active layer in the sub-pixel ; a first gate , disposed in correspondence to the first active layer , and disposed between the first active layer and the first source drain layer; a plurality of data lines (DL), disposed at the first source drain layer, wherein the plurality of data lines (DL) are respectively coupled to the first source or the first drain in a plurality of columns of sub-pixels ; and a wiring layer , disposed on a side that is of the first source drain layer and that is away from the base , wherein the wiring layer comprises a plurality of first metal wires , one end of each of the plurality of first metal wires is coupled to each of the plurality of data lines (DL), and the other end of each of the plurality of first metal wires is used to be coupled to a display driver chip , wherein the plurality of first metal wires form a first area on the TFT substrate, the wiring layer further comprises a plurality of second metal wires disposed in a second area of the TFT substrate, the second area is an area on the TFT substrate except for the first area, and the second metal wire is separated from the first metal wire , and wherein the TFT substrate further comprises a second source drain layer, disposed between the first source drain layer and the wiring layer , wherein the second source drain layer is coupled to the second metal wire . a base ; a first active layer , disposed on a side of the base , wherein each sub-pixel comprises the first active layer ; a first source drain layer, disposed on a side that is of the first active layer and that is away from the base , wherein the first source drain layer comprises a first source and a first drain in each sub-pixel , and both the first source and the first drain in each sub-pixel are coupled to the first active layer in the sub-pixel ; a first gate , disposed in correspondence to the first active layer , and disposed between the first active layer and the first source drain layer; a plurality of data lines (DL), disposed at the first source drain layer, wherein the plurality of data lines (DL) are respectively coupled to the first source or the first drain in a plurality of columns of sub-pixels ; and a wiring layer , disposed on a side that is of the first source drain layer and that is away from the base , wherein the wiring layer comprises a plurality of first metal wires , one end of each of the plurality of first metal wires is coupled to each of the plurality of data lines (DL), and the other end of each of the plurality of first metal wires is used to be coupled to a display driver chip , wherein the plurality of first metal wires form a first area on the TFT substrate, the wiring layer further comprises a plurality of second metal wires disposed in a second area of the TFT substrate, the second area is an area on the TFT substrate except for the first area, and the second metal wire is separated from the first metal wire , and wherein the TFT substrate further comprises a second source drain layer, disposed between the first source drain layer and the wiring layer , wherein the second source drain layer is coupled to the second metal wire . <EOS>