A clock recovery circuit adapted to recover a timing signal from a bursty input signal where the input signal is periodically present and absent, said recovery circuit comprising: a main phase detector adapted to compare the phases of the input signal and a recovered clock signal to produce a phase error signal; an analog-to-digital, A/D, converter adapted to convert the phase error signal to a digital phase error signal; a burst detector adapted to detect the input signal when the input signal is being received by the recovery circuit; a switch responsive to the digital phase error signal, which is adapted to be closed by the burst detector in response to detecting the presence of the input signal; a digital main loop filter adapted to filter the digital phase error signal and to generate a digital tuning signal; and a numerically controlled oscillator, NCO, circuit responsive to a reference clock signal and the digital tuning signal, said NCO circuit including an inner phase locked loop, PLL, having an inner phase detector adapted to generate an inner error signal by comparing phases of the reference clock signal and a recovered feedback clock recovery signal, a feedback divider adapted to divide the recovered clock signal by a programmable value defined by the tuning signal to generate the recovered feedback clock recovery signal, an NCO circuit loop filter adapted to filter the inner error signal, a digital-to-analog, D/A, converter adapted to convert the digital tuning signal to an analog tuning signal, an NCO circuit summer adapted to add the filtered inner error signal and the analog tuning signal to generate a summed signal, and an NCO circuit controlled oscillator that is tuned by the summed signal so as to generate the clock recovery signal. a main phase detector adapted to compare the phases of the input signal and a recovered clock signal to produce a phase error signal; an analog-to-digital, A/D, converter adapted to convert the phase error signal to a digital phase error signal; a burst detector adapted to detect the input signal when the input signal is being received by the recovery circuit; a switch responsive to the digital phase error signal, which is adapted to be closed by the burst detector in response to detecting the presence of the input signal; a digital main loop filter adapted to filter the digital phase error signal and to generate a digital tuning signal; and a numerically controlled oscillator, NCO, circuit responsive to a reference clock signal and the digital tuning signal, said NCO circuit including an inner phase locked loop, PLL, having an inner phase detector adapted to generate an inner error signal by comparing phases of the reference clock signal and a recovered feedback clock recovery signal, a feedback divider adapted to divide the recovered clock signal by a programmable value defined by the tuning signal to generate the recovered feedback clock recovery signal, an NCO circuit loop filter adapted to filter the inner error signal, a digital-to-analog, D/A, converter adapted to convert the digital tuning signal to an analog tuning signal, an NCO circuit summer adapted to add the filtered inner error signal and the analog tuning signal to generate a summed signal, and an NCO circuit controlled oscillator that is tuned by the summed signal so as to generate the clock recovery signal. <EOS>