A display device comprising: a first pixel circuit portion (PX1) including at least one transistor; a second pixel circuit portion (PX2) including at least one transistor; a first pixel electrode electrically connected to the first pixel circuit portion (PX1); a second pixel electrode electrically connected to the second pixel circuit portion (PX2); a first data line electrically connected to the first pixel circuit portion (PX1); and a second data line electrically connected to the second pixel circuit portion (PX2), wherein the first data line and the second data line are arranged adjacent to each other along a first direction (DR1), and the second pixel electrode overlaps the first data line and the second data line in a plan view, the first pixel circuit portion (PX1) and the second pixel circuit portion (PX2) are arranged adjacent to each other along a second direction (DR2) perpendicular to the first direction (DR1) wherein the display device further comprising: a third pixel circuit portion (PX3) including at least one transistor; and a third pixel electrode electrically connected to the third pixel circuit portion (PX3), wherein, in a plan view, the third pixel circuit portion (PX3) is arranged along the second direction (DR2) with the first pixel circuit portion (PX1) and the second pixel circuit portion (PX2), and the first pixel electrode , the second pixel electrode and the third pixel electrode are arranged adjacent to each other along the first direction (DR1). a first pixel circuit portion (PX1) including at least one transistor; a second pixel circuit portion (PX2) including at least one transistor; a first pixel electrode electrically connected to the first pixel circuit portion (PX1); a second pixel electrode electrically connected to the second pixel circuit portion (PX2); a first data line electrically connected to the first pixel circuit portion (PX1); and a second data line electrically connected to the second pixel circuit portion (PX2), wherein the first data line and the second data line are arranged adjacent to each other along a first direction (DR1), and the second pixel electrode overlaps the first data line and the second data line in a plan view, the first pixel circuit portion (PX1) and the second pixel circuit portion (PX2) are arranged adjacent to each other along a second direction (DR2) perpendicular to the first direction (DR1) wherein the display device further comprising: a third pixel circuit portion (PX3) including at least one transistor; and a third pixel electrode electrically connected to the third pixel circuit portion (PX3), wherein, in a plan view, the third pixel circuit portion (PX3) is arranged along the second direction (DR2) with the first pixel circuit portion (PX1) and the second pixel circuit portion (PX2), and the first pixel electrode , the second pixel electrode and the third pixel electrode are arranged adjacent to each other along the first direction (DR1). a third pixel circuit portion (PX3) including at least one transistor; and a third pixel electrode electrically connected to the third pixel circuit portion (PX3), wherein, in a plan view, the third pixel circuit portion (PX3) is arranged along the second direction (DR2) with the first pixel circuit portion (PX1) and the second pixel circuit portion (PX2), and the first pixel electrode , the second pixel electrode and the third pixel electrode are arranged adjacent to each other along the first direction (DR1). <EOS>