A display device comprising: a first pixel (PX1); a second pixel (PX2) adjacent to the first pixel (PX1) in a predetermined direction; a first data line (DL1) extending in the predetermined direction and connected to the first pixel (PX1); and a second data line (DL2) extending in the predetermined direction and connected to the second pixel (PX2), each of the first pixel (PX1) and the second pixel (PX2) includes: a transistor (TR1, TR2) including a semiconductor layer , a gate electrode disposed on the semiconductor layer , and a source/drain electrode (141/142, 143/144) connected to the semiconductor layer ; a capacitor (CAP) including a first capacitor electrode (CE1) disposed in a same layer as the gate electrode and a second capacitor electrode (CE2) disposed on the first capacitor electrode (CE1); and a light emitting device (LE) disposed on the transistor (TR1, TR2) and the capacitor (CAP), and wherein the first data line (DL1) is disposed in a same layer as the source/drain electrode (141/142, 143/144), and the second data line (DL2) is disposed in a same layer as one of the conductive layer and the second capacitor electrode (CE2); characterized in that the transistor (TR1, TR2) comprises a conductive layer disposed under the semiconductor layer ; wherein an insulating layer is disposed on the second capacitor electrode (CE2) and under the source/drain electrode (141/142, 143/144). a first pixel (PX1); a second pixel (PX2) adjacent to the first pixel (PX1) in a predetermined direction; a first data line (DL1) extending in the predetermined direction and connected to the first pixel (PX1); and a second data line (DL2) extending in the predetermined direction and connected to the second pixel (PX2), each of the first pixel (PX1) and the second pixel (PX2) includes: a transistor (TR1, TR2) including a semiconductor layer , a gate electrode disposed on the semiconductor layer , and a source/drain electrode (141/142, 143/144) connected to the semiconductor layer ; a capacitor (CAP) including a first capacitor electrode (CE1) disposed in a same layer as the gate electrode and a second capacitor electrode (CE2) disposed on the first capacitor electrode (CE1); and a light emitting device (LE) disposed on the transistor (TR1, TR2) and the capacitor (CAP), and wherein a transistor (TR1, TR2) including a semiconductor layer , a gate electrode disposed on the semiconductor layer , and a source/drain electrode (141/142, 143/144) connected to the semiconductor layer ; a capacitor (CAP) including a first capacitor electrode (CE1) disposed in a same layer as the gate electrode and a second capacitor electrode (CE2) disposed on the first capacitor electrode (CE1); and a light emitting device (LE) disposed on the transistor (TR1, TR2) and the capacitor (CAP), and wherein the first data line (DL1) is disposed in a same layer as the source/drain electrode (141/142, 143/144), and the second data line (DL2) is disposed in a same layer as one of the conductive layer and the second capacitor electrode (CE2); characterized in that the transistor (TR1, TR2) comprises a conductive layer disposed under the semiconductor layer ; wherein an insulating layer is disposed on the second capacitor electrode (CE2) and under the source/drain electrode (141/142, 143/144). <EOS>