A multi-thread systolic array comprising: a plurality of processing elements each including a processor , wherein each of the processing elements is configured to: receive a plurality of first inputs from a respective first input source ; receive a plurality of second inputs from a respective second input source , wherein the plurality of first inputs and the plurality of second inputs are arranged as a plurality of pairs corresponding to a plurality of threads, wherein each thread includes one of the first inputs paired with one of the second inputs; schedule, for each operation cycle of the processor, a certain thread of the plurality of threads for execution of a computation operation by each processor of the respective processing element of the multi-thread systolic array , wherein the scheduling is performed according to available impacting values of the certain thread, wherein the impacting values are input values that significantly impact outputted values when the computation operation is performed; and execute the computation operation for the certain thread, wherein the processor is configured to execute the computation operation for the certain thread and in parallel, execute for each respective thread of the other threads, a bypass operation when at least one of the values of the respective thread is a non-impacting value, or a stalling operation when at least one of the values of the respective thread is an impacting value, wherein the non-impacting value is an input value that does not significantly impact an output value when the computation operation is performed, and the bypassing is performed without execution of the computation operation. receive a plurality of first inputs from a respective first input source ; receive a plurality of second inputs from a respective second input source , wherein the plurality of first inputs and the plurality of second inputs are arranged as a plurality of pairs corresponding to a plurality of threads, wherein each thread includes one of the first inputs paired with one of the second inputs; schedule, for each operation cycle of the processor, a certain thread of the plurality of threads for execution of a computation operation by each processor of the respective processing element of the multi-thread systolic array , wherein the scheduling is performed according to available impacting values of the certain thread, wherein the impacting values are input values that significantly impact outputted values when the computation operation is performed; and execute the computation operation for the certain thread, wherein the processor is configured to execute the computation operation for the certain thread and in parallel, execute for each respective thread of the other threads, a bypass operation when at least one of the values of the respective thread is a non-impacting value, or a stalling operation when at least one of the values of the respective thread is an impacting value, wherein the non-impacting value is an input value that does not significantly impact an output value when the computation operation is performed, and the bypassing is performed without execution of the computation operation. <EOS>