PAM transceiver with an electronic circuit set up for processing a received electrical data signal (D) with at least two states, and in particular at least three states, wherein the data signal comprises a sequence of states, which states each represent an information symbol, each symbol being assigned a clock (T) of the data signal, comprising: A data interface set up for connection to a communication channel , in particular a duplex communication channel, and set up for digitizing the data signal, the data interface having an analog/digital converter (12.1) which is set up to digitize the data signal received from the data interface and to feed it to the first circuit section (11.1) and to the second circuit section (11.2), A first circuit section (11.1) connected to the data interface: - An equalizer to compensate for distortions of the data signal caused by the communication channel; - An interpreter arranged behind the equalizer for recognizing symbols (S) which are transmitted by the data signal; A second circuit section (11.2) connected to the data interface: - A delay unit for time-shifting the data signal; An MMA processor operating according to the Mueller-Müller algorithm for recognizing a signal phase of the data signal with a first input (16.1) and a second input (16.2), where the first circuit section is connected to the first input to feed recognized symbols to the MMA processor, and where the second circuit section is connected to the second input, characterized in that the second circuit section has an adjustable filter with a finite impulse response, whereby the filter is set up to symmetrize an impulse response of the communication channel. A data interface set up for connection to a communication channel , in particular a duplex communication channel, and set up for digitizing the data signal, the data interface having an analog/digital converter (12.1) which is set up to digitize the data signal received from the data interface and to feed it to the first circuit section (11.1) and to the second circuit section (11.2), A first circuit section (11.1) connected to the data interface: - An equalizer to compensate for distortions of the data signal caused by the communication channel; - An interpreter arranged behind the equalizer for recognizing symbols (S) which are transmitted by the data signal; - An equalizer to compensate for distortions of the data signal caused by the communication channel; - An interpreter arranged behind the equalizer for recognizing symbols (S) which are transmitted by the data signal; A second circuit section (11.2) connected to the data interface: - A delay unit for time-shifting the data signal; - A delay unit for time-shifting the data signal; An MMA processor operating according to the Mueller-Müller algorithm for recognizing a signal phase of the data signal with a first input (16.1) and a second input (16.2), where the first circuit section is connected to the first input to feed recognized symbols to the MMA processor, and where the second circuit section is connected to the second input, characterized in that the second circuit section has an adjustable filter with a finite impulse response, whereby the filter is set up to symmetrize an impulse response of the communication channel. <EOS>