A method of manufacturing a circuit, comprising: forming a power switch comprising multiple stages connected in parallel, connecting the power switch between an external power voltage (Vdd_ex) and an internal power voltage (Vdd_in) and operable to turn on in response to a couple of enable signals (en_rest, en_few), the enable signals independent of an electrostatic discharge (ESD) event and independent of an external power supply rail voltage, wherein each stage of the multiple stages is formed by a PMOS transistor, wherein at least a first stage is controlled by a first enable signal (en_few) and at least a second stage is controlled by a second enable signal (en_rest), and the enable signals are directly applied to the gate of the PMOS transistor of the respective first and second stages, the power switch further comprising at least one third stage of the multiple stages; forming means for ESD protection comprising an RC clamp , the at least one third stage , and an ESD protection circuit, the RC clamp comprising a resistor connected in series to a capacitor, and an ESD diode , an anode of which is coupled to the internal power voltage and a cathode of which is coupled to the external power voltage, the resistor having a terminal connected to the external power voltage (Vdd_ex), the capacitor having a terminal connected to the internal power voltage (Vdd_in); wherein the ESD protection circuit consists of: a NAND gate having a first input receiving the second enable signal (en_rest), a second input connected to the common node of the resistor and the capacitor, and an output producing an intermediate signal; and an inverter receiving the intermediate signal and producing an output signal provided to the gate of the PMOS transistor of the at least one third stage. forming a power switch comprising multiple stages connected in parallel, connecting the power switch between an external power voltage (Vdd_ex) and an internal power voltage (Vdd_in) and operable to turn on in response to a couple of enable signals (en_rest, en_few), the enable signals independent of an electrostatic discharge (ESD) event and independent of an external power supply rail voltage, wherein each stage of the multiple stages is formed by a PMOS transistor, wherein at least a first stage is controlled by a first enable signal (en_few) and at least a second stage is controlled by a second enable signal (en_rest), and the enable signals are directly applied to the gate of the PMOS transistor of the respective first and second stages, the power switch further comprising at least one third stage of the multiple stages; forming means for ESD protection comprising an RC clamp , the at least one third stage , and an ESD protection circuit, the RC clamp comprising a resistor connected in series to a capacitor, and an ESD diode , an anode of which is coupled to the internal power voltage and a cathode of which is coupled to the external power voltage, the resistor having a terminal connected to the external power voltage (Vdd_ex), the capacitor having a terminal connected to the internal power voltage (Vdd_in); wherein the ESD protection circuit consists of: a NAND gate having a first input receiving the second enable signal (en_rest), a second input connected to the common node of the resistor and the capacitor, and an output producing an intermediate signal; and an inverter receiving the intermediate signal and producing an output signal provided to the gate of the PMOS transistor of the at least one third stage. <EOS>