A semiconductor component, comprising: a semiconductor substrate having a first surface and an opposing, second surface; and at least one via, comprising: an annular conductive metal layer substantially even with and extending between planes of the first surface and the opposing, second surface of the semiconductor substrate; a seed layer between the annular conductive metal layer and the substrate, the seed layer substantially even with and extending between the planes of the first surface and the opposing, second surface of the semiconductor substrate; and a silicon-containing filler material circumscribed by the annular conductive metal layer, the silicon-containing filler material being substantially even with and extending between the planes of the first surface and the opposing, second surface of the semiconductor substrate; bond pads overlying opposing ends of the at least one via, one of bond pads located on the first surface of the semiconductor substrate and another of the bond pads located on the opposing, second surface of the semiconductor substrate; contact pads on the first surface and the opposing, second surface of the semiconductor substrate; and circuit traces configured to electrically connect the at least one via to the contact pads. a semiconductor substrate having a first surface and an opposing, second surface; and at least one via, comprising: an annular conductive metal layer substantially even with and extending between planes of the first surface and the opposing, second surface of the semiconductor substrate; a seed layer between the annular conductive metal layer and the substrate, the seed layer substantially even with and extending between the planes of the first surface and the opposing, second surface of the semiconductor substrate; and a silicon-containing filler material circumscribed by the annular conductive metal layer, the silicon-containing filler material being substantially even with and extending between the planes of the first surface and the opposing, second surface of the semiconductor substrate; an annular conductive metal layer substantially even with and extending between planes of the first surface and the opposing, second surface of the semiconductor substrate; a seed layer between the annular conductive metal layer and the substrate, the seed layer substantially even with and extending between the planes of the first surface and the opposing, second surface of the semiconductor substrate; and a silicon-containing filler material circumscribed by the annular conductive metal layer, the silicon-containing filler material being substantially even with and extending between the planes of the first surface and the opposing, second surface of the semiconductor substrate; bond pads overlying opposing ends of the at least one via, one of bond pads located on the first surface of the semiconductor substrate and another of the bond pads located on the opposing, second surface of the semiconductor substrate; contact pads on the first surface and the opposing, second surface of the semiconductor substrate; and circuit traces configured to electrically connect the at least one via to the contact pads. <EOS>