An in-memory computation circuit in FD-SOI technology, comprising: a memory array including a plurality of static random access memory (SRAM) cells arranged in a matrix with plural rows and plural columns, each row including a word line connected to the SRAM cells of the row, and each column including at least one bit line connected to the SRAM cells of the column; wherein each SRAM cell includes a first body bias voltage line connected to body nodes of first-type transistors of the SRAM cell; a word line drive circuit for each row having an output connected to drive the word line of the row; a row controller circuit configured to simultaneously actuate the plurality of word lines by applying pulses through the word line driver circuits to the word lines for an in-memory compute operation; a column processing circuit connected to the at least one bit line for each column and configured to process analog voltages developed on the bit lines in response to the simultaneous actuation of the plurality of word lines to generate a decision output for the in-memory compute operation; a voltage generator circuit configured to generate a first modulated body bias voltage applied to the first body bias voltage line, said first modulated body bias voltage having a first negative voltage level during the simultaneous actuation of the plurality of word lines for the in-memory compute operation, and a control circuit configured to generate a control signal configured to be applied to the voltage generator circuit, and comprising a temperature sensor , the control signal being configured to cause a temperature dependent tuning of the negative voltage level, or modulation of the negative voltage level away from a nominal level in response to an integrated circuit temperature sensed by the temperature sensor. a memory array including a plurality of static random access memory (SRAM) cells arranged in a matrix with plural rows and plural columns, each row including a word line connected to the SRAM cells of the row, and each column including at least one bit line connected to the SRAM cells of the column; wherein each SRAM cell includes a first body bias voltage line connected to body nodes of first-type transistors of the SRAM cell; a word line drive circuit for each row having an output connected to drive the word line of the row; a row controller circuit configured to simultaneously actuate the plurality of word lines by applying pulses through the word line driver circuits to the word lines for an in-memory compute operation; a column processing circuit connected to the at least one bit line for each column and configured to process analog voltages developed on the bit lines in response to the simultaneous actuation of the plurality of word lines to generate a decision output for the in-memory compute operation; a voltage generator circuit configured to generate a first modulated body bias voltage applied to the first body bias voltage line, said first modulated body bias voltage having a first negative voltage level during the simultaneous actuation of the plurality of word lines for the in-memory compute operation, and a control circuit configured to generate a control signal configured to be applied to the voltage generator circuit, and comprising a temperature sensor , the control signal being configured to cause a temperature dependent tuning of the negative voltage level, or modulation of the negative voltage level away from a nominal level in response to an integrated circuit temperature sensed by the temperature sensor. <EOS>