An electronic circuit with protection against eavesdropping by power analysis, comprising: a storage element configured to store a set of bits corresponding to correct values, wherein the storage element is driven by a first clock signal (clk/2 520) having a first frequency; a random bit generator , configured to generate one random bit (R0, R1, Ri) for each of the stored set of bits corresponding to correct values respectively, said random bit generator being driven by the first clock signal; an indicator , driven by a second clock signal at a second frequency which is two times the first frequency, configured to provide a first value for a first cycle of the second clock signal and a second value for a second cycle of the second clock signal; a plurality of selectors (L0, L1), coupled to the storage element and the random bit generator , each selector being driven by one of the random bits and being configured to either the corresponding bit of the stored set of bits corresponding to correct values, or a replaced bit, wherein the first value enables a random value to be provided as the replaced bit, and the second value enables the correct value to be set as the replaced bit; and a combinatorial logic unit , coupled to the plurality of selectors (L0, L1), configured to provide a next state set of bits (N0, N1, 540) after two cycles of the second clock signal to the storage element , wherein the combinatorial logic unit is configured to perform a first logic calculation on the output of the plurality of selectors (L0, L1) including each of the replaced bits in the first cycle, and is configured to perform a last logic calculation on all of the stored set of bits corresponding to correct values in the second cycle. a storage element configured to store a set of bits corresponding to correct values, wherein the storage element is driven by a first clock signal (clk/2 520) having a first frequency; a random bit generator , configured to generate one random bit (R0, R1, Ri) for each of the stored set of bits corresponding to correct values respectively, said random bit generator being driven by the first clock signal; an indicator , driven by a second clock signal at a second frequency which is two times the first frequency, configured to provide a first value for a first cycle of the second clock signal and a second value for a second cycle of the second clock signal; a plurality of selectors (L0, L1), coupled to the storage element and the random bit generator , each selector being driven by one of the random bits and being configured to either the corresponding bit of the stored set of bits corresponding to correct values, or a replaced bit, wherein the first value enables a random value to be provided as the replaced bit, and the second value enables the correct value to be set as the replaced bit; and a combinatorial logic unit , coupled to the plurality of selectors (L0, L1), configured to provide a next state set of bits (N0, N1, 540) after two cycles of the second clock signal to the storage element , wherein the combinatorial logic unit is configured to perform a first logic calculation on the output of the plurality of selectors (L0, L1) including each of the replaced bits in the first cycle, and is configured to perform a last logic calculation on all of the stored set of bits corresponding to correct values in the second cycle. <EOS>