An optical receiver comprising: a PD chip on which two photodiodes (PDs(PD1,PD2)) constituting a dual photodiode are mounted for each channel; and a TIA chip on which a transimpedance amplifier (TIA) corresponding to each channel is mounted, wherein a signal line (IN or INC) connecting the PD chip and the TIA chip is surrounded by a conductor pattern that is not connected to the signal line (IN or INC) for each channel, the conductor pattern being connected to a ground pattern on the TIA chip or a power source pattern for the PDs, wherein: the two PDs (PD1,PD2) constituting the dual photodiode are connected with their cathodes facing each other, a connecting point of the cathodes being connected to a PD power source pattern (VPD) on the TIA chip ; from two anodes of the two PDs, two signal lines (IN,INC) are drawn out and are inputted into the TIA chip; from the cathode connecting point, the conductor pattern is branched so as to surround the two PDs toward circumferential sides of the PD chip , and the branched patterns are drawn out as two PD power source patterns from positions sandwiching the two signal lines (IN,INC) and are connected to the PD power source pattern (VPD) on the TIA chip; and the PD power source pattern on the TIA chip is grounded at a high frequency with a capacitor (C60) on the TIA chip. a PD chip on which two photodiodes (PDs(PD1,PD2)) constituting a dual photodiode are mounted for each channel; and a TIA chip on which a transimpedance amplifier (TIA) corresponding to each channel is mounted, wherein a signal line (IN or INC) connecting the PD chip and the TIA chip is surrounded by a conductor pattern that is not connected to the signal line (IN or INC) for each channel, the conductor pattern being connected to a ground pattern on the TIA chip or a power source pattern for the PDs, wherein: the two PDs (PD1,PD2) constituting the dual photodiode are connected with their cathodes facing each other, a connecting point of the cathodes being connected to a PD power source pattern (VPD) on the TIA chip ; from two anodes of the two PDs, two signal lines (IN,INC) are drawn out and are inputted into the TIA chip; from the cathode connecting point, the conductor pattern is branched so as to surround the two PDs toward circumferential sides of the PD chip , and the branched patterns are drawn out as two PD power source patterns from positions sandwiching the two signal lines (IN,INC) and are connected to the PD power source pattern (VPD) on the TIA chip; and the PD power source pattern on the TIA chip is grounded at a high frequency with a capacitor (C60) on the TIA chip. the two PDs (PD1,PD2) constituting the dual photodiode are connected with their cathodes facing each other, a connecting point of the cathodes being connected to a PD power source pattern (VPD) on the TIA chip ; from two anodes of the two PDs, two signal lines (IN,INC) are drawn out and are inputted into the TIA chip; from the cathode connecting point, the conductor pattern is branched so as to surround the two PDs toward circumferential sides of the PD chip , and the branched patterns are drawn out as two PD power source patterns from positions sandwiching the two signal lines (IN,INC) and are connected to the PD power source pattern (VPD) on the TIA chip; and the PD power source pattern on the TIA chip is grounded at a high frequency with a capacitor (C60) on the TIA chip. <EOS>