A processor , comprising: a cache memory ; and a processing core , communicatively coupled to an architecturally-protected environment comprising an architecturally-protected memory, the processing core to: identify a code comprising a plurality of instructions to be executed in the architecturally-protected environment; execute a preamble instruction prior to execution of the plurality of instructions, to perform address pre-translation of virtual memory pages to physical memory pages to be used by the code; lock an area of the cache memory to the architecturally-protected environment, wherein the locked area is not an eviction victim when the cache memory is full; determine that a first physical memory page stored in the architecturally-protected memory matches a first virtual memory page referenced by a first instruction of the plurality of instructions; generate a first address mapping between a first address of the first virtual memory page and a second address of the first physical memory page; store, in the locked area of cache memory , an address translation data structure comprising a plurality of address mappings, including the first address mapping, to map virtual memory pages, referenced by the plurality of instructions, to physical memory pages; and execute the code by retrieving the first address mapping stored in the address translation data structure. a cache memory ; and a processing core , communicatively coupled to an architecturally-protected environment comprising an architecturally-protected memory, the processing core to: identify a code comprising a plurality of instructions to be executed in the architecturally-protected environment; execute a preamble instruction prior to execution of the plurality of instructions, to perform address pre-translation of virtual memory pages to physical memory pages to be used by the code; lock an area of the cache memory to the architecturally-protected environment, wherein the locked area is not an eviction victim when the cache memory is full; determine that a first physical memory page stored in the architecturally-protected memory matches a first virtual memory page referenced by a first instruction of the plurality of instructions; generate a first address mapping between a first address of the first virtual memory page and a second address of the first physical memory page; store, in the locked area of cache memory , an address translation data structure comprising a plurality of address mappings, including the first address mapping, to map virtual memory pages, referenced by the plurality of instructions, to physical memory pages; and execute the code by retrieving the first address mapping stored in the address translation data structure. identify a code comprising a plurality of instructions to be executed in the architecturally-protected environment; execute a preamble instruction prior to execution of the plurality of instructions, to perform address pre-translation of virtual memory pages to physical memory pages to be used by the code; lock an area of the cache memory to the architecturally-protected environment, wherein the locked area is not an eviction victim when the cache memory is full; determine that a first physical memory page stored in the architecturally-protected memory matches a first virtual memory page referenced by a first instruction of the plurality of instructions; generate a first address mapping between a first address of the first virtual memory page and a second address of the first physical memory page; store, in the locked area of cache memory , an address translation data structure comprising a plurality of address mappings, including the first address mapping, to map virtual memory pages, referenced by the plurality of instructions, to physical memory pages; and execute the code by retrieving the first address mapping stored in the address translation data structure. <EOS>