An execution unit circuit for an image processor, the execution unit circuit comprising: a first arithmetic logic unit (ALU) circuit comprising a first input for receiving a first input value (X), a second input for receiving a second input value (Y), and an output, the first ALU circuit being configured to subtract the second input value (Y) from the first input value (X) to thereby generate an output value (Q) at the output of the first ALU circuit ; and a second ALU circuit comprising a first input coupled to a first data path comprising register space and the output of the first ALU circuit as alternative sources of an input value (Q, R) at the first input, and a second input coupled to a second data path comprising the register space as a source for an input value (Z) at the second input, wherein the second ALU circuit comprises circuitry to determine an absolute value (|Q|, |R|) of the input value (Q, R) at the first input and to add the absolute value (|Q|, |R|) to the input value (Z) at the second input, wherein the execution unit circuit is configured to execute a sum of absolute difference (SAD) instruction wherein the input value (Z) at the second input of the second ALU circuit has a non-zero value, and the execution unit circuit selects the output of the first ALU circuit as the source of the input value at the first input of the second ALU circuit so that the output value (Q) at the output of the first ALU circuit is provided at the first input of the second ALU circuit , and wherein the execution unit circuit is configured to execute an absolute value (ABS) instruction or a modified absolute value (ABS*) instruction wherein the execution unit circuit selects the register space as the source of the input value (R) at the first input of the second ALU circuit so that an input value (R) from the register space is provided at the first input of the second ALU circuit . a first arithmetic logic unit (ALU) circuit comprising a first input for receiving a first input value (X), a second input for receiving a second input value (Y), and an output, the first ALU circuit being configured to subtract the second input value (Y) from the first input value (X) to thereby generate an output value (Q) at the output of the first ALU circuit ; and a second ALU circuit comprising a first input coupled to a first data path comprising register space and the output of the first ALU circuit as alternative sources of an input value (Q, R) at the first input, and a second input coupled to a second data path comprising the register space as a source for an input value (Z) at the second input, wherein the second ALU circuit comprises circuitry to determine an absolute value (|Q|, |R|) of the input value (Q, R) at the first input and to add the absolute value (|Q|, |R|) to the input value (Z) at the second input, wherein the execution unit circuit is configured to execute a sum of absolute difference (SAD) instruction wherein the input value (Z) at the second input of the second ALU circuit has a non-zero value, and the execution unit circuit selects the output of the first ALU circuit as the source of the input value at the first input of the second ALU circuit so that the output value (Q) at the output of the first ALU circuit is provided at the first input of the second ALU circuit , and wherein the execution unit circuit is configured to execute an absolute value (ABS) instruction or a modified absolute value (ABS*) instruction wherein the execution unit circuit selects the register space as the source of the input value (R) at the first input of the second ALU circuit so that an input value (R) from the register space is provided at the first input of the second ALU circuit . <EOS>