A method comprising: providing a hard-wired integer multiplier circuit configured to multiply a first physical operand and a second physical operand; mapping a first logical operand to a first portion of the first physical operand; mapping a second logical operand to a second portion of the first physical operand; mapping a third logical operand to the second physical operand; mapping a fourth logical operand to a third portion of the first physical operand; multiplying the first physical operand and the second physical operand using the hard-wired integer multiplier circuit to provide a multiplication result that includes a first portion comprising a product of the first logical operand and the third logical operand, a second portion comprising a product of the second logical operand and the third logical operand and a third portion comprising a product of the third logical operand and the fourth logical operand; wherein the mapping to the first physical operand comprises: inserting a number of zero padding bits between the first portion of the first physical operand and the second portion of the first physical operand, where the number of zero padding bits is less than a maximum word length of the first logical operand, the second logical operand, and the third logical operand; and wherein the mapping to the first physical operand further comprises: inserting a second number of zero paddings bits between the second portion of the first physical operand and the third portion of the first physical operand, where the second number of zero padding bits is less than a maximum word length of the first logical operand, the second logical operand, the third logical operand and the fourth logical operand. providing a hard-wired integer multiplier circuit configured to multiply a first physical operand and a second physical operand; mapping a first logical operand to a first portion of the first physical operand; mapping a second logical operand to a second portion of the first physical operand; mapping a third logical operand to the second physical operand; mapping a fourth logical operand to a third portion of the first physical operand; multiplying the first physical operand and the second physical operand using the hard-wired integer multiplier circuit to provide a multiplication result that includes a first portion comprising a product of the first logical operand and the third logical operand, a second portion comprising a product of the second logical operand and the third logical operand and a third portion comprising a product of the third logical operand and the fourth logical operand; wherein the mapping to the first physical operand comprises: inserting a number of zero padding bits between the first portion of the first physical operand and the second portion of the first physical operand, where the number of zero padding bits is less than a maximum word length of the first logical operand, the second logical operand, and the third logical operand; and inserting a number of zero padding bits between the first portion of the first physical operand and the second portion of the first physical operand, where the number of zero padding bits is less than a maximum word length of the first logical operand, the second logical operand, and the third logical operand; and wherein the mapping to the first physical operand further comprises: inserting a second number of zero paddings bits between the second portion of the first physical operand and the third portion of the first physical operand, where the second number of zero padding bits is less than a maximum word length of the first logical operand, the second logical operand, the third logical operand and the fourth logical operand. <EOS>