A method of forming a semiconductor package, comprising: providing an electrically insulative layer having a first surface opposing a second surface ; plating a first copper layer onto the second surface of the electrically insulative layer ; patterning the first copper layer ; forming traces in the first copper layer by etching through exposed portions of the first copper layer ; plating a second copper layer onto the traces in the first copper layer ; patterning the second copper layer ; forming traces in the second copper layer that correspond with the traces in the first copper layer by etching through exposed portions of the second copper layer ; bonding at least one semiconductor device with at least one of the traces in the second copper layer ; encapsulating the at least one semiconductor device with a mold compound ; and bonding at least one package electrical connector with one of the first copper layer and the second copper layer ; wherein a width of the traces of the second copper layer are thinner than a width of the traces of the first copper layer by an offset distance; and plating a first copper layer on the first surface of the electrically insulative layer ; patterning the first copper layer ; removing an exposed portion of the first copper layer ; plating a second copper layer onto the first copper layer ; patterning the second copper layer ; and removing an exposed portion of the second copper layer ; wherein a distance from an edge of the electrically insulative layer to an edge of the first copper layer is smaller than a distance from the edge of the electrically insulative layer to an edge of the second copper layer . providing an electrically insulative layer having a first surface opposing a second surface ; plating a first copper layer onto the second surface of the electrically insulative layer ; patterning the first copper layer ; forming traces in the first copper layer by etching through exposed portions of the first copper layer ; plating a second copper layer onto the traces in the first copper layer ; patterning the second copper layer ; forming traces in the second copper layer that correspond with the traces in the first copper layer by etching through exposed portions of the second copper layer ; bonding at least one semiconductor device with at least one of the traces in the second copper layer ; encapsulating the at least one semiconductor device with a mold compound ; and bonding at least one package electrical connector with one of the first copper layer and the second copper layer ; wherein a width of the traces of the second copper layer are thinner than a width of the traces of the first copper layer by an offset distance; and plating a first copper layer on the first surface of the electrically insulative layer ; patterning the first copper layer ; removing an exposed portion of the first copper layer ; plating a second copper layer onto the first copper layer ; patterning the second copper layer ; and removing an exposed portion of the second copper layer ; wherein a distance from an edge of the electrically insulative layer to an edge of the first copper layer is smaller than a distance from the edge of the electrically insulative layer to an edge of the second copper layer . <EOS>