A method of fabricating an electrically erasable programmable nonvolatile memory cell in a memory cell region of an integrated circuit, and a logic transistor in a peripheral region of the integrated circuit outside the memory cell region , the method comprising: concurrently, in both the memory cell region and the peripheral region : forming a gate dielectric layer on a top surface of a substrate of the integrated circuit; and after forming the gate dielectric layer , depositing a gate conductor material over the gate dielectric layer ; in the memory cell region , after forming the gate conductor material : forming a trench in the substrate ; forming a vertical floating gate having a portion disposed inside the trench ; forming a source region underneath the trench in the substrate ; forming a source line adjacent to the vertical floating gate , the source line having a portion disposed inside the trench ; forming an erase gate over a portion of a tunneling dielectric layer extending over the vertical floating gate; and concurrently: in the memory cell region , forming a word line using a portion of the gate conductor material, the word line including a control gate of the electrically erasable programmable nonvolatile memory cell, and in the peripheral region , forming a transistor gate of the logic transistor . concurrently, in both the memory cell region and the peripheral region : forming a gate dielectric layer on a top surface of a substrate of the integrated circuit; and after forming the gate dielectric layer , depositing a gate conductor material over the gate dielectric layer ; forming a gate dielectric layer on a top surface of a substrate of the integrated circuit; and after forming the gate dielectric layer , depositing a gate conductor material over the gate dielectric layer ; in the memory cell region , after forming the gate conductor material : forming a trench in the substrate ; forming a vertical floating gate having a portion disposed inside the trench ; forming a source region underneath the trench in the substrate ; forming a source line adjacent to the vertical floating gate , the source line having a portion disposed inside the trench ; forming an erase gate over a portion of a tunneling dielectric layer extending over the vertical floating gate; and forming a trench in the substrate ; forming a vertical floating gate having a portion disposed inside the trench ; forming a source region underneath the trench in the substrate ; forming a source line adjacent to the vertical floating gate , the source line having a portion disposed inside the trench ; forming an erase gate over a portion of a tunneling dielectric layer extending over the vertical floating gate; and concurrently: in the memory cell region , forming a word line using a portion of the gate conductor material, the word line including a control gate of the electrically erasable programmable nonvolatile memory cell, and in the peripheral region , forming a transistor gate of the logic transistor . in the memory cell region , forming a word line using a portion of the gate conductor material, the word line including a control gate of the electrically erasable programmable nonvolatile memory cell, and in the peripheral region , forming a transistor gate of the logic transistor . <EOS>