A manufacturing method of a package substrate , comprising: providing a first copper layer and a first plating copper layer formed thereon, a first dielectric layer , a second copper layer and a second plating copper layer formed thereon, a second dielectric layer , a third copper layer and a third plating copper layer formed thereon, wherein the first dielectric layer is located between the first copper layer and the second copper layer , the second dielectric layer is located between the second plating copper layer and the third copper layer , and edges of the second copper layer are retracted a distance (D) compared to edges of the first copper layer and edges of the third copper layer ; laminating the first copper layer , the first dielectric layer , the second copper layer , the second dielectric layer and the third copper layer such that the first dielectric layer and the second dielectric layer completely encapsulate the edges of the second copper layer and the edges of the second plating copper layer thereon so as to form a temporary carrier , and wherein the edges of the first copper layer and the edges of the third copper layer are aligned to each other; forming two circuit structures (CS1, CS2) on two opposite surfaces of the temporary carrier , wherein each of the circuit structures (CS1, CS2) includes at least two patterned circuit layers , an insulation layer located between the patterned circuit layers , and a plurality of conductive through hole structures penetrating the insulation layer and electrically connected with the patterned circuit layers ; cutting the temporary carrier and the circuit structures (CS1, CS2) so as to expose the edges of the second copper layer and the edges of the second plating copper layer ; and separating the temporary carrier and the circuit structures (CS1, CS2) along the exposed edges of the second copper layer and the exposed edges of the second plating copper layer so as to form two package substrates independent from each other. providing a first copper layer and a first plating copper layer formed thereon, a first dielectric layer , a second copper layer and a second plating copper layer formed thereon, a second dielectric layer , a third copper layer and a third plating copper layer formed thereon, wherein the first dielectric layer is located between the first copper layer and the second copper layer , the second dielectric layer is located between the second plating copper layer and the third copper layer , and edges of the second copper layer are retracted a distance (D) compared to edges of the first copper layer and edges of the third copper layer ; laminating the first copper layer , the first dielectric layer , the second copper layer , the second dielectric layer and the third copper layer such that the first dielectric layer and the second dielectric layer completely encapsulate the edges of the second copper layer and the edges of the second plating copper layer thereon so as to form a temporary carrier , and wherein the edges of the first copper layer and the edges of the third copper layer are aligned to each other; forming two circuit structures (CS1, CS2) on two opposite surfaces of the temporary carrier , wherein each of the circuit structures (CS1, CS2) includes at least two patterned circuit layers , an insulation layer located between the patterned circuit layers , and a plurality of conductive through hole structures penetrating the insulation layer and electrically connected with the patterned circuit layers ; cutting the temporary carrier and the circuit structures (CS1, CS2) so as to expose the edges of the second copper layer and the edges of the second plating copper layer ; and separating the temporary carrier and the circuit structures (CS1, CS2) along the exposed edges of the second copper layer and the exposed edges of the second plating copper layer so as to form two package substrates independent from each other. <EOS>