A semiconductor device (A1, A2, A3) comprising: a first semiconductor layer having a first conductivity type (n) and made of silicon carbide; a second semiconductor layer made of silicon carbide, provided on the first semiconductor layer and having a second conductivity type (p) opposite to the first conductivity type (n); a semiconductor region made of silicon carbide, having the first conductivity type (n) and formed on the second semiconductor layer ; a trench penetrating through the semiconductor region and the second semiconductor layer to reach the first semiconductor layer ; an insulating layer formed at a bottom and a side of the trench along an inner surface of the trench ; and a gate electrode insulated by the insulating layer from the first semiconductor layer , the second semiconductor layer and the semiconductor region , at least part of the gate electrode being formed inside the trench ; wherein the second semiconductor layer includes a channel region that is along the trench and in contact with the first semiconductor layer at a first end and the semiconductor region at a second end opposite to the first end, a size of the channel region in a depth direction of the trench is 0.1 to 0.5 μm, a peak impurity concentration along a depth of the channel region is in a range of 4×10 17 cm -3 to 2×10 18 cm -3 , an impurity concentration of the second semiconductor layer initially increases starting from the second end, reaches a maximum at a predetermined depth and decreases, as proceeding from the semiconductor region toward the first semiconductor layer in the depth direction of the trench . a first semiconductor layer having a first conductivity type (n) and made of silicon carbide; a second semiconductor layer made of silicon carbide, provided on the first semiconductor layer and having a second conductivity type (p) opposite to the first conductivity type (n); a semiconductor region made of silicon carbide, having the first conductivity type (n) and formed on the second semiconductor layer ; a trench penetrating through the semiconductor region and the second semiconductor layer to reach the first semiconductor layer ; an insulating layer formed at a bottom and a side of the trench along an inner surface of the trench ; and a gate electrode insulated by the insulating layer from the first semiconductor layer , the second semiconductor layer and the semiconductor region , at least part of the gate electrode being formed inside the trench ; wherein the second semiconductor layer includes a channel region that is along the trench and in contact with the first semiconductor layer at a first end and the semiconductor region at a second end opposite to the first end, a size of the channel region in a depth direction of the trench is 0.1 to 0.5 μm, a peak impurity concentration along a depth of the channel region is in a range of 4×10 17 cm -3 to 2×10 18 cm -3 , an impurity concentration of the second semiconductor layer initially increases starting from the second end, reaches a maximum at a predetermined depth and decreases, as proceeding from the semiconductor region toward the first semiconductor layer in the depth direction of the trench . <EOS>