A silicon carbide insulating gate type semiconductor device comprising: a support substrate , a semiconductor layer of a first conductivity type formed on said support substrate, and having a first main face opposite to a side of a face in contact with said support substrate, and an electrode and an interconnection formed on said main face, said semiconductor layer including an active region formed so as to include said first main face, and a circumferential resurf region formed in a strip so as to surround a circumference of said active region and to include said first main face, said active region having a plurality of basic cells surrounded by an imaginary boundary line constituting a polygon in plan view, arranged with no gap, so as to form contact at the boundary line, each of said plurality of basic cells including a body region of a second conductivity type constituting an analogue to said polygon at said main face, said circumferential resurf region of said second conductivity type being formed to include said body region in a basic cell constituting an outermost circumference in said active region, among said plurality of basic cells, a width of a portion of said circumferential resurf region, excluding said body region, being greater than or equal to 1/2 a thickness of at least said semiconductor layer, and an average impurity concentration of said second conductivity type circumferential resurf region is higher than the average impurity concentration of said second conductivity type body region, at a surface region of said semiconductor layer as far as a depth of 0.05 μm from said first main face, said electrode includes a gate electrode located at an overlapping region between said basic cell of the outermost circumference and said circumferential resurf region and extends partially on an exposed surface of the circumferential resurf region in plan view. a support substrate , a semiconductor layer of a first conductivity type formed on said support substrate, and having a first main face opposite to a side of a face in contact with said support substrate, and an electrode and an interconnection formed on said main face, said semiconductor layer including an active region formed so as to include said first main face, and a circumferential resurf region formed in a strip so as to surround a circumference of said active region and to include said first main face, said active region having a plurality of basic cells surrounded by an imaginary boundary line constituting a polygon in plan view, arranged with no gap, so as to form contact at the boundary line, each of said plurality of basic cells including a body region of a second conductivity type constituting an analogue to said polygon at said main face, said circumferential resurf region of said second conductivity type being formed to include said body region in a basic cell constituting an outermost circumference in said active region, among said plurality of basic cells, a width of a portion of said circumferential resurf region, excluding said body region, being greater than or equal to 1/2 a thickness of at least said semiconductor layer, and an average impurity concentration of said second conductivity type circumferential resurf region is higher than the average impurity concentration of said second conductivity type body region, at a surface region of said semiconductor layer as far as a depth of 0.05 μm from said first main face, said electrode includes a gate electrode located at an overlapping region between said basic cell of the outermost circumference and said circumferential resurf region and extends partially on an exposed surface of the circumferential resurf region in plan view. <EOS>