A time to digital converter device comprising: a medium resolution delay unit including a plurality of delay buffers connected in series, the medium resolution delay unit configured to receive as inputs a reference clock signal and a data clock signal and configured to output a plurality of delayed data clock signals at taps of the plurality of delay buffers , to which the data clock signal is input, wherein the delay between the plurality of delayed data clock signals is a medium resolution delay value; a fine resolution delay unit including a plurality of cores (212-216, 300) configured to receive as inputs the reference clock signal and the plurality of delayed data clock signals from the medium resolution delay unit , wherein the plurality of cores (212-216, 300) includes: a first delay bank configured to receive one of the plurality of the delayed data clock signals and configured to apply a calibration delay value, a second delay bank configured to receive the reference clock signal , and; a fast flip flop connected to the outputs of the first delay bank and the second delay bank , wherein the output of the fast flip flop indicates a fine resolution delay value; and a controller configured to receive the output of the fast flip flop and configured, when the fast flip flop indicates that the outputs of the first delay bank and the second delay bank are not aligned, to increment the calibration delay value and to reapply the incremented calibration delay value to the first delay bank . a medium resolution delay unit including a plurality of delay buffers connected in series, the medium resolution delay unit configured to receive as inputs a reference clock signal and a data clock signal and configured to output a plurality of delayed data clock signals at taps of the plurality of delay buffers , to which the data clock signal is input, wherein the delay between the plurality of delayed data clock signals is a medium resolution delay value; a fine resolution delay unit including a plurality of cores (212-216, 300) configured to receive as inputs the reference clock signal and the plurality of delayed data clock signals from the medium resolution delay unit , wherein the plurality of cores (212-216, 300) includes: a first delay bank configured to receive one of the plurality of the delayed data clock signals and configured to apply a calibration delay value, a second delay bank configured to receive the reference clock signal , and; a fast flip flop connected to the outputs of the first delay bank and the second delay bank , wherein the output of the fast flip flop indicates a fine resolution delay value; and a first delay bank configured to receive one of the plurality of the delayed data clock signals and configured to apply a calibration delay value, a second delay bank configured to receive the reference clock signal , and; a fast flip flop connected to the outputs of the first delay bank and the second delay bank , wherein the output of the fast flip flop indicates a fine resolution delay value; and a controller configured to receive the output of the fast flip flop and configured, when the fast flip flop indicates that the outputs of the first delay bank and the second delay bank are not aligned, to increment the calibration delay value and to reapply the incremented calibration delay value to the first delay bank . <EOS>