A processor-based device comprising one or more processing elements, PEs (102 -102(P)), communicatively coupled to each other via an interconnect bus , each PE comprising: an execution pipeline (110 -110(P)) comprising a memory access stage (118 -118(P)); an instruction cache (120 -120(P)); and a store-and-invalidate logic circuit (130 -130(P)); each PE configured to: receive , by the memory access stage of the execution pipeline, an indication to perform a store-and-invalidate operation, the indication comprising a store address and store data ; and responsive to receiving the indication, perform the store-and-invalidate operation by being configured to: write , using the store-and-invalidate logic circuit, the store data to a memory location indicated by the store address; and invalidate , using the store-and-invalidate logic circuit, an instruction cache line (122 -122(C), 122'(o)-122'(C))) corresponding to the store address in the instruction cache; characterized in that each PE is configured to perform the store-and-invalidate operation atomically whereby the store-and-invalidate operation is considered successful only if both the write operation and the invalidate operation are performed successfully. an execution pipeline (110 -110(P)) comprising a memory access stage (118 -118(P)); an instruction cache (120 -120(P)); and a store-and-invalidate logic circuit (130 -130(P)); each PE configured to: receive , by the memory access stage of the execution pipeline, an indication to perform a store-and-invalidate operation, the indication comprising a store address and store data ; and responsive to receiving the indication, perform the store-and-invalidate operation by being configured to: write , using the store-and-invalidate logic circuit, the store data to a memory location indicated by the store address; and invalidate , using the store-and-invalidate logic circuit, an instruction cache line (122 -122(C), 122'(o)-122'(C))) corresponding to the store address in the instruction cache; characterized in that each PE is configured to perform the store-and-invalidate operation atomically whereby the store-and-invalidate operation is considered successful only if both the write operation and the invalidate operation are performed successfully. receive , by the memory access stage of the execution pipeline, an indication to perform a store-and-invalidate operation, the indication comprising a store address and store data ; and responsive to receiving the indication, perform the store-and-invalidate operation by being configured to: write , using the store-and-invalidate logic circuit, the store data to a memory location indicated by the store address; and invalidate , using the store-and-invalidate logic circuit, an instruction cache line (122 -122(C), 122'(o)-122'(C))) corresponding to the store address in the instruction cache; characterized in that each PE is configured to perform the store-and-invalidate operation atomically whereby the store-and-invalidate operation is considered successful only if both the write operation and the invalidate operation are performed successfully. write , using the store-and-invalidate logic circuit, the store data to a memory location indicated by the store address; and invalidate , using the store-and-invalidate logic circuit, an instruction cache line (122 -122(C), 122'(o)-122'(C))) corresponding to the store address in the instruction cache; characterized in that each PE is configured to perform the store-and-invalidate operation atomically whereby the store-and-invalidate operation is considered successful only if both the write operation and the invalidate operation are performed successfully. <EOS>