An apparatus comprising: processing circuitry ; a branch control storage ; an input interface to receive instruction execution information from the processing circuitry indicative of a sequence of instructions executed by the processing circuitry, said sequence including a branch behaviour setting instruction that indicates an identified instruction within said sequence, execution of the branch behaviour setting instruction enabling a branch behaviour to be associated with said identified instruction that causes the processing circuitry to: store branch control information for that identified instruction within the branch control storage, and branch to a target address identified by the branch behaviour setting instruction when the identified instruction is encountered in said sequence; and trace generation circuitry to generate from the instruction execution information a trace stream comprising a plurality of trace elements indicative of execution by the processing circuitry of instruction flow changing instructions within said sequence; and the trace generation circuitry further being arranged to generate, from the instruction execution information, a trace element indicative of execution behaviour of said branch behaviour setting instruction, and a trace element to indicate that said branch behaviour has been triggered when the instruction execution information indicates that a branch has occurred due to the identified instruction being encountered in the sequence at a time where branch control information for that identified instruction is stored within the branch control storage. processing circuitry ; a branch control storage ; an input interface to receive instruction execution information from the processing circuitry indicative of a sequence of instructions executed by the processing circuitry, said sequence including a branch behaviour setting instruction that indicates an identified instruction within said sequence, execution of the branch behaviour setting instruction enabling a branch behaviour to be associated with said identified instruction that causes the processing circuitry to: store branch control information for that identified instruction within the branch control storage, and branch to a target address identified by the branch behaviour setting instruction when the identified instruction is encountered in said sequence; and store branch control information for that identified instruction within the branch control storage, and branch to a target address identified by the branch behaviour setting instruction when the identified instruction is encountered in said sequence; and trace generation circuitry to generate from the instruction execution information a trace stream comprising a plurality of trace elements indicative of execution by the processing circuitry of instruction flow changing instructions within said sequence; and the trace generation circuitry further being arranged to generate, from the instruction execution information, a trace element indicative of execution behaviour of said branch behaviour setting instruction, and a trace element to indicate that said branch behaviour has been triggered when the instruction execution information indicates that a branch has occurred due to the identified instruction being encountered in the sequence at a time where branch control information for that identified instruction is stored within the branch control storage. <EOS>