A thin-film transistor array, comprising: an insulating substrate ; a gate insulating film ; a plurality of gate electrodes , and a plurality of gate wires connected to the gate electrodes , a plurality of capacitor electrodes , a plurality of capacitor wires connected to the capacitor electrodes , , a plurality of source electrodes , and a plurality of source wires connected to the source electrodes , a plurality of drain electrodes , and a plurality of pixel electrodes connected to the drain electrodes , said gate insulating film being sandwiched between: - the gate electrodes and their wires, and the capacitor electrodes and their wire on the one hand, - and the source electrodes and their wires, the drain electrodes and the pixel electrodes, on the other hand; wherein: the pixel electrodes are laid over the capacitor electrodes via the gate insulating film to have a storage capacitance; the source electrodes and the drain electrodes are laid over the gate electrodes via the gate insulating film; a semiconductor layer is provided between the source electrodes and the drain electrode; and characterized in that the thin-film transistor array further comprises a common capacitor wire to which all the capacitor wires are connected; and one resistor is serially connected to the common capacitor wire. an insulating substrate ; a gate insulating film ; a plurality of gate electrodes , and a plurality of gate wires connected to the gate electrodes , a plurality of capacitor electrodes , a plurality of capacitor wires connected to the capacitor electrodes , , a plurality of source electrodes , and a plurality of source wires connected to the source electrodes , a plurality of drain electrodes , and a plurality of pixel electrodes connected to the drain electrodes , said gate insulating film being sandwiched between: - the gate electrodes and their wires, and the capacitor electrodes and their wire on the one hand, - and the source electrodes and their wires, the drain electrodes and the pixel electrodes, on the other hand; - the gate electrodes and their wires, and the capacitor electrodes and their wire on the one hand, - and the source electrodes and their wires, the drain electrodes and the pixel electrodes, on the other hand; wherein: the pixel electrodes are laid over the capacitor electrodes via the gate insulating film to have a storage capacitance; the source electrodes and the drain electrodes are laid over the gate electrodes via the gate insulating film; a semiconductor layer is provided between the source electrodes and the drain electrode; and characterized in that the thin-film transistor array further comprises a common capacitor wire to which all the capacitor wires are connected; and one resistor is serially connected to the common capacitor wire. the pixel electrodes are laid over the capacitor electrodes via the gate insulating film to have a storage capacitance; the source electrodes and the drain electrodes are laid over the gate electrodes via the gate insulating film; a semiconductor layer is provided between the source electrodes and the drain electrode; and characterized in that the thin-film transistor array further comprises a common capacitor wire to which all the capacitor wires are connected; and one resistor is serially connected to the common capacitor wire. <EOS>