A semiconductor manufacturing method, comprising: providing a substrate , and forming a plurality of bit line structures on a surface of the substrate , each of the bit line structure comprising a bottom dielectric layer , a conductive body layer , an upper dielectric layer and a bit line contact ; and forming an inter-layer dielectric layer between two adjacent ones of the bit line structures , wherein an upper surface of the inter-layer dielectric layer is higher than upper surfaces of the bit line structures , characterized in that , the method further comprises: forming a first mask layer having an etching window, wherein the first mask layer comprises a first sub-mask layer and a second sub-mask layer , the first sub-mask layer is formed on the upper surfaces of the bit line structures and has a plurality of strip-shaped patterns extending in a first direction and spaced apart from each other, an upper surface of the first sub-mask layer is level with the upper surface of the inter-layer dielectric layer , and the second sub-mask layer is located on the upper surface of the first sub-mask layer and the upper surface of the inter-layer dielectric layer and has a plurality of strip-shaped patterns extending in a second direction perpendicular to the first direction and spaced apart from each other; and etching the inter-layer dielectric layer by using the first mask layer as a mask, to form a contact hole , wherein the contact hole exposes the surface of the substrate. providing a substrate , and forming a plurality of bit line structures on a surface of the substrate , each of the bit line structure comprising a bottom dielectric layer , a conductive body layer , an upper dielectric layer and a bit line contact ; and forming an inter-layer dielectric layer between two adjacent ones of the bit line structures , wherein an upper surface of the inter-layer dielectric layer is higher than upper surfaces of the bit line structures , characterized in that , the method further comprises: forming a first mask layer having an etching window, wherein the first mask layer comprises a first sub-mask layer and a second sub-mask layer , the first sub-mask layer is formed on the upper surfaces of the bit line structures and has a plurality of strip-shaped patterns extending in a first direction and spaced apart from each other, an upper surface of the first sub-mask layer is level with the upper surface of the inter-layer dielectric layer , and the second sub-mask layer is located on the upper surface of the first sub-mask layer and the upper surface of the inter-layer dielectric layer and has a plurality of strip-shaped patterns extending in a second direction perpendicular to the first direction and spaced apart from each other; and etching the inter-layer dielectric layer by using the first mask layer as a mask, to form a contact hole , wherein the contact hole exposes the surface of the substrate. forming a first mask layer having an etching window, wherein the first mask layer comprises a first sub-mask layer and a second sub-mask layer , the first sub-mask layer is formed on the upper surfaces of the bit line structures and has a plurality of strip-shaped patterns extending in a first direction and spaced apart from each other, an upper surface of the first sub-mask layer is level with the upper surface of the inter-layer dielectric layer , and the second sub-mask layer is located on the upper surface of the first sub-mask layer and the upper surface of the inter-layer dielectric layer and has a plurality of strip-shaped patterns extending in a second direction perpendicular to the first direction and spaced apart from each other; and etching the inter-layer dielectric layer by using the first mask layer as a mask, to form a contact hole , wherein the contact hole exposes the surface of the substrate. <EOS>