A device , comprising: a plurality of device cells at least partially disposed in a semiconductor device layer having a first conductivity type, wherein each device cell of the plurality comprises: a drift layer having the first conductivity type; an optimization layer extending from a surface of the semiconductor device layer to the drift layer and having the first conductivity type, wherein the optimization layer has an average dopant duping concentration that is greater than an average dopant concentration of the drift layer; a source region having the first conductivity type at least partially disposed within the optimization layer; a channel region having a second conductivity type at least partially disposed within the optimization layer adjacent to the source region; and a JFET region having the first conductivity type and a second dopant concentration disposed within the optimization layer between the channel regions of the plurality of device cells, wherein the JFET region has a parallel JFET width between the well region of the device cell and a parallel portion of a well region of a neighboring device cell; and a plurality of shielding regions disposed within said semiconductor device layer that lack the optimization layer, hereinafter SROLs having the first conductivity type and the first doping concentration, wherein the plurality of SROLs are at least partially disposed within a portion of the JFET region between the channel regions of neighboring device cells of the plurality of device cells, characterised in that ; the optimization layer has a retrograde doping profile that increases in dopant concentration between a first dopant concentration at a surface of the semiconductor device layer to a second concentration at a first depth from the surface of the semiconductor device layer, and maintains the second concentration between the first depth and the drift region of the semiconductor layer, wherein the second dopant concentration is between four and ten times greater than the first dopant concentration. a drift layer having the first conductivity type; an optimization layer extending from a surface of the semiconductor device layer to the drift layer and having the first conductivity type, wherein the optimization layer has an average dopant duping concentration that is greater than an average dopant concentration of the drift layer; a source region having the first conductivity type at least partially disposed within the optimization layer; a channel region having a second conductivity type at least partially disposed within the optimization layer adjacent to the source region; and a JFET region having the first conductivity type and a second dopant concentration disposed within the optimization layer between the channel regions of the plurality of device cells, wherein the JFET region has a parallel JFET width between the well region of the device cell and a parallel portion of a well region of a neighboring device cell; and a plurality of shielding regions disposed within said semiconductor device layer that lack the optimization layer, hereinafter SROLs having the first conductivity type and the first doping concentration, wherein the plurality of SROLs are at least partially disposed within a portion of the JFET region between the channel regions of neighboring device cells of the plurality of device cells, characterised in that ; the optimization layer has a retrograde doping profile that increases in dopant concentration between a first dopant concentration at a surface of the semiconductor device layer to a second concentration at a first depth from the surface of the semiconductor device layer, and maintains the second concentration between the first depth and the drift region of the semiconductor layer, wherein the second dopant concentration is between four and ten times greater than the first dopant concentration. <EOS>