A solid state image sensor (10; 102) comprising: a first semiconductor substrate provided with at least a pixel array unit in which pixels that perform photoelectric conversion are arranged in a matrix form; and a second semiconductor substrate provided with at least a control circuit unit (2; 2-1; 2-2; 2-3; 2-4; 2A-1; 2A-2; 2A-3; 2A-4) that drives the pixels , wherein the first semiconductor substrate and the second semiconductor substrate are stacked, with first surfaces on which wiring layers are formed facing each other, the pixel array unit is composed of a plurality of divided array units (1A; 1B; 1C; 1D), the control circuit unit (2; 2-1; 2-2; 2-3; 2-4; 2A-1; 2A-2; 2A-3; 2A-4) is provided corresponding to each of the plurality of divided array units (1A; 1B; 1C; 1D), and electrical connection is established in each of the divided array units (1A; 1B; 1C; 1D), through an electrode located on each of the first surfaces of the first semiconductor substrate and the second semiconductor substrate , between the pixel array unit and the control circuit unit (2; 2-1; 2-2; 2-3; 2-4; 2A-1; 2A-2; 2A-3; 2A-4), wherein the control circuit unit (2; 2-1; 2-2; 2-3; 2-4; 2A-1; 2A-2; 2A-3; 2A-4) includes a control line driver unit (2A; 2A-1; 2A-2; 2A-3; 2A-4) that drives pixel control lines (11A; 11B; 11C; 11D) arranged for respective pixel rows in the pixel array unit , and wherein the control line driver unit (2A; 2A-1; 2A-2; 2A-3; 2A-4) delivers a timing control signal referred in circuit operation, to circuit units corresponding to the respective pixel rows, in a clock tree structure, wherein the pixel control lines (11A; 11B; 11C; 11D) are grouped into blocks including a plurality of pixel control lines (11A; 11B; 11C; 11D), and the control line driver unit (2A; 2A-1; 2A-2; 2A-3; 2A-4) delivers the timing control signal to the pixel control lines (11A; 11B; 11C; 11D), with a constant delay between the blocks. a first semiconductor substrate provided with at least a pixel array unit in which pixels that perform photoelectric conversion are arranged in a matrix form; and a second semiconductor substrate provided with at least a control circuit unit (2; 2-1; 2-2; 2-3; 2-4; 2A-1; 2A-2; 2A-3; 2A-4) that drives the pixels , wherein the first semiconductor substrate and the second semiconductor substrate are stacked, with first surfaces on which wiring layers are formed facing each other, the pixel array unit is composed of a plurality of divided array units (1A; 1B; 1C; 1D), the control circuit unit (2; 2-1; 2-2; 2-3; 2-4; 2A-1; 2A-2; 2A-3; 2A-4) is provided corresponding to each of the plurality of divided array units (1A; 1B; 1C; 1D), and electrical connection is established in each of the divided array units (1A; 1B; 1C; 1D), through an electrode located on each of the first surfaces of the first semiconductor substrate and the second semiconductor substrate , between the pixel array unit and the control circuit unit (2; 2-1; 2-2; 2-3; 2-4; 2A-1; 2A-2; 2A-3; 2A-4), wherein the control circuit unit (2; 2-1; 2-2; 2-3; 2-4; 2A-1; 2A-2; 2A-3; 2A-4) includes a control line driver unit (2A; 2A-1; 2A-2; 2A-3; 2A-4) that drives pixel control lines (11A; 11B; 11C; 11D) arranged for respective pixel rows in the pixel array unit , and wherein the control line driver unit (2A; 2A-1; 2A-2; 2A-3; 2A-4) delivers a timing control signal referred in circuit operation, to circuit units corresponding to the respective pixel rows, in a clock tree structure, wherein the pixel control lines (11A; 11B; 11C; 11D) are grouped into blocks including a plurality of pixel control lines (11A; 11B; 11C; 11D), and the control line driver unit (2A; 2A-1; 2A-2; 2A-3; 2A-4) delivers the timing control signal to the pixel control lines (11A; 11B; 11C; 11D), with a constant delay between the blocks. <EOS>