A transistor, comprising: a channel layer ; a barrier layer on the channel layer; a protective layer on the barrier layer having a first opening that extends through the protective layer ; first and second ohmic contact regions on the barrier layer that are laterally adjacent to and spaced apart from the protective layer ; and a gate electrode in the first opening, wherein the gate electrode includes a first portion laterally extending on surface portions of the protective layer outside the first opening and a second portion spaced apart from the protective layer and laterally extending beyond the first portion; and a dielectric layer on the protective layer , wherein the dielectric layer and the protective layer are formed of different materials, the dielectric layer having a second opening that extends through the dielectric layer and that is wider than the first opening, wherein the dielectric layer extends between the first and second ohmic contact regions and the protective layer such that the first and second ohmic contact regions are spaced apart from the protective layer by the dielectric layer , wherein the gate electrode is in the second opening, and wherein the second portion of the gate electrode laterally extends on portions of the dielectric layer outside the second opening, wherein the first and second ohmic contact regions are at opposite sides of the gate electrode, wherein the second portion comprises second portions laterally extending in opposing directions beyond the first portion on opposite sides thereof, and wherein the channel layer and the barrier layer are configured to provide a High Electron Mobility Transistor, HEMT, and wherein an angle of sidewalls of the protective layer defining the first opening to the bottom surface of the protective layer are between 45 degrees to 90 degrees. a channel layer ; a barrier layer on the channel layer; a protective layer on the barrier layer having a first opening that extends through the protective layer ; first and second ohmic contact regions on the barrier layer that are laterally adjacent to and spaced apart from the protective layer ; and a gate electrode in the first opening, wherein the gate electrode includes a first portion laterally extending on surface portions of the protective layer outside the first opening and a second portion spaced apart from the protective layer and laterally extending beyond the first portion; and a dielectric layer on the protective layer , wherein the dielectric layer and the protective layer are formed of different materials, the dielectric layer having a second opening that extends through the dielectric layer and that is wider than the first opening, wherein the dielectric layer extends between the first and second ohmic contact regions and the protective layer such that the first and second ohmic contact regions are spaced apart from the protective layer by the dielectric layer , wherein the gate electrode is in the second opening, and wherein the second portion of the gate electrode laterally extends on portions of the dielectric layer outside the second opening, wherein the first and second ohmic contact regions are at opposite sides of the gate electrode, wherein the second portion comprises second portions laterally extending in opposing directions beyond the first portion on opposite sides thereof, and wherein the channel layer and the barrier layer are configured to provide a High Electron Mobility Transistor, HEMT, and wherein an angle of sidewalls of the protective layer defining the first opening to the bottom surface of the protective layer are between 45 degrees to 90 degrees. <EOS>