An imaging array including rows and columns of vertical detector color pixel sensors, each vertical detector color pixel sensor disposed in a row and column of the array and having individual color detectors for a number of colors ; and a readout wiring architecture comprising: a plurality of row-select lines for each row of the array, the number of row-select lines equal to the number of colors in the vertical detector color pixel sensors in the array; an individual column line for each column of the array; a transfer transistor for each individual color detector in each vertical detector color pixel sensor in the array, each transfer transistor coupled between a color detector disposed in a column of the array and a column line associated with the column of the array in which the color detector is disposed, each transfer transistor having a gate coupled to one of the plurality of row-select lines in a row of the array in which the vertical detector color pixel sensor is disposed; CHARACTERIZED in that : for a row i in the array , the transfer transistors for each color in a column j of the array are coupled to the row-select lines in a first order and the transfer transistors for each color in column j +1 are coupled to the row-select lines in a second order different from the first order; and for row i + 1 , the transfer transistors for each color in column j are coupled to the row-select lines in the first order and the transfer transistors for each color in column j +1 are coupled to the row-select lines in a third order different from the first and second orders. a plurality of row-select lines for each row of the array, the number of row-select lines equal to the number of colors in the vertical detector color pixel sensors in the array; an individual column line for each column of the array; a transfer transistor for each individual color detector in each vertical detector color pixel sensor in the array, each transfer transistor coupled between a color detector disposed in a column of the array and a column line associated with the column of the array in which the color detector is disposed, each transfer transistor having a gate coupled to one of the plurality of row-select lines in a row of the array in which the vertical detector color pixel sensor is disposed; CHARACTERIZED in that : for a row i in the array , the transfer transistors for each color in a column j of the array are coupled to the row-select lines in a first order and the transfer transistors for each color in column j +1 are coupled to the row-select lines in a second order different from the first order; and for row i + 1 , the transfer transistors for each color in column j are coupled to the row-select lines in the first order and the transfer transistors for each color in column j +1 are coupled to the row-select lines in a third order different from the first and second orders. for a row i in the array , the transfer transistors for each color in a column j of the array are coupled to the row-select lines in a first order and the transfer transistors for each color in column j +1 are coupled to the row-select lines in a second order different from the first order; and for row i + 1 , the transfer transistors for each color in column j are coupled to the row-select lines in the first order and the transfer transistors for each color in column j +1 are coupled to the row-select lines in a third order different from the first and second orders. <EOS>