A wafer manufacturing method, comprising: providing a wafer body on which a scribe lane is provided for dicing; and forming dicing through-silicon-vias at the scribe lane to form a dicing line, wherein the dicing through-silicon-vias are filled with a protective material, wherein the method further comprises: stacking a first wafer body and a second wafer body , and then forming the dicing through-silicon-vias at the scribe lane , characterized in that , forming the dicing through-silicon-vias at the scribe lane comprises the steps of: forming first dicing through-silicon-vias at a scribe lane of the first wafer body to expose the second wafer ; filling the protective material into the first dicing through-silicon-vias ; forming second dicing through-silicon-vias at a scribe lane of the second wafer body at positions aligned with the first dicing through-silicon-vias to expose the first dicing through-silicon-vias , after filling the protective material into the first through-silicon-vias ; and filling the protective material into the second dicing through-silicon-vias . providing a wafer body on which a scribe lane is provided for dicing; and forming dicing through-silicon-vias at the scribe lane to form a dicing line, wherein the dicing through-silicon-vias are filled with a protective material, wherein the method further comprises: stacking a first wafer body and a second wafer body , and then forming the dicing through-silicon-vias at the scribe lane , characterized in that , forming the dicing through-silicon-vias at the scribe lane comprises the steps of: forming first dicing through-silicon-vias at a scribe lane of the first wafer body to expose the second wafer ; filling the protective material into the first dicing through-silicon-vias ; forming second dicing through-silicon-vias at a scribe lane of the second wafer body at positions aligned with the first dicing through-silicon-vias to expose the first dicing through-silicon-vias , after filling the protective material into the first through-silicon-vias ; and filling the protective material into the second dicing through-silicon-vias . stacking a first wafer body and a second wafer body , and then forming the dicing through-silicon-vias at the scribe lane , characterized in that , forming the dicing through-silicon-vias at the scribe lane comprises the steps of: forming first dicing through-silicon-vias at a scribe lane of the first wafer body to expose the second wafer ; filling the protective material into the first dicing through-silicon-vias ; forming second dicing through-silicon-vias at a scribe lane of the second wafer body at positions aligned with the first dicing through-silicon-vias to expose the first dicing through-silicon-vias , after filling the protective material into the first through-silicon-vias ; and filling the protective material into the second dicing through-silicon-vias . forming first dicing through-silicon-vias at a scribe lane of the first wafer body to expose the second wafer ; filling the protective material into the first dicing through-silicon-vias ; forming second dicing through-silicon-vias at a scribe lane of the second wafer body at positions aligned with the first dicing through-silicon-vias to expose the first dicing through-silicon-vias , after filling the protective material into the first through-silicon-vias ; and filling the protective material into the second dicing through-silicon-vias . <EOS>