A multiplexer for fine-grain power gating comprising: a first supply voltage input to receive a first supply voltage and a second supply voltage input to receive a second supply voltage, where the first supply voltage is greater than the second supply voltage; a plurality of inputs ; a plurality of selection inputs; a selection circuitry configured to select one of the plurality of inputs based upon the plurality of selection inputs, wherein the selection circuitry includes a plurality of pass transistors including a first power gate pass transistor, wherein each pass transistor includes an input which is associated with and coupled to one of the plurality of inputs and a gate which is associated with and coupled to one of the plurality of selection inputs, where one of the plurality of inputs is the first supply voltage which is coupled to the first power gate pass transistor and one of the selection inputs is a power gating enable input which is coupled to the first power gate pass transistor to enable the first power gate pass transistor; an output inverter stage, coupled to outputs of the plurality of transistors of the selection circuitry, comprising a PMOS transistor and an NMOS transistor connected in series between the second supply voltage and a reference voltage, where at least one input to the output inverter stage is provided to the gates of the PMOS and NMOS transistors and the connection between the PMOS and NMOS transistors forms an inverted output; wherein the selection circuitry is configured so that selection of the power gating enable signal applies the first supply voltage to the gate of the PMOS transistor and places the PMOS transistor in a cutoff mode of operation; and wherein the reference voltage is ground. a first supply voltage input to receive a first supply voltage and a second supply voltage input to receive a second supply voltage, where the first supply voltage is greater than the second supply voltage; a plurality of inputs ; a plurality of selection inputs; a selection circuitry configured to select one of the plurality of inputs based upon the plurality of selection inputs, wherein the selection circuitry includes a plurality of pass transistors including a first power gate pass transistor, wherein each pass transistor includes an input which is associated with and coupled to one of the plurality of inputs and a gate which is associated with and coupled to one of the plurality of selection inputs, where one of the plurality of inputs is the first supply voltage which is coupled to the first power gate pass transistor and one of the selection inputs is a power gating enable input which is coupled to the first power gate pass transistor to enable the first power gate pass transistor; an output inverter stage, coupled to outputs of the plurality of transistors of the selection circuitry, comprising a PMOS transistor and an NMOS transistor connected in series between the second supply voltage and a reference voltage, where at least one input to the output inverter stage is provided to the gates of the PMOS and NMOS transistors and the connection between the PMOS and NMOS transistors forms an inverted output; wherein the selection circuitry is configured so that selection of the power gating enable signal applies the first supply voltage to the gate of the PMOS transistor and places the PMOS transistor in a cutoff mode of operation; and wherein the reference voltage is ground. <EOS>