An integrated circuit comprising: first circuitry including: a first state machine configured to transition among first states based on both a request for power and a request for a first clock signal each on behalf of a first port controller, the first state machine further to generate a first control signal; a second state machine configured to transition among second states based on a request for a second clock signal on behalf of the first port controller, wherein a first frequency of the first clock signal is greater than a second frequency of the second clock signal, the second state machine further to generate a second control signal; and first clock control logic responsive to the first control signal to transmit the first clock signal toward the first port controller, and further responsive to the second control signal to transmit the second clock signal toward the first port controller; and a third state machine configured to transition among third states based on requests from the first state machine and the second state machine, the third state machine to send from the first circuitry to physical layer circuitry requests on behalf of the first port controller. first circuitry including: a first state machine configured to transition among first states based on both a request for power and a request for a first clock signal each on behalf of a first port controller, the first state machine further to generate a first control signal; a second state machine configured to transition among second states based on a request for a second clock signal on behalf of the first port controller, wherein a first frequency of the first clock signal is greater than a second frequency of the second clock signal, the second state machine further to generate a second control signal; and first clock control logic responsive to the first control signal to transmit the first clock signal toward the first port controller, and further responsive to the second control signal to transmit the second clock signal toward the first port controller; and a first state machine configured to transition among first states based on both a request for power and a request for a first clock signal each on behalf of a first port controller, the first state machine further to generate a first control signal; a second state machine configured to transition among second states based on a request for a second clock signal on behalf of the first port controller, wherein a first frequency of the first clock signal is greater than a second frequency of the second clock signal, the second state machine further to generate a second control signal; and first clock control logic responsive to the first control signal to transmit the first clock signal toward the first port controller, and further responsive to the second control signal to transmit the second clock signal toward the first port controller; and a third state machine configured to transition among third states based on requests from the first state machine and the second state machine, the third state machine to send from the first circuitry to physical layer circuitry requests on behalf of the first port controller. <EOS>