A computer-implemented method for simulating a set of instructions to be executed on an out-of-order processor, the method comprising performing a performance simulation of the processor over a number of simulation cycles, wherein performing the performance simulation of the processor comprises - obtaining from a storage or an input port a set of instructions and a processing architecture of the processor for which the simulation is to be made, - modeling an instruction window of a predetermined maximum size for the cycle, the maximum size being the maximum number of instructions actively processed in parallel; said modeling comprising modeling, in a frontend component, branch prediction and instruction cache providing instructions to the instruction window, - inserting said instructions obtained from the frontend component into the instruction window, and modeling the progress of the instructions in the instruction window from inserting the instruction until it is fully executed and can commit and leave the instruction window, - recording an estimation of the timing of the instructions, - generating the number of instructions processed in a period of time, and - deriving a performance parameter of the processor, being a timing of the execution of the set of instructions, from the estimation of the timing of the instructions and the number of instructions processed in the period of time including the time during which the frontend component is stalled and no instructions can be inserted in the instruction window due to branch misprediction or cache misses, due to lack of instructions to be dispatched or due to the instruction window being full, the performance parameter of the processor being produced without modeling a reorder buffer, issue queue(s), register renaming, load-store queue(s) and other buffers of the processor. - obtaining from a storage or an input port a set of instructions and a processing architecture of the processor for which the simulation is to be made, - modeling an instruction window of a predetermined maximum size for the cycle, the maximum size being the maximum number of instructions actively processed in parallel; said modeling comprising modeling, in a frontend component, branch prediction and instruction cache providing instructions to the instruction window, - inserting said instructions obtained from the frontend component into the instruction window, and modeling the progress of the instructions in the instruction window from inserting the instruction until it is fully executed and can commit and leave the instruction window, - recording an estimation of the timing of the instructions, - generating the number of instructions processed in a period of time, and - deriving a performance parameter of the processor, being a timing of the execution of the set of instructions, from the estimation of the timing of the instructions and the number of instructions processed in the period of time including the time during which the frontend component is stalled and no instructions can be inserted in the instruction window due to branch misprediction or cache misses, due to lack of instructions to be dispatched or due to the instruction window being full, the performance parameter of the processor being produced without modeling a reorder buffer, issue queue(s), register renaming, load-store queue(s) and other buffers of the processor. <EOS>