A memory device, comprising: a substrate of semiconductor material; a plurality of memory cells formed on the substrate and arranged in an array of rows and columns, wherein the rows of the memory cells are arranged in alternating even and odd numbered rows; each of the memory cells includes: spaced apart source and drain regions in the substrate, with a channel region in the substrate extending there between, a floating gate disposed over and insulated from a first portion of the channel region adjacent the source region, and a control gate disposed over and insulated from a second portion of the channel region adjacent the drain region; each of the rows of memory cells includes a source line that electrically connects together all the source regions for the row of memory cells; each of the columns of memory cells includes a bit line that electrically connects together all the drain regions for the column of memory cells; characterised in that each of the columns of memory cells includes a first control gate line that electrically connects together all the control gates of the memory cells in the column of memory cells that are in the odd numbered rows of the memory cells and that is not electrically connected to the control gates of the memory cells in the column of memory cells that are in the even numbered rows of the memory cells; and each of the columns of memory cells includes a second control gate line that electrically connects together all the control gates of the memory cells in the column of memory cells that are in the even numbered rows of the memory cells and that is not electrically connected to the control gates of the memory cells in the column of memory cells that are in the odd numbered rows of the memory cells. a substrate of semiconductor material; a plurality of memory cells formed on the substrate and arranged in an array of rows and columns, wherein the rows of the memory cells are arranged in alternating even and odd numbered rows; each of the memory cells includes: spaced apart source and drain regions in the substrate, with a channel region in the substrate extending there between, a floating gate disposed over and insulated from a first portion of the channel region adjacent the source region, and a control gate disposed over and insulated from a second portion of the channel region adjacent the drain region; spaced apart source and drain regions in the substrate, with a channel region in the substrate extending there between, a floating gate disposed over and insulated from a first portion of the channel region adjacent the source region, and a control gate disposed over and insulated from a second portion of the channel region adjacent the drain region; each of the rows of memory cells includes a source line that electrically connects together all the source regions for the row of memory cells; each of the columns of memory cells includes a bit line that electrically connects together all the drain regions for the column of memory cells; each of the columns of memory cells includes a first control gate line that electrically connects together all the control gates of the memory cells in the column of memory cells that are in the odd numbered rows of the memory cells and that is not electrically connected to the control gates of the memory cells in the column of memory cells that are in the even numbered rows of the memory cells; and each of the columns of memory cells includes a second control gate line that electrically connects together all the control gates of the memory cells in the column of memory cells that are in the even numbered rows of the memory cells and that is not electrically connected to the control gates of the memory cells in the column of memory cells that are in the odd numbered rows of the memory cells. <EOS>