A power conversion device comprising: a three-level inverter circuit including a plurality of semiconductor switching elements; and an inverter control circuit outputting a gate signal to driving the three-level inverter circuit in a double carrier modulation manner, the inverter control circuit including a command value calculating part generating three-phase output voltage command values (V ∗ u1 , V ∗ v1 , V ∗ w1 ) having one AC voltage command value and other two AC voltage command values based on an output current and an output voltage from the three-level inverter circuit , a command value correcting part outputting corrected command values (V ∗ u2 , V ∗ v2 , V ∗ w2 ) by correcting the three-phase output voltage command values (V ∗ u1 , V ∗ v1 , V ∗ w1 ), and a gate signal generating part generating the gate signal based on the corrected command values (V ∗ u2 , V ∗ v2 , V ∗ w2 ), characterized in that the command value correcting part is configured to, during a dead band passage period (T DB ) in which the one AC voltage command value passes through a dead band (DB) predetermined around a zero value of a voltage command value, output a predetermined voltage command value (V DB ) corresponding to one of an upper limit value (V DBH ) or a lower limit value (V DBL ) of the dead band (DB) instead of the one AC voltage command value, and to add a difference (ΔV ∗ ) between the one AC voltage command value and the predetermined voltage command value (V DB ) in the dead band passage period (T DB ) to each of the other two AC voltage command values such that a phase-to-phase voltage in the three phases is held. a three-level inverter circuit including a plurality of semiconductor switching elements; and an inverter control circuit outputting a gate signal to driving the three-level inverter circuit in a double carrier modulation manner, the inverter control circuit including a command value calculating part generating three-phase output voltage command values (V ∗ u1 , V ∗ v1 , V ∗ w1 ) having one AC voltage command value and other two AC voltage command values based on an output current and an output voltage from the three-level inverter circuit , a command value correcting part outputting corrected command values (V ∗ u2 , V ∗ v2 , V ∗ w2 ) by correcting the three-phase output voltage command values (V ∗ u1 , V ∗ v1 , V ∗ w1 ), and a gate signal generating part generating the gate signal based on the corrected command values (V ∗ u2 , V ∗ v2 , V ∗ w2 ), a command value calculating part generating three-phase output voltage command values (V ∗ u1 , V ∗ v1 , V ∗ w1 ) having one AC voltage command value and other two AC voltage command values based on an output current and an output voltage from the three-level inverter circuit , a command value correcting part outputting corrected command values (V ∗ u2 , V ∗ v2 , V ∗ w2 ) by correcting the three-phase output voltage command values (V ∗ u1 , V ∗ v1 , V ∗ w1 ), and a gate signal generating part generating the gate signal based on the corrected command values (V ∗ u2 , V ∗ v2 , V ∗ w2 ), characterized in that the command value correcting part is configured to, during a dead band passage period (T DB ) in which the one AC voltage command value passes through a dead band (DB) predetermined around a zero value of a voltage command value, output a predetermined voltage command value (V DB ) corresponding to one of an upper limit value (V DBH ) or a lower limit value (V DBL ) of the dead band (DB) instead of the one AC voltage command value, and to add a difference (ΔV ∗ ) between the one AC voltage command value and the predetermined voltage command value (V DB ) in the dead band passage period (T DB ) to each of the other two AC voltage command values such that a phase-to-phase voltage in the three phases is held. <EOS>