An amplifier , comprising: an input stage , configured to receive an input signal to generate an amplified signal; an amplifier stage , coupled to the input stage , configured to generate a first driving signal and a second driving signal according to the amplified signal; a power stage comprising a first input terminal and a second input terminal, wherein the power stage is coupled to a supply voltage and a ground voltage, configured to receive the first driving signal and the second driving signal from the first input terminal and the second input terminal, respectively, and to generate an output signal; and a de-gain stage , coupled to the power stage , configured to generate a first control signal to the first input terminal according to the second driving signal; the power stage further comprises a P-type transistor and an N-type transistor; and the P-type transistor is coupled between the supply voltage and an output terminal, the N-type transistor is coupled between the output terminal and the ground voltage, the P-type transistor receives the first driving signal from the first input terminal, and the N-type transistor receives the second driving signal from the second input terminal, to generate the output signal; and characterized in that the de-gain stage comprises: a first low-pass filter , configured to filter the second driving signal to generate a filtered second driving signal; and a first control circuit , coupled to the first low-pass filter , configured to generate the first control signal to the first input terminal of the power stage to limit a swing of the first driving signal according to filtered second driving signal. an input stage , configured to receive an input signal to generate an amplified signal; an amplifier stage , coupled to the input stage , configured to generate a first driving signal and a second driving signal according to the amplified signal; a power stage comprising a first input terminal and a second input terminal, wherein the power stage is coupled to a supply voltage and a ground voltage, configured to receive the first driving signal and the second driving signal from the first input terminal and the second input terminal, respectively, and to generate an output signal; and a de-gain stage , coupled to the power stage , configured to generate a first control signal to the first input terminal according to the second driving signal; the power stage further comprises a P-type transistor and an N-type transistor; and the P-type transistor is coupled between the supply voltage and an output terminal, the N-type transistor is coupled between the output terminal and the ground voltage, the P-type transistor receives the first driving signal from the first input terminal, and the N-type transistor receives the second driving signal from the second input terminal, to generate the output signal; and characterized in that the de-gain stage comprises: a first low-pass filter , configured to filter the second driving signal to generate a filtered second driving signal; and a first control circuit , coupled to the first low-pass filter , configured to generate the first control signal to the first input terminal of the power stage to limit a swing of the first driving signal according to filtered second driving signal. a first low-pass filter , configured to filter the second driving signal to generate a filtered second driving signal; and a first control circuit , coupled to the first low-pass filter , configured to generate the first control signal to the first input terminal of the power stage to limit a swing of the first driving signal according to filtered second driving signal. <EOS>