A method of memory power reduction by an apparatus , comprising: determining whether to store data into a dynamic random-access memory , DRAM), or a non-volatile random-access memory , NVRAM, based on a power consumption by the DRAM in association with refreshing the data in the DRAM and use of the data stored in the DRAM by a processor, based on a power consumption by the NVRAM in association with use of the data stored in the NVRAM by the processor, and based on current drawn by the DRAM, or NVRAM, respectively, in association with the data in a first power state of the processor during a duty cycle and current drawn by the DRAM, or NVRAM, respectively, in association with the data in a second power state of the processor, wherein the data within the DRAM and/or NVRAM is accessed during the first power state, and the data within the DRAM and/or NVRAM is not accessed during the second power state, the NVRAM being a type of random-access memory other than flash memory; and storing the data into one of the DRAM or the NVRAM based on the determination whether to store the data in the DRAM or the NVRAM; wherein the determination whether to store the data in the DRAM or the NVRAM further comprises: determining a use case for the data; and accessing a table associated with use cases to determine whether to store the data in the NVRAM or the DRAM based on the determined use case, and determining that a use case is not included in the table; and based on whether the use case consumes more or less power in the DRAM or the NVRAM, listing the use case in the table with information indicating whether the DRAM or the NVRAM should be used in association with the use case. determining whether to store data into a dynamic random-access memory , DRAM), or a non-volatile random-access memory , NVRAM, based on a power consumption by the DRAM in association with refreshing the data in the DRAM and use of the data stored in the DRAM by a processor, based on a power consumption by the NVRAM in association with use of the data stored in the NVRAM by the processor, and based on current drawn by the DRAM, or NVRAM, respectively, in association with the data in a first power state of the processor during a duty cycle and current drawn by the DRAM, or NVRAM, respectively, in association with the data in a second power state of the processor, wherein the data within the DRAM and/or NVRAM is accessed during the first power state, and the data within the DRAM and/or NVRAM is not accessed during the second power state, the NVRAM being a type of random-access memory other than flash memory; and storing the data into one of the DRAM or the NVRAM based on the determination whether to store the data in the DRAM or the NVRAM; wherein the determination whether to store the data in the DRAM or the NVRAM further comprises: determining a use case for the data; and accessing a table associated with use cases to determine whether to store the data in the NVRAM or the DRAM based on the determined use case, and determining a use case for the data; and accessing a table associated with use cases to determine whether to store the data in the NVRAM or the DRAM based on the determined use case, and determining that a use case is not included in the table; and based on whether the use case consumes more or less power in the DRAM or the NVRAM, listing the use case in the table with information indicating whether the DRAM or the NVRAM should be used in association with the use case. <EOS>