A processor comprising: a plurality of first cores to independently execute instructions, each of the plurality of first cores including a plurality of counters to store performance information; a power controller to receive performance information from at least some of the plurality of counters, whereby the processor further comprises: at least one second memory-optimized core which is optimized to perform memory operations effectively by operating at a low frequency saturating memory resources, the at least one second memory-optimized core comprising a shorter pipeline than the first cores; and the power controller configured to determine a memory bound workload type executed on the processor based at least in part on the performance information including detecting a low instruction per second and a high memory bandwidth characteristic, and based on the determination of a memory bound workload type dynamically migrate one or more threads from one or more of the plurality of first cores to the at least one second memory-optimized core for execution during a next operation interval, wherein the at least one second memory-optimized core is heterogeneous to the plurality of first cores and includes a first plurality of hardware thread resources, a number of the first plurality of hardware thread resources equal to a number of hardware thread resources of the plurality of first cores collectively. a plurality of first cores to independently execute instructions, each of the plurality of first cores including a plurality of counters to store performance information; a power controller to receive performance information from at least some of the plurality of counters, whereby the processor further comprises: at least one second memory-optimized core which is optimized to perform memory operations effectively by operating at a low frequency saturating memory resources, the at least one second memory-optimized core comprising a shorter pipeline than the first cores; and the power controller configured to determine a memory bound workload type executed on the processor based at least in part on the performance information including detecting a low instruction per second and a high memory bandwidth characteristic, and based on the determination of a memory bound workload type dynamically migrate one or more threads from one or more of the plurality of first cores to the at least one second memory-optimized core for execution during a next operation interval, wherein the at least one second memory-optimized core is heterogeneous to the plurality of first cores and includes a first plurality of hardware thread resources, a number of the first plurality of hardware thread resources equal to a number of hardware thread resources of the plurality of first cores collectively. at least one second memory-optimized core which is optimized to perform memory operations effectively by operating at a low frequency saturating memory resources, the at least one second memory-optimized core comprising a shorter pipeline than the first cores; and the power controller configured to determine a memory bound workload type executed on the processor based at least in part on the performance information including detecting a low instruction per second and a high memory bandwidth characteristic, and based on the determination of a memory bound workload type dynamically migrate one or more threads from one or more of the plurality of first cores to the at least one second memory-optimized core for execution during a next operation interval, wherein the at least one second memory-optimized core is heterogeneous to the plurality of first cores and includes a first plurality of hardware thread resources, a number of the first plurality of hardware thread resources equal to a number of hardware thread resources of the plurality of first cores collectively. <EOS>