A method of current integration, comprising: in a first conversion stage, during an integration time (Tint), transforming an input current (I in ) into an output integrated voltage (V out_int ) using a parallel connection of an operational transconductance amplifier (OTA) and an integration capacitor (C int ), reducing the output integrated voltage (V out_int ) by repeatedly discharging the integration capacitor (C int ) through a feedback loop via a digital-to-analog converter (DAC, SC DAC1) generating feedback pulses, and in a second conversion stage, after the integration time (Tint), sampling an output voltage residue (v residue ) during a sampling time (T sample ), wherein power saving is provided by either - applying a feedback clock period (T clk_DAC ) defining time intervals between successive rising edges of the feedback pulses, and sampling the output voltage residue (V residue ) of the current integrator during an extended feedback clock period (T*) after a lapse of a plurality of feedback clock periods (T clk_DAC ) and after a range check for the output integrated voltage (V out_int ), the range check being based on a number of feedback pulses prior to sampling, wherein the extended feedback clock period (T*) is provided if the result of the range check indicates that the input current is below half range, or - applying an electric power (P) for the operational transconductance amplifier (OTA), and elevating the applied electric power (P) only in a last cycle during the sampling time (T sample ) for sampling the output voltage residue (V residue ). in a first conversion stage, during an integration time (Tint), transforming an input current (I in ) into an output integrated voltage (V out_int ) using a parallel connection of an operational transconductance amplifier (OTA) and an integration capacitor (C int ), reducing the output integrated voltage (V out_int ) by repeatedly discharging the integration capacitor (C int ) through a feedback loop via a digital-to-analog converter (DAC, SC DAC1) generating feedback pulses, and in a second conversion stage, after the integration time (Tint), sampling an output voltage residue (v residue ) during a sampling time (T sample ), wherein power saving is provided by either - applying a feedback clock period (T clk_DAC ) defining time intervals between successive rising edges of the feedback pulses, and sampling the output voltage residue (V residue ) of the current integrator during an extended feedback clock period (T*) after a lapse of a plurality of feedback clock periods (T clk_DAC ) and after a range check for the output integrated voltage (V out_int ), the range check being based on a number of feedback pulses prior to sampling, wherein the extended feedback clock period (T*) is provided if the result of the range check indicates that the input current is below half range, or - applying an electric power (P) for the operational transconductance amplifier (OTA), and elevating the applied electric power (P) only in a last cycle during the sampling time (T sample ) for sampling the output voltage residue (V residue ). - applying a feedback clock period (T clk_DAC ) defining time intervals between successive rising edges of the feedback pulses, and sampling the output voltage residue (V residue ) of the current integrator during an extended feedback clock period (T*) after a lapse of a plurality of feedback clock periods (T clk_DAC ) and after a range check for the output integrated voltage (V out_int ), the range check being based on a number of feedback pulses prior to sampling, wherein the extended feedback clock period (T*) is provided if the result of the range check indicates that the input current is below half range, or - applying an electric power (P) for the operational transconductance amplifier (OTA), and elevating the applied electric power (P) only in a last cycle during the sampling time (T sample ) for sampling the output voltage residue (V residue ). <EOS>