An apparatus, comprising: a central processing unit, CPU, core ; a first memory cache to store instructions for execution by the CPU core; a second memory cache to store instructions for execution by the CPU core, the second memory cache to retrieve instructions responsive to a miss in the first memory cache; and a memory controller subsystem coupled to the CPU core and the first and second memory caches, the memory controller subsystem is configured to: speculatively determine a hit or miss condition of a first virtual address in the first memory cache; speculatively translate the first virtual address to a physical address; characterised in that the memory controller is configured to: associated with the hit or miss condition and the physical address, configure a status to a valid state; responsive to receipt of a first indication from the CPU core that no program instructions associated with the first virtual address are needed, reconfigure the status to an invalid state; and responsive to receipt of a second indication from the CPU core that a program instruction associated with the first virtual address is needed, reconfigure the status back to a valid state. a central processing unit, CPU, core ; a first memory cache to store instructions for execution by the CPU core; a second memory cache to store instructions for execution by the CPU core, the second memory cache to retrieve instructions responsive to a miss in the first memory cache; and a memory controller subsystem coupled to the CPU core and the first and second memory caches, the memory controller subsystem is configured to: speculatively determine a hit or miss condition of a first virtual address in the first memory cache; speculatively translate the first virtual address to a physical address; characterised in that the memory controller is configured to: associated with the hit or miss condition and the physical address, configure a status to a valid state; responsive to receipt of a first indication from the CPU core that no program instructions associated with the first virtual address are needed, reconfigure the status to an invalid state; and responsive to receipt of a second indication from the CPU core that a program instruction associated with the first virtual address is needed, reconfigure the status back to a valid state. speculatively determine a hit or miss condition of a first virtual address in the first memory cache; speculatively translate the first virtual address to a physical address; characterised in that the memory controller is configured to: associated with the hit or miss condition and the physical address, configure a status to a valid state; responsive to receipt of a first indication from the CPU core that no program instructions associated with the first virtual address are needed, reconfigure the status to an invalid state; and responsive to receipt of a second indication from the CPU core that a program instruction associated with the first virtual address is needed, reconfigure the status back to a valid state. associated with the hit or miss condition and the physical address, configure a status to a valid state; responsive to receipt of a first indication from the CPU core that no program instructions associated with the first virtual address are needed, reconfigure the status to an invalid state; and responsive to receipt of a second indication from the CPU core that a program instruction associated with the first virtual address is needed, reconfigure the status back to a valid state. <EOS>