A method of implementing a debugging system, the method comprising: compiling a representation of a source circuit including source logic including one or more source subchannels associated with source logic portions , each source logic portion driven by one of a plurality of clocks, each source subchannel generating packets carrying signal data from one of the source logic portions, where each source subchannel carries the packets from one of the source logic portions; compiling a representation of a destination circuit including destination logic including one or more destination subchannels associated with destination logic portions replicating the source logic, each destination subchannel fowarding the signal data via the packets to one of the destination logic portions, where each destination subchannel carries the packets associated with one of the destination logic portions; configuring a switching logic mapping the source subchannels to the destination subchannels as virtual channels to forward the packets from the source subchannels to the destination subchannels; and configuring, in a deep buffer memory, a single queue coupled to the switching logic to record packets from the source subchannels into a packet stream for a delay period to distribute to the destination subchannels for the destination logic to emulate the source logic synchronized with the plurality of clocks delayed by the delay period, the single queue recording signal traces for debugging the source logic, wherein the packets have a packet format including a header field and a payload field, the header field to carry channel identifiers identifying the virtual channels and the payload field to carry the signal data, wherein each packet includes one of the channel identifiers identifying one of the virtual channels mapping a source subchannel from the one or more source subchannels to one of the destination subchannels. compiling a representation of a source circuit including source logic including one or more source subchannels associated with source logic portions , each source logic portion driven by one of a plurality of clocks, each source subchannel generating packets carrying signal data from one of the source logic portions, where each source subchannel carries the packets from one of the source logic portions; compiling a representation of a destination circuit including destination logic including one or more destination subchannels associated with destination logic portions replicating the source logic, each destination subchannel fowarding the signal data via the packets to one of the destination logic portions, where each destination subchannel carries the packets associated with one of the destination logic portions; configuring a switching logic mapping the source subchannels to the destination subchannels as virtual channels to forward the packets from the source subchannels to the destination subchannels; and configuring, in a deep buffer memory, a single queue coupled to the switching logic to record packets from the source subchannels into a packet stream for a delay period to distribute to the destination subchannels for the destination logic to emulate the source logic synchronized with the plurality of clocks delayed by the delay period, the single queue recording signal traces for debugging the source logic, wherein the packets have a packet format including a header field and a payload field, the header field to carry channel identifiers identifying the virtual channels and the payload field to carry the signal data, wherein each packet includes one of the channel identifiers identifying one of the virtual channels mapping a source subchannel from the one or more source subchannels to one of the destination subchannels. <EOS>