A high electron mobility transistor (HEMT), comprising: a plurality of active semiconductor layers formed on a substrate, wherein said active layers comprise a buffer layer, a barrier layer and a 2DEG; a source contact formed in electrical contact with said plurality of active layers; a drain contact also in electrical contact with said plurality of active layers with space between said source and drain contacts on the topmost of said plurality of active layers; a gate in electrical contact with said topmost of said plurality of active layers, between said source and drain contacts; a spacer layer on and covering the surface of the topmost of said plurality of active layers, between said gate and said source and drain contacts, wherein said gate is not covered by said spacer layer and wherein said spacer layer comprises a plurality of spacer layers comprising a first spacer layer between the gate and the source and between the gate and the drain, and at least a further spacer layer, comprising a second spacer layer, on the first spacer layer between the gate and the drain, the plurality of spacer layers forming a step arrangement between said gate and said drain contact; and a field plate formed on said spacer layer and integral with said gate, wherein said field plate extends on said first spacer layer toward said source and wherein said field plate is on said spacer layer step arrangement between said gate and said drain, said field plate comprising a plurality of field plate portions between said gate and drain, each of which has a different distance between it and the topmost of said plurality of active layers. a plurality of active semiconductor layers formed on a substrate, wherein said active layers comprise a buffer layer, a barrier layer and a 2DEG; a source contact formed in electrical contact with said plurality of active layers; a drain contact also in electrical contact with said plurality of active layers with space between said source and drain contacts on the topmost of said plurality of active layers; a gate in electrical contact with said topmost of said plurality of active layers, between said source and drain contacts; a spacer layer on and covering the surface of the topmost of said plurality of active layers, between said gate and said source and drain contacts, wherein said gate is not covered by said spacer layer and wherein said spacer layer comprises a plurality of spacer layers comprising a first spacer layer between the gate and the source and between the gate and the drain, and at least a further spacer layer, comprising a second spacer layer, on the first spacer layer between the gate and the drain, the plurality of spacer layers forming a step arrangement between said gate and said drain contact; and a field plate formed on said spacer layer and integral with said gate, wherein said field plate extends on said first spacer layer toward said source and wherein said field plate is on said spacer layer step arrangement between said gate and said drain, said field plate comprising a plurality of field plate portions between said gate and drain, each of which has a different distance between it and the topmost of said plurality of active layers. <EOS>