A latch circuit , comprising: an input stage , for receiving at least a clock signal and a data control signal; an amplifying stage (MN1, MN2, MP1, MP2), coupled to the input stage and supplied by a supply voltage and a ground voltage, for outputting a data value according to the clock signal and the data control signal; and a clock gating circuit , coupled to the amplifying stage (MN1, MN2, MP1, MP2), for disconnecting a path between the supply voltage and the ground voltage while the clock signal has a state transition, wherein the amplifying stage (MN1, MN2, MP1, MP2) comprises: a first N-type metal-oxide-semiconductor (NMOS) (MN1) and a second NMOS (MN2), wherein source electrodes of the first NMOS (MN1) and the second NMOS (MN2) are coupled to the ground voltage; a first P-type metal-oxide-semiconductor (PMOS) (MP1) and a second PMOS (MP2), wherein source electrodes of the first PMOS (MP1) and the second PMOS (MP2) are coupled to the supply voltage; and differential output terminals (N1, N2) comprising a first output terminal (N1) and a second output terminal (N2), wherein the first output terminal (N1) is coupled to gate electrodes of the first NMOS (MN1) and the first PMOS (MP1), and the second output terminal (N2) is coupled to gate electrodes of the second NMOS (MN2) and the second PMOS (MP2); characterized in that the clock gating circuit is arranged to selectively couple the first output terminal (N1) to drain electrodes of the second NMOS (MN2) and the second PMOS (MP2), and to selectively couple the second output terminal (N2) to drain electrodes of the first NMOS (MN1) and the first PMOS (MP1). an input stage , for receiving at least a clock signal and a data control signal; an amplifying stage (MN1, MN2, MP1, MP2), coupled to the input stage and supplied by a supply voltage and a ground voltage, for outputting a data value according to the clock signal and the data control signal; and a clock gating circuit , coupled to the amplifying stage (MN1, MN2, MP1, MP2), for disconnecting a path between the supply voltage and the ground voltage while the clock signal has a state transition, wherein the amplifying stage (MN1, MN2, MP1, MP2) comprises: a first N-type metal-oxide-semiconductor (NMOS) (MN1) and a second NMOS (MN2), wherein source electrodes of the first NMOS (MN1) and the second NMOS (MN2) are coupled to the ground voltage; a first P-type metal-oxide-semiconductor (PMOS) (MP1) and a second PMOS (MP2), wherein source electrodes of the first PMOS (MP1) and the second PMOS (MP2) are coupled to the supply voltage; and differential output terminals (N1, N2) comprising a first output terminal (N1) and a second output terminal (N2), wherein the first output terminal (N1) is coupled to gate electrodes of the first NMOS (MN1) and the first PMOS (MP1), and the second output terminal (N2) is coupled to gate electrodes of the second NMOS (MN2) and the second PMOS (MP2); a first N-type metal-oxide-semiconductor (NMOS) (MN1) and a second NMOS (MN2), wherein source electrodes of the first NMOS (MN1) and the second NMOS (MN2) are coupled to the ground voltage; a first P-type metal-oxide-semiconductor (PMOS) (MP1) and a second PMOS (MP2), wherein source electrodes of the first PMOS (MP1) and the second PMOS (MP2) are coupled to the supply voltage; and differential output terminals (N1, N2) comprising a first output terminal (N1) and a second output terminal (N2), wherein the first output terminal (N1) is coupled to gate electrodes of the first NMOS (MN1) and the first PMOS (MP1), and the second output terminal (N2) is coupled to gate electrodes of the second NMOS (MN2) and the second PMOS (MP2); characterized in that the clock gating circuit is arranged to selectively couple the first output terminal (N1) to drain electrodes of the second NMOS (MN2) and the second PMOS (MP2), and to selectively couple the second output terminal (N2) to drain electrodes of the first NMOS (MN1) and the first PMOS (MP1). <EOS>