A CAM memory circuit comprising: a memory cell comprising a first non-volatile transistor comprising a first control gate connected to a first bit line, and a second non-volatile transistor comprising a second control gate connected to a second bit line, wherein a transistor state of each of the first non-volatile transistor and the second non-volatile transistor is configured to be programmed in a first transistor state or a second transistor state, and wherein the first non-volatile transistor is connected in series with the second non-volatile transistor; wherein the input state of the memory cell is defined by a first bit on the first bit line and a second bit on the second bit line and is configured to be a plurality of states comprising an input zero state, an input one state, and an input blocking state, wherein the stored state of the memory cell is defined by the transistor states of the first non-volatile transistor and the second non-volatile transistor and is configured to be a plurality of states comprising a stored zero state, a stored one state, and a stored no care state, and wherein when the input state of the memory cell is the input blocking state and compared to the stored state of the memory cell, the memory cell is configured to be in a blocking mode unless the stored state of the memory cell is a stored no care state, and wherein the blocking mode provides high impedance across the memory cell such that the memory cell is not conductive. a memory cell comprising a first non-volatile transistor comprising a first control gate connected to a first bit line, and a second non-volatile transistor comprising a second control gate connected to a second bit line, wherein a transistor state of each of the first non-volatile transistor and the second non-volatile transistor is configured to be programmed in a first transistor state or a second transistor state, and wherein the first non-volatile transistor is connected in series with the second non-volatile transistor; a first non-volatile transistor comprising a first control gate connected to a first bit line, and a second non-volatile transistor comprising a second control gate connected to a second bit line, wherein a transistor state of each of the first non-volatile transistor and the second non-volatile transistor is configured to be programmed in a first transistor state or a second transistor state, and wherein the first non-volatile transistor is connected in series with the second non-volatile transistor; wherein the input state of the memory cell is defined by a first bit on the first bit line and a second bit on the second bit line and is configured to be a plurality of states comprising an input zero state, an input one state, and an input blocking state, wherein the stored state of the memory cell is defined by the transistor states of the first non-volatile transistor and the second non-volatile transistor and is configured to be a plurality of states comprising a stored zero state, a stored one state, and a stored no care state, and wherein when the input state of the memory cell is the input blocking state and compared to the stored state of the memory cell, the memory cell is configured to be in a blocking mode unless the stored state of the memory cell is a stored no care state, and wherein the blocking mode provides high impedance across the memory cell such that the memory cell is not conductive. <EOS>