An imaging system comprising: a plurality of pixels configured to convert light into a charge; one or more amplifier transistors (SF_AMP) configured to convert a charge from a plurality of pixels; one or more selection transistors (SEL) configured to select a row or column of the plurality of pixels to be read out; one or more reset transistors (RST) configured to reset at least one of the plurality of pixels; a plurality of transfer gate transistors (TG1, TG2), wherein each of the plurality of transfer gate transistors (TG1, TG2) corresponds to one of the plurality of pixels; a pixel array including the plurality of pixels arranged in one or more shared pixel architectures , wherein each of the plurality of pixels comprises: a storage capacitor (CS1, CS2) connected to be charged by a photodiode (PD1, PD2), the storage capacitor (CS1, CS2) having a capacitance adapted to store an accumulated charge representing a plurality of charge dumps from the connected photodiode (PD1, PD2), each of the plurality of charge dumps comprising a charge representative of the light integrated in the connected photodiode (PD1, PD2), wherein the storage capacitor (CS1, CS2) is arranged to be in series with the photodiode (PD1, PD2) via a transfer gate transistor (TG1, TG2); and a transistor (TS1, TS2) in communication with the storage capacitor (CS1, CS2) and configured to control the flow of charge from the storage capacitor (CS1, CS2) to a floating diffusion node (FD); the array being arranged in a plurality of rows and columns; a first silicon structure in a first plane upon which the plurality of pixels are disposed; and a second silicon structure in a second plane upon which at least one of the one or more amplifier transistors (SF_AMP), selection transistors (SEL), and reset transistors (RST) are disposed, the second plane different from but parallel to and overlapping the first plane. a plurality of pixels configured to convert light into a charge; one or more amplifier transistors (SF_AMP) configured to convert a charge from a plurality of pixels; one or more selection transistors (SEL) configured to select a row or column of the plurality of pixels to be read out; one or more reset transistors (RST) configured to reset at least one of the plurality of pixels; a plurality of transfer gate transistors (TG1, TG2), wherein each of the plurality of transfer gate transistors (TG1, TG2) corresponds to one of the plurality of pixels; a pixel array including the plurality of pixels arranged in one or more shared pixel architectures , wherein each of the plurality of pixels comprises: a storage capacitor (CS1, CS2) connected to be charged by a photodiode (PD1, PD2), the storage capacitor (CS1, CS2) having a capacitance adapted to store an accumulated charge representing a plurality of charge dumps from the connected photodiode (PD1, PD2), each of the plurality of charge dumps comprising a charge representative of the light integrated in the connected photodiode (PD1, PD2), wherein the storage capacitor (CS1, CS2) is arranged to be in series with the photodiode (PD1, PD2) via a transfer gate transistor (TG1, TG2); and a transistor (TS1, TS2) in communication with the storage capacitor (CS1, CS2) and configured to control the flow of charge from the storage capacitor (CS1, CS2) to a floating diffusion node (FD); the array being arranged in a plurality of rows and columns; a first silicon structure in a first plane upon which the plurality of pixels are disposed; and a second silicon structure in a second plane upon which at least one of the one or more amplifier transistors (SF_AMP), selection transistors (SEL), and reset transistors (RST) are disposed, the second plane different from but parallel to and overlapping the first plane. <EOS>