A circuit for tripling frequency configured to receive an input voltage (V in ) having a sinusoidal shape and a base frequency, the circuit comprising a first and a second transistor pair (Q1-Q4) having a trans-characteristic f(V in ) approximating a polynomial nominal trans-characteristic : f V in = 3 A V in − 4 A 3 V in 3 g m wherein g m is a transconductance of transistors of the first and second transistor pairs and A is an amplitude of the input voltage (V in ), wherein: the first transistor pair comprises a first and a second transistor (Q1, Q2) having respective first and second conduction terminals and a respective control terminal, the second transistor pair comprises a third and a fourth transistor (Q3, Q4) having respective first and second conduction terminals and a respective control terminal; the circuit further comprises a first, a second, a third and a fourth input nodes and a first and a second output , wherein the first conduction terminals of the first, second, third and fourth transistors are coupled together, the second conduction terminals of the first (Q1) and fourth (Q4) transistors are coupled together and to the first output , the second conduction terminals of the second (Q2) and third (Q3) transistors are coupled together and to the second output , the control terminal of the first transistor (Q1) is coupled to the first input node and configured to receive a first fraction (1/2) of the input voltage (V in ) decreased by an offset value (V os ), the control terminal of the second transistor (Q2) is coupled to the second input node and configured to receive a counter-phase of the first fraction of the input voltage (Vi n ) decreased by the offset value (V os ), the control terminal of the third transistor (Q3) is coupled to the third input node and configured to receive a second fraction (α V in / 2 ) of the input voltage, and the control terminal of the fourth transistor (Q4) is coupled to the fourth input node and configured to receive a counter-phase of the second fraction of the input voltage, wherein the second fraction α and offset voltage V os satisfy the following condition: 2 V OS 1 − α = 3 2 A . the first transistor pair comprises a first and a second transistor (Q1, Q2) having respective first and second conduction terminals and a respective control terminal, the second transistor pair comprises a third and a fourth transistor (Q3, Q4) having respective first and second conduction terminals and a respective control terminal; the circuit further comprises a first, a second, a third and a fourth input nodes and a first and a second output , wherein the first conduction terminals of the first, second, third and fourth transistors are coupled together, the second conduction terminals of the first (Q1) and fourth (Q4) transistors are coupled together and to the first output , the second conduction terminals of the second (Q2) and third (Q3) transistors are coupled together and to the second output , the control terminal of the first transistor (Q1) is coupled to the first input node and configured to receive a first fraction (1/2) of the input voltage (V in ) decreased by an offset value (V os ), the control terminal of the second transistor (Q2) is coupled to the second input node and configured to receive a counter-phase of the first fraction of the input voltage (Vi n ) decreased by the offset value (V os ), the control terminal of the third transistor (Q3) is coupled to the third input node and configured to receive a second fraction (α V in / 2 ) of the input voltage, and the control terminal of the fourth transistor (Q4) is coupled to the fourth input node and configured to receive a counter-phase of the second fraction of the input voltage, wherein the second fraction α and offset voltage V os satisfy the following condition: 2 V OS 1 − α = 3 2 A . <EOS>