A magnetic random access memory, MRAM, structure formed on a substrate , comprising: (a) a first conductive metal layer formed on the substrate and comprising a first conductive line and a first conductive metal pad ; (b) a plurality of bottom electrodes aligned above said first conductive line and separated from the first conductive line by a first dielectric layer ; (c) a plurality of magnetic tunnel junction, MTJ, elements wherein each MTJ has a bottom layer contacting a bottom electrode, BE, and an uppermost top electrode with a top surface having a first width (n); (d) a plurality of metal contact bridges, MCBs, wherein each MCB has a bottom surface contacting a top surface of an underlying top electrode, and a top surface contacting a second conductive line , each of said MCBs has a second width (w) greater than said first width; (e) a second conductive metal layer comprising: a plurality of second conductive lines, bit lines, wherein each second conductive line has a bottom surface facing said substrate and contacting an upper surface of a MCB; a second conductive metal pad that is electrically connected to said first conductive metal pad; and a plurality of vias that connect said second conductive metal pad with said first conductive metal pad; and (f) a dielectric layer that contacts the top surface of each MCB, wherein a first bit line is formed above a first BE/MTJ/MCB stack in a first MRAM cell , a second bit line is formed above a second BE/MTJ/MCB stack in a second MRAM cell , and both of the first and second MRAM cells are aligned above the first conductive line, characterised in that the dielectric layer has a sidewall that is aligned with a sidewall of an underlying MCB. (a) a first conductive metal layer formed on the substrate and comprising a first conductive line and a first conductive metal pad ; (b) a plurality of bottom electrodes aligned above said first conductive line and separated from the first conductive line by a first dielectric layer ; (c) a plurality of magnetic tunnel junction, MTJ, elements wherein each MTJ has a bottom layer contacting a bottom electrode, BE, and an uppermost top electrode with a top surface having a first width (n); (d) a plurality of metal contact bridges, MCBs, wherein each MCB has a bottom surface contacting a top surface of an underlying top electrode, and a top surface contacting a second conductive line , each of said MCBs has a second width (w) greater than said first width; (e) a second conductive metal layer comprising: a plurality of second conductive lines, bit lines, wherein each second conductive line has a bottom surface facing said substrate and contacting an upper surface of a MCB; a second conductive metal pad that is electrically connected to said first conductive metal pad; and a plurality of vias that connect said second conductive metal pad with said first conductive metal pad; and a plurality of second conductive lines, bit lines, wherein each second conductive line has a bottom surface facing said substrate and contacting an upper surface of a MCB; a second conductive metal pad that is electrically connected to said first conductive metal pad; and a plurality of vias that connect said second conductive metal pad with said first conductive metal pad; and (f) a dielectric layer that contacts the top surface of each MCB, wherein a first bit line is formed above a first BE/MTJ/MCB stack in a first MRAM cell , a second bit line is formed above a second BE/MTJ/MCB stack in a second MRAM cell , and both of the first and second MRAM cells are aligned above the first conductive line, <EOS>