A memory device, comprising: a plurality of stacked layers of horizontal active lines , each layer comprising a semiconductor material and extending in a word line direction and in a bit line direction, whereby both directions are in the same horizontal plane and perpendicular to each other; a plurality of vertical slices penetrated by, and surrounding, the horizontal active lines , and comprising a conductive material; characterized in that the memory device further comprises a plurality of vertical buttress posts , each buttress post positioned over a buttress region of a horizontal active line that includes the buttress region , whereby each buttress region has four extensions of which two extend in opposite directions along the word line direction and the other two in opposite directions along the bit line direction; a plurality of holes (304-1, 304-2, 304-3, 304-4) that sever the extensions in the word line direction and in a direction normal to the layers of the semiconductor material; and a memory film between the horizontal active lines in the plurality of stacked layers and the vertical slices in the plurality of vertical slices , the memory film comprising a multilayer, dielectric charge trapping structure, wherein each horizontal active line in the bit line direction includes a channel region within a strip region of the memory device, whereby the strip region is in the word line direction, and wherein sides of the horizontal active lines are not straight in the channel region , are arcuate, and are more narrow in a cross-section (A-A') near a center of the strip region than in a cross-section (B-B') near edges of the strip region . a plurality of stacked layers of horizontal active lines , each layer comprising a semiconductor material and extending in a word line direction and in a bit line direction, whereby both directions are in the same horizontal plane and perpendicular to each other; a plurality of vertical slices penetrated by, and surrounding, the horizontal active lines , and comprising a conductive material; characterized in that the memory device further comprises a plurality of vertical buttress posts , each buttress post positioned over a buttress region of a horizontal active line that includes the buttress region , whereby each buttress region has four extensions of which two extend in opposite directions along the word line direction and the other two in opposite directions along the bit line direction; a plurality of holes (304-1, 304-2, 304-3, 304-4) that sever the extensions in the word line direction and in a direction normal to the layers of the semiconductor material; and a memory film between the horizontal active lines in the plurality of stacked layers and the vertical slices in the plurality of vertical slices , the memory film comprising a multilayer, dielectric charge trapping structure, wherein each horizontal active line in the bit line direction includes a channel region within a strip region of the memory device, whereby the strip region is in the word line direction, and wherein sides of the horizontal active lines are not straight in the channel region , are arcuate, and are more narrow in a cross-section (A-A') near a center of the strip region than in a cross-section (B-B') near edges of the strip region . <EOS>