A power management unit for an embedded flash memory system comprising a first voltage source providing a main power supply VDD , a second voltage source providing a core logic power supply VDDCORE , and a third voltage source providing an IO voltage supply VDDFLASH configured to perform a power-on sequence, wherein: during a first time period, the voltage output from the first voltage source ramps upward, the voltage output from the second voltage source remains at a constant level, and the voltage output from the third voltage source remains at a constant level; during a second time period immediately following the first time period, the voltage output from the first voltage source remains at a constant level, the voltage output from the second voltage source remains at a constant level, and the voltage output from the third voltage source remains at a constant level; during a third time period immediately following the second time period, the voltage output from the first voltage source remains at a constant level, the voltage output from the second voltage source ramps upward, and the voltage output from the third voltage source remains at a constant level; during a fourth time period immediately following the third time period, the voltage output from the first voltage source remains at a constant level, the voltage output from the second voltage source remains at a constant level, and the voltage output from the third voltage source remains at a constant level; and during a fifth time period immediately following the fourth time period, the voltage output from the first voltage source remains at a constant level, the voltage output from the second voltage source remains at a constant level, and the voltage output from the third voltage source ramps upward. during a first time period, the voltage output from the first voltage source ramps upward, the voltage output from the second voltage source remains at a constant level, and the voltage output from the third voltage source remains at a constant level; during a second time period immediately following the first time period, the voltage output from the first voltage source remains at a constant level, the voltage output from the second voltage source remains at a constant level, and the voltage output from the third voltage source remains at a constant level; during a third time period immediately following the second time period, the voltage output from the first voltage source remains at a constant level, the voltage output from the second voltage source ramps upward, and the voltage output from the third voltage source remains at a constant level; during a fourth time period immediately following the third time period, the voltage output from the first voltage source remains at a constant level, the voltage output from the second voltage source remains at a constant level, and the voltage output from the third voltage source remains at a constant level; and during a fifth time period immediately following the fourth time period, the voltage output from the first voltage source remains at a constant level, the voltage output from the second voltage source remains at a constant level, and the voltage output from the third voltage source ramps upward. <EOS>