An apparatus comprising: a matrix operations accelerator circuit comprising: a two-dimensional grid of processing elements, a plurality of registers that represents a two-dimensional matrix coupled to the two-dimensional grid of processing elements, and a coupling to a cache ; and a hardware processor core coupled to the matrix operations accelerator circuit and comprising: a vector register , a decoder circuit configured to decode a single instruction into a decoded instruction, the single instruction including a first field that identifies the two-dimensional matrix, a second field that identifies a location in the cache , and a third field that identifies the vector register , and an opcode that indicates an execution circuit of the hardware processor core is to load first elements into the plurality of registers that represents the two-dimensional matrix from the location in the cache by the coupling to the cache , and load second elements from the vector register into the plurality of registers that represents the two-dimensional matrix by a coupling of the hardware processor core to the matrix operations accelerator circuit that is separate from the coupling to the cache , and the execution circuit of the hardware processor core configured to execute the decoded instruction according to the opcode. a matrix operations accelerator circuit comprising: a two-dimensional grid of processing elements, a plurality of registers that represents a two-dimensional matrix coupled to the two-dimensional grid of processing elements, and a coupling to a cache ; and a two-dimensional grid of processing elements, a plurality of registers that represents a two-dimensional matrix coupled to the two-dimensional grid of processing elements, and a coupling to a cache ; and a hardware processor core coupled to the matrix operations accelerator circuit and comprising: a vector register , a decoder circuit configured to decode a single instruction into a decoded instruction, the single instruction including a first field that identifies the two-dimensional matrix, a second field that identifies a location in the cache , and a third field that identifies the vector register , and an opcode that indicates an execution circuit of the hardware processor core is to load first elements into the plurality of registers that represents the two-dimensional matrix from the location in the cache by the coupling to the cache , and load second elements from the vector register into the plurality of registers that represents the two-dimensional matrix by a coupling of the hardware processor core to the matrix operations accelerator circuit that is separate from the coupling to the cache , and the execution circuit of the hardware processor core configured to execute the decoded instruction according to the opcode. a vector register , a decoder circuit configured to decode a single instruction into a decoded instruction, the single instruction including a first field that identifies the two-dimensional matrix, a second field that identifies a location in the cache , and a third field that identifies the vector register , and an opcode that indicates an execution circuit of the hardware processor core is to load first elements into the plurality of registers that represents the two-dimensional matrix from the location in the cache by the coupling to the cache , and load second elements from the vector register into the plurality of registers that represents the two-dimensional matrix by a coupling of the hardware processor core to the matrix operations accelerator circuit that is separate from the coupling to the cache , and the execution circuit of the hardware processor core configured to execute the decoded instruction according to the opcode. <EOS>