A solid-state imaging apparatus comprising: an A/D converter ; and a plurality of time code transfer sections ; wherein the A/D converter includes a differential input circuit configured to operate on a first power supply voltage (VDD1) and to output a signal when a voltage of a pixel signal (SIG) is higher than a voltage of a reference signal (REF), a voltage conversion circuit configured to convert the output signal from the differential input circuit into a signal corresponding to a second power supply voltage (VDD2), a positive feedback circuit configured to operate on the second power supply voltage (VDD2) lower than the first power supply voltage (VDD1) and to accelerate a transition rate at which a comparison result signal is inverted, on a basis of the output signal from the differential input circuit , the comparison result signal being indicative of a result of a comparison in voltage between the pixel signal (SIG) and the reference signal (REF), and a data storage section configured to store a time code at the time the comparison result signal is inverted and to output the time code to the time code transfer section , and the plurality of time code transfer sections each include a shift register configured to successively transfer the time code to an output section . an A/D converter ; and a plurality of time code transfer sections ; wherein the A/D converter includes a differential input circuit configured to operate on a first power supply voltage (VDD1) and to output a signal when a voltage of a pixel signal (SIG) is higher than a voltage of a reference signal (REF), a voltage conversion circuit configured to convert the output signal from the differential input circuit into a signal corresponding to a second power supply voltage (VDD2), a positive feedback circuit configured to operate on the second power supply voltage (VDD2) lower than the first power supply voltage (VDD1) and to accelerate a transition rate at which a comparison result signal is inverted, on a basis of the output signal from the differential input circuit , the comparison result signal being indicative of a result of a comparison in voltage between the pixel signal (SIG) and the reference signal (REF), and a data storage section configured to store a time code at the time the comparison result signal is inverted and to output the time code to the time code transfer section , and a differential input circuit configured to operate on a first power supply voltage (VDD1) and to output a signal when a voltage of a pixel signal (SIG) is higher than a voltage of a reference signal (REF), a voltage conversion circuit configured to convert the output signal from the differential input circuit into a signal corresponding to a second power supply voltage (VDD2), a positive feedback circuit configured to operate on the second power supply voltage (VDD2) lower than the first power supply voltage (VDD1) and to accelerate a transition rate at which a comparison result signal is inverted, on a basis of the output signal from the differential input circuit , the comparison result signal being indicative of a result of a comparison in voltage between the pixel signal (SIG) and the reference signal (REF), and a data storage section configured to store a time code at the time the comparison result signal is inverted and to output the time code to the time code transfer section , and the plurality of time code transfer sections each include a shift register configured to successively transfer the time code to an output section . <EOS>