A TOF, time-of-flight, sensor , wherein the TOF sensor controls a light-emitting module to intermittently transmit a light pulse , and the light pulse is reflected by a target to generate a reflected light pulse , characterized in that the TOF sensor comprises: a clock signal generation circuit , configured to generate a first clock signal (clk1) and a second clock signal (clk2), wherein the first clock signal (clkl) and the second clock signal (clk2) have a same frequency, and there is a predetermined phase difference between the first clock signal (clkl) and the second clock signal (clk2); a transmission circuit , configured to generate a third clock signal (clk3) based on the first clock signal (clkl), wherein the third clock signal (clk3) is outputted to the light-emitting module , so that the light-emitting module intermittently transmit the light pulse ; a replicated transmission circuit , configured to simulate the transmission circuit , and generate a fourth clock signal (clk4) based on the second clock signal (clk2), so that the phase difference between the fourth clock signal (clk4) and the third clock signal (clk3) is kept the same as the predetermined phase difference; a delay locked loop , coupled to the replicated transmission circuit and one of a plurality of sixth clock signals (clk6) to generate a fifth clock signal (clk5) based on the fourth clock signal (clk4) and on one of the plurality of sixth clock signals (clk6), so that the phase difference between one of the plurality of sixth clock signals (clk6) and the fourth clock signal (clk4) is kept at zero; a clock tree , configured to generate the plurality of sixth clock signals (clk6) based on the fifth clock signal (clk5), wherein a plurality of phases of the plurality of sixth clock signals (clk6) are all the same; and a pixel array , having a plurality of pixel columns, wherein the plurality of pixel columns perform sampling on the reflected light pulse , respectively, based on the plurality of sixth clock signals (clk6) to generate a sampling result (pout). a clock signal generation circuit , configured to generate a first clock signal (clk1) and a second clock signal (clk2), wherein the first clock signal (clkl) and the second clock signal (clk2) have a same frequency, and there is a predetermined phase difference between the first clock signal (clkl) and the second clock signal (clk2); a transmission circuit , configured to generate a third clock signal (clk3) based on the first clock signal (clkl), wherein the third clock signal (clk3) is outputted to the light-emitting module , so that the light-emitting module intermittently transmit the light pulse ; a replicated transmission circuit , configured to simulate the transmission circuit , and generate a fourth clock signal (clk4) based on the second clock signal (clk2), so that the phase difference between the fourth clock signal (clk4) and the third clock signal (clk3) is kept the same as the predetermined phase difference; a delay locked loop , coupled to the replicated transmission circuit and one of a plurality of sixth clock signals (clk6) to generate a fifth clock signal (clk5) based on the fourth clock signal (clk4) and on one of the plurality of sixth clock signals (clk6), so that the phase difference between one of the plurality of sixth clock signals (clk6) and the fourth clock signal (clk4) is kept at zero; a clock tree , configured to generate the plurality of sixth clock signals (clk6) based on the fifth clock signal (clk5), wherein a plurality of phases of the plurality of sixth clock signals (clk6) are all the same; and a pixel array , having a plurality of pixel columns, wherein the plurality of pixel columns perform sampling on the reflected light pulse , respectively, based on the plurality of sixth clock signals (clk6) to generate a sampling result (pout). <EOS>