An apparatus comprising: a pad; a first transistor (MN2) coupled in series with a second transistor (MN1) and coupled to the pad, wherein the first and second transistors are n-type FinFETs, wherein a source terminal of the first transistor is coupled to a drain terminal of the second transistor, wherein a drain terminal of the first transistor is coupled to the pad, and wherein a source terminal of the second transistor is coupled to ground; a third transistor (MP2) coupled in series with a fourth transistor (MP1) and coupled to the pad, wherein the third and fourth transistors are p-type FinFETs, wherein a source terminal of the third transistor is coupled to a drain terminal of the fourth transistor, wherein a drain terminal of the third transistor is coupled to the pad, and wherein a source terminal of the fourth transistor is coupled to a first power supply node; and a self-biasing circuit to bias the first and third transistors such that the first and third transistors are to be weakly biased to provide local gate ballasting during an electrostatic discharge, ESD, event; wherein the self-biasing circuit comprises a diode-connected n-type transistor (MN3) having a source terminal arranged to bias the first transistor and a drain terminal coupled to a second power supply node, and a diode-connected p-type transistor (MP3) having a source terminal arranged to bias the third transistor and a drain terminal coupled to the second power supply node; and wherein the ESD event is an ESD event during which a power supply to the first power supply node is absent, a power supply to the second power supply node is absent, and a voltage or current occurs on the pad. a pad; a first transistor (MN2) coupled in series with a second transistor (MN1) and coupled to the pad, wherein the first and second transistors are n-type FinFETs, wherein a source terminal of the first transistor is coupled to a drain terminal of the second transistor, wherein a drain terminal of the first transistor is coupled to the pad, and wherein a source terminal of the second transistor is coupled to ground; a third transistor (MP2) coupled in series with a fourth transistor (MP1) and coupled to the pad, wherein the third and fourth transistors are p-type FinFETs, wherein a source terminal of the third transistor is coupled to a drain terminal of the fourth transistor, wherein a drain terminal of the third transistor is coupled to the pad, and wherein a source terminal of the fourth transistor is coupled to a first power supply node; and a self-biasing circuit to bias the first and third transistors such that the first and third transistors are to be weakly biased to provide local gate ballasting during an electrostatic discharge, ESD, event; wherein the self-biasing circuit comprises a diode-connected n-type transistor (MN3) having a source terminal arranged to bias the first transistor and a drain terminal coupled to a second power supply node, and a diode-connected p-type transistor (MP3) having a source terminal arranged to bias the third transistor and a drain terminal coupled to the second power supply node; and wherein the ESD event is an ESD event during which a power supply to the first power supply node is absent, a power supply to the second power supply node is absent, and a voltage or current occurs on the pad. <EOS>