An integrated circuit, IC, comprising: a core circuit coupled to a core supply voltage terminal that is configured to receive a core supply voltage (Vdd); input/output, I/O, buffers coupled to an output supply voltage terminal that is configured to receive an output supply voltage (Vddio), where each of the I/O buffers comprises: a bias voltage generator that is configured to generate a first bias voltage (Bxn) with a magnitude that depends on a control signal (En18), core supply voltage Vdd and output supply voltage (Vddio); a bandgap voltage generator configured to generate a first bandgap reference voltage (BGR1); an output stage that receives the first bias voltage (Bxn), wherein the output stage is configured to drive an I/O pad based upon a data signal received at the I/O buffer , and; an I/O buffer controller coupled to the I/O buffers and configured to: compare the output supply voltage (Vddio) to the first bandgap reference voltage (BGR1); generate the control signal (En18) based upon the comparison of the output supply voltage (Vddio) to the first bandgap reference voltage (BGR1); and generate first and second low voltage inhibiter, LVI, control signals (LVIp, LVIn) with respective logic low voltages to control the output stage when magnitudes of core supply voltage (Vdd) and output supply voltage (Vddio) are below respective threshold voltages (V1, V2). a core circuit coupled to a core supply voltage terminal that is configured to receive a core supply voltage (Vdd); input/output, I/O, buffers coupled to an output supply voltage terminal that is configured to receive an output supply voltage (Vddio), where each of the I/O buffers comprises: a bias voltage generator that is configured to generate a first bias voltage (Bxn) with a magnitude that depends on a control signal (En18), core supply voltage Vdd and output supply voltage (Vddio); a bandgap voltage generator configured to generate a first bandgap reference voltage (BGR1); an output stage that receives the first bias voltage (Bxn), wherein the output stage is configured to drive an I/O pad based upon a data signal received at the I/O buffer , and; a bias voltage generator that is configured to generate a first bias voltage (Bxn) with a magnitude that depends on a control signal (En18), core supply voltage Vdd and output supply voltage (Vddio); a bandgap voltage generator configured to generate a first bandgap reference voltage (BGR1); an output stage that receives the first bias voltage (Bxn), wherein the output stage is configured to drive an I/O pad based upon a data signal received at the I/O buffer , and; an I/O buffer controller coupled to the I/O buffers and configured to: compare the output supply voltage (Vddio) to the first bandgap reference voltage (BGR1); generate the control signal (En18) based upon the comparison of the output supply voltage (Vddio) to the first bandgap reference voltage (BGR1); and generate first and second low voltage inhibiter, LVI, control signals (LVIp, LVIn) with respective logic low voltages to control the output stage when magnitudes of core supply voltage (Vdd) and output supply voltage (Vddio) are below respective threshold voltages (V1, V2). compare the output supply voltage (Vddio) to the first bandgap reference voltage (BGR1); generate the control signal (En18) based upon the comparison of the output supply voltage (Vddio) to the first bandgap reference voltage (BGR1); and generate first and second low voltage inhibiter, LVI, control signals (LVIp, LVIn) with respective logic low voltages to control the output stage when magnitudes of core supply voltage (Vdd) and output supply voltage (Vddio) are below respective threshold voltages (V1, V2). <EOS>