A solar cell, comprising: a substrate ; an emitter , a first passivation film , an antireflection film and a first electrode that are sequentially disposed on an upper surface of the substrate ; a tunneling layer , a retardation layer , a field passivation layer , a second passivation film and a second electrode that are sequentially disposed on a lower surface of the substrate ; wherein the retardation layer is configured to retard a migration of a doped ion in the field passivation layer to the substrate , and the retardation layer includes: a first retardation sub-layer , wherein an orthographic projection of the first retardation sub-layer overlaps with an orthographic projection of the second electrode in a direction perpendicular to the surface of the substrate , and a second retardation sub-layer , wherein an orthographic projection of the second retardation sub-layer misaligns with the orthographic projection of the second electrode in the direction perpendicular to the surface of the substrate , and at least the second retardation sub-layer is configured as an intrinsic semiconductor layer; wherein a thickness of the first retardation sub-layer is smaller than a thickness of the second retardation sub-layer in the direction perpendicular to the lower surface of the substrate , and a material of the substrate is a semiconductor. a substrate ; an emitter , a first passivation film , an antireflection film and a first electrode that are sequentially disposed on an upper surface of the substrate ; a tunneling layer , a retardation layer , a field passivation layer , a second passivation film and a second electrode that are sequentially disposed on a lower surface of the substrate ; wherein the retardation layer is configured to retard a migration of a doped ion in the field passivation layer to the substrate , and the retardation layer includes: a first retardation sub-layer , wherein an orthographic projection of the first retardation sub-layer overlaps with an orthographic projection of the second electrode in a direction perpendicular to the surface of the substrate , and a second retardation sub-layer , wherein an orthographic projection of the second retardation sub-layer misaligns with the orthographic projection of the second electrode in the direction perpendicular to the surface of the substrate , and at least the second retardation sub-layer is configured as an intrinsic semiconductor layer; a first retardation sub-layer , wherein an orthographic projection of the first retardation sub-layer overlaps with an orthographic projection of the second electrode in a direction perpendicular to the surface of the substrate , and a second retardation sub-layer , wherein an orthographic projection of the second retardation sub-layer misaligns with the orthographic projection of the second electrode in the direction perpendicular to the surface of the substrate , and at least the second retardation sub-layer is configured as an intrinsic semiconductor layer; wherein a thickness of the first retardation sub-layer is smaller than a thickness of the second retardation sub-layer in the direction perpendicular to the lower surface of the substrate , and a material of the substrate is a semiconductor. <EOS>