A semiconductor device comprising: a summing amplifier ; a plurality of transistor mismatch circuits , wherein the transistor mismatch circuits are operable to output a value indicative of a mismatch between transistors in a respective one of the transistor mismatch circuits, and wherein the transistor mismatch circuits each comprise: a first inverter circuit including a first PMOS transistor and a first NMOS transistor , a drain electrode of the first PMOS transistor coupled to a drain electrode of the first NMOS transistor; a second inverter circuit including a second PMOS transistor and a second NMOS transistor , a drain electrode of the second PMOS transistor coupled to a drain electrode of the second NMOS transistor; a first output, for a first output voltage Vo1, wherein the first output is coupled to gate electrodes of the first and second PMOS and NMOS transistors, to the drain electrode of the first PMOS transistor and to the drain electrode of the first NMOS transistor to self-bias the first inverter circuit; and a second output, for a second output voltage Vo2, wherein the second output is coupled to the drain electrode of the second PMOS transistor and to the drain electrode of the second NMOS transistor; and a plurality of absolute value circuits coupled between the first and second outputs of respective transistor mismatch circuits and the summing amplifier , wherein the summing amplifier is operable to provide a value indicating a standard deviation of the mismatch between the transistors. a summing amplifier ; a plurality of transistor mismatch circuits , wherein the transistor mismatch circuits are operable to output a value indicative of a mismatch between transistors in a respective one of the transistor mismatch circuits, and wherein the transistor mismatch circuits each comprise: a first inverter circuit including a first PMOS transistor and a first NMOS transistor , a drain electrode of the first PMOS transistor coupled to a drain electrode of the first NMOS transistor; a second inverter circuit including a second PMOS transistor and a second NMOS transistor , a drain electrode of the second PMOS transistor coupled to a drain electrode of the second NMOS transistor; a first output, for a first output voltage Vo1, wherein the first output is coupled to gate electrodes of the first and second PMOS and NMOS transistors, to the drain electrode of the first PMOS transistor and to the drain electrode of the first NMOS transistor to self-bias the first inverter circuit; and a second output, for a second output voltage Vo2, wherein the second output is coupled to the drain electrode of the second PMOS transistor and to the drain electrode of the second NMOS transistor; and a first inverter circuit including a first PMOS transistor and a first NMOS transistor , a drain electrode of the first PMOS transistor coupled to a drain electrode of the first NMOS transistor; a second inverter circuit including a second PMOS transistor and a second NMOS transistor , a drain electrode of the second PMOS transistor coupled to a drain electrode of the second NMOS transistor; a first output, for a first output voltage Vo1, wherein the first output is coupled to gate electrodes of the first and second PMOS and NMOS transistors, to the drain electrode of the first PMOS transistor and to the drain electrode of the first NMOS transistor to self-bias the first inverter circuit; and a second output, for a second output voltage Vo2, wherein the second output is coupled to the drain electrode of the second PMOS transistor and to the drain electrode of the second NMOS transistor; and a plurality of absolute value circuits coupled between the first and second outputs of respective transistor mismatch circuits and the summing amplifier , wherein the summing amplifier is operable to provide a value indicating a standard deviation of the mismatch between the transistors. <EOS>