An apparatus for reducing replays in an out-of-order processor in the apparatus, the apparatus comprising: a first reservation station, configured to dispatch a first load micro instruction, and configured to detect and indicate on a hold bus if said first load micro instruction is one of a plurality of specified load instruction types directed to one of a plurality of non-core resources, wherein said non-core resources comprise resources disposed on the apparatus along with the out-of-order processor, but which are not disposed within the out-of-order processor; a second reservation station, coupled to said hold bus, configured to dispatch one or more younger micro instructions therein that depend on said first load micro instruction for execution after a first number of clock cycles following dispatch of said first load micro instruction, and if it is indicated on said hold bus that said first load micro instruction is said one of a plurality of specified load instruction types, said second reservation station is configured to stall dispatch of said one or more younger micro instructions until said first load micro instruction has resolved and has retrieved said operand, and is configured to preclude assertion of any indications that would otherwise result in a replay event; load execution logic, coupled to said first reservation station, configured to receive and execute said first load micro instruction; and said plurality of non-core resources, comprising: a random access memory, programmed via a Joint Test Action Group interface with said plurality of specified load instruction types corresponding to the out-of-order processor which, upon initialization, accesses said random access memory to determine said plurality of specified load instruction types. a first reservation station, configured to dispatch a first load micro instruction, and configured to detect and indicate on a hold bus if said first load micro instruction is one of a plurality of specified load instruction types directed to one of a plurality of non-core resources, wherein said non-core resources comprise resources disposed on the apparatus along with the out-of-order processor, but which are not disposed within the out-of-order processor; a second reservation station, coupled to said hold bus, configured to dispatch one or more younger micro instructions therein that depend on said first load micro instruction for execution after a first number of clock cycles following dispatch of said first load micro instruction, and if it is indicated on said hold bus that said first load micro instruction is said one of a plurality of specified load instruction types, said second reservation station is configured to stall dispatch of said one or more younger micro instructions until said first load micro instruction has resolved and has retrieved said operand, and is configured to preclude assertion of any indications that would otherwise result in a replay event; load execution logic, coupled to said first reservation station, configured to receive and execute said first load micro instruction; and said plurality of non-core resources, comprising: a random access memory, programmed via a Joint Test Action Group interface with said plurality of specified load instruction types corresponding to the out-of-order processor which, upon initialization, accesses said random access memory to determine said plurality of specified load instruction types. <EOS>