A liquid crystal display, comprising: a gate line (121, Gi) extending in a horizontal first direction (x); a first data line (171, Dj) extending in a vertical second direction (y) substantially orthogonal to the horizontal first direction (x); a second data line (171, Dj) extending in the vertical second direction (y); at least one thin film transistor (Qa, Qb, Qc) comprising a gate electrode connected to the gate line (121, Gi), a source electrode connected to the first data line (171, Dj), and a drain electrode ; a vertical storage electrode line extending substantially in parallel to and between the first data line (171, Dj) and the second data line (171, Dj); a passivation layer disposed on the thin film transistor (Qa, Qb, Qc) and the storage electrode line ; an insulating layer disposed on the passivation layer ; and a pixel electrode disposed on the insulating layer , the pixel electrode being connected to the drain electrode , wherein the vertical storage electrode line comprises a first expansion adjacent to the gate line (121, Gi), wherein the insulating layer comprises a first opening exposing a portion of the passivation layer , the portion of the passivation layer overlapping the first expansion , and wherein the pixel electrode comprises a first protrusion , overlapping the first expansion in the first opening , a storage capacitor (Cst2) being formed between the first protrusion and the first expansion characterized in that the vertical storage electrode line is bent at least once towards the horizontal first direction (x) near a horizontal edge of the pixel electrode adjacent to the gate line , and the storage capacitor (Cst2) is disposed adjacent to the at least one thin film transistor (Qa, Qb, Qc) in the horizontal first direction (x) or the vertical second direction (y). a gate line (121, Gi) extending in a horizontal first direction (x); a first data line (171, Dj) extending in a vertical second direction (y) substantially orthogonal to the horizontal first direction (x); a second data line (171, Dj) extending in the vertical second direction (y); at least one thin film transistor (Qa, Qb, Qc) comprising a gate electrode connected to the gate line (121, Gi), a source electrode connected to the first data line (171, Dj), and a drain electrode ; a vertical storage electrode line extending substantially in parallel to and between the first data line (171, Dj) and the second data line (171, Dj); a passivation layer disposed on the thin film transistor (Qa, Qb, Qc) and the storage electrode line ; an insulating layer disposed on the passivation layer ; and a pixel electrode disposed on the insulating layer , the pixel electrode being connected to the drain electrode , wherein the vertical storage electrode line comprises a first expansion adjacent to the gate line (121, Gi), wherein the insulating layer comprises a first opening exposing a portion of the passivation layer , the portion of the passivation layer overlapping the first expansion , and wherein the pixel electrode comprises a first protrusion , overlapping the first expansion in the first opening , a storage capacitor (Cst2) being formed between the first protrusion and the first expansion characterized in that the vertical storage electrode line is bent at least once towards the horizontal first direction (x) near a horizontal edge of the pixel electrode adjacent to the gate line , and the storage capacitor (Cst2) is disposed adjacent to the at least one thin film transistor (Qa, Qb, Qc) in the horizontal first direction (x) or the vertical second direction (y). <EOS>