A distributed timing system comprising: a source IC comprising: a time-to-digital converter, TDC, configured to detect the timing of a signal by generating a plurality of digital time stamps representing a plurality of time instances at which respective edge transitions of the signal occur, a first format conversion circuit configured to generate, based on the plurality of digital time stamps, a digital timing signal that digitally represents the timing of the signal, and a first synchronization circuit configured to synchronize the TDC and the first format conversion circuit based on a common reference signal, a digital interface electrically coupled to the source IC; and a destination IC configured to receive the digital timing signal from the digital interface, the destination IC comprising: a second format conversion circuit configured to process the digital timing signal to generate a plurality of digital time stamps representing the plurality of time instances at which respective edge transitions of the signal occur, a digital phase-locked loop, DPLL, configured to recover the signal based on the plurality of digital time stamps, and a second synchronization circuit configured to synchronize the second format conversion circuit and the DPLL based on the common reference signal, wherein the common reference signal indicates a zero against which the plurality of digital time stamps are represented. a source IC comprising: a time-to-digital converter, TDC, configured to detect the timing of a signal by generating a plurality of digital time stamps representing a plurality of time instances at which respective edge transitions of the signal occur, a first format conversion circuit configured to generate, based on the plurality of digital time stamps, a digital timing signal that digitally represents the timing of the signal, and a first synchronization circuit configured to synchronize the TDC and the first format conversion circuit based on a common reference signal, a time-to-digital converter, TDC, configured to detect the timing of a signal by generating a plurality of digital time stamps representing a plurality of time instances at which respective edge transitions of the signal occur, a first format conversion circuit configured to generate, based on the plurality of digital time stamps, a digital timing signal that digitally represents the timing of the signal, and a first synchronization circuit configured to synchronize the TDC and the first format conversion circuit based on a common reference signal, a digital interface electrically coupled to the source IC; and a destination IC configured to receive the digital timing signal from the digital interface, the destination IC comprising: a second format conversion circuit configured to process the digital timing signal to generate a plurality of digital time stamps representing the plurality of time instances at which respective edge transitions of the signal occur, a digital phase-locked loop, DPLL, configured to recover the signal based on the plurality of digital time stamps, and a second synchronization circuit configured to synchronize the second format conversion circuit and the DPLL based on the common reference signal, a second format conversion circuit configured to process the digital timing signal to generate a plurality of digital time stamps representing the plurality of time instances at which respective edge transitions of the signal occur, a digital phase-locked loop, DPLL, configured to recover the signal based on the plurality of digital time stamps, and a second synchronization circuit configured to synchronize the second format conversion circuit and the DPLL based on the common reference signal, wherein the common reference signal indicates a zero against which the plurality of digital time stamps are represented. <EOS>