A circuit , comprising: an input node (IN) configured to receive a data signal (Data_in) having a data rate, the data signal comprising rising and falling edges, a digital oscillator configured to produce a local clock signal (CLK) with a frequency higher than said data rate, wherein the rising and falling edges in the data signal (Data_in) are separated by plural periods of the local clock signal (CLK), sampling signal generator circuitry comprising a counter clocked by the local clock signal (CLK), the counter configured to have its count value sampled and then reset at the rising and falling edges of the data signal (Data_in), and a storage block coupled to the counter to receive the sampled count value of the counter , the storage block configured to store a count value of the counter , wherein the count value stored in the storage block is updated (SE) in response to the current sampled count value of the counter lying in an update range between a lower bound that is a function of half the value previously stored in the storage block and an upper bound that is function of the value previously stored in the storage block , wherein the sampling signal generator circuitry is configured to produce a threshold value set (Edge1, Edge2) as a function of the updated count value stored in the storage block , and sampling circuitry configured to receive the data signal (Data_in) at the input node (IN), the sampling circuitry coupled to the sampling signal generator circuitry and configured to be actuated by the sampling signal generator and sample (SI) the data signal (Data_in) at the input node and provide at an output node (OUT) a sampled version (Sampled Data_in) of the data signal (Data_in) at the input node (IN) in response to the count value of the counter reaching any of the threshold values in the threshold value set (Edge1, Edge2). an input node (IN) configured to receive a data signal (Data_in) having a data rate, the data signal comprising rising and falling edges, a digital oscillator configured to produce a local clock signal (CLK) with a frequency higher than said data rate, wherein the rising and falling edges in the data signal (Data_in) are separated by plural periods of the local clock signal (CLK), sampling signal generator circuitry comprising a counter clocked by the local clock signal (CLK), the counter configured to have its count value sampled and then reset at the rising and falling edges of the data signal (Data_in), and a storage block coupled to the counter to receive the sampled count value of the counter , the storage block configured to store a count value of the counter , wherein the count value stored in the storage block is updated (SE) in response to the current sampled count value of the counter lying in an update range between a lower bound that is a function of half the value previously stored in the storage block and an upper bound that is function of the value previously stored in the storage block , wherein the sampling signal generator circuitry is configured to produce a threshold value set (Edge1, Edge2) as a function of the updated count value stored in the storage block , and sampling circuitry configured to receive the data signal (Data_in) at the input node (IN), the sampling circuitry coupled to the sampling signal generator circuitry and configured to be actuated by the sampling signal generator and sample (SI) the data signal (Data_in) at the input node and provide at an output node (OUT) a sampled version (Sampled Data_in) of the data signal (Data_in) at the input node (IN) in response to the count value of the counter reaching any of the threshold values in the threshold value set (Edge1, Edge2). <EOS>