A method of operating a processor , comprising: performing successive read cycles from an instruction cache array and a response buffer array including providing a plurality of sequential addresses to the instruction cache array and the response buffer array during successive clock cycles, wherein the instruction cache stores cache lines retrieved from an external memory, and wherein the response buffer array buffers the cache lines for the instruction cache array ; during said performing successive read cycles, detecting a read hit in the response buffer array ; and in response to said detecting a read hit in the response buffer array during said performing successive read cycles, performing a zero clock retire to write a cache line from a response buffer to the instruction cache array , wherein the zero clock retire is performed during the next cycle after said detecting a read hit; wherein the zero clock retire comprises: switching the instruction cache array from a read cycle to a write cycle for one cycle; selecting a response buffer of the response buffer array and providing a cache line stored in the selected response buffer to be stored into the instruction cache array at an address stored in the selected response buffer ; wherein said address stored in the selected response buffer is provided to the instruction cache array ; and bypassing a sequential address being provided to the instruction cache array for the read cycle during the zero clock retire. performing successive read cycles from an instruction cache array and a response buffer array including providing a plurality of sequential addresses to the instruction cache array and the response buffer array during successive clock cycles, wherein the instruction cache stores cache lines retrieved from an external memory, and wherein the response buffer array buffers the cache lines for the instruction cache array ; during said performing successive read cycles, detecting a read hit in the response buffer array ; and in response to said detecting a read hit in the response buffer array during said performing successive read cycles, performing a zero clock retire to write a cache line from a response buffer to the instruction cache array , wherein the zero clock retire is performed during the next cycle after said detecting a read hit; wherein the zero clock retire comprises: switching the instruction cache array from a read cycle to a write cycle for one cycle; selecting a response buffer of the response buffer array and providing a cache line stored in the selected response buffer to be stored into the instruction cache array at an address stored in the selected response buffer ; wherein said address stored in the selected response buffer is provided to the instruction cache array ; and bypassing a sequential address being provided to the instruction cache array for the read cycle during the zero clock retire. switching the instruction cache array from a read cycle to a write cycle for one cycle; selecting a response buffer of the response buffer array and providing a cache line stored in the selected response buffer to be stored into the instruction cache array at an address stored in the selected response buffer ; wherein said address stored in the selected response buffer is provided to the instruction cache array ; and bypassing a sequential address being provided to the instruction cache array for the read cycle during the zero clock retire. <EOS>