A memory interface for raising the speed of transmitting data, comprising: a multiphase clock generator , which is configured to receive a reference clock signal and generate a plurality of divided clock signals (CLK 0, CLK 90, CLK 180, CLK 270) having a phase-difference from one another by dividing the reference clock signal; a first error correction block , which is configured to receive a first divided clock signal (CLK 0) among the plurality of divided clock signals (CLK 0, CLK 90, CLK 180, CLK 270); a first data multiplexer , which is configured to receive the first divided clock signal (CLK 0) from the first error correction block and transmit first least significant bit data (LSB Data 1) in response to a rising or falling edge of the first divided clock signal (CLK 0); and a second error correction block , which is configured to receive the first divided clock signal (CLK 0); and a second data multiplexer , which is configured to receive the first divided clock signal (CLK 0) from the second error correction block and transmit first most significant bit data (MSB Data 1) in response to the rising or falling edge of the first divided clock signal (CLK 0), wherein the first error correction block includes one of a duty cycle correction circuit and a quadrature error correction circuit, and is configured to receive the first least significant bit data (LSB Data 1) and correct the timing of transmitting the first least significant bit data (LSB Data 1) using the one of the duty cycle correction circuit and the quadrature error correction circuit, and wherein the second error correction block includes one of a duty cycle correction circuit and a quadrature error correction circuit, and is configured to receive the first most significant bit data (MSB Data 1) and correct the timing of transmitting the first most significant bit data (MSB Data 1) using the one of the duty cycle correction circuit and the quadrature error correction circuit. a multiphase clock generator , which is configured to receive a reference clock signal and generate a plurality of divided clock signals (CLK 0, CLK 90, CLK 180, CLK 270) having a phase-difference from one another by dividing the reference clock signal; a first error correction block , which is configured to receive a first divided clock signal (CLK 0) among the plurality of divided clock signals (CLK 0, CLK 90, CLK 180, CLK 270); a first data multiplexer , which is configured to receive the first divided clock signal (CLK 0) from the first error correction block and transmit first least significant bit data (LSB Data 1) in response to a rising or falling edge of the first divided clock signal (CLK 0); and a second error correction block , which is configured to receive the first divided clock signal (CLK 0); and a second data multiplexer , which is configured to receive the first divided clock signal (CLK 0) from the second error correction block and transmit first most significant bit data (MSB Data 1) in response to the rising or falling edge of the first divided clock signal (CLK 0), wherein the first error correction block includes one of a duty cycle correction circuit and a quadrature error correction circuit, and is configured to receive the first least significant bit data (LSB Data 1) and correct the timing of transmitting the first least significant bit data (LSB Data 1) using the one of the duty cycle correction circuit and the quadrature error correction circuit, and wherein the second error correction block includes one of a duty cycle correction circuit and a quadrature error correction circuit, and is configured to receive the first most significant bit data (MSB Data 1) and correct the timing of transmitting the first most significant bit data (MSB Data 1) using the one of the duty cycle correction circuit and the quadrature error correction circuit. <EOS>