A class AB amplifier , comprising: an input stage configured to receive an input signal and to generate an amplified input signal (Von); a cascode stage (120_1, 120_2) coupled to the input stage and configured to receive the amplified input signal (Von), wherein the cascode stage (120_1, 120_2) has a high-pass filter configured to filter the amplified input signal (Von) to generate a filtered input signal, and wherein the cascode stage (120_1, 120_2) is configured to generate a first driving signal (Von_p) and a second driving signal (Von_n) according to the filtered input signal; and an output stage (130_1, 130_2) coupled to the cascode stage (120_1, 120_2) and configured to generate an output signal (Vout_N) according to the first driving signal (Von_p) and the second driving signal (Von_n); wherein the cascode stage (120_1, 120_2) comprises a P-type transistor (MFP3) and an N-type transistor (MFN3); wherein the cascode stage (120_1, 120_2) is configured to input the filtered input signal into a gate electrode of the P-type transistor (MFP3) to generate the first driving signal (Von_p) at a source electrode of the P-type transistor (MFP3); the cascode stage (120_1, 120_2) is further configured to input the filtered input signal into a gate electrode of the N-type transistor (MFN3) to generate the second driving signal (Von_n) at a source electrode of the N-type transistor (MFB3); and the source electrode of the P-type transistor (MFP3) is coupled to a drain electrode of the N-type transistor (MFN3), and the source electrode of the N-type transistor (MFN3) is coupled to a drain electrode of the P-type transistor (MFP3). an input stage configured to receive an input signal and to generate an amplified input signal (Von); a cascode stage (120_1, 120_2) coupled to the input stage and configured to receive the amplified input signal (Von), wherein the cascode stage (120_1, 120_2) has a high-pass filter configured to filter the amplified input signal (Von) to generate a filtered input signal, and wherein the cascode stage (120_1, 120_2) is configured to generate a first driving signal (Von_p) and a second driving signal (Von_n) according to the filtered input signal; and an output stage (130_1, 130_2) coupled to the cascode stage (120_1, 120_2) and configured to generate an output signal (Vout_N) according to the first driving signal (Von_p) and the second driving signal (Von_n); wherein the cascode stage (120_1, 120_2) comprises a P-type transistor (MFP3) and an N-type transistor (MFN3); wherein the cascode stage (120_1, 120_2) is configured to input the filtered input signal into a gate electrode of the P-type transistor (MFP3) to generate the first driving signal (Von_p) at a source electrode of the P-type transistor (MFP3); the cascode stage (120_1, 120_2) is further configured to input the filtered input signal into a gate electrode of the N-type transistor (MFN3) to generate the second driving signal (Von_n) at a source electrode of the N-type transistor (MFB3); and the source electrode of the P-type transistor (MFP3) is coupled to a drain electrode of the N-type transistor (MFN3), and the source electrode of the N-type transistor (MFN3) is coupled to a drain electrode of the P-type transistor (MFP3). <EOS>