A memory controller comprising: a command logic configured to generate a first command to trigger a memory device to enter one of a first command bus training mode or a second command bus training mode configured to train a command and address, CA, interface of the memory device; and input/output, I/O, training circuitry configured to cause a CA pattern to be output via a command bus coupled with the CA interface of the memory device, the I/O training circuitry further configured to: if a sampled CA pattern is received from the memory device via a data bus coupled with a DQ interface of the memory device, compress the sampled CA pattern to generate a first compressed value based on the memory device being in the first command bus training mode and forward the first compressed value to the command logic; and if a second compressed value is received from the memory device via the data bus, forward the second compressed value to the command logic, the second compressed value representing the sampled CA pattern compressed at the memory device based on the memory device being in the second command bus training mode, wherein the CA pattern to be output via the command bus comprises the CA pattern generated based on a same CA training algorithm that is capable of being implemented for the first command bus training mode and the second command bus training mode. a command logic configured to generate a first command to trigger a memory device to enter one of a first command bus training mode or a second command bus training mode configured to train a command and address, CA, interface of the memory device; and input/output, I/O, training circuitry configured to cause a CA pattern to be output via a command bus coupled with the CA interface of the memory device, the I/O training circuitry further configured to: if a sampled CA pattern is received from the memory device via a data bus coupled with a DQ interface of the memory device, compress the sampled CA pattern to generate a first compressed value based on the memory device being in the first command bus training mode and forward the first compressed value to the command logic; and if a second compressed value is received from the memory device via the data bus, forward the second compressed value to the command logic, the second compressed value representing the sampled CA pattern compressed at the memory device based on the memory device being in the second command bus training mode, if a sampled CA pattern is received from the memory device via a data bus coupled with a DQ interface of the memory device, compress the sampled CA pattern to generate a first compressed value based on the memory device being in the first command bus training mode and forward the first compressed value to the command logic; and if a second compressed value is received from the memory device via the data bus, forward the second compressed value to the command logic, the second compressed value representing the sampled CA pattern compressed at the memory device based on the memory device being in the second command bus training mode, wherein the CA pattern to be output via the command bus comprises the CA pattern generated based on a same CA training algorithm that is capable of being implemented for the first command bus training mode and the second command bus training mode. <EOS>