A 3D NAND memory device comprising: a cell region in which memory blocks (BLK) are disposed, each of the memory blocks including gate electrode layers and insulating layers , alternately stacked on a substrate , and channel structures (CH) extending in a first direction perpendicular to an upper surface of the substrate and passing through the gate electrode layers and the insulating layers to be connected to the substrate ; and a peripheral circuit region including a row decoder connected to the gate electrode layers and a page buffer connected to the channel structures (CH), wherein the memory blocks (BLK) include main blocks (MBK) and at least a first spare block (SBK), wherein a length of the first spare block (SBK) is shorter than a length of each of the main blocks (MBK) in a second direction parallel to the upper surface of the substrate wherein the memory blocks (BLK) are divided by first separation layers (MS1) extending in a third direction parallel to the upper surface of the substrate , wherein each of the memory blocks (BLK) includes string selection lines (SSL) provided by upper gate electrode layers with respect to the first direction and divided by second separation layers (MS2) disposed between the first separation layers (MS1) and upper separation layers (SS), both of the second separation layers (MS2) and the upper separation layers (SS) being extended in the third direction and shorter than the first separation layers (MS1), and wherein the number of the string selection lines (SSL) included in each of the main blocks (MBK) is greater than the number of the string selection lines (SSL) included in the first spare block (SBK). a cell region in which memory blocks (BLK) are disposed, each of the memory blocks including gate electrode layers and insulating layers , alternately stacked on a substrate , and channel structures (CH) extending in a first direction perpendicular to an upper surface of the substrate and passing through the gate electrode layers and the insulating layers to be connected to the substrate ; and a peripheral circuit region including a row decoder connected to the gate electrode layers and a page buffer connected to the channel structures (CH), wherein the memory blocks (BLK) include main blocks (MBK) and at least a first spare block (SBK), wherein a length of the first spare block (SBK) is shorter than a length of each of the main blocks (MBK) in a second direction parallel to the upper surface of the substrate wherein the memory blocks (BLK) are divided by first separation layers (MS1) extending in a third direction parallel to the upper surface of the substrate , wherein each of the memory blocks (BLK) includes string selection lines (SSL) provided by upper gate electrode layers with respect to the first direction and divided by second separation layers (MS2) disposed between the first separation layers (MS1) and upper separation layers (SS), both of the second separation layers (MS2) and the upper separation layers (SS) being extended in the third direction and shorter than the first separation layers (MS1), and wherein the number of the string selection lines (SSL) included in each of the main blocks (MBK) is greater than the number of the string selection lines (SSL) included in the first spare block (SBK). <EOS>