A circuit , comprising: - a first (M1) and a second (M2) transistor having their control electrodes coupled at a first common node (A) and the current paths therethrough coupled at a second common node (B) in an anti-series arrangement, with the current paths providing a current line between a first (Va) and a second (Vb) electrical line nodes, wherein said first and second electrical line nodes are connected to the terminals of said first and second transistors respectively, which are not coupled an the second common node (B); - a first electrical path between the first common node (A) and the first electrical line node (Va), the first electrical path comprising a first switch (C1) switchable (S2) between a conductive state and a non-conductive state, - a second electrical path between the first common node (A) and a second electrical line node (Vb), the second electrical path comprising a second switch (C2) switchable (S1) between a conductive state and a non-conductive state, - a third electrical path between the first common node (A) and the second common node (B), the third electrical path comprising a third switch (C3) switchable between a conductive state and a non-conductive state, - a logical network coupling the third switch (C3) with the first (C1) and second (C2) switches, the logical network configured to switch the third switch (C3) : a) to the conductive state with both the first switch (C1) and the second switch (C2) switched to the non-conductive state, b) to the non-conductive state with either one of the first switch (C1) and the second switch (C2) switched to the conductive state. - a first (M1) and a second (M2) transistor having their control electrodes coupled at a first common node (A) and the current paths therethrough coupled at a second common node (B) in an anti-series arrangement, with the current paths providing a current line between a first (Va) and a second (Vb) electrical line nodes, wherein said first and second electrical line nodes are connected to the terminals of said first and second transistors respectively, which are not coupled an the second common node (B); - a first electrical path between the first common node (A) and the first electrical line node (Va), the first electrical path comprising a first switch (C1) switchable (S2) between a conductive state and a non-conductive state, - a second electrical path between the first common node (A) and a second electrical line node (Vb), the second electrical path comprising a second switch (C2) switchable (S1) between a conductive state and a non-conductive state, - a third electrical path between the first common node (A) and the second common node (B), the third electrical path comprising a third switch (C3) switchable between a conductive state and a non-conductive state, - a logical network coupling the third switch (C3) with the first (C1) and second (C2) switches, the logical network configured to switch the third switch (C3) : a) to the conductive state with both the first switch (C1) and the second switch (C2) switched to the non-conductive state, b) to the non-conductive state with either one of the first switch (C1) and the second switch (C2) switched to the conductive state. a) to the conductive state with both the first switch (C1) and the second switch (C2) switched to the non-conductive state, b) to the non-conductive state with either one of the first switch (C1) and the second switch (C2) switched to the conductive state. <EOS>