A thin-film transistor (100, 200, 300, 400, TR1, TR2, TR3, TR4), comprising: a semiconductor layer (130, A1, A2) comprising: a first oxide semiconductor layer comprising gallium, wherein the first oxide semiconductor layer is configured to serve as a supporting layer for supporting a second oxide semiconductor layer ; the second oxide semiconductor layer , wherein the second oxide semiconductor layer is configured to serve as a channel layer; and a silicon semiconductor layer between the first oxide semiconductor layer and the second oxide semiconductor layer such that the first oxide semiconductor layer contacts a first surface of the silicon semiconductor layer and the second oxide semiconductor layer contacts a second surface of the silicon semiconductor layer opposite to the first surface, wherein the silicon semiconductor layer is configured to function as a light-shielding layer and/or an electron-interrupting layer; and a gate electrode (140, G1, G2) spaced apart from the semiconductor layer and partially overlapping at least a part of the semiconductor layer, wherein a concentration of gallium in the first oxide semiconductor layer is higher than a concentration of gallium in the second oxide semiconductor layer . a semiconductor layer (130, A1, A2) comprising: a first oxide semiconductor layer comprising gallium, wherein the first oxide semiconductor layer is configured to serve as a supporting layer for supporting a second oxide semiconductor layer ; the second oxide semiconductor layer , wherein the second oxide semiconductor layer is configured to serve as a channel layer; and a silicon semiconductor layer between the first oxide semiconductor layer and the second oxide semiconductor layer such that the first oxide semiconductor layer contacts a first surface of the silicon semiconductor layer and the second oxide semiconductor layer contacts a second surface of the silicon semiconductor layer opposite to the first surface, wherein the silicon semiconductor layer is configured to function as a light-shielding layer and/or an electron-interrupting layer; and a first oxide semiconductor layer comprising gallium, wherein the first oxide semiconductor layer is configured to serve as a supporting layer for supporting a second oxide semiconductor layer ; the second oxide semiconductor layer , wherein the second oxide semiconductor layer is configured to serve as a channel layer; and a silicon semiconductor layer between the first oxide semiconductor layer and the second oxide semiconductor layer such that the first oxide semiconductor layer contacts a first surface of the silicon semiconductor layer and the second oxide semiconductor layer contacts a second surface of the silicon semiconductor layer opposite to the first surface, wherein the silicon semiconductor layer is configured to function as a light-shielding layer and/or an electron-interrupting layer; and a gate electrode (140, G1, G2) spaced apart from the semiconductor layer and partially overlapping at least a part of the semiconductor layer, wherein a concentration of gallium in the first oxide semiconductor layer is higher than a concentration of gallium in the second oxide semiconductor layer . <EOS>