A hardware processor comprising: a register comprising a field, that when set, is to enable an architecturally protected execution environment for code in an architecturally protected enclave in memory ; a thread control structure in the architecturally protected enclave ; a decoder circuit to decode a single instruction comprising an opcode into a decoded instruction, the opcode to indicate an execution circuit is to invoke a handler on the architecturally protected enclave to handle an asynchronous exit, AEX, from execution of the code in the architecturally protected enclave and then resume execution of the code in the architecturally protected enclave from where the asynchronous exit occurred; and the execution circuit to respond to the decoded instruction as specified by the opcode; characterized in that the single instruction is configured to perform: checking whether a pre-defined bit in the thread control structure is enabled for a current thread executing in the architecturally protected enclave , said pre-defined bit enabling the Return-To-Handler, RTH, feature for the architecturally protected enclave , and checking whether a pre-defined bit in the thread control structure is enabled for a current state save area of the architecturally protected enclave , said pre-defined bit enabling the RTH feature for the current state save area; if both pre-defined bits are enabled, pushing a return instruction pointer, RIP, to a stack of the architecturally protected enclave ; and setting the RIP to point to the handler to handle the AEX. a register comprising a field, that when set, is to enable an architecturally protected execution environment for code in an architecturally protected enclave in memory ; a thread control structure in the architecturally protected enclave ; a decoder circuit to decode a single instruction comprising an opcode into a decoded instruction, the opcode to indicate an execution circuit is to invoke a handler on the architecturally protected enclave to handle an asynchronous exit, AEX, from execution of the code in the architecturally protected enclave and then resume execution of the code in the architecturally protected enclave from where the asynchronous exit occurred; and the execution circuit to respond to the decoded instruction as specified by the opcode; characterized in that the single instruction is configured to perform: checking whether a pre-defined bit in the thread control structure is enabled for a current thread executing in the architecturally protected enclave , said pre-defined bit enabling the Return-To-Handler, RTH, feature for the architecturally protected enclave , and checking whether a pre-defined bit in the thread control structure is enabled for a current state save area of the architecturally protected enclave , said pre-defined bit enabling the RTH feature for the current state save area; if both pre-defined bits are enabled, pushing a return instruction pointer, RIP, to a stack of the architecturally protected enclave ; and setting the RIP to point to the handler to handle the AEX. checking whether a pre-defined bit in the thread control structure is enabled for a current thread executing in the architecturally protected enclave , said pre-defined bit enabling the Return-To-Handler, RTH, feature for the architecturally protected enclave , and checking whether a pre-defined bit in the thread control structure is enabled for a current state save area of the architecturally protected enclave , said pre-defined bit enabling the RTH feature for the current state save area; if both pre-defined bits are enabled, pushing a return instruction pointer, RIP, to a stack of the architecturally protected enclave ; and setting the RIP to point to the handler to handle the AEX. <EOS>