Method for calibrating a Successive Approximation Register analog-to-digital converter, ADC, converting in (N+1) comparator cycles an input voltage signal into a (N+1) bit code to represent a N bit output signal corresponding to said input voltage signal, the method comprising : - sampling said input voltage signal applied to said analog-to-digital converter, - successively comparing said sampled input voltage signal with successive output signals of a feedback digital-to-analogue converter, DAC, , comprising a set of binary scaled capacitors, to yield (N+1) comparison results, - determining, in a search logic block of said ADC, a (N+1) bit code representation for the (N+1) comparison result s , said (N+1) bit code yielding said N bit output signal, characterised by - on detection of said (N+1) bit code being equal to a predefined calibration trigger code, performing a calibration for one of the most significant bits of said (N+1) bit code by : replacing said (N+1) bit code by an alternative (N+1) bit code which yields the same N bit output signal, performing one additional (N+2) th comparator cycle using said alternative (N+1) bit code, to yield an additional comparison result, determining, using the comparison results of said additional (N+2) th comparator cycle and of the preceding (N+1) th cycle, a sign of a DAC capacitor mismatch error, tuning, in accordance with said sign of said DAC capacitor mismatch error, a set of switchable binary scaled calibration capacitors connected in parallel to a capacitor of said set of binary scaled capacitors of said DAC, said capacitor corresponding to said one of the most significant bits of said (N+1) bit code for which the calibration is performed. - sampling said input voltage signal applied to said analog-to-digital converter, - successively comparing said sampled input voltage signal with successive output signals of a feedback digital-to-analogue converter, DAC, , comprising a set of binary scaled capacitors, to yield (N+1) comparison results, - determining, in a search logic block of said ADC, a (N+1) bit code representation for the (N+1) comparison result s , said (N+1) bit code yielding said N bit output signal, characterised by - on detection of said (N+1) bit code being equal to a predefined calibration trigger code, performing a calibration for one of the most significant bits of said (N+1) bit code by : replacing said (N+1) bit code by an alternative (N+1) bit code which yields the same N bit output signal, performing one additional (N+2) th comparator cycle using said alternative (N+1) bit code, to yield an additional comparison result, determining, using the comparison results of said additional (N+2) th comparator cycle and of the preceding (N+1) th cycle, a sign of a DAC capacitor mismatch error, tuning, in accordance with said sign of said DAC capacitor mismatch error, a set of switchable binary scaled calibration capacitors connected in parallel to a capacitor of said set of binary scaled capacitors of said DAC, said capacitor corresponding to said one of the most significant bits of said (N+1) bit code for which the calibration is performed. replacing said (N+1) bit code by an alternative (N+1) bit code which yields the same N bit output signal, performing one additional (N+2) th comparator cycle using said alternative (N+1) bit code, to yield an additional comparison result, determining, using the comparison results of said additional (N+2) th comparator cycle and of the preceding (N+1) th cycle, a sign of a DAC capacitor mismatch error, tuning, in accordance with said sign of said DAC capacitor mismatch error, a set of switchable binary scaled calibration capacitors connected in parallel to a capacitor of said set of binary scaled capacitors of said DAC, said capacitor corresponding to said one of the most significant bits of said (N+1) bit code for which the calibration is performed. <EOS>