An equalization circuit comprising: • a receiver impedance network (Z t ) disposed inside a receiver chip (RX), • a passive equalizer disposed outside the receiver chip (RX), the passive equalizer containing a first inductor and a second inductor , • a first connector , a second connector , a third connector , and a fourth connector , wherein the structures of the first connector , the second connector , the third connector , and the fourth connector are the same, • wherein: ∘ the receiver chip (RX) is connected to the passive equalizer by the first connector and the second connector , and is connected to a first trace and a second trace of a differential trace by the first connector and the second connector respectively, wherein the differential trace is configured to connect the receiver chip (RX) and a transmitter chip (TX), and characterized in that ∘ a first end of the first inductor is connected to the first connector , a second end of the first inductor is connected to a first end of the receiver impedance network (Z t ) by the third connector , a second end of the receiver impedance network (Z t ) is connected to a first end of the second inductor by the fourth connector , and a second end of the second inductor is connected to the second connector ; and ∘ the first end of the first inductor is further connected to the first trace , and the second end of the second inductor is further connected to the second trace . • a receiver impedance network (Z t ) disposed inside a receiver chip (RX), • a passive equalizer disposed outside the receiver chip (RX), the passive equalizer containing a first inductor and a second inductor , • a first connector , a second connector , a third connector , and a fourth connector , wherein the structures of the first connector , the second connector , the third connector , and the fourth connector are the same, • wherein: ∘ the receiver chip (RX) is connected to the passive equalizer by the first connector and the second connector , and is connected to a first trace and a second trace of a differential trace by the first connector and the second connector respectively, wherein the differential trace is configured to connect the receiver chip (RX) and a transmitter chip (TX), and characterized in that ∘ a first end of the first inductor is connected to the first connector , a second end of the first inductor is connected to a first end of the receiver impedance network (Z t ) by the third connector , a second end of the receiver impedance network (Z t ) is connected to a first end of the second inductor by the fourth connector , and a second end of the second inductor is connected to the second connector ; and ∘ the first end of the first inductor is further connected to the first trace , and the second end of the second inductor is further connected to the second trace . ∘ the receiver chip (RX) is connected to the passive equalizer by the first connector and the second connector , and is connected to a first trace and a second trace of a differential trace by the first connector and the second connector respectively, wherein the differential trace is configured to connect the receiver chip (RX) and a transmitter chip (TX), and characterized in that ∘ a first end of the first inductor is connected to the first connector , a second end of the first inductor is connected to a first end of the receiver impedance network (Z t ) by the third connector , a second end of the receiver impedance network (Z t ) is connected to a first end of the second inductor by the fourth connector , and a second end of the second inductor is connected to the second connector ; and ∘ the first end of the first inductor is further connected to the first trace , and the second end of the second inductor is further connected to the second trace . <EOS>