A reference voltage circuit with low temperature drift, comprising a first voltage unit, a second voltage unit and a K times' amplification unit; wherein, the first voltage unit is configured to generate a first voltage, a first end of the first voltage unit is grounded; the K times' amplification unit is configured to amplify the first voltage by K times, wherein K is a constant greater than zero; a first end of the K times' amplification unit is connected to a second end of the first voltage unit; a second end of the K times' amplification unit is connected to a first end of the second voltage unit,; the second voltage unit is configured to generate a second voltage; the first end of the second voltage unit is connected to a third end of the first voltage unit and to a current source circuit (I); a second end of the second voltage unit serves as an output end of a reference voltage; the first voltage unit comprises a first P-channel Metal-Oxide Semiconductor Field-Effect Transistor, PMOSFET, (MP) and a first N-channel Metal-Oxide Semiconductor Field-Effect Transistor, NMOSFET (M1); the second voltage unit comprises a second NMOSFET (MN) and a third NMOSFET (M2); the K times' amplification unit comprises a first resistor (R1) and a second resistor (R2); wherein, a source of the second NMOSFET (MN) is connected to a drain of the third NMOSFET (M2) and serves as the output end of the reference voltage; a gate and a drain of the second NMOSFET (MN) are connected to the current source circuit (I); a gate of the third NMOSFET (M2) is connected to a gate and a drain of the first NMOSFET (M1) and to a drain of the first PMOSFET (MP); a source of the third NMOSFET (M2) is grounded; a gate of the first PMOSFET (MP) is connected to a first end of the first resistor (R1) and a first end of the second resistor (R2); a source of the first PMOSFET (MP) is connected to a second end of the first resistor (R1) and to the current source circuit (I); a source of the first NMOSFET (M1) is grounded; a second end of the second resistor (R2) is grounded. the first voltage unit is configured to generate a first voltage, a first end of the first voltage unit is grounded; the K times' amplification unit is configured to amplify the first voltage by K times, wherein K is a constant greater than zero; a first end of the K times' amplification unit is connected to a second end of the first voltage unit; a second end of the K times' amplification unit is connected to a first end of the second voltage unit,; the second voltage unit is configured to generate a second voltage; the first end of the second voltage unit is connected to a third end of the first voltage unit and to a current source circuit (I); a second end of the second voltage unit serves as an output end of a reference voltage; the first voltage unit comprises a first P-channel Metal-Oxide Semiconductor Field-Effect Transistor, PMOSFET, (MP) and a first N-channel Metal-Oxide Semiconductor Field-Effect Transistor, NMOSFET (M1); the second voltage unit comprises a second NMOSFET (MN) and a third NMOSFET (M2); the K times' amplification unit comprises a first resistor (R1) and a second resistor (R2); wherein, a source of the second NMOSFET (MN) is connected to a drain of the third NMOSFET (M2) and serves as the output end of the reference voltage; a gate and a drain of the second NMOSFET (MN) are connected to the current source circuit (I); a gate of the third NMOSFET (M2) is connected to a gate and a drain of the first NMOSFET (M1) and to a drain of the first PMOSFET (MP); a source of the third NMOSFET (M2) is grounded; a gate of the first PMOSFET (MP) is connected to a first end of the first resistor (R1) and a first end of the second resistor (R2); a source of the first PMOSFET (MP) is connected to a second end of the first resistor (R1) and to the current source circuit (I); a source of the first NMOSFET (M1) is grounded; a second end of the second resistor (R2) is grounded. <EOS>