A slave device for a synchronous bi-directional point-to-point serial bus, the slave device comprising: an upstream two-wire bus segment interface for connection to an upstream two- wire bus segment (1806 1 ); a downstream two-wire bus segment interface for connection to a downstream two-wire bus segment (1806 2 ); a transceiver having a transceiver upstream two-wire interface and a transceiver downstream two-wire interface; first and second upstream AC couplings (Cs) respectively connecting the transceiver upstream two-wire interface to the upstream two-wire bus segment interface (1806 1 ), the first and second upstream AC couplings substantially isolating the transceiver from bias voltages on the upstream two-wire bus segment interface; first and second downstream AC couplings respectively connecting the transceiver downstream two-wire interface to the downstream two-wire bus segment interface (1806 2 ); first and second upstream filters respectively coupled to first and second upstream connections between the upstream two-wire bus segment interface and the upstream AC couplings for outputting bias voltages tapped from the upstream two-wire bus segment (1806 1 ); and a power supply including a power supply input coupled to receive the bias voltages output by the first and second upstream filters and a power supply output configured to provide power to the slave device, wherein the transceiver is configured to recover a clock signal from encoded data signals received from the upstream two-wire bus interface and to transmit data signals to the downstream two-wire bus segment interface via the first and second downstream AC couplings, the data signals encoded to allow downstream slave devices to further recover the clock signal. an upstream two-wire bus segment interface for connection to an upstream two- wire bus segment (1806 1 ); a downstream two-wire bus segment interface for connection to a downstream two-wire bus segment (1806 2 ); a transceiver having a transceiver upstream two-wire interface and a transceiver downstream two-wire interface; first and second upstream AC couplings (Cs) respectively connecting the transceiver upstream two-wire interface to the upstream two-wire bus segment interface (1806 1 ), the first and second upstream AC couplings substantially isolating the transceiver from bias voltages on the upstream two-wire bus segment interface; first and second downstream AC couplings respectively connecting the transceiver downstream two-wire interface to the downstream two-wire bus segment interface (1806 2 ); first and second upstream filters respectively coupled to first and second upstream connections between the upstream two-wire bus segment interface and the upstream AC couplings for outputting bias voltages tapped from the upstream two-wire bus segment (1806 1 ); and a power supply including a power supply input coupled to receive the bias voltages output by the first and second upstream filters and a power supply output configured to provide power to the slave device, wherein the transceiver is configured to recover a clock signal from encoded data signals received from the upstream two-wire bus interface and to transmit data signals to the downstream two-wire bus segment interface via the first and second downstream AC couplings, the data signals encoded to allow downstream slave devices to further recover the clock signal. <EOS>