An imaging device , comprising: a pixel array including a plurality of pixel units in a matrix arrangement, at least a first pixel unit of the plurality of pixel units including: a substrate including a first photoelectric conversion region (PD0) and a second photoelectric conversion region (PD1); a first layer (M1) over the substrate and including a first pixel circuit coupled to the first photoelectric conversion region (PD0) and a second pixel circuit coupled to the second photoelectric conversion region (PD1), the first pixel circuit having one or more first transfer elements (TRG0, AMP0, SEL0, RST) to output a first pixel signal, the second pixel circuit having one or more second transfer elements (TRG1, AMP1, SEL1, RST) to output a second pixel signal; a second layer (M2) over the first layer (M1) and including first and second wirings extending in a first direction, the first wiring being spaced apart from the second wiring in a second direction that is perpendicular to the first direction, the first wiring being coupled to the one or more first transfer elements (TRG0, AMP0, SEL0, RST), the second wiring being coupled to the one or more second transfer elements (TRG1, AMP1, SEL1, RST); a third layer (M3) over the second layer (M2) and including signal lines (VSLO to VSL11) that extend in the second direction; a first via that couples a first signal line (VSLO) of the signal lines to the first wiring ; and characterised in that a second via is offset from the first via in the first direction and couples a second signal line (VSL6) of the signal lines (VSL0 to VSL11) to the second wiring , wherein, in a plan view, the first wiring overlaps at least a portion of the first pixel circuit, and the second wiring overlaps at least a portion of the second pixel circuit. a substrate including a first photoelectric conversion region (PD0) and a second photoelectric conversion region (PD1); a first layer (M1) over the substrate and including a first pixel circuit coupled to the first photoelectric conversion region (PD0) and a second pixel circuit coupled to the second photoelectric conversion region (PD1), the first pixel circuit having one or more first transfer elements (TRG0, AMP0, SEL0, RST) to output a first pixel signal, the second pixel circuit having one or more second transfer elements (TRG1, AMP1, SEL1, RST) to output a second pixel signal; a second layer (M2) over the first layer (M1) and including first and second wirings extending in a first direction, the first wiring being spaced apart from the second wiring in a second direction that is perpendicular to the first direction, the first wiring being coupled to the one or more first transfer elements (TRG0, AMP0, SEL0, RST), the second wiring being coupled to the one or more second transfer elements (TRG1, AMP1, SEL1, RST); a third layer (M3) over the second layer (M2) and including signal lines (VSLO to VSL11) that extend in the second direction; a first via that couples a first signal line (VSLO) of the signal lines to the first wiring ; and characterised in that a second via is offset from the first via in the first direction and couples a second signal line (VSL6) of the signal lines (VSL0 to VSL11) to the second wiring , wherein, in a plan view, the first wiring overlaps at least a portion of the first pixel circuit, and the second wiring overlaps at least a portion of the second pixel circuit. <EOS>