A method of forming a semiconductor device, comprising: providing a semiconductor substrate comprising a main surface ; simultaneously forming an upper portion of a field electrode trench and a gate trench in the main surface of the substrate to the same depth; forming a first protective layer on the substrate , the first protective layer completely filling the gate trench and lining sidewalls of the upper portion of the field electrode trench , a bottom of the upper portion of the field electrode trench being exposed from the first protective layer ; removing semiconductor material from the exposed bottom of the upper portion of the field electrode trench thereby forming a lower portion of the field electrode trench while the gate trench remains completely filled by the first protective layer ; forming a field electrode dielectric layer followed by an electrically conductive field electrode layer in the upper and lower portions of the field electrode trench while the gate trench remains completely filled by the first protective layer, wherein, in the upper portion of the field electrode trench , the field electrode dielectric layer covers the remaining sections of the first protective layer and wherein the field electrode dielectric layer lines the bottom and sidewalls of the lower portion of the field electrode trench ; removing at least some of the first protective layer from the gate trench ; forming a conformal gate dielectric layer that covers the field electrode and lines sidewalls of the gate trench after removing the at least some of the first protective layer ; and forming an electrically conductive gate electrode in the gate trench while the field electrode remains covered by the gate dielectric layer . providing a semiconductor substrate comprising a main surface ; simultaneously forming an upper portion of a field electrode trench and a gate trench in the main surface of the substrate to the same depth; forming a first protective layer on the substrate , the first protective layer completely filling the gate trench and lining sidewalls of the upper portion of the field electrode trench , a bottom of the upper portion of the field electrode trench being exposed from the first protective layer ; removing semiconductor material from the exposed bottom of the upper portion of the field electrode trench thereby forming a lower portion of the field electrode trench while the gate trench remains completely filled by the first protective layer ; forming a field electrode dielectric layer followed by an electrically conductive field electrode layer in the upper and lower portions of the field electrode trench while the gate trench remains completely filled by the first protective layer, wherein, in the upper portion of the field electrode trench , the field electrode dielectric layer covers the remaining sections of the first protective layer and wherein the field electrode dielectric layer lines the bottom and sidewalls of the lower portion of the field electrode trench ; removing at least some of the first protective layer from the gate trench ; forming a conformal gate dielectric layer that covers the field electrode and lines sidewalls of the gate trench after removing the at least some of the first protective layer ; and forming an electrically conductive gate electrode in the gate trench while the field electrode remains covered by the gate dielectric layer . <EOS>