A switch comprising: a channel path comprising a first MOS transistor and a second MOS transistor arranged in a back to back configuration with a common source terminal and a common gate terminal , wherein a drain terminal of the first MOS transistor defines a first terminal of the channel path and a drain terminal of the second MOS transistor defines a second terminal of the channel path; and control circuitry comprising: a third MOS transistor comprising: a gate terminal coupled to the common source terminal ; a source terminal coupled to the common gate terminal by only one drive resistor ; and a drain terminal coupled to a first reference voltage terminal ; a first current source coupled between the first reference voltage terminal and the common gate terminal and configured to provide a first current; a second current source coupled between the source terminal of the third MOS transistor and a second reference voltage terminal , and configured to provide a second current greater than the first current; and a first switching arrangement configured to selectively enable and disable the first current source ; and a second switching arrangement configured to selectively couple the common source terminal to the second reference voltage terminal . a channel path comprising a first MOS transistor and a second MOS transistor arranged in a back to back configuration with a common source terminal and a common gate terminal , wherein a drain terminal of the first MOS transistor defines a first terminal of the channel path and a drain terminal of the second MOS transistor defines a second terminal of the channel path; and control circuitry comprising: a third MOS transistor comprising: a gate terminal coupled to the common source terminal ; a source terminal coupled to the common gate terminal by only one drive resistor ; and a drain terminal coupled to a first reference voltage terminal ; a first current source coupled between the first reference voltage terminal and the common gate terminal and configured to provide a first current; a second current source coupled between the source terminal of the third MOS transistor and a second reference voltage terminal , and configured to provide a second current greater than the first current; and a first switching arrangement configured to selectively enable and disable the first current source ; and a second switching arrangement configured to selectively couple the common source terminal to the second reference voltage terminal . a third MOS transistor comprising: a gate terminal coupled to the common source terminal ; a source terminal coupled to the common gate terminal by only one drive resistor ; and a drain terminal coupled to a first reference voltage terminal ; a gate terminal coupled to the common source terminal ; a source terminal coupled to the common gate terminal by only one drive resistor ; and a drain terminal coupled to a first reference voltage terminal ; a first current source coupled between the first reference voltage terminal and the common gate terminal and configured to provide a first current; a second current source coupled between the source terminal of the third MOS transistor and a second reference voltage terminal , and configured to provide a second current greater than the first current; and a first switching arrangement configured to selectively enable and disable the first current source ; and a second switching arrangement configured to selectively couple the common source terminal to the second reference voltage terminal . <EOS>