A gate driving circuit comprising: a shift register (SR) including a plurality of stages (SRS) connected to each other by a cascade connection and sequentially outputting a gate voltage (VG) using a high level power voltage (VDD), a low level power voltage (VSS), a start voltage (VST) at the first stage (SRS1), a gate voltage (VG) from a previous stage at the second to nth stages (SRS2 to SRSn), a next stage gate voltage (VNEXT) and a clock (CLK), each of the plurality of stages (SRS) comprising: a first thin film transistor (TFT) (T1) switched by the start voltage (VST) or the previous stage gate voltage and transmitting the high level power voltage (VDD) to a Q node (Q); a second TFT (T2) switched by the next stage gate voltage (VNEXT) and transmitting the low level power voltage (VSS) to the Q node (Q); an eighth TFT (T8) switched by a voltage of the Q node (Q) and transmitting the clock (CLK) to an output node; second and third resistor (R2, R3) connected between the output node and the low level power voltage (VSS) in series; a third TFT (T3) switched by a voltage of a QB node (QB) and transmitting the low level power voltage (VSS) to the Q node (Q); a fourth TFT (T4) switched by the next stage gate voltage (VNEXT) and transmitting the high level power voltage (VDD) to the QB node (QB); a fifth TFT (T5) switched by the voltage of the Q node (Q) and transmitting the low level power voltage (VSS) to the QB node (QB); a sixth TFT (T6) switched by the high level power voltage (VDD) and transmitting the high level power voltage (VDD) to the QB node (QB); and a seventh TFT (T7) switched by the start voltage (VST) in the first stage (SRS1) and the gate voltage (VG) from a previous stage in the second to nth stages (SRS2 to SRSn) and transmitting the low level power voltage (VSS) to the QB node (QB); a ninth TFT (T9) switched by a voltage of the output node and transmitting the high level power voltage (VDD) to a first node (V1) between the second and third resistors (R2, R3); and a tenth TFT (T10) switched by the next stage gate voltage (VNEXT) and transmitting the low level power voltage (VSS) to the first node (V1). a first thin film transistor (TFT) (T1) switched by the start voltage (VST) or the previous stage gate voltage and transmitting the high level power voltage (VDD) to a Q node (Q); a second TFT (T2) switched by the next stage gate voltage (VNEXT) and transmitting the low level power voltage (VSS) to the Q node (Q); an eighth TFT (T8) switched by a voltage of the Q node (Q) and transmitting the clock (CLK) to an output node; second and third resistor (R2, R3) connected between the output node and the low level power voltage (VSS) in series; a third TFT (T3) switched by a voltage of a QB node (QB) and transmitting the low level power voltage (VSS) to the Q node (Q); a fourth TFT (T4) switched by the next stage gate voltage (VNEXT) and transmitting the high level power voltage (VDD) to the QB node (QB); a fifth TFT (T5) switched by the voltage of the Q node (Q) and transmitting the low level power voltage (VSS) to the QB node (QB); a sixth TFT (T6) switched by the high level power voltage (VDD) and transmitting the high level power voltage (VDD) to the QB node (QB); and a seventh TFT (T7) switched by the start voltage (VST) in the first stage (SRS1) and the gate voltage (VG) from a previous stage in the second to nth stages (SRS2 to SRSn) and transmitting the low level power voltage (VSS) to the QB node (QB); a ninth TFT (T9) switched by a voltage of the output node and transmitting the high level power voltage (VDD) to a first node (V1) between the second and third resistors (R2, R3); and a tenth TFT (T10) switched by the next stage gate voltage (VNEXT) and transmitting the low level power voltage (VSS) to the first node (V1). <EOS>