An apparatus comprising: a memory interface ; an input/output, IO, unit ; a processing cluster array of one or more processing clusters (214A-214N), each processing cluster (214A-214N) of the processing cluster array to execute an instruction in parallel across multiple threads; a processing cluster (214A-214N) of the processing cluster array comprising: a plurality of input registers to store vector input operands storing multiple packed input values, the input values of at least some of the vector input operands having different bit lengths than those of other input values of other vector input operands, and a compute unit to execute a dot-product instruction on the vector input operands to perform a number of parallel multiply operations and an accumulate operation per 32-bit lane of input corresponding to a bit length of the lowest-sized input value of a first vector input operand, wherein the bit length is determined relative to the 32-bit lane of input, the compute unit comprising: a multiplier to perform the number of parallel multiply operations of each of the lowest-sized input values with a corresponding input value of a second vector input operand to generate a corresponding number of products; and an adder to add the corresponding number of products to an accumulator value to generate an accumulation result. a memory interface ; an input/output, IO, unit ; a processing cluster array of one or more processing clusters (214A-214N), each processing cluster (214A-214N) of the processing cluster array to execute an instruction in parallel across multiple threads; a processing cluster (214A-214N) of the processing cluster array comprising: a plurality of input registers to store vector input operands storing multiple packed input values, the input values of at least some of the vector input operands having different bit lengths than those of other input values of other vector input operands, and a compute unit to execute a dot-product instruction on the vector input operands to perform a number of parallel multiply operations and an accumulate operation per 32-bit lane of input corresponding to a bit length of the lowest-sized input value of a first vector input operand, wherein the bit length is determined relative to the 32-bit lane of input, the compute unit comprising: a multiplier to perform the number of parallel multiply operations of each of the lowest-sized input values with a corresponding input value of a second vector input operand to generate a corresponding number of products; and an adder to add the corresponding number of products to an accumulator value to generate an accumulation result. a plurality of input registers to store vector input operands storing multiple packed input values, the input values of at least some of the vector input operands having different bit lengths than those of other input values of other vector input operands, and a compute unit to execute a dot-product instruction on the vector input operands to perform a number of parallel multiply operations and an accumulate operation per 32-bit lane of input corresponding to a bit length of the lowest-sized input value of a first vector input operand, wherein the bit length is determined relative to the 32-bit lane of input, the compute unit comprising: a multiplier to perform the number of parallel multiply operations of each of the lowest-sized input values with a corresponding input value of a second vector input operand to generate a corresponding number of products; and an adder to add the corresponding number of products to an accumulator value to generate an accumulation result. a multiplier to perform the number of parallel multiply operations of each of the lowest-sized input values with a corresponding input value of a second vector input operand to generate a corresponding number of products; and an adder to add the corresponding number of products to an accumulator value to generate an accumulation result. <EOS>