A semiconductor device with three-dimensional structure, comprising: a substrate comprising a memory region and a peripheral region located at an outer side of the memory region ; a memory structure located above the memory region and comprising a memory array and a plurality of signal lines , the memory array at least comprising a plurality of memory cells spaced apart from each other along a first direction, and the signal lines being electrically connected with the memory cells, wherein the first direction is perpendicular to a top surface of the substrate , wherein the signal lines comprise first signal lines and second signal lines , first signal line plugs are electrically connected to the first signal lines , second signal line plugs are electrically connected to the second signal lines ; a peripheral structure located above the peripheral region and comprising peripheral stacked layers , peripheral circuits located above the peripheral stacked layers , and a plurality of peripheral leads located above the peripheral circuits , one end of one of the peripheral leads being electrically connected with each of the peripheral circuits , and the other end being electrically connected with one of the signal lines , wherein the peripheral circuits comprise first peripheral circuits and second peripheral circuits , peripheral leads comprise first peripheral leads and second peripheral leads , first peripheral leads are electrically connected to the first peripheral circuits , second peripheral leads are electrically connected to the second peripheral circuits ; characterized by further comprising: first connecting bridges electrically connecting the first signal line plugs and the first peripheral leads , and second connecting bridges parallel to the first connecting bridges electrically connecting the second signal line plugs and the second peripheral leads . a substrate comprising a memory region and a peripheral region located at an outer side of the memory region ; a memory structure located above the memory region and comprising a memory array and a plurality of signal lines , the memory array at least comprising a plurality of memory cells spaced apart from each other along a first direction, and the signal lines being electrically connected with the memory cells, wherein the first direction is perpendicular to a top surface of the substrate , wherein the signal lines comprise first signal lines and second signal lines , first signal line plugs are electrically connected to the first signal lines , second signal line plugs are electrically connected to the second signal lines ; a peripheral structure located above the peripheral region and comprising peripheral stacked layers , peripheral circuits located above the peripheral stacked layers , and a plurality of peripheral leads located above the peripheral circuits , one end of one of the peripheral leads being electrically connected with each of the peripheral circuits , and the other end being electrically connected with one of the signal lines , wherein the peripheral circuits comprise first peripheral circuits and second peripheral circuits , peripheral leads comprise first peripheral leads and second peripheral leads , first peripheral leads are electrically connected to the first peripheral circuits , second peripheral leads are electrically connected to the second peripheral circuits ; characterized by further comprising: first connecting bridges electrically connecting the first signal line plugs and the first peripheral leads , and second connecting bridges parallel to the first connecting bridges electrically connecting the second signal line plugs and the second peripheral leads . <EOS>