A non-volatile memory device comprising: a memory cell array comprising a plurality of memory cells, MC, in which each memory cell is connected to a respective bit line, BL, from a plurality of bit lines that extend in a first direction, and comprise first to twelfth bit lines arranged in a second direction different from the first direction; and a page buffer circuit disposed below the memory cell array in a vertical direction different from the first direction and the second direction and having a multi-stage structure in the first direction, wherein a stage of the multi-stage structure comprises: a high voltage region, HV1, comprising a first high voltage transistor, TR1a, connected to one of first to sixth bit lines from the plurality of bit lines and a second high voltage transistor, TR1b, connected to one of seventh to twelfth bit lines from the plurality of bit lines, a first low voltage region, LV1a, comprising a first transistor, TRa, adjacent to the high voltage region in the first direction and connected to the first high voltage transistor, and a second low voltage region, LV1b, adjacent to the first low voltage region in the second direction and comprising a second transistor, TRb, connected to the second high voltage transistor, wherein each of the first low voltage region and the second low voltage region has a first width, WD1, corresponding to a pitch of six bit lines in the second direction, and wherein the high voltage region has a second width, WD2, corresponding to a pitch of twelve bit lines in the second direction. a memory cell array comprising a plurality of memory cells, MC, in which each memory cell is connected to a respective bit line, BL, from a plurality of bit lines that extend in a first direction, and comprise first to twelfth bit lines arranged in a second direction different from the first direction; and a page buffer circuit disposed below the memory cell array in a vertical direction different from the first direction and the second direction and having a multi-stage structure in the first direction, wherein a stage of the multi-stage structure comprises: a high voltage region, HV1, comprising a first high voltage transistor, TR1a, connected to one of first to sixth bit lines from the plurality of bit lines and a second high voltage transistor, TR1b, connected to one of seventh to twelfth bit lines from the plurality of bit lines, a first low voltage region, LV1a, comprising a first transistor, TRa, adjacent to the high voltage region in the first direction and connected to the first high voltage transistor, and a second low voltage region, LV1b, adjacent to the first low voltage region in the second direction and comprising a second transistor, TRb, connected to the second high voltage transistor, a high voltage region, HV1, comprising a first high voltage transistor, TR1a, connected to one of first to sixth bit lines from the plurality of bit lines and a second high voltage transistor, TR1b, connected to one of seventh to twelfth bit lines from the plurality of bit lines, a first low voltage region, LV1a, comprising a first transistor, TRa, adjacent to the high voltage region in the first direction and connected to the first high voltage transistor, and a second low voltage region, LV1b, adjacent to the first low voltage region in the second direction and comprising a second transistor, TRb, connected to the second high voltage transistor, wherein each of the first low voltage region and the second low voltage region has a first width, WD1, corresponding to a pitch of six bit lines in the second direction, and wherein the high voltage region has a second width, WD2, corresponding to a pitch of twelve bit lines in the second direction. <EOS>