A quantum dot semiconductor optical amplifier QD-SOA, wherein the quantum dot semiconductor optical amplifier comprises an epitaxial wafer , a buffer layer , a pre-etching layer , a plurality of nanowires , an n-electrode , and a p-electrode , wherein the buffer layer is located on an upper surface of the epitaxial wafer , the pre-etching layer is located on an upper surface of the buffer layer , and the pre-etching layer comprises a plurality of localization etching holes, wherein the plurality of localization etching holes penetrate the pre-etching layer to expose the buffer layer ; the plurality of nanowires are in a one-to-one correspondence to the plurality of localization etching holes, a bottom end of each nanowire is in contact with a bottom of a corresponding localization etching hole, a top end passes through the corresponding localization etching hole, a height of each nanowire is greater than a depth of a corresponding localization etching hole, and each nanowire comprises an n-type section, an active section, and a p-type section, wherein the active section is embedded with a plurality of layers of quantum dots; and the n-electrode is located on a surface of the epitaxial wafer , and the p-electrode is located above the plurality of nanowires , wherein a bottom end of the p-type section is in contact with the top end of the active section, a cross-sectional area of the p-type section gradually increases from the bottom end to a top end of the p-type section until a plurality of p-type sections adjacent to each other in the plurality of p-type sections included in the plurality of nanowires come into contact with each other to form a two-dimensional plane for subsequent preparation of the p-electrode on the two-dimensional plane. the buffer layer is located on an upper surface of the epitaxial wafer , the pre-etching layer is located on an upper surface of the buffer layer , and the pre-etching layer comprises a plurality of localization etching holes, wherein the plurality of localization etching holes penetrate the pre-etching layer to expose the buffer layer ; the plurality of nanowires are in a one-to-one correspondence to the plurality of localization etching holes, a bottom end of each nanowire is in contact with a bottom of a corresponding localization etching hole, a top end passes through the corresponding localization etching hole, a height of each nanowire is greater than a depth of a corresponding localization etching hole, and each nanowire comprises an n-type section, an active section, and a p-type section, wherein the active section is embedded with a plurality of layers of quantum dots; and the n-electrode is located on a surface of the epitaxial wafer , and the p-electrode is located above the plurality of nanowires , wherein a bottom end of the p-type section is in contact with the top end of the active section, a cross-sectional area of the p-type section gradually increases from the bottom end to a top end of the p-type section until a plurality of p-type sections adjacent to each other in the plurality of p-type sections included in the plurality of nanowires come into contact with each other to form a two-dimensional plane for subsequent preparation of the p-electrode on the two-dimensional plane. <EOS>