A method for forming a memory structure, the method comprising: providing a semiconductor substrate , wherein a number of discrete active areas are arranged in rows and columns on the semiconductor substrate , and a first groove is formed between two of the active areas that are adjacent, the first groove comprising a number of first trenches arranged in a column direction and a number of second trenches arranged in a row direction, the first trenches being filled with an insulating layer and the second trenches being filled with a first anti-etching dielectric layer ; forming a second anti-etching dielectric layer on a sidewall surface of the active area between adjacent first anti-etching dielectric layers and in the insulating layer ; etching each of the active areas to form two second grooves along the row direction in each of the active areas , wherein the two second grooves divide each active area into a drain located in the middle of the active area and two sources located at both sides of the drain , and the two second grooves are respectively located at both sides of the second anti-etching dielectric layer ; characterized by removing part of the insulating layer between the first anti-etching dielectric layer and the second anti-etching dielectric layer by etching, to form a third groove which exposes at least part of the surface of the sidewalls on both sides of the active area at a bottom of the second grooves and part of the surface of the sidewalls of the source and drain on both sides of the second grooves , the third groove being in connection with the second groove ; and forming a gate structure in the second groove and the third groove . providing a semiconductor substrate , wherein a number of discrete active areas are arranged in rows and columns on the semiconductor substrate , and a first groove is formed between two of the active areas that are adjacent, the first groove comprising a number of first trenches arranged in a column direction and a number of second trenches arranged in a row direction, the first trenches being filled with an insulating layer and the second trenches being filled with a first anti-etching dielectric layer ; forming a second anti-etching dielectric layer on a sidewall surface of the active area between adjacent first anti-etching dielectric layers and in the insulating layer ; etching each of the active areas to form two second grooves along the row direction in each of the active areas , wherein the two second grooves divide each active area into a drain located in the middle of the active area and two sources located at both sides of the drain , and the two second grooves are respectively located at both sides of the second anti-etching dielectric layer ; characterized by removing part of the insulating layer between the first anti-etching dielectric layer and the second anti-etching dielectric layer by etching, to form a third groove which exposes at least part of the surface of the sidewalls on both sides of the active area at a bottom of the second grooves and part of the surface of the sidewalls of the source and drain on both sides of the second grooves , the third groove being in connection with the second groove ; and forming a gate structure in the second groove and the third groove . <EOS>