An integrated circuit, IC , comprising: a monolithic semiconductor substrate; a first device disposed on the monolithic semiconductor substrate; a second device disposed on the monolithic semiconductor substrate; and an electrical node electrically connecting the first device and the second device , the electrical node comprising one or more electrically-conductive elements (P21, P31, P22) that contribute to a total capacitance at the electrical node , wherein a first subset of the one or more electrically-conductive elements comprises a primary wiring that electrically couples the first device to the second device , the primary wiring having a first end connected to an output terminal of the first device and a second end connected to an input terminal of the second device, a second subset of the one or more electrically-conductive elements comprises at least one compensation stub (S6) having a fixed end and a free end, and the at least one compensation stub (S6) is electrically coupled to the primary wiring through the fixed end and is terminated in the free end, wherein the total capacitance at the electrical node fulfills a hold-time requirement at the electrical node , wherein the at least one compensation stub (S6) is electrically coupled to the primary wiring by having the fixed end connected to a joint location of the primary wiring, the joint location is located on a first electrically-conductive layer of the IC and the fixed end is located on a second electrically-conductive layer of the IC adjacent to the first electrically-conductive layer; characterized in that the fixed end is connected to the joint location through one or more vias (V3) between the first and second electrically-conductive layers. a monolithic semiconductor substrate; a first device disposed on the monolithic semiconductor substrate; a second device disposed on the monolithic semiconductor substrate; and an electrical node electrically connecting the first device and the second device , the electrical node comprising one or more electrically-conductive elements (P21, P31, P22) that contribute to a total capacitance at the electrical node , wherein a first subset of the one or more electrically-conductive elements comprises a primary wiring that electrically couples the first device to the second device , the primary wiring having a first end connected to an output terminal of the first device and a second end connected to an input terminal of the second device, a second subset of the one or more electrically-conductive elements comprises at least one compensation stub (S6) having a fixed end and a free end, and the at least one compensation stub (S6) is electrically coupled to the primary wiring through the fixed end and is terminated in the free end, wherein the total capacitance at the electrical node fulfills a hold-time requirement at the electrical node , wherein the at least one compensation stub (S6) is electrically coupled to the primary wiring by having the fixed end connected to a joint location of the primary wiring, the joint location is located on a first electrically-conductive layer of the IC and the fixed end is located on a second electrically-conductive layer of the IC adjacent to the first electrically-conductive layer; characterized in that the fixed end is connected to the joint location through one or more vias (V3) between the first and second electrically-conductive layers. <EOS>