Method for determining an optimal voltage pulse for programming a NOR-type flash memory cell comprising a floating gate , a control gate and a drain , said optimal voltage pulse, to apply to the control gate of the memory cell, being defined by a voltage ramp from a non-zero initial voltage level (Vg start ) during a programming duration (t pulse ), the method comprising the following steps: - providing a set of parameters including a programming window target value (PW TG ) and a drain current target value (Id TG ) of the memory cell ; - dynamically measuring (F1) the drain current (Id) of the memory cell when a rectangular-shaped voltage pulse is applied to the control gate ; - providing a transistor equivalent to the memory cell and comprising a gate electrode (G') and a drain electrode (D'), such that the drain current (Id TREQ ) of the transistor is equal to the drain current (Id) of the memory cell when the gate electrode (G') of the transistor is brought to a potential (Vg TREQ ) equal to the potential of the floating gate (V FG ) of the memory cell; - dynamically measuring (F2) the drain current (Id TREQ ) of the transistor as a function of the potential (Vg TREQ ) of the gate electrode (G') of the transistor ; - determining (F3) the potential of the floating gate (V FG ) during the rectangular-shaped voltage pulse , from the measurement of the drain current (Id) of the memory cell and the measurement of the drain current (Id TREQ ) of the transistor ; - determining, respectively from the drain current target value (Id TG ), the potential of the floating gate (V FG ) during the rectangular-shaped voltage pulse and from the programming window target value (PW TG ), the initial voltage level (Vg start ), the slope (S) of the voltage ramp and the programming duration (t pulse ), such that the drain current (Id) of the memory cell during the optimal voltage pulse is substantially equal to the drain current target value (Id TG ); and wherein the drain (D) is brought, during the measurement of the drain current (Id) of the memory cell , to a constant potential (Vd PROG ) identical to that of the drain electrode (D') during the measurement of the drain current (Id TREQ ) of the transistor . - providing a set of parameters including a programming window target value (PW TG ) and a drain current target value (Id TG ) of the memory cell ; - dynamically measuring (F1) the drain current (Id) of the memory cell when a rectangular-shaped voltage pulse is applied to the control gate ; - providing a transistor equivalent to the memory cell and comprising a gate electrode (G') and a drain electrode (D'), such that the drain current (Id TREQ ) of the transistor is equal to the drain current (Id) of the memory cell when the gate electrode (G') of the transistor is brought to a potential (Vg TREQ ) equal to the potential of the floating gate (V FG ) of the memory cell; - dynamically measuring (F2) the drain current (Id TREQ ) of the transistor as a function of the potential (Vg TREQ ) of the gate electrode (G') of the transistor ; - determining (F3) the potential of the floating gate (V FG ) during the rectangular-shaped voltage pulse , from the measurement of the drain current (Id) of the memory cell and the measurement of the drain current (Id TREQ ) of the transistor ; - determining, respectively from the drain current target value (Id TG ), the potential of the floating gate (V FG ) during the rectangular-shaped voltage pulse and from the programming window target value (PW TG ), the initial voltage level (Vg start ), the slope (S) of the voltage ramp and the programming duration (t pulse ), such that the drain current (Id) of the memory cell during the optimal voltage pulse is substantially equal to the drain current target value (Id TG ); <EOS>