A program-inhibit method for a NAND flash memory device , comprising: increasing a voltage applied to a first access line connected to a control gate of an unprogrammed first memory cell in a string of series-connected memory cells from a first voltage (Vlow) to a second voltage (Vint) while a voltage applied to second access lines connected to control gates of second memory cells in the string of series-connected memory cells is at the first voltage; increasing the voltage applied to the second access lines from the first voltage to a pass voltage (Vpass) concurrently with increasing the voltage applied to the first access line from the second voltage (Vint) to a program voltage (Vpgm); applying a first deactivation voltage (Vdeactlow) to a control gate of a select transistor connected to an end of the string of series-connected memory cells while the first access line is at the first voltage, wherein the first deactivation voltage is configured to deactivate the select transistor; and applying a second deactivation voltage (Vdeacthigh), higher than the first deactivation voltage, to the control gate of the select transistor while the first access line is at the second voltage, while the voltage applied to the first access line is increasing from the second voltage to the program voltage, and while the first access line is at the program voltage, wherein the second deactivation voltage is configured to deactivate the select transistor; wherein the unprogrammed first memory cell is being inhibited; wherein the first access line is further connected to a target memory cell that is being programmed; wherein a voltage difference between the program voltage and the second voltage is equal to a voltage difference between the pass voltage and the first voltage; and wherein the second memory cells in the string of series-connected memory cells comprise all of the memory cells in the string of series-connected memory cells other than the unprogrammed first memory cell. increasing a voltage applied to a first access line connected to a control gate of an unprogrammed first memory cell in a string of series-connected memory cells from a first voltage (Vlow) to a second voltage (Vint) while a voltage applied to second access lines connected to control gates of second memory cells in the string of series-connected memory cells is at the first voltage; increasing the voltage applied to the second access lines from the first voltage to a pass voltage (Vpass) concurrently with increasing the voltage applied to the first access line from the second voltage (Vint) to a program voltage (Vpgm); applying a first deactivation voltage (Vdeactlow) to a control gate of a select transistor connected to an end of the string of series-connected memory cells while the first access line is at the first voltage, wherein the first deactivation voltage is configured to deactivate the select transistor; and applying a second deactivation voltage (Vdeacthigh), higher than the first deactivation voltage, to the control gate of the select transistor while the first access line is at the second voltage, while the voltage applied to the first access line is increasing from the second voltage to the program voltage, and while the first access line is at the program voltage, wherein the second deactivation voltage is configured to deactivate the select transistor; wherein the unprogrammed first memory cell is being inhibited; wherein the first access line is further connected to a target memory cell that is being programmed; wherein a voltage difference between the program voltage and the second voltage is equal to a voltage difference between the pass voltage and the first voltage; and wherein the second memory cells in the string of series-connected memory cells comprise all of the memory cells in the string of series-connected memory cells other than the unprogrammed first memory cell. <EOS>