A Digital Video Recorder (DVR) for storing video data received from an imaging device, comprising: a communication port configured to connect to the imaging device via a coaxial cable; a processor including a processing module and a detection module, wherein the processing module is configured to determine whether the DVR receives video data from the imaging device through the communication port; and the detection module is configured to acquire an operating voltage across the imaging device in a circuit when the DVR fails to receive the video data, the detection module including a Metal Oxide Semi-Conductor Field Effect Transistor (MOS FET), a first resistor, a diode, a capacitor, and a first power source, wherein a gate of the MOS FET connects to the processing module; a source of the MOS FET connects to the first power source; a drain of the MOS FET connects to a first end of the first resistor, the processing module being configured to provide an appropriate voltage to the gate of the MOS FET to make the source and the drain of the MOS FET being conducted; a second end of the first resistor connects to an anode of the diode; and a cathode of the diode connects to a first connection node between the communication port and the capacitor; and a power supply switch configured to turn on or off a power supply to the imaging device based on the operating voltage of the imaging device. a communication port configured to connect to the imaging device via a coaxial cable; a processor including a processing module and a detection module, wherein the processing module is configured to determine whether the DVR receives video data from the imaging device through the communication port; and the detection module is configured to acquire an operating voltage across the imaging device in a circuit when the DVR fails to receive the video data, the detection module including a Metal Oxide Semi-Conductor Field Effect Transistor (MOS FET), a first resistor, a diode, a capacitor, and a first power source, wherein a gate of the MOS FET connects to the processing module; a source of the MOS FET connects to the first power source; a drain of the MOS FET connects to a first end of the first resistor, the processing module being configured to provide an appropriate voltage to the gate of the MOS FET to make the source and the drain of the MOS FET being conducted; a second end of the first resistor connects to an anode of the diode; and a cathode of the diode connects to a first connection node between the communication port and the capacitor; and a gate of the MOS FET connects to the processing module; a source of the MOS FET connects to the first power source; a drain of the MOS FET connects to a first end of the first resistor, the processing module being configured to provide an appropriate voltage to the gate of the MOS FET to make the source and the drain of the MOS FET being conducted; a second end of the first resistor connects to an anode of the diode; and a cathode of the diode connects to a first connection node between the communication port and the capacitor; and a power supply switch configured to turn on or off a power supply to the imaging device based on the operating voltage of the imaging device. <EOS>