A content-addressable memory comprising: a match line (ML) extending in a first direction; a word line (WL) spaced apart from the match line, the word line extending parallel to the first direction; a search line (SL) spaced apart from the match line and the word line; and a plurality of memory cells respectively connected to the match line, the word line, and the search line, wherein at least one of the plurality of memory cells includes a source electrode and a drain electrode spaced apart from each other, characterised in that the at least one of the plurality of memory cells further includes : a first channel layer and a second channel layer doped with different dopants, the first channel layer and the second channel layer between the source electrode and the drain electrode such that a first end of the first channel layer and a first end of the second channel layer contact the source electrode and a second end of the first channel layer and a second end of the second channel layer contact the drain electrode, and a gate electrode spaced apart from all of the first channel layer, the second channel layer, the source electrode, and the drain electrode, wherein the first channel layer is doped with an n-type dopant and the second channel layer is doped with an p-type dopant, so that the source electrode , the drain electrode , the first channel layer , and gate electrode operate as an n-type transistor, and the source electrode , the drain electrode , the second channel layer , and gate electrode operate as a p-type transistor. a match line (ML) extending in a first direction; a word line (WL) spaced apart from the match line, the word line extending parallel to the first direction; a search line (SL) spaced apart from the match line and the word line; and a plurality of memory cells respectively connected to the match line, the word line, and the search line, wherein at least one of the plurality of memory cells includes a source electrode and a drain electrode spaced apart from each other, characterised in that the at least one of the plurality of memory cells further includes : a first channel layer and a second channel layer doped with different dopants, the first channel layer and the second channel layer between the source electrode and the drain electrode such that a first end of the first channel layer and a first end of the second channel layer contact the source electrode and a second end of the first channel layer and a second end of the second channel layer contact the drain electrode, and a gate electrode spaced apart from all of the first channel layer, the second channel layer, the source electrode, and the drain electrode, a first channel layer and a second channel layer doped with different dopants, the first channel layer and the second channel layer between the source electrode and the drain electrode such that a first end of the first channel layer and a first end of the second channel layer contact the source electrode and a second end of the first channel layer and a second end of the second channel layer contact the drain electrode, and a gate electrode spaced apart from all of the first channel layer, the second channel layer, the source electrode, and the drain electrode, wherein the first channel layer is doped with an n-type dopant and the second channel layer is doped with an p-type dopant, so that the source electrode , the drain electrode , the first channel layer , and gate electrode operate as an n-type transistor, and the source electrode , the drain electrode , the second channel layer , and gate electrode operate as a p-type transistor. <EOS>