Apparatus for processing data comprising: processing circuitry to perform processing operations specified by program instructions; an instruction decoder to decode said program instructions to generate control signals to control said processing circuitry to perform said processing operations; wherein said instruction decoder comprises loop-end instruction decoding circuitry to decode a loop-end instruction at a finish of a program loop body to generate control signals to control said processing circuitry to store loop control data, to determine if further loop iterations are required and, if further loop iterations are required to branch to a beginning instruction of said program loop body; and further comprising loop control circuitry to determine, when enabled, if further loop iterations are required, and if further loop iterations are required, to control said processing circuitry to perform processing operations specified by program instructions of said program loop body preceding said loop-end instruction, and excluding said loop-end instruction, under control of said loop control data; and said instruction decoder comprises loop-start instruction decoding circuitry to decode a loop-start instruction specifying a loop end address identifying an instruction following the loop end instruction, to generate control signals to control said processing circuitry to store a loop count value indicative of a number of times said program loop body is to be executed, and determine whether the loop count value indicates that the number of times said program loop body is to be executed is zero; and when the program loop body is to be executed zero times, the instruction decoder is configured to control the processing circuitry to branch to the instruction following the loop-end instruction or to suppress effects of instructions of said program loop body. processing circuitry to perform processing operations specified by program instructions; an instruction decoder to decode said program instructions to generate control signals to control said processing circuitry to perform said processing operations; wherein said instruction decoder comprises loop-end instruction decoding circuitry to decode a loop-end instruction at a finish of a program loop body to generate control signals to control said processing circuitry to store loop control data, to determine if further loop iterations are required and, if further loop iterations are required to branch to a beginning instruction of said program loop body; and further comprising loop control circuitry to determine, when enabled, if further loop iterations are required, and if further loop iterations are required, to control said processing circuitry to perform processing operations specified by program instructions of said program loop body preceding said loop-end instruction, and excluding said loop-end instruction, under control of said loop control data; and said instruction decoder comprises loop-start instruction decoding circuitry to decode a loop-start instruction specifying a loop end address identifying an instruction following the loop end instruction, to generate control signals to control said processing circuitry to store a loop count value indicative of a number of times said program loop body is to be executed, and determine whether the loop count value indicates that the number of times said program loop body is to be executed is zero; and when the program loop body is to be executed zero times, the instruction decoder is configured to control the processing circuitry to branch to the instruction following the loop-end instruction or to suppress effects of instructions of said program loop body. <EOS>