A display device comprising: a substrate (SUB) including a plurality of first thin film transistors (T1) and a plurality of second thin film transistors (T2); each of the first thin film transistors (T1) disposed on the substrate and including a polycrystalline semiconductor layer (A1), a first gate electrode (G1) on the polycrystalline semiconductor layer, a first source electrode (S1) and a first drain electrode (D1); each of the second thin film transistors (T2) disposed on the substrate and including a second gate electrode (G2), an oxide semiconductor layer (A2) on the second gate electrode, a second source electrode (S2) and a second drain electrode (D2); a gate insulating layer (GI) covering the poly crystalline semiconductor layer (A1); wherein the first gate electrode (G1) is disposed on the gate insulating layer and overlaps with the poly crystalline semiconductor layer (A1); wherein the second gate electrode (G2) is disposed on the gate insulating layer; an intermediate insulating layer (ILD) consisting of a lower oxide layer (SIO1) having a thickness of 500Å to 1500Å, a nitride layer (SIN) having a thickness of 1000Å to 2000Å directly on the lower oxide layer (SIO1), and an upper oxide layer (SIO2) having a thickness of 1000Å to 3000Å directly on the nitride layer (SIN), the intermediate insulating layer (ILD) being disposed directly on the first gate electrode (G1), the gate insulating layer (GI), and the second gate electrode (G2), and the intermediate insulating layer (ILD) being disposed directly under the oxide semiconductor layer (A2), the upper oxide layer (SIO2) being thicker than the nitride layer (SIN); wherein the first source electrode (S1) and the first drain electrode (D1) are disposed on the intermediate insulating layer (ILD); and wherein the second source electrode (S2) and the second drain electrode (D2) are disposed on the oxide semiconductor layer (A2). a substrate (SUB) including a plurality of first thin film transistors (T1) and a plurality of second thin film transistors (T2); each of the first thin film transistors (T1) disposed on the substrate and including a polycrystalline semiconductor layer (A1), a first gate electrode (G1) on the polycrystalline semiconductor layer, a first source electrode (S1) and a first drain electrode (D1); each of the second thin film transistors (T2) disposed on the substrate and including a second gate electrode (G2), an oxide semiconductor layer (A2) on the second gate electrode, a second source electrode (S2) and a second drain electrode (D2); a gate insulating layer (GI) covering the poly crystalline semiconductor layer (A1); wherein the first gate electrode (G1) is disposed on the gate insulating layer and overlaps with the poly crystalline semiconductor layer (A1); wherein the second gate electrode (G2) is disposed on the gate insulating layer; an intermediate insulating layer (ILD) consisting of a lower oxide layer (SIO1) having a thickness of 500Å to 1500Å, a nitride layer (SIN) having a thickness of 1000Å to 2000Å directly on the lower oxide layer (SIO1), and an upper oxide layer (SIO2) having a thickness of 1000Å to 3000Å directly on the nitride layer (SIN), the intermediate insulating layer (ILD) being disposed directly on the first gate electrode (G1), the gate insulating layer (GI), and the second gate electrode (G2), and the intermediate insulating layer (ILD) being disposed directly under the oxide semiconductor layer (A2), the upper oxide layer (SIO2) being thicker than the nitride layer (SIN); wherein the first source electrode (S1) and the first drain electrode (D1) are disposed on the intermediate insulating layer (ILD); and wherein the second source electrode (S2) and the second drain electrode (D2) are disposed on the oxide semiconductor layer (A2). <EOS>