A shift register unit, comprising: an input module adapted to provide an input signal (STV) to a first node (A) in response to a first clock signal inputted at a first clock signal input terminal (CLK1); a pull-up module adapted to provide a positive voltage (VGH) of a power supply to a second node (C) in response to the input signal (STV); a pull-down module adapted to provide a negative voltage (VGL) of the power supply to the second node (C) in response to a third clock signal inputted at a third clock signal input terminal (CLK3); a reset module adapted to provide the positive voltage (VGH) of the power supply to the first node (A) in response to a signal at the second node (C); a first output module connected between the positive voltage (VGH) of the power supply and the output node (Output) of the shift register unit, adapted to provide the positive voltage (VGH) of the power supply to an output node (Output) of the shift register unit in response to the signal at the second node (C), a second capacitor (C2) being provided between the positive voltage (VGH) of the power supply and the second node (C); a second output module adapted to provide a second clock signal inputted at a second clock signal terminal (CLK2) to a third node (D) in response to a signal at the first node (A), a first capacitor (C1) being provided between the third node (D) and the first node (A); characterised by a signal amplification module connected between the third node (D) and the output node (Output) of the shift register unit and adapted to amplify signal at the third node (D) for outputting to the output node (Output) of the shift register unit. an input module adapted to provide an input signal (STV) to a first node (A) in response to a first clock signal inputted at a first clock signal input terminal (CLK1); a pull-up module adapted to provide a positive voltage (VGH) of a power supply to a second node (C) in response to the input signal (STV); a pull-down module adapted to provide a negative voltage (VGL) of the power supply to the second node (C) in response to a third clock signal inputted at a third clock signal input terminal (CLK3); a reset module adapted to provide the positive voltage (VGH) of the power supply to the first node (A) in response to a signal at the second node (C); a first output module connected between the positive voltage (VGH) of the power supply and the output node (Output) of the shift register unit, adapted to provide the positive voltage (VGH) of the power supply to an output node (Output) of the shift register unit in response to the signal at the second node (C), a second capacitor (C2) being provided between the positive voltage (VGH) of the power supply and the second node (C); a second output module adapted to provide a second clock signal inputted at a second clock signal terminal (CLK2) to a third node (D) in response to a signal at the first node (A), a first capacitor (C1) being provided between the third node (D) and the first node (A); characterised by a signal amplification module connected between the third node (D) and the output node (Output) of the shift register unit and adapted to amplify signal at the third node (D) for outputting to the output node (Output) of the shift register unit. <EOS>