A computing system , comprising: a host system ; a memory bus ; a plurality of memory components (109A ...; 109N; 221, ... , 223, ..., 225) of different tiers; and a processing device (115, 117; 227, 113), operatively coupled to the plurality of memory components (109A ...; 109N; 221, ..., 223, ..., 225), said processing device and at least a portion of the plurality of memory components (221, ..., 223) being configured on a memory module of the computing system, said memory module being connected to the host system via the memory bus , and the processing device configured with a data stream segregator to at least: receive data access requests via the memory bus from the host system ; generate, by the data stream segregator , a plurality of data access streams in accordance with the data access requests received in the processing device and respective access characteristics of the data access requests; match, by the data stream segregator , characteristics of the data access streams with characteristics of the different tiers of the memory components (109A ...; 109N; 221, ... , 223, ..., 225); and direct, by the data stream segregator , the plurality of data access streams to the different tiers of the memory components (109A ...; 109N; 221, ... , 223, ..., 225) based on matching the characteristics of the data access streams with the characteristics of the different tiers of the memory components (109A ...; 109N; 221, ..., 223, ..., 225), characterized in that the memory bus comprises a double data rate bus. a host system ; a memory bus ; a plurality of memory components (109A ...; 109N; 221, ... , 223, ..., 225) of different tiers; and a processing device (115, 117; 227, 113), operatively coupled to the plurality of memory components (109A ...; 109N; 221, ..., 223, ..., 225), said processing device and at least a portion of the plurality of memory components (221, ..., 223) being configured on a memory module of the computing system, said memory module being connected to the host system via the memory bus , and the processing device configured with a data stream segregator to at least: receive data access requests via the memory bus from the host system ; generate, by the data stream segregator , a plurality of data access streams in accordance with the data access requests received in the processing device and respective access characteristics of the data access requests; match, by the data stream segregator , characteristics of the data access streams with characteristics of the different tiers of the memory components (109A ...; 109N; 221, ... , 223, ..., 225); and direct, by the data stream segregator , the plurality of data access streams to the different tiers of the memory components (109A ...; 109N; 221, ... , 223, ..., 225) based on matching the characteristics of the data access streams with the characteristics of the different tiers of the memory components (109A ...; 109N; 221, ..., 223, ..., 225), receive data access requests via the memory bus from the host system ; generate, by the data stream segregator , a plurality of data access streams in accordance with the data access requests received in the processing device and respective access characteristics of the data access requests; match, by the data stream segregator , characteristics of the data access streams with characteristics of the different tiers of the memory components (109A ...; 109N; 221, ... , 223, ..., 225); and direct, by the data stream segregator , the plurality of data access streams to the different tiers of the memory components (109A ...; 109N; 221, ... , 223, ..., 225) based on matching the characteristics of the data access streams with the characteristics of the different tiers of the memory components (109A ...; 109N; 221, ..., 223, ..., 225), characterized in that the memory bus comprises a double data rate bus. <EOS>