A method for fabricating a semiconductor structure, comprising: providing a substrate having a dielectric layer formed on the substrate , wherein an opening is formed in the dielectric layer , and bottom of the opening exposes surface of the substrate ; forming a first metal layer over the top of the dielectric layer , wherein a temperature for forming the first metal layer is a first temperature; forming a second metal layer filling the opening , wherein a temperature for forming the second metal layer is a second temperature, and the second temperature is higher than the first temperature; and planarizing the second metal layer and the first metal layer until the top surface of the dielectric layer is exposed, the planarizing process including: performing a first planarization process to remove the second metal layer formed over the dielectric layer , wherein the first planarization process also includes: removing part of thickness of the first metal layer formed over the dielectric layer , such that the thickness of the first metal layer formed over the dielectric layer reaches a preset thickness; performing a second planarization process to remove the first metal layer formed over the dielectric layer until the top surface of the liner structure layer is exposed; and performing a third planarization process until the top surface of the remaining second metal layer and the top surface of the dielectric layer are flush. providing a substrate having a dielectric layer formed on the substrate , wherein an opening is formed in the dielectric layer , and bottom of the opening exposes surface of the substrate ; forming a first metal layer over the top of the dielectric layer , wherein a temperature for forming the first metal layer is a first temperature; forming a second metal layer filling the opening , wherein a temperature for forming the second metal layer is a second temperature, and the second temperature is higher than the first temperature; and planarizing the second metal layer and the first metal layer until the top surface of the dielectric layer is exposed, the planarizing process including: performing a first planarization process to remove the second metal layer formed over the dielectric layer , wherein the first planarization process also includes: removing part of thickness of the first metal layer formed over the dielectric layer , such that the thickness of the first metal layer formed over the dielectric layer reaches a preset thickness; performing a second planarization process to remove the first metal layer formed over the dielectric layer until the top surface of the liner structure layer is exposed; and performing a third planarization process until the top surface of the remaining second metal layer and the top surface of the dielectric layer are flush. removing part of thickness of the first metal layer formed over the dielectric layer , such that the thickness of the first metal layer formed over the dielectric layer reaches a preset thickness; performing a second planarization process to remove the first metal layer formed over the dielectric layer until the top surface of the liner structure layer is exposed; and performing a third planarization process until the top surface of the remaining second metal layer and the top surface of the dielectric layer are flush. <EOS>