An image chip , used for image synthesis and comprising: a layer division unit , configured to divide an image frame into at least two image segments perpendicular to a first coordinate axis, wherein the image frame includes multiple layers, any image segment comprises a part that is in at least one layer and that falls within an interval at which the any image segment is located, and a part that is in any layer and that falls within the interval at which the any image segment is located is a sublayer of the any layer; an image reading unit , configured to read, along a direction of the first coordinate axis, in a time-division manner and according to a scanning sequence, the at least two image segments obtained by division by the layer division unit ; and an image synthesis unit , configured to successively perform image synthesis on the at least two image segments according to a time sequence in which the image reading unit reads the at least two image segments in the time-division manner, so as to generate display data corresponding to the image frame, wherein image synthesis for an image segment comprises image synthesis for all sublayers that are comprised in the image segment; characterized by that the chip further comprises: an obtaining unit , configured to separately obtain two coordinates, on the first coordinate axis, corresponding to two boundaries that are of each layer in the multiple layers and that are perpendicular to the first coordinate axis, so as to obtain multiple coordinates corresponding to the multiple layers, wherein each layer is a rectangular layer wherein the layer division unit is specifically configured to divide the image frame into the at least two image segments by using the multiple coordinates according to all sorted coordinates, two boundaries of the any image segment correspond to two neighboring coordinates in the multiple coordinates. a layer division unit , configured to divide an image frame into at least two image segments perpendicular to a first coordinate axis, wherein the image frame includes multiple layers, any image segment comprises a part that is in at least one layer and that falls within an interval at which the any image segment is located, and a part that is in any layer and that falls within the interval at which the any image segment is located is a sublayer of the any layer; an image reading unit , configured to read, along a direction of the first coordinate axis, in a time-division manner and according to a scanning sequence, the at least two image segments obtained by division by the layer division unit ; and an image synthesis unit , configured to successively perform image synthesis on the at least two image segments according to a time sequence in which the image reading unit reads the at least two image segments in the time-division manner, so as to generate display data corresponding to the image frame, wherein image synthesis for an image segment comprises image synthesis for all sublayers that are comprised in the image segment; characterized by that the chip further comprises: an obtaining unit , configured to separately obtain two coordinates, on the first coordinate axis, corresponding to two boundaries that are of each layer in the multiple layers and that are perpendicular to the first coordinate axis, so as to obtain multiple coordinates corresponding to the multiple layers, wherein each layer is a rectangular layer wherein the layer division unit is specifically configured to divide the image frame into the at least two image segments by using the multiple coordinates according to all sorted coordinates, two boundaries of the any image segment correspond to two neighboring coordinates in the multiple coordinates. <EOS>