A receive beamformer comprising a delay element (46 1 -46 N ) including an analog random access memory, ARAM, , wherein the delay element comprises: an input line configured to receive an input analog electrical signal generated from an acoustic signal received by an array of transducer elements ; a write shift register (66 1 , 70) configured to operate a plurality of write switches (65 1 -65 M ) connected to the input line; a plurality of capacitive elements (62 1 -62 M ) configured to store a charge that can be read from a plurality of outputs of each capacitive element at different delay times; a plurality of read shift registers (66 2 , 72 1 ; 66 3 , 72 2 ) configured to operate a plurality of read switches (67 1 -67 M ; 68 1 -68 M ) connected to the plurality of outputs of each capacitive element, such that the charge in each capacitive element is read at the different delay times from different outputs of each capacitive element; and a plurality of summing elements (48 1 , 48 2 ; 89 a , 89 b ), each summing element being configured to sum output signals from one of the plurality of outputs of each capacitive element; wherein at least one capacitive element of the plurality of capacitive elements includes a capacitor (62; 62 a , 62 b ) that is coupled to the input line and a DC voltage source (82 a ; 82 b ) during a write operation, and wherein each of the plurality of outputs of the at least one capacitive element of the plurality of capacitive elements is coupled via the corresponding read switch (67 1 -67 M ; 68 1 -68 M ) to an inverting amplifier (88 a ; 88 b ) configured to allow interrogation of a stored charge on the capacitor that can be non-destructively read at the different delay times. an input line configured to receive an input analog electrical signal generated from an acoustic signal received by an array of transducer elements ; a write shift register (66 1 , 70) configured to operate a plurality of write switches (65 1 -65 M ) connected to the input line; a plurality of capacitive elements (62 1 -62 M ) configured to store a charge that can be read from a plurality of outputs of each capacitive element at different delay times; a plurality of read shift registers (66 2 , 72 1 ; 66 3 , 72 2 ) configured to operate a plurality of read switches (67 1 -67 M ; 68 1 -68 M ) connected to the plurality of outputs of each capacitive element, such that the charge in each capacitive element is read at the different delay times from different outputs of each capacitive element; and a plurality of summing elements (48 1 , 48 2 ; 89 a , 89 b ), each summing element being configured to sum output signals from one of the plurality of outputs of each capacitive element; wherein at least one capacitive element of the plurality of capacitive elements includes a capacitor (62; 62 a , 62 b ) that is coupled to the input line and a DC voltage source (82 a ; 82 b ) during a write operation, and wherein each of the plurality of outputs of the at least one capacitive element of the plurality of capacitive elements is coupled via the corresponding read switch (67 1 -67 M ; 68 1 -68 M ) to an inverting amplifier (88 a ; 88 b ) configured to allow interrogation of a stored charge on the capacitor that can be non-destructively read at the different delay times. <EOS>