A microprocessor , comprising: an indicator; and a plurality of processing cores , each configured to generate a default core ID number for itself, wherein each default core ID is unique; wherein each of the plurality of processing cores is configured to sample the indicator; wherein when the indicator indicates a first predetermined value, the default core ID generated by a default one of the processing cores designates the default processing core to be a bootstrap processor; wherein when the indicator indicates a second predetermined value distinct from the first predetermined value, the plurality of processing cores are each configured to generate alternate core IDs that are different from the default core IDs, wherein one of the alternate core IDs designates an alternate processing core, other than the default processing core, to be the bootstrap processor; wherein each processing core of the plurality of processing cores is configured to: set the default core ID of the processing core as a distinct respective default interrupt controller identifier associated with the processing core ; and when the indicator indicates the second predetermined value, modify the associated default respective interrupt controller identifier such that the processing core has a new distinct respective interrupt controller identifier corresponding to the alternate core ID; and wherein to generate the alternate core IDs, the plurality of processing cores are configured to rotate the default respective core IDs among themselves. an indicator; and a plurality of processing cores , each configured to generate a default core ID number for itself, wherein each default core ID is unique; wherein each of the plurality of processing cores is configured to sample the indicator; wherein when the indicator indicates a first predetermined value, the default core ID generated by a default one of the processing cores designates the default processing core to be a bootstrap processor; wherein when the indicator indicates a second predetermined value distinct from the first predetermined value, the plurality of processing cores are each configured to generate alternate core IDs that are different from the default core IDs, wherein one of the alternate core IDs designates an alternate processing core, other than the default processing core, to be the bootstrap processor; wherein each processing core of the plurality of processing cores is configured to: set the default core ID of the processing core as a distinct respective default interrupt controller identifier associated with the processing core ; and when the indicator indicates the second predetermined value, modify the associated default respective interrupt controller identifier such that the processing core has a new distinct respective interrupt controller identifier corresponding to the alternate core ID; and set the default core ID of the processing core as a distinct respective default interrupt controller identifier associated with the processing core ; and when the indicator indicates the second predetermined value, modify the associated default respective interrupt controller identifier such that the processing core has a new distinct respective interrupt controller identifier corresponding to the alternate core ID; and wherein to generate the alternate core IDs, the plurality of processing cores are configured to rotate the default respective core IDs among themselves. <EOS>