A processor comprising: a decode stage to decode a first instruction for a Single Instruction Multiple Data (SIMD) SM4 block cipher algorithm operation, the first instruction specifying a first source data operand set of elements , a second source data operand set of elements , and one or more substitution function indicators; and one or more execution units , responsive to the decoded first instruction, to: perform one or more SM4-round exchange on a first portion of the first source data operand set of elements with a corresponding first one or more keys from the second source data operand set of elements in response to a first indicator of said one or more substitution function indicators which indicates a first substitution function; characterized in that the one or more execution units , responsive to the decoded first instruction, to also perform one or more SM4 key generation on a second portion of the first source data operand set of elements with a corresponding first one or more constants from the second source data operand set of elements in response to a second indicator of said one or more substitution function indicators which indicates a second substitution function; and store a result set of elements of the first instruction in a SIMD destination register. a decode stage to decode a first instruction for a Single Instruction Multiple Data (SIMD) SM4 block cipher algorithm operation, the first instruction specifying a first source data operand set of elements , a second source data operand set of elements , and one or more substitution function indicators; and one or more execution units , responsive to the decoded first instruction, to: perform one or more SM4-round exchange on a first portion of the first source data operand set of elements with a corresponding first one or more keys from the second source data operand set of elements in response to a first indicator of said one or more substitution function indicators which indicates a first substitution function; characterized in that the one or more execution units , responsive to the decoded first instruction, to also perform one or more SM4 key generation on a second portion of the first source data operand set of elements with a corresponding first one or more constants from the second source data operand set of elements in response to a second indicator of said one or more substitution function indicators which indicates a second substitution function; and store a result set of elements of the first instruction in a SIMD destination register. perform one or more SM4-round exchange on a first portion of the first source data operand set of elements with a corresponding first one or more keys from the second source data operand set of elements in response to a first indicator of said one or more substitution function indicators which indicates a first substitution function; characterized in that the one or more execution units , responsive to the decoded first instruction, to also perform one or more SM4 key generation on a second portion of the first source data operand set of elements with a corresponding first one or more constants from the second source data operand set of elements in response to a second indicator of said one or more substitution function indicators which indicates a second substitution function; and store a result set of elements of the first instruction in a SIMD destination register. <EOS>