An electroluminescent display device, comprising: a substrate ; a high level power line (VDD) and a low level power line (VSS) arranged in a first direction on the substrate ; a plurality of circuit device columns (C1, C2, C3) including a plurality of thin film transistors (T1, T2, T3) for controlling a light emission positioned between the high level power line (VDD) and the low level power line (VSS) on the substrate ; a bank formed in a matrix configuration on the substrate to define a plurality of emission areas (E1, E2, E3) next to each other that overlap with the high level power line (VDD), the low level power line (VSS), and the plurality of circuit device columns (C1, C2, C3); and a respective emission layer provided in each of the plurality of emission areas (E1, E2, E3), wherein the plurality of emission areas (E1, E2, E3) includes a red emission area (E1) having the smallest area which is provided on each of the high level power line (VDD) and the low level power line (VSS) and overlapped with each of the high level power line (VDD) and the low level power line (VSS), wherein the red emission area (E1) has a width (W1) which is the same as or less than at least one of a width (Wvdd) of the high level power line (VDD) and a width (Wvss) of the low level power line (VSS), wherein the plurality of emission areas (E1, E2, E3) additionally include a green emission area (E2) and a blue emission area (E3) which are overlapped with at least one of the plurality of circuit device columns (C1, C2, C3), wherein the blue emission area (E3) is overlapped with two of the plurality of circuit device columns (C1, C2, C3), and a width (W3) of the blue emission area (E3) is larger than the width (W1) of the red emission area (E1) and a width (W2) of the green emission area (E2). a substrate ; a high level power line (VDD) and a low level power line (VSS) arranged in a first direction on the substrate ; a plurality of circuit device columns (C1, C2, C3) including a plurality of thin film transistors (T1, T2, T3) for controlling a light emission positioned between the high level power line (VDD) and the low level power line (VSS) on the substrate ; a bank formed in a matrix configuration on the substrate to define a plurality of emission areas (E1, E2, E3) next to each other that overlap with the high level power line (VDD), the low level power line (VSS), and the plurality of circuit device columns (C1, C2, C3); and a respective emission layer provided in each of the plurality of emission areas (E1, E2, E3), wherein the plurality of emission areas (E1, E2, E3) includes a red emission area (E1) having the smallest area which is provided on each of the high level power line (VDD) and the low level power line (VSS) and overlapped with each of the high level power line (VDD) and the low level power line (VSS), wherein the red emission area (E1) has a width (W1) which is the same as or less than at least one of a width (Wvdd) of the high level power line (VDD) and a width (Wvss) of the low level power line (VSS), wherein the plurality of emission areas (E1, E2, E3) additionally include a green emission area (E2) and a blue emission area (E3) which are overlapped with at least one of the plurality of circuit device columns (C1, C2, C3), wherein the blue emission area (E3) is overlapped with two of the plurality of circuit device columns (C1, C2, C3), and a width (W3) of the blue emission area (E3) is larger than the width (W1) of the red emission area (E1) and a width (W2) of the green emission area (E2). <EOS>