A discrete-time amplifier circuit operable in a sampling phase and an amplification phase, the amplifier circuit comprising: a plurality of switches (S 1 , S 2 ); a common-mode voltage (ground); a first capacitor (C 1 ) having a first terminal and a second terminal; a second capacitor (C 2 ) having a first terminal and a second terminal; and a first buffer amplifier (BA) having a voltage gain equal to 1-ε, where ε<<1, the first buffer amplifier having an input terminal and an output terminal , wherein: during the sampling phase, the plurality of switches are configured to couple a first input voltage (V IN ) to the first terminal of the first capacitor and a second input voltage (V REF ) to the first terminal of the second capacitor, and wherein, also during the sampling phase, either the second terminals of the first capacitor and the second capacitor are coupled to the output terminal of the buffer amplifier and the input terminal of the buffer amplifier is coupled to the common-mode voltage, or the second terminals of the first capacitor and the second capacitor as well as the input terminal of the buffer amplifier are coupled to the common-mode voltage; and during the amplification phase, the plurality of switches are configured to couple the second terminals of the first and the second capacitors to the input terminal of the first buffer amplifier and the first terminals of the first and second capacitors to the output terminal of the first buffer amplifier. a plurality of switches (S 1 , S 2 ); a common-mode voltage (ground); a first capacitor (C 1 ) having a first terminal and a second terminal; a second capacitor (C 2 ) having a first terminal and a second terminal; and a first buffer amplifier (BA) having a voltage gain equal to 1-ε, where ε<<1, the first buffer amplifier having an input terminal and an output terminal , wherein: during the sampling phase, the plurality of switches are configured to couple a first input voltage (V IN ) to the first terminal of the first capacitor and a second input voltage (V REF ) to the first terminal of the second capacitor, and wherein, also during the sampling phase, either the second terminals of the first capacitor and the second capacitor are coupled to the output terminal of the buffer amplifier and the input terminal of the buffer amplifier is coupled to the common-mode voltage, or the second terminals of the first capacitor and the second capacitor as well as the input terminal of the buffer amplifier are coupled to the common-mode voltage; and during the amplification phase, the plurality of switches are configured to couple the second terminals of the first and the second capacitors to the input terminal of the first buffer amplifier and the first terminals of the first and second capacitors to the output terminal of the first buffer amplifier. during the sampling phase, the plurality of switches are configured to couple a first input voltage (V IN ) to the first terminal of the first capacitor and a second input voltage (V REF ) to the first terminal of the second capacitor, and wherein, also during the sampling phase, either the second terminals of the first capacitor and the second capacitor are coupled to the output terminal of the buffer amplifier and the input terminal of the buffer amplifier is coupled to the common-mode voltage, or the second terminals of the first capacitor and the second capacitor as well as the input terminal of the buffer amplifier are coupled to the common-mode voltage; and during the amplification phase, the plurality of switches are configured to couple the second terminals of the first and the second capacitors to the input terminal of the first buffer amplifier and the first terminals of the first and second capacitors to the output terminal of the first buffer amplifier. <EOS>