A three-level power inverter comprising: a first semiconductor device, a second semiconductor device, a third semiconductor device and a fourth semiconductor device, the semiconductor devices being four devices of a three-level electric power inverter circuit of the three-level power inverter; a plurality of insulating substrates on each of which at least one of the first semiconductor device to the fourth semiconductor devices is mounted; and a base plate on the surface of which the plurality of the insulating substrates are arranged, the surface of the base plate on which the plurality of the insulating substrates are arranged being divided grid-like into four regions (DA1-DA4), so that, respectively, one of the first to fourth semiconductor devices is arranged in each of the four regions (DA1-DA4) to thereby disperse heat generated in the first to fourth semiconductor devices, wherein the insulating substrates include at least one of first insulating substrates (SB11-SB13) that mounts two of the first to fourth semiconductor devices and at least one of second insulating substrates (SB21-SB23) that mounts the rest two of the first to fourth semiconductor devices, wherein in the four regions (DA1-DA4), in each of first and second diagonally positioned regions (DA1,DA3) (DA2,DA4), at least one of said semiconductor devices is arranged in the first diagonally positioned region, the three-level power inverter being configured such that in operation, said at least one of said semiconductor devices generates heat with the same timing as at least one of said semiconductor devices arranged in the second diagonally positioned region. a first semiconductor device, a second semiconductor device, a third semiconductor device and a fourth semiconductor device, the semiconductor devices being four devices of a three-level electric power inverter circuit of the three-level power inverter; a plurality of insulating substrates on each of which at least one of the first semiconductor device to the fourth semiconductor devices is mounted; and a base plate on the surface of which the plurality of the insulating substrates are arranged, the surface of the base plate on which the plurality of the insulating substrates are arranged being divided grid-like into four regions (DA1-DA4), so that, respectively, one of the first to fourth semiconductor devices is arranged in each of the four regions (DA1-DA4) to thereby disperse heat generated in the first to fourth semiconductor devices, wherein the insulating substrates include at least one of first insulating substrates (SB11-SB13) that mounts two of the first to fourth semiconductor devices and at least one of second insulating substrates (SB21-SB23) that mounts the rest two of the first to fourth semiconductor devices, wherein in the four regions (DA1-DA4), in each of first and second diagonally positioned regions (DA1,DA3) (DA2,DA4), at least one of said semiconductor devices is arranged in the first diagonally positioned region, the three-level power inverter being configured such that in operation, said at least one of said semiconductor devices generates heat with the same timing as at least one of said semiconductor devices arranged in the second diagonally positioned region. <EOS>