A high-voltage semiconductor device comprising: an n-type well region which is formed on a p-type semiconductor substrate and includes a logic circuit formation region and a withstand voltage region surrounding the logic circuit formation region ; a p-type well region which is formed on the semiconductor substrate so as to surround the withstand voltage region; a transistor which includes an n-type drain region selectively formed in a surface layer of the n-type well region between the withstand voltage region and the logic circuit formation region and having a higher concentration of impurities than the withstand voltage region, and an n-type source region selectively formed in the surface layer of the n-type well region , wherein the portion of the withstand voltage region situated between the drain region and the source region is a drift region of the transistor, and a portion of the p-type well region is a base region of the transistor; an opening region which is provided locally in the n-type well region between the drain region and the logic circuit formation region so as to prevent the n-type well region from lying all over the opening region in a depth direction; a conductive path which electrically connects the drain region with a logic circuit in the logic circuit formation region ; and a power supply (E1) connected to the logic circuit in the logic circuit formation region ; the high-voltage semiconductor device being characterized by further comprising: a shield layer which is formed on a first insulating layer formed on a surface of the opening region and which is connected to a negative electrode side of said power supply (E1), wherein the conductive path is formed on the shield layer through a second insulating layer so as to cross over the opening region . an n-type well region which is formed on a p-type semiconductor substrate and includes a logic circuit formation region and a withstand voltage region surrounding the logic circuit formation region ; a p-type well region which is formed on the semiconductor substrate so as to surround the withstand voltage region; a transistor which includes an n-type drain region selectively formed in a surface layer of the n-type well region between the withstand voltage region and the logic circuit formation region and having a higher concentration of impurities than the withstand voltage region, and an n-type source region selectively formed in the surface layer of the n-type well region , wherein the portion of the withstand voltage region situated between the drain region and the source region is a drift region of the transistor, and a portion of the p-type well region is a base region of the transistor; an opening region which is provided locally in the n-type well region between the drain region and the logic circuit formation region so as to prevent the n-type well region from lying all over the opening region in a depth direction; a conductive path which electrically connects the drain region with a logic circuit in the logic circuit formation region ; and a power supply (E1) connected to the logic circuit in the logic circuit formation region ; the high-voltage semiconductor device being characterized by further comprising: a shield layer which is formed on a first insulating layer formed on a surface of the opening region and which is connected to a negative electrode side of said power supply (E1), wherein the conductive path is formed on the shield layer through a second insulating layer so as to cross over the opening region . <EOS>