A display device comprising: a first pixel region (PA1) and a second pixel region (PA2) having different widths along a horizontal direction; first pixels (PXL1) in the first pixel region (PA1), each first pixel (PXL1) including a first transistor (T1; T3); and second pixels (PXL2) in the second pixel region (PA2), each second pixel (PXL2) including a second transistor (T1'; T3') performing a same function as the first transistor (T1), wherein the first pixel region (PA1) has a larger width than the second pixel region (PA2), the number of first and second pixels (PXL1, PXL2) in the horizontal direction being arranged to correspond to the respective width of the first and second pixel regions (PA1, PA2) such that an RC load value of a scan line (S1) extended in the horizontal direction in the first pixel region (PA1) is greater than an RC load value of a scan line (S2) extended in the horizontal direction in the second pixel region (PA2), and wherein at least one of a channel width (W) and a channel length (L) of the first and second transistors (T1, T1'; T3, T3') is different from one another, wherein either: the first transistor (T1) and the second transistor (T1') are driving transistors, and a W/L of the first transistor (T1) is smaller than a W/L of the second transistor (T1'); or the first transistor (T3) and the second transistor (T3') are control transistors for diode-connecting driving transistors (T1, T1'), and a mounting area of the first transistor (T3) is larger than a mounting area of the second transistor (T3') so that the parasitic capacitance of the first transistor (Cp) is larger than the parasitic capacitance of the second transistor (Cp'). a first pixel region (PA1) and a second pixel region (PA2) having different widths along a horizontal direction; first pixels (PXL1) in the first pixel region (PA1), each first pixel (PXL1) including a first transistor (T1; T3); and second pixels (PXL2) in the second pixel region (PA2), each second pixel (PXL2) including a second transistor (T1'; T3') performing a same function as the first transistor (T1), wherein the first pixel region (PA1) has a larger width than the second pixel region (PA2), the number of first and second pixels (PXL1, PXL2) in the horizontal direction being arranged to correspond to the respective width of the first and second pixel regions (PA1, PA2) such that an RC load value of a scan line (S1) extended in the horizontal direction in the first pixel region (PA1) is greater than an RC load value of a scan line (S2) extended in the horizontal direction in the second pixel region (PA2), and wherein at least one of a channel width (W) and a channel length (L) of the first and second transistors (T1, T1'; T3, T3') is different from one another, the first transistor (T1) and the second transistor (T1') are driving transistors, and a W/L of the first transistor (T1) is smaller than a W/L of the second transistor (T1'); or the first transistor (T3) and the second transistor (T3') are control transistors for diode-connecting driving transistors (T1, T1'), and a mounting area of the first transistor (T3) is larger than a mounting area of the second transistor (T3') so that the parasitic capacitance of the first transistor (Cp) is larger than the parasitic capacitance of the second transistor (Cp'). <EOS>