A 3D ferroelectric memory comprising: a substrate; first, second, and third word lines; first, second, and third layers, wherein the first layer, the second layer, and the third layer provide source lines coupled to a common source line; wherein the first layer includes a metal, the second layer includes the metal, and the third layer includes the metal; and wherein the first layer is between the substrate and the first word line, the second layer is between the first and second word lines, and the third layer is between the second and third word lines; first, second, and third portions of a material, wherein the material includes a ferroelectric material and wherein the first portion of the material is between the first word line and the first layer, the second portion of the material is between the second word line and the second layer, and the third portion of the material is between the third word line and the third layer; wherein the material includes oxygen and at least one of hafnium, silicon, yttrium, zirconium, barium, titanium, lead, or combinations thereof; a monolithic semiconductor layer on the first, second, and third portions of the material; a bit line having a long axis and a short axis; wherein the system comprises a NOR logic gate, wherein: the NOR logic gate includes the first, second, and third portions of the material; and the NOR logic gate includes the semiconductor layer; wherein a first plane, parallel to the short axis, intersects the first layer, the semiconductor layer, and the bit line; a second plane, parallel to the short axis, intersects the second layer, the semiconductor layer, and the bit line; and a third plane, parallel to the short axis, intersects the third layer, the semiconductor layer, and the bit line; and wherein the system further comprises: a first axis that is parallel to the long axis, the first axis intersecting the first, second, and third word lines and the first, second, and third portions of the material; a second axis that is parallel to the long axis, the second axis intersecting the first, second, and third layers; wherein the first axis does not intersect any of the first, second, or third layers;and wherein the second axis intersects the first, second, and third word lines and the first, second, and third portions of the material. a substrate; first, second, and third word lines; first, second, and third layers, wherein the first layer, the second layer, and the third layer provide source lines coupled to a common source line; wherein the first layer includes a metal, the second layer includes the metal, and the third layer includes the metal; and wherein the first layer is between the substrate and the first word line, the second layer is between the first and second word lines, and the third layer is between the second and third word lines; first, second, and third portions of a material, wherein the material includes a ferroelectric material and wherein the first portion of the material is between the first word line and the first layer, the second portion of the material is between the second word line and the second layer, and the third portion of the material is between the third word line and the third layer; wherein the material includes oxygen and at least one of hafnium, silicon, yttrium, zirconium, barium, titanium, lead, or combinations thereof; a monolithic semiconductor layer on the first, second, and third portions of the material; a bit line having a long axis and a short axis; wherein the system comprises a NOR logic gate, wherein: the NOR logic gate includes the first, second, and third portions of the material; and the NOR logic gate includes the semiconductor layer; the NOR logic gate includes the first, second, and third portions of the material; and the NOR logic gate includes the semiconductor layer; wherein a first plane, parallel to the short axis, intersects the first layer, the semiconductor layer, and the bit line; a second plane, parallel to the short axis, intersects the second layer, the semiconductor layer, and the bit line; and a third plane, parallel to the short axis, intersects the third layer, the semiconductor layer, and the bit line; and wherein the system further comprises: a first axis that is parallel to the long axis, the first axis intersecting the first, second, and third word lines and the first, second, and third portions of the material; a second axis that is parallel to the long axis, the second axis intersecting the first, second, and third layers; wherein the first axis does not intersect any of the first, second, or third layers;and wherein the second axis intersects the first, second, and third word lines and the first, second, and third portions of the material. a first axis that is parallel to the long axis, the first axis intersecting the first, second, and third word lines and the first, second, and third portions of the material; a second axis that is parallel to the long axis, the second axis intersecting the first, second, and third layers; wherein the first axis does not intersect any of the first, second, or third layers;and wherein the second axis intersects the first, second, and third word lines and the first, second, and third portions of the material.