A differential Colpitts oscillator circuit comprising: a first transistor pair (M1, M3) having a first tap point between a source of one transistor and a drain of the other transistor; a first power supply connected to a first transistor of the first transistor pair (M1, M3); a first inductor (L a) connected in a first line between a gate (aa) of the first transistor of the first transistor pair (M1, M3) and a connecting point; a second transistor pair (M2, M4) having a second tap point between a source of one transistor and a drain of the other transistor; a second power supply connected to a transistor of the second transistor pair (M2, M4); a second inductor (L b) connected in a second line between a gate (bb) of the first transistor of the second transistor pair (M2, M4) and the connecting point; a first variable capacitor (C2') connected in a third line between the first and second tap points (250, 260); and a resistor connected to a second transistor of the first transistor pair (M1, M3) and to a second transistor of the second transistor pair (M2, M4), the resistor also being connected to a ground point; characterized in that the differential Colpitts oscillator circuit comprises a capacitive voltage divider connected between the third line and the line between a gate (aa) of the first transistor of the first transistor pair (M1 M3) and a gate (bb) of the first transistor of the second transistor pair (M2, M4); and in that the capacitive voltage divider comprises: at least a first pair of capacitors (C1 a, C3 a) connected between the gate (aa) of the first transistor in the first transistor pair (M1, M3) in the first line and the first tap point in the third line; at least a second pair of capacitors (C1 b, C3 b) connected between the gate (bb) of the first transistor of the second transistor pair (M2, M4) in the second line and the second tap point in the third line; and a second variable capacitor (Ctune') connected between the first and second pairs of capacitors (C1 a, C3 a, C1 b, C3 b) at respective intermediate points (310, 320), the first variable capacitor (C2') forming part of the capacitive voltage divider. a first transistor pair (M1, M3) having a first tap point between a source of one transistor and a drain of the other transistor; a first power supply connected to a first transistor of the first transistor pair (M1, M3); a first inductor (L a) connected in a first line between a gate (aa) of the first transistor of the first transistor pair (M1, M3) and a connecting point; a second transistor pair (M2, M4) having a second tap point between a source of one transistor and a drain of the other transistor; a second power supply connected to a transistor of the second transistor pair (M2, M4); a second inductor (L b) connected in a second line between a gate (bb) of the first transistor of the second transistor pair (M2, M4) and the connecting point; a first variable capacitor (C2') connected in a third line between the first and second tap points (250, 260); and a resistor connected to a second transistor of the first transistor pair (M1, M3) and to a second transistor of the second transistor pair (M2, M4), the resistor also being connected to a ground point; characterized in that the differential Colpitts oscillator circuit comprises a capacitive voltage divider connected between the third line and the line between a gate (aa) of the first transistor of the first transistor pair (M1 M3) and a gate (bb) of the first transistor of the second transistor pair (M2, M4); and in that the capacitive voltage divider comprises: at least a first pair of capacitors (C1 a, C3 a) connected between the gate (aa) of the first transistor in the first transistor pair (M1, M3) in the first line and the first tap point in the third line; at least a second pair of capacitors (C1 b, C3 b) connected between the gate (bb) of the first transistor of the second transistor pair (M2, M4) in the second line and the second tap point in the third line; and a second variable capacitor (Ctune') connected between the first and second pairs of capacitors (C1 a, C3 a, C1 b, C3 b) at respective intermediate points (310, 320), the first variable capacitor (C2') forming part of the capacitive voltage divider. at least a first pair of capacitors (C1 a, C3 a) connected between the gate (aa) of the first transistor in the first transistor pair (M1, M3) in the first line and the first tap point in the third line; at least a second pair of capacitors (C1 b, C3 b) connected between the gate (bb) of the first transistor of the second transistor pair (M2, M4) in the second line and the second tap point in the third line; and a second variable capacitor (Ctune') connected between the first and second pairs of capacitors (C1 a, C3 a, C1 b, C3 b) at respective intermediate points (310, 320), the first variable capacitor (C2') forming part of the capacitive voltage divider.