A method, comprising: discharging during a first time period a residual charge from a middle electrode between a ferroelectric capacitor of a ferroelectric memory cell (105, 415, 420, 1410, 1520) and a selection component that is coupled to an access line (110, 1420) of the ferroelectric memory cell (105, 415, 420, 1410, 1520), wherein a supply voltage for the ferroelectric memory cell is a first supply voltage for a group of memory cells that include the ferroelectric memory cell (105, 415, 420, 1410, 1520), charging after the first time period a capacitor that is in electronic communication with a digit line (115, 1440) of the ferroelectric memory cell (105, 415, 420, 1410, 1520), wherein charging the capacitor comprises activating during a second time period a switching component of a plurality of switching components (530, 540) that couples the capacitor to the ferroelectric memory cell (105, 415, 420, 1410, 1520) via the digit line (115, 1440), and wherein the second time period is after the first time period; and determining a logic state of the ferroelectric memory cell (105, 415, 420, 1410, 1520) based at least in part on a charge of the capacitor after the first time period, wherein determining the logic state of the ferroelectric memory cell (105, 415, 420, 1410, 1520) comprises activating during a third time period another switching component of the plurality of switching components (530, 540) that couples the capacitor to a latch (505, 1445), wherein the third time period is after the second time period and the latch (505, 1445) is coupled to a second supply voltage that is lower than the first supply voltage. discharging during a first time period a residual charge from a middle electrode between a ferroelectric capacitor of a ferroelectric memory cell (105, 415, 420, 1410, 1520) and a selection component that is coupled to an access line (110, 1420) of the ferroelectric memory cell (105, 415, 420, 1410, 1520), wherein a supply voltage for the ferroelectric memory cell is a first supply voltage for a group of memory cells that include the ferroelectric memory cell (105, 415, 420, 1410, 1520), charging after the first time period a capacitor that is in electronic communication with a digit line (115, 1440) of the ferroelectric memory cell (105, 415, 420, 1410, 1520), wherein charging the capacitor comprises activating during a second time period a switching component of a plurality of switching components (530, 540) that couples the capacitor to the ferroelectric memory cell (105, 415, 420, 1410, 1520) via the digit line (115, 1440), and wherein the second time period is after the first time period; and determining a logic state of the ferroelectric memory cell (105, 415, 420, 1410, 1520) based at least in part on a charge of the capacitor after the first time period, wherein determining the logic state of the ferroelectric memory cell (105, 415, 420, 1410, 1520) comprises activating during a third time period another switching component of the plurality of switching components (530, 540) that couples the capacitor to a latch (505, 1445), wherein the third time period is after the second time period and the latch (505, 1445) is coupled to a second supply voltage that is lower than the first supply voltage.