A preamplifier, comprising: a transistor having a gate configured to receive a bias voltage (Vn), a source and a drain, the source being coupled to an input node and the drain being coupled to an output node; a load impedance coupled between the drain of the transistor and a first supply voltage node; and a bleeder impedance coupled between the source of the transistor and a second supply voltage node, the preamplifier further comprising a bias voltage source configured to provide the bias voltage, wherein the bias voltage source comprises: a second transistor having a gate, a source and a drain, the source being coupled to a first reference voltage and the drain being coupled to an output voltage node; a second load impedance coupled between the drain of the second transistor and the first supply voltage node; a second bleeder impedance coupled between the source of the second transistor, and the second supply voltage node; and a differential amplifier having a first input node coupled to the output voltage node, a second input node coupled to receive a second reference voltage, and an output node coupled to the gate of the second transistor, the differential amplifier being configured to generate the bias voltage with a magnitude corresponding to a difference between voltages at the first and second input nodes. a transistor having a gate configured to receive a bias voltage (Vn), a source and a drain, the source being coupled to an input node and the drain being coupled to an output node; a load impedance coupled between the drain of the transistor and a first supply voltage node; and a bleeder impedance coupled between the source of the transistor and a second supply voltage node, the preamplifier further comprising a bias voltage source configured to provide the bias voltage, wherein the bias voltage source comprises: a second transistor having a gate, a source and a drain, the source being coupled to a first reference voltage and the drain being coupled to an output voltage node; a second load impedance coupled between the drain of the second transistor and the first supply voltage node; a second bleeder impedance coupled between the source of the second transistor, and the second supply voltage node; and a differential amplifier having a first input node coupled to the output voltage node, a second input node coupled to receive a second reference voltage, and an output node coupled to the gate of the second transistor, the differential amplifier being configured to generate the bias voltage with a magnitude corresponding to a difference between voltages at the first and second input nodes. a second transistor having a gate, a source and a drain, the source being coupled to a first reference voltage and the drain being coupled to an output voltage node; a second load impedance coupled between the drain of the second transistor and the first supply voltage node; a second bleeder impedance coupled between the source of the second transistor, and the second supply voltage node; and a differential amplifier having a first input node coupled to the output voltage node, a second input node coupled to receive a second reference voltage, and an output node coupled to the gate of the second transistor, the differential amplifier being configured to generate the bias voltage with a magnitude corresponding to a difference between voltages at the first and second input nodes.