A method of gain calibration in a successive approximation register analog-to-digital converter, SAR ADC, (200; 700) configured to convert an analog input signal (V IN) into a digital signal (C OUT) formed by m most significant bits (B MSB) and n least significant bits (B LSB), the method comprising the steps of: a) determining, by a first stage ADC (210; 710), the number of most significant bits (B MSB) of the digital signal (C OUT) corresponding to the analog input signal (V IN); b) amplifying, by a gain module (230; 730) having a gain factor, a residue signal (V RES) output from the first stage ADC (210; 710), wherein a most significant bit of the n least significant bits (B LSB) is equal to a least significant bit of the m most significant bits (B MSB) multiplied with the gain factor; c) determining, by a second stage ADC (220; 720), the least significant bits (B LSB) of the digital signal (C OUT) corresponding to the analog input signal (V IN); d) detecting if a binary code determined from the analog input signal (V IN) matches a binary trigger code; e) retrieving, from a memory module (242; 742), a pre-set binary calibration code associated with said binary trigger code that yields the same digital signal (C OUT) of said binary trigger code if said calibration process is triggered; f) using said binary code to determine a calibration residue signal (V* RES) in the first stage ADC (210; 710) by calculating a difference between the analog input signal (V IN) and an analog signal (V* MSB) representing the first m bits of said binary calibration code; g) temporarily storing, by the gain module (230; 730), the calibration residue signal (V* RES) until all least significant bits (B LSB) have been determined by the second stage ADC (220; 720); h) amplifying, after step g), by the gain module (230; 730), the calibration residue signal (V* RES) to form an amplified calibration residue signal (V* AMP); i) using said binary calibration code to determine a calibration bit (B* LSB) in the second stage ADC (220; 720) by comparing the amplified calibration residue signal (V* AMP) to a further analog signal (V* LSB) representing the last n bits of said binary calibration code; j) determining whether a least significant bit of the digital signal (C OUT) and the calibration bit (B* LSB) are different to one another which indicates a presence of gain error in the gain module (230; 730); and k) calibrating gain error in the gain module (230; 730) if the presence of gain error is determined by adjusting at least one of a plurality of tunable capacitors (224a, 224b,..., 224n; 724a, 724b,..., 724n) in the second stage ADC (220; 720). a) determining, by a first stage ADC (210; 710), the number of most significant bits (B MSB) of the digital signal (C OUT) corresponding to the analog input signal (V IN); b) amplifying, by a gain module (230; 730) having a gain factor, a residue signal (V RES) output from the first stage ADC (210; 710), wherein a most significant bit of the n least significant bits (B LSB) is equal to a least significant bit of the m most significant bits (B MSB) multiplied with the gain factor; c) determining, by a second stage ADC (220; 720), the least significant bits (B LSB) of the digital signal (C OUT) corresponding to the analog input signal (V IN); d) detecting if a binary code determined from the analog input signal (V IN) matches a binary trigger code; e) retrieving, from a memory module (242; 742), a pre-set binary calibration code associated with said binary trigger code that yields the same digital signal (C OUT) of said binary trigger code if said calibration process is triggered; f) using said binary code to determine a calibration residue signal (V* RES) in the first stage ADC (210; 710) by calculating a difference between the analog input signal (V IN) and an analog signal (V* MSB) representing the first m bits of said binary calibration code; g) temporarily storing, by the gain module (230; 730), the calibration residue signal (V* RES) until all least significant bits (B LSB) have been determined by the second stage ADC (220; 720); h) amplifying, after step g), by the gain module (230; 730), the calibration residue signal (V* RES) to form an amplified calibration residue signal (V* AMP); i) using said binary calibration code to determine a calibration bit (B* LSB) in the second stage ADC (220; 720) by comparing the amplified calibration residue signal (V* AMP) to a further analog signal (V* LSB) representing the last n bits of said binary calibration code; j) determining whether a least significant bit of the digital signal (C OUT) and the calibration bit (B* LSB) are different to one another which indicates a presence of gain error in the gain module (230; 730); and k) calibrating gain error in the gain module (230; 730) if the presence of gain error is determined by adjusting at least one of a plurality of tunable capacitors (224a, 224b,..., 224n; 724a, 724b,..., 724n) in the second stage ADC (220; 720).