A system for accessing a plurality of instruments embedded in a semiconductor device, the system comprising: - a hardware interface configured to access a control mechanism for controlling the plurality of instruments; - a test controller for testing the semiconductor device or generating test patterns for the semiconductor device, wherein the test controller comprises an instrument connectivity language and procedural description language configuration for operating the plurality of instruments, the test controller being configured to perform the steps of: o testing at least one functionality of each of the plurality of instruments by accessing the control mechanism for controlling the plurality of instruments through the hardware interface, thereby receiving a fault status of each of the plurality of instruments; characterized in that the test controller is configured to perform: o based on the fault status of the plurality of instruments, configuring a test block in the semiconductor device such that valid test patterns for the semiconductor device can be generated without updating the instrument connectivity language and procedural description language configuration, and in that: the instruments are reconfigurable scan networks and the testing is scan testing, the test block comprises a repair component configured to exclude specific faulty scan registers from a scan-path, an active scan-path is configured such that only instruments without faulty scan chains are included in the testing, and the test controller is configurable to send a test command to the test block through the hardware interface and/or wherein the test controller is configurable to send a repair command to the test block through the hardware interface. - a hardware interface configured to access a control mechanism for controlling the plurality of instruments; - a test controller for testing the semiconductor device or generating test patterns for the semiconductor device, wherein the test controller comprises an instrument connectivity language and procedural description language configuration for operating the plurality of instruments, the test controller being configured to perform the steps of: o testing at least one functionality of each of the plurality of instruments by accessing the control mechanism for controlling the plurality of instruments through the hardware interface, thereby receiving a fault status of each of the plurality of instruments; characterized in that the test controller is configured to perform: o based on the fault status of the plurality of instruments, configuring a test block in the semiconductor device such that valid test patterns for the semiconductor device can be generated without updating the instrument connectivity language and procedural description language configuration, and in that: the instruments are reconfigurable scan networks and the testing is scan testing, the test block comprises a repair component configured to exclude specific faulty scan registers from a scan-path, an active scan-path is configured such that only instruments without faulty scan chains are included in the testing, and the test controller is configurable to send a test command to the test block through the hardware interface and/or wherein the test controller is configurable to send a repair command to the test block through the hardware interface. o testing at least one functionality of each of the plurality of instruments by accessing the control mechanism for controlling the plurality of instruments through the hardware interface, thereby receiving a fault status of each of the plurality of instruments; characterized in that the test controller is configured to perform: o based on the fault status of the plurality of instruments, configuring a test block in the semiconductor device such that valid test patterns for the semiconductor device can be generated without updating the instrument connectivity language and procedural description language configuration, o based on the fault status of the plurality of instruments, configuring a test block in the semiconductor device such that valid test patterns for the semiconductor device can be generated without updating the instrument connectivity language and procedural description language configuration, and in that: the instruments are reconfigurable scan networks and the testing is scan testing, the test block comprises a repair component configured to exclude specific faulty scan registers from a scan-path, an active scan-path is configured such that only instruments without faulty scan chains are included in the testing, and the test controller is configurable to send a test command to the test block through the hardware interface and/or wherein the test controller is configurable to send a repair command to the test block through the hardware interface. the instruments are reconfigurable scan networks and the testing is scan testing, the test block comprises a repair component configured to exclude specific faulty scan registers from a scan-path, an active scan-path is configured such that only instruments without faulty scan chains are included in the testing, and the test controller is configurable to send a test command to the test block through the hardware interface and/or wherein the test controller is configurable to send a repair command to the test block through the hardware interface.