A communication jack for use in a communication network, said jack comprising: a plurality of current-carrying paths through the communication jack, the current-carrying paths are traces that allow a DC current to flow between two points, said current-carrying paths comprising at least first and second signal pairs of conductors, each of said signal pairs comprising a first and a second conductive pathway; compensation circuitry adapted to decrease the overall crosstalk when said communication jack is connected to a plug, said compensation circuitry comprising: a first pad capacitor connected between the second conductive pathway of the first signal pair and the first conductive pathway of the second signal pair; a second pad capacitor connected between the first conductive pathway of the first signal pair and the second conductive pathway of the second signal pair; a third pad capacitor connected between the first conductive pathway of the first signal pair and the first conductive pathway of the second signal pair, with first and second inductive stubs (L3, L4) further being positioned between said first conductive pathway of said first signal pair and said first conductive pathway of said second signal pair on opposing sides of said third pad capacitor; and a fourth pad capacitor connected between the second conductive pathway of the first signal pair and the second conductive pathway of the second signal pair, characterised in that third and fourth inductive stubs (L5, L6) further being positioned between said second conductive pathway of said first signal pair and said second conductive pathway of said second signal pair; wherein the inductive stubs (L3, L4, L5, L6) are traces made specific lengths to take advantage of their self-inductance, and wherein the inductive stubs are off of the current-carrying paths. a plurality of current-carrying paths through the communication jack, the current-carrying paths are traces that allow a DC current to flow between two points, said current-carrying paths comprising at least first and second signal pairs of conductors, each of said signal pairs comprising a first and a second conductive pathway; compensation circuitry adapted to decrease the overall crosstalk when said communication jack is connected to a plug, said compensation circuitry comprising: a first pad capacitor connected between the second conductive pathway of the first signal pair and the first conductive pathway of the second signal pair; a second pad capacitor connected between the first conductive pathway of the first signal pair and the second conductive pathway of the second signal pair; a third pad capacitor connected between the first conductive pathway of the first signal pair and the first conductive pathway of the second signal pair, with first and second inductive stubs (L3, L4) further being positioned between said first conductive pathway of said first signal pair and said first conductive pathway of said second signal pair on opposing sides of said third pad capacitor; and a fourth pad capacitor connected between the second conductive pathway of the first signal pair and the second conductive pathway of the second signal pair, characterised in that third and fourth inductive stubs (L5, L6) further being positioned between said second conductive pathway of said first signal pair and said second conductive pathway of said second signal pair; a first pad capacitor connected between the second conductive pathway of the first signal pair and the first conductive pathway of the second signal pair; a second pad capacitor connected between the first conductive pathway of the first signal pair and the second conductive pathway of the second signal pair; a third pad capacitor connected between the first conductive pathway of the first signal pair and the first conductive pathway of the second signal pair, with first and second inductive stubs (L3, L4) further being positioned between said first conductive pathway of said first signal pair and said first conductive pathway of said second signal pair on opposing sides of said third pad capacitor; and a fourth pad capacitor connected between the second conductive pathway of the first signal pair and the second conductive pathway of the second signal pair, characterised in that third and fourth inductive stubs (L5, L6) further being positioned between said second conductive pathway of said first signal pair and said second conductive pathway of said second signal pair;