A memory, comprising: a plurality of columns, each column including: a bit line; a complement bit line; a first read multiplexer transistor coupled to the bit line and having a read terminal; a second read multiplexer transistor coupled to the complement bit line and having a complement read terminal; a write driver having a write data output terminal and a complement write data output terminal; a scan multiplexer having a first pair of input terminals coupled to the write data output terminal and the complement write data output terminal and having a second pair of input terminals coupled to the read terminal and the complement read terminal; and a sense amplifier coupled to an output from the scan multiplexer, the memory further configured in response to a column redundancy signal for a column of the plurality of the columns being false during a scan mode of operation to: responsive to a triggering edge of a scan clock signal, route a shift-in signal through a write column redundancy multiplexer to the write driver; process the shift-in signal through the write driver to form a pair of write driver output signals; route the pair of write driver output signals through the scan multiplexer to the sense amplifier; sense the pair of write driver output signals in the sense amplifier to form a sensed version of the shift-in signal; and route the sensed version of the shift-in signal through a read column redundancy multiplexer to a data output latch. a bit line; a complement bit line; a first read multiplexer transistor coupled to the bit line and having a read terminal; a second read multiplexer transistor coupled to the complement bit line and having a complement read terminal; a write driver having a write data output terminal and a complement write data output terminal; a scan multiplexer having a first pair of input terminals coupled to the write data output terminal and the complement write data output terminal and having a second pair of input terminals coupled to the read terminal and the complement read terminal; and a sense amplifier coupled to an output from the scan multiplexer, the memory further configured in response to a column redundancy signal for a column of the plurality of the columns being false during a scan mode of operation to: responsive to a triggering edge of a scan clock signal, route a shift-in signal through a write column redundancy multiplexer to the write driver; process the shift-in signal through the write driver to form a pair of write driver output signals; route the pair of write driver output signals through the scan multiplexer to the sense amplifier; sense the pair of write driver output signals in the sense amplifier to form a sensed version of the shift-in signal; and route the sensed version of the shift-in signal through a read column redundancy multiplexer to a data output latch. responsive to a triggering edge of a scan clock signal, route a shift-in signal through a write column redundancy multiplexer to the write driver; process the shift-in signal through the write driver to form a pair of write driver output signals; route the pair of write driver output signals through the scan multiplexer to the sense amplifier; sense the pair of write driver output signals in the sense amplifier to form a sensed version of the shift-in signal; and route the sensed version of the shift-in signal through a read column redundancy multiplexer to a data output latch.