A driver circuit, comprising: a plurality of field effect transistors (122, 132, 150, 190) of a same conductivity type coupled in a cascode arrangement with a current flowing through each of the plurality of field effect transistors being the same current; and a first passive biasing cell coupled to a gate terminal of a first field effect transistor of the plurality of field effect transistors, a second passive biasing cell coupled to a gate terminal of a second field effect transistor of the plurality of field effect transistors, wherein the first and second field effect transistors (150, 190) are configured as common gate stages and a source terminal of the second field effect transistor is directly connected to a drain terminal of the first field effect transistor, wherein each of the first and second passive biasing cells includes (a) a respective biasing circuit coupled to a circuit node (144, 184) to provide a respective biasing signal to the gate terminal of the respective field effect transistor, (b) a first capacitor (146, 186) coupled between the circuit node and a power supply conductor, (c) a first resistor (152, 192) directly connected between the gate terminal and a drain terminal of the respective field effect transistor, and (d) a second resistor (154, 194) directly connected between the gate terminal and a source terminal of the respective field effect transistor. a plurality of field effect transistors (122, 132, 150, 190) of a same conductivity type coupled in a cascode arrangement with a current flowing through each of the plurality of field effect transistors being the same current; and a first passive biasing cell coupled to a gate terminal of a first field effect transistor of the plurality of field effect transistors, a second passive biasing cell coupled to a gate terminal of a second field effect transistor of the plurality of field effect transistors, wherein the first and second field effect transistors (150, 190) are configured as common gate stages and a source terminal of the second field effect transistor is directly connected to a drain terminal of the first field effect transistor, wherein each of the first and second passive biasing cells includes (a) a respective biasing circuit coupled to a circuit node (144, 184) to provide a respective biasing signal to the gate terminal of the respective field effect transistor, (b) a first capacitor (146, 186) coupled between the circuit node and a power supply conductor, (c) a first resistor (152, 192) directly connected between the gate terminal and a drain terminal of the respective field effect transistor, and (d) a second resistor (154, 194) directly connected between the gate terminal and a source terminal of the respective field effect transistor. (a) a respective biasing circuit coupled to a circuit node (144, 184) to provide a respective biasing signal to the gate terminal of the respective field effect transistor, (b) a first capacitor (146, 186) coupled between the circuit node and a power supply conductor, (c) a first resistor (152, 192) directly connected between the gate terminal and a drain terminal of the respective field effect transistor, and (d) a second resistor (154, 194) directly connected between the gate terminal and a source terminal of the respective field effect transistor.