A lateral thyristor device, comprising: a semiconductor layer which is positioned atop a layer of insulator, and is completely isolated by trenches on all sides thereof; a heavily-doped n+ emitter region at one end of a length of said semiconductor layer, and a lightly doped p-type base region adjacent said n+ emitter region, and a lightly doped n-type base region adjacent to said p-type base region but not to said n+ emitter region, the n+ emitter region, the p-type base region, and the n-type base region forming an NPN bipolar transistor, and a heavily doped p+ emitter region which abuts said lightly doped n-type base region but not said lightly doped p-type base region nor said heavily doped n+ emitter; the p+ emitter region, the n-type base region, and the p-type base region forming a PNP transistor; a plurality of embedded gate electrodes spaced along the boundary between said p-type base region and said n-type emitter region, each said gate electrode being capacitively coupled to a portion of said p-type base region which is nearest said n+ emitter region so as to invert a portion of the p-type base region when a sufficiently high positive voltage is applied to the gate electrodes, wherein the p-type base region extends beyond the gate electrodes toward the p+ emitter region such that there is no channel created between the n+ emitter region and the n-type base region when the sufficiently high positive voltage is applied to the gate electrodes; all of said gate electrodes which are adjacent said n+ emitter region being electrically connected together; wherein, when said gate electrodes are sufficiently positively biased and the gate electrodes invert an adjacent portion of said p-type base region, a population of electrons, adjacent to said gate electrodes, increases an emitter size of said NPN transistor and reduces its base size to increase its beta such that a product of the betas of the NPN transistor and the PNP transistor is greater than one to thereby sustain latchup once conduction has been initiated; and wherein the combination of said n+ emitter and said p-type base, and the combination of said p+ emitter region and said n-type base region, are not jointly able to sustain latching if said gate electrodes have not inverted adjacent portions of said p-type base region due to the product of the betas of the NPN transistor and the PNP transistor being less than one. a semiconductor layer which is positioned atop a layer of insulator, and is completely isolated by trenches on all sides thereof; a heavily-doped n+ emitter region at one end of a length of said semiconductor layer, and a lightly doped p-type base region adjacent said n+ emitter region, and a lightly doped n-type base region adjacent to said p-type base region but not to said n+ emitter region, the n+ emitter region, the p-type base region, and the n-type base region forming an NPN bipolar transistor, and a heavily doped p+ emitter region which abuts said lightly doped n-type base region but not said lightly doped p-type base region nor said heavily doped n+ emitter; the p+ emitter region, the n-type base region, and the p-type base region forming a PNP transistor; a plurality of embedded gate electrodes spaced along the boundary between said p-type base region and said n-type emitter region, each said gate electrode being capacitively coupled to a portion of said p-type base region which is nearest said n+ emitter region so as to invert a portion of the p-type base region when a sufficiently high positive voltage is applied to the gate electrodes, wherein the p-type base region extends beyond the gate electrodes toward the p+ emitter region such that there is no channel created between the n+ emitter region and the n-type base region when the sufficiently high positive voltage is applied to the gate electrodes; all of said gate electrodes which are adjacent said n+ emitter region being electrically connected together; wherein, when said gate electrodes are sufficiently positively biased and the gate electrodes invert an adjacent portion of said p-type base region, a population of electrons, adjacent to said gate electrodes, increases an emitter size of said NPN transistor and reduces its base size to increase its beta such that a product of the betas of the NPN transistor and the PNP transistor is greater than one to thereby sustain latchup once conduction has been initiated; and wherein the combination of said n+ emitter and said p-type base, and the combination of said p+ emitter region and said n-type base region, are not jointly able to sustain latching if said gate electrodes have not inverted adjacent portions of said p-type base region due to the product of the betas of the NPN transistor and the PNP transistor being less than one.