An image sensor system, comprising: a matrix having rows and columns of photo-sensitive pixels, wherein pixels that are arranged in the same column are configured to output an output signal onto a column bus for that column if such pixel is selected for read out; a conversion unit for converting a pixel signal that is based on one or more output signals for a given pixel into a respective digital number, said conversion unit comprising a global ramp unit configured for generating a ramp signal, the conversion unit further comprising, for each column of pixels: a comparator for comparing the relevant pixel signal to the ramp signal; a binary counter configured to increase a binary count value in dependence of a clock signal and a result of said comparing; a controller for resetting each binary counter to an initial value at the start of a conversion cycle; a binary count value collecting unit for collecting the binary count values from each binary counter; characterized in that the conversion unit further comprises, for each column of pixels, a load that comprises a toggling unit configured for toggling a predefined number of bits in response to the clock signal; wherein the load and binary counter are operable in a counting mode, in which mode the binary counter increases said binary count value in dependence of the clock signal and the load does not toggle, and in a non-counting mode, in which mode the binary counter has stopped counting and the load toggles said predefined number of bits in dependence of the clock signal; wherein said predefined number corresponds to the average number of bits that toggle in the binary counter per counting step while the binary counter is in the counting mode. a matrix having rows and columns of photo-sensitive pixels, wherein pixels that are arranged in the same column are configured to output an output signal onto a column bus for that column if such pixel is selected for read out; a conversion unit for converting a pixel signal that is based on one or more output signals for a given pixel into a respective digital number, said conversion unit comprising a global ramp unit configured for generating a ramp signal, the conversion unit further comprising, for each column of pixels: a comparator for comparing the relevant pixel signal to the ramp signal; a binary counter configured to increase a binary count value in dependence of a clock signal and a result of said comparing; a comparator for comparing the relevant pixel signal to the ramp signal; a binary counter configured to increase a binary count value in dependence of a clock signal and a result of said comparing; a controller for resetting each binary counter to an initial value at the start of a conversion cycle; a binary count value collecting unit for collecting the binary count values from each binary counter; characterized in that the conversion unit further comprises, for each column of pixels, a load that comprises a toggling unit configured for toggling a predefined number of bits in response to the clock signal; wherein the load and binary counter are operable in a counting mode, in which mode the binary counter increases said binary count value in dependence of the clock signal and the load does not toggle, and in a non-counting mode, in which mode the binary counter has stopped counting and the load toggles said predefined number of bits in dependence of the clock signal; wherein said predefined number corresponds to the average number of bits that toggle in the binary counter per counting step while the binary counter is in the counting mode.