A non-volatile memory, comprising: a first word line comb structure, the first word line comb structure includes a first word line segment and a second word line segment connected to the first word line segment; wherein a first adjustable resistance bit line structure, the first adjustable resistance bit line structure includes a first adjustable resistance local bit line and a first select gate, a first memory cell is arranged between and connected to the first adjustable resistance local bit line and the first word line segment, the first adjustable resistance local bit line is arranged between the first select gate and the first memory cell, the first adjustable resistance bit line structure includes a first dielectric layer arranged between the first select gate and the first adjustable resistance local bit line, the first adjustable resistance local bit line surrounding the first dielectric layer, the first dielectric layer surrounding the first select gate, a resistance of the first adjustable resistance local bit line is set based on a first voltage applied to the first select gate; and a second adjustable resistance bit line structure, the second adjustable resistance bit line structure includes a second adjustable resistance local bit line and a second select gate, a second memory cell is arranged between and connected to the second adjustable resistance local bit line and the second word line segment, the second adjustable resistance local bit line is arranged between the second select gate and the second memory cell, the second adjustable resistance bit line structure includes a second dielectric layer arranged between the second select gate and the second adjustable resistance local bit line, the second adjustable resistance local bit line surrounding the second dielectric layer, the second dielectric layer surrounding the second select gate, a resistance of the second adjustable resistance local bit line is set based on a second voltage applied to the second select gate, the non-volatile memory is configured to set the first adjustable resistance local bit line into a conducting state during a memory operation and set the second adjustable resistance local bit line into a non-conducting state during the memory operation. a first word line comb structure, the first word line comb structure includes a first word line segment and a second word line segment connected to the first word line segment; wherein a first adjustable resistance bit line structure, the first adjustable resistance bit line structure includes a first adjustable resistance local bit line and a first select gate, a first memory cell is arranged between and connected to the first adjustable resistance local bit line and the first word line segment, the first adjustable resistance local bit line is arranged between the first select gate and the first memory cell, the first adjustable resistance bit line structure includes a first dielectric layer arranged between the first select gate and the first adjustable resistance local bit line, the first adjustable resistance local bit line surrounding the first dielectric layer, the first dielectric layer surrounding the first select gate, a resistance of the first adjustable resistance local bit line is set based on a first voltage applied to the first select gate; and a second adjustable resistance bit line structure, the second adjustable resistance bit line structure includes a second adjustable resistance local bit line and a second select gate, a second memory cell is arranged between and connected to the second adjustable resistance local bit line and the second word line segment, the second adjustable resistance local bit line is arranged between the second select gate and the second memory cell, the second adjustable resistance bit line structure includes a second dielectric layer arranged between the second select gate and the second adjustable resistance local bit line, the second adjustable resistance local bit line surrounding the second dielectric layer, the second dielectric layer surrounding the second select gate, a resistance of the second adjustable resistance local bit line is set based on a second voltage applied to the second select gate, the non-volatile memory is configured to set the first adjustable resistance local bit line into a conducting state during a memory operation and set the second adjustable resistance local bit line into a non-conducting state during the memory operation.