A method for manufacturing a device comprising a power vertical double diffused metal-oxide-semiconductor field-effect transistor, VDMOS, in a VDMOS region, integrated with a junction field effect transistor, JFET, in a JFET region wherein the device comprises a drain, and a first conduction type region disposed on a front surface of the drain, while a part of the drain is located in the JFET region and the other part of the drain is located in the VDMOS region, and a part of the first conduction type region is located in the JFET region and the other part of the first conduction type region is located in the VDMOS region, the method comprising: providing a substrate of the first conduction type serving as said drain, wherein the first conduction type region is formed on the substrate; forming a second conduction type buried layer in the first conduction type region of the JFET region; while the first conduction type is opposite to the second conduction type; implanting ions of the second conduction type into the first conduction type region and forming a first well of the JFET region in the first conduction type region by driving-in; growing a field oxide layer and a gate oxide layer on a surface of the first conduction type region in turn, and forming a polysilicon layer on the surface of the first conduction type region; implanting the ions of the second conduction type into the first conduction type region and forming a second well of the JFET region and a second well of the VDMOS region, by driving-in; implanting ions of the first conduction type, to form a JFET source at the JFET region and form a VDMOS source at the VDMOS region; and forming a photoresist mask and etching contact holes while the photoresist mask is present, depositing a metal layer filling the contact holes, to form a metal electrode of the JFET source, a JFET metal gate and a metal contact of the VDMOS source respectively; wherein after the step of implanting the ions of the second conduction type into the first conduction type region and forming a second well of the JFET region and a second well of the VDMOS region, by driving-in, and prior to the step of implanting ions of the first conduction type, the method further comprises: forming an implanting barrier layer and implanting the ions of the second conduction type through the implanting barrier layer into the second well of the JFET region and into the second well of the VDMOS region to form unclamped inductive switching, UIS, regions, wherein the implanting energy of the UIS regions is greater than the implanting energy of the ions of the first conduction type. providing a substrate of the first conduction type serving as said drain, wherein the first conduction type region is formed on the substrate; forming a second conduction type buried layer in the first conduction type region of the JFET region; while the first conduction type is opposite to the second conduction type; implanting ions of the second conduction type into the first conduction type region and forming a first well of the JFET region in the first conduction type region by driving-in; growing a field oxide layer and a gate oxide layer on a surface of the first conduction type region in turn, and forming a polysilicon layer on the surface of the first conduction type region; implanting the ions of the second conduction type into the first conduction type region and forming a second well of the JFET region and a second well of the VDMOS region, by driving-in; implanting ions of the first conduction type, to form a JFET source at the JFET region and form a VDMOS source at the VDMOS region; and forming a photoresist mask and etching contact holes while the photoresist mask is present, depositing a metal layer filling the contact holes, to form a metal electrode of the JFET source, a JFET metal gate and a metal contact of the VDMOS source respectively; wherein after the step of implanting the ions of the second conduction type into the first conduction type region and forming a second well of the JFET region and a second well of the VDMOS region, by driving-in, and prior to the step of implanting ions of the first conduction type, the method further comprises: forming an implanting barrier layer and implanting the ions of the second conduction type through the implanting barrier layer into the second well of the JFET region and into the second well of the VDMOS region to form unclamped inductive switching, UIS, regions, wherein the implanting energy of the UIS regions is greater than the implanting energy of the ions of the first conduction type.