A plurality of memory circuits, each of which is connected to a respective one of a plurality of integrated circuits, ICs, each of the ICs being connected to at least one of the other ICs by inter-IC connections so that an IC exchanges memory circuit data with another IC via the inter-IC connections, each of the ICs including memory manager circuitry comprising: a logic block manager for maintaining a unique global identification, global ID, for each block of data contained in any portion of any of the memory circuits, the global ID including a node ID identifying the IC that is connected to the memory circuit containing that block and a logical block number for that block; a translator for maintaining a mapping between the logical block number of each block contained in the memory circuit connected to the IC that includes that translator, and a physical portion ID of a portion of that memory circuit that contains that block; and a driver for receiving the physical portion ID from the translator of the IC that includes that driver and accessing the portion of the memory connected to that IC that is identified by that physical portion ID, wherein at least one of the ICs includes circuitry for receiving a request from an external source for a block identified by the global ID of that requested block, and wherein the logic block manager of that IC includes circuitry for using the global ID of the requested block to determine the node ID and the logical block number of the requested block; if the circuitry for using determines that the node ID of the requested block is not the node ID of the IC that includes that circuitry for using, then the logic block manager circuitry of that IC employs circuitry for causing that IC to route data for the request to at least one other of the ICs; and each of the ICs, also referred to as the source IC, further includes: circuitry for maintaining a count of how many times each of the other ICs requests a respective block contained in the memory circuit that is connected to the source IC; and circuitry for transferring a block also referred to as the transferred block, for which the count for one of the other ICs, also referred to as the destination IC, exceeds a threshold value, from the memory circuit connected to the source IC to the memory circuit connected to the destination IC. a logic block manager for maintaining a unique global identification, global ID, for each block of data contained in any portion of any of the memory circuits, the global ID including a node ID identifying the IC that is connected to the memory circuit containing that block and a logical block number for that block; a translator for maintaining a mapping between the logical block number of each block contained in the memory circuit connected to the IC that includes that translator, and a physical portion ID of a portion of that memory circuit that contains that block; and a driver for receiving the physical portion ID from the translator of the IC that includes that driver and accessing the portion of the memory connected to that IC that is identified by that physical portion ID, wherein at least one of the ICs includes circuitry for receiving a request from an external source for a block identified by the global ID of that requested block, and wherein the logic block manager of that IC includes circuitry for using the global ID of the requested block to determine the node ID and the logical block number of the requested block; if the circuitry for using determines that the node ID of the requested block is not the node ID of the IC that includes that circuitry for using, then the logic block manager circuitry of that IC employs circuitry for causing that IC to route data for the request to at least one other of the ICs; and each of the ICs, also referred to as the source IC, further includes: circuitry for maintaining a count of how many times each of the other ICs requests a respective block contained in the memory circuit that is connected to the source IC; and circuitry for transferring a block also referred to as the transferred block, for which the count for one of the other ICs, also referred to as the destination IC, exceeds a threshold value, from the memory circuit connected to the source IC to the memory circuit connected to the destination IC.