A phase-change-based memory die comprising: a plurality of partitions; and a chip controller, the chip controller to: receive a first memory write operation at a first time; receive a second memory write operation at a second time; and send first memory write data corresponding to the first memory write operation to a first partition of the plurality of partitions; wherein the phase-change-based memory die requires a minimum amount of time to elapse after performing a memory write operation before performing a subsequent write operation, characterised in that the chip controller is further configured to: determine that a time difference between the first time and the second time is less than the minimum amount of time before performing a subsequent write operation; and in response to determining that the time difference between the first time and the second time is less than the minimum amount of time before performing a subsequent write operation: store second memory write data corresponding to the second memory write operation in a buffer of the phase-change-based memory die; and send the second memory write data from the buffer to a second partition of the plurality of partitions at least after the minimum amount of time before performing a subsequent write operation after the first memory write data is sent to the first partition has elapsed. a plurality of partitions; and a chip controller, the chip controller to: receive a first memory write operation at a first time; receive a second memory write operation at a second time; and send first memory write data corresponding to the first memory write operation to a first partition of the plurality of partitions; receive a first memory write operation at a first time; receive a second memory write operation at a second time; and send first memory write data corresponding to the first memory write operation to a first partition of the plurality of partitions; wherein the phase-change-based memory die requires a minimum amount of time to elapse after performing a memory write operation before performing a subsequent write operation, characterised in that the chip controller is further configured to: determine that a time difference between the first time and the second time is less than the minimum amount of time before performing a subsequent write operation; and in response to determining that the time difference between the first time and the second time is less than the minimum amount of time before performing a subsequent write operation: store second memory write data corresponding to the second memory write operation in a buffer of the phase-change-based memory die; and send the second memory write data from the buffer to a second partition of the plurality of partitions at least after the minimum amount of time before performing a subsequent write operation after the first memory write data is sent to the first partition has elapsed. determine that a time difference between the first time and the second time is less than the minimum amount of time before performing a subsequent write operation; and in response to determining that the time difference between the first time and the second time is less than the minimum amount of time before performing a subsequent write operation: store second memory write data corresponding to the second memory write operation in a buffer of the phase-change-based memory die; and send the second memory write data from the buffer to a second partition of the plurality of partitions at least after the minimum amount of time before performing a subsequent write operation after the first memory write data is sent to the first partition has elapsed. store second memory write data corresponding to the second memory write operation in a buffer of the phase-change-based memory die; and send the second memory write data from the buffer to a second partition of the plurality of partitions at least after the minimum amount of time before performing a subsequent write operation after the first memory write data is sent to the first partition has elapsed.