A method (600, 1500) for forming a three-dimensional semiconductor device (100, 500, 700, 1000, 1100, 1200, 1300, 1400), comprising: forming a first memory chip, comprising: forming at least one first memory cell on a first substrate and forming a first interconnect layer on the at least one first memory cell, the first interconnect layer comprising at least one first interconnect structure; forming a second memory chip, comprising: forming at least one second memory cell on a second substrate; and forming a second interconnect layer on the at least one second memory cell, the second interconnect layer comprising at least one second interconnect structure; bonding the first interconnect layer of the first memory chip with the second interconnect layer of the second memory chip, such that the at least one first memory cell of the first memory chip is electrically connected with the at least one second memory cell of the second memory chip through the at least one first interconnect structure and the at least one second interconnect structure, wherein the bonding of the first interconnect layer of the first memory chip with the second interconnect layer of the second memory chip comprises dielectric-to-dielectric bonding and metal-to-metal bonding at a bonding interface (526, 536, 1070, 1376); forming a microprocessor chip (101, 300), comprising: forming at least one microprocessor device on a third substrate; and forming a third interconnect layer on the at least one microprocessor device, the third interconnect layer comprising at least one third interconnect structure; bonding the third interconnect layer of the microprocessor chip (101, 300) with the first substrate of the first memory chip, such that the at least one microprocessor device of the microprocessor chip (101, 300) is electrically connected with the at least one first memory cell of the first memory chip through a TSV structure through the first substrate, through the at least one first interconnect structure and through the at least one third interconnect structure; and disposing an insulating film on the second substrate, wherein one or more input/output (I/O) pads are formed in the insulating film and one or more TSVs connecting through the second substrate the I/O pads to substrate contacts. forming a first memory chip, comprising: forming at least one first memory cell on a first substrate and forming a first interconnect layer on the at least one first memory cell, the first interconnect layer comprising at least one first interconnect structure; forming at least one first memory cell on a first substrate and forming a first interconnect layer on the at least one first memory cell, the first interconnect layer comprising at least one first interconnect structure; forming a second memory chip, comprising: forming at least one second memory cell on a second substrate; and forming a second interconnect layer on the at least one second memory cell, forming at least one second memory cell on a second substrate; and forming a second interconnect layer on the at least one second memory cell, the second interconnect layer comprising at least one second interconnect structure; bonding the first interconnect layer of the first memory chip with the second interconnect layer of the second memory chip, such that the at least one first memory cell of the first memory chip is electrically connected with the at least one second memory cell of the second memory chip through the at least one first interconnect structure and the at least one second interconnect structure, wherein the bonding of the first interconnect layer of the first memory chip with the second interconnect layer of the second memory chip comprises dielectric-to-dielectric bonding and metal-to-metal bonding at a bonding interface (526, 536, 1070, 1376); forming a microprocessor chip (101, 300), comprising: forming at least one microprocessor device on a third substrate; and forming a third interconnect layer on the at least one microprocessor device forming at least one microprocessor device on a third substrate; and forming a third interconnect layer on the at least one microprocessor device, the third interconnect layer comprising at least one third interconnect structure; bonding the third interconnect layer of the microprocessor chip (101, 300) with the first substrate of the first memory chip, such that the at least one microprocessor device of the microprocessor chip (101, 300) is electrically connected with the at least one first memory cell of the first memory chip through a TSV structure through the first substrate, through the at least one first interconnect structure and through the at least one third interconnect structure; and disposing an insulating film on the second substrate, wherein one or more input/output (I/O) pads are formed in the insulating film and one or more TSVs connecting through the second substrate the I/O pads to substrate contacts.