A power converter, comprising: switching devices constituting each of upper and lower arms, each switching device being composed of plural semiconductor chips, the plural semiconductor chips being connected in parallel and evenly divided into a first group and a second group; an insulating substrate having thereon plural circuit patterns (24A, 24B, 24C, 24D); a positive conductor and a negative conductor being insulated from and disposed adjacent to and parallel to each other; a capacitor having a positive terminal and a negative terminal, the positive terminal being connected to the positive conductor, the negative terminal being connected to the negative conductor; and an output electrode (32U, 32V, 32W) being connected to a node between the upper and lower arms, characterized in that the positive conductor includes a first terminal portion and a second terminal portion, the first terminal portion is joined to a circuit pattern on which the first group of semiconductor chips are mounted, the second terminal portion is joined to a circuit pattern on which the second group of semiconductor chips are mounted, the output electrode (32U, 32V, 32W) includes a base portion and an electrode portion, the electrode portion has an end portion being joined to the base portion, the base portion has a first connecting portion and a second connecting portion, the first connecting portion is joined to a circuit pattern that is electrically connected to the first group of semiconductor chips of the upper arm, the second connecting portion is joined to a circuit pattern that is electrically connected to the second group of semiconductor chips of the upper arm, and the output electrode (32U, 32V, 32W) is formed so as to reduce or cancel a difference existing between an inductance L1 of a current path from the positive terminal to the first terminal portion and an inductance L2 of a current path from the positive terminal to the second terminal portion, by providing a difference between an inductance L3 of a current path from the first connecting portion to the end portion and an inductance L4 of a current path from the second connecting portion to the end portion. switching devices constituting each of upper and lower arms, each switching device being composed of plural semiconductor chips, the plural semiconductor chips being connected in parallel and evenly divided into a first group and a second group; an insulating substrate having thereon plural circuit patterns (24A, 24B, 24C, 24D); a positive conductor and a negative conductor being insulated from and disposed adjacent to and parallel to each other; a capacitor having a positive terminal and a negative terminal, the positive terminal being connected to the positive conductor, the negative terminal being connected to the negative conductor; and an output electrode (32U, 32V, 32W) being connected to a node between the upper and lower arms, characterized in that the positive conductor includes a first terminal portion and a second terminal portion, the first terminal portion is joined to a circuit pattern on which the first group of semiconductor chips are mounted, the second terminal portion is joined to a circuit pattern on which the second group of semiconductor chips are mounted, the output electrode (32U, 32V, 32W) includes a base portion and an electrode portion, the electrode portion has an end portion being joined to the base portion, the base portion has a first connecting portion and a second connecting portion, the first connecting portion is joined to a circuit pattern that is electrically connected to the first group of semiconductor chips of the upper arm, the second connecting portion is joined to a circuit pattern that is electrically connected to the second group of semiconductor chips of the upper arm, and the output electrode (32U, 32V, 32W) is formed so as to reduce or cancel a difference existing between an inductance L1 of a current path from the positive terminal to the first terminal portion and an inductance L2 of a current path from the positive terminal to the second terminal portion, by providing a difference between an inductance L3 of a current path from the first connecting portion to the end portion and an inductance L4 of a current path from the second connecting portion to the end portion.