A memory device (200, 500) comprising: a plurality of magnetic random access memory ("MRAM") cells; a plurality of bit lines, each of the plurality of bit lines being electrically connected to a corresponding one of the plurality of MRAM cells; a bit line controller (940, 540); a field line; and a field line controller (930, 530) configured to generate a write sequence that traverses the field line, the write sequence for writing a multi-bit word to the plurality of MRAM cells, the multi-bit word including a first subset of bits having a first polarity and a second subset of bits having a second polarity; wherein the write sequence writes concurrently to at least a subset of the plurality of MRAM cells corresponding to the first subset of bits having the first polarity so as to orient the subset of the plurality of MRAM cells to the first polarity, then subsequently writes concurrently to a remaining subset of the plurality of MRAM cells corresponding to the second subset of bits having the second polarity so as to orient the remaining subset of the plurality of MRAM cells to the second polarity; and wherein the bit line controller is configured to generate a first heating signal that traverses each of at least a subset of the plurality of bit lines electrically connected to corresponding ones of the at least a subset of the plurality of MRAM cells, wherein the first heating signal heats each of the at least a subset of the plurality of MRAM cells for a heating time period during a first write cycle; wherein the bit line controller is configured to generate a second heating signal that traverses each of a remaining subset of the plurality of bit lines electrically connected to corresponding ones of the remaining subset of the plurality of MRAM cells, wherein the second heating signal pre-heats each of the remaining subset of the plurality of MRAM cells for a pre-heating time period during the first write cycle, and heats the each of the remaining subset of the plurality of MRAM cells for a heating time period during the second write cycle that is shorter than the heating time period during the first write cycle, so that a duration of the second write cycle is shorter than a duration of the first write cycle. a plurality of magnetic random access memory ("MRAM") cells; a plurality of bit lines, each of the plurality of bit lines being electrically connected to a corresponding one of the plurality of MRAM cells; a bit line controller (940, 540); a field line; and a field line controller (930, 530) configured to generate a write sequence that traverses the field line, the write sequence for writing a multi-bit word to the plurality of MRAM cells, the multi-bit word including a first subset of bits having a first polarity and a second subset of bits having a second polarity; wherein the write sequence writes concurrently to at least a subset of the plurality of MRAM cells corresponding to the first subset of bits having the first polarity so as to orient the subset of the plurality of MRAM cells to the first polarity, then subsequently writes concurrently to a remaining subset of the plurality of MRAM cells corresponding to the second subset of bits having the second polarity so as to orient the remaining subset of the plurality of MRAM cells to the second polarity; and wherein the bit line controller is configured to generate a first heating signal that traverses each of at least a subset of the plurality of bit lines electrically connected to corresponding ones of the at least a subset of the plurality of MRAM cells, wherein the first heating signal heats each of the at least a subset of the plurality of MRAM cells for a heating time period during a first write cycle; wherein the bit line controller is configured to generate a second heating signal that traverses each of a remaining subset of the plurality of bit lines electrically connected to corresponding ones of the remaining subset of the plurality of MRAM cells, wherein the second heating signal pre-heats each of the remaining subset of the plurality of MRAM cells for a pre-heating time period during the first write cycle, and heats the each of the remaining subset of the plurality of MRAM cells for a heating time period during the second write cycle that is shorter than the heating time period during the first write cycle, so that a duration of the second write cycle is shorter than a duration of the first write cycle.