A display apparatus with a driving device comprising: a first voltage generator which receives a power voltage from an exterior power source and outputs a first driving voltage (AVDD1); a second voltage generator which receives the power voltage and outputs a second driving voltage (AVDD2); an output timing controller (130, 170) which receives the first and second driving voltages (AVDD1, AVDD2) from the first and second voltage generators (110, 120), respectively, wherein the output timing controller comprises means to output a third driving voltage (AVDD3) at a predetermined time only when both the first and second driving voltages (AVDD1, AVDD2) are in a high state; a gamma voltage generator, which receives the third driving voltage (AVDD3) from the output timing controller, wherein the gamma voltage generator comprises means to output a plurality of gamma voltages (V GMMA), having a time delay with respect to the third driving voltage (AVDD3); a first data driver which operates in response to the third driving voltage (AVDD3) from the output timing controller to change a first image signal to a first data signal based on the gamma voltages (V GMMA) provided from the gamma voltage generator; and a second data driver which operates in response to the third driving voltage (AVDD3) from the output timing controller to change a second image signal to a second data signal based on the gamma voltages (V GMMA) provided from the gamma voltage generator; a gate driver, 272) which receives a gate-on voltage and a gate-off voltage output from either the first voltage generator or the second voltage generator and sequentially outputs a gate signal; and a timing controller which generates a timing control signal and provides the timing control signal to the output timing controller, wherein the output timing controller outputs the third driving voltage (AVDD3) at a predetermined time in response to the timing control signal, and wherein the output timing controller comprises a plurality of transistors (Tr3, Tr4) connected between a plurality of input terminals (IT1, IT2), respectively, receiving the driving voltages and a plurality of output terminals (OT1, OT2) to output the third driving voltage (AVDD3), each transistor (Tr3, Tr4) comprises an input electrode connected to a corresponding input terminal (IT1, IT2) among the input terminals (IT1, IT2), a control electrode which receives the timing control signal, and an output electrode connected to a corresponding output terminal (OT1, OT2) among the output terminals (OT1, OT2), and each transistor (Tr3, Tr4) outputs the third driving voltage (AVDD3) to the corresponding output terminal (OT1, OT2) in response to the timing control signal. a first voltage generator which receives a power voltage from an exterior power source and outputs a first driving voltage (AVDD1); a second voltage generator which receives the power voltage and outputs a second driving voltage (AVDD2); an output timing controller (130, 170) which receives the first and second driving voltages (AVDD1, AVDD2) from the first and second voltage generators (110, 120), respectively, wherein the output timing controller comprises means to output a third driving voltage (AVDD3) at a predetermined time only when both the first and second driving voltages (AVDD1, AVDD2) are in a high state; a gamma voltage generator, which receives the third driving voltage (AVDD3) from the output timing controller, wherein the gamma voltage generator comprises means to output a plurality of gamma voltages (V GMMA), having a time delay with respect to the third driving voltage (AVDD3); a first data driver which operates in response to the third driving voltage (AVDD3) from the output timing controller to change a first image signal to a first data signal based on the gamma voltages (V GMMA) provided from the gamma voltage generator; and a second data driver which operates in response to the third driving voltage (AVDD3) from the output timing controller to change a second image signal to a second data signal based on the gamma voltages (V GMMA) provided from the gamma voltage generator; a gate driver, 272) which receives a gate-on voltage and a gate-off voltage output from either the first voltage generator or the second voltage generator and sequentially outputs a gate signal; and a timing controller which generates a timing control signal and provides the timing control signal to the output timing controller, wherein the output timing controller outputs the third driving voltage (AVDD3) at a predetermined time in response to the timing control signal, and wherein the output timing controller comprises a plurality of transistors (Tr3, Tr4) connected between a plurality of input terminals (IT1, IT2), respectively, receiving the driving voltages and a plurality of output terminals (OT1, OT2) to output the third driving voltage (AVDD3), each transistor (Tr3, Tr4) comprises an input electrode connected to a corresponding input terminal (IT1, IT2) among the input terminals (IT1, IT2), a control electrode which receives the timing control signal, and an output electrode connected to a corresponding output terminal (OT1, OT2) among the output terminals (OT1, OT2), and each transistor (Tr3, Tr4) outputs the third driving voltage (AVDD3) to the corresponding output terminal (OT1, OT2) in response to the timing control signal.