Method for the production of a bipolar transistor having the steps of: providing a semiconductor substrate with a collector region of a first conduction type (n) embedded therein, said collector region being bare toward the top; providing a monocrystalline base foundation region of the second conduction type (p) and a monocrystalline base cap region of the first or second conduction type (n, p) as a base region (120, 130) above the collector region, wherein the base region (120, 130) is deposited over the whole area of the semiconductor substrate providing a base terminal region of the second conduction type (p) above the base region (120, 130); providing a first insulation region above the base terminal region; forming a window in the first insulation region and base terminal region for the purpose of at least partly uncovering the base region (120, 130); providing a first insulating sidewall spacer in the window for the purpose of insulating the base terminal region; removing a natural oxide in the uncovered base region (120, 130); differentially depositing and patterning an emitter layer (60a, 60b), which forms a monocrystalline emitter region above the base region (120, 130) and a polycrystalline emitter region above the first insulation region and the first sidewall spacer; and carrying out a heat treatment step for the purpose of partly driving the monocrystalline emitter region into the base region (120, 130) and for the purpose of forming an enlarged monocrystalline emitter region; and wherein a mask region (140, 150) is formed above the base region (120, 130) in accordance with the later window, said mask region being embedded in the base terminal region and the overlying first insulation region, after which the window is formed; the base region (120, 130) as base foundation region bordering on the collector region has a lower, more highly doped first SiGe base foundation layer and as base cap layer an upper, more lightly doped Si base cap layer, above which the base terminal region is provided, the base cap layer being doped upward during the heat treatment step from the base terminal region; and the base cap layer that is uncovered after the formation of the mask region is thinned. providing a semiconductor substrate with a collector region of a first conduction type (n) embedded therein, said collector region being bare toward the top; providing a monocrystalline base foundation region of the second conduction type (p) and a monocrystalline base cap region of the first or second conduction type (n, p) as a base region (120, 130) above the collector region, wherein the base region (120, 130) is deposited over the whole area of the semiconductor substrate providing a base terminal region of the second conduction type (p) above the base region (120, 130); providing a first insulation region above the base terminal region; forming a window in the first insulation region and base terminal region for the purpose of at least partly uncovering the base region (120, 130); providing a first insulating sidewall spacer in the window for the purpose of insulating the base terminal region; removing a natural oxide in the uncovered base region (120, 130); differentially depositing and patterning an emitter layer (60a, 60b), which forms a monocrystalline emitter region above the base region (120, 130) and a polycrystalline emitter region above the first insulation region and the first sidewall spacer; and carrying out a heat treatment step for the purpose of partly driving the monocrystalline emitter region into the base region (120, 130) and for the purpose of forming an enlarged monocrystalline emitter region; and wherein a mask region (140, 150) is formed above the base region (120, 130) in accordance with the later window, said mask region being embedded in the base terminal region and the overlying first insulation region, after which the window is formed; the base region (120, 130) as base foundation region bordering on the collector region has a lower, more highly doped first SiGe base foundation layer and as base cap layer an upper, more lightly doped Si base cap layer, above which the base terminal region is provided, the base cap layer being doped upward during the heat treatment step from the base terminal region; and the base cap layer that is uncovered after the formation of the mask region is thinned.