A device for generating an identification key based on a plurality of digital bits, the device comprising: a first node (110, 250) included in a semiconductor chip; a second node (120, 210, 230, 322, 324, 326, 540, 640) formed in a different layer from the first node (110, 250); a via (130, 220, 240, 321, 323, 325, 530, 630) formed between the first node (110, 250) and the second node (120, 210, 230, 322, 324, 326, 540, 640) and electrically shorted to the first node (110, 250), and a reader configured to determine whether the first node (110, 250) and the second node (120, 210, 230, 322, 324, 326, 540, 640) are shorted by the via and to generate a digital bit value; wherein the first node (110, 250), the second node (120, 210, 230, 322, 324, 326, 540, 640), the via (130, 220, 240, 321, 323, 325, 530, 630) and the reader are formed on a semiconductor substrate characterized in that the second node (120, 210, 230, 322, 324, 326, 540, 640) overlaps only part of the via (130, 220, 240, 321, 323, 325, 530, 630) in a top view of a pattern layout of the semiconductor chip, an overlap distance between the second node (120, 210, 230, 322, 324, 326, 540, 640) and the via (130, 220, 240, 321, 323, 325, 530, 630) in the pattern layout being adjusted to be less than a threshold according to a design rule that ensures that the first node (110, 250) and the second node (120, 210, 230, 322, 324, 326, 540, 640) are shorted by the via (130, 220,240,321,323,325,530,630); wherein the overlap distance between the second node (120, 210, 230, 322, 324, 326, 540, 640) and the via (130, 220, 240, 321, 323, 325, 530, 630) in the pattern layout of the semiconductor chip is adjusted to be equal to or greater than a first threshold and equal to or less than a second threshold; wherein the first threshold is a minimum value of an overlap distance allowing a difference between a probability that the first node (110, 250) and the second node (120, 210, 230, 322, 324, 326, 540, 640) are shorted by the via (130, 220, 240, 321, 323, 325, 530, 630) and a probability that the first node (110, 250) and the second node (120, 210, 230, 322, 324, 326, 540, 640) are not shorted to be within a predetermined error range, and wherein the second threshold is a maximum value of the overlap distance allowing the difference between the probability that the first node (110, 250) and the second node (120, 210, 230, 322, 324, 326, 540, 640) are shorted by the via (130, 220, 240, 321, 323, 325, 530, 630) and the probability that the first node (110, 250) and the second node (120, 210, 230, 322, 324, 326, 540, 640) are not shorted to be within the predetermined error range.. a first node (110, 250) included in a semiconductor chip; a second node (120, 210, 230, 322, 324, 326, 540, 640) formed in a different layer from the first node (110, 250); a via (130, 220, 240, 321, 323, 325, 530, 630) formed between the first node (110, 250) and the second node (120, 210, 230, 322, 324, 326, 540, 640) and electrically shorted to the first node (110, 250), and a reader configured to determine whether the first node (110, 250) and the second node (120, 210, 230, 322, 324, 326, 540, 640) are shorted by the via and to generate a digital bit value; wherein the first node (110, 250), the second node (120, 210, 230, 322, 324, 326, 540, 640), the via (130, 220, 240, 321, 323, 325, 530, 630) and the reader are formed on a semiconductor substrate characterized in that the second node (120, 210, 230, 322, 324, 326, 540, 640) overlaps only part of the via (130, 220, 240, 321, 323, 325, 530, 630) in a top view of a pattern layout of the semiconductor chip, an overlap distance between the second node (120, 210, 230, 322, 324, 326, 540, 640) and the via (130, 220, 240, 321, 323, 325, 530, 630) in the pattern layout being adjusted to be less than a threshold according to a design rule that ensures that the first node (110, 250) and the second node (120, 210, 230, 322, 324, 326, 540, 640) are shorted by the via (130, 220,240,321,323,325,530,630); wherein the overlap distance between the second node (120, 210, 230, 322, 324, 326, 540, 640) and the via (130, 220, 240, 321, 323, 325, 530, 630) in the pattern layout of the semiconductor chip is adjusted to be equal to or greater than a first threshold and equal to or less than a second threshold; wherein the first threshold is a minimum value of an overlap distance allowing a difference between a probability that the first node (110, 250) and the second node (120, 210, 230, 322, 324, 326, 540, 640) are shorted by the via (130, 220, 240, 321, 323, 325, 530, 630) and a probability that the first node (110, 250) and the second node (120, 210, 230, 322, 324, 326, 540, 640) are not shorted to be within a predetermined error range, and wherein the second threshold is a maximum value of the overlap distance allowing the difference between the probability that the first node (110, 250) and the second node (120, 210, 230, 322, 324, 326, 540, 640) are shorted by the via (130, 220, 240, 321, 323, 325, 530, 630) and the probability that the first node (110, 250) and the second node (120, 210, 230, 322, 324, 326, 540, 640) are not shorted to be within the predetermined error range..