A semiconductor storage device comprising: a memory array comprising a plurality of memory cells provided in rows and columns; and a control circuit for controlling the memory array, each of the memory cells being a static-type memory cell comprising driving transistors (NT0, NT1), transfer transistors (AT0, AT1), and load elements (PTO, PT1), the memory array being divided into subdivisions, each subdivision being at least one column of memory cells, the control circuit comprising, with respect to each column of memory cells: a source line (ARVSS) coupled to a source electrode of each of the driving transistors; a plurality of first switching transistors coupled between the source line and a ground voltage; and a plurality of second switching transistors coupled between the source line and the ground voltage, wherein one pair of the first and second switching transistors (31, 32) is provided at one end side of said column of memory cells, another pair of the first and second switching transistors (31, 32) is provided at the other end side of said column of memory cells, the control circuit is adapted to adjust the potential of the source line by controlling the first and second switching transistors, and the control circuit is adapted to make the first and second switching transistors conductive to couple the source line to the ground voltage, respectively, when the memory cells are operating, and set the first switching transistors non-conductive and set a gate electrode of the second switching transistors coupled to the source line, when the memory cells are in standby mode. a memory array comprising a plurality of memory cells provided in rows and columns; and a control circuit for controlling the memory array, each of the memory cells being a static-type memory cell comprising driving transistors (NT0, NT1), transfer transistors (AT0, AT1), and load elements (PTO, PT1), the memory array being divided into subdivisions, each subdivision being at least one column of memory cells, the control circuit comprising, with respect to each column of memory cells: a source line (ARVSS) coupled to a source electrode of each of the driving transistors; a plurality of first switching transistors coupled between the source line and a ground voltage; and a plurality of second switching transistors coupled between the source line and the ground voltage, a source line (ARVSS) coupled to a source electrode of each of the driving transistors; a plurality of first switching transistors coupled between the source line and a ground voltage; and a plurality of second switching transistors coupled between the source line and the ground voltage, wherein one pair of the first and second switching transistors (31, 32) is provided at one end side of said column of memory cells, another pair of the first and second switching transistors (31, 32) is provided at the other end side of said column of memory cells, the control circuit is adapted to adjust the potential of the source line by controlling the first and second switching transistors, and the control circuit is adapted to make the first and second switching transistors conductive to couple the source line to the ground voltage, respectively, when the memory cells are operating, and set the first switching transistors non-conductive and set a gate electrode of the second switching transistors coupled to the source line, when the memory cells are in standby mode.