A display panel including a pixel which has a plurality of sub-pixels comprising: a transistor array substrate which is formed by providing a plurality of transistors for a red sub-pixel (Pr), a green sub-pixel (Pg) and a blue sub-pixel (Pb) of the plurality of the sub-pixels, each of the transistors having a gate, a gate insulating film, a source, and a drain; a plurality of interconnections (89, 90) which are arrayed on a surface of the transistor array substrate; a plurality of sub-pixel electrodes which are provided for the sub-pixels and arrayed between the interconnections on the surface of the transistor array substrate along the interconnections; a counter electrode which is provided above the plurality of the sub-pixel electrodes; and a plurality of light emitting layers each of which is provided between the one of the sub-pixel electrodes and the counter electrode, and which includes a red light-emitting layer for the red sub-pixel (Pr), a green light-emitting layer for the green sub-pixel (Pg) and a blue light-emitting layer for the blue sub-pixel (Pb), wherein the plurality of transistors include at least a driving transistor one of the source and drain of which is connected to the sub-pixel electrode, and a switch transistor which supplies a write current between the drain and source of the driving transistor, the plurality of interconnections include a feed interconnection connected to the other of the source and drain of the driving transistor, and a select interconnection which selects the switch transistor, the feed interconnection and the select interconnection being arrayed in parallel to each other and projecting from the transistor array substrate, and the light-emitting layer is positioned lower than the upper surface of the feed interconnection and the select interconnection, two opposite sides of the light-emitting layer being adjacent to the feed interconnection and the select interconnection characterized in that the plurality of interconnections further comprise a common interconnection which is connected to the counter electrode and which is provided so as to project from a surface of the transistor array substrate so as to be arrayed in parallel to the feed interconnection, wherein the light-emitting layer is positioned lower than the upper surface of the common interconnection, and each of the red light-emitting layer, the green light-emitting layer and the blue light-emitting layer is arranged so as to be formed respectively between two arbitrary interconnections among the feed interconnection, the select interconnection and the common interconnection. a transistor array substrate which is formed by providing a plurality of transistors for a red sub-pixel (Pr), a green sub-pixel (Pg) and a blue sub-pixel (Pb) of the plurality of the sub-pixels, each of the transistors having a gate, a gate insulating film, a source, and a drain; a plurality of interconnections (89, 90) which are arrayed on a surface of the transistor array substrate; a plurality of sub-pixel electrodes which are provided for the sub-pixels and arrayed between the interconnections on the surface of the transistor array substrate along the interconnections; a counter electrode which is provided above the plurality of the sub-pixel electrodes; and a plurality of light emitting layers each of which is provided between the one of the sub-pixel electrodes and the counter electrode, and which includes a red light-emitting layer for the red sub-pixel (Pr), a green light-emitting layer for the green sub-pixel (Pg) and a blue light-emitting layer for the blue sub-pixel (Pb), wherein the plurality of transistors include at least a driving transistor one of the source and drain of which is connected to the sub-pixel electrode, and a switch transistor which supplies a write current between the drain and source of the driving transistor, the plurality of interconnections include a feed interconnection connected to the other of the source and drain of the driving transistor, and a select interconnection which selects the switch transistor, the feed interconnection and the select interconnection being arrayed in parallel to each other and projecting from the transistor array substrate, and the light-emitting layer is positioned lower than the upper surface of the feed interconnection and the select interconnection, two opposite sides of the light-emitting layer being adjacent to the feed interconnection and the select interconnection characterized in that the plurality of interconnections further comprise a common interconnection which is connected to the counter electrode and which is provided so as to project from a surface of the transistor array substrate so as to be arrayed in parallel to the feed interconnection, wherein the light-emitting layer is positioned lower than the upper surface of the common interconnection, and each of the red light-emitting layer, the green light-emitting layer and the blue light-emitting layer is arranged so as to be formed respectively between two arbitrary interconnections among the feed interconnection, the select interconnection and the common interconnection.