An identification device, comprising: a) an interposer (132, 210) having pads (134, 136) thereon, wherein said interposer comprises a metal foil and at least one barrier coat thereon; b) an antenna and/or inductor affixed to or positioned on an applicator sheet, said antenna and/or inductor being attached or affixed to said interposer, such that electrical connections are formed between the pads on the interposer and terminals of the antenna and/or inductor through the holes or vias through the interposer at locations corresponding to the locations of said pads, said antenna and/or inductor being planar; and c) integrated circuitry on a major surface of and formed directly on said interposer(132, 210), said integrated circuitry being electrically connected to said terminals of said antenna and/or inductor via said pads, said pads (134, 136) being electrically connected to said integrated circuitry through vias or holes in an uppermost dielectric layer of said integrated circuitry, and said integrated circuitry comprising (i) a plurality of thin film transistors and (ii) metallization conductive structures interconnecting the thin film transistors, the integrated circuitry comprising at least one printed thin film layer and having a lowest layer in physical contact with said major surface of said interposer, said integrated circuitry further comprising a gate metal layer (230, 232, 234), a semiconductor layer (250, 255) and a gate insulator layer between said gate metal layer and said semiconductor layer, and said at least one printed thin film layer comprising at least one of said gate metal layer and said semiconductor layer. a) an interposer (132, 210) having pads (134, 136) thereon, wherein said interposer comprises a metal foil and at least one barrier coat thereon; b) an antenna and/or inductor affixed to or positioned on an applicator sheet, said antenna and/or inductor being attached or affixed to said interposer, such that electrical connections are formed between the pads on the interposer and terminals of the antenna and/or inductor through the holes or vias through the interposer at locations corresponding to the locations of said pads, said antenna and/or inductor being planar; and c) integrated circuitry on a major surface of and formed directly on said interposer(132, 210), said integrated circuitry being electrically connected to said terminals of said antenna and/or inductor via said pads, said pads (134, 136) being electrically connected to said integrated circuitry through vias or holes in an uppermost dielectric layer of said integrated circuitry, and said integrated circuitry comprising (i) a plurality of thin film transistors and (ii) metallization conductive structures interconnecting the thin film transistors, the integrated circuitry comprising at least one printed thin film layer and having a lowest layer in physical contact with said major surface of said interposer, said integrated circuitry further comprising a gate metal layer (230, 232, 234), a semiconductor layer (250, 255) and a gate insulator layer between said gate metal layer and said semiconductor layer, and said at least one printed thin film layer comprising at least one of said gate metal layer and said semiconductor layer. (i) a plurality of thin film transistors and (ii) metallization conductive structures interconnecting the thin film transistors, the integrated circuitry comprising at least one printed thin film layer and having a lowest layer in physical contact with said major surface of said interposer, said integrated circuitry further comprising a gate metal layer (230, 232, 234), a semiconductor layer (250, 255) and a gate insulator layer between said gate metal layer and said semiconductor layer, and said at least one printed thin film layer comprising at least one of said gate metal layer and said semiconductor layer.