A processor, comprising: a network; a plurality of processing cores (302_1,... 302_8) coupled to the network; a transmitter circuit (501, 610) coupled to the network, the transmitter circuit (501, 610) to transmit output data generated by one of the processing cores (302_1,... 302_8) into the network, the transmitter circuit (501, 610) comprising control logic circuitry which is configured to cause the transmitter circuit (501, 610) to send, prior to completion of the transmitter circuit's (501, 610) transmission of an earlier first packet (PACKET_1) of output data to a first destination, a request (RTS_2) to permit the transmitter circuit (501, 610) to transmit a second packet (PACKET_2) of output data to a second destination, wherein the control logic circuitry includes a first credit counter (606_1) and a second credit counter (606_2) and is configured to: control the transmission of the first packet (PACKET_1) to the first destination according to a credit count kept in the first credit counter (606_1) and to control the transmission of the second packet (PACKET_2) to the second destination according to a credit count kept in the second credit counter (606_2); cause the transmitter circuit (501, 610) to receive, from the second destination, an acknowledgement (ACK_2) of the request (RTS_2) for the second data packet (PACKET_2) to be transmitted to the second destination before a last data unit of the first data packet (PACKET_1) has been transmitted from the transmitter circuit (501, 610) to the first destination; increment the second credit counter (606_2) with credits received from the second destination in response to receiving the acknowledgement (ACK_2) of the request (RTS_2) for the second data packet (PACKET_2) to be transmitted; and cause the transmitter circuit (501, 610) to transmit the second packet (PACKET_1) of output data to the second destination according to the credit count kept in the second credit counter (606_2). a network; a plurality of processing cores (302_1,... 302_8) coupled to the network; a transmitter circuit (501, 610) coupled to the network, the transmitter circuit (501, 610) to transmit output data generated by one of the processing cores (302_1,... 302_8) into the network, the transmitter circuit (501, 610) comprising control logic circuitry which is configured to cause the transmitter circuit (501, 610) to send, prior to completion of the transmitter circuit's (501, 610) transmission of an earlier first packet (PACKET_1) of output data to a first destination, a request (RTS_2) to permit the transmitter circuit (501, 610) to transmit a second packet (PACKET_2) of output data to a second destination, wherein the control logic circuitry includes a first credit counter (606_1) and a second credit counter (606_2) and is configured to: control the transmission of the first packet (PACKET_1) to the first destination according to a credit count kept in the first credit counter (606_1) and to control the transmission of the second packet (PACKET_2) to the second destination according to a credit count kept in the second credit counter (606_2); cause the transmitter circuit (501, 610) to receive, from the second destination, an acknowledgement (ACK_2) of the request (RTS_2) for the second data packet (PACKET_2) to be transmitted to the second destination before a last data unit of the first data packet (PACKET_1) has been transmitted from the transmitter circuit (501, 610) to the first destination; increment the second credit counter (606_2) with credits received from the second destination in response to receiving the acknowledgement (ACK_2) of the request (RTS_2) for the second data packet (PACKET_2) to be transmitted; and cause the transmitter circuit (501, 610) to transmit the second packet (PACKET_1) of output data to the second destination according to the credit count kept in the second credit counter (606_2). control the transmission of the first packet (PACKET_1) to the first destination according to a credit count kept in the first credit counter (606_1) and to control the transmission of the second packet (PACKET_2) to the second destination according to a credit count kept in the second credit counter (606_2); cause the transmitter circuit (501, 610) to receive, from the second destination, an acknowledgement (ACK_2) of the request (RTS_2) for the second data packet (PACKET_2) to be transmitted to the second destination before a last data unit of the first data packet (PACKET_1) has been transmitted from the transmitter circuit (501, 610) to the first destination; increment the second credit counter (606_2) with credits received from the second destination in response to receiving the acknowledgement (ACK_2) of the request (RTS_2) for the second data packet (PACKET_2) to be transmitted; and cause the transmitter circuit (501, 610) to transmit the second packet (PACKET_1) of output data to the second destination according to the credit count kept in the second credit counter (606_2).