A simulator comprising: a first core unit corresponding to a first simulation model in which a non-blocking processing is performed, a second core unit corresponding to a second simulation model in which a blocking processing is performed, the first simulation model being a model for simulation with higher precision than the second simulation model, and the second simulation model being a model for simulation faster than the first simulation model, a slave block unit (2, 3) for communicating with either the first core unit or the second core unit, and a simulation control unit for making either the first core unit or the second core unit execute instructions, wherein the first core unit includes: an instruction execution unit for executing a program for the first simulation model while updating a program counter, an instruction execution control unit for controlling the instruction execution unit, a data unit for receiving data that is generated when the program is executed, a data copy control unit connected between the first core unit and the second core unit, a high speed mode instruction execution control unit for controlling the instruction execution unit, instead of the instruction execution control unit, so as to stop the execution of subsequent instructions, in response to the switching request from the first simulation model to the second simulation model, and a transaction monitor unit for monitoring whether all transaction processing, which is non-blocking, between the first core unit and the slave block unit (2, 3) is completed or not, wherein the simulation control unit instructs, in response to a notification of completion of all transaction processing from the transaction monitor unit, the data copy control unit to copy the data in the data unit to a data unit of the second core unit, wherein the simulation control unit causes the second core unit to execute instructions in response to a notification of completion of the data copy from the data copy control unit. a first core unit corresponding to a first simulation model in which a non-blocking processing is performed, a second core unit corresponding to a second simulation model in which a blocking processing is performed, the first simulation model being a model for simulation with higher precision than the second simulation model, and the second simulation model being a model for simulation faster than the first simulation model, a slave block unit (2, 3) for communicating with either the first core unit or the second core unit, and a simulation control unit for making either the first core unit or the second core unit execute instructions, wherein the first core unit includes: an instruction execution unit for executing a program for the first simulation model while updating a program counter, an instruction execution control unit for controlling the instruction execution unit, a data unit for receiving data that is generated when the program is executed, a data copy control unit connected between the first core unit and the second core unit, a high speed mode instruction execution control unit for controlling the instruction execution unit, instead of the instruction execution control unit, so as to stop the execution of subsequent instructions, in response to the switching request from the first simulation model to the second simulation model, and a transaction monitor unit for monitoring whether all transaction processing, which is non-blocking, between the first core unit and the slave block unit (2, 3) is completed or not, wherein the simulation control unit instructs, in response to a notification of completion of all transaction processing from the transaction monitor unit, the data copy control unit to copy the data in the data unit to a data unit of the second core unit, wherein the simulation control unit causes the second core unit to execute instructions in response to a notification of completion of the data copy from the data copy control unit. an instruction execution unit for executing a program for the first simulation model while updating a program counter, an instruction execution control unit for controlling the instruction execution unit, a data unit for receiving data that is generated when the program is executed, a data copy control unit connected between the first core unit and the second core unit, a high speed mode instruction execution control unit for controlling the instruction execution unit, instead of the instruction execution control unit, so as to stop the execution of subsequent instructions, in response to the switching request from the first simulation model to the second simulation model, and a transaction monitor unit for monitoring whether all transaction processing, which is non-blocking, between the first core unit and the slave block unit (2, 3) is completed or not, wherein the simulation control unit instructs, in response to a notification of completion of all transaction processing from the transaction monitor unit, the data copy control unit to copy the data in the data unit to a data unit of the second core unit, wherein the simulation control unit causes the second core unit to execute instructions in response to a notification of completion of the data copy from the data copy control unit.