A liquid crystal display device including a thin film transistor substrate comprising: a plurality of gate lines, a plurality of first and second data lines (130a, 130b) intersecting the gate lines; a plurality of first and second thin film transistors (120a, 120b) formed in unit pixel regions each defined by a gate line, a first data line, and a second data line, the first thin film transistor (120a, 120b) having a first drain electrode and a first gate electrode, the second thin film transistor having a second drain electrode and a second gate electrode, respectively; a plurality of first and second pixel electrodes (170a, 170b) formed in the unit pixel regions; a plurality, of first drain electrode plates each of which is connected to one of the pixel electrodes (170a, 170b) and one of the drain electrodes (126a; 126b) included in the unit pixel region; a plurality of second drain electrode plates each of which is connected to the other one of the pixel electrodes (170a, 170b) and the other one of the dra in electrodes (126a, 126b) included in the unit pixel region; the first gate electrode and the second gate electrode in the unit pixel region being extended from the same gate line; characterized in that one storage electrode plate partially overlaps the first and second drain electrode plates (150a; 150b) of the first and second drain electrodes (126a; 126b) in each unit pixel region; a longer side of the storage electrode plate is parallel to the plurality of first and second data lines (130a, 130b); in one unit pixel region, the first drain electrode is connected to the first drain electrode plate and the second drain electrode is connected to the second drain electrode plate; and in another unit pixel region adjacent to the one unit pixel region, the first drain electrode is connected to the second drain electrode plate, and the second drain electrode is connected to the first drain electrode plate. a plurality of gate lines, a plurality of first and second data lines (130a, 130b) intersecting the gate lines; a plurality of first and second thin film transistors (120a, 120b) formed in unit pixel regions each defined by a gate line, a first data line, and a second data line, the first thin film transistor (120a, 120b) having a first drain electrode and a first gate electrode, the second thin film transistor having a second drain electrode and a second gate electrode, respectively; a plurality of first and second pixel electrodes (170a, 170b) formed in the unit pixel regions; a plurality, of first drain electrode plates each of which is connected to one of the pixel electrodes (170a, 170b) and one of the drain electrodes (126a; 126b) included in the unit pixel region; a plurality of second drain electrode plates each of which is connected to the other one of the pixel electrodes (170a, 170b) and the other one of the dra in electrodes (126a, 126b) included in the unit pixel region; the first gate electrode and the second gate electrode in the unit pixel region being extended from the same gate line; characterized in that one storage electrode plate partially overlaps the first and second drain electrode plates (150a; 150b) of the first and second drain electrodes (126a; 126b) in each unit pixel region; a longer side of the storage electrode plate is parallel to the plurality of first and second data lines (130a, 130b); in one unit pixel region, the first drain electrode is connected to the first drain electrode plate and the second drain electrode is connected to the second drain electrode plate; and in another unit pixel region adjacent to the one unit pixel region, the first drain electrode is connected to the second drain electrode plate, and the second drain electrode is connected to the first drain electrode plate.