A semiconductor device comprising: a first chip including first and second surfaces opposed to each other, wherein the first chip includes first, second and third dummy bumps (152d3, 152d2 and 152d1), used for conduction test in the semiconductor device, on a side of the first surface and a first wiring electrically connecting the second and third dummy bumps with each other, the first dummy bump being disconnected from each of the second and third dummy bumps in the first chip, characterized in that the semiconductor device further comprises a second chip including third and fourth surfaces opposed to each other, and being stacked with the first chip such that the third surface faces to the first surface of the first chip; that the second chip includes fourth, fifth and sixth dummy bumps (151d3, 151d2 and 151d1), used for conduction test in the semiconductor device, on a side of the third surface and a second wiring electrically connecting the fourth and fifth dummy bumps with each other, the sixth bump being disconnected from each of the fourth and fifth dummy bumps in the second chip; that the first and second chips are stacked with each other such that the first, second and third dummy bumps are coupled respectively to the fourth, fifth and sixth dummy bumps so that the first, fourth, fifth, second, third and sixth dummy bumps (152d3, 151d3, 151d2, 152d2, 152d1, and 151d1, respectively) are electrically connected in series through the first and second wirings; that the first chip further includes ninth, tenth and eleventh dummy bumps (151d3, 151d2 and 151d1 on 101) on the second surface, the ninth, tenth and eleventh dummy bumps being aligned with the first, second and third dummy bumps in a second direction perpendicular to the first and second surfaces, respectively; and that the semiconductor device further comprises a third chip stacked with the first and second chips and including twelfth, thirteenth and fourteenth dummy bumps on a side thereof which are coupled respectively to the ninth, tenth and eleventh dummy bumps of the first chip in the same manner as the serial connection of the first, fourth, fifth, second, third and sixth dummy bumps, wherein the third chip comprises a third dummy bump connecting wiring; and wherein the conduction test is performed on the electrical series connection of the first, second and third wiring. a first chip including first and second surfaces opposed to each other, wherein the first chip includes first, second and third dummy bumps (152d3, 152d2 and 152d1), used for conduction test in the semiconductor device, on a side of the first surface and a first wiring electrically connecting the second and third dummy bumps with each other, the first dummy bump being disconnected from each of the second and third dummy bumps in the first chip, characterized in that the semiconductor device further comprises a second chip including third and fourth surfaces opposed to each other, and being stacked with the first chip such that the third surface faces to the first surface of the first chip; that the second chip includes fourth, fifth and sixth dummy bumps (151d3, 151d2 and 151d1), used for conduction test in the semiconductor device, on a side of the third surface and a second wiring electrically connecting the fourth and fifth dummy bumps with each other, the sixth bump being disconnected from each of the fourth and fifth dummy bumps in the second chip; that the first and second chips are stacked with each other such that the first, second and third dummy bumps are coupled respectively to the fourth, fifth and sixth dummy bumps so that the first, fourth, fifth, second, third and sixth dummy bumps (152d3, 151d3, 151d2, 152d2, 152d1, and 151d1, respectively) are electrically connected in series through the first and second wirings; that the first chip further includes ninth, tenth and eleventh dummy bumps (151d3, 151d2 and 151d1 on 101) on the second surface, the ninth, tenth and eleventh dummy bumps being aligned with the first, second and third dummy bumps in a second direction perpendicular to the first and second surfaces, respectively; and that the semiconductor device further comprises a third chip stacked with the first and second chips and including twelfth, thirteenth and fourteenth dummy bumps on a side thereof which are coupled respectively to the ninth, tenth and eleventh dummy bumps of the first chip in the same manner as the serial connection of the first, fourth, fifth, second, third and sixth dummy bumps, wherein the third chip comprises a third dummy bump connecting wiring; and wherein the conduction test is performed on the electrical series connection of the first, second and third wiring.