An image sensor for an electronic device, comprising: a photodiode chip comprising: at least one photodiode for receiving light; a transfer gate extending vertically from a top surface of the photodiode chip; a transistor array chip in communication with the photodiode chip and vertically stacked on the photodiode chip, the transistor array chip comprising: a floating diffusion node in communication with the at least one photodiode; a reset gate in communication with the at least one photodiode; a source follower gate in communication with the floating diffusion node; and a row select gate in communication with the source follower gate and the floating diffusion node; a logic chip operably vertically stacked on the transistor array chip and in communication therewith; wherein the transfer gate communicates data from the at least one photodiode to the transistor array chip and is connected to the transistor array chip, wherein the transfer gate comprises: a semiconductor transfer channel; an oxide layer surrounding an outer perimeter surface of the semiconductor transfer channel; a polysilicon layer at least partially surrounding an outer perimeter surface of the oxide layer; and a metal layer in communication with the semiconductor transfer channel and the oxide layer; wherein the semiconductor transfer channel extends vertically from the top surface of the photodiode chip; and the metal layer communicatively connects the transfer gate to the transistor array chip; and the logic chip selectively activates the vertical transfer gate, the reset gate, the source follower gate, and the row select gate. a photodiode chip comprising: at least one photodiode for receiving light; a transfer gate extending vertically from a top surface of the photodiode chip; at least one photodiode for receiving light; a transfer gate extending vertically from a top surface of the photodiode chip; a transistor array chip in communication with the photodiode chip and vertically stacked on the photodiode chip, the transistor array chip comprising: a floating diffusion node in communication with the at least one photodiode; a reset gate in communication with the at least one photodiode; a source follower gate in communication with the floating diffusion node; and a row select gate in communication with the source follower gate and the floating diffusion node; a floating diffusion node in communication with the at least one photodiode; a reset gate in communication with the at least one photodiode; a source follower gate in communication with the floating diffusion node; and a row select gate in communication with the source follower gate and the floating diffusion node; a logic chip operably vertically stacked on the transistor array chip and in communication therewith; wherein the transfer gate communicates data from the at least one photodiode to the transistor array chip and is connected to the transistor array chip, wherein the transfer gate comprises: a semiconductor transfer channel; an oxide layer surrounding an outer perimeter surface of the semiconductor transfer channel; a polysilicon layer at least partially surrounding an outer perimeter surface of the oxide layer; and a metal layer in communication with the semiconductor transfer channel and the oxide layer; wherein the semiconductor transfer channel extends vertically from the top surface of the photodiode chip; and the metal layer communicatively connects the transfer gate to the transistor array chip; and the logic chip selectively activates the vertical transfer gate, the reset gate, the source follower gate, and the row select gate. a semiconductor transfer channel; an oxide layer surrounding an outer perimeter surface of the semiconductor transfer channel; a polysilicon layer at least partially surrounding an outer perimeter surface of the oxide layer; and a metal layer in communication with the semiconductor transfer channel and the oxide layer; wherein the semiconductor transfer channel extends vertically from the top surface of the photodiode chip; and the metal layer communicatively connects the transfer gate to the transistor array chip; and the logic chip selectively activates the vertical transfer gate, the reset gate, the source follower gate, and the row select gate.