A method of management of an electronic microcontroller system, said microcontroller system comprising: - two processors (CPU1, CPU2), with a first processor intended for the execution of a non-secure application (Appli1), exhibiting a non-guaranteed level of functional security and integrity, and a second processor dedicated to the execution of a secure application (Appli2), implementing code and data, and involving a guaranteed level of functional security and integrity, said secure application (Appli2) being able to implement a security function; - means of access to a shared memory space; - said first processor comprising a memory management unit able to implement a check of write-access, to manage write-access to the shared memory space, intended to be non-modifiable when the secure application (Appli2) implements its security function, said management method making it possible to ensure said check of write-access rendered non-modifiable by the implementation of the following steps: - the apportionment of the shared memory space between a memory area allocated to the secure application and a memory area allocated to the non-secure application; - the implementation of a buffer for the anticipation of the translation of the addresses; - the loading into said buffer for the anticipation of the translation of the addresses of a set of rules of access to the shared memory space comprising a rule prohibiting writing by the non-secure application in a reserved area of the memory area allocated to the secure application, the execution of said rule prohibiting writing being checked by the secure application (Appli2); - the copying into the shared memory space of an image (TLBCPU1) of the buffer for the anticipation of the translation of the addresses; - the loading into said image (TLBCPU1) of the buffer for the anticipation of the translation of the addresses of a rule prohibiting writing in the buffer for the anticipation of the translation of the images; - the implementation, by the memory management unit, of the access rules contained in the image (TLBCPU1) of the buffer for the anticipation of the translation of the addresses. - two processors (CPU1, CPU2), with a first processor intended for the execution of a non-secure application (Appli1), exhibiting a non-guaranteed level of functional security and integrity, and a second processor dedicated to the execution of a secure application (Appli2), implementing code and data, and involving a guaranteed level of functional security and integrity, said secure application (Appli2) being able to implement a security function; - means of access to a shared memory space; - said first processor comprising a memory management unit able to implement a check of write-access, to manage write-access to the shared memory space, intended to be non-modifiable when the secure application (Appli2) implements its security function, - the apportionment of the shared memory space between a memory area allocated to the secure application and a memory area allocated to the non-secure application; - the implementation of a buffer for the anticipation of the translation of the addresses; - the loading into said buffer for the anticipation of the translation of the addresses of a set of rules of access to the shared memory space comprising a rule prohibiting writing by the non-secure application in a reserved area of the memory area allocated to the secure application, the execution of said rule prohibiting writing being checked by the secure application (Appli2); - the copying into the shared memory space of an image (TLBCPU1) of the buffer for the anticipation of the translation of the addresses; - the loading into said image (TLBCPU1) of the buffer for the anticipation of the translation of the addresses of a rule prohibiting writing in the buffer for the anticipation of the translation of the images; - the implementation, by the memory management unit, of the access rules contained in the image (TLBCPU1) of the buffer for the anticipation of the translation of the addresses.