A receiver for generating a binary data stream from a modulated analog signal, the receiver comprising: a differentiator; a first comparator; a second comparator; and a digital circuit, an input of the differentiator configured to receive the analog signal, an output of the differentiator connected to a non-inverting input of the first comparator, an inverting input of the first comparator configured to receive a first threshold value, the output of the differentiator connected to an inverting input of the second comparator, a non-inverting input of the second comparator configured to receive a second threshold value, an output of each of the first and second comparators connected to an input of the digital circuit, and the digital circuit configured to generate the binary data stream; wherein: the first threshold value is greater than zero; and the second threshold value is less than zero; wherein the digital circuit is configured to output: a value of 1 when the output of the first comparator is 1; a value of 0 when the value of the second comparator is 1; and an unchanging value otherwise; further wherein the digital circuit comprises: a three-input NOR gate, comprising a first input, a second input, a third input, and an output; a two-input OR gate, comprising a first input, a second input, and an output; a delay block comprising an input and an output, configured to introduce a signal delay of one unit interval; and an inverter comprising an input and an output; the output of the first comparator being connected to the first input of the three-input NOR gate and to the first input of the two-input OR gate, the output of the second comparator being connected to the second input of the three-input NOR gate, the output of the three-input NOR gate being connected to the second input of the two-input OR gate, the output of the two-input OR gate being connected to the input of the delay block, the output of the delay block being connected to the input of the inverter, the output of the inverter being connected to the third input of the three-input NOR gate, and the output of the two-input OR gate being connected to the output of the digital circuit. a differentiator; a first comparator; a second comparator; and a digital circuit, an input of the differentiator configured to receive the analog signal, an output of the differentiator connected to a non-inverting input of the first comparator, an inverting input of the first comparator configured to receive a first threshold value, the output of the differentiator connected to an inverting input of the second comparator, a non-inverting input of the second comparator configured to receive a second threshold value, an output of each of the first and second comparators connected to an input of the digital circuit, and the digital circuit configured to generate the binary data stream; the first threshold value is greater than zero; and the second threshold value is less than zero; wherein the digital circuit is configured to output: a value of 1 when the output of the first comparator is 1; a value of 0 when the value of the second comparator is 1; and an unchanging value otherwise; a value of 1 when the output of the first comparator is 1; a value of 0 when the value of the second comparator is 1; and an unchanging value otherwise; further wherein the digital circuit comprises: a three-input NOR gate, comprising a first input, a second input, a third input, and an output; a two-input OR gate, comprising a first input, a second input, and an output; a delay block comprising an input and an output, configured to introduce a signal delay of one unit interval; and an inverter comprising an input and an output; a three-input NOR gate, comprising a first input, a second input, a third input, and an output; a two-input OR gate, comprising a first input, a second input, and an output; a delay block comprising an input and an output, configured to introduce a signal delay of one unit interval; and an inverter comprising an input and an output; the output of the first comparator being connected to the first input of the three-input NOR gate and to the first input of the two-input OR gate, the output of the second comparator being connected to the second input of the three-input NOR gate, the output of the three-input NOR gate being connected to the second input of the two-input OR gate, the output of the two-input OR gate being connected to the input of the delay block, the output of the delay block being connected to the input of the inverter, the output of the inverter being connected to the third input of the three-input NOR gate, and the output of the two-input OR gate being connected to the output of the digital circuit.