An integrated circuit (110, 120, 140), comprising: a physical network layer (107, 127, 147) having a first set of dies configured to perform functions associated with networking, a first side, and a second side opposite to the first side, wherein a die of the first set of dies includes multiple tiles, wherein the physical network layer further includes one or more signal pathways dynamically configurable to define respective virtual circuits, VCs, associated with respective pre-defined interconnect topologies to thereby interconnect different sets of tiles of the multiple tiles, where each topology of the multiple pre-defined interconnect topologies corresponds to a communication pattern related to a workload; a physical computing layer (105, 125, 145) having a second set of dies configured to perform functions associated with computing, with at least a die of the second set of dies being adjacent to the first side of the physical network layer or including multiple tiles; and a physical memory layer (109, 129, 149) having a third set of dies configured to perform functions associated with memory processing, with at least a die of the third set of dies being adjacent to the second side of the physical network layer, wherein at least a die of the third set of dies includes multiple tiles, and a tile of the physical memory layer includes one or more storage cells; and wherein at least a tile in the physical computing layer is further arranged to move data to another tile in the physical computing layer or a storage cell of the physical memory layer through at least one VC defined by the one or more signal pathways in the physical network layer. a physical network layer (107, 127, 147) having a first set of dies configured to perform functions associated with networking, a first side, and a second side opposite to the first side, wherein a die of the first set of dies includes multiple tiles, wherein the physical network layer further includes one or more signal pathways dynamically configurable to define respective virtual circuits, VCs, associated with respective pre-defined interconnect topologies to thereby interconnect different sets of tiles of the multiple tiles, where each topology of the multiple pre-defined interconnect topologies corresponds to a communication pattern related to a workload; a physical computing layer (105, 125, 145) having a second set of dies configured to perform functions associated with computing, with at least a die of the second set of dies being adjacent to the first side of the physical network layer or including multiple tiles; and a physical memory layer (109, 129, 149) having a third set of dies configured to perform functions associated with memory processing, with at least a die of the third set of dies being adjacent to the second side of the physical network layer, wherein at least a die of the third set of dies includes multiple tiles, and a tile of the physical memory layer includes one or more storage cells; and wherein at least a tile in the physical computing layer is further arranged to move data to another tile in the physical computing layer or a storage cell of the physical memory layer through at least one VC defined by the one or more signal pathways in the physical network layer.