A method for processing signals in a circuit, the method comprising: performing, by one or more processors and/or circuits (125, 129) comprising a multi-modulus divider, a loop filter and a voltage controlled oscillator integrated within a two-input analog phase locked loop (156, 306, 500), and a K-estimator block, a 1/K-gain block and a differentiator block integrated within a digital compensator coupled to said two-input analog phase locked loop (156, 306, 500), where K is a parameter which is representative of a bandwidth of the analogue phase locked loop: generating a first digital signal (W n) and a second digital signal (V n) based on an analog feedback signal (P t) distinct from an output (O t) of said voltage controlled oscillator and generated by said two-input analog phase locked loop (156, 306, 500) as an output of the multi-modulus divider or the loop filter, wherein the differentiator block generates a difference value for the second digital signal (V n) between a present output and a previous output from the 1/K-gain block, said difference value for the second digital signal (V n) is communicated to the two-input analog phase locked loop (156, 306, 500) as a compensated data signal (U n) for the two-input analog phase locked loop (156, 306, 500); and digitally controlling said two-input analog phase locked loop (156, 306, 500) during modulation of said signal based on said generated first digital signal (W n) and said generated second digital signal (V n). performing, by one or more processors and/or circuits (125, 129) comprising a multi-modulus divider, a loop filter and a voltage controlled oscillator integrated within a two-input analog phase locked loop (156, 306, 500), and a K-estimator block, a 1/K-gain block and a differentiator block integrated within a digital compensator coupled to said two-input analog phase locked loop (156, 306, 500), where K is a parameter which is representative of a bandwidth of the analogue phase locked loop: generating a first digital signal (W n) and a second digital signal (V n) based on an analog feedback signal (P t) distinct from an output (O t) of said voltage controlled oscillator and generated by said two-input analog phase locked loop (156, 306, 500) as an output of the multi-modulus divider or the loop filter, wherein the differentiator block generates a difference value for the second digital signal (V n) between a present output and a previous output from the 1/K-gain block, said difference value for the second digital signal (V n) is communicated to the two-input analog phase locked loop (156, 306, 500) as a compensated data signal (U n) for the two-input analog phase locked loop (156, 306, 500); and digitally controlling said two-input analog phase locked loop (156, 306, 500) during modulation of said signal based on said generated first digital signal (W n) and said generated second digital signal (V n). generating a first digital signal (W n) and a second digital signal (V n) based on an analog feedback signal (P t) distinct from an output (O t) of said voltage controlled oscillator and generated by said two-input analog phase locked loop (156, 306, 500) as an output of the multi-modulus divider or the loop filter, wherein the differentiator block generates a difference value for the second digital signal (V n) between a present output and a previous output from the 1/K-gain block, said difference value for the second digital signal (V n) is communicated to the two-input analog phase locked loop (156, 306, 500) as a compensated data signal (U n) for the two-input analog phase locked loop (156, 306, 500); and digitally controlling said two-input analog phase locked loop (156, 306, 500) during modulation of said signal based on said generated first digital signal (W n) and said generated second digital signal (V n).