An integrated circuit device comprising: a first processing subsystem (10; 210) comprising: a first local bus; a first processor (14; 214) connected to the first local bus (12; 212); a first set of one or more local peripherals (16; 216) connected to the first local bus (14; 214); and a first bridge unit (22; 222) connected to the first local bus (14; 214); a second processing subsystem (40; 240) comprising: a second local bus (42; 242); a second processor (44; 244) connected to the second local bus (42; 242); a second set of one or more local peripherals (46; 246) connected to the second local bus (42; 242); a second bridge unit (52; 252) connected to the second local bus (42; 242); and a local-event line, between the second bridge unit (52; 252) and a peripheral of the second set of peripherals (46; 246), for sending a local event signal from the second bridge unit (52; 252) to said peripheral; and an electrical interconnect (70; 270) between the first bridge unit (22; 222) and the second bridge unit (52; 252), wherein: the first processing subsystem (14; 214), the second processing subsystem (40; 240), and the electrical interconnect (70; 270) are integrated on a common semiconductor substrate; the first bridge unit (22; 222) comprises a task register, accessible over the first local bus (12; 212); the first bridge unit (22; 222) is configured, or is configurable, to: detect a write to the task register; and respond to the write by sending an event signal over the electrical interconnect (70; 270) to the second bridge unit (52; 252), and the second bridge unit (52; 252) is configured, or is configurable, to: receive the event signal from the first bridge unit (22; 222); send an interrupt signal to the second processor (44; 244) in response to receiving the event signal; and send a local event signal over the local-event line to said peripheral of the second set of peripherals (46; 246) in response to receiving said event signal or in response to receiving a further event signal over the electrical interconnect (70; 270). a first processing subsystem (10; 210) comprising: a first local bus; a first processor (14; 214) connected to the first local bus (12; 212); a first set of one or more local peripherals (16; 216) connected to the first local bus (14; 214); and a first bridge unit (22; 222) connected to the first local bus (14; 214); a first local bus; a first processor (14; 214) connected to the first local bus (12; 212); a first set of one or more local peripherals (16; 216) connected to the first local bus (14; 214); and a first bridge unit (22; 222) connected to the first local bus (14; 214); a second processing subsystem (40; 240) comprising: a second local bus (42; 242); a second processor (44; 244) connected to the second local bus (42; 242); a second set of one or more local peripherals (46; 246) connected to the second local bus (42; 242); a second bridge unit (52; 252) connected to the second local bus (42; 242); and a local-event line, between the second bridge unit (52; 252) and a peripheral of the second set of peripherals (46; 246), for sending a local event signal from the second bridge unit (52; 252) to said peripheral; and a second local bus (42; 242); a second processor (44; 244) connected to the second local bus (42; 242); a second set of one or more local peripherals (46; 246) connected to the second local bus (42; 242); a second bridge unit (52; 252) connected to the second local bus (42; 242); and a local-event line, between the second bridge unit (52; 252) and a peripheral of the second set of peripherals (46; 246), for sending a local event signal from the second bridge unit (52; 252) to said peripheral; and an electrical interconnect (70; 270) between the first bridge unit (22; 222) and the second bridge unit (52; 252), the first processing subsystem (14; 214), the second processing subsystem (40; 240), and the electrical interconnect (70; 270) are integrated on a common semiconductor substrate; the first bridge unit (22; 222) comprises a task register, accessible over the first local bus (12; 212); the first bridge unit (22; 222) is configured, or is configurable, to: detect a write to the task register; and respond to the write by sending an event signal over the electrical interconnect (70; 270) to the second bridge unit (52; 252), and detect a write to the task register; and respond to the write by sending an event signal over the electrical interconnect (70; 270) to the second bridge unit (52; 252), and the second bridge unit (52; 252) is configured, or is configurable, to: receive the event signal from the first bridge unit (22; 222); send an interrupt signal to the second processor (44; 244) in response to receiving the event signal; and send a local event signal over the local-event line to said peripheral of the second set of peripherals (46; 246) in response to receiving said event signal or in response to receiving a further event signal over the electrical interconnect (70; 270). receive the event signal from the first bridge unit (22; 222); send an interrupt signal to the second processor (44; 244) in response to receiving the event signal; and send a local event signal over the local-event line to said peripheral of the second set of peripherals (46; 246) in response to receiving said event signal or in response to receiving a further event signal over the electrical interconnect (70; 270).