A packet processor (1a, 1b) comprising first through N-th packet processing units (14, 17, 20) which are connected in cascade, where N represents an integer which is not less than two, the packet processor (1a, 1b) comprising: first through N-th packet detecting means (16,19, 21) configured to detect whether or not a packet exists in the first through the N-th packet processing units (14,17,20), respectively, and to output, respectively, first through N-th packet detection signals (A, B, C) indicating a result of the detection; an input-side packet buffer configured to accumulate a packet input to the packet processor, to transfer the accumulated packet to the first packet processing unit and to output an (N+1)-th packet detection signal indicating whether or not a packet is accumulated therein; a clock frequency controlling means (27, 28, 29, 32) including a clock frequency control logic table defining a relation between the first through the (N+1)-th packet detection signals (A, B, C, F) and first through N-th clock frequency control clock signals, the clock frequency controlling means being configured to reduce a frequency of first through N-th clocks supplied, respectively, to the first through the N-th packet processing units (14,17, 20) when a packet exists neither in each of the respective first through the N-th packet processing units (14,17, 20) nor in a preceding unit (13,14,17) which inputs a packet to each of the respective first through the N-th packet processing units (14,17, 20); wherein the preceding unit of each N-th packet processing unit with N>1 is the (N-1)-th packet processing unit and the preceding unit of the first packet processing unit is the input-side packet buffer; a setting information input means configured to receive information relating to a reduction ratio of the first through N-th clocks supplied, respectively, to the first through the N-th packet processing units; and a clock frequency control information setting means configured to send the received information to the clock frequency control means (27, 28, 29, 32). first through N-th packet detecting means (16,19, 21) configured to detect whether or not a packet exists in the first through the N-th packet processing units (14,17,20), respectively, and to output, respectively, first through N-th packet detection signals (A, B, C) indicating a result of the detection; an input-side packet buffer configured to accumulate a packet input to the packet processor, to transfer the accumulated packet to the first packet processing unit and to output an (N+1)-th packet detection signal indicating whether or not a packet is accumulated therein; a clock frequency controlling means (27, 28, 29, 32) including a clock frequency control logic table defining a relation between the first through the (N+1)-th packet detection signals (A, B, C, F) and first through N-th clock frequency control clock signals, the clock frequency controlling means being configured to reduce a frequency of first through N-th clocks supplied, respectively, to the first through the N-th packet processing units (14,17, 20) when a packet exists neither in each of the respective first through the N-th packet processing units (14,17, 20) nor in a preceding unit (13,14,17) which inputs a packet to each of the respective first through the N-th packet processing units (14,17, 20); wherein the preceding unit of each N-th packet processing unit with N>1 is the (N-1)-th packet processing unit and the preceding unit of the first packet processing unit is the input-side packet buffer; a setting information input means configured to receive information relating to a reduction ratio of the first through N-th clocks supplied, respectively, to the first through the N-th packet processing units; and a clock frequency control information setting means configured to send the received information to the clock frequency control means (27, 28, 29, 32).