A host computer comprising: a memory configured to store a proxy virtual machine, VM, for emulating target hardware, the target hardware having an incomplete design wherein a processor and operating system of the target hardware are known but firmware and an input/output device are unknown, the proxy VM including: an emulated Ethernet controller; a virtual processor for emulating a target processor; and emulated memory in communication with the virtual processor via a virtual memory bus, the emulated memory including at least one portion storing target code which is software to run on the emulated target hardware; and a host central processing unit, CPU, configured to execute the proxy VM to emulate the target hardware, the proxy VM, upon execution by the host CPU, configured to: execute, by the virtual processor, the target code, read-in input data, operate on the input data using the executed target code to generate output data, and write the output data over the virtual memory bus in response to execution of the target code, and update the proxy VM to omit the emulated Ethernet controller and to include a target hardware I/O device; wherein the target code is configured to interact with an emulated input/output device in the emulated target hardware through an application programming interface, API, comprises at least one functional application that interacts with at least one peripheral hardware abstraction layer, and does not interact with peripheral hardware (112,114,116,118) omitted from the incomplete design. a memory configured to store a proxy virtual machine, VM, for emulating target hardware, the target hardware having an incomplete design wherein a processor and operating system of the target hardware are known but firmware and an input/output device are unknown, the proxy VM including: an emulated Ethernet controller; a virtual processor for emulating a target processor; and emulated memory in communication with the virtual processor via a virtual memory bus, the emulated memory including at least one portion storing target code which is software to run on the emulated target hardware; and an emulated Ethernet controller; a virtual processor for emulating a target processor; and emulated memory in communication with the virtual processor via a virtual memory bus, the emulated memory including at least one portion storing target code which is software to run on the emulated target hardware; and a host central processing unit, CPU, configured to execute the proxy VM to emulate the target hardware, the proxy VM, upon execution by the host CPU, configured to: execute, by the virtual processor, the target code, read-in input data, operate on the input data using the executed target code to generate output data, and write the output data over the virtual memory bus in response to execution of the target code, and update the proxy VM to omit the emulated Ethernet controller and to include a target hardware I/O device; wherein the target code is configured to interact with an emulated input/output device in the emulated target hardware through an application programming interface, API, comprises at least one functional application that interacts with at least one peripheral hardware abstraction layer, and does not interact with peripheral hardware (112,114,116,118) omitted from the incomplete design. execute, by the virtual processor, the target code, read-in input data, operate on the input data using the executed target code to generate output data, and write the output data over the virtual memory bus in response to execution of the target code, and update the proxy VM to omit the emulated Ethernet controller and to include a target hardware I/O device; wherein the target code is configured to interact with an emulated input/output device in the emulated target hardware through an application programming interface, API, comprises at least one functional application that interacts with at least one peripheral hardware abstraction layer, and does not interact with peripheral hardware (112,114,116,118) omitted from the incomplete design.