An apparatus comprising: a decoder to decode an instruction having fields for a first packed data source operand to provide a first source data element and a second source data element, a second packed data source operand or immediate to provide a first shift value and a second shift value corresponding to the first source data element and second source data element, respectively, and a packed data destination operand to indicate a first result value and a second result value corresponding to the first source data element and second source data element, and execution circuitry to execute the decoded instruction to: shift the first source data element by an amount based on the first shift value to generate a first shifted data element; shift the second source data element by an amount based on the second shift value to generate a second shifted data element; update a saturation indicator responsive to detecting a saturation condition resulting from the shift of the first and/or second source data elements; round and/or saturate the first and second shifted data elements in accordance with a specified rounding mode and the saturation indicator, respectively, to generate the first and second result data elements; and store the first result value and the second result value in a first data element location and a second data element location in a destination register, wherein the execution circuitry is to left-shift the first and second source data elements by the amount based on the first and second shift values, respectively, the left-shift being determined as a shift direction by the instruction, and wherein the execution circuitry is to set a positive saturation flag upon detecting a first saturation condition associated with the left-shift and a negative saturation flag associated with a second saturation condition associated with the left-shift, one of the positive and negative saturation flags to be used during the round and/or saturate operations to generate positively or negatively saturated values for the first result value or the second result value. a decoder to decode an instruction having fields for a first packed data source operand to provide a first source data element and a second source data element, a second packed data source operand or immediate to provide a first shift value and a second shift value corresponding to the first source data element and second source data element, respectively, and a packed data destination operand to indicate a first result value and a second result value corresponding to the first source data element and second source data element, and execution circuitry to execute the decoded instruction to: shift the first source data element by an amount based on the first shift value to generate a first shifted data element; shift the second source data element by an amount based on the second shift value to generate a second shifted data element; update a saturation indicator responsive to detecting a saturation condition resulting from the shift of the first and/or second source data elements; round and/or saturate the first and second shifted data elements in accordance with a specified rounding mode and the saturation indicator, respectively, to generate the first and second result data elements; and store the first result value and the second result value in a first data element location and a second data element location in a destination register, shift the first source data element by an amount based on the first shift value to generate a first shifted data element; shift the second source data element by an amount based on the second shift value to generate a second shifted data element; update a saturation indicator responsive to detecting a saturation condition resulting from the shift of the first and/or second source data elements; round and/or saturate the first and second shifted data elements in accordance with a specified rounding mode and the saturation indicator, respectively, to generate the first and second result data elements; and store the first result value and the second result value in a first data element location and a second data element location in a destination register, wherein the execution circuitry is to left-shift the first and second source data elements by the amount based on the first and second shift values, respectively, the left-shift being determined as a shift direction by the instruction, and wherein the execution circuitry is to set a positive saturation flag upon detecting a first saturation condition associated with the left-shift and a negative saturation flag associated with a second saturation condition associated with the left-shift, one of the positive and negative saturation flags to be used during the round and/or saturate operations to generate positively or negatively saturated values for the first result value or the second result value.