A three-dimensional, 3D, ferroelectric memory device, comprising: a substrate; and a plurality of first ferroelectric memory cells each extending vertically above the substrate and comprising: a first ferroelectric capacitor comprising a first electrode, a second electrode, and a ferroelectric layer disposed laterally between the first electrode and the second electrode; and a first transistor electrically connected to the first ferroelectric capacitor and comprising a channel structure electrically connected to the first electrode, a gate conductor, and a gate dielectric layer disposed laterally between the channel structure and the gate conductor; characterized in that a first conductor layer is provided extending laterally and in contact with the second electrode, and the first conductor layer has a different vertical dimension from the second electrode, wherein the second electrode is disposed laterally between the first conductor layer and the ferroelectric layer, wherein each of the ferroelectric memory cells comprises a plurality of ferroelectric capacitors (204-1, 204-2) including the first ferroelectric capacitor and stacked vertically, the plurality of ferroelectric capacitors (204-1, 204-2) comprising at least one upper ferroelectric capacitor stacked vertically above a respective lower ferroelectric capacitor, each of the ferroelectric capacitors (204-1, 204-2) comprising a respective first electrode (222-1, 222-2), a respective second electrode (226-1, 226-2), and a respective ferroelectric layer (224-1, 224-2) disposed laterally between the respective first electrode (222-1, 222-2) and the respective second electrode (226-1, 226-2), and the second electrode of each lower ferroelectric capacitor and the second electrode of a respective upper ferroelectric capacitor are electrically isolated from one another. a substrate; and a plurality of first ferroelectric memory cells each extending vertically above the substrate and comprising: a first ferroelectric capacitor comprising a first electrode, a second electrode, and a ferroelectric layer disposed laterally between the first electrode and the second electrode; and a first transistor electrically connected to the first ferroelectric capacitor and comprising a channel structure electrically connected to the first electrode, a gate conductor, and a gate dielectric layer disposed laterally between the channel structure and the gate conductor; characterized in that a first conductor layer is provided extending laterally and in contact with the second electrode, and the first conductor layer has a different vertical dimension from the second electrode, wherein the second electrode is disposed laterally between the first conductor layer and the ferroelectric layer, wherein each of the ferroelectric memory cells comprises a plurality of ferroelectric capacitors (204-1, 204-2) including the first ferroelectric capacitor and stacked vertically, the plurality of ferroelectric capacitors (204-1, 204-2) comprising at least one upper ferroelectric capacitor stacked vertically above a respective lower ferroelectric capacitor, each of the ferroelectric capacitors (204-1, 204-2) comprising a respective first electrode (222-1, 222-2), a respective second electrode (226-1, 226-2), and a respective ferroelectric layer (224-1, 224-2) disposed laterally between the respective first electrode (222-1, 222-2) and the respective second electrode (226-1, 226-2), and the second electrode of each lower ferroelectric capacitor and the second electrode of a respective upper ferroelectric capacitor are electrically isolated from one another. a first ferroelectric capacitor comprising a first electrode, a second electrode, and a ferroelectric layer disposed laterally between the first electrode and the second electrode; and a first transistor electrically connected to the first ferroelectric capacitor and comprising a channel structure electrically connected to the first electrode, a gate conductor, and a gate dielectric layer disposed laterally between the channel structure and the gate conductor; characterized in that a first conductor layer is provided extending laterally and in contact with the second electrode, and the first conductor layer has a different vertical dimension from the second electrode, wherein the second electrode is disposed laterally between the first conductor layer and the ferroelectric layer, wherein each of the ferroelectric memory cells comprises a plurality of ferroelectric capacitors (204-1, 204-2) including the first ferroelectric capacitor and stacked vertically, the plurality of ferroelectric capacitors (204-1, 204-2) comprising at least one upper ferroelectric capacitor stacked vertically above a respective lower ferroelectric capacitor, each of the ferroelectric capacitors (204-1, 204-2) comprising a respective first electrode (222-1, 222-2), a respective second electrode (226-1, 226-2), and a respective ferroelectric layer (224-1, 224-2) disposed laterally between the respective first electrode (222-1, 222-2) and the respective second electrode (226-1, 226-2), and the second electrode of each lower ferroelectric capacitor and the second electrode of a respective upper ferroelectric capacitor are electrically isolated from one another.