An integrated circuit comprising: a memory array comprising a plurality of multi-level 2-terminal passive element memory cells (101, 103, 105, 107), each connected between an associated word line (102, 104) and an associated bit line (106, 108) and each having first, second, third, and fourth memory cell states corresponding respectively to first, second, third, and fourth decreasing resistance levels; means for discriminating between the four memory cell states by sensing current on a selected bit line by using at least two different combinations of reference current level and read bias voltages for the selected bit line; wherein the means for discriminating between the memory states is characterised by: means for biasing, at respective times, a selected bit line with a first read bias voltage and a second read bias voltage; means (302, 306, 308-311) for sensing, for each of the first and second read bias voltages, the current on the selected bit line relative to a respective reference current level; and means for generating a read data value for a first data bit as a function of the sensed current on the selected bit line for the first and second read bias voltages; wherein the first read bias voltage is higher than the second read bias voltage, and the first reference current level is lower or equal to the second reference current level. a memory array comprising a plurality of multi-level 2-terminal passive element memory cells (101, 103, 105, 107), each connected between an associated word line (102, 104) and an associated bit line (106, 108) and each having first, second, third, and fourth memory cell states corresponding respectively to first, second, third, and fourth decreasing resistance levels; means for discriminating between the four memory cell states by sensing current on a selected bit line by using at least two different combinations of reference current level and read bias voltages for the selected bit line; wherein the means for discriminating between the memory states is characterised by: means for biasing, at respective times, a selected bit line with a first read bias voltage and a second read bias voltage; means (302, 306, 308-311) for sensing, for each of the first and second read bias voltages, the current on the selected bit line relative to a respective reference current level; and means for generating a read data value for a first data bit as a function of the sensed current on the selected bit line for the first and second read bias voltages; wherein the first read bias voltage is higher than the second read bias voltage, and the first reference current level is lower or equal to the second reference current level. means for biasing, at respective times, a selected bit line with a first read bias voltage and a second read bias voltage; means (302, 306, 308-311) for sensing, for each of the first and second read bias voltages, the current on the selected bit line relative to a respective reference current level; and means for generating a read data value for a first data bit as a function of the sensed current on the selected bit line for the first and second read bias voltages; wherein the first read bias voltage is higher than the second read bias voltage, and the first reference current level is lower or equal to the second reference current level.